[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-prph.h

/******************************************************************************
 *
 * This file is provided under a dual BSD/GPLv2 license.  When using or
 * redistributing this file, you may do so under either license.
 *
 * GPL LICENSE SUMMARY
 *
 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
 * USA
 *
 * The full GNU General Public License is included in this distribution
 * in the file called COPYING.
 *
 * Contact Information:
 *  Intel Linux Wireless <ilw@linux.intel.com>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *
 * BSD LICENSE
 *
 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name Intel Corporation nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *****************************************************************************/

#ifndef	__iwl_prph_h__
#define __iwl_prph_h__

/*
 * Registers in this file are internal, not PCI bus memory mapped.
 * Driver accesses these via HBUS_TARG_PRPH_* registers.
 */
#define PRPH_BASE	(0x00000)
#define PRPH_END	(0xFFFFF)

/* APMG (power management) constants */
#define APMG_BASE			(PRPH_BASE + 0x3000)
#define APMG_CLK_CTRL_REG		(APMG_BASE + 0x0000)
#define APMG_CLK_EN_REG			(APMG_BASE + 0x0004)
#define APMG_CLK_DIS_REG		(APMG_BASE + 0x0008)
#define APMG_PS_CTRL_REG		(APMG_BASE + 0x000c)
#define APMG_PCIDEV_STT_REG		(APMG_BASE + 0x0010)
#define APMG_RFKILL_REG			(APMG_BASE + 0x0014)
#define APMG_RTC_INT_STT_REG		(APMG_BASE + 0x001c)
#define APMG_RTC_INT_MSK_REG		(APMG_BASE + 0x0020)
#define APMG_DIGITAL_SVR_REG		(APMG_BASE + 0x0058)
#define APMG_ANALOG_SVR_REG		(APMG_BASE + 0x006C)

#define APMS_CLK_VAL_MRB_FUNC_MODE	(0x00000001)
#define APMG_CLK_VAL_DMA_CLK_RQT	(0x00000200)
#define APMG_CLK_VAL_BSM_CLK_RQT	(0x00000800)

#define APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS	(0x00400000)
#define APMG_PS_CTRL_VAL_RESET_REQ		(0x04000000)
#define APMG_PS_CTRL_MSK_PWR_SRC		(0x03000000)
#define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN		(0x00000000)
#define APMG_PS_CTRL_VAL_PWR_SRC_VAUX		(0x02000000)
#define APMG_SVR_VOLTAGE_CONFIG_BIT_MSK	(0x000001E0) /* bit 8:5 */
#define APMG_SVR_DIGITAL_VOLTAGE_1_32		(0x00000060)

#define APMG_PCIDEV_STT_VAL_PERSIST_DIS	(0x00000200)
#define APMG_PCIDEV_STT_VAL_L1_ACT_DIS	(0x00000800)

#define APMG_RTC_INT_STT_RFKILL		(0x10000000)

/* Device system time */
#define DEVICE_SYSTEM_TIME_REG 0xA0206C

/* Device NMI register */
#define DEVICE_SET_NMI_REG 0x00a01c30
#define DEVICE_SET_NMI_VAL 0x1
#define DEVICE_SET_NMI_8000B_REG 0x00a01c24
#define DEVICE_SET_NMI_8000B_VAL 0x1000000

/* Shared registers (0x0..0x3ff, via target indirect or periphery */
#define SHR_BASE	0x00a10000

/* Shared GP1 register */
#define SHR_APMG_GP1_REG		0x01dc
#define SHR_APMG_GP1_REG_PRPH		(SHR_BASE + SHR_APMG_GP1_REG)
#define SHR_APMG_GP1_WF_XTAL_LP_EN	0x00000004
#define SHR_APMG_GP1_CHICKEN_BIT_SELECT	0x80000000

/* Shared DL_CFG register */
#define SHR_APMG_DL_CFG_REG			0x01c4
#define SHR_APMG_DL_CFG_REG_PRPH		(SHR_BASE + SHR_APMG_DL_CFG_REG)
#define SHR_APMG_DL_CFG_RTCS_CLK_SELECTOR_MSK	0x000000c0
#define SHR_APMG_DL_CFG_RTCS_CLK_INTERNAL_XTAL	0x00000080
#define SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP	0x00000100

/* Shared APMG_XTAL_CFG register */
#define SHR_APMG_XTAL_CFG_REG		0x1c0
#define SHR_APMG_XTAL_CFG_XTAL_ON_REQ	0x80000000

/*
 * Device reset for family 8000
 * write to bit 24 in order to reset the CPU
*/
#define RELEASE_CPU_RESET		(0x300C)
#define RELEASE_CPU_RESET_BIT		BIT(24)

/*****************************************************************************
 *                        7000/3000 series SHR DTS addresses                 *
 *****************************************************************************/

#define SHR_MISC_WFM_DTS_EN	(0x00a10024)
#define DTSC_CFG_MODE		(0x00a10604)
#define DTSC_VREF_AVG		(0x00a10648)
#define DTSC_VREF5_AVG		(0x00a1064c)
#define DTSC_CFG_MODE_PERIODIC	(0x2)
#define DTSC_PTAT_AVG		(0x00a10650)


/**
 * Tx Scheduler
 *
 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs
 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in
 * host DRAM.  It steers each frame's Tx command (which contains the frame
 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the
 * device.  A queue maps to only one (selectable by driver) Tx DMA channel,
 * but one DMA channel may take input from several queues.
 *
 * Tx DMA FIFOs have dedicated purposes.
 *
 * For 5000 series and up, they are used differently
 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c):
 *
 * 0 -- EDCA BK (background) frames, lowest priority
 * 1 -- EDCA BE (best effort) frames, normal priority
 * 2 -- EDCA VI (video) frames, higher priority
 * 3 -- EDCA VO (voice) and management frames, highest priority
 * 4 -- unused
 * 5 -- unused
 * 6 -- unused
 * 7 -- Commands
 *
 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.
 * In addition, driver can map the remaining queues to Tx DMA/FIFO
 * channels 0-3 to support 11n aggregation via EDCA DMA channels.
 *
 * The driver sets up each queue to work in one of two modes:
 *
 * 1)  Scheduler-Ack, in which the scheduler automatically supports a
 *     block-ack (BA) window of up to 64 TFDs.  In this mode, each queue
 *     contains TFDs for a unique combination of Recipient Address (RA)
 *     and Traffic Identifier (TID), that is, traffic of a given
 *     Quality-Of-Service (QOS) priority, destined for a single station.
 *
 *     In scheduler-ack mode, the scheduler keeps track of the Tx status of
 *     each frame within the BA window, including whether it's been transmitted,
 *     and whether it's been acknowledged by the receiving station.  The device
 *     automatically processes block-acks received from the receiving STA,
 *     and reschedules un-acked frames to be retransmitted (successful
 *     Tx completion may end up being out-of-order).
 *
 *     The driver must maintain the queue's Byte Count table in host DRAM
 *     for this mode.
 *     This mode does not support fragmentation.
 *
 * 2)  FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order.
 *     The device may automatically retry Tx, but will retry only one frame
 *     at a time, until receiving ACK from receiving station, or reaching
 *     retry limit and giving up.
 *
 *     The command queue (#4/#9) must use this mode!
 *     This mode does not require use of the Byte Count table in host DRAM.
 *
 * Driver controls scheduler operation via 3 means:
 * 1)  Scheduler registers
 * 2)  Shared scheduler data base in internal SRAM
 * 3)  Shared data in host DRAM
 *
 * Initialization:
 *
 * When loading, driver should allocate memory for:
 * 1)  16 TFD circular buffers, each with space for (typically) 256 TFDs.
 * 2)  16 Byte Count circular buffers in 16 KBytes contiguous memory
 *     (1024 bytes for each queue).
 *
 * After receiving "Alive" response from uCode, driver must initialize
 * the scheduler (especially for queue #4/#9, the command queue, otherwise
 * the driver can't issue commands!):
 */
#define SCD_MEM_LOWER_BOUND		(0x0000)

/**
 * Max Tx window size is the max number of contiguous TFDs that the scheduler
 * can keep track of at one time when creating block-ack chains of frames.
 * Note that "64" matches the number of ack bits in a block-ack packet.
 */
#define SCD_WIN_SIZE				64
#define SCD_FRAME_LIMIT				64

#define SCD_TXFIFO_POS_TID			(0)
#define SCD_TXFIFO_POS_RA			(4)
#define SCD_QUEUE_RA_TID_MAP_RATID_MSK	(0x01FF)

/* agn SCD */
#define SCD_QUEUE_STTS_REG_POS_TXF	(0)
#define SCD_QUEUE_STTS_REG_POS_ACTIVE	(3)
#define SCD_QUEUE_STTS_REG_POS_WSL	(4)
#define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19)
#define SCD_QUEUE_STTS_REG_MSK		(0x017F0000)

#define SCD_QUEUE_CTX_REG1_CREDIT_POS		(8)
#define SCD_QUEUE_CTX_REG1_CREDIT_MSK		(0x00FFFF00)
#define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS	(24)
#define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK	(0xFF000000)
#define SCD_QUEUE_CTX_REG2_WIN_SIZE_POS		(0)
#define SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK		(0x0000007F)
#define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS	(16)
#define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK	(0x007F0000)

/* Context Data */
#define SCD_CONTEXT_MEM_LOWER_BOUND	(SCD_MEM_LOWER_BOUND + 0x600)
#define SCD_CONTEXT_MEM_UPPER_BOUND	(SCD_MEM_LOWER_BOUND + 0x6A0)

/* Tx status */
#define SCD_TX_STTS_MEM_LOWER_BOUND	(SCD_MEM_LOWER_BOUND + 0x6A0)
#define SCD_TX_STTS_MEM_UPPER_BOUND	(SCD_MEM_LOWER_BOUND + 0x7E0)

/* Translation Data */
#define SCD_TRANS_TBL_MEM_LOWER_BOUND	(SCD_MEM_LOWER_BOUND + 0x7E0)
#define SCD_TRANS_TBL_MEM_UPPER_BOUND	(SCD_MEM_LOWER_BOUND + 0x808)

#define SCD_CONTEXT_QUEUE_OFFSET(x)\
	(SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8))

#define SCD_TX_STTS_QUEUE_OFFSET(x)\
	(SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16))

#define SCD_TRANS_TBL_OFFSET_QUEUE(x) \
	((SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc)

#define SCD_BASE			(PRPH_BASE + 0xa02c00)

#define SCD_SRAM_BASE_ADDR	(SCD_BASE + 0x0)
#define SCD_DRAM_BASE_ADDR	(SCD_BASE + 0x8)
#define SCD_AIT			(SCD_BASE + 0x0c)
#define SCD_TXFACT		(SCD_BASE + 0x10)
#define SCD_ACTIVE		(SCD_BASE + 0x14)
#define SCD_QUEUECHAIN_SEL	(SCD_BASE + 0xe8)
#define SCD_CHAINEXT_EN		(SCD_BASE + 0x244)
#define SCD_AGGR_SEL		(SCD_BASE + 0x248)
#define SCD_INTERRUPT_MASK	(SCD_BASE + 0x108)

static inline unsigned int SCD_QUEUE_WRPTR(unsigned int chnl)
{
	if (chnl < 20)
		return SCD_BASE + 0x18 + chnl * 4;
	WARN_ON_ONCE(chnl >= 32);
	return SCD_BASE + 0x284 + (chnl - 20) * 4;
}

static inline unsigned int SCD_QUEUE_RDPTR(unsigned int chnl)
{
	if (chnl < 20)
		return SCD_BASE + 0x68 + chnl * 4;
	WARN_ON_ONCE(chnl >= 32);
	return SCD_BASE + 0x2B4 + (chnl - 20) * 4;
}

static inline unsigned int SCD_QUEUE_STATUS_BITS(unsigned int chnl)
{
	if (chnl < 20)
		return SCD_BASE + 0x10c + chnl * 4;
	WARN_ON_ONCE(chnl >= 32);
	return SCD_BASE + 0x384 + (chnl - 20) * 4;
}

/*********************** END TX SCHEDULER *************************************/

/* Oscillator clock */
#define OSC_CLK				(0xa04068)
#define OSC_CLK_FORCE_CONTROL		(0x8)

/* SECURE boot registers */
#define LMPM_SECURE_BOOT_CONFIG_ADDR	(0x100)
enum secure_boot_config_reg {
	LMPM_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP	= 0x00000001,
	LMPM_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ	= 0x00000002,
};

#define LMPM_SECURE_BOOT_CPU1_STATUS_ADDR	(0x1E30)
#define LMPM_SECURE_BOOT_CPU2_STATUS_ADDR	(0x1E34)
enum secure_boot_status_reg {
	LMPM_SECURE_BOOT_CPU_STATUS_VERF_STATUS		= 0x00000001,
	LMPM_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED	= 0x00000002,
	LMPM_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS	= 0x00000004,
	LMPM_SECURE_BOOT_CPU_STATUS_VERF_FAIL		= 0x00000008,
	LMPM_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL	= 0x00000010,
	LMPM_SECURE_BOOT_STATUS_SUCCESS			= 0x00000003,
};

#define CSR_UCODE_LOAD_STATUS_ADDR	(0x1E70)
enum secure_load_status_reg {
	LMPM_CPU_UCODE_LOADING_STARTED			= 0x00000001,
	LMPM_CPU_HDRS_LOADING_COMPLETED			= 0x00000003,
	LMPM_CPU_UCODE_LOADING_COMPLETED		= 0x00000007,
	LMPM_CPU_STATUS_NUM_OF_LAST_COMPLETED		= 0x000000F8,
	LMPM_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK	= 0x0000FF00,
};

#define LMPM_SECURE_INSPECTOR_CODE_ADDR	(0x1E38)
#define LMPM_SECURE_INSPECTOR_DATA_ADDR	(0x1E3C)
#define LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR	(0x1E78)
#define LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR	(0x1E7C)

#define LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE	(0x400000)
#define LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE	(0x402000)
#define LMPM_SECURE_CPU1_HDR_MEM_SPACE		(0x420000)
#define LMPM_SECURE_CPU2_HDR_MEM_SPACE		(0x420400)

#define LMPM_SECURE_TIME_OUT	(100)

/* Rx FIFO */
#define RXF_SIZE_ADDR			(0xa00c88)
#define RXF_SIZE_BYTE_CND_POS		(7)
#define RXF_SIZE_BYTE_CNT_MSK		(0x3ff << RXF_SIZE_BYTE_CND_POS)

#define RXF_LD_FENCE_OFFSET_ADDR	(0xa00c10)
#define RXF_FIFO_RD_FENCE_ADDR		(0xa00c0c)

/* FW monitor */
#define MON_BUFF_BASE_ADDR		(0xa03c3c)
#define MON_BUFF_END_ADDR		(0xa03c40)
#define MON_BUFF_WRPTR			(0xa03c44)
#define MON_BUFF_CYCLE_CNT		(0xa03c48)

#endif				/* __iwl_prph_h__ */
Commit	Line	Data
b481de9c ZY	1	/******************************************************************************
	2	*
	3	* This file is provided under a dual BSD/GPLv2 license. When using or
	4	* redistributing this file, you may do so under either license.
	5	*
	6	* GPL LICENSE SUMMARY
	7	*
51368bf7	8	* Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
b481de9c ZY	9	*
b481de9c ZY	10	* This program is free software; you can redistribute it and/or modify
01ebd063	11	* it under the terms of version 2 of the GNU General Public License as
b481de9c ZY	12	* published by the Free Software Foundation.
	13	*
	14	* This program is distributed in the hope that it will be useful, but
	15	* WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	17	* General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
	22	* USA
	23	*
	24	* The full GNU General Public License is included in this distribution
410dc5aa	25	* in the file called COPYING.
b481de9c ZY	26	*
b481de9c ZY	27	* Contact Information:
759ef89f	28	* Intel Linux Wireless <ilw@linux.intel.com>
b481de9c ZY	29	* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	30	*
	31	* BSD LICENSE
	32	*
51368bf7	33	* Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
b481de9c ZY	34	* All rights reserved.
	35	*
	36	* Redistribution and use in source and binary forms, with or without
	37	* modification, are permitted provided that the following conditions
	38	* are met:
	39	*
	40	* * Redistributions of source code must retain the above copyright
	41	* notice, this list of conditions and the following disclaimer.
	42	* * Redistributions in binary form must reproduce the above copyright
	43	* notice, this list of conditions and the following disclaimer in
	44	* the documentation and/or other materials provided with the
	45	* distribution.
	46	* * Neither the name Intel Corporation nor the names of its
	47	* contributors may be used to endorse or promote products derived
	48	* from this software without specific prior written permission.
	49	*
	50	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	51	* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	52	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
	53	* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
	54	* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
	55	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
	56	* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	57	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	58	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	59	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	60	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	61	*****************************************************************************/
	62
	63	#ifndef __iwl_prph_h__
	64	#define __iwl_prph_h__
	65
e3851447 BC	66	/*
	67	* Registers in this file are internal, not PCI bus memory mapped.
	68	* Driver accesses these via HBUS_TARG_PRPH_* registers.
	69	*/
b481de9c ZY	70	#define PRPH_BASE (0x00000)
	71	#define PRPH_END (0xFFFFF)
	72
	73	/* APMG (power management) constants */
	74	#define APMG_BASE (PRPH_BASE + 0x3000)
	75	#define APMG_CLK_CTRL_REG (APMG_BASE + 0x0000)
	76	#define APMG_CLK_EN_REG (APMG_BASE + 0x0004)
	77	#define APMG_CLK_DIS_REG (APMG_BASE + 0x0008)
	78	#define APMG_PS_CTRL_REG (APMG_BASE + 0x000c)
	79	#define APMG_PCIDEV_STT_REG (APMG_BASE + 0x0010)
	80	#define APMG_RFKILL_REG (APMG_BASE + 0x0014)
	81	#define APMG_RTC_INT_STT_REG (APMG_BASE + 0x001c)
	82	#define APMG_RTC_INT_MSK_REG (APMG_BASE + 0x0020)
02c06e4a WYG	83	#define APMG_DIGITAL_SVR_REG (APMG_BASE + 0x0058)
02c06e4a WYG	84	#define APMG_ANALOG_SVR_REG (APMG_BASE + 0x006C)
b481de9c	85
50619ac9	86	#define APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001)
b481de9c ZY	87	#define APMG_CLK_VAL_DMA_CLK_RQT (0x00000200)
	88	#define APMG_CLK_VAL_BSM_CLK_RQT (0x00000800)
	89
4c43e0d0 TW	90	#define APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000)
	91	#define APMG_PS_CTRL_VAL_RESET_REQ (0x04000000)
	92	#define APMG_PS_CTRL_MSK_PWR_SRC (0x03000000)
	93	#define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000)
4c43e0d0	94	#define APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000)
02c06e4a WYG	95	#define APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */
02c06e4a WYG	96	#define APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060)
b481de9c	97
a812cba9 AB	98	#define APMG_PCIDEV_STT_VAL_PERSIST_DIS (0x00000200)
a812cba9 AB	99	#define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)
b481de9c	100
889b1696 EG	101	#define APMG_RTC_INT_STT_RFKILL (0x10000000)
889b1696 EG	102
99cd4714 JB	103	/* Device system time */
	104	#define DEVICE_SYSTEM_TIME_REG 0xA0206C
	105
119663c3 AB	106	/* Device NMI register */
119663c3 AB	107	#define DEVICE_SET_NMI_REG 0x00a01c30
4c9706dc LK	108	#define DEVICE_SET_NMI_VAL 0x1
	109	#define DEVICE_SET_NMI_8000B_REG 0x00a01c24
	110	#define DEVICE_SET_NMI_8000B_VAL 0x1000000
119663c3	111
a812cba9 AB	112	/* Shared registers (0x0..0x3ff, via target indirect or periphery */
	113	#define SHR_BASE 0x00a10000
	114
	115	/* Shared GP1 register */
	116	#define SHR_APMG_GP1_REG 0x01dc
	117	#define SHR_APMG_GP1_REG_PRPH (SHR_BASE + SHR_APMG_GP1_REG)
	118	#define SHR_APMG_GP1_WF_XTAL_LP_EN 0x00000004
	119	#define SHR_APMG_GP1_CHICKEN_BIT_SELECT 0x80000000
	120
	121	/* Shared DL_CFG register */
	122	#define SHR_APMG_DL_CFG_REG 0x01c4
	123	#define SHR_APMG_DL_CFG_REG_PRPH (SHR_BASE + SHR_APMG_DL_CFG_REG)
	124	#define SHR_APMG_DL_CFG_RTCS_CLK_SELECTOR_MSK 0x000000c0
	125	#define SHR_APMG_DL_CFG_RTCS_CLK_INTERNAL_XTAL 0x00000080
	126	#define SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP 0x00000100
	127
	128	/* Shared APMG_XTAL_CFG register */
	129	#define SHR_APMG_XTAL_CFG_REG 0x1c0
	130	#define SHR_APMG_XTAL_CFG_XTAL_ON_REQ 0x80000000
	131
e12ba844 EH	132	/*
	133	* Device reset for family 8000
	134	* write to bit 24 in order to reset the CPU
	135	*/
	136	#define RELEASE_CPU_RESET (0x300C)
	137	#define RELEASE_CPU_RESET_BIT BIT(24)
	138
9ee718aa EL	139	/*****************************************************************************
	140	* 7000/3000 series SHR DTS addresses *
	141	*****************************************************************************/
	142
	143	#define SHR_MISC_WFM_DTS_EN (0x00a10024)
	144	#define DTSC_CFG_MODE (0x00a10604)
	145	#define DTSC_VREF_AVG (0x00a10648)
	146	#define DTSC_VREF5_AVG (0x00a1064c)
	147	#define DTSC_CFG_MODE_PERIODIC (0x2)
	148	#define DTSC_PTAT_AVG (0x00a10650)
	149
	150
038669e4 EG	151	/**
	152	* Tx Scheduler
	153	*
a96a27f9	154	* The Tx Scheduler selects the next frame to be transmitted, choosing TFDs
038669e4 EG	155	* (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in
	156	* host DRAM. It steers each frame's Tx command (which contains the frame
	157	* data) into one of up to 7 prioritized Tx DMA FIFO channels within the
	158	* device. A queue maps to only one (selectable by driver) Tx DMA channel,
	159	* but one DMA channel may take input from several queues.
	160	*
8ff84a2c	161	* Tx DMA FIFOs have dedicated purposes.
038669e4	162	*
edc1a3a0	163	* For 5000 series and up, they are used differently
68198865 JB	164	* (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c):
	165	*
	166	* 0 -- EDCA BK (background) frames, lowest priority
	167	* 1 -- EDCA BE (best effort) frames, normal priority
	168	* 2 -- EDCA VI (video) frames, higher priority
	169	* 3 -- EDCA VO (voice) and management frames, highest priority
edc1a3a0 JB	170	* 4 -- unused
	171	* 5 -- unused
	172	* 6 -- unused
68198865 JB	173	* 7 -- Commands
68198865 JB	174	*
038669e4	175	* Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.
68198865 JB	176	* In addition, driver can map the remaining queues to Tx DMA/FIFO
68198865 JB	177	* channels 0-3 to support 11n aggregation via EDCA DMA channels.
038669e4 EG	178	*
	179	* The driver sets up each queue to work in one of two modes:
	180	*
	181	* 1) Scheduler-Ack, in which the scheduler automatically supports a
	182	* block-ack (BA) window of up to 64 TFDs. In this mode, each queue
	183	* contains TFDs for a unique combination of Recipient Address (RA)
	184	* and Traffic Identifier (TID), that is, traffic of a given
	185	* Quality-Of-Service (QOS) priority, destined for a single station.
	186	*
	187	* In scheduler-ack mode, the scheduler keeps track of the Tx status of
	188	* each frame within the BA window, including whether it's been transmitted,
	189	* and whether it's been acknowledged by the receiving station. The device
	190	* automatically processes block-acks received from the receiving STA,
	191	* and reschedules un-acked frames to be retransmitted (successful
	192	* Tx completion may end up being out-of-order).
	193	*
	194	* The driver must maintain the queue's Byte Count table in host DRAM
8ff84a2c	195	* for this mode.
038669e4 EG	196	* This mode does not support fragmentation.
	197	*
	198	* 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order.
	199	* The device may automatically retry Tx, but will retry only one frame
	200	* at a time, until receiving ACK from receiving station, or reaching
	201	* retry limit and giving up.
	202	*
13bb9483	203	* The command queue (#4/#9) must use this mode!
038669e4 EG	204	* This mode does not require use of the Byte Count table in host DRAM.
	205	*
	206	* Driver controls scheduler operation via 3 means:
	207	* 1) Scheduler registers
8ff84a2c	208	* 2) Shared scheduler data base in internal SRAM
038669e4 EG	209	* 3) Shared data in host DRAM
	210	*
	211	* Initialization:
	212	*
	213	* When loading, driver should allocate memory for:
	214	* 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs.
	215	* 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory
	216	* (1024 bytes for each queue).
	217	*
	218	* After receiving "Alive" response from uCode, driver must initialize
13bb9483	219	* the scheduler (especially for queue #4/#9, the command queue, otherwise
038669e4 EG	220	* the driver can't issue commands!):
038669e4 EG	221	*/
f86af7ba	222	#define SCD_MEM_LOWER_BOUND (0x0000)
038669e4 EG	223
	224	/**
	225	* Max Tx window size is the max number of contiguous TFDs that the scheduler
	226	* can keep track of at one time when creating block-ack chains of frames.
	227	* Note that "64" matches the number of ack bits in a block-ack packet.
038669e4 EG	228	*/
	229	#define SCD_WIN_SIZE 64
	230	#define SCD_FRAME_LIMIT 64
	231
b3c2ce13 EG	232	#define SCD_TXFIFO_POS_TID (0)
	233	#define SCD_TXFIFO_POS_RA (4)
	234	#define SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)
038669e4	235
f4388adc	236	/* agn SCD */
b3c2ce13 EG	237	#define SCD_QUEUE_STTS_REG_POS_TXF (0)
	238	#define SCD_QUEUE_STTS_REG_POS_ACTIVE (3)
	239	#define SCD_QUEUE_STTS_REG_POS_WSL (4)
	240	#define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19)
cde5b487	241	#define SCD_QUEUE_STTS_REG_MSK (0x017F0000)
b3c2ce13 EG	242
	243	#define SCD_QUEUE_CTX_REG1_CREDIT_POS (8)
	244	#define SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00)
	245	#define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24)
	246	#define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000)
	247	#define SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0)
	248	#define SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F)
	249	#define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)
	250	#define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)
f4388adc	251
f86af7ba	252	/* Context Data */
b3c2ce13 EG	253	#define SCD_CONTEXT_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x600)
b3c2ce13 EG	254	#define SCD_CONTEXT_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0)
f86af7ba WYG	255
f86af7ba WYG	256	/* Tx status */
b3c2ce13 EG	257	#define SCD_TX_STTS_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0)
b3c2ce13 EG	258	#define SCD_TX_STTS_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0)
f86af7ba WYG	259
f86af7ba WYG	260	/* Translation Data */
b3c2ce13 EG	261	#define SCD_TRANS_TBL_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0)
b3c2ce13 EG	262	#define SCD_TRANS_TBL_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x808)
f4388adc	263
b3c2ce13 EG	264	#define SCD_CONTEXT_QUEUE_OFFSET(x)\
b3c2ce13 EG	265	(SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8))
f4388adc	266
986ea6c9 EG	267	#define SCD_TX_STTS_QUEUE_OFFSET(x)\
	268	(SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16))
	269
b3c2ce13 EG	270	#define SCD_TRANS_TBL_OFFSET_QUEUE(x) \
b3c2ce13 EG	271	((SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc)
f4388adc	272
b3c2ce13 EG	273	#define SCD_BASE (PRPH_BASE + 0xa02c00)
	274
	275	#define SCD_SRAM_BASE_ADDR (SCD_BASE + 0x0)
	276	#define SCD_DRAM_BASE_ADDR (SCD_BASE + 0x8)
	277	#define SCD_AIT (SCD_BASE + 0x0c)
	278	#define SCD_TXFACT (SCD_BASE + 0x10)
	279	#define SCD_ACTIVE (SCD_BASE + 0x14)
b3c2ce13	280	#define SCD_QUEUECHAIN_SEL (SCD_BASE + 0xe8)
d012d04e	281	#define SCD_CHAINEXT_EN (SCD_BASE + 0x244)
b3c2ce13 EG	282	#define SCD_AGGR_SEL (SCD_BASE + 0x248)
b3c2ce13 EG	283	#define SCD_INTERRUPT_MASK (SCD_BASE + 0x108)
5ef4acd5 JB	284
	285	static inline unsigned int SCD_QUEUE_WRPTR(unsigned int chnl)
	286	{
	287	if (chnl < 20)
	288	return SCD_BASE + 0x18 + chnl * 4;
	289	WARN_ON_ONCE(chnl >= 32);
	290	return SCD_BASE + 0x284 + (chnl - 20) * 4;
	291	}
	292
	293	static inline unsigned int SCD_QUEUE_RDPTR(unsigned int chnl)
	294	{
	295	if (chnl < 20)
	296	return SCD_BASE + 0x68 + chnl * 4;
	297	WARN_ON_ONCE(chnl >= 32);
	298	return SCD_BASE + 0x2B4 + (chnl - 20) * 4;
	299	}
	300
	301	static inline unsigned int SCD_QUEUE_STATUS_BITS(unsigned int chnl)
	302	{
	303	if (chnl < 20)
	304	return SCD_BASE + 0x10c + chnl * 4;
	305	WARN_ON_ONCE(chnl >= 32);
	306	return SCD_BASE + 0x384 + (chnl - 20) * 4;
	307	}
b559e66c	308
038669e4 EG	309	/********************* END TX SCHEDULER ***********************************/
038669e4 EG	310
2d93aee1 EG	311	/* Oscillator clock */
	312	#define OSC_CLK (0xa04068)
	313	#define OSC_CLK_FORCE_CONTROL (0x8)
	314
189fa2fa EH	315	/* SECURE boot registers */
	316	#define LMPM_SECURE_BOOT_CONFIG_ADDR (0x100)
	317	enum secure_boot_config_reg {
	318	LMPM_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001,
	319	LMPM_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002,
	320	};
	321
	322	#define LMPM_SECURE_BOOT_CPU1_STATUS_ADDR (0x1E30)
	323	#define LMPM_SECURE_BOOT_CPU2_STATUS_ADDR (0x1E34)
	324	enum secure_boot_status_reg {
	325	LMPM_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000001,
	326	LMPM_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002,
	327	LMPM_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004,
	328	LMPM_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008,
	329	LMPM_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010,
	330	LMPM_SECURE_BOOT_STATUS_SUCCESS = 0x00000003,
	331	};
	332
	333	#define CSR_UCODE_LOAD_STATUS_ADDR (0x1E70)
	334	enum secure_load_status_reg {
	335	LMPM_CPU_UCODE_LOADING_STARTED = 0x00000001,
	336	LMPM_CPU_HDRS_LOADING_COMPLETED = 0x00000003,
	337	LMPM_CPU_UCODE_LOADING_COMPLETED = 0x00000007,
	338	LMPM_CPU_STATUS_NUM_OF_LAST_COMPLETED = 0x000000F8,
	339	LMPM_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK = 0x0000FF00,
	340	};
	341
	342	#define LMPM_SECURE_INSPECTOR_CODE_ADDR (0x1E38)
	343	#define LMPM_SECURE_INSPECTOR_DATA_ADDR (0x1E3C)
	344	#define LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR (0x1E78)
	345	#define LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR (0x1E7C)
	346
	347	#define LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE (0x400000)
	348	#define LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE (0x402000)
	349	#define LMPM_SECURE_CPU1_HDR_MEM_SPACE (0x420000)
	350	#define LMPM_SECURE_CPU2_HDR_MEM_SPACE (0x420400)
	351
	352	#define LMPM_SECURE_TIME_OUT (100)
	353
7b445f35 EG	354	/* Rx FIFO */
	355	#define RXF_SIZE_ADDR (0xa00c88)
	356	#define RXF_SIZE_BYTE_CND_POS (7)
	357	#define RXF_SIZE_BYTE_CNT_MSK (0x3ff << RXF_SIZE_BYTE_CND_POS)
	358
	359	#define RXF_LD_FENCE_OFFSET_ADDR (0xa00c10)
	360	#define RXF_FIFO_RD_FENCE_ADDR (0xa00c0c)
	361
c2d20201 EG	362	/* FW monitor */
	363	#define MON_BUFF_BASE_ADDR (0xa03c3c)
	364	#define MON_BUFF_END_ADDR (0xa03c40)
	365	#define MON_BUFF_WRPTR (0xa03c44)
	366	#define MON_BUFF_CYCLE_CNT (0xa03c48)
	367
b481de9c	368	#endif /* __iwl_prph_h__ */