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1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
8 | * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
01ebd063 | 11 | * it under the terms of version 2 of the GNU General Public License as |
b481de9c ZY |
12 | * published by the Free Software Foundation. |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
22 | * USA | |
23 | * | |
24 | * The full GNU General Public License is included in this distribution | |
25 | * in the file called LICENSE.GPL. | |
26 | * | |
27 | * Contact Information: | |
28 | * James P. Ketrenos <ipw2100-admin@linux.intel.com> | |
29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
30 | * | |
31 | * BSD LICENSE | |
32 | * | |
33 | * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved. | |
34 | * All rights reserved. | |
35 | * | |
36 | * Redistribution and use in source and binary forms, with or without | |
37 | * modification, are permitted provided that the following conditions | |
38 | * are met: | |
39 | * | |
40 | * * Redistributions of source code must retain the above copyright | |
41 | * notice, this list of conditions and the following disclaimer. | |
42 | * * Redistributions in binary form must reproduce the above copyright | |
43 | * notice, this list of conditions and the following disclaimer in | |
44 | * the documentation and/or other materials provided with the | |
45 | * distribution. | |
46 | * * Neither the name Intel Corporation nor the names of its | |
47 | * contributors may be used to endorse or promote products derived | |
48 | * from this software without specific prior written permission. | |
49 | * | |
50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
61 | *****************************************************************************/ | |
62 | ||
63 | #ifndef __iwl_prph_h__ | |
64 | #define __iwl_prph_h__ | |
65 | ||
66 | ||
67 | #define PRPH_BASE (0x00000) | |
68 | #define PRPH_END (0xFFFFF) | |
69 | ||
70 | /* APMG (power management) constants */ | |
71 | #define APMG_BASE (PRPH_BASE + 0x3000) | |
72 | #define APMG_CLK_CTRL_REG (APMG_BASE + 0x0000) | |
73 | #define APMG_CLK_EN_REG (APMG_BASE + 0x0004) | |
74 | #define APMG_CLK_DIS_REG (APMG_BASE + 0x0008) | |
75 | #define APMG_PS_CTRL_REG (APMG_BASE + 0x000c) | |
76 | #define APMG_PCIDEV_STT_REG (APMG_BASE + 0x0010) | |
77 | #define APMG_RFKILL_REG (APMG_BASE + 0x0014) | |
78 | #define APMG_RTC_INT_STT_REG (APMG_BASE + 0x001c) | |
79 | #define APMG_RTC_INT_MSK_REG (APMG_BASE + 0x0020) | |
80 | ||
81 | #define APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) | |
82 | #define APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) | |
83 | ||
84 | #define APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) | |
85 | ||
86 | #define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) | |
87 | ||
88 | #define APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) | |
89 | #define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) | |
90 | #define APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x01000000) | |
91 | ||
92 | ||
93 | /** | |
94 | * BSM (Bootstrap State Machine) | |
95 | * | |
96 | * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program | |
97 | * in special SRAM that does not power down when the embedded control | |
98 | * processor is sleeping (e.g. for periodic power-saving shutdowns of radio). | |
99 | * | |
100 | * When powering back up after sleeps (or during initial uCode load), the BSM | |
101 | * internally loads the short bootstrap program from the special SRAM into the | |
102 | * embedded processor's instruction SRAM, and starts the processor so it runs | |
103 | * the bootstrap program. | |
104 | * | |
105 | * This bootstrap program loads (via PCI busmaster DMA) instructions and data | |
106 | * images for a uCode program from host DRAM locations. The host driver | |
107 | * indicates DRAM locations and sizes for instruction and data images via the | |
108 | * four BSM_DRAM_* registers. Once the bootstrap program loads the new program, | |
109 | * the new program starts automatically. | |
110 | * | |
111 | * The uCode used for open-source drivers includes two programs: | |
112 | * | |
113 | * 1) Initialization -- performs hardware calibration and sets up some | |
114 | * internal data, then notifies host via "initialize alive" notification | |
115 | * (struct iwl_init_alive_resp) that it has completed all of its work. | |
116 | * After signal from host, it then loads and starts the runtime program. | |
117 | * The initialization program must be used when initially setting up the | |
118 | * NIC after loading the driver. | |
119 | * | |
120 | * 2) Runtime/Protocol -- performs all normal runtime operations. This | |
121 | * notifies host via "alive" notification (struct iwl_alive_resp) that it | |
122 | * is ready to be used. | |
123 | * | |
124 | * When initializing the NIC, the host driver does the following procedure: | |
125 | * | |
126 | * 1) Load bootstrap program (instructions only, no data image for bootstrap) | |
127 | * into bootstrap memory. Use dword writes starting at BSM_SRAM_LOWER_BOUND | |
128 | * | |
129 | * 2) Point (via BSM_DRAM_*) to the "initialize" uCode data and instruction | |
130 | * images in host DRAM. | |
131 | * | |
132 | * 3) Set up BSM to copy from BSM SRAM into uCode instruction SRAM when asked: | |
133 | * BSM_WR_MEM_SRC_REG = 0 | |
134 | * BSM_WR_MEM_DST_REG = RTC_INST_LOWER_BOUND | |
135 | * BSM_WR_MEM_DWCOUNT_REG = # dwords in bootstrap instruction image | |
136 | * | |
137 | * 4) Load bootstrap into instruction SRAM: | |
138 | * BSM_WR_CTRL_REG = BSM_WR_CTRL_REG_BIT_START | |
139 | * | |
140 | * 5) Wait for load completion: | |
141 | * Poll BSM_WR_CTRL_REG for BSM_WR_CTRL_REG_BIT_START = 0 | |
142 | * | |
143 | * 6) Enable future boot loads whenever NIC's power management triggers it: | |
144 | * BSM_WR_CTRL_REG = BSM_WR_CTRL_REG_BIT_START_EN | |
145 | * | |
146 | * 7) Start the NIC by removing all reset bits: | |
147 | * CSR_RESET = 0 | |
148 | * | |
149 | * The bootstrap uCode (already in instruction SRAM) loads initialization | |
150 | * uCode. Initialization uCode performs data initialization, sends | |
151 | * "initialize alive" notification to host, and waits for a signal from | |
152 | * host to load runtime code. | |
153 | * | |
154 | * 4) Point (via BSM_DRAM_*) to the "runtime" uCode data and instruction | |
155 | * images in host DRAM. The last register loaded must be the instruction | |
156 | * bytecount register ("1" in MSbit tells initialization uCode to load | |
157 | * the runtime uCode): | |
158 | * BSM_DRAM_INST_BYTECOUNT_REG = bytecount | BSM_DRAM_INST_LOAD | |
159 | * | |
160 | * 5) Wait for "alive" notification, then issue normal runtime commands. | |
161 | * | |
162 | * Data caching during power-downs: | |
163 | * | |
164 | * Just before the embedded controller powers down (e.g for automatic | |
165 | * power-saving modes, or for RFKILL), uCode stores (via PCI busmaster DMA) | |
166 | * a current snapshot of the embedded processor's data SRAM into host DRAM. | |
167 | * This caches the data while the embedded processor's memory is powered down. | |
168 | * Location and size are controlled by BSM_DRAM_DATA_* registers. | |
169 | * | |
170 | * NOTE: Instruction SRAM does not need to be saved, since that doesn't | |
171 | * change during operation; the original image (from uCode distribution | |
172 | * file) can be used for reload. | |
173 | * | |
174 | * When powering back up, the BSM loads the bootstrap program. Bootstrap looks | |
175 | * at the BSM_DRAM_* registers, which now point to the runtime instruction | |
176 | * image and the cached (modified) runtime data (*not* the initialization | |
177 | * uCode). Bootstrap reloads these runtime images into SRAM, and restarts the | |
178 | * uCode from where it left off before the power-down. | |
179 | * | |
180 | * NOTE: Initialization uCode does *not* run as part of the save/restore | |
181 | * procedure. | |
182 | * | |
183 | * This save/restore method is mostly for autonomous power management during | |
184 | * normal operation (result of POWER_TABLE_CMD). Platform suspend/resume and | |
185 | * RFKILL should use complete restarts (with total re-initialization) of uCode, | |
186 | * allowing total shutdown (including BSM memory). | |
187 | * | |
188 | * Note that, during normal operation, the host DRAM that held the initial | |
189 | * startup data for the runtime code is now being used as a backup data cache | |
190 | * for modified data! If you need to completely re-initialize the NIC, make | |
191 | * sure that you use the runtime data image from the uCode distribution file, | |
192 | * not the modified/saved runtime data. You may want to store a separate | |
193 | * "clean" runtime data image in DRAM to avoid disk reads of distribution file. | |
194 | */ | |
195 | ||
196 | /* BSM bit fields */ | |
197 | #define BSM_WR_CTRL_REG_BIT_START (0x80000000) /* start boot load now */ | |
198 | #define BSM_WR_CTRL_REG_BIT_START_EN (0x40000000) /* enable boot after pwrup*/ | |
199 | #define BSM_DRAM_INST_LOAD (0x80000000) /* start program load now */ | |
200 | ||
201 | /* BSM addresses */ | |
202 | #define BSM_BASE (PRPH_BASE + 0x3400) | |
203 | #define BSM_END (PRPH_BASE + 0x3800) | |
204 | ||
205 | #define BSM_WR_CTRL_REG (BSM_BASE + 0x000) /* ctl and status */ | |
206 | #define BSM_WR_MEM_SRC_REG (BSM_BASE + 0x004) /* source in BSM mem */ | |
207 | #define BSM_WR_MEM_DST_REG (BSM_BASE + 0x008) /* dest in SRAM mem */ | |
208 | #define BSM_WR_DWCOUNT_REG (BSM_BASE + 0x00C) /* bytes */ | |
209 | #define BSM_WR_STATUS_REG (BSM_BASE + 0x010) /* bit 0: 1 == done */ | |
210 | ||
211 | /* | |
212 | * Pointers and size regs for bootstrap load and data SRAM save/restore. | |
213 | * NOTE: 3945 pointers use bits 31:0 of DRAM address. | |
214 | * 4965 pointers use bits 35:4 of DRAM address. | |
215 | */ | |
216 | #define BSM_DRAM_INST_PTR_REG (BSM_BASE + 0x090) | |
217 | #define BSM_DRAM_INST_BYTECOUNT_REG (BSM_BASE + 0x094) | |
218 | #define BSM_DRAM_DATA_PTR_REG (BSM_BASE + 0x098) | |
219 | #define BSM_DRAM_DATA_BYTECOUNT_REG (BSM_BASE + 0x09C) | |
220 | ||
221 | /* | |
222 | * BSM special memory, stays powered on during power-save sleeps. | |
223 | * Read/write, address range from LOWER_BOUND to (LOWER_BOUND + SIZE -1) | |
224 | */ | |
225 | #define BSM_SRAM_LOWER_BOUND (PRPH_BASE + 0x3800) | |
226 | #define BSM_SRAM_SIZE (1024) /* bytes */ | |
227 | ||
67dc320d EG |
228 | /* 4965 SCD memory mapped registers */ |
229 | #define KDR_SCD_BASE (PRPH_BASE + 0xa02c00) | |
230 | ||
231 | #define KDR_SCD_SRAM_BASE_ADDR (KDR_SCD_BASE + 0x0) | |
232 | #define KDR_SCD_EMPTY_BITS (KDR_SCD_BASE + 0x4) | |
233 | #define KDR_SCD_DRAM_BASE_ADDR (KDR_SCD_BASE + 0x10) | |
234 | #define KDR_SCD_AIT (KDR_SCD_BASE + 0x18) | |
235 | #define KDR_SCD_TXFACT (KDR_SCD_BASE + 0x1c) | |
236 | #define KDR_SCD_QUEUE_WRPTR(x) (KDR_SCD_BASE + 0x24 + (x) * 4) | |
237 | #define KDR_SCD_QUEUE_RDPTR(x) (KDR_SCD_BASE + 0x64 + (x) * 4) | |
238 | #define KDR_SCD_SETQUEUENUM (KDR_SCD_BASE + 0xa4) | |
239 | #define KDR_SCD_SET_TXSTAT_TXED (KDR_SCD_BASE + 0xa8) | |
240 | #define KDR_SCD_SET_TXSTAT_DONE (KDR_SCD_BASE + 0xac) | |
241 | #define KDR_SCD_SET_TXSTAT_NOT_SCHD (KDR_SCD_BASE + 0xb0) | |
242 | #define KDR_SCD_DECREASE_CREDIT (KDR_SCD_BASE + 0xb4) | |
243 | #define KDR_SCD_DECREASE_SCREDIT (KDR_SCD_BASE + 0xb8) | |
244 | #define KDR_SCD_LOAD_CREDIT (KDR_SCD_BASE + 0xbc) | |
245 | #define KDR_SCD_LOAD_SCREDIT (KDR_SCD_BASE + 0xc0) | |
246 | #define KDR_SCD_BAR (KDR_SCD_BASE + 0xc4) | |
247 | #define KDR_SCD_BAR_DW0 (KDR_SCD_BASE + 0xc8) | |
248 | #define KDR_SCD_BAR_DW1 (KDR_SCD_BASE + 0xcc) | |
249 | #define KDR_SCD_QUEUECHAIN_SEL (KDR_SCD_BASE + 0xd0) | |
250 | #define KDR_SCD_QUERY_REQ (KDR_SCD_BASE + 0xd8) | |
251 | #define KDR_SCD_QUERY_RES (KDR_SCD_BASE + 0xdc) | |
252 | #define KDR_SCD_PENDING_FRAMES (KDR_SCD_BASE + 0xe0) | |
253 | #define KDR_SCD_INTERRUPT_MASK (KDR_SCD_BASE + 0xe4) | |
254 | #define KDR_SCD_INTERRUPT_THRESHOLD (KDR_SCD_BASE + 0xe8) | |
255 | #define KDR_SCD_QUERY_MIN_FRAME_SIZE (KDR_SCD_BASE + 0x100) | |
256 | #define KDR_SCD_QUEUE_STATUS_BITS(x) (KDR_SCD_BASE + 0x104 + (x) * 4) | |
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257 | |
258 | #endif /* __iwl_prph_h__ */ |