Commit | Line | Data |
---|---|---|
b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
eb7ae89c | 8 | * Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved. |
b481de9c ZY |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
01ebd063 | 11 | * it under the terms of version 2 of the GNU General Public License as |
b481de9c ZY |
12 | * published by the Free Software Foundation. |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
22 | * USA | |
23 | * | |
24 | * The full GNU General Public License is included in this distribution | |
25 | * in the file called LICENSE.GPL. | |
26 | * | |
27 | * Contact Information: | |
759ef89f | 28 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
30 | * | |
31 | * BSD LICENSE | |
32 | * | |
eb7ae89c | 33 | * Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved. |
b481de9c ZY |
34 | * All rights reserved. |
35 | * | |
36 | * Redistribution and use in source and binary forms, with or without | |
37 | * modification, are permitted provided that the following conditions | |
38 | * are met: | |
39 | * | |
40 | * * Redistributions of source code must retain the above copyright | |
41 | * notice, this list of conditions and the following disclaimer. | |
42 | * * Redistributions in binary form must reproduce the above copyright | |
43 | * notice, this list of conditions and the following disclaimer in | |
44 | * the documentation and/or other materials provided with the | |
45 | * distribution. | |
46 | * * Neither the name Intel Corporation nor the names of its | |
47 | * contributors may be used to endorse or promote products derived | |
48 | * from this software without specific prior written permission. | |
49 | * | |
50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
61 | *****************************************************************************/ | |
62 | ||
63 | #ifndef __iwl_prph_h__ | |
64 | #define __iwl_prph_h__ | |
65 | ||
e3851447 BC |
66 | /* |
67 | * Registers in this file are internal, not PCI bus memory mapped. | |
68 | * Driver accesses these via HBUS_TARG_PRPH_* registers. | |
69 | */ | |
b481de9c ZY |
70 | #define PRPH_BASE (0x00000) |
71 | #define PRPH_END (0xFFFFF) | |
72 | ||
73 | /* APMG (power management) constants */ | |
74 | #define APMG_BASE (PRPH_BASE + 0x3000) | |
75 | #define APMG_CLK_CTRL_REG (APMG_BASE + 0x0000) | |
76 | #define APMG_CLK_EN_REG (APMG_BASE + 0x0004) | |
77 | #define APMG_CLK_DIS_REG (APMG_BASE + 0x0008) | |
78 | #define APMG_PS_CTRL_REG (APMG_BASE + 0x000c) | |
79 | #define APMG_PCIDEV_STT_REG (APMG_BASE + 0x0010) | |
80 | #define APMG_RFKILL_REG (APMG_BASE + 0x0014) | |
81 | #define APMG_RTC_INT_STT_REG (APMG_BASE + 0x001c) | |
82 | #define APMG_RTC_INT_MSK_REG (APMG_BASE + 0x0020) | |
83 | ||
84 | #define APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) | |
85 | #define APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) | |
86 | ||
b481de9c | 87 | |
4c43e0d0 TW |
88 | #define APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000) |
89 | #define APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) | |
90 | #define APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) | |
91 | #define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) | |
92 | #define APMG_PS_CTRL_VAL_PWR_SRC_MAX (0x01000000) /* 3945 only */ | |
93 | #define APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000) | |
b481de9c | 94 | |
b481de9c | 95 | |
4c43e0d0 | 96 | #define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) |
b481de9c ZY |
97 | |
98 | /** | |
99 | * BSM (Bootstrap State Machine) | |
100 | * | |
101 | * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program | |
102 | * in special SRAM that does not power down when the embedded control | |
103 | * processor is sleeping (e.g. for periodic power-saving shutdowns of radio). | |
104 | * | |
105 | * When powering back up after sleeps (or during initial uCode load), the BSM | |
106 | * internally loads the short bootstrap program from the special SRAM into the | |
107 | * embedded processor's instruction SRAM, and starts the processor so it runs | |
108 | * the bootstrap program. | |
109 | * | |
110 | * This bootstrap program loads (via PCI busmaster DMA) instructions and data | |
111 | * images for a uCode program from host DRAM locations. The host driver | |
112 | * indicates DRAM locations and sizes for instruction and data images via the | |
113 | * four BSM_DRAM_* registers. Once the bootstrap program loads the new program, | |
114 | * the new program starts automatically. | |
115 | * | |
116 | * The uCode used for open-source drivers includes two programs: | |
117 | * | |
118 | * 1) Initialization -- performs hardware calibration and sets up some | |
119 | * internal data, then notifies host via "initialize alive" notification | |
120 | * (struct iwl_init_alive_resp) that it has completed all of its work. | |
121 | * After signal from host, it then loads and starts the runtime program. | |
122 | * The initialization program must be used when initially setting up the | |
123 | * NIC after loading the driver. | |
124 | * | |
125 | * 2) Runtime/Protocol -- performs all normal runtime operations. This | |
126 | * notifies host via "alive" notification (struct iwl_alive_resp) that it | |
127 | * is ready to be used. | |
128 | * | |
129 | * When initializing the NIC, the host driver does the following procedure: | |
130 | * | |
131 | * 1) Load bootstrap program (instructions only, no data image for bootstrap) | |
132 | * into bootstrap memory. Use dword writes starting at BSM_SRAM_LOWER_BOUND | |
133 | * | |
134 | * 2) Point (via BSM_DRAM_*) to the "initialize" uCode data and instruction | |
135 | * images in host DRAM. | |
136 | * | |
137 | * 3) Set up BSM to copy from BSM SRAM into uCode instruction SRAM when asked: | |
138 | * BSM_WR_MEM_SRC_REG = 0 | |
139 | * BSM_WR_MEM_DST_REG = RTC_INST_LOWER_BOUND | |
140 | * BSM_WR_MEM_DWCOUNT_REG = # dwords in bootstrap instruction image | |
141 | * | |
142 | * 4) Load bootstrap into instruction SRAM: | |
143 | * BSM_WR_CTRL_REG = BSM_WR_CTRL_REG_BIT_START | |
144 | * | |
145 | * 5) Wait for load completion: | |
146 | * Poll BSM_WR_CTRL_REG for BSM_WR_CTRL_REG_BIT_START = 0 | |
147 | * | |
148 | * 6) Enable future boot loads whenever NIC's power management triggers it: | |
149 | * BSM_WR_CTRL_REG = BSM_WR_CTRL_REG_BIT_START_EN | |
150 | * | |
151 | * 7) Start the NIC by removing all reset bits: | |
152 | * CSR_RESET = 0 | |
153 | * | |
154 | * The bootstrap uCode (already in instruction SRAM) loads initialization | |
155 | * uCode. Initialization uCode performs data initialization, sends | |
156 | * "initialize alive" notification to host, and waits for a signal from | |
157 | * host to load runtime code. | |
158 | * | |
159 | * 4) Point (via BSM_DRAM_*) to the "runtime" uCode data and instruction | |
160 | * images in host DRAM. The last register loaded must be the instruction | |
a96a27f9 | 161 | * byte count register ("1" in MSbit tells initialization uCode to load |
b481de9c | 162 | * the runtime uCode): |
a96a27f9 | 163 | * BSM_DRAM_INST_BYTECOUNT_REG = byte count | BSM_DRAM_INST_LOAD |
b481de9c ZY |
164 | * |
165 | * 5) Wait for "alive" notification, then issue normal runtime commands. | |
166 | * | |
167 | * Data caching during power-downs: | |
168 | * | |
169 | * Just before the embedded controller powers down (e.g for automatic | |
170 | * power-saving modes, or for RFKILL), uCode stores (via PCI busmaster DMA) | |
171 | * a current snapshot of the embedded processor's data SRAM into host DRAM. | |
172 | * This caches the data while the embedded processor's memory is powered down. | |
173 | * Location and size are controlled by BSM_DRAM_DATA_* registers. | |
174 | * | |
175 | * NOTE: Instruction SRAM does not need to be saved, since that doesn't | |
176 | * change during operation; the original image (from uCode distribution | |
177 | * file) can be used for reload. | |
178 | * | |
179 | * When powering back up, the BSM loads the bootstrap program. Bootstrap looks | |
180 | * at the BSM_DRAM_* registers, which now point to the runtime instruction | |
181 | * image and the cached (modified) runtime data (*not* the initialization | |
182 | * uCode). Bootstrap reloads these runtime images into SRAM, and restarts the | |
183 | * uCode from where it left off before the power-down. | |
184 | * | |
185 | * NOTE: Initialization uCode does *not* run as part of the save/restore | |
186 | * procedure. | |
187 | * | |
188 | * This save/restore method is mostly for autonomous power management during | |
189 | * normal operation (result of POWER_TABLE_CMD). Platform suspend/resume and | |
190 | * RFKILL should use complete restarts (with total re-initialization) of uCode, | |
191 | * allowing total shutdown (including BSM memory). | |
192 | * | |
193 | * Note that, during normal operation, the host DRAM that held the initial | |
194 | * startup data for the runtime code is now being used as a backup data cache | |
195 | * for modified data! If you need to completely re-initialize the NIC, make | |
196 | * sure that you use the runtime data image from the uCode distribution file, | |
197 | * not the modified/saved runtime data. You may want to store a separate | |
198 | * "clean" runtime data image in DRAM to avoid disk reads of distribution file. | |
199 | */ | |
200 | ||
201 | /* BSM bit fields */ | |
202 | #define BSM_WR_CTRL_REG_BIT_START (0x80000000) /* start boot load now */ | |
203 | #define BSM_WR_CTRL_REG_BIT_START_EN (0x40000000) /* enable boot after pwrup*/ | |
204 | #define BSM_DRAM_INST_LOAD (0x80000000) /* start program load now */ | |
205 | ||
206 | /* BSM addresses */ | |
207 | #define BSM_BASE (PRPH_BASE + 0x3400) | |
208 | #define BSM_END (PRPH_BASE + 0x3800) | |
209 | ||
210 | #define BSM_WR_CTRL_REG (BSM_BASE + 0x000) /* ctl and status */ | |
211 | #define BSM_WR_MEM_SRC_REG (BSM_BASE + 0x004) /* source in BSM mem */ | |
212 | #define BSM_WR_MEM_DST_REG (BSM_BASE + 0x008) /* dest in SRAM mem */ | |
213 | #define BSM_WR_DWCOUNT_REG (BSM_BASE + 0x00C) /* bytes */ | |
214 | #define BSM_WR_STATUS_REG (BSM_BASE + 0x010) /* bit 0: 1 == done */ | |
215 | ||
216 | /* | |
217 | * Pointers and size regs for bootstrap load and data SRAM save/restore. | |
218 | * NOTE: 3945 pointers use bits 31:0 of DRAM address. | |
219 | * 4965 pointers use bits 35:4 of DRAM address. | |
220 | */ | |
221 | #define BSM_DRAM_INST_PTR_REG (BSM_BASE + 0x090) | |
222 | #define BSM_DRAM_INST_BYTECOUNT_REG (BSM_BASE + 0x094) | |
223 | #define BSM_DRAM_DATA_PTR_REG (BSM_BASE + 0x098) | |
224 | #define BSM_DRAM_DATA_BYTECOUNT_REG (BSM_BASE + 0x09C) | |
225 | ||
226 | /* | |
227 | * BSM special memory, stays powered on during power-save sleeps. | |
228 | * Read/write, address range from LOWER_BOUND to (LOWER_BOUND + SIZE -1) | |
229 | */ | |
230 | #define BSM_SRAM_LOWER_BOUND (PRPH_BASE + 0x3800) | |
231 | #define BSM_SRAM_SIZE (1024) /* bytes */ | |
232 | ||
e3851447 BC |
233 | |
234 | /* 3945 Tx scheduler registers */ | |
70883109 EG |
235 | #define ALM_SCD_BASE (PRPH_BASE + 0x2E00) |
236 | #define ALM_SCD_MODE_REG (ALM_SCD_BASE + 0x000) | |
237 | #define ALM_SCD_ARASTAT_REG (ALM_SCD_BASE + 0x004) | |
238 | #define ALM_SCD_TXFACT_REG (ALM_SCD_BASE + 0x010) | |
239 | #define ALM_SCD_TXF4MF_REG (ALM_SCD_BASE + 0x014) | |
240 | #define ALM_SCD_TXF5MF_REG (ALM_SCD_BASE + 0x020) | |
241 | #define ALM_SCD_SBYP_MODE_1_REG (ALM_SCD_BASE + 0x02C) | |
242 | #define ALM_SCD_SBYP_MODE_2_REG (ALM_SCD_BASE + 0x030) | |
243 | ||
038669e4 EG |
244 | /** |
245 | * Tx Scheduler | |
246 | * | |
a96a27f9 | 247 | * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs |
038669e4 EG |
248 | * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in |
249 | * host DRAM. It steers each frame's Tx command (which contains the frame | |
250 | * data) into one of up to 7 prioritized Tx DMA FIFO channels within the | |
251 | * device. A queue maps to only one (selectable by driver) Tx DMA channel, | |
252 | * but one DMA channel may take input from several queues. | |
253 | * | |
254 | * Tx DMA channels have dedicated purposes. For 4965, they are used as follows: | |
255 | * | |
256 | * 0 -- EDCA BK (background) frames, lowest priority | |
257 | * 1 -- EDCA BE (best effort) frames, normal priority | |
258 | * 2 -- EDCA VI (video) frames, higher priority | |
259 | * 3 -- EDCA VO (voice) and management frames, highest priority | |
260 | * 4 -- Commands (e.g. RXON, etc.) | |
261 | * 5 -- HCCA short frames | |
262 | * 6 -- HCCA long frames | |
263 | * 7 -- not used by driver (device-internal only) | |
264 | * | |
265 | * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. | |
266 | * In addition, driver can map queues 7-15 to Tx DMA/FIFO channels 0-3 to | |
267 | * support 11n aggregation via EDCA DMA channels. | |
268 | * | |
269 | * The driver sets up each queue to work in one of two modes: | |
270 | * | |
271 | * 1) Scheduler-Ack, in which the scheduler automatically supports a | |
272 | * block-ack (BA) window of up to 64 TFDs. In this mode, each queue | |
273 | * contains TFDs for a unique combination of Recipient Address (RA) | |
274 | * and Traffic Identifier (TID), that is, traffic of a given | |
275 | * Quality-Of-Service (QOS) priority, destined for a single station. | |
276 | * | |
277 | * In scheduler-ack mode, the scheduler keeps track of the Tx status of | |
278 | * each frame within the BA window, including whether it's been transmitted, | |
279 | * and whether it's been acknowledged by the receiving station. The device | |
280 | * automatically processes block-acks received from the receiving STA, | |
281 | * and reschedules un-acked frames to be retransmitted (successful | |
282 | * Tx completion may end up being out-of-order). | |
283 | * | |
284 | * The driver must maintain the queue's Byte Count table in host DRAM | |
285 | * (struct iwl4965_sched_queue_byte_cnt_tbl) for this mode. | |
286 | * This mode does not support fragmentation. | |
287 | * | |
288 | * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. | |
289 | * The device may automatically retry Tx, but will retry only one frame | |
290 | * at a time, until receiving ACK from receiving station, or reaching | |
291 | * retry limit and giving up. | |
292 | * | |
293 | * The command queue (#4) must use this mode! | |
294 | * This mode does not require use of the Byte Count table in host DRAM. | |
295 | * | |
296 | * Driver controls scheduler operation via 3 means: | |
297 | * 1) Scheduler registers | |
298 | * 2) Shared scheduler data base in internal 4956 SRAM | |
299 | * 3) Shared data in host DRAM | |
300 | * | |
301 | * Initialization: | |
302 | * | |
303 | * When loading, driver should allocate memory for: | |
304 | * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. | |
305 | * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory | |
306 | * (1024 bytes for each queue). | |
307 | * | |
308 | * After receiving "Alive" response from uCode, driver must initialize | |
309 | * the scheduler (especially for queue #4, the command queue, otherwise | |
310 | * the driver can't issue commands!): | |
311 | */ | |
312 | ||
313 | /** | |
314 | * Max Tx window size is the max number of contiguous TFDs that the scheduler | |
315 | * can keep track of at one time when creating block-ack chains of frames. | |
316 | * Note that "64" matches the number of ack bits in a block-ack packet. | |
317 | * Driver should use SCD_WIN_SIZE and SCD_FRAME_LIMIT values to initialize | |
318 | * IWL49_SCD_CONTEXT_QUEUE_OFFSET(x) values. | |
319 | */ | |
320 | #define SCD_WIN_SIZE 64 | |
321 | #define SCD_FRAME_LIMIT 64 | |
322 | ||
323 | /* SCD registers are internal, must be accessed via HBUS_TARG_PRPH regs */ | |
324 | #define IWL49_SCD_START_OFFSET 0xa02c00 | |
325 | ||
326 | /* | |
327 | * 4965 tells driver SRAM address for internal scheduler structs via this reg. | |
328 | * Value is valid only after "Alive" response from uCode. | |
329 | */ | |
330 | #define IWL49_SCD_SRAM_BASE_ADDR (IWL49_SCD_START_OFFSET + 0x0) | |
331 | ||
332 | /* | |
333 | * Driver may need to update queue-empty bits after changing queue's | |
334 | * write and read pointers (indexes) during (re-)initialization (i.e. when | |
335 | * scheduler is not tracking what's happening). | |
336 | * Bit fields: | |
337 | * 31-16: Write mask -- 1: update empty bit, 0: don't change empty bit | |
338 | * 15-00: Empty state, one for each queue -- 1: empty, 0: non-empty | |
339 | * NOTE: This register is not used by Linux driver. | |
340 | */ | |
341 | #define IWL49_SCD_EMPTY_BITS (IWL49_SCD_START_OFFSET + 0x4) | |
342 | ||
343 | /* | |
344 | * Physical base address of array of byte count (BC) circular buffers (CBs). | |
345 | * Each Tx queue has a BC CB in host DRAM to support Scheduler-ACK mode. | |
346 | * This register points to BC CB for queue 0, must be on 1024-byte boundary. | |
347 | * Others are spaced by 1024 bytes. | |
348 | * Each BC CB is 2 bytes * (256 + 64) = 740 bytes, followed by 384 bytes pad. | |
349 | * (Index into a queue's BC CB) = (index into queue's TFD CB) = (SSN & 0xff). | |
350 | * Bit fields: | |
351 | * 25-00: Byte Count CB physical address [35:10], must be 1024-byte aligned. | |
352 | */ | |
353 | #define IWL49_SCD_DRAM_BASE_ADDR (IWL49_SCD_START_OFFSET + 0x10) | |
354 | ||
355 | /* | |
356 | * Enables any/all Tx DMA/FIFO channels. | |
357 | * Scheduler generates requests for only the active channels. | |
358 | * Set this to 0xff to enable all 8 channels (normal usage). | |
359 | * Bit fields: | |
360 | * 7- 0: Enable (1), disable (0), one bit for each channel 0-7 | |
361 | */ | |
362 | #define IWL49_SCD_TXFACT (IWL49_SCD_START_OFFSET + 0x1c) | |
038669e4 EG |
363 | /* |
364 | * Queue (x) Write Pointers (indexes, really!), one for each Tx queue. | |
365 | * Initialized and updated by driver as new TFDs are added to queue. | |
366 | * NOTE: If using Block Ack, index must correspond to frame's | |
367 | * Start Sequence Number; index = (SSN & 0xff) | |
368 | * NOTE: Alternative to HBUS_TARG_WRPTR, which is what Linux driver uses? | |
369 | */ | |
370 | #define IWL49_SCD_QUEUE_WRPTR(x) (IWL49_SCD_START_OFFSET + 0x24 + (x) * 4) | |
371 | ||
372 | /* | |
373 | * Queue (x) Read Pointers (indexes, really!), one for each Tx queue. | |
374 | * For FIFO mode, index indicates next frame to transmit. | |
375 | * For Scheduler-ACK mode, index indicates first frame in Tx window. | |
376 | * Initialized by driver, updated by scheduler. | |
377 | */ | |
378 | #define IWL49_SCD_QUEUE_RDPTR(x) (IWL49_SCD_START_OFFSET + 0x64 + (x) * 4) | |
379 | ||
380 | /* | |
381 | * Select which queues work in chain mode (1) vs. not (0). | |
382 | * Use chain mode to build chains of aggregated frames. | |
383 | * Bit fields: | |
384 | * 31-16: Reserved | |
385 | * 15-00: Mode, one bit for each queue -- 1: Chain mode, 0: one-at-a-time | |
386 | * NOTE: If driver sets up queue for chain mode, it should be also set up | |
387 | * Scheduler-ACK mode as well, via SCD_QUEUE_STATUS_BITS(x). | |
388 | */ | |
389 | #define IWL49_SCD_QUEUECHAIN_SEL (IWL49_SCD_START_OFFSET + 0xd0) | |
390 | ||
391 | /* | |
392 | * Select which queues interrupt driver when scheduler increments | |
393 | * a queue's read pointer (index). | |
394 | * Bit fields: | |
395 | * 31-16: Reserved | |
396 | * 15-00: Interrupt enable, one bit for each queue -- 1: enabled, 0: disabled | |
397 | * NOTE: This functionality is apparently a no-op; driver relies on interrupts | |
398 | * from Rx queue to read Tx command responses and update Tx queues. | |
399 | */ | |
400 | #define IWL49_SCD_INTERRUPT_MASK (IWL49_SCD_START_OFFSET + 0xe4) | |
401 | ||
402 | /* | |
403 | * Queue search status registers. One for each queue. | |
404 | * Sets up queue mode and assigns queue to Tx DMA channel. | |
405 | * Bit fields: | |
406 | * 19-10: Write mask/enable bits for bits 0-9 | |
407 | * 9: Driver should init to "0" | |
408 | * 8: Scheduler-ACK mode (1), non-Scheduler-ACK (i.e. FIFO) mode (0). | |
409 | * Driver should init to "1" for aggregation mode, or "0" otherwise. | |
410 | * 7-6: Driver should init to "0" | |
411 | * 5: Window Size Left; indicates whether scheduler can request | |
412 | * another TFD, based on window size, etc. Driver should init | |
413 | * this bit to "1" for aggregation mode, or "0" for non-agg. | |
414 | * 4-1: Tx FIFO to use (range 0-7). | |
415 | * 0: Queue is active (1), not active (0). | |
416 | * Other bits should be written as "0" | |
417 | * | |
418 | * NOTE: If enabling Scheduler-ACK mode, chain mode should also be enabled | |
419 | * via SCD_QUEUECHAIN_SEL. | |
420 | */ | |
421 | #define IWL49_SCD_QUEUE_STATUS_BITS(x)\ | |
422 | (IWL49_SCD_START_OFFSET + 0x104 + (x) * 4) | |
423 | ||
424 | /* Bit field positions */ | |
425 | #define IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE (0) | |
426 | #define IWL49_SCD_QUEUE_STTS_REG_POS_TXF (1) | |
427 | #define IWL49_SCD_QUEUE_STTS_REG_POS_WSL (5) | |
428 | #define IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK (8) | |
429 | ||
430 | /* Write masks */ | |
431 | #define IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (10) | |
432 | #define IWL49_SCD_QUEUE_STTS_REG_MSK (0x0007FC00) | |
433 | ||
434 | /** | |
435 | * 4965 internal SRAM structures for scheduler, shared with driver ... | |
436 | * | |
437 | * Driver should clear and initialize the following areas after receiving | |
438 | * "Alive" response from 4965 uCode, i.e. after initial | |
439 | * uCode load, or after a uCode load done for error recovery: | |
440 | * | |
441 | * SCD_CONTEXT_DATA_OFFSET (size 128 bytes) | |
442 | * SCD_TX_STTS_BITMAP_OFFSET (size 256 bytes) | |
443 | * SCD_TRANSLATE_TBL_OFFSET (size 32 bytes) | |
444 | * | |
445 | * Driver accesses SRAM via HBUS_TARG_MEM_* registers. | |
446 | * Driver reads base address of this scheduler area from SCD_SRAM_BASE_ADDR. | |
447 | * All OFFSET values must be added to this base address. | |
448 | */ | |
449 | ||
450 | /* | |
451 | * Queue context. One 8-byte entry for each of 16 queues. | |
452 | * | |
453 | * Driver should clear this entire area (size 0x80) to 0 after receiving | |
454 | * "Alive" notification from uCode. Additionally, driver should init | |
455 | * each queue's entry as follows: | |
456 | * | |
457 | * LS Dword bit fields: | |
458 | * 0-06: Max Tx window size for Scheduler-ACK. Driver should init to 64. | |
459 | * | |
460 | * MS Dword bit fields: | |
461 | * 16-22: Frame limit. Driver should init to 10 (0xa). | |
462 | * | |
463 | * Driver should init all other bits to 0. | |
464 | * | |
465 | * Init must be done after driver receives "Alive" response from 4965 uCode, | |
466 | * and when setting up queue for aggregation. | |
467 | */ | |
468 | #define IWL49_SCD_CONTEXT_DATA_OFFSET 0x380 | |
469 | #define IWL49_SCD_CONTEXT_QUEUE_OFFSET(x) \ | |
470 | (IWL49_SCD_CONTEXT_DATA_OFFSET + ((x) * 8)) | |
471 | ||
472 | #define IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS (0) | |
473 | #define IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK (0x0000007F) | |
474 | #define IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) | |
475 | #define IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) | |
476 | ||
e3851447 | 477 | /* |
038669e4 EG |
478 | * Tx Status Bitmap |
479 | * | |
480 | * Driver should clear this entire area (size 0x100) to 0 after receiving | |
481 | * "Alive" notification from uCode. Area is used only by device itself; | |
482 | * no other support (besides clearing) is required from driver. | |
e3851447 | 483 | */ |
038669e4 EG |
484 | #define IWL49_SCD_TX_STTS_BITMAP_OFFSET 0x400 |
485 | ||
486 | /* | |
487 | * RAxTID to queue translation mapping. | |
488 | * | |
489 | * When queue is in Scheduler-ACK mode, frames placed in a that queue must be | |
490 | * for only one combination of receiver address (RA) and traffic ID (TID), i.e. | |
491 | * one QOS priority level destined for one station (for this wireless link, | |
492 | * not final destination). The SCD_TRANSLATE_TABLE area provides 16 16-bit | |
493 | * mappings, one for each of the 16 queues. If queue is not in Scheduler-ACK | |
494 | * mode, the device ignores the mapping value. | |
495 | * | |
496 | * Bit fields, for each 16-bit map: | |
497 | * 15-9: Reserved, set to 0 | |
498 | * 8-4: Index into device's station table for recipient station | |
499 | * 3-0: Traffic ID (tid), range 0-15 | |
500 | * | |
501 | * Driver should clear this entire area (size 32 bytes) to 0 after receiving | |
502 | * "Alive" notification from uCode. To update a 16-bit map value, driver | |
503 | * must read a dword-aligned value from device SRAM, replace the 16-bit map | |
504 | * value of interest, and write the dword value back into device SRAM. | |
505 | */ | |
506 | #define IWL49_SCD_TRANSLATE_TBL_OFFSET 0x500 | |
507 | ||
508 | /* Find translation table dword to read/write for given queue */ | |
509 | #define IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \ | |
510 | ((IWL49_SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffffffc) | |
511 | ||
30e553e3 TW |
512 | #define IWL_SCD_TXFIFO_POS_TID (0) |
513 | #define IWL_SCD_TXFIFO_POS_RA (4) | |
514 | #define IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) | |
038669e4 EG |
515 | |
516 | /* 5000 SCD */ | |
99da1b48 RR |
517 | #define IWL50_SCD_QUEUE_STTS_REG_POS_TXF (0) |
518 | #define IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE (3) | |
519 | #define IWL50_SCD_QUEUE_STTS_REG_POS_WSL (4) | |
520 | #define IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19) | |
521 | #define IWL50_SCD_QUEUE_STTS_REG_MSK (0x00FF0000) | |
522 | ||
523 | #define IWL50_SCD_QUEUE_CTX_REG1_CREDIT_POS (8) | |
524 | #define IWL50_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00) | |
525 | #define IWL50_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24) | |
526 | #define IWL50_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000) | |
527 | #define IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0) | |
528 | #define IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F) | |
529 | #define IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) | |
530 | #define IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) | |
531 | ||
532 | #define IWL50_SCD_CONTEXT_DATA_OFFSET (0x600) | |
533 | #define IWL50_SCD_TX_STTS_BITMAP_OFFSET (0x7B1) | |
534 | #define IWL50_SCD_TRANSLATE_TBL_OFFSET (0x7E0) | |
535 | ||
536 | #define IWL50_SCD_CONTEXT_QUEUE_OFFSET(x)\ | |
537 | (IWL50_SCD_CONTEXT_DATA_OFFSET + ((x) * 8)) | |
538 | ||
539 | #define IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \ | |
540 | ((IWL50_SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffc) | |
541 | ||
542 | #define IWL50_SCD_QUEUECHAIN_SEL_ALL(x) (((1<<(x)) - 1) &\ | |
543 | (~(1<<IWL_CMD_QUEUE_NUM))) | |
544 | ||
12a81f60 | 545 | #define IWL50_SCD_BASE (PRPH_BASE + 0xa02c00) |
b559e66c | 546 | |
12a81f60 TW |
547 | #define IWL50_SCD_SRAM_BASE_ADDR (IWL50_SCD_BASE + 0x0) |
548 | #define IWL50_SCD_DRAM_BASE_ADDR (IWL50_SCD_BASE + 0x8) | |
549 | #define IWL50_SCD_AIT (IWL50_SCD_BASE + 0x0c) | |
550 | #define IWL50_SCD_TXFACT (IWL50_SCD_BASE + 0x10) | |
551 | #define IWL50_SCD_ACTIVE (IWL50_SCD_BASE + 0x14) | |
552 | #define IWL50_SCD_QUEUE_WRPTR(x) (IWL50_SCD_BASE + 0x18 + (x) * 4) | |
553 | #define IWL50_SCD_QUEUE_RDPTR(x) (IWL50_SCD_BASE + 0x68 + (x) * 4) | |
554 | #define IWL50_SCD_QUEUECHAIN_SEL (IWL50_SCD_BASE + 0xe8) | |
555 | #define IWL50_SCD_AGGR_SEL (IWL50_SCD_BASE + 0x248) | |
556 | #define IWL50_SCD_INTERRUPT_MASK (IWL50_SCD_BASE + 0x108) | |
557 | #define IWL50_SCD_QUEUE_STATUS_BITS(x) (IWL50_SCD_BASE + 0x10c + (x) * 4) | |
b559e66c | 558 | |
038669e4 EG |
559 | /*********************** END TX SCHEDULER *************************************/ |
560 | ||
b481de9c | 561 | #endif /* __iwl_prph_h__ */ |