projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
iwlwifi: add more comments to IWL_DL_xx
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-rx.c
CommitLineData
a55360e4
TW		 1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
a55360e4
TW		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
1781a07f 30#include <linux/etherdevice.h>
a55360e4 31#include <net/mac80211.h>
a05ffd39 32#include <asm/unaligned.h>
a55360e4
TW		 33#include "iwl-eeprom.h"
34#include "iwl-dev.h"
35#include "iwl-core.h"
36#include "iwl-sta.h"
37#include "iwl-io.h"
c1354754 38#include "iwl-calib.h"
a55360e4
TW		 39#include "iwl-helpers.h"
40/************************** RX-FUNCTIONS ****************************/
41/*
42 * Rx theory of operation
43 *
44 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
45 * each of which point to Receive Buffers to be filled by the NIC. These get
46 * used not only for Rx frames, but for any command response or notification
47 * from the NIC. The driver and NIC manage the Rx buffers by means
48 * of indexes into the circular buffer.
49 *
50 * Rx Queue Indexes
51 * The host/firmware share two index registers for managing the Rx buffers.
52 *
53 * The READ index maps to the first position that the firmware may be writing
54 * to -- the driver can read up to (but not including) this position and get
55 * good data.
56 * The READ index is managed by the firmware once the card is enabled.
57 *
58 * The WRITE index maps to the last position the driver has read from -- the
59 * position preceding WRITE is the last slot the firmware can place a packet.
60 *
61 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
62 * WRITE = READ.
63 *
64 * During initialization, the host sets up the READ queue position to the first
65 * INDEX position, and WRITE to the last (READ - 1 wrapped)
66 *
67 * When the firmware places a packet in a buffer, it will advance the READ index
68 * and fire the RX interrupt. The driver can then query the READ index and
69 * process as many packets as possible, moving the WRITE index forward as it
70 * resets the Rx queue buffers with new memory.
71 *
72 * The management in the driver is as follows:
73 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
74 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
75 * to replenish the iwl->rxq->rx_free.
76 * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
77 * iwl->rxq is replenished and the READ INDEX is updated (updating the
78 * 'processed' and 'read' driver indexes as well)
79 * + A received packet is processed and handed to the kernel network stack,
80 * detached from the iwl->rxq. The driver 'processed' index is updated.
81 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
82 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
83 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
84 * were enough free buffers and RX_STALLED is set it is cleared.
85 *
86 *
87 * Driver sequence:
88 *
89 * iwl_rx_queue_alloc() Allocates rx_free
90 * iwl_rx_replenish() Replenishes rx_free list from rx_used, and calls
91 * iwl_rx_queue_restock
92 * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
93 * queue, updates firmware pointers, and updates
94 * the WRITE index. If insufficient rx_free buffers
95 * are available, schedules iwl_rx_replenish
96 *
97 * -- enable interrupts --
98 * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
99 * READ INDEX, detaching the SKB from the pool.
100 * Moves the packet buffer from queue to rx_used.
101 * Calls iwl_rx_queue_restock to refill any empty
102 * slots.
103 * ...
104 *
105 */
106
107/**
108 * iwl_rx_queue_space - Return number of free slots available in queue.
109 */
110int iwl_rx_queue_space(const struct iwl_rx_queue *q)
111{
112 int s = q->read - q->write;
113 if (s <= 0)
114 s += RX_QUEUE_SIZE;
115 /* keep some buffer to not confuse full and empty queue */
116 s -= 2;
117 if (s < 0)
118 s = 0;
119 return s;
120}
121EXPORT_SYMBOL(iwl_rx_queue_space);
122
123/**
124 * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
125 */
126int iwl_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue *q)
127{
128 u32 reg = 0;
129 int ret = 0;
130 unsigned long flags;
131
132 spin_lock_irqsave(&q->lock, flags);
133
134 if (q->need_update == 0)
135 goto exit_unlock;
136
137 /* If power-saving is in use, make sure device is awake */
138 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
139 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
140
141 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
142 iwl_set_bit(priv, CSR_GP_CNTRL,
143 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
144 goto exit_unlock;
145 }
146
147 ret = iwl_grab_nic_access(priv);
148 if (ret)
149 goto exit_unlock;
150
151 /* Device expects a multiple of 8 */
152 iwl_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
153 q->write & ~0x7);
154 iwl_release_nic_access(priv);
155
156 /* Else device is assumed to be awake */
157 } else
158 /* Device expects a multiple of 8 */
159 iwl_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
160
161
162 q->need_update = 0;
163
164 exit_unlock:
165 spin_unlock_irqrestore(&q->lock, flags);
166 return ret;
167}
168EXPORT_SYMBOL(iwl_rx_queue_update_write_ptr);
169/**
170 * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
171 */
172static inline __le32 iwl_dma_addr2rbd_ptr(struct iwl_priv *priv,
173 dma_addr_t dma_addr)
174{
175 return cpu_to_le32((u32)(dma_addr >> 8));
176}
177
178/**
179 * iwl_rx_queue_restock - refill RX queue from pre-allocated pool
180 *
181 * If there are slots in the RX queue that need to be restocked,
182 * and we have free pre-allocated buffers, fill the ranks as much
183 * as we can, pulling from rx_free.
184 *
185 * This moves the 'write' index forward to catch up with 'processed', and
186 * also updates the memory address in the firmware to reference the new
187 * target buffer.
188 */
189int iwl_rx_queue_restock(struct iwl_priv *priv)
190{
191 struct iwl_rx_queue *rxq = &priv->rxq;
192 struct list_head *element;
193 struct iwl_rx_mem_buffer *rxb;
194 unsigned long flags;
195 int write;
196 int ret = 0;
197
198 spin_lock_irqsave(&rxq->lock, flags);
199 write = rxq->write & ~0x7;
200 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
201 /* Get next free Rx buffer, remove from free list */
202 element = rxq->rx_free.next;
203 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
204 list_del(element);
205
206 /* Point to Rx buffer via next RBD in circular buffer */
4018517a 207 rxq->bd[rxq->write] = iwl_dma_addr2rbd_ptr(priv, rxb->aligned_dma_addr);
a55360e4
TW		 208 rxq->queue[rxq->write] = rxb;
209 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
210 rxq->free_count--;
211 }
212 spin_unlock_irqrestore(&rxq->lock, flags);
213 /* If the pre-allocated buffer pool is dropping low, schedule to
214 * refill it */
215 if (rxq->free_count <= RX_LOW_WATERMARK)
216 queue_work(priv->workqueue, &priv->rx_replenish);
217
218
219 /* If we've added more space for the firmware to place data, tell it.
220 * Increment device's write pointer in multiples of 8. */
e4e58cf8 221 if (write != (rxq->write & ~0x7)) {
a55360e4
TW		 222 spin_lock_irqsave(&rxq->lock, flags);
223 rxq->need_update = 1;
224 spin_unlock_irqrestore(&rxq->lock, flags);
225 ret = iwl_rx_queue_update_write_ptr(priv, rxq);
226 }
227
228 return ret;
229}
230EXPORT_SYMBOL(iwl_rx_queue_restock);
231
232
233/**
234 * iwl_rx_replenish - Move all used packet from rx_used to rx_free
235 *
236 * When moving to rx_free an SKB is allocated for the slot.
237 *
238 * Also restock the Rx queue via iwl_rx_queue_restock.
239 * This is called as a scheduled work item (except for during initialization)
240 */
241void iwl_rx_allocate(struct iwl_priv *priv)
242{
243 struct iwl_rx_queue *rxq = &priv->rxq;
244 struct list_head *element;
245 struct iwl_rx_mem_buffer *rxb;
246 unsigned long flags;
f1bc4ac6
ZY		 247
248 while (1) {
249 spin_lock_irqsave(&rxq->lock, flags);
250
251 if (list_empty(&rxq->rx_used)) {
252 spin_unlock_irqrestore(&rxq->lock, flags);
253 return;
254 }
a55360e4
TW		 255 element = rxq->rx_used.next;
256 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
f1bc4ac6
ZY		 257 list_del(element);
258
259 spin_unlock_irqrestore(&rxq->lock, flags);
a55360e4
TW		 260
261 /* Alloc a new receive buffer */
4018517a 262 rxb->skb = alloc_skb(priv->hw_params.rx_buf_size + 256,
f1bc4ac6 263 GFP_KERNEL);
a55360e4 264 if (!rxb->skb) {
a3139c59
SO		 265 dev_printk(KERN_CRIT, &(priv->hw->wiphy->dev),
266 "Can not allocate SKB buffers\n");
a55360e4
TW		 267 /* We don't reschedule replenish work here -- we will
268 * call the restock method and if it still needs
269 * more buffers it will schedule replenish */
270 break;
271 }
a55360e4
TW		 272
273 /* Get physical address of RB/SKB */
4018517a
JB		 274 rxb->real_dma_addr = pci_map_single(
275 priv->pci_dev,
276 rxb->skb->data,
277 priv->hw_params.rx_buf_size + 256,
278 PCI_DMA_FROMDEVICE);
279 /* dma address must be no more than 36 bits */
280 BUG_ON(rxb->real_dma_addr & ~DMA_BIT_MASK(36));
281 /* and also 256 byte aligned! */
282 rxb->aligned_dma_addr = ALIGN(rxb->real_dma_addr, 256);
283 skb_reserve(rxb->skb, rxb->aligned_dma_addr - rxb->real_dma_addr);
284
f1bc4ac6
ZY		 285 spin_lock_irqsave(&rxq->lock, flags);
286
a55360e4
TW		 287 list_add_tail(&rxb->list, &rxq->rx_free);
288 rxq->free_count++;
f1bc4ac6
ZY		 289 priv->alloc_rxb_skb++;
290
291 spin_unlock_irqrestore(&rxq->lock, flags);
a55360e4 292 }
a55360e4 293}
a55360e4
TW		 294
295void iwl_rx_replenish(struct iwl_priv *priv)
296{
297 unsigned long flags;
298
299 iwl_rx_allocate(priv);
300
301 spin_lock_irqsave(&priv->lock, flags);
302 iwl_rx_queue_restock(priv);
303 spin_unlock_irqrestore(&priv->lock, flags);
304}
305EXPORT_SYMBOL(iwl_rx_replenish);
306
307
308/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
309 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
310 * This free routine walks the list of POOL entries and if SKB is set to
311 * non NULL it is unmapped and freed
312 */
313void iwl_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
314{
315 int i;
316 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
317 if (rxq->pool[i].skb != NULL) {
318 pci_unmap_single(priv->pci_dev,
4018517a
JB		 319 rxq->pool[i].real_dma_addr,
320 priv->hw_params.rx_buf_size + 256,
a55360e4
TW		 321 PCI_DMA_FROMDEVICE);
322 dev_kfree_skb(rxq->pool[i].skb);
323 }
324 }
325
326 pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
327 rxq->dma_addr);
8d86422a
WT		 328 pci_free_consistent(priv->pci_dev, sizeof(struct iwl_rb_status),
329 rxq->rb_stts, rxq->rb_stts_dma);
a55360e4 330 rxq->bd = NULL;
8d86422a 331 rxq->rb_stts = NULL;
a55360e4
TW		 332}
333EXPORT_SYMBOL(iwl_rx_queue_free);
334
335int iwl_rx_queue_alloc(struct iwl_priv *priv)
336{
337 struct iwl_rx_queue *rxq = &priv->rxq;
338 struct pci_dev *dev = priv->pci_dev;
339 int i;
340
341 spin_lock_init(&rxq->lock);
342 INIT_LIST_HEAD(&rxq->rx_free);
343 INIT_LIST_HEAD(&rxq->rx_used);
344
345 /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
346 rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
347 if (!rxq->bd)
8d86422a
WT		 348 goto err_bd;
349
350 rxq->rb_stts = pci_alloc_consistent(dev, sizeof(struct iwl_rb_status),
351 &rxq->rb_stts_dma);
352 if (!rxq->rb_stts)
353 goto err_rb;
a55360e4
TW		 354
355 /* Fill the rx_used queue with _all_ of the Rx buffers */
356 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
357 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
358
359 /* Set us so that we have processed and used all buffers, but have
360 * not restocked the Rx queue with fresh buffers */
361 rxq->read = rxq->write = 0;
362 rxq->free_count = 0;
363 rxq->need_update = 0;
364 return 0;
8d86422a
WT		 365
366err_rb:
367 pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
368 rxq->dma_addr);
369err_bd:
370 return -ENOMEM;
a55360e4
TW		 371}
372EXPORT_SYMBOL(iwl_rx_queue_alloc);
373
374void iwl_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
375{
376 unsigned long flags;
377 int i;
378 spin_lock_irqsave(&rxq->lock, flags);
379 INIT_LIST_HEAD(&rxq->rx_free);
380 INIT_LIST_HEAD(&rxq->rx_used);
381 /* Fill the rx_used queue with _all_ of the Rx buffers */
382 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
383 /* In the reset function, these buffers may have been allocated
384 * to an SKB, so we need to unmap and free potential storage */
385 if (rxq->pool[i].skb != NULL) {
386 pci_unmap_single(priv->pci_dev,
4018517a
JB		 387 rxq->pool[i].real_dma_addr,
388 priv->hw_params.rx_buf_size + 256,
a55360e4
TW		 389 PCI_DMA_FROMDEVICE);
390 priv->alloc_rxb_skb--;
391 dev_kfree_skb(rxq->pool[i].skb);
392 rxq->pool[i].skb = NULL;
393 }
394 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
395 }
396
397 /* Set us so that we have processed and used all buffers, but have
398 * not restocked the Rx queue with fresh buffers */
399 rxq->read = rxq->write = 0;
400 rxq->free_count = 0;
401 spin_unlock_irqrestore(&rxq->lock, flags);
402}
403EXPORT_SYMBOL(iwl_rx_queue_reset);
404
1053d35f
RR		 405int iwl_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
406{
407 int ret;
408 unsigned long flags;
8cd519e8
WT		 409 u32 rb_size;
410 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
411 const u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT why this stalls RX */
1053d35f
RR		 412
413 spin_lock_irqsave(&priv->lock, flags);
414 ret = iwl_grab_nic_access(priv);
415 if (ret) {
416 spin_unlock_irqrestore(&priv->lock, flags);
417 return ret;
418 }
419
420 if (priv->cfg->mod_params->amsdu_size_8K)
421 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
422 else
423 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
424
425 /* Stop Rx DMA */
426 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
427
428 /* Reset driver's Rx queue write index */
429 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
430
431 /* Tell device where to find RBD circular buffer in DRAM */
432 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
8cd519e8 433 (u32)(rxq->dma_addr >> 8));
1053d35f
RR		 434
435 /* Tell device where in DRAM to update its Rx status */
436 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
8d86422a 437 rxq->rb_stts_dma >> 4);
1053d35f 438
8cd519e8 439 /* Enable Rx DMA
a96a27f9 440 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
8cd519e8
WT		 441 * the credit mechanism in 5000 HW RX FIFO
442 * Direct rx interrupts to hosts
443 * Rx buffer size 4 or 8k
444 * RB timeout 0x10
445 * 256 RBDs
446 */
1053d35f
RR		 447 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
448 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
8cd519e8 449 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
1053d35f 450 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
9f925938 451 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
8cd519e8
WT		 452 rb_size|
453 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
454 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
1053d35f
RR		 455
456 iwl_release_nic_access(priv);
8cd519e8
WT		 457
458 iwl_write32(priv, CSR_INT_COALESCING, 0x40);
459
1053d35f
RR		 460 spin_unlock_irqrestore(&priv->lock, flags);
461
462 return 0;
463}
464
b3bbacb7
TW		 465int iwl_rxq_stop(struct iwl_priv *priv)
466{
467 int ret;
468 unsigned long flags;
469
470 spin_lock_irqsave(&priv->lock, flags);
471 ret = iwl_grab_nic_access(priv);
472 if (unlikely(ret)) {
473 spin_unlock_irqrestore(&priv->lock, flags);
474 return ret;
475 }
476
477 /* stop Rx DMA */
478 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
73d7b5ac
ZY		 479 iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
480 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
b3bbacb7
TW		 481
482 iwl_release_nic_access(priv);
483 spin_unlock_irqrestore(&priv->lock, flags);
484
485 return 0;
486}
487EXPORT_SYMBOL(iwl_rxq_stop);
488
c1354754
TW		 489void iwl_rx_missed_beacon_notif(struct iwl_priv *priv,
490 struct iwl_rx_mem_buffer *rxb)
491
492{
c1354754 493 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2aa6ab86 494 struct iwl_missed_beacon_notif *missed_beacon;
c1354754
TW		 495
496 missed_beacon = &pkt->u.missed_beacon;
497 if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
498 IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
499 le32_to_cpu(missed_beacon->consequtive_missed_beacons),
500 le32_to_cpu(missed_beacon->total_missed_becons),
501 le32_to_cpu(missed_beacon->num_recvd_beacons),
502 le32_to_cpu(missed_beacon->num_expected_beacons));
503 if (!test_bit(STATUS_SCANNING, &priv->status))
504 iwl_init_sensitivity(priv);
505 }
c1354754
TW		 506}
507EXPORT_SYMBOL(iwl_rx_missed_beacon_notif);
8f91aecb
EG		 508
509
510/* Calculate noise level, based on measurements during network silence just
511 * before arriving beacon. This measurement can be done only if we know
512 * exactly when to expect beacons, therefore only when we're associated. */
513static void iwl_rx_calc_noise(struct iwl_priv *priv)
514{
515 struct statistics_rx_non_phy *rx_info
516 = &(priv->statistics.rx.general);
517 int num_active_rx = 0;
518 int total_silence = 0;
519 int bcn_silence_a =
520 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
521 int bcn_silence_b =
522 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
523 int bcn_silence_c =
524 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
525
526 if (bcn_silence_a) {
527 total_silence += bcn_silence_a;
528 num_active_rx++;
529 }
530 if (bcn_silence_b) {
531 total_silence += bcn_silence_b;
532 num_active_rx++;
533 }
534 if (bcn_silence_c) {
535 total_silence += bcn_silence_c;
536 num_active_rx++;
537 }
538
539 /* Average among active antennas */
540 if (num_active_rx)
541 priv->last_rx_noise = (total_silence / num_active_rx) - 107;
542 else
543 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
544
545 IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
546 bcn_silence_a, bcn_silence_b, bcn_silence_c,
547 priv->last_rx_noise);
548}
549
550#define REG_RECALIB_PERIOD (60)
551
552void iwl_rx_statistics(struct iwl_priv *priv,
553 struct iwl_rx_mem_buffer *rxb)
554{
5225640b 555 int change;
8f91aecb
EG		 556 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
557
558 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
559 (int)sizeof(priv->statistics), pkt->len);
560
5225640b
ZY		 561 change = ((priv->statistics.general.temperature !=
562 pkt->u.stats.general.temperature) ||
563 ((priv->statistics.flag &
564 STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
565 (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
566
8f91aecb
EG		 567 memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
568
569 set_bit(STATUS_STATISTICS, &priv->status);
570
571 /* Reschedule the statistics timer to occur in
572 * REG_RECALIB_PERIOD seconds to ensure we get a
573 * thermal update even if the uCode doesn't give
574 * us one */
575 mod_timer(&priv->statistics_periodic, jiffies +
576 msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
577
578 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
579 (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
580 iwl_rx_calc_noise(priv);
581 queue_work(priv->workqueue, &priv->run_time_calib_work);
582 }
583
584 iwl_leds_background(priv);
585
5225640b
ZY		 586 if (priv->cfg->ops->lib->temperature && change)
587 priv->cfg->ops->lib->temperature(priv);
8f91aecb
EG		 588}
589EXPORT_SYMBOL(iwl_rx_statistics);
1781a07f
EG		 590
591#define PERFECT_RSSI (-20) /* dBm */
592#define WORST_RSSI (-95) /* dBm */
593#define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
594
595/* Calculate an indication of rx signal quality (a percentage, not dBm!).
596 * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
597 * about formulas used below. */
598static int iwl_calc_sig_qual(int rssi_dbm, int noise_dbm)
599{
600 int sig_qual;
601 int degradation = PERFECT_RSSI - rssi_dbm;
602
603 /* If we get a noise measurement, use signal-to-noise ratio (SNR)
604 * as indicator; formula is (signal dbm - noise dbm).
605 * SNR at or above 40 is a great signal (100%).
606 * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
607 * Weakest usable signal is usually 10 - 15 dB SNR. */
608 if (noise_dbm) {
609 if (rssi_dbm - noise_dbm >= 40)
610 return 100;
611 else if (rssi_dbm < noise_dbm)
612 return 0;
613 sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
614
615 /* Else use just the signal level.
616 * This formula is a least squares fit of data points collected and
617 * compared with a reference system that had a percentage (%) display
618 * for signal quality. */
619 } else
620 sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
621 (15 * RSSI_RANGE + 62 * degradation)) /
622 (RSSI_RANGE * RSSI_RANGE);
623
624 if (sig_qual > 100)
625 sig_qual = 100;
626 else if (sig_qual < 1)
627 sig_qual = 0;
628
629 return sig_qual;
630}
631
00e540b3
HD		 632/* Calc max signal level (dBm) among 3 possible receivers */
633static inline int iwl_calc_rssi(struct iwl_priv *priv,
634 struct iwl_rx_phy_res *rx_resp)
635{
636 return priv->cfg->ops->utils->calc_rssi(priv, rx_resp);
637}
1781a07f 638
00e540b3 639#ifdef CONFIG_IWLWIFI_DEBUG
1781a07f
EG		 640/**
641 * iwl_dbg_report_frame - dump frame to syslog during debug sessions
642 *
643 * You may hack this function to show different aspects of received frames,
644 * including selective frame dumps.
00e540b3
HD		 645 * group100 parameter selects whether to show 1 out of 100 good data frames.
646 * All beacon and probe response frames are printed.
1781a07f
EG		 647 */
648static void iwl_dbg_report_frame(struct iwl_priv *priv,
00e540b3 649 struct iwl_rx_phy_res *phy_res, u16 length,
1781a07f
EG		 650 struct ieee80211_hdr *header, int group100)
651{
652 u32 to_us;
653 u32 print_summary = 0;
654 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
655 u32 hundred = 0;
656 u32 dataframe = 0;
657 __le16 fc;
658 u16 seq_ctl;
659 u16 channel;
660 u16 phy_flags;
00e540b3 661 u32 rate_n_flags;
1781a07f 662 u32 tsf_low;
00e540b3 663 int rssi;
1781a07f
EG		 664
665 if (likely(!(priv->debug_level & IWL_DL_RX)))
666 return;
667
668 /* MAC header */
669 fc = header->frame_control;
670 seq_ctl = le16_to_cpu(header->seq_ctrl);
671
672 /* metadata */
00e540b3
HD		 673 channel = le16_to_cpu(phy_res->channel);
674 phy_flags = le16_to_cpu(phy_res->phy_flags);
675 rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
1781a07f
EG		 676
677 /* signal statistics */
00e540b3
HD		 678 rssi = iwl_calc_rssi(priv, phy_res);
679 tsf_low = le64_to_cpu(phy_res->timestamp) & 0x0ffffffff;
1781a07f
EG		 680
681 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
682
683 /* if data frame is to us and all is good,
684 * (optionally) print summary for only 1 out of every 100 */
685 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
686 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
687 dataframe = 1;
688 if (!group100)
689 print_summary = 1; /* print each frame */
690 else if (priv->framecnt_to_us < 100) {
691 priv->framecnt_to_us++;
692 print_summary = 0;
693 } else {
694 priv->framecnt_to_us = 0;
695 print_summary = 1;
696 hundred = 1;
697 }
698 } else {
699 /* print summary for all other frames */
700 print_summary = 1;
701 }
702
703 if (print_summary) {
704 char *title;
705 int rate_idx;
706 u32 bitrate;
707
708 if (hundred)
709 title = "100Frames";
710 else if (ieee80211_has_retry(fc))
711 title = "Retry";
712 else if (ieee80211_is_assoc_resp(fc))
713 title = "AscRsp";
714 else if (ieee80211_is_reassoc_resp(fc))
715 title = "RasRsp";
716 else if (ieee80211_is_probe_resp(fc)) {
717 title = "PrbRsp";
718 print_dump = 1; /* dump frame contents */
719 } else if (ieee80211_is_beacon(fc)) {
720 title = "Beacon";
721 print_dump = 1; /* dump frame contents */
722 } else if (ieee80211_is_atim(fc))
723 title = "ATIM";
724 else if (ieee80211_is_auth(fc))
725 title = "Auth";
726 else if (ieee80211_is_deauth(fc))
727 title = "DeAuth";
728 else if (ieee80211_is_disassoc(fc))
729 title = "DisAssoc";
730 else
731 title = "Frame";
732
00e540b3
HD		 733 rate_idx = iwl_hwrate_to_plcp_idx(rate_n_flags);
734 if (unlikely((rate_idx < 0) || (rate_idx >= IWL_RATE_COUNT))) {
1781a07f 735 bitrate = 0;
00e540b3
HD		 736 WARN_ON_ONCE(1);
737 } else {
1781a07f 738 bitrate = iwl_rates[rate_idx].ieee / 2;
00e540b3 739 }
1781a07f
EG		 740
741 /* print frame summary.
742 * MAC addresses show just the last byte (for brevity),
743 * but you can hack it to show more, if you'd like to. */
744 if (dataframe)
745 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
746 "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
747 title, le16_to_cpu(fc), header->addr1[5],
748 length, rssi, channel, bitrate);
749 else {
750 /* src/dst addresses assume managed mode */
00e540b3
HD		 751 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, src=0x%02x, "
752 "len=%u, rssi=%d, tim=%lu usec, "
1781a07f
EG		 753 "phy=0x%02x, chnl=%d\n",
754 title, le16_to_cpu(fc), header->addr1[5],
00e540b3 755 header->addr3[5], length, rssi,
1781a07f
EG		 756 tsf_low - priv->scan_start_tsf,
757 phy_flags, channel);
758 }
759 }
760 if (print_dump)
00e540b3 761 iwl_print_hex_dump(priv, IWL_DL_RX, header, length);
1781a07f 762}
1781a07f
EG		 763#endif
764
1781a07f
EG		 765static void iwl_update_rx_stats(struct iwl_priv *priv, u16 fc, u16 len)
766{
767 /* 0 - mgmt, 1 - cnt, 2 - data */
768 int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
769 priv->rx_stats[idx].cnt++;
770 priv->rx_stats[idx].bytes += len;
771}
772
773/*
774 * returns non-zero if packet should be dropped
775 */
776static int iwl_set_decrypted_flag(struct iwl_priv *priv,
777 struct ieee80211_hdr *hdr,
778 u32 decrypt_res,
779 struct ieee80211_rx_status *stats)
780{
781 u16 fc = le16_to_cpu(hdr->frame_control);
782
783 if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
784 return 0;
785
786 if (!(fc & IEEE80211_FCTL_PROTECTED))
787 return 0;
788
789 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
790 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
791 case RX_RES_STATUS_SEC_TYPE_TKIP:
792 /* The uCode has got a bad phase 1 Key, pushes the packet.
793 * Decryption will be done in SW. */
794 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
795 RX_RES_STATUS_BAD_KEY_TTAK)
796 break;
797
798 case RX_RES_STATUS_SEC_TYPE_WEP:
799 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
800 RX_RES_STATUS_BAD_ICV_MIC) {
801 /* bad ICV, the packet is destroyed since the
802 * decryption is inplace, drop it */
803 IWL_DEBUG_RX("Packet destroyed\n");
804 return -1;
805 }
806 case RX_RES_STATUS_SEC_TYPE_CCMP:
807 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
808 RX_RES_STATUS_DECRYPT_OK) {
809 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
810 stats->flag |= RX_FLAG_DECRYPTED;
811 }
812 break;
813
814 default:
815 break;
816 }
817 return 0;
818}
819
820static u32 iwl_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
821{
822 u32 decrypt_out = 0;
823
824 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
825 RX_RES_STATUS_STATION_FOUND)
826 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
827 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
828
829 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
830
831 /* packet was not encrypted */
832 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
833 RX_RES_STATUS_SEC_TYPE_NONE)
834 return decrypt_out;
835
836 /* packet was encrypted with unknown alg */
837 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
838 RX_RES_STATUS_SEC_TYPE_ERR)
839 return decrypt_out;
840
841 /* decryption was not done in HW */
842 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
843 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
844 return decrypt_out;
845
846 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
847
848 case RX_RES_STATUS_SEC_TYPE_CCMP:
849 /* alg is CCM: check MIC only */
850 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
851 /* Bad MIC */
852 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
853 else
854 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
855
856 break;
857
858 case RX_RES_STATUS_SEC_TYPE_TKIP:
859 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
860 /* Bad TTAK */
861 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
862 break;
863 }
864 /* fall through if TTAK OK */
865 default:
866 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
867 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
868 else
869 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
870 break;
871 };
872
873 IWL_DEBUG_RX("decrypt_in:0x%x decrypt_out = 0x%x\n",
874 decrypt_in, decrypt_out);
875
876 return decrypt_out;
877}
878
4b8817b2 879static void iwl_pass_packet_to_mac80211(struct iwl_priv *priv,
1781a07f
EG		 880 int include_phy,
881 struct iwl_rx_mem_buffer *rxb,
882 struct ieee80211_rx_status *stats)
883{
884 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
caab8f1a
TW		 885 struct iwl_rx_phy_res *rx_start = (include_phy) ?
886 (struct iwl_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
1781a07f
EG		 887 struct ieee80211_hdr *hdr;
888 u16 len;
889 __le32 *rx_end;
890 unsigned int skblen;
891 u32 ampdu_status;
892 u32 ampdu_status_legacy;
893
894 if (!include_phy && priv->last_phy_res[0])
caab8f1a 895 rx_start = (struct iwl_rx_phy_res *)&priv->last_phy_res[1];
1781a07f
EG		 896
897 if (!rx_start) {
898 IWL_ERROR("MPDU frame without a PHY data\n");
899 return;
900 }
901 if (include_phy) {
902 hdr = (struct ieee80211_hdr *)((u8 *) &rx_start[1] +
903 rx_start->cfg_phy_cnt);
904
905 len = le16_to_cpu(rx_start->byte_count);
906
caab8f1a
TW		 907 rx_end = (__le32 *)((u8 *) &pkt->u.raw[0] +
908 sizeof(struct iwl_rx_phy_res) +
1781a07f
EG		 909 rx_start->cfg_phy_cnt + len);
910
911 } else {
912 struct iwl4965_rx_mpdu_res_start *amsdu =
913 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
914
915 hdr = (struct ieee80211_hdr *)(pkt->u.raw +
916 sizeof(struct iwl4965_rx_mpdu_res_start));
917 len = le16_to_cpu(amsdu->byte_count);
918 rx_start->byte_count = amsdu->byte_count;
919 rx_end = (__le32 *) (((u8 *) hdr) + len);
920 }
1781a07f
EG		 921
922 ampdu_status = le32_to_cpu(*rx_end);
923 skblen = ((u8 *) rx_end - (u8 *) &pkt->u.raw[0]) + sizeof(u32);
924
925 if (!include_phy) {
926 /* New status scheme, need to translate */
927 ampdu_status_legacy = ampdu_status;
928 ampdu_status = iwl_translate_rx_status(priv, ampdu_status);
929 }
930
931 /* start from MAC */
932 skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
933 skb_put(rxb->skb, len); /* end where data ends */
934
935 /* We only process data packets if the interface is open */
936 if (unlikely(!priv->is_open)) {
937 IWL_DEBUG_DROP_LIMIT
938 ("Dropping packet while interface is not open.\n");
939 return;
940 }
941
1781a07f
EG		 942 hdr = (struct ieee80211_hdr *)rxb->skb->data;
943
944 /* in case of HW accelerated crypto and bad decryption, drop */
945 if (!priv->hw_params.sw_crypto &&
946 iwl_set_decrypted_flag(priv, hdr, ampdu_status, stats))
947 return;
948
1781a07f
EG		 949 iwl_update_rx_stats(priv, le16_to_cpu(hdr->frame_control), len);
950 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
951 priv->alloc_rxb_skb--;
952 rxb->skb = NULL;
953}
954
4b8817b2 955/* This is necessary only for a number of statistics, see the caller. */
1781a07f
EG		 956static int iwl_is_network_packet(struct iwl_priv *priv,
957 struct ieee80211_hdr *header)
958{
959 /* Filter incoming packets to determine if they are targeted toward
960 * this network, discarding packets coming from ourselves */
961 switch (priv->iw_mode) {
05c914fe 962 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
4b8817b2
EG		 963 /* packets to our IBSS update information */
964 return !compare_ether_addr(header->addr3, priv->bssid);
05c914fe 965 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
4b8817b2
EG		 966 /* packets to our IBSS update information */
967 return !compare_ether_addr(header->addr2, priv->bssid);
1781a07f 968 default:
4b8817b2 969 return 1;
1781a07f 970 }
1781a07f
EG		 971}
972
973/* Called for REPLY_RX (legacy ABG frames), or
974 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
975void iwl_rx_reply_rx(struct iwl_priv *priv,
976 struct iwl_rx_mem_buffer *rxb)
977{
978 struct ieee80211_hdr *header;
979 struct ieee80211_rx_status rx_status;
980 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
981 /* Use phy data (Rx signal strength, etc.) contained within
982 * this rx packet for legacy frames,
983 * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
984 int include_phy = (pkt->hdr.cmd == REPLY_RX);
caab8f1a
TW		 985 struct iwl_rx_phy_res *rx_start = (include_phy) ?
986 (struct iwl_rx_phy_res *)&(pkt->u.raw[0]) :
987 (struct iwl_rx_phy_res *)&priv->last_phy_res[1];
1781a07f
EG		 988 __le32 *rx_end;
989 unsigned int len = 0;
990 u16 fc;
991 u8 network_packet;
992
993 rx_status.mactime = le64_to_cpu(rx_start->timestamp);
994 rx_status.freq =
995 ieee80211_channel_to_frequency(le16_to_cpu(rx_start->channel));
996 rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
997 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
998 rx_status.rate_idx =
999 iwl_hwrate_to_plcp_idx(le32_to_cpu(rx_start->rate_n_flags));
1000 if (rx_status.band == IEEE80211_BAND_5GHZ)
1001 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
1002
1781a07f 1003 rx_status.flag = 0;
b94d8eea
AK		 1004
1005 /* TSF isn't reliable. In order to allow smooth user experience,
1006 * this W/A doesn't propagate it to the mac80211 */
1007 /*rx_status.flag |= RX_FLAG_TSFT;*/
1781a07f
EG		 1008
1009 if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
1010 IWL_DEBUG_DROP("dsp size out of range [0,20]: %d/n",
1011 rx_start->cfg_phy_cnt);
1012 return;
1013 }
1014
1015 if (!include_phy) {
1016 if (priv->last_phy_res[0])
caab8f1a 1017 rx_start = (struct iwl_rx_phy_res *)
1781a07f
EG		 1018 &priv->last_phy_res[1];
1019 else
1020 rx_start = NULL;
1021 }
1022
1023 if (!rx_start) {
1024 IWL_ERROR("MPDU frame without a PHY data\n");
1025 return;
1026 }
1027
1028 if (include_phy) {
1029 header = (struct ieee80211_hdr *)((u8 *) &rx_start[1]
1030 + rx_start->cfg_phy_cnt);
1031
1032 len = le16_to_cpu(rx_start->byte_count);
1033 rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt +
caab8f1a 1034 sizeof(struct iwl_rx_phy_res) + len);
1781a07f
EG		 1035 } else {
1036 struct iwl4965_rx_mpdu_res_start *amsdu =
1037 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
1038
1039 header = (void *)(pkt->u.raw +
1040 sizeof(struct iwl4965_rx_mpdu_res_start));
1041 len = le16_to_cpu(amsdu->byte_count);
1042 rx_end = (__le32 *) (pkt->u.raw +
1043 sizeof(struct iwl4965_rx_mpdu_res_start) + len);
1044 }
1045
1046 if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
1047 !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
1048 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
1049 le32_to_cpu(*rx_end));
1050 return;
1051 }
1052
1053 priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
1054
1055 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
1056 rx_status.signal = iwl_calc_rssi(priv, rx_start);
1057
1058 /* Meaningful noise values are available only from beacon statistics,
1059 * which are gathered only when associated, and indicate noise
1060 * only for the associated network channel ...
1061 * Ignore these noise values while scanning (other channels) */
1062 if (iwl_is_associated(priv) &&
1063 !test_bit(STATUS_SCANNING, &priv->status)) {
1064 rx_status.noise = priv->last_rx_noise;
1065 rx_status.qual = iwl_calc_sig_qual(rx_status.signal,
1066 rx_status.noise);
1067 } else {
1068 rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
1069 rx_status.qual = iwl_calc_sig_qual(rx_status.signal, 0);
1070 }
1071
1072 /* Reset beacon noise level if not associated. */
1073 if (!iwl_is_associated(priv))
1074 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
1075
1076 /* Set "1" to report good data frames in groups of 100 */
21a49fc6 1077#ifdef CONFIG_IWLWIFI_DEBUG
00e540b3
HD		 1078 if (unlikely(priv->debug_level & IWL_DL_RX))
1079 iwl_dbg_report_frame(priv, rx_start, len, header, 1);
21a49fc6 1080#endif
1781a07f
EG		 1081 IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n",
1082 rx_status.signal, rx_status.noise, rx_status.signal,
1083 (unsigned long long)rx_status.mactime);
1084
6f0a2c4d
BR		 1085 /*
1086 * "antenna number"
1087 *
1088 * It seems that the antenna field in the phy flags value
a96a27f9 1089 * is actually a bit field. This is undefined by radiotap,
6f0a2c4d
BR		 1090 * it wants an actual antenna number but I always get "7"
1091 * for most legacy frames I receive indicating that the
1092 * same frame was received on all three RX chains.
1093 *
a96a27f9 1094 * I think this field should be removed in favor of a
6f0a2c4d
BR		 1095 * new 802.11n radiotap field "RX chains" that is defined
1096 * as a bitmask.
1097 */
1098 rx_status.antenna = le16_to_cpu(rx_start->phy_flags &
1099 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
1100
1101 /* set the preamble flag if appropriate */
1102 if (rx_start->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
1103 rx_status.flag |= RX_FLAG_SHORTPRE;
1104
4b8817b2 1105 /* Take shortcut when only in monitor mode */
05c914fe 1106 if (priv->iw_mode == NL80211_IFTYPE_MONITOR) {
4b8817b2 1107 iwl_pass_packet_to_mac80211(priv, include_phy,
1781a07f
EG		 1108 rxb, &rx_status);
1109 return;
1110 }
1111
1112 network_packet = iwl_is_network_packet(priv, header);
1113 if (network_packet) {
1114 priv->last_rx_rssi = rx_status.signal;
1115 priv->last_beacon_time = priv->ucode_beacon_time;
1116 priv->last_tsf = le64_to_cpu(rx_start->timestamp);
1117 }
1118
1119 fc = le16_to_cpu(header->frame_control);
1120 switch (fc & IEEE80211_FCTL_FTYPE) {
1121 case IEEE80211_FTYPE_MGMT:
4b8817b2 1122 case IEEE80211_FTYPE_DATA:
05c914fe 1123 if (priv->iw_mode == NL80211_IFTYPE_AP)
1781a07f
EG		 1124 iwl_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
1125 header->addr2);
4b8817b2 1126 /* fall through */
1781a07f 1127 default:
4b8817b2
EG		 1128 iwl_pass_packet_to_mac80211(priv, include_phy, rxb,
1129 &rx_status);
1781a07f
EG		 1130 break;
1131
1132 }
1133}
1134EXPORT_SYMBOL(iwl_rx_reply_rx);
1135
1136/* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
1137 * This will be used later in iwl_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
1138void iwl_rx_reply_rx_phy(struct iwl_priv *priv,
1139 struct iwl_rx_mem_buffer *rxb)
1140{
1141 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1142 priv->last_phy_res[0] = 1;
1143 memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
caab8f1a 1144 sizeof(struct iwl_rx_phy_res));
1781a07f
EG		 1145}
1146EXPORT_SYMBOL(iwl_rx_reply_rx_phy);
Linux kernel - Deliverables
This page took 0.184562 seconds and 5 git commands to generate.