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a55360e4 TW |
1 | /****************************************************************************** |
2 | * | |
01f8162a | 3 | * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved. |
a55360e4 TW |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
a55360e4 TW |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
1781a07f | 30 | #include <linux/etherdevice.h> |
a55360e4 | 31 | #include <net/mac80211.h> |
a05ffd39 | 32 | #include <asm/unaligned.h> |
a55360e4 TW |
33 | #include "iwl-eeprom.h" |
34 | #include "iwl-dev.h" | |
35 | #include "iwl-core.h" | |
36 | #include "iwl-sta.h" | |
37 | #include "iwl-io.h" | |
c1354754 | 38 | #include "iwl-calib.h" |
a55360e4 TW |
39 | #include "iwl-helpers.h" |
40 | /************************** RX-FUNCTIONS ****************************/ | |
41 | /* | |
42 | * Rx theory of operation | |
43 | * | |
44 | * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs), | |
45 | * each of which point to Receive Buffers to be filled by the NIC. These get | |
46 | * used not only for Rx frames, but for any command response or notification | |
47 | * from the NIC. The driver and NIC manage the Rx buffers by means | |
48 | * of indexes into the circular buffer. | |
49 | * | |
50 | * Rx Queue Indexes | |
51 | * The host/firmware share two index registers for managing the Rx buffers. | |
52 | * | |
53 | * The READ index maps to the first position that the firmware may be writing | |
54 | * to -- the driver can read up to (but not including) this position and get | |
55 | * good data. | |
56 | * The READ index is managed by the firmware once the card is enabled. | |
57 | * | |
58 | * The WRITE index maps to the last position the driver has read from -- the | |
59 | * position preceding WRITE is the last slot the firmware can place a packet. | |
60 | * | |
61 | * The queue is empty (no good data) if WRITE = READ - 1, and is full if | |
62 | * WRITE = READ. | |
63 | * | |
64 | * During initialization, the host sets up the READ queue position to the first | |
65 | * INDEX position, and WRITE to the last (READ - 1 wrapped) | |
66 | * | |
67 | * When the firmware places a packet in a buffer, it will advance the READ index | |
68 | * and fire the RX interrupt. The driver can then query the READ index and | |
69 | * process as many packets as possible, moving the WRITE index forward as it | |
70 | * resets the Rx queue buffers with new memory. | |
71 | * | |
72 | * The management in the driver is as follows: | |
73 | * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When | |
74 | * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled | |
75 | * to replenish the iwl->rxq->rx_free. | |
76 | * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the | |
77 | * iwl->rxq is replenished and the READ INDEX is updated (updating the | |
78 | * 'processed' and 'read' driver indexes as well) | |
79 | * + A received packet is processed and handed to the kernel network stack, | |
80 | * detached from the iwl->rxq. The driver 'processed' index is updated. | |
81 | * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free | |
82 | * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ | |
83 | * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there | |
84 | * were enough free buffers and RX_STALLED is set it is cleared. | |
85 | * | |
86 | * | |
87 | * Driver sequence: | |
88 | * | |
89 | * iwl_rx_queue_alloc() Allocates rx_free | |
90 | * iwl_rx_replenish() Replenishes rx_free list from rx_used, and calls | |
91 | * iwl_rx_queue_restock | |
92 | * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx | |
93 | * queue, updates firmware pointers, and updates | |
94 | * the WRITE index. If insufficient rx_free buffers | |
95 | * are available, schedules iwl_rx_replenish | |
96 | * | |
97 | * -- enable interrupts -- | |
98 | * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the | |
99 | * READ INDEX, detaching the SKB from the pool. | |
100 | * Moves the packet buffer from queue to rx_used. | |
101 | * Calls iwl_rx_queue_restock to refill any empty | |
102 | * slots. | |
103 | * ... | |
104 | * | |
105 | */ | |
106 | ||
107 | /** | |
108 | * iwl_rx_queue_space - Return number of free slots available in queue. | |
109 | */ | |
110 | int iwl_rx_queue_space(const struct iwl_rx_queue *q) | |
111 | { | |
112 | int s = q->read - q->write; | |
113 | if (s <= 0) | |
114 | s += RX_QUEUE_SIZE; | |
115 | /* keep some buffer to not confuse full and empty queue */ | |
116 | s -= 2; | |
117 | if (s < 0) | |
118 | s = 0; | |
119 | return s; | |
120 | } | |
121 | EXPORT_SYMBOL(iwl_rx_queue_space); | |
122 | ||
123 | /** | |
124 | * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue | |
125 | */ | |
126 | int iwl_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue *q) | |
127 | { | |
a55360e4 | 128 | unsigned long flags; |
141c43a3 WT |
129 | u32 rx_wrt_ptr_reg = priv->hw_params.rx_wrt_ptr_reg; |
130 | u32 reg; | |
131 | int ret = 0; | |
a55360e4 TW |
132 | |
133 | spin_lock_irqsave(&q->lock, flags); | |
134 | ||
135 | if (q->need_update == 0) | |
136 | goto exit_unlock; | |
137 | ||
138 | /* If power-saving is in use, make sure device is awake */ | |
139 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { | |
140 | reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); | |
141 | ||
142 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
143 | iwl_set_bit(priv, CSR_GP_CNTRL, | |
144 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
145 | goto exit_unlock; | |
146 | } | |
147 | ||
4752c93c MA |
148 | q->write_actual = (q->write & ~0x7); |
149 | iwl_write_direct32(priv, rx_wrt_ptr_reg, q->write_actual); | |
a55360e4 TW |
150 | |
151 | /* Else device is assumed to be awake */ | |
141c43a3 | 152 | } else { |
a55360e4 | 153 | /* Device expects a multiple of 8 */ |
4752c93c MA |
154 | q->write_actual = (q->write & ~0x7); |
155 | iwl_write_direct32(priv, rx_wrt_ptr_reg, q->write_actual); | |
141c43a3 | 156 | } |
a55360e4 TW |
157 | |
158 | q->need_update = 0; | |
159 | ||
160 | exit_unlock: | |
161 | spin_unlock_irqrestore(&q->lock, flags); | |
162 | return ret; | |
163 | } | |
164 | EXPORT_SYMBOL(iwl_rx_queue_update_write_ptr); | |
165 | /** | |
166 | * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr | |
167 | */ | |
168 | static inline __le32 iwl_dma_addr2rbd_ptr(struct iwl_priv *priv, | |
169 | dma_addr_t dma_addr) | |
170 | { | |
171 | return cpu_to_le32((u32)(dma_addr >> 8)); | |
172 | } | |
173 | ||
174 | /** | |
175 | * iwl_rx_queue_restock - refill RX queue from pre-allocated pool | |
176 | * | |
177 | * If there are slots in the RX queue that need to be restocked, | |
178 | * and we have free pre-allocated buffers, fill the ranks as much | |
179 | * as we can, pulling from rx_free. | |
180 | * | |
181 | * This moves the 'write' index forward to catch up with 'processed', and | |
182 | * also updates the memory address in the firmware to reference the new | |
183 | * target buffer. | |
184 | */ | |
185 | int iwl_rx_queue_restock(struct iwl_priv *priv) | |
186 | { | |
187 | struct iwl_rx_queue *rxq = &priv->rxq; | |
188 | struct list_head *element; | |
189 | struct iwl_rx_mem_buffer *rxb; | |
190 | unsigned long flags; | |
191 | int write; | |
192 | int ret = 0; | |
193 | ||
194 | spin_lock_irqsave(&rxq->lock, flags); | |
195 | write = rxq->write & ~0x7; | |
196 | while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) { | |
197 | /* Get next free Rx buffer, remove from free list */ | |
198 | element = rxq->rx_free.next; | |
199 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); | |
200 | list_del(element); | |
201 | ||
202 | /* Point to Rx buffer via next RBD in circular buffer */ | |
4018517a | 203 | rxq->bd[rxq->write] = iwl_dma_addr2rbd_ptr(priv, rxb->aligned_dma_addr); |
a55360e4 TW |
204 | rxq->queue[rxq->write] = rxb; |
205 | rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; | |
206 | rxq->free_count--; | |
207 | } | |
208 | spin_unlock_irqrestore(&rxq->lock, flags); | |
209 | /* If the pre-allocated buffer pool is dropping low, schedule to | |
210 | * refill it */ | |
211 | if (rxq->free_count <= RX_LOW_WATERMARK) | |
212 | queue_work(priv->workqueue, &priv->rx_replenish); | |
213 | ||
214 | ||
215 | /* If we've added more space for the firmware to place data, tell it. | |
216 | * Increment device's write pointer in multiples of 8. */ | |
4752c93c | 217 | if (rxq->write_actual != (rxq->write & ~0x7)) { |
a55360e4 TW |
218 | spin_lock_irqsave(&rxq->lock, flags); |
219 | rxq->need_update = 1; | |
220 | spin_unlock_irqrestore(&rxq->lock, flags); | |
221 | ret = iwl_rx_queue_update_write_ptr(priv, rxq); | |
222 | } | |
223 | ||
224 | return ret; | |
225 | } | |
226 | EXPORT_SYMBOL(iwl_rx_queue_restock); | |
227 | ||
228 | ||
229 | /** | |
230 | * iwl_rx_replenish - Move all used packet from rx_used to rx_free | |
231 | * | |
232 | * When moving to rx_free an SKB is allocated for the slot. | |
233 | * | |
234 | * Also restock the Rx queue via iwl_rx_queue_restock. | |
235 | * This is called as a scheduled work item (except for during initialization) | |
236 | */ | |
4752c93c | 237 | void iwl_rx_allocate(struct iwl_priv *priv, gfp_t priority) |
a55360e4 TW |
238 | { |
239 | struct iwl_rx_queue *rxq = &priv->rxq; | |
240 | struct list_head *element; | |
241 | struct iwl_rx_mem_buffer *rxb; | |
242 | unsigned long flags; | |
f1bc4ac6 ZY |
243 | |
244 | while (1) { | |
245 | spin_lock_irqsave(&rxq->lock, flags); | |
246 | ||
247 | if (list_empty(&rxq->rx_used)) { | |
248 | spin_unlock_irqrestore(&rxq->lock, flags); | |
249 | return; | |
250 | } | |
a55360e4 TW |
251 | element = rxq->rx_used.next; |
252 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); | |
f1bc4ac6 ZY |
253 | list_del(element); |
254 | ||
255 | spin_unlock_irqrestore(&rxq->lock, flags); | |
a55360e4 TW |
256 | |
257 | /* Alloc a new receive buffer */ | |
4018517a | 258 | rxb->skb = alloc_skb(priv->hw_params.rx_buf_size + 256, |
4752c93c MA |
259 | priority); |
260 | ||
a55360e4 | 261 | if (!rxb->skb) { |
978785a3 | 262 | IWL_CRIT(priv, "Can not allocate SKB buffers\n"); |
a55360e4 TW |
263 | /* We don't reschedule replenish work here -- we will |
264 | * call the restock method and if it still needs | |
265 | * more buffers it will schedule replenish */ | |
266 | break; | |
267 | } | |
a55360e4 TW |
268 | |
269 | /* Get physical address of RB/SKB */ | |
4018517a JB |
270 | rxb->real_dma_addr = pci_map_single( |
271 | priv->pci_dev, | |
272 | rxb->skb->data, | |
273 | priv->hw_params.rx_buf_size + 256, | |
274 | PCI_DMA_FROMDEVICE); | |
275 | /* dma address must be no more than 36 bits */ | |
276 | BUG_ON(rxb->real_dma_addr & ~DMA_BIT_MASK(36)); | |
277 | /* and also 256 byte aligned! */ | |
278 | rxb->aligned_dma_addr = ALIGN(rxb->real_dma_addr, 256); | |
279 | skb_reserve(rxb->skb, rxb->aligned_dma_addr - rxb->real_dma_addr); | |
280 | ||
f1bc4ac6 ZY |
281 | spin_lock_irqsave(&rxq->lock, flags); |
282 | ||
a55360e4 TW |
283 | list_add_tail(&rxb->list, &rxq->rx_free); |
284 | rxq->free_count++; | |
f1bc4ac6 ZY |
285 | priv->alloc_rxb_skb++; |
286 | ||
287 | spin_unlock_irqrestore(&rxq->lock, flags); | |
a55360e4 | 288 | } |
a55360e4 | 289 | } |
a55360e4 TW |
290 | |
291 | void iwl_rx_replenish(struct iwl_priv *priv) | |
292 | { | |
293 | unsigned long flags; | |
294 | ||
4752c93c | 295 | iwl_rx_allocate(priv, GFP_KERNEL); |
a55360e4 TW |
296 | |
297 | spin_lock_irqsave(&priv->lock, flags); | |
298 | iwl_rx_queue_restock(priv); | |
299 | spin_unlock_irqrestore(&priv->lock, flags); | |
300 | } | |
301 | EXPORT_SYMBOL(iwl_rx_replenish); | |
302 | ||
4752c93c MA |
303 | void iwl_rx_replenish_now(struct iwl_priv *priv) |
304 | { | |
305 | iwl_rx_allocate(priv, GFP_ATOMIC); | |
306 | ||
307 | iwl_rx_queue_restock(priv); | |
308 | } | |
309 | EXPORT_SYMBOL(iwl_rx_replenish_now); | |
310 | ||
a55360e4 TW |
311 | |
312 | /* Assumes that the skb field of the buffers in 'pool' is kept accurate. | |
313 | * If an SKB has been detached, the POOL needs to have its SKB set to NULL | |
314 | * This free routine walks the list of POOL entries and if SKB is set to | |
315 | * non NULL it is unmapped and freed | |
316 | */ | |
317 | void iwl_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq) | |
318 | { | |
319 | int i; | |
320 | for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) { | |
321 | if (rxq->pool[i].skb != NULL) { | |
322 | pci_unmap_single(priv->pci_dev, | |
4018517a JB |
323 | rxq->pool[i].real_dma_addr, |
324 | priv->hw_params.rx_buf_size + 256, | |
a55360e4 TW |
325 | PCI_DMA_FROMDEVICE); |
326 | dev_kfree_skb(rxq->pool[i].skb); | |
327 | } | |
328 | } | |
329 | ||
330 | pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd, | |
331 | rxq->dma_addr); | |
8d86422a WT |
332 | pci_free_consistent(priv->pci_dev, sizeof(struct iwl_rb_status), |
333 | rxq->rb_stts, rxq->rb_stts_dma); | |
a55360e4 | 334 | rxq->bd = NULL; |
8d86422a | 335 | rxq->rb_stts = NULL; |
a55360e4 TW |
336 | } |
337 | EXPORT_SYMBOL(iwl_rx_queue_free); | |
338 | ||
339 | int iwl_rx_queue_alloc(struct iwl_priv *priv) | |
340 | { | |
341 | struct iwl_rx_queue *rxq = &priv->rxq; | |
342 | struct pci_dev *dev = priv->pci_dev; | |
343 | int i; | |
344 | ||
345 | spin_lock_init(&rxq->lock); | |
346 | INIT_LIST_HEAD(&rxq->rx_free); | |
347 | INIT_LIST_HEAD(&rxq->rx_used); | |
348 | ||
349 | /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */ | |
350 | rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr); | |
351 | if (!rxq->bd) | |
8d86422a WT |
352 | goto err_bd; |
353 | ||
354 | rxq->rb_stts = pci_alloc_consistent(dev, sizeof(struct iwl_rb_status), | |
355 | &rxq->rb_stts_dma); | |
356 | if (!rxq->rb_stts) | |
357 | goto err_rb; | |
a55360e4 TW |
358 | |
359 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
360 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) | |
361 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
362 | ||
363 | /* Set us so that we have processed and used all buffers, but have | |
364 | * not restocked the Rx queue with fresh buffers */ | |
365 | rxq->read = rxq->write = 0; | |
4752c93c | 366 | rxq->write_actual = 0; |
a55360e4 TW |
367 | rxq->free_count = 0; |
368 | rxq->need_update = 0; | |
369 | return 0; | |
8d86422a WT |
370 | |
371 | err_rb: | |
372 | pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd, | |
373 | rxq->dma_addr); | |
374 | err_bd: | |
375 | return -ENOMEM; | |
a55360e4 TW |
376 | } |
377 | EXPORT_SYMBOL(iwl_rx_queue_alloc); | |
378 | ||
379 | void iwl_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq) | |
380 | { | |
381 | unsigned long flags; | |
382 | int i; | |
383 | spin_lock_irqsave(&rxq->lock, flags); | |
384 | INIT_LIST_HEAD(&rxq->rx_free); | |
385 | INIT_LIST_HEAD(&rxq->rx_used); | |
386 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
387 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { | |
388 | /* In the reset function, these buffers may have been allocated | |
389 | * to an SKB, so we need to unmap and free potential storage */ | |
390 | if (rxq->pool[i].skb != NULL) { | |
391 | pci_unmap_single(priv->pci_dev, | |
4018517a JB |
392 | rxq->pool[i].real_dma_addr, |
393 | priv->hw_params.rx_buf_size + 256, | |
a55360e4 TW |
394 | PCI_DMA_FROMDEVICE); |
395 | priv->alloc_rxb_skb--; | |
396 | dev_kfree_skb(rxq->pool[i].skb); | |
397 | rxq->pool[i].skb = NULL; | |
398 | } | |
399 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
400 | } | |
401 | ||
402 | /* Set us so that we have processed and used all buffers, but have | |
403 | * not restocked the Rx queue with fresh buffers */ | |
404 | rxq->read = rxq->write = 0; | |
4752c93c | 405 | rxq->write_actual = 0; |
a55360e4 TW |
406 | rxq->free_count = 0; |
407 | spin_unlock_irqrestore(&rxq->lock, flags); | |
408 | } | |
a55360e4 | 409 | |
1053d35f RR |
410 | int iwl_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq) |
411 | { | |
8cd519e8 WT |
412 | u32 rb_size; |
413 | const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ | |
0324c14b MA |
414 | u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */ |
415 | ||
416 | if (!priv->cfg->use_isr_legacy) | |
417 | rb_timeout = RX_RB_TIMEOUT; | |
1053d35f | 418 | |
1053d35f RR |
419 | if (priv->cfg->mod_params->amsdu_size_8K) |
420 | rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; | |
421 | else | |
422 | rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; | |
423 | ||
424 | /* Stop Rx DMA */ | |
425 | iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); | |
426 | ||
427 | /* Reset driver's Rx queue write index */ | |
428 | iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); | |
429 | ||
430 | /* Tell device where to find RBD circular buffer in DRAM */ | |
431 | iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG, | |
8cd519e8 | 432 | (u32)(rxq->dma_addr >> 8)); |
1053d35f RR |
433 | |
434 | /* Tell device where in DRAM to update its Rx status */ | |
435 | iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG, | |
8d86422a | 436 | rxq->rb_stts_dma >> 4); |
1053d35f | 437 | |
8cd519e8 | 438 | /* Enable Rx DMA |
a96a27f9 | 439 | * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in |
8cd519e8 WT |
440 | * the credit mechanism in 5000 HW RX FIFO |
441 | * Direct rx interrupts to hosts | |
442 | * Rx buffer size 4 or 8k | |
443 | * RB timeout 0x10 | |
444 | * 256 RBDs | |
445 | */ | |
1053d35f RR |
446 | iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, |
447 | FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | | |
8cd519e8 | 448 | FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | |
1053d35f | 449 | FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | |
9f925938 | 450 | FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK | |
8cd519e8 WT |
451 | rb_size| |
452 | (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)| | |
453 | (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); | |
1053d35f | 454 | |
8cd519e8 WT |
455 | iwl_write32(priv, CSR_INT_COALESCING, 0x40); |
456 | ||
1053d35f RR |
457 | return 0; |
458 | } | |
459 | ||
b3bbacb7 TW |
460 | int iwl_rxq_stop(struct iwl_priv *priv) |
461 | { | |
b3bbacb7 TW |
462 | |
463 | /* stop Rx DMA */ | |
464 | iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); | |
73d7b5ac ZY |
465 | iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG, |
466 | FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000); | |
b3bbacb7 | 467 | |
b3bbacb7 TW |
468 | return 0; |
469 | } | |
470 | EXPORT_SYMBOL(iwl_rxq_stop); | |
471 | ||
c1354754 TW |
472 | void iwl_rx_missed_beacon_notif(struct iwl_priv *priv, |
473 | struct iwl_rx_mem_buffer *rxb) | |
474 | ||
475 | { | |
c1354754 | 476 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; |
2aa6ab86 | 477 | struct iwl_missed_beacon_notif *missed_beacon; |
c1354754 TW |
478 | |
479 | missed_beacon = &pkt->u.missed_beacon; | |
480 | if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) { | |
e1623446 | 481 | IWL_DEBUG_CALIB(priv, "missed bcn cnsq %d totl %d rcd %d expctd %d\n", |
c1354754 TW |
482 | le32_to_cpu(missed_beacon->consequtive_missed_beacons), |
483 | le32_to_cpu(missed_beacon->total_missed_becons), | |
484 | le32_to_cpu(missed_beacon->num_recvd_beacons), | |
485 | le32_to_cpu(missed_beacon->num_expected_beacons)); | |
486 | if (!test_bit(STATUS_SCANNING, &priv->status)) | |
487 | iwl_init_sensitivity(priv); | |
488 | } | |
c1354754 TW |
489 | } |
490 | EXPORT_SYMBOL(iwl_rx_missed_beacon_notif); | |
8f91aecb EG |
491 | |
492 | ||
493 | /* Calculate noise level, based on measurements during network silence just | |
494 | * before arriving beacon. This measurement can be done only if we know | |
495 | * exactly when to expect beacons, therefore only when we're associated. */ | |
496 | static void iwl_rx_calc_noise(struct iwl_priv *priv) | |
497 | { | |
498 | struct statistics_rx_non_phy *rx_info | |
499 | = &(priv->statistics.rx.general); | |
500 | int num_active_rx = 0; | |
501 | int total_silence = 0; | |
502 | int bcn_silence_a = | |
503 | le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER; | |
504 | int bcn_silence_b = | |
505 | le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER; | |
506 | int bcn_silence_c = | |
507 | le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER; | |
508 | ||
509 | if (bcn_silence_a) { | |
510 | total_silence += bcn_silence_a; | |
511 | num_active_rx++; | |
512 | } | |
513 | if (bcn_silence_b) { | |
514 | total_silence += bcn_silence_b; | |
515 | num_active_rx++; | |
516 | } | |
517 | if (bcn_silence_c) { | |
518 | total_silence += bcn_silence_c; | |
519 | num_active_rx++; | |
520 | } | |
521 | ||
522 | /* Average among active antennas */ | |
523 | if (num_active_rx) | |
524 | priv->last_rx_noise = (total_silence / num_active_rx) - 107; | |
525 | else | |
526 | priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE; | |
527 | ||
e1623446 | 528 | IWL_DEBUG_CALIB(priv, "inband silence a %u, b %u, c %u, dBm %d\n", |
8f91aecb EG |
529 | bcn_silence_a, bcn_silence_b, bcn_silence_c, |
530 | priv->last_rx_noise); | |
531 | } | |
532 | ||
533 | #define REG_RECALIB_PERIOD (60) | |
534 | ||
535 | void iwl_rx_statistics(struct iwl_priv *priv, | |
536 | struct iwl_rx_mem_buffer *rxb) | |
537 | { | |
5225640b | 538 | int change; |
8f91aecb EG |
539 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; |
540 | ||
e1623446 | 541 | IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n", |
8f91aecb EG |
542 | (int)sizeof(priv->statistics), pkt->len); |
543 | ||
5225640b ZY |
544 | change = ((priv->statistics.general.temperature != |
545 | pkt->u.stats.general.temperature) || | |
546 | ((priv->statistics.flag & | |
7aafef1c WYG |
547 | STATISTICS_REPLY_FLG_HT40_MODE_MSK) != |
548 | (pkt->u.stats.flag & STATISTICS_REPLY_FLG_HT40_MODE_MSK))); | |
5225640b | 549 | |
8f91aecb EG |
550 | memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics)); |
551 | ||
552 | set_bit(STATUS_STATISTICS, &priv->status); | |
553 | ||
554 | /* Reschedule the statistics timer to occur in | |
555 | * REG_RECALIB_PERIOD seconds to ensure we get a | |
556 | * thermal update even if the uCode doesn't give | |
557 | * us one */ | |
558 | mod_timer(&priv->statistics_periodic, jiffies + | |
559 | msecs_to_jiffies(REG_RECALIB_PERIOD * 1000)); | |
560 | ||
561 | if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) && | |
562 | (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) { | |
563 | iwl_rx_calc_noise(priv); | |
564 | queue_work(priv->workqueue, &priv->run_time_calib_work); | |
565 | } | |
566 | ||
567 | iwl_leds_background(priv); | |
568 | ||
62161aef WYG |
569 | if (priv->cfg->ops->lib->temp_ops.temperature && change) |
570 | priv->cfg->ops->lib->temp_ops.temperature(priv); | |
8f91aecb EG |
571 | } |
572 | EXPORT_SYMBOL(iwl_rx_statistics); | |
1781a07f EG |
573 | |
574 | #define PERFECT_RSSI (-20) /* dBm */ | |
575 | #define WORST_RSSI (-95) /* dBm */ | |
576 | #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI) | |
577 | ||
578 | /* Calculate an indication of rx signal quality (a percentage, not dBm!). | |
579 | * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info | |
580 | * about formulas used below. */ | |
581 | static int iwl_calc_sig_qual(int rssi_dbm, int noise_dbm) | |
582 | { | |
583 | int sig_qual; | |
584 | int degradation = PERFECT_RSSI - rssi_dbm; | |
585 | ||
586 | /* If we get a noise measurement, use signal-to-noise ratio (SNR) | |
587 | * as indicator; formula is (signal dbm - noise dbm). | |
588 | * SNR at or above 40 is a great signal (100%). | |
589 | * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator. | |
590 | * Weakest usable signal is usually 10 - 15 dB SNR. */ | |
591 | if (noise_dbm) { | |
592 | if (rssi_dbm - noise_dbm >= 40) | |
593 | return 100; | |
594 | else if (rssi_dbm < noise_dbm) | |
595 | return 0; | |
596 | sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2; | |
597 | ||
598 | /* Else use just the signal level. | |
599 | * This formula is a least squares fit of data points collected and | |
600 | * compared with a reference system that had a percentage (%) display | |
601 | * for signal quality. */ | |
602 | } else | |
603 | sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation * | |
604 | (15 * RSSI_RANGE + 62 * degradation)) / | |
605 | (RSSI_RANGE * RSSI_RANGE); | |
606 | ||
607 | if (sig_qual > 100) | |
608 | sig_qual = 100; | |
609 | else if (sig_qual < 1) | |
610 | sig_qual = 0; | |
611 | ||
612 | return sig_qual; | |
613 | } | |
614 | ||
00e540b3 HD |
615 | /* Calc max signal level (dBm) among 3 possible receivers */ |
616 | static inline int iwl_calc_rssi(struct iwl_priv *priv, | |
617 | struct iwl_rx_phy_res *rx_resp) | |
618 | { | |
619 | return priv->cfg->ops->utils->calc_rssi(priv, rx_resp); | |
620 | } | |
1781a07f | 621 | |
00e540b3 | 622 | #ifdef CONFIG_IWLWIFI_DEBUG |
1781a07f EG |
623 | /** |
624 | * iwl_dbg_report_frame - dump frame to syslog during debug sessions | |
625 | * | |
626 | * You may hack this function to show different aspects of received frames, | |
627 | * including selective frame dumps. | |
00e540b3 HD |
628 | * group100 parameter selects whether to show 1 out of 100 good data frames. |
629 | * All beacon and probe response frames are printed. | |
1781a07f EG |
630 | */ |
631 | static void iwl_dbg_report_frame(struct iwl_priv *priv, | |
00e540b3 | 632 | struct iwl_rx_phy_res *phy_res, u16 length, |
1781a07f EG |
633 | struct ieee80211_hdr *header, int group100) |
634 | { | |
635 | u32 to_us; | |
636 | u32 print_summary = 0; | |
637 | u32 print_dump = 0; /* set to 1 to dump all frames' contents */ | |
638 | u32 hundred = 0; | |
639 | u32 dataframe = 0; | |
640 | __le16 fc; | |
641 | u16 seq_ctl; | |
642 | u16 channel; | |
643 | u16 phy_flags; | |
00e540b3 | 644 | u32 rate_n_flags; |
1781a07f | 645 | u32 tsf_low; |
00e540b3 | 646 | int rssi; |
1781a07f | 647 | |
3d816c77 | 648 | if (likely(!(iwl_get_debug_level(priv) & IWL_DL_RX))) |
1781a07f EG |
649 | return; |
650 | ||
651 | /* MAC header */ | |
652 | fc = header->frame_control; | |
653 | seq_ctl = le16_to_cpu(header->seq_ctrl); | |
654 | ||
655 | /* metadata */ | |
00e540b3 HD |
656 | channel = le16_to_cpu(phy_res->channel); |
657 | phy_flags = le16_to_cpu(phy_res->phy_flags); | |
658 | rate_n_flags = le32_to_cpu(phy_res->rate_n_flags); | |
1781a07f EG |
659 | |
660 | /* signal statistics */ | |
00e540b3 HD |
661 | rssi = iwl_calc_rssi(priv, phy_res); |
662 | tsf_low = le64_to_cpu(phy_res->timestamp) & 0x0ffffffff; | |
1781a07f EG |
663 | |
664 | to_us = !compare_ether_addr(header->addr1, priv->mac_addr); | |
665 | ||
666 | /* if data frame is to us and all is good, | |
667 | * (optionally) print summary for only 1 out of every 100 */ | |
668 | if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) == | |
669 | cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) { | |
670 | dataframe = 1; | |
671 | if (!group100) | |
672 | print_summary = 1; /* print each frame */ | |
673 | else if (priv->framecnt_to_us < 100) { | |
674 | priv->framecnt_to_us++; | |
675 | print_summary = 0; | |
676 | } else { | |
677 | priv->framecnt_to_us = 0; | |
678 | print_summary = 1; | |
679 | hundred = 1; | |
680 | } | |
681 | } else { | |
682 | /* print summary for all other frames */ | |
683 | print_summary = 1; | |
684 | } | |
685 | ||
686 | if (print_summary) { | |
687 | char *title; | |
688 | int rate_idx; | |
689 | u32 bitrate; | |
690 | ||
691 | if (hundred) | |
692 | title = "100Frames"; | |
693 | else if (ieee80211_has_retry(fc)) | |
694 | title = "Retry"; | |
695 | else if (ieee80211_is_assoc_resp(fc)) | |
696 | title = "AscRsp"; | |
697 | else if (ieee80211_is_reassoc_resp(fc)) | |
698 | title = "RasRsp"; | |
699 | else if (ieee80211_is_probe_resp(fc)) { | |
700 | title = "PrbRsp"; | |
701 | print_dump = 1; /* dump frame contents */ | |
702 | } else if (ieee80211_is_beacon(fc)) { | |
703 | title = "Beacon"; | |
704 | print_dump = 1; /* dump frame contents */ | |
705 | } else if (ieee80211_is_atim(fc)) | |
706 | title = "ATIM"; | |
707 | else if (ieee80211_is_auth(fc)) | |
708 | title = "Auth"; | |
709 | else if (ieee80211_is_deauth(fc)) | |
710 | title = "DeAuth"; | |
711 | else if (ieee80211_is_disassoc(fc)) | |
712 | title = "DisAssoc"; | |
713 | else | |
714 | title = "Frame"; | |
715 | ||
00e540b3 HD |
716 | rate_idx = iwl_hwrate_to_plcp_idx(rate_n_flags); |
717 | if (unlikely((rate_idx < 0) || (rate_idx >= IWL_RATE_COUNT))) { | |
1781a07f | 718 | bitrate = 0; |
00e540b3 HD |
719 | WARN_ON_ONCE(1); |
720 | } else { | |
1781a07f | 721 | bitrate = iwl_rates[rate_idx].ieee / 2; |
00e540b3 | 722 | } |
1781a07f EG |
723 | |
724 | /* print frame summary. | |
725 | * MAC addresses show just the last byte (for brevity), | |
726 | * but you can hack it to show more, if you'd like to. */ | |
727 | if (dataframe) | |
e1623446 | 728 | IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, " |
1781a07f EG |
729 | "len=%u, rssi=%d, chnl=%d, rate=%u, \n", |
730 | title, le16_to_cpu(fc), header->addr1[5], | |
731 | length, rssi, channel, bitrate); | |
732 | else { | |
733 | /* src/dst addresses assume managed mode */ | |
e1623446 | 734 | IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, src=0x%02x, " |
00e540b3 | 735 | "len=%u, rssi=%d, tim=%lu usec, " |
1781a07f EG |
736 | "phy=0x%02x, chnl=%d\n", |
737 | title, le16_to_cpu(fc), header->addr1[5], | |
00e540b3 | 738 | header->addr3[5], length, rssi, |
1781a07f EG |
739 | tsf_low - priv->scan_start_tsf, |
740 | phy_flags, channel); | |
741 | } | |
742 | } | |
743 | if (print_dump) | |
3d816c77 | 744 | iwl_print_hex_dump(priv, IWL_DL_RX, header, length); |
1781a07f | 745 | } |
1781a07f EG |
746 | #endif |
747 | ||
1781a07f EG |
748 | /* |
749 | * returns non-zero if packet should be dropped | |
750 | */ | |
8ccde88a SO |
751 | int iwl_set_decrypted_flag(struct iwl_priv *priv, |
752 | struct ieee80211_hdr *hdr, | |
753 | u32 decrypt_res, | |
754 | struct ieee80211_rx_status *stats) | |
1781a07f EG |
755 | { |
756 | u16 fc = le16_to_cpu(hdr->frame_control); | |
757 | ||
758 | if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK) | |
759 | return 0; | |
760 | ||
761 | if (!(fc & IEEE80211_FCTL_PROTECTED)) | |
762 | return 0; | |
763 | ||
e1623446 | 764 | IWL_DEBUG_RX(priv, "decrypt_res:0x%x\n", decrypt_res); |
1781a07f EG |
765 | switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) { |
766 | case RX_RES_STATUS_SEC_TYPE_TKIP: | |
767 | /* The uCode has got a bad phase 1 Key, pushes the packet. | |
768 | * Decryption will be done in SW. */ | |
769 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
770 | RX_RES_STATUS_BAD_KEY_TTAK) | |
771 | break; | |
772 | ||
773 | case RX_RES_STATUS_SEC_TYPE_WEP: | |
774 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
775 | RX_RES_STATUS_BAD_ICV_MIC) { | |
776 | /* bad ICV, the packet is destroyed since the | |
777 | * decryption is inplace, drop it */ | |
e1623446 | 778 | IWL_DEBUG_RX(priv, "Packet destroyed\n"); |
1781a07f EG |
779 | return -1; |
780 | } | |
781 | case RX_RES_STATUS_SEC_TYPE_CCMP: | |
782 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
783 | RX_RES_STATUS_DECRYPT_OK) { | |
e1623446 | 784 | IWL_DEBUG_RX(priv, "hw decrypt successfully!!!\n"); |
1781a07f EG |
785 | stats->flag |= RX_FLAG_DECRYPTED; |
786 | } | |
787 | break; | |
788 | ||
789 | default: | |
790 | break; | |
791 | } | |
792 | return 0; | |
793 | } | |
8ccde88a | 794 | EXPORT_SYMBOL(iwl_set_decrypted_flag); |
1781a07f EG |
795 | |
796 | static u32 iwl_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in) | |
797 | { | |
798 | u32 decrypt_out = 0; | |
799 | ||
800 | if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) == | |
801 | RX_RES_STATUS_STATION_FOUND) | |
802 | decrypt_out |= (RX_RES_STATUS_STATION_FOUND | | |
803 | RX_RES_STATUS_NO_STATION_INFO_MISMATCH); | |
804 | ||
805 | decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK); | |
806 | ||
807 | /* packet was not encrypted */ | |
808 | if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) == | |
809 | RX_RES_STATUS_SEC_TYPE_NONE) | |
810 | return decrypt_out; | |
811 | ||
812 | /* packet was encrypted with unknown alg */ | |
813 | if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) == | |
814 | RX_RES_STATUS_SEC_TYPE_ERR) | |
815 | return decrypt_out; | |
816 | ||
817 | /* decryption was not done in HW */ | |
818 | if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) != | |
819 | RX_MPDU_RES_STATUS_DEC_DONE_MSK) | |
820 | return decrypt_out; | |
821 | ||
822 | switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) { | |
823 | ||
824 | case RX_RES_STATUS_SEC_TYPE_CCMP: | |
825 | /* alg is CCM: check MIC only */ | |
826 | if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK)) | |
827 | /* Bad MIC */ | |
828 | decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC; | |
829 | else | |
830 | decrypt_out |= RX_RES_STATUS_DECRYPT_OK; | |
831 | ||
832 | break; | |
833 | ||
834 | case RX_RES_STATUS_SEC_TYPE_TKIP: | |
835 | if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) { | |
836 | /* Bad TTAK */ | |
837 | decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK; | |
838 | break; | |
839 | } | |
840 | /* fall through if TTAK OK */ | |
841 | default: | |
842 | if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK)) | |
843 | decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC; | |
844 | else | |
845 | decrypt_out |= RX_RES_STATUS_DECRYPT_OK; | |
846 | break; | |
847 | }; | |
848 | ||
e1623446 | 849 | IWL_DEBUG_RX(priv, "decrypt_in:0x%x decrypt_out = 0x%x\n", |
1781a07f EG |
850 | decrypt_in, decrypt_out); |
851 | ||
852 | return decrypt_out; | |
853 | } | |
854 | ||
4b8817b2 | 855 | static void iwl_pass_packet_to_mac80211(struct iwl_priv *priv, |
9f30e04e DH |
856 | struct ieee80211_hdr *hdr, |
857 | u16 len, | |
858 | u32 ampdu_status, | |
859 | struct iwl_rx_mem_buffer *rxb, | |
860 | struct ieee80211_rx_status *stats) | |
1781a07f | 861 | { |
1781a07f EG |
862 | /* We only process data packets if the interface is open */ |
863 | if (unlikely(!priv->is_open)) { | |
e1623446 TW |
864 | IWL_DEBUG_DROP_LIMIT(priv, |
865 | "Dropping packet while interface is not open.\n"); | |
1781a07f EG |
866 | return; |
867 | } | |
868 | ||
9f30e04e | 869 | /* In case of HW accelerated crypto and bad decryption, drop */ |
90e8e424 | 870 | if (!priv->cfg->mod_params->sw_crypto && |
1781a07f EG |
871 | iwl_set_decrypted_flag(priv, hdr, ampdu_status, stats)) |
872 | return; | |
873 | ||
9f30e04e DH |
874 | /* Resize SKB from mac header to end of packet */ |
875 | skb_reserve(rxb->skb, (void *)hdr - (void *)rxb->skb->data); | |
876 | skb_put(rxb->skb, len); | |
877 | ||
22fdf3c9 | 878 | iwl_update_stats(priv, false, hdr->frame_control, len); |
f1d58c25 JB |
879 | memcpy(IEEE80211_SKB_RXCB(rxb->skb), stats, sizeof(*stats)); |
880 | ieee80211_rx_irqsafe(priv->hw, rxb->skb); | |
1781a07f EG |
881 | priv->alloc_rxb_skb--; |
882 | rxb->skb = NULL; | |
883 | } | |
884 | ||
4b8817b2 | 885 | /* This is necessary only for a number of statistics, see the caller. */ |
1781a07f EG |
886 | static int iwl_is_network_packet(struct iwl_priv *priv, |
887 | struct ieee80211_hdr *header) | |
888 | { | |
889 | /* Filter incoming packets to determine if they are targeted toward | |
890 | * this network, discarding packets coming from ourselves */ | |
891 | switch (priv->iw_mode) { | |
05c914fe | 892 | case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */ |
4b8817b2 EG |
893 | /* packets to our IBSS update information */ |
894 | return !compare_ether_addr(header->addr3, priv->bssid); | |
05c914fe | 895 | case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */ |
4b8817b2 EG |
896 | /* packets to our IBSS update information */ |
897 | return !compare_ether_addr(header->addr2, priv->bssid); | |
1781a07f | 898 | default: |
4b8817b2 | 899 | return 1; |
1781a07f | 900 | } |
1781a07f EG |
901 | } |
902 | ||
903 | /* Called for REPLY_RX (legacy ABG frames), or | |
904 | * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */ | |
905 | void iwl_rx_reply_rx(struct iwl_priv *priv, | |
906 | struct iwl_rx_mem_buffer *rxb) | |
907 | { | |
908 | struct ieee80211_hdr *header; | |
909 | struct ieee80211_rx_status rx_status; | |
910 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; | |
9f30e04e DH |
911 | struct iwl_rx_phy_res *phy_res; |
912 | __le32 rx_pkt_status; | |
913 | struct iwl4965_rx_mpdu_res_start *amsdu; | |
914 | u32 len; | |
915 | u32 ampdu_status; | |
1781a07f | 916 | u16 fc; |
1781a07f | 917 | |
9f30e04e DH |
918 | /** |
919 | * REPLY_RX and REPLY_RX_MPDU_CMD are handled differently. | |
920 | * REPLY_RX: physical layer info is in this buffer | |
921 | * REPLY_RX_MPDU_CMD: physical layer info was sent in separate | |
922 | * command and cached in priv->last_phy_res | |
923 | * | |
924 | * Here we set up local variables depending on which command is | |
925 | * received. | |
926 | */ | |
927 | if (pkt->hdr.cmd == REPLY_RX) { | |
928 | phy_res = (struct iwl_rx_phy_res *)pkt->u.raw; | |
929 | header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res) | |
930 | + phy_res->cfg_phy_cnt); | |
931 | ||
932 | len = le16_to_cpu(phy_res->byte_count); | |
933 | rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*phy_res) + | |
934 | phy_res->cfg_phy_cnt + len); | |
935 | ampdu_status = le32_to_cpu(rx_pkt_status); | |
936 | } else { | |
937 | if (!priv->last_phy_res[0]) { | |
938 | IWL_ERR(priv, "MPDU frame without cached PHY data\n"); | |
939 | return; | |
940 | } | |
941 | phy_res = (struct iwl_rx_phy_res *)&priv->last_phy_res[1]; | |
942 | amsdu = (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw; | |
943 | header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu)); | |
944 | len = le16_to_cpu(amsdu->byte_count); | |
945 | rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*amsdu) + len); | |
946 | ampdu_status = iwl_translate_rx_status(priv, | |
947 | le32_to_cpu(rx_pkt_status)); | |
948 | } | |
949 | ||
950 | if ((unlikely(phy_res->cfg_phy_cnt > 20))) { | |
951 | IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n", | |
952 | phy_res->cfg_phy_cnt); | |
953 | return; | |
954 | } | |
955 | ||
956 | if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) || | |
957 | !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) { | |
958 | IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", | |
959 | le32_to_cpu(rx_pkt_status)); | |
960 | return; | |
961 | } | |
962 | ||
963 | /* rx_status carries information about the packet to mac80211 */ | |
964 | rx_status.mactime = le64_to_cpu(phy_res->timestamp); | |
1781a07f | 965 | rx_status.freq = |
9f30e04e DH |
966 | ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel)); |
967 | rx_status.band = (phy_res->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ? | |
1781a07f EG |
968 | IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ; |
969 | rx_status.rate_idx = | |
9f30e04e | 970 | iwl_hwrate_to_plcp_idx(le32_to_cpu(phy_res->rate_n_flags)); |
1781a07f EG |
971 | if (rx_status.band == IEEE80211_BAND_5GHZ) |
972 | rx_status.rate_idx -= IWL_FIRST_OFDM_RATE; | |
973 | ||
1781a07f | 974 | rx_status.flag = 0; |
b94d8eea AK |
975 | |
976 | /* TSF isn't reliable. In order to allow smooth user experience, | |
977 | * this W/A doesn't propagate it to the mac80211 */ | |
978 | /*rx_status.flag |= RX_FLAG_TSFT;*/ | |
1781a07f | 979 | |
9f30e04e | 980 | priv->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp); |
1781a07f EG |
981 | |
982 | /* Find max signal strength (dBm) among 3 antenna/receiver chains */ | |
9f30e04e | 983 | rx_status.signal = iwl_calc_rssi(priv, phy_res); |
1781a07f EG |
984 | |
985 | /* Meaningful noise values are available only from beacon statistics, | |
986 | * which are gathered only when associated, and indicate noise | |
987 | * only for the associated network channel ... | |
988 | * Ignore these noise values while scanning (other channels) */ | |
989 | if (iwl_is_associated(priv) && | |
990 | !test_bit(STATUS_SCANNING, &priv->status)) { | |
991 | rx_status.noise = priv->last_rx_noise; | |
992 | rx_status.qual = iwl_calc_sig_qual(rx_status.signal, | |
993 | rx_status.noise); | |
994 | } else { | |
995 | rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE; | |
996 | rx_status.qual = iwl_calc_sig_qual(rx_status.signal, 0); | |
997 | } | |
998 | ||
999 | /* Reset beacon noise level if not associated. */ | |
1000 | if (!iwl_is_associated(priv)) | |
1001 | priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE; | |
1002 | ||
21a49fc6 | 1003 | #ifdef CONFIG_IWLWIFI_DEBUG |
9f30e04e | 1004 | /* Set "1" to report good data frames in groups of 100 */ |
3d816c77 | 1005 | if (unlikely(iwl_get_debug_level(priv) & IWL_DL_RX)) |
9f30e04e | 1006 | iwl_dbg_report_frame(priv, phy_res, len, header, 1); |
21a49fc6 | 1007 | #endif |
20594eb0 | 1008 | iwl_dbg_log_rx_data_frame(priv, len, header); |
e1623446 | 1009 | IWL_DEBUG_STATS_LIMIT(priv, "Rssi %d, noise %d, qual %d, TSF %llu\n", |
244294e8 | 1010 | rx_status.signal, rx_status.noise, rx_status.qual, |
1781a07f EG |
1011 | (unsigned long long)rx_status.mactime); |
1012 | ||
6f0a2c4d BR |
1013 | /* |
1014 | * "antenna number" | |
1015 | * | |
1016 | * It seems that the antenna field in the phy flags value | |
a96a27f9 | 1017 | * is actually a bit field. This is undefined by radiotap, |
6f0a2c4d BR |
1018 | * it wants an actual antenna number but I always get "7" |
1019 | * for most legacy frames I receive indicating that the | |
1020 | * same frame was received on all three RX chains. | |
1021 | * | |
a96a27f9 | 1022 | * I think this field should be removed in favor of a |
6f0a2c4d BR |
1023 | * new 802.11n radiotap field "RX chains" that is defined |
1024 | * as a bitmask. | |
1025 | */ | |
9f30e04e DH |
1026 | rx_status.antenna = |
1027 | le16_to_cpu(phy_res->phy_flags & RX_RES_PHY_FLAGS_ANTENNA_MSK) | |
1028 | >> RX_RES_PHY_FLAGS_ANTENNA_POS; | |
6f0a2c4d BR |
1029 | |
1030 | /* set the preamble flag if appropriate */ | |
9f30e04e | 1031 | if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK) |
6f0a2c4d BR |
1032 | rx_status.flag |= RX_FLAG_SHORTPRE; |
1033 | ||
9f30e04e | 1034 | if (iwl_is_network_packet(priv, header)) { |
1781a07f EG |
1035 | priv->last_rx_rssi = rx_status.signal; |
1036 | priv->last_beacon_time = priv->ucode_beacon_time; | |
9f30e04e | 1037 | priv->last_tsf = le64_to_cpu(phy_res->timestamp); |
1781a07f EG |
1038 | } |
1039 | ||
1040 | fc = le16_to_cpu(header->frame_control); | |
1041 | switch (fc & IEEE80211_FCTL_FTYPE) { | |
1042 | case IEEE80211_FTYPE_MGMT: | |
4b8817b2 | 1043 | case IEEE80211_FTYPE_DATA: |
05c914fe | 1044 | if (priv->iw_mode == NL80211_IFTYPE_AP) |
1781a07f EG |
1045 | iwl_update_ps_mode(priv, fc & IEEE80211_FCTL_PM, |
1046 | header->addr2); | |
4b8817b2 | 1047 | /* fall through */ |
1781a07f | 1048 | default: |
9f30e04e DH |
1049 | iwl_pass_packet_to_mac80211(priv, header, len, ampdu_status, |
1050 | rxb, &rx_status); | |
1781a07f EG |
1051 | break; |
1052 | ||
1053 | } | |
1054 | } | |
1055 | EXPORT_SYMBOL(iwl_rx_reply_rx); | |
1056 | ||
1057 | /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD). | |
1058 | * This will be used later in iwl_rx_reply_rx() for REPLY_RX_MPDU_CMD. */ | |
1059 | void iwl_rx_reply_rx_phy(struct iwl_priv *priv, | |
1060 | struct iwl_rx_mem_buffer *rxb) | |
1061 | { | |
1062 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; | |
1063 | priv->last_phy_res[0] = 1; | |
1064 | memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]), | |
caab8f1a | 1065 | sizeof(struct iwl_rx_phy_res)); |
1781a07f EG |
1066 | } |
1067 | EXPORT_SYMBOL(iwl_rx_reply_rx_phy); |