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a55360e4 TW |
1 | /****************************************************************************** |
2 | * | |
1f447808 | 3 | * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved. |
a55360e4 TW |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
a55360e4 TW |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
1781a07f | 30 | #include <linux/etherdevice.h> |
a55360e4 | 31 | #include <net/mac80211.h> |
a05ffd39 | 32 | #include <asm/unaligned.h> |
a55360e4 TW |
33 | #include "iwl-eeprom.h" |
34 | #include "iwl-dev.h" | |
35 | #include "iwl-core.h" | |
36 | #include "iwl-sta.h" | |
37 | #include "iwl-io.h" | |
c1354754 | 38 | #include "iwl-calib.h" |
a55360e4 TW |
39 | #include "iwl-helpers.h" |
40 | /************************** RX-FUNCTIONS ****************************/ | |
41 | /* | |
42 | * Rx theory of operation | |
43 | * | |
44 | * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs), | |
45 | * each of which point to Receive Buffers to be filled by the NIC. These get | |
46 | * used not only for Rx frames, but for any command response or notification | |
47 | * from the NIC. The driver and NIC manage the Rx buffers by means | |
48 | * of indexes into the circular buffer. | |
49 | * | |
50 | * Rx Queue Indexes | |
51 | * The host/firmware share two index registers for managing the Rx buffers. | |
52 | * | |
53 | * The READ index maps to the first position that the firmware may be writing | |
54 | * to -- the driver can read up to (but not including) this position and get | |
55 | * good data. | |
56 | * The READ index is managed by the firmware once the card is enabled. | |
57 | * | |
58 | * The WRITE index maps to the last position the driver has read from -- the | |
59 | * position preceding WRITE is the last slot the firmware can place a packet. | |
60 | * | |
61 | * The queue is empty (no good data) if WRITE = READ - 1, and is full if | |
62 | * WRITE = READ. | |
63 | * | |
64 | * During initialization, the host sets up the READ queue position to the first | |
65 | * INDEX position, and WRITE to the last (READ - 1 wrapped) | |
66 | * | |
67 | * When the firmware places a packet in a buffer, it will advance the READ index | |
68 | * and fire the RX interrupt. The driver can then query the READ index and | |
69 | * process as many packets as possible, moving the WRITE index forward as it | |
70 | * resets the Rx queue buffers with new memory. | |
71 | * | |
72 | * The management in the driver is as follows: | |
73 | * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When | |
74 | * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled | |
75 | * to replenish the iwl->rxq->rx_free. | |
76 | * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the | |
77 | * iwl->rxq is replenished and the READ INDEX is updated (updating the | |
78 | * 'processed' and 'read' driver indexes as well) | |
79 | * + A received packet is processed and handed to the kernel network stack, | |
80 | * detached from the iwl->rxq. The driver 'processed' index is updated. | |
81 | * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free | |
82 | * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ | |
83 | * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there | |
84 | * were enough free buffers and RX_STALLED is set it is cleared. | |
85 | * | |
86 | * | |
87 | * Driver sequence: | |
88 | * | |
89 | * iwl_rx_queue_alloc() Allocates rx_free | |
90 | * iwl_rx_replenish() Replenishes rx_free list from rx_used, and calls | |
91 | * iwl_rx_queue_restock | |
92 | * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx | |
93 | * queue, updates firmware pointers, and updates | |
94 | * the WRITE index. If insufficient rx_free buffers | |
95 | * are available, schedules iwl_rx_replenish | |
96 | * | |
97 | * -- enable interrupts -- | |
98 | * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the | |
99 | * READ INDEX, detaching the SKB from the pool. | |
100 | * Moves the packet buffer from queue to rx_used. | |
101 | * Calls iwl_rx_queue_restock to refill any empty | |
102 | * slots. | |
103 | * ... | |
104 | * | |
105 | */ | |
106 | ||
107 | /** | |
108 | * iwl_rx_queue_space - Return number of free slots available in queue. | |
109 | */ | |
110 | int iwl_rx_queue_space(const struct iwl_rx_queue *q) | |
111 | { | |
112 | int s = q->read - q->write; | |
113 | if (s <= 0) | |
114 | s += RX_QUEUE_SIZE; | |
115 | /* keep some buffer to not confuse full and empty queue */ | |
116 | s -= 2; | |
117 | if (s < 0) | |
118 | s = 0; | |
119 | return s; | |
120 | } | |
121 | EXPORT_SYMBOL(iwl_rx_queue_space); | |
122 | ||
123 | /** | |
124 | * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue | |
125 | */ | |
126 | int iwl_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue *q) | |
127 | { | |
a55360e4 | 128 | unsigned long flags; |
141c43a3 WT |
129 | u32 rx_wrt_ptr_reg = priv->hw_params.rx_wrt_ptr_reg; |
130 | u32 reg; | |
131 | int ret = 0; | |
a55360e4 TW |
132 | |
133 | spin_lock_irqsave(&q->lock, flags); | |
134 | ||
135 | if (q->need_update == 0) | |
136 | goto exit_unlock; | |
137 | ||
138 | /* If power-saving is in use, make sure device is awake */ | |
139 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { | |
140 | reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); | |
141 | ||
142 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
309e731a BC |
143 | IWL_DEBUG_INFO(priv, "Rx queue requesting wakeup, GP1 = 0x%x\n", |
144 | reg); | |
a55360e4 TW |
145 | iwl_set_bit(priv, CSR_GP_CNTRL, |
146 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
147 | goto exit_unlock; | |
148 | } | |
149 | ||
4752c93c MA |
150 | q->write_actual = (q->write & ~0x7); |
151 | iwl_write_direct32(priv, rx_wrt_ptr_reg, q->write_actual); | |
a55360e4 TW |
152 | |
153 | /* Else device is assumed to be awake */ | |
141c43a3 | 154 | } else { |
a55360e4 | 155 | /* Device expects a multiple of 8 */ |
4752c93c MA |
156 | q->write_actual = (q->write & ~0x7); |
157 | iwl_write_direct32(priv, rx_wrt_ptr_reg, q->write_actual); | |
141c43a3 | 158 | } |
a55360e4 TW |
159 | |
160 | q->need_update = 0; | |
161 | ||
162 | exit_unlock: | |
163 | spin_unlock_irqrestore(&q->lock, flags); | |
164 | return ret; | |
165 | } | |
166 | EXPORT_SYMBOL(iwl_rx_queue_update_write_ptr); | |
167 | /** | |
168 | * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr | |
169 | */ | |
170 | static inline __le32 iwl_dma_addr2rbd_ptr(struct iwl_priv *priv, | |
171 | dma_addr_t dma_addr) | |
172 | { | |
173 | return cpu_to_le32((u32)(dma_addr >> 8)); | |
174 | } | |
175 | ||
176 | /** | |
177 | * iwl_rx_queue_restock - refill RX queue from pre-allocated pool | |
178 | * | |
179 | * If there are slots in the RX queue that need to be restocked, | |
180 | * and we have free pre-allocated buffers, fill the ranks as much | |
181 | * as we can, pulling from rx_free. | |
182 | * | |
183 | * This moves the 'write' index forward to catch up with 'processed', and | |
184 | * also updates the memory address in the firmware to reference the new | |
185 | * target buffer. | |
186 | */ | |
187 | int iwl_rx_queue_restock(struct iwl_priv *priv) | |
188 | { | |
189 | struct iwl_rx_queue *rxq = &priv->rxq; | |
190 | struct list_head *element; | |
191 | struct iwl_rx_mem_buffer *rxb; | |
192 | unsigned long flags; | |
193 | int write; | |
194 | int ret = 0; | |
195 | ||
196 | spin_lock_irqsave(&rxq->lock, flags); | |
197 | write = rxq->write & ~0x7; | |
198 | while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) { | |
199 | /* Get next free Rx buffer, remove from free list */ | |
200 | element = rxq->rx_free.next; | |
201 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); | |
202 | list_del(element); | |
203 | ||
204 | /* Point to Rx buffer via next RBD in circular buffer */ | |
2f301227 | 205 | rxq->bd[rxq->write] = iwl_dma_addr2rbd_ptr(priv, rxb->page_dma); |
a55360e4 TW |
206 | rxq->queue[rxq->write] = rxb; |
207 | rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; | |
208 | rxq->free_count--; | |
209 | } | |
210 | spin_unlock_irqrestore(&rxq->lock, flags); | |
211 | /* If the pre-allocated buffer pool is dropping low, schedule to | |
212 | * refill it */ | |
213 | if (rxq->free_count <= RX_LOW_WATERMARK) | |
214 | queue_work(priv->workqueue, &priv->rx_replenish); | |
215 | ||
216 | ||
217 | /* If we've added more space for the firmware to place data, tell it. | |
218 | * Increment device's write pointer in multiples of 8. */ | |
4752c93c | 219 | if (rxq->write_actual != (rxq->write & ~0x7)) { |
a55360e4 TW |
220 | spin_lock_irqsave(&rxq->lock, flags); |
221 | rxq->need_update = 1; | |
222 | spin_unlock_irqrestore(&rxq->lock, flags); | |
223 | ret = iwl_rx_queue_update_write_ptr(priv, rxq); | |
224 | } | |
225 | ||
226 | return ret; | |
227 | } | |
228 | EXPORT_SYMBOL(iwl_rx_queue_restock); | |
229 | ||
230 | ||
231 | /** | |
232 | * iwl_rx_replenish - Move all used packet from rx_used to rx_free | |
233 | * | |
234 | * When moving to rx_free an SKB is allocated for the slot. | |
235 | * | |
236 | * Also restock the Rx queue via iwl_rx_queue_restock. | |
237 | * This is called as a scheduled work item (except for during initialization) | |
238 | */ | |
4752c93c | 239 | void iwl_rx_allocate(struct iwl_priv *priv, gfp_t priority) |
a55360e4 TW |
240 | { |
241 | struct iwl_rx_queue *rxq = &priv->rxq; | |
242 | struct list_head *element; | |
243 | struct iwl_rx_mem_buffer *rxb; | |
2f301227 | 244 | struct page *page; |
a55360e4 | 245 | unsigned long flags; |
29b1b268 | 246 | gfp_t gfp_mask = priority; |
f1bc4ac6 ZY |
247 | |
248 | while (1) { | |
249 | spin_lock_irqsave(&rxq->lock, flags); | |
f1bc4ac6 ZY |
250 | if (list_empty(&rxq->rx_used)) { |
251 | spin_unlock_irqrestore(&rxq->lock, flags); | |
252 | return; | |
253 | } | |
f1bc4ac6 | 254 | spin_unlock_irqrestore(&rxq->lock, flags); |
a55360e4 | 255 | |
f82a924c | 256 | if (rxq->free_count > RX_LOW_WATERMARK) |
29b1b268 | 257 | gfp_mask |= __GFP_NOWARN; |
4752c93c | 258 | |
2f301227 | 259 | if (priv->hw_params.rx_page_order > 0) |
29b1b268 | 260 | gfp_mask |= __GFP_COMP; |
2f301227 ZY |
261 | |
262 | /* Alloc a new receive buffer */ | |
29b1b268 | 263 | page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order); |
2f301227 | 264 | if (!page) { |
f82a924c | 265 | if (net_ratelimit()) |
2f301227 ZY |
266 | IWL_DEBUG_INFO(priv, "alloc_pages failed, " |
267 | "order: %d\n", | |
268 | priv->hw_params.rx_page_order); | |
269 | ||
f82a924c RC |
270 | if ((rxq->free_count <= RX_LOW_WATERMARK) && |
271 | net_ratelimit()) | |
2f301227 | 272 | IWL_CRIT(priv, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n", |
f82a924c RC |
273 | priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL", |
274 | rxq->free_count); | |
a55360e4 TW |
275 | /* We don't reschedule replenish work here -- we will |
276 | * call the restock method and if it still needs | |
277 | * more buffers it will schedule replenish */ | |
2f301227 | 278 | return; |
a55360e4 | 279 | } |
a55360e4 | 280 | |
de0bd508 RC |
281 | spin_lock_irqsave(&rxq->lock, flags); |
282 | ||
283 | if (list_empty(&rxq->rx_used)) { | |
284 | spin_unlock_irqrestore(&rxq->lock, flags); | |
2f301227 | 285 | __free_pages(page, priv->hw_params.rx_page_order); |
de0bd508 RC |
286 | return; |
287 | } | |
288 | element = rxq->rx_used.next; | |
289 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); | |
290 | list_del(element); | |
291 | ||
292 | spin_unlock_irqrestore(&rxq->lock, flags); | |
293 | ||
2f301227 ZY |
294 | rxb->page = page; |
295 | /* Get physical address of the RB */ | |
296 | rxb->page_dma = pci_map_page(priv->pci_dev, page, 0, | |
297 | PAGE_SIZE << priv->hw_params.rx_page_order, | |
298 | PCI_DMA_FROMDEVICE); | |
4018517a | 299 | /* dma address must be no more than 36 bits */ |
2f301227 | 300 | BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36)); |
4018517a | 301 | /* and also 256 byte aligned! */ |
2f301227 | 302 | BUG_ON(rxb->page_dma & DMA_BIT_MASK(8)); |
4018517a | 303 | |
f1bc4ac6 ZY |
304 | spin_lock_irqsave(&rxq->lock, flags); |
305 | ||
a55360e4 TW |
306 | list_add_tail(&rxb->list, &rxq->rx_free); |
307 | rxq->free_count++; | |
2f301227 | 308 | priv->alloc_rxb_page++; |
f1bc4ac6 ZY |
309 | |
310 | spin_unlock_irqrestore(&rxq->lock, flags); | |
a55360e4 | 311 | } |
a55360e4 | 312 | } |
a55360e4 TW |
313 | |
314 | void iwl_rx_replenish(struct iwl_priv *priv) | |
315 | { | |
316 | unsigned long flags; | |
317 | ||
4752c93c | 318 | iwl_rx_allocate(priv, GFP_KERNEL); |
a55360e4 TW |
319 | |
320 | spin_lock_irqsave(&priv->lock, flags); | |
321 | iwl_rx_queue_restock(priv); | |
322 | spin_unlock_irqrestore(&priv->lock, flags); | |
323 | } | |
324 | EXPORT_SYMBOL(iwl_rx_replenish); | |
325 | ||
4752c93c MA |
326 | void iwl_rx_replenish_now(struct iwl_priv *priv) |
327 | { | |
328 | iwl_rx_allocate(priv, GFP_ATOMIC); | |
329 | ||
330 | iwl_rx_queue_restock(priv); | |
331 | } | |
332 | EXPORT_SYMBOL(iwl_rx_replenish_now); | |
333 | ||
a55360e4 TW |
334 | |
335 | /* Assumes that the skb field of the buffers in 'pool' is kept accurate. | |
336 | * If an SKB has been detached, the POOL needs to have its SKB set to NULL | |
337 | * This free routine walks the list of POOL entries and if SKB is set to | |
338 | * non NULL it is unmapped and freed | |
339 | */ | |
340 | void iwl_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq) | |
341 | { | |
342 | int i; | |
343 | for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) { | |
2f301227 ZY |
344 | if (rxq->pool[i].page != NULL) { |
345 | pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma, | |
346 | PAGE_SIZE << priv->hw_params.rx_page_order, | |
347 | PCI_DMA_FROMDEVICE); | |
64a76b50 | 348 | __iwl_free_pages(priv, rxq->pool[i].page); |
2f301227 | 349 | rxq->pool[i].page = NULL; |
a55360e4 TW |
350 | } |
351 | } | |
352 | ||
353 | pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd, | |
354 | rxq->dma_addr); | |
8d86422a WT |
355 | pci_free_consistent(priv->pci_dev, sizeof(struct iwl_rb_status), |
356 | rxq->rb_stts, rxq->rb_stts_dma); | |
a55360e4 | 357 | rxq->bd = NULL; |
8d86422a | 358 | rxq->rb_stts = NULL; |
a55360e4 TW |
359 | } |
360 | EXPORT_SYMBOL(iwl_rx_queue_free); | |
361 | ||
362 | int iwl_rx_queue_alloc(struct iwl_priv *priv) | |
363 | { | |
364 | struct iwl_rx_queue *rxq = &priv->rxq; | |
365 | struct pci_dev *dev = priv->pci_dev; | |
366 | int i; | |
367 | ||
368 | spin_lock_init(&rxq->lock); | |
369 | INIT_LIST_HEAD(&rxq->rx_free); | |
370 | INIT_LIST_HEAD(&rxq->rx_used); | |
371 | ||
372 | /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */ | |
373 | rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr); | |
374 | if (!rxq->bd) | |
8d86422a WT |
375 | goto err_bd; |
376 | ||
377 | rxq->rb_stts = pci_alloc_consistent(dev, sizeof(struct iwl_rb_status), | |
378 | &rxq->rb_stts_dma); | |
379 | if (!rxq->rb_stts) | |
380 | goto err_rb; | |
a55360e4 TW |
381 | |
382 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
383 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) | |
384 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
385 | ||
386 | /* Set us so that we have processed and used all buffers, but have | |
387 | * not restocked the Rx queue with fresh buffers */ | |
388 | rxq->read = rxq->write = 0; | |
4752c93c | 389 | rxq->write_actual = 0; |
a55360e4 TW |
390 | rxq->free_count = 0; |
391 | rxq->need_update = 0; | |
392 | return 0; | |
8d86422a WT |
393 | |
394 | err_rb: | |
395 | pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd, | |
396 | rxq->dma_addr); | |
397 | err_bd: | |
398 | return -ENOMEM; | |
a55360e4 TW |
399 | } |
400 | EXPORT_SYMBOL(iwl_rx_queue_alloc); | |
401 | ||
402 | void iwl_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq) | |
403 | { | |
404 | unsigned long flags; | |
405 | int i; | |
406 | spin_lock_irqsave(&rxq->lock, flags); | |
407 | INIT_LIST_HEAD(&rxq->rx_free); | |
408 | INIT_LIST_HEAD(&rxq->rx_used); | |
409 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
410 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { | |
411 | /* In the reset function, these buffers may have been allocated | |
412 | * to an SKB, so we need to unmap and free potential storage */ | |
2f301227 ZY |
413 | if (rxq->pool[i].page != NULL) { |
414 | pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma, | |
415 | PAGE_SIZE << priv->hw_params.rx_page_order, | |
416 | PCI_DMA_FROMDEVICE); | |
64a76b50 | 417 | __iwl_free_pages(priv, rxq->pool[i].page); |
2f301227 | 418 | rxq->pool[i].page = NULL; |
a55360e4 TW |
419 | } |
420 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
421 | } | |
422 | ||
423 | /* Set us so that we have processed and used all buffers, but have | |
424 | * not restocked the Rx queue with fresh buffers */ | |
425 | rxq->read = rxq->write = 0; | |
4752c93c | 426 | rxq->write_actual = 0; |
a55360e4 TW |
427 | rxq->free_count = 0; |
428 | spin_unlock_irqrestore(&rxq->lock, flags); | |
429 | } | |
a55360e4 | 430 | |
1053d35f RR |
431 | int iwl_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq) |
432 | { | |
8cd519e8 WT |
433 | u32 rb_size; |
434 | const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ | |
0324c14b MA |
435 | u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */ |
436 | ||
437 | if (!priv->cfg->use_isr_legacy) | |
438 | rb_timeout = RX_RB_TIMEOUT; | |
1053d35f | 439 | |
1053d35f RR |
440 | if (priv->cfg->mod_params->amsdu_size_8K) |
441 | rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; | |
442 | else | |
443 | rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; | |
444 | ||
445 | /* Stop Rx DMA */ | |
446 | iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); | |
447 | ||
448 | /* Reset driver's Rx queue write index */ | |
449 | iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); | |
450 | ||
451 | /* Tell device where to find RBD circular buffer in DRAM */ | |
452 | iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG, | |
8cd519e8 | 453 | (u32)(rxq->dma_addr >> 8)); |
1053d35f RR |
454 | |
455 | /* Tell device where in DRAM to update its Rx status */ | |
456 | iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG, | |
8d86422a | 457 | rxq->rb_stts_dma >> 4); |
1053d35f | 458 | |
8cd519e8 | 459 | /* Enable Rx DMA |
a96a27f9 | 460 | * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in |
8cd519e8 WT |
461 | * the credit mechanism in 5000 HW RX FIFO |
462 | * Direct rx interrupts to hosts | |
463 | * Rx buffer size 4 or 8k | |
464 | * RB timeout 0x10 | |
465 | * 256 RBDs | |
466 | */ | |
1053d35f RR |
467 | iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, |
468 | FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | | |
8cd519e8 | 469 | FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | |
1053d35f | 470 | FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | |
9f925938 | 471 | FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK | |
8cd519e8 WT |
472 | rb_size| |
473 | (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)| | |
474 | (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); | |
1053d35f | 475 | |
2be76703 WYG |
476 | /* Set interrupt coalescing timer to default (2048 usecs) */ |
477 | iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); | |
8cd519e8 | 478 | |
1053d35f RR |
479 | return 0; |
480 | } | |
481 | ||
b3bbacb7 TW |
482 | int iwl_rxq_stop(struct iwl_priv *priv) |
483 | { | |
b3bbacb7 TW |
484 | |
485 | /* stop Rx DMA */ | |
486 | iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); | |
73d7b5ac ZY |
487 | iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG, |
488 | FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000); | |
b3bbacb7 | 489 | |
b3bbacb7 TW |
490 | return 0; |
491 | } | |
492 | EXPORT_SYMBOL(iwl_rxq_stop); | |
493 | ||
c1354754 TW |
494 | void iwl_rx_missed_beacon_notif(struct iwl_priv *priv, |
495 | struct iwl_rx_mem_buffer *rxb) | |
496 | ||
497 | { | |
2f301227 | 498 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
2aa6ab86 | 499 | struct iwl_missed_beacon_notif *missed_beacon; |
c1354754 TW |
500 | |
501 | missed_beacon = &pkt->u.missed_beacon; | |
502 | if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) { | |
e1623446 | 503 | IWL_DEBUG_CALIB(priv, "missed bcn cnsq %d totl %d rcd %d expctd %d\n", |
c1354754 TW |
504 | le32_to_cpu(missed_beacon->consequtive_missed_beacons), |
505 | le32_to_cpu(missed_beacon->total_missed_becons), | |
506 | le32_to_cpu(missed_beacon->num_recvd_beacons), | |
507 | le32_to_cpu(missed_beacon->num_expected_beacons)); | |
508 | if (!test_bit(STATUS_SCANNING, &priv->status)) | |
509 | iwl_init_sensitivity(priv); | |
510 | } | |
c1354754 TW |
511 | } |
512 | EXPORT_SYMBOL(iwl_rx_missed_beacon_notif); | |
8f91aecb EG |
513 | |
514 | ||
515 | /* Calculate noise level, based on measurements during network silence just | |
516 | * before arriving beacon. This measurement can be done only if we know | |
517 | * exactly when to expect beacons, therefore only when we're associated. */ | |
518 | static void iwl_rx_calc_noise(struct iwl_priv *priv) | |
519 | { | |
520 | struct statistics_rx_non_phy *rx_info | |
521 | = &(priv->statistics.rx.general); | |
522 | int num_active_rx = 0; | |
523 | int total_silence = 0; | |
524 | int bcn_silence_a = | |
525 | le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER; | |
526 | int bcn_silence_b = | |
527 | le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER; | |
528 | int bcn_silence_c = | |
529 | le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER; | |
530 | ||
531 | if (bcn_silence_a) { | |
532 | total_silence += bcn_silence_a; | |
533 | num_active_rx++; | |
534 | } | |
535 | if (bcn_silence_b) { | |
536 | total_silence += bcn_silence_b; | |
537 | num_active_rx++; | |
538 | } | |
539 | if (bcn_silence_c) { | |
540 | total_silence += bcn_silence_c; | |
541 | num_active_rx++; | |
542 | } | |
543 | ||
544 | /* Average among active antennas */ | |
545 | if (num_active_rx) | |
546 | priv->last_rx_noise = (total_silence / num_active_rx) - 107; | |
547 | else | |
548 | priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE; | |
549 | ||
e1623446 | 550 | IWL_DEBUG_CALIB(priv, "inband silence a %u, b %u, c %u, dBm %d\n", |
8f91aecb EG |
551 | bcn_silence_a, bcn_silence_b, bcn_silence_c, |
552 | priv->last_rx_noise); | |
553 | } | |
554 | ||
92a35bda WYG |
555 | #ifdef CONFIG_IWLWIFI_DEBUG |
556 | /* | |
557 | * based on the assumption of all statistics counter are in DWORD | |
558 | * FIXME: This function is for debugging, do not deal with | |
559 | * the case of counters roll-over. | |
560 | */ | |
561 | static void iwl_accumulative_statistics(struct iwl_priv *priv, | |
562 | __le32 *stats) | |
563 | { | |
564 | int i; | |
565 | __le32 *prev_stats; | |
566 | u32 *accum_stats; | |
e3ef2164 | 567 | u32 *delta, *max_delta; |
92a35bda WYG |
568 | |
569 | prev_stats = (__le32 *)&priv->statistics; | |
570 | accum_stats = (u32 *)&priv->accum_statistics; | |
e3ef2164 WYG |
571 | delta = (u32 *)&priv->delta_statistics; |
572 | max_delta = (u32 *)&priv->max_delta; | |
92a35bda WYG |
573 | |
574 | for (i = sizeof(__le32); i < sizeof(struct iwl_notif_statistics); | |
e3ef2164 WYG |
575 | i += sizeof(__le32), stats++, prev_stats++, delta++, |
576 | max_delta++, accum_stats++) { | |
577 | if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) { | |
578 | *delta = (le32_to_cpu(*stats) - | |
92a35bda | 579 | le32_to_cpu(*prev_stats)); |
e3ef2164 WYG |
580 | *accum_stats += *delta; |
581 | if (*delta > *max_delta) | |
582 | *max_delta = *delta; | |
583 | } | |
584 | } | |
92a35bda WYG |
585 | |
586 | /* reset accumulative statistics for "no-counter" type statistics */ | |
587 | priv->accum_statistics.general.temperature = | |
588 | priv->statistics.general.temperature; | |
589 | priv->accum_statistics.general.temperature_m = | |
590 | priv->statistics.general.temperature_m; | |
591 | priv->accum_statistics.general.ttl_timestamp = | |
592 | priv->statistics.general.ttl_timestamp; | |
593 | priv->accum_statistics.tx.tx_power.ant_a = | |
594 | priv->statistics.tx.tx_power.ant_a; | |
595 | priv->accum_statistics.tx.tx_power.ant_b = | |
596 | priv->statistics.tx.tx_power.ant_b; | |
597 | priv->accum_statistics.tx.tx_power.ant_c = | |
598 | priv->statistics.tx.tx_power.ant_c; | |
599 | } | |
600 | #endif | |
601 | ||
8f91aecb EG |
602 | #define REG_RECALIB_PERIOD (60) |
603 | ||
604 | void iwl_rx_statistics(struct iwl_priv *priv, | |
605 | struct iwl_rx_mem_buffer *rxb) | |
606 | { | |
5225640b | 607 | int change; |
2f301227 | 608 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
8f91aecb | 609 | |
e1623446 | 610 | IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n", |
396887a2 DH |
611 | (int)sizeof(priv->statistics), |
612 | le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK); | |
8f91aecb | 613 | |
5225640b ZY |
614 | change = ((priv->statistics.general.temperature != |
615 | pkt->u.stats.general.temperature) || | |
616 | ((priv->statistics.flag & | |
7aafef1c WYG |
617 | STATISTICS_REPLY_FLG_HT40_MODE_MSK) != |
618 | (pkt->u.stats.flag & STATISTICS_REPLY_FLG_HT40_MODE_MSK))); | |
5225640b | 619 | |
92a35bda WYG |
620 | #ifdef CONFIG_IWLWIFI_DEBUG |
621 | iwl_accumulative_statistics(priv, (__le32 *)&pkt->u.stats); | |
622 | #endif | |
8f91aecb EG |
623 | memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics)); |
624 | ||
625 | set_bit(STATUS_STATISTICS, &priv->status); | |
626 | ||
627 | /* Reschedule the statistics timer to occur in | |
628 | * REG_RECALIB_PERIOD seconds to ensure we get a | |
629 | * thermal update even if the uCode doesn't give | |
630 | * us one */ | |
631 | mod_timer(&priv->statistics_periodic, jiffies + | |
632 | msecs_to_jiffies(REG_RECALIB_PERIOD * 1000)); | |
633 | ||
634 | if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) && | |
635 | (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) { | |
636 | iwl_rx_calc_noise(priv); | |
637 | queue_work(priv->workqueue, &priv->run_time_calib_work); | |
638 | } | |
62161aef WYG |
639 | if (priv->cfg->ops->lib->temp_ops.temperature && change) |
640 | priv->cfg->ops->lib->temp_ops.temperature(priv); | |
8f91aecb EG |
641 | } |
642 | EXPORT_SYMBOL(iwl_rx_statistics); | |
1781a07f | 643 | |
ef8d5529 WYG |
644 | void iwl_reply_statistics(struct iwl_priv *priv, |
645 | struct iwl_rx_mem_buffer *rxb) | |
646 | { | |
647 | struct iwl_rx_packet *pkt = rxb_addr(rxb); | |
648 | ||
649 | if (le32_to_cpu(pkt->u.stats.flag) & UCODE_STATISTICS_CLEAR_MSK) { | |
ef8d5529 WYG |
650 | #ifdef CONFIG_IWLWIFI_DEBUG |
651 | memset(&priv->accum_statistics, 0, | |
652 | sizeof(struct iwl_notif_statistics)); | |
e3ef2164 WYG |
653 | memset(&priv->delta_statistics, 0, |
654 | sizeof(struct iwl_notif_statistics)); | |
655 | memset(&priv->max_delta, 0, | |
656 | sizeof(struct iwl_notif_statistics)); | |
ef8d5529 WYG |
657 | #endif |
658 | IWL_DEBUG_RX(priv, "Statistics have been cleared\n"); | |
659 | } | |
660 | iwl_rx_statistics(priv, rxb); | |
661 | } | |
662 | EXPORT_SYMBOL(iwl_reply_statistics); | |
663 | ||
00e540b3 HD |
664 | /* Calc max signal level (dBm) among 3 possible receivers */ |
665 | static inline int iwl_calc_rssi(struct iwl_priv *priv, | |
666 | struct iwl_rx_phy_res *rx_resp) | |
667 | { | |
668 | return priv->cfg->ops->utils->calc_rssi(priv, rx_resp); | |
669 | } | |
1781a07f | 670 | |
00e540b3 | 671 | #ifdef CONFIG_IWLWIFI_DEBUG |
1781a07f EG |
672 | /** |
673 | * iwl_dbg_report_frame - dump frame to syslog during debug sessions | |
674 | * | |
675 | * You may hack this function to show different aspects of received frames, | |
676 | * including selective frame dumps. | |
00e540b3 HD |
677 | * group100 parameter selects whether to show 1 out of 100 good data frames. |
678 | * All beacon and probe response frames are printed. | |
1781a07f EG |
679 | */ |
680 | static void iwl_dbg_report_frame(struct iwl_priv *priv, | |
00e540b3 | 681 | struct iwl_rx_phy_res *phy_res, u16 length, |
1781a07f EG |
682 | struct ieee80211_hdr *header, int group100) |
683 | { | |
684 | u32 to_us; | |
685 | u32 print_summary = 0; | |
686 | u32 print_dump = 0; /* set to 1 to dump all frames' contents */ | |
687 | u32 hundred = 0; | |
688 | u32 dataframe = 0; | |
689 | __le16 fc; | |
690 | u16 seq_ctl; | |
691 | u16 channel; | |
692 | u16 phy_flags; | |
00e540b3 | 693 | u32 rate_n_flags; |
1781a07f | 694 | u32 tsf_low; |
00e540b3 | 695 | int rssi; |
1781a07f | 696 | |
3d816c77 | 697 | if (likely(!(iwl_get_debug_level(priv) & IWL_DL_RX))) |
1781a07f EG |
698 | return; |
699 | ||
700 | /* MAC header */ | |
701 | fc = header->frame_control; | |
702 | seq_ctl = le16_to_cpu(header->seq_ctrl); | |
703 | ||
704 | /* metadata */ | |
00e540b3 HD |
705 | channel = le16_to_cpu(phy_res->channel); |
706 | phy_flags = le16_to_cpu(phy_res->phy_flags); | |
707 | rate_n_flags = le32_to_cpu(phy_res->rate_n_flags); | |
1781a07f EG |
708 | |
709 | /* signal statistics */ | |
00e540b3 HD |
710 | rssi = iwl_calc_rssi(priv, phy_res); |
711 | tsf_low = le64_to_cpu(phy_res->timestamp) & 0x0ffffffff; | |
1781a07f EG |
712 | |
713 | to_us = !compare_ether_addr(header->addr1, priv->mac_addr); | |
714 | ||
715 | /* if data frame is to us and all is good, | |
716 | * (optionally) print summary for only 1 out of every 100 */ | |
717 | if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) == | |
718 | cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) { | |
719 | dataframe = 1; | |
720 | if (!group100) | |
721 | print_summary = 1; /* print each frame */ | |
722 | else if (priv->framecnt_to_us < 100) { | |
723 | priv->framecnt_to_us++; | |
724 | print_summary = 0; | |
725 | } else { | |
726 | priv->framecnt_to_us = 0; | |
727 | print_summary = 1; | |
728 | hundred = 1; | |
729 | } | |
730 | } else { | |
731 | /* print summary for all other frames */ | |
732 | print_summary = 1; | |
733 | } | |
734 | ||
735 | if (print_summary) { | |
736 | char *title; | |
737 | int rate_idx; | |
738 | u32 bitrate; | |
739 | ||
740 | if (hundred) | |
741 | title = "100Frames"; | |
742 | else if (ieee80211_has_retry(fc)) | |
743 | title = "Retry"; | |
744 | else if (ieee80211_is_assoc_resp(fc)) | |
745 | title = "AscRsp"; | |
746 | else if (ieee80211_is_reassoc_resp(fc)) | |
747 | title = "RasRsp"; | |
748 | else if (ieee80211_is_probe_resp(fc)) { | |
749 | title = "PrbRsp"; | |
750 | print_dump = 1; /* dump frame contents */ | |
751 | } else if (ieee80211_is_beacon(fc)) { | |
752 | title = "Beacon"; | |
753 | print_dump = 1; /* dump frame contents */ | |
754 | } else if (ieee80211_is_atim(fc)) | |
755 | title = "ATIM"; | |
756 | else if (ieee80211_is_auth(fc)) | |
757 | title = "Auth"; | |
758 | else if (ieee80211_is_deauth(fc)) | |
759 | title = "DeAuth"; | |
760 | else if (ieee80211_is_disassoc(fc)) | |
761 | title = "DisAssoc"; | |
762 | else | |
763 | title = "Frame"; | |
764 | ||
00e540b3 HD |
765 | rate_idx = iwl_hwrate_to_plcp_idx(rate_n_flags); |
766 | if (unlikely((rate_idx < 0) || (rate_idx >= IWL_RATE_COUNT))) { | |
1781a07f | 767 | bitrate = 0; |
00e540b3 HD |
768 | WARN_ON_ONCE(1); |
769 | } else { | |
1781a07f | 770 | bitrate = iwl_rates[rate_idx].ieee / 2; |
00e540b3 | 771 | } |
1781a07f EG |
772 | |
773 | /* print frame summary. | |
774 | * MAC addresses show just the last byte (for brevity), | |
775 | * but you can hack it to show more, if you'd like to. */ | |
776 | if (dataframe) | |
e1623446 | 777 | IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, " |
1781a07f EG |
778 | "len=%u, rssi=%d, chnl=%d, rate=%u, \n", |
779 | title, le16_to_cpu(fc), header->addr1[5], | |
780 | length, rssi, channel, bitrate); | |
781 | else { | |
782 | /* src/dst addresses assume managed mode */ | |
e1623446 | 783 | IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, src=0x%02x, " |
00e540b3 | 784 | "len=%u, rssi=%d, tim=%lu usec, " |
1781a07f EG |
785 | "phy=0x%02x, chnl=%d\n", |
786 | title, le16_to_cpu(fc), header->addr1[5], | |
00e540b3 | 787 | header->addr3[5], length, rssi, |
1781a07f EG |
788 | tsf_low - priv->scan_start_tsf, |
789 | phy_flags, channel); | |
790 | } | |
791 | } | |
792 | if (print_dump) | |
3d816c77 | 793 | iwl_print_hex_dump(priv, IWL_DL_RX, header, length); |
1781a07f | 794 | } |
1781a07f EG |
795 | #endif |
796 | ||
1781a07f EG |
797 | /* |
798 | * returns non-zero if packet should be dropped | |
799 | */ | |
8ccde88a SO |
800 | int iwl_set_decrypted_flag(struct iwl_priv *priv, |
801 | struct ieee80211_hdr *hdr, | |
802 | u32 decrypt_res, | |
803 | struct ieee80211_rx_status *stats) | |
1781a07f EG |
804 | { |
805 | u16 fc = le16_to_cpu(hdr->frame_control); | |
806 | ||
807 | if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK) | |
808 | return 0; | |
809 | ||
810 | if (!(fc & IEEE80211_FCTL_PROTECTED)) | |
811 | return 0; | |
812 | ||
e1623446 | 813 | IWL_DEBUG_RX(priv, "decrypt_res:0x%x\n", decrypt_res); |
1781a07f EG |
814 | switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) { |
815 | case RX_RES_STATUS_SEC_TYPE_TKIP: | |
816 | /* The uCode has got a bad phase 1 Key, pushes the packet. | |
817 | * Decryption will be done in SW. */ | |
818 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
819 | RX_RES_STATUS_BAD_KEY_TTAK) | |
820 | break; | |
821 | ||
822 | case RX_RES_STATUS_SEC_TYPE_WEP: | |
823 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
824 | RX_RES_STATUS_BAD_ICV_MIC) { | |
825 | /* bad ICV, the packet is destroyed since the | |
826 | * decryption is inplace, drop it */ | |
e1623446 | 827 | IWL_DEBUG_RX(priv, "Packet destroyed\n"); |
1781a07f EG |
828 | return -1; |
829 | } | |
830 | case RX_RES_STATUS_SEC_TYPE_CCMP: | |
831 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
832 | RX_RES_STATUS_DECRYPT_OK) { | |
e1623446 | 833 | IWL_DEBUG_RX(priv, "hw decrypt successfully!!!\n"); |
1781a07f EG |
834 | stats->flag |= RX_FLAG_DECRYPTED; |
835 | } | |
836 | break; | |
837 | ||
838 | default: | |
839 | break; | |
840 | } | |
841 | return 0; | |
842 | } | |
8ccde88a | 843 | EXPORT_SYMBOL(iwl_set_decrypted_flag); |
1781a07f EG |
844 | |
845 | static u32 iwl_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in) | |
846 | { | |
847 | u32 decrypt_out = 0; | |
848 | ||
849 | if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) == | |
850 | RX_RES_STATUS_STATION_FOUND) | |
851 | decrypt_out |= (RX_RES_STATUS_STATION_FOUND | | |
852 | RX_RES_STATUS_NO_STATION_INFO_MISMATCH); | |
853 | ||
854 | decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK); | |
855 | ||
856 | /* packet was not encrypted */ | |
857 | if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) == | |
858 | RX_RES_STATUS_SEC_TYPE_NONE) | |
859 | return decrypt_out; | |
860 | ||
861 | /* packet was encrypted with unknown alg */ | |
862 | if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) == | |
863 | RX_RES_STATUS_SEC_TYPE_ERR) | |
864 | return decrypt_out; | |
865 | ||
866 | /* decryption was not done in HW */ | |
867 | if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) != | |
868 | RX_MPDU_RES_STATUS_DEC_DONE_MSK) | |
869 | return decrypt_out; | |
870 | ||
871 | switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) { | |
872 | ||
873 | case RX_RES_STATUS_SEC_TYPE_CCMP: | |
874 | /* alg is CCM: check MIC only */ | |
875 | if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK)) | |
876 | /* Bad MIC */ | |
877 | decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC; | |
878 | else | |
879 | decrypt_out |= RX_RES_STATUS_DECRYPT_OK; | |
880 | ||
881 | break; | |
882 | ||
883 | case RX_RES_STATUS_SEC_TYPE_TKIP: | |
884 | if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) { | |
885 | /* Bad TTAK */ | |
886 | decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK; | |
887 | break; | |
888 | } | |
889 | /* fall through if TTAK OK */ | |
890 | default: | |
891 | if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK)) | |
892 | decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC; | |
893 | else | |
894 | decrypt_out |= RX_RES_STATUS_DECRYPT_OK; | |
895 | break; | |
896 | }; | |
897 | ||
e1623446 | 898 | IWL_DEBUG_RX(priv, "decrypt_in:0x%x decrypt_out = 0x%x\n", |
1781a07f EG |
899 | decrypt_in, decrypt_out); |
900 | ||
901 | return decrypt_out; | |
902 | } | |
903 | ||
4b8817b2 | 904 | static void iwl_pass_packet_to_mac80211(struct iwl_priv *priv, |
9f30e04e DH |
905 | struct ieee80211_hdr *hdr, |
906 | u16 len, | |
907 | u32 ampdu_status, | |
908 | struct iwl_rx_mem_buffer *rxb, | |
909 | struct ieee80211_rx_status *stats) | |
1781a07f | 910 | { |
2f301227 ZY |
911 | struct sk_buff *skb; |
912 | int ret = 0; | |
29b1b268 | 913 | __le16 fc = hdr->frame_control; |
2f301227 | 914 | |
1781a07f EG |
915 | /* We only process data packets if the interface is open */ |
916 | if (unlikely(!priv->is_open)) { | |
e1623446 TW |
917 | IWL_DEBUG_DROP_LIMIT(priv, |
918 | "Dropping packet while interface is not open.\n"); | |
1781a07f EG |
919 | return; |
920 | } | |
921 | ||
9f30e04e | 922 | /* In case of HW accelerated crypto and bad decryption, drop */ |
90e8e424 | 923 | if (!priv->cfg->mod_params->sw_crypto && |
1781a07f EG |
924 | iwl_set_decrypted_flag(priv, hdr, ampdu_status, stats)) |
925 | return; | |
926 | ||
a3b6bd5b | 927 | skb = alloc_skb(IWL_LINK_HDR_MAX * 2, GFP_ATOMIC); |
2f301227 ZY |
928 | if (!skb) { |
929 | IWL_ERR(priv, "alloc_skb failed\n"); | |
930 | return; | |
931 | } | |
932 | ||
a3b6bd5b | 933 | skb_reserve(skb, IWL_LINK_HDR_MAX); |
2f301227 ZY |
934 | skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len); |
935 | ||
936 | /* mac80211 currently doesn't support paged SKB. Convert it to | |
937 | * linear SKB for management frame and data frame requires | |
938 | * software decryption or software defragementation. */ | |
29b1b268 ZY |
939 | if (ieee80211_is_mgmt(fc) || |
940 | ieee80211_has_protected(fc) || | |
941 | ieee80211_has_morefrags(fc) || | |
2f301227 ZY |
942 | le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) |
943 | ret = skb_linearize(skb); | |
944 | else | |
945 | ret = __pskb_pull_tail(skb, min_t(u16, IWL_LINK_HDR_MAX, len)) ? | |
946 | 0 : -ENOMEM; | |
947 | ||
948 | if (ret) { | |
949 | kfree_skb(skb); | |
950 | goto out; | |
951 | } | |
9f30e04e | 952 | |
29b1b268 ZY |
953 | /* |
954 | * XXX: We cannot touch the page and its virtual memory (hdr) after | |
955 | * here. It might have already been freed by the above skb change. | |
956 | */ | |
957 | ||
958 | iwl_update_stats(priv, false, fc, len); | |
2f301227 ZY |
959 | memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats)); |
960 | ||
961 | ieee80211_rx(priv->hw, skb); | |
962 | out: | |
963 | priv->alloc_rxb_page--; | |
964 | rxb->page = NULL; | |
1781a07f EG |
965 | } |
966 | ||
4b8817b2 | 967 | /* This is necessary only for a number of statistics, see the caller. */ |
1781a07f EG |
968 | static int iwl_is_network_packet(struct iwl_priv *priv, |
969 | struct ieee80211_hdr *header) | |
970 | { | |
971 | /* Filter incoming packets to determine if they are targeted toward | |
972 | * this network, discarding packets coming from ourselves */ | |
973 | switch (priv->iw_mode) { | |
05c914fe | 974 | case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */ |
4b8817b2 EG |
975 | /* packets to our IBSS update information */ |
976 | return !compare_ether_addr(header->addr3, priv->bssid); | |
05c914fe | 977 | case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */ |
4b8817b2 EG |
978 | /* packets to our IBSS update information */ |
979 | return !compare_ether_addr(header->addr2, priv->bssid); | |
1781a07f | 980 | default: |
4b8817b2 | 981 | return 1; |
1781a07f | 982 | } |
1781a07f EG |
983 | } |
984 | ||
985 | /* Called for REPLY_RX (legacy ABG frames), or | |
986 | * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */ | |
987 | void iwl_rx_reply_rx(struct iwl_priv *priv, | |
988 | struct iwl_rx_mem_buffer *rxb) | |
989 | { | |
990 | struct ieee80211_hdr *header; | |
991 | struct ieee80211_rx_status rx_status; | |
2f301227 | 992 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
9f30e04e DH |
993 | struct iwl_rx_phy_res *phy_res; |
994 | __le32 rx_pkt_status; | |
995 | struct iwl4965_rx_mpdu_res_start *amsdu; | |
996 | u32 len; | |
997 | u32 ampdu_status; | |
c5f8cdb7 | 998 | u32 rate_n_flags; |
1781a07f | 999 | |
9f30e04e DH |
1000 | /** |
1001 | * REPLY_RX and REPLY_RX_MPDU_CMD are handled differently. | |
1002 | * REPLY_RX: physical layer info is in this buffer | |
1003 | * REPLY_RX_MPDU_CMD: physical layer info was sent in separate | |
1004 | * command and cached in priv->last_phy_res | |
1005 | * | |
1006 | * Here we set up local variables depending on which command is | |
1007 | * received. | |
1008 | */ | |
1009 | if (pkt->hdr.cmd == REPLY_RX) { | |
1010 | phy_res = (struct iwl_rx_phy_res *)pkt->u.raw; | |
1011 | header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res) | |
1012 | + phy_res->cfg_phy_cnt); | |
1013 | ||
1014 | len = le16_to_cpu(phy_res->byte_count); | |
1015 | rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*phy_res) + | |
1016 | phy_res->cfg_phy_cnt + len); | |
1017 | ampdu_status = le32_to_cpu(rx_pkt_status); | |
1018 | } else { | |
1019 | if (!priv->last_phy_res[0]) { | |
1020 | IWL_ERR(priv, "MPDU frame without cached PHY data\n"); | |
1021 | return; | |
1022 | } | |
1023 | phy_res = (struct iwl_rx_phy_res *)&priv->last_phy_res[1]; | |
1024 | amsdu = (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw; | |
1025 | header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu)); | |
1026 | len = le16_to_cpu(amsdu->byte_count); | |
1027 | rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*amsdu) + len); | |
1028 | ampdu_status = iwl_translate_rx_status(priv, | |
1029 | le32_to_cpu(rx_pkt_status)); | |
1030 | } | |
1031 | ||
1032 | if ((unlikely(phy_res->cfg_phy_cnt > 20))) { | |
1033 | IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n", | |
1034 | phy_res->cfg_phy_cnt); | |
1035 | return; | |
1036 | } | |
1037 | ||
1038 | if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) || | |
1039 | !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) { | |
1040 | IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", | |
1041 | le32_to_cpu(rx_pkt_status)); | |
1042 | return; | |
1043 | } | |
1044 | ||
31513be8 DH |
1045 | /* This will be used in several places later */ |
1046 | rate_n_flags = le32_to_cpu(phy_res->rate_n_flags); | |
1047 | ||
9f30e04e DH |
1048 | /* rx_status carries information about the packet to mac80211 */ |
1049 | rx_status.mactime = le64_to_cpu(phy_res->timestamp); | |
1781a07f | 1050 | rx_status.freq = |
9f30e04e DH |
1051 | ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel)); |
1052 | rx_status.band = (phy_res->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ? | |
1781a07f EG |
1053 | IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ; |
1054 | rx_status.rate_idx = | |
31513be8 | 1055 | iwl_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band); |
1781a07f | 1056 | rx_status.flag = 0; |
b94d8eea AK |
1057 | |
1058 | /* TSF isn't reliable. In order to allow smooth user experience, | |
1059 | * this W/A doesn't propagate it to the mac80211 */ | |
1060 | /*rx_status.flag |= RX_FLAG_TSFT;*/ | |
1781a07f | 1061 | |
9f30e04e | 1062 | priv->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp); |
1781a07f EG |
1063 | |
1064 | /* Find max signal strength (dBm) among 3 antenna/receiver chains */ | |
9f30e04e | 1065 | rx_status.signal = iwl_calc_rssi(priv, phy_res); |
1781a07f EG |
1066 | |
1067 | /* Meaningful noise values are available only from beacon statistics, | |
1068 | * which are gathered only when associated, and indicate noise | |
1069 | * only for the associated network channel ... | |
1070 | * Ignore these noise values while scanning (other channels) */ | |
1071 | if (iwl_is_associated(priv) && | |
1072 | !test_bit(STATUS_SCANNING, &priv->status)) { | |
1073 | rx_status.noise = priv->last_rx_noise; | |
1781a07f EG |
1074 | } else { |
1075 | rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE; | |
1781a07f EG |
1076 | } |
1077 | ||
1078 | /* Reset beacon noise level if not associated. */ | |
1079 | if (!iwl_is_associated(priv)) | |
1080 | priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE; | |
1081 | ||
21a49fc6 | 1082 | #ifdef CONFIG_IWLWIFI_DEBUG |
9f30e04e | 1083 | /* Set "1" to report good data frames in groups of 100 */ |
3d816c77 | 1084 | if (unlikely(iwl_get_debug_level(priv) & IWL_DL_RX)) |
9f30e04e | 1085 | iwl_dbg_report_frame(priv, phy_res, len, header, 1); |
21a49fc6 | 1086 | #endif |
20594eb0 | 1087 | iwl_dbg_log_rx_data_frame(priv, len, header); |
671adc93 JB |
1088 | IWL_DEBUG_STATS_LIMIT(priv, "Rssi %d, noise %d, TSF %llu\n", |
1089 | rx_status.signal, rx_status.noise, | |
1781a07f EG |
1090 | (unsigned long long)rx_status.mactime); |
1091 | ||
6f0a2c4d BR |
1092 | /* |
1093 | * "antenna number" | |
1094 | * | |
1095 | * It seems that the antenna field in the phy flags value | |
a96a27f9 | 1096 | * is actually a bit field. This is undefined by radiotap, |
6f0a2c4d BR |
1097 | * it wants an actual antenna number but I always get "7" |
1098 | * for most legacy frames I receive indicating that the | |
1099 | * same frame was received on all three RX chains. | |
1100 | * | |
a96a27f9 | 1101 | * I think this field should be removed in favor of a |
6f0a2c4d BR |
1102 | * new 802.11n radiotap field "RX chains" that is defined |
1103 | * as a bitmask. | |
1104 | */ | |
9f30e04e | 1105 | rx_status.antenna = |
9024adf5 | 1106 | (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK) |
9f30e04e | 1107 | >> RX_RES_PHY_FLAGS_ANTENNA_POS; |
6f0a2c4d BR |
1108 | |
1109 | /* set the preamble flag if appropriate */ | |
9f30e04e | 1110 | if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK) |
6f0a2c4d BR |
1111 | rx_status.flag |= RX_FLAG_SHORTPRE; |
1112 | ||
c5f8cdb7 | 1113 | /* Set up the HT phy flags */ |
c5f8cdb7 DH |
1114 | if (rate_n_flags & RATE_MCS_HT_MSK) |
1115 | rx_status.flag |= RX_FLAG_HT; | |
1116 | if (rate_n_flags & RATE_MCS_HT40_MSK) | |
1117 | rx_status.flag |= RX_FLAG_40MHZ; | |
1118 | if (rate_n_flags & RATE_MCS_SGI_MSK) | |
1119 | rx_status.flag |= RX_FLAG_SHORT_GI; | |
1120 | ||
9f30e04e | 1121 | if (iwl_is_network_packet(priv, header)) { |
1781a07f EG |
1122 | priv->last_rx_rssi = rx_status.signal; |
1123 | priv->last_beacon_time = priv->ucode_beacon_time; | |
9f30e04e | 1124 | priv->last_tsf = le64_to_cpu(phy_res->timestamp); |
1781a07f EG |
1125 | } |
1126 | ||
6ab10ff8 JB |
1127 | iwl_pass_packet_to_mac80211(priv, header, len, ampdu_status, |
1128 | rxb, &rx_status); | |
1781a07f EG |
1129 | } |
1130 | EXPORT_SYMBOL(iwl_rx_reply_rx); | |
1131 | ||
1132 | /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD). | |
1133 | * This will be used later in iwl_rx_reply_rx() for REPLY_RX_MPDU_CMD. */ | |
1134 | void iwl_rx_reply_rx_phy(struct iwl_priv *priv, | |
1135 | struct iwl_rx_mem_buffer *rxb) | |
1136 | { | |
2f301227 | 1137 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
1781a07f EG |
1138 | priv->last_phy_res[0] = 1; |
1139 | memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]), | |
caab8f1a | 1140 | sizeof(struct iwl_rx_phy_res)); |
1781a07f EG |
1141 | } |
1142 | EXPORT_SYMBOL(iwl_rx_reply_rx_phy); |