[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-trans-int-pcie.h

/******************************************************************************
 *
 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
 *
 * Portions of this file are derived from the ipw3945 project, as well
 * as portions of the ieee80211 subsystem header files.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
 *
 * The full GNU General Public License is included in this distribution in the
 * file called LICENSE.
 *
 * Contact Information:
 *  Intel Linux Wireless <ilw@linux.intel.com>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *
 *****************************************************************************/
#ifndef __iwl_trans_int_pcie_h__
#define __iwl_trans_int_pcie_h__

#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/skbuff.h>

#include "iwl-fh.h"
#include "iwl-csr.h"
#include "iwl-shared.h"
#include "iwl-trans.h"
#include "iwl-debug.h"
#include "iwl-io.h"

struct iwl_tx_queue;
struct iwl_queue;
struct iwl_host_cmd;

/*This file includes the declaration that are internal to the
 * trans_pcie layer */

/**
 * struct isr_statistics - interrupt statistics
 *
 */
struct isr_statistics {
	u32 hw;
	u32 sw;
	u32 err_code;
	u32 sch;
	u32 alive;
	u32 rfkill;
	u32 ctkill;
	u32 wakeup;
	u32 rx;
	u32 tx;
	u32 unhandled;
};

/**
 * struct iwl_rx_queue - Rx queue
 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
 * @pool:
 * @queue:
 * @read: Shared index to newest available Rx buffer
 * @write: Shared index to oldest written Rx packet
 * @free_count: Number of pre-allocated buffers in rx_free
 * @write_actual:
 * @rx_free: list of free SKBs for use
 * @rx_used: List of Rx buffers with no SKB
 * @need_update: flag to indicate we need to update read/write index
 * @rb_stts: driver's pointer to receive buffer status
 * @rb_stts_dma: bus address of receive buffer status
 * @lock:
 *
 * NOTE:  rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
 */
struct iwl_rx_queue {
	__le32 *bd;
	dma_addr_t bd_dma;
	struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
	struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
	u32 read;
	u32 write;
	u32 free_count;
	u32 write_actual;
	struct list_head rx_free;
	struct list_head rx_used;
	int need_update;
	struct iwl_rb_status *rb_stts;
	dma_addr_t rb_stts_dma;
	spinlock_t lock;
};

struct iwl_dma_ptr {
	dma_addr_t dma;
	void *addr;
	size_t size;
};

/*
 * This queue number is required for proper operation
 * because the ucode will stop/start the scheduler as
 * required.
 */
#define IWL_IPAN_MCAST_QUEUE		8

/**
 * struct iwl_trans_pcie - PCIe transport specific data
 * @rxq: all the RX queue data
 * @rx_replenish: work that will be called when buffers need to be allocated
 * @trans: pointer to the generic transport area
 * @scd_base_addr: scheduler sram base address in SRAM
 * @scd_bc_tbls: pointer to the byte count table of the scheduler
 * @kw: keep warm address
 * @ac_to_fifo: to what fifo is a specifc AC mapped ?
 * @ac_to_queue: to what tx queue  is a specifc AC mapped ?
 * @mcast_queue:
 * @txq: Tx DMA processing queues
 * @txq_ctx_active_msk: what queue is active
 * queue_stopped: tracks what queue is stopped
 * queue_stop_count: tracks what SW queue is stopped
 */
struct iwl_trans_pcie {
	struct iwl_rx_queue rxq;
	struct work_struct rx_replenish;
	struct iwl_trans *trans;

	/* INT ICT Table */
	__le32 *ict_tbl;
	void *ict_tbl_vir;
	dma_addr_t ict_tbl_dma;
	dma_addr_t aligned_ict_tbl_dma;
	int ict_index;
	u32 inta;
	bool use_ict;
	struct tasklet_struct irq_tasklet;
	struct isr_statistics isr_stats;

	u32 inta_mask;
	u32 scd_base_addr;
	struct iwl_dma_ptr scd_bc_tbls;
	struct iwl_dma_ptr kw;

	const u8 *ac_to_fifo[NUM_IWL_RXON_CTX];
	const u8 *ac_to_queue[NUM_IWL_RXON_CTX];
	u8 mcast_queue[NUM_IWL_RXON_CTX];

	struct iwl_tx_queue *txq;
	unsigned long txq_ctx_active_msk;
#define IWL_MAX_HW_QUEUES	32
	unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
	atomic_t queue_stop_count[4];
};

#define IWL_TRANS_GET_PCIE_TRANS(_iwl_trans) \
	((struct iwl_trans_pcie *) ((_iwl_trans)->trans_specific))

/*****************************************************
* RX
******************************************************/
void iwl_bg_rx_replenish(struct work_struct *data);
void iwl_irq_tasklet(struct iwl_trans *trans);
void iwlagn_rx_replenish(struct iwl_trans *trans);
void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
			struct iwl_rx_queue *q);

/*****************************************************
* ICT
******************************************************/
int iwl_reset_ict(struct iwl_trans *trans);
void iwl_disable_ict(struct iwl_trans *trans);
int iwl_alloc_isr_ict(struct iwl_trans *trans);
void iwl_free_isr_ict(struct iwl_trans *trans);
irqreturn_t iwl_isr_ict(int irq, void *data);

/*****************************************************
* TX / HCMD
******************************************************/
void iwl_txq_update_write_ptr(struct iwl_trans *trans,
			struct iwl_tx_queue *txq);
int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans,
				 struct iwl_tx_queue *txq,
				 dma_addr_t addr, u16 len, u8 reset);
int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id);
int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
int __must_check iwl_trans_pcie_send_cmd_pdu(struct iwl_trans *trans, u8 id,
			u32 flags, u16 len, const void *data);
void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb);
void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
					   struct iwl_tx_queue *txq,
					   u16 byte_cnt);
void iwl_trans_pcie_txq_agg_disable(struct iwl_trans *trans, int txq_id);
int iwl_trans_pcie_tx_agg_disable(struct iwl_trans *trans,
				  enum iwl_rxon_context_id ctx, int sta_id,
				  int tid);
void iwl_trans_set_wr_ptrs(struct iwl_trans *trans, int txq_id, u32 index);
void iwl_trans_tx_queue_set_status(struct iwl_trans *trans,
			     struct iwl_tx_queue *txq,
			     int tx_fifo_id, int scd_retry);
int iwl_trans_pcie_tx_agg_alloc(struct iwl_trans *trans,
				enum iwl_rxon_context_id ctx, int sta_id,
				int tid, u16 *ssn);
void iwl_trans_pcie_tx_agg_setup(struct iwl_trans *trans,
				 enum iwl_rxon_context_id ctx,
				 int sta_id, int tid, int frame_limit);
void iwlagn_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq,
	int index);
int iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index,
			 struct sk_buff_head *skbs);
int iwl_queue_space(const struct iwl_queue *q);

/*****************************************************
* Error handling
******************************************************/
int iwl_dump_nic_event_log(struct iwl_trans *trans, bool full_log,
			    char **buf, bool display);
int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display);
void iwl_dump_csr(struct iwl_trans *trans);

/*****************************************************
* Helpers
******************************************************/
static inline void iwl_disable_interrupts(struct iwl_trans *trans)
{
	clear_bit(STATUS_INT_ENABLED, &trans->shrd->status);

	/* disable interrupts from uCode/NIC to host */
	iwl_write32(bus(trans), CSR_INT_MASK, 0x00000000);

	/* acknowledge/clear/reset any interrupts still pending
	 * from uCode or flow handler (Rx/Tx DMA) */
	iwl_write32(bus(trans), CSR_INT, 0xffffffff);
	iwl_write32(bus(trans), CSR_FH_INT_STATUS, 0xffffffff);
	IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
}

static inline void iwl_enable_interrupts(struct iwl_trans *trans)
{
	struct iwl_trans_pcie *trans_pcie =
		IWL_TRANS_GET_PCIE_TRANS(trans);

	IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
	set_bit(STATUS_INT_ENABLED, &trans->shrd->status);
	iwl_write32(bus(trans), CSR_INT_MASK, trans_pcie->inta_mask);
}

/*
 * we have 8 bits used like this:
 *
 * 7 6 5 4 3 2 1 0
 * | | | | | | | |
 * | | | | | | +-+-------- AC queue (0-3)
 * | | | | | |
 * | +-+-+-+-+------------ HW queue ID
 * |
 * +---------------------- unused
 */
static inline void iwl_set_swq_id(struct iwl_tx_queue *txq, u8 ac, u8 hwq)
{
	BUG_ON(ac > 3);   /* only have 2 bits */
	BUG_ON(hwq > 31); /* only use 5 bits */

	txq->swq_id = (hwq << 2) | ac;
}

static inline void iwl_wake_queue(struct iwl_trans *trans,
				  struct iwl_tx_queue *txq)
{
	u8 queue = txq->swq_id;
	u8 ac = queue & 3;
	u8 hwq = (queue >> 2) & 0x1f;
	struct iwl_trans_pcie *trans_pcie =
		IWL_TRANS_GET_PCIE_TRANS(trans);

	if (unlikely(!trans->shrd->mac80211_registered))
		return;

	if (test_and_clear_bit(hwq, trans_pcie->queue_stopped))
		if (atomic_dec_return(&trans_pcie->queue_stop_count[ac]) <= 0)
			ieee80211_wake_queue(trans->shrd->hw, ac);
}

static inline void iwl_stop_queue(struct iwl_trans *trans,
				  struct iwl_tx_queue *txq)
{
	u8 queue = txq->swq_id;
	u8 ac = queue & 3;
	u8 hwq = (queue >> 2) & 0x1f;
	struct iwl_trans_pcie *trans_pcie =
		IWL_TRANS_GET_PCIE_TRANS(trans);

	if (unlikely(!trans->shrd->mac80211_registered))
		return;

	if (!test_and_set_bit(hwq, trans_pcie->queue_stopped))
		if (atomic_inc_return(&trans_pcie->queue_stop_count[ac]) > 0)
			ieee80211_stop_queue(trans->shrd->hw, ac);
}

#ifdef ieee80211_stop_queue
#undef ieee80211_stop_queue
#endif

#define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue

#ifdef ieee80211_wake_queue
#undef ieee80211_wake_queue
#endif

#define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue

static inline void iwl_txq_ctx_activate(struct iwl_trans_pcie *trans_pcie,
					int txq_id)
{
	set_bit(txq_id, &trans_pcie->txq_ctx_active_msk);
}

static inline void iwl_txq_ctx_deactivate(struct iwl_trans_pcie *trans_pcie,
					  int txq_id)
{
	clear_bit(txq_id, &trans_pcie->txq_ctx_active_msk);
}

static inline int iwl_queue_used(const struct iwl_queue *q, int i)
{
	return q->write_ptr >= q->read_ptr ?
		(i >= q->read_ptr && i < q->write_ptr) :
		!(i < q->read_ptr && i >= q->write_ptr);
}

static inline u8 get_cmd_index(struct iwl_queue *q, u32 index)
{
	return index & (q->n_window - 1);
}

#endif /* __iwl_trans_int_pcie_h__ */
Commit	Line	Data
ab697a9f EG	1	/******************************************************************************
	2	*
	3	* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
	4	*
	5	* Portions of this file are derived from the ipw3945 project, as well
	6	* as portions of the ieee80211 subsystem header files.
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of version 2 of the GNU General Public License as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	15	* more details.
	16	*
	17	* You should have received a copy of the GNU General Public License along with
	18	* this program; if not, write to the Free Software Foundation, Inc.,
	19	* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
	20	*
	21	* The full GNU General Public License is included in this distribution in the
	22	* file called LICENSE.
	23	*
	24	* Contact Information:
	25	* Intel Linux Wireless <ilw@linux.intel.com>
	26	* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	27	*
	28	*****************************************************************************/
	29	#ifndef __iwl_trans_int_pcie_h__
	30	#define __iwl_trans_int_pcie_h__
	31
a72b8b08 EG	32	#include <linux/spinlock.h>
	33	#include <linux/interrupt.h>
	34	#include <linux/skbuff.h>
	35
dda61a44	36	#include "iwl-fh.h"
a72b8b08 EG	37	#include "iwl-csr.h"
	38	#include "iwl-shared.h"
	39	#include "iwl-trans.h"
	40	#include "iwl-debug.h"
	41	#include "iwl-io.h"
	42
	43	struct iwl_tx_queue;
	44	struct iwl_queue;
	45	struct iwl_host_cmd;
dda61a44	46
ab697a9f EG	47	/*This file includes the declaration that are internal to the
	48	* trans_pcie layer */
	49
1f7b6172 EG	50	/**
	51	* struct isr_statistics - interrupt statistics
	52	*
	53	*/
	54	struct isr_statistics {
	55	u32 hw;
	56	u32 sw;
	57	u32 err_code;
	58	u32 sch;
	59	u32 alive;
	60	u32 rfkill;
	61	u32 ctkill;
	62	u32 wakeup;
	63	u32 rx;
	64	u32 tx;
	65	u32 unhandled;
	66	};
	67
5a878bf6 EG	68	/**
	69	* struct iwl_rx_queue - Rx queue
	70	* @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
	71	* @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
	72	* @pool:
	73	* @queue:
	74	* @read: Shared index to newest available Rx buffer
	75	* @write: Shared index to oldest written Rx packet
	76	* @free_count: Number of pre-allocated buffers in rx_free
	77	* @write_actual:
	78	* @rx_free: list of free SKBs for use
	79	* @rx_used: List of Rx buffers with no SKB
	80	* @need_update: flag to indicate we need to update read/write index
	81	* @rb_stts: driver's pointer to receive buffer status
	82	* @rb_stts_dma: bus address of receive buffer status
	83	* @lock:
	84	*
	85	* NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
	86	*/
	87	struct iwl_rx_queue {
	88	__le32 *bd;
	89	dma_addr_t bd_dma;
	90	struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
	91	struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
	92	u32 read;
	93	u32 write;
	94	u32 free_count;
	95	u32 write_actual;
	96	struct list_head rx_free;
	97	struct list_head rx_used;
	98	int need_update;
	99	struct iwl_rb_status *rb_stts;
	100	dma_addr_t rb_stts_dma;
	101	spinlock_t lock;
	102	};
	103
a72b8b08 EG	104	struct iwl_dma_ptr {
	105	dma_addr_t dma;
	106	void *addr;
	107	size_t size;
	108	};
	109
e13c0c59 EG	110	/*
	111	* This queue number is required for proper operation
	112	* because the ucode will stop/start the scheduler as
	113	* required.
	114	*/
	115	#define IWL_IPAN_MCAST_QUEUE 8
	116
e6bb4c9c EG	117	/**
e6bb4c9c EG	118	* struct iwl_trans_pcie - PCIe transport specific data
5a878bf6 EG	119	* @rxq: all the RX queue data
	120	* @rx_replenish: work that will be called when buffers need to be allocated
	121	* @trans: pointer to the generic transport area
105183b1 EG	122	* @scd_base_addr: scheduler sram base address in SRAM
105183b1 EG	123	* @scd_bc_tbls: pointer to the byte count table of the scheduler
9d6b2cb1	124	* @kw: keep warm address
e13c0c59 EG	125	* @ac_to_fifo: to what fifo is a specifc AC mapped ?
	126	* @ac_to_queue: to what tx queue is a specifc AC mapped ?
	127	* @mcast_queue:
8ad71bef EG	128	* @txq: Tx DMA processing queues
	129	* @txq_ctx_active_msk: what queue is active
	130	* queue_stopped: tracks what queue is stopped
	131	* queue_stop_count: tracks what SW queue is stopped
e6bb4c9c EG	132	*/
e6bb4c9c EG	133	struct iwl_trans_pcie {
5a878bf6 EG	134	struct iwl_rx_queue rxq;
	135	struct work_struct rx_replenish;
	136	struct iwl_trans *trans;
0c325769 EG	137
	138	/* INT ICT Table */
	139	__le32 *ict_tbl;
	140	void *ict_tbl_vir;
	141	dma_addr_t ict_tbl_dma;
	142	dma_addr_t aligned_ict_tbl_dma;
	143	int ict_index;
	144	u32 inta;
	145	bool use_ict;
	146	struct tasklet_struct irq_tasklet;
1f7b6172	147	struct isr_statistics isr_stats;
0c325769 EG	148
0c325769 EG	149	u32 inta_mask;
105183b1 EG	150	u32 scd_base_addr;
105183b1 EG	151	struct iwl_dma_ptr scd_bc_tbls;
9d6b2cb1	152	struct iwl_dma_ptr kw;
e13c0c59 EG	153
	154	const u8 *ac_to_fifo[NUM_IWL_RXON_CTX];
	155	const u8 *ac_to_queue[NUM_IWL_RXON_CTX];
	156	u8 mcast_queue[NUM_IWL_RXON_CTX];
8ad71bef EG	157
	158	struct iwl_tx_queue *txq;
	159	unsigned long txq_ctx_active_msk;
	160	#define IWL_MAX_HW_QUEUES 32
	161	unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
	162	atomic_t queue_stop_count[4];
e6bb4c9c EG	163	};
e6bb4c9c EG	164
5a878bf6 EG	165	#define IWL_TRANS_GET_PCIE_TRANS(_iwl_trans) \
	166	((struct iwl_trans_pcie *) ((_iwl_trans)->trans_specific))
	167
253a634c EG	168	/*****************************************************
	169	* RX
	170	******************************************************/
ab697a9f	171	void iwl_bg_rx_replenish(struct work_struct *data);
0c325769	172	void iwl_irq_tasklet(struct iwl_trans *trans);
5a878bf6 EG	173	void iwlagn_rx_replenish(struct iwl_trans *trans);
5a878bf6 EG	174	void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
ab697a9f EG	175	struct iwl_rx_queue *q);
ab697a9f EG	176
1a361cd8 EG	177	/*****************************************************
	178	* ICT
	179	******************************************************/
6bb78847	180	int iwl_reset_ict(struct iwl_trans *trans);
0c325769 EG	181	void iwl_disable_ict(struct iwl_trans *trans);
	182	int iwl_alloc_isr_ict(struct iwl_trans *trans);
	183	void iwl_free_isr_ict(struct iwl_trans *trans);
1a361cd8 EG	184	irqreturn_t iwl_isr_ict(int irq, void *data);
1a361cd8 EG	185
253a634c EG	186	/*****************************************************
	187	* TX / HCMD
	188	******************************************************/
fd656935 EG	189	void iwl_txq_update_write_ptr(struct iwl_trans *trans,
fd656935 EG	190	struct iwl_tx_queue *txq);
6d8f6eeb	191	int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans,
253a634c EG	192	struct iwl_tx_queue *txq,
253a634c EG	193	dma_addr_t addr, u16 len, u8 reset);
6d8f6eeb EG	194	int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id);
	195	int iwl_trans_pcie_send_cmd(struct iwl_trans trans, struct iwl_host_cmd cmd);
	196	int __must_check iwl_trans_pcie_send_cmd_pdu(struct iwl_trans *trans, u8 id,
e6bb4c9c	197	u32 flags, u16 len, const void *data);
253a634c	198	void iwl_tx_cmd_complete(struct iwl_priv priv, struct iwl_rx_mem_buffer rxb);
6d8f6eeb	199	void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
48d42c42 EG	200	struct iwl_tx_queue *txq,
48d42c42 EG	201	u16 byte_cnt);
7f01d567 EG	202	void iwl_trans_pcie_txq_agg_disable(struct iwl_trans *trans, int txq_id);
	203	int iwl_trans_pcie_tx_agg_disable(struct iwl_trans *trans,
	204	enum iwl_rxon_context_id ctx, int sta_id,
	205	int tid);
6d8f6eeb	206	void iwl_trans_set_wr_ptrs(struct iwl_trans *trans, int txq_id, u32 index);
c91bd124	207	void iwl_trans_tx_queue_set_status(struct iwl_trans *trans,
48d42c42 EG	208	struct iwl_tx_queue *txq,
48d42c42 EG	209	int tx_fifo_id, int scd_retry);
288712a6 EG	210	int iwl_trans_pcie_tx_agg_alloc(struct iwl_trans *trans,
	211	enum iwl_rxon_context_id ctx, int sta_id,
	212	int tid, u16 *ssn);
c91bd124 EG	213	void iwl_trans_pcie_tx_agg_setup(struct iwl_trans *trans,
	214	enum iwl_rxon_context_id ctx,
	215	int sta_id, int tid, int frame_limit);
6d8f6eeb	216	void iwlagn_txq_free_tfd(struct iwl_trans trans, struct iwl_tx_queue txq,
04e1cabe	217	int index);
464021ff EG	218	int iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index,
464021ff EG	219	struct sk_buff_head *skbs);
8ad71bef	220	int iwl_queue_space(const struct iwl_queue *q);
253a634c	221
7ff94706 EG	222	/*****************************************************
	223	* Error handling
	224	******************************************************/
6bb78847 EG	225	int iwl_dump_nic_event_log(struct iwl_trans *trans, bool full_log,
6bb78847 EG	226	char **buf, bool display);
16db88ba EG	227	int iwl_dump_fh(struct iwl_trans trans, char *buf, bool display);
	228	void iwl_dump_csr(struct iwl_trans *trans);
	229
8ad71bef EG	230	/*****************************************************
	231	* Helpers
	232	******************************************************/
0c325769 EG	233	static inline void iwl_disable_interrupts(struct iwl_trans *trans)
	234	{
	235	clear_bit(STATUS_INT_ENABLED, &trans->shrd->status);
	236
	237	/* disable interrupts from uCode/NIC to host */
83ed9015	238	iwl_write32(bus(trans), CSR_INT_MASK, 0x00000000);
0c325769 EG	239
	240	/* acknowledge/clear/reset any interrupts still pending
	241	* from uCode or flow handler (Rx/Tx DMA) */
83ed9015 EG	242	iwl_write32(bus(trans), CSR_INT, 0xffffffff);
83ed9015 EG	243	iwl_write32(bus(trans), CSR_FH_INT_STATUS, 0xffffffff);
0c325769 EG	244	IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
	245	}
	246
	247	static inline void iwl_enable_interrupts(struct iwl_trans *trans)
	248	{
	249	struct iwl_trans_pcie *trans_pcie =
	250	IWL_TRANS_GET_PCIE_TRANS(trans);
	251
	252	IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
	253	set_bit(STATUS_INT_ENABLED, &trans->shrd->status);
83ed9015	254	iwl_write32(bus(trans), CSR_INT_MASK, trans_pcie->inta_mask);
0c325769 EG	255	}
0c325769 EG	256
e20d4341 EG	257	/*
	258	* we have 8 bits used like this:
	259	*
	260	* 7 6 5 4 3 2 1 0
	261	* \| \| \| \| \| \| \| \|
	262	* \| \| \| \| \| \| +-+-------- AC queue (0-3)
	263	* \| \| \| \| \| \|
	264	* \| +-+-+-+-+------------ HW queue ID
	265	* \|
	266	* +---------------------- unused
	267	*/
	268	static inline void iwl_set_swq_id(struct iwl_tx_queue *txq, u8 ac, u8 hwq)
	269	{
	270	BUG_ON(ac > 3); /* only have 2 bits */
	271	BUG_ON(hwq > 31); /* only use 5 bits */
	272
	273	txq->swq_id = (hwq << 2) \| ac;
	274	}
	275
	276	static inline void iwl_wake_queue(struct iwl_trans *trans,
	277	struct iwl_tx_queue *txq)
	278	{
	279	u8 queue = txq->swq_id;
	280	u8 ac = queue & 3;
	281	u8 hwq = (queue >> 2) & 0x1f;
8ad71bef EG	282	struct iwl_trans_pcie *trans_pcie =
8ad71bef EG	283	IWL_TRANS_GET_PCIE_TRANS(trans);
e20d4341 EG	284
	285	if (unlikely(!trans->shrd->mac80211_registered))
	286	return;
	287
8ad71bef EG	288	if (test_and_clear_bit(hwq, trans_pcie->queue_stopped))
8ad71bef EG	289	if (atomic_dec_return(&trans_pcie->queue_stop_count[ac]) <= 0)
e20d4341 EG	290	ieee80211_wake_queue(trans->shrd->hw, ac);
	291	}
	292
	293	static inline void iwl_stop_queue(struct iwl_trans *trans,
	294	struct iwl_tx_queue *txq)
	295	{
	296	u8 queue = txq->swq_id;
	297	u8 ac = queue & 3;
	298	u8 hwq = (queue >> 2) & 0x1f;
8ad71bef EG	299	struct iwl_trans_pcie *trans_pcie =
8ad71bef EG	300	IWL_TRANS_GET_PCIE_TRANS(trans);
e20d4341 EG	301
	302	if (unlikely(!trans->shrd->mac80211_registered))
	303	return;
	304
8ad71bef EG	305	if (!test_and_set_bit(hwq, trans_pcie->queue_stopped))
8ad71bef EG	306	if (atomic_inc_return(&trans_pcie->queue_stop_count[ac]) > 0)
e20d4341 EG	307	ieee80211_stop_queue(trans->shrd->hw, ac);
	308	}
	309
	310	#ifdef ieee80211_stop_queue
	311	#undef ieee80211_stop_queue
	312	#endif
	313
	314	#define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue
	315
	316	#ifdef ieee80211_wake_queue
	317	#undef ieee80211_wake_queue
	318	#endif
	319
	320	#define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue
	321
8ad71bef EG	322	static inline void iwl_txq_ctx_activate(struct iwl_trans_pcie *trans_pcie,
	323	int txq_id)
	324	{
	325	set_bit(txq_id, &trans_pcie->txq_ctx_active_msk);
	326	}
	327
	328	static inline void iwl_txq_ctx_deactivate(struct iwl_trans_pcie *trans_pcie,
	329	int txq_id)
	330	{
	331	clear_bit(txq_id, &trans_pcie->txq_ctx_active_msk);
	332	}
	333
	334	static inline int iwl_queue_used(const struct iwl_queue *q, int i)
	335	{
	336	return q->write_ptr >= q->read_ptr ?
	337	(i >= q->read_ptr && i < q->write_ptr) :
	338	!(i < q->read_ptr && i >= q->write_ptr);
	339	}
	340
	341	static inline u8 get_cmd_index(struct iwl_queue *q, u32 index)
	342	{
	343	return index & (q->n_window - 1);
	344	}
	345
ab697a9f	346	#endif /* __iwl_trans_int_pcie_h__ */