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ab697a9f EG |
1 | /****************************************************************************** |
2 | * | |
fb4961db | 3 | * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved. |
ab697a9f EG |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
25 | * Intel Linux Wireless <ilw@linux.intel.com> | |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
27 | * | |
28 | *****************************************************************************/ | |
29 | #include <linux/sched.h> | |
30 | #include <linux/wait.h> | |
1a361cd8 | 31 | #include <linux/gfp.h> |
ab697a9f | 32 | |
1b29dc94 | 33 | #include "iwl-prph.h" |
ab697a9f | 34 | #include "iwl-io.h" |
c17d0681 | 35 | #include "iwl-trans-pcie-int.h" |
db70f290 | 36 | #include "iwl-op-mode.h" |
ab697a9f | 37 | |
a5916977 GG |
38 | #ifdef CONFIG_IWLWIFI_IDI |
39 | #include "iwl-amfh.h" | |
40 | #endif | |
41 | ||
ab697a9f EG |
42 | /****************************************************************************** |
43 | * | |
44 | * RX path functions | |
45 | * | |
46 | ******************************************************************************/ | |
47 | ||
48 | /* | |
49 | * Rx theory of operation | |
50 | * | |
51 | * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs), | |
52 | * each of which point to Receive Buffers to be filled by the NIC. These get | |
53 | * used not only for Rx frames, but for any command response or notification | |
54 | * from the NIC. The driver and NIC manage the Rx buffers by means | |
55 | * of indexes into the circular buffer. | |
56 | * | |
57 | * Rx Queue Indexes | |
58 | * The host/firmware share two index registers for managing the Rx buffers. | |
59 | * | |
60 | * The READ index maps to the first position that the firmware may be writing | |
61 | * to -- the driver can read up to (but not including) this position and get | |
62 | * good data. | |
63 | * The READ index is managed by the firmware once the card is enabled. | |
64 | * | |
65 | * The WRITE index maps to the last position the driver has read from -- the | |
66 | * position preceding WRITE is the last slot the firmware can place a packet. | |
67 | * | |
68 | * The queue is empty (no good data) if WRITE = READ - 1, and is full if | |
69 | * WRITE = READ. | |
70 | * | |
71 | * During initialization, the host sets up the READ queue position to the first | |
72 | * INDEX position, and WRITE to the last (READ - 1 wrapped) | |
73 | * | |
74 | * When the firmware places a packet in a buffer, it will advance the READ index | |
75 | * and fire the RX interrupt. The driver can then query the READ index and | |
76 | * process as many packets as possible, moving the WRITE index forward as it | |
77 | * resets the Rx queue buffers with new memory. | |
78 | * | |
79 | * The management in the driver is as follows: | |
80 | * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When | |
81 | * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled | |
82 | * to replenish the iwl->rxq->rx_free. | |
83 | * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the | |
84 | * iwl->rxq is replenished and the READ INDEX is updated (updating the | |
85 | * 'processed' and 'read' driver indexes as well) | |
86 | * + A received packet is processed and handed to the kernel network stack, | |
87 | * detached from the iwl->rxq. The driver 'processed' index is updated. | |
88 | * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free | |
89 | * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ | |
90 | * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there | |
91 | * were enough free buffers and RX_STALLED is set it is cleared. | |
92 | * | |
93 | * | |
94 | * Driver sequence: | |
95 | * | |
96 | * iwl_rx_queue_alloc() Allocates rx_free | |
97 | * iwl_rx_replenish() Replenishes rx_free list from rx_used, and calls | |
98 | * iwl_rx_queue_restock | |
99 | * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx | |
100 | * queue, updates firmware pointers, and updates | |
101 | * the WRITE index. If insufficient rx_free buffers | |
102 | * are available, schedules iwl_rx_replenish | |
103 | * | |
104 | * -- enable interrupts -- | |
105 | * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the | |
106 | * READ INDEX, detaching the SKB from the pool. | |
107 | * Moves the packet buffer from queue to rx_used. | |
108 | * Calls iwl_rx_queue_restock to refill any empty | |
109 | * slots. | |
110 | * ... | |
111 | * | |
112 | */ | |
113 | ||
114 | /** | |
115 | * iwl_rx_queue_space - Return number of free slots available in queue. | |
116 | */ | |
117 | static int iwl_rx_queue_space(const struct iwl_rx_queue *q) | |
118 | { | |
119 | int s = q->read - q->write; | |
120 | if (s <= 0) | |
121 | s += RX_QUEUE_SIZE; | |
122 | /* keep some buffer to not confuse full and empty queue */ | |
123 | s -= 2; | |
124 | if (s < 0) | |
125 | s = 0; | |
126 | return s; | |
127 | } | |
128 | ||
129 | /** | |
130 | * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue | |
131 | */ | |
5a878bf6 | 132 | void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans, |
20d3b647 | 133 | struct iwl_rx_queue *q) |
ab697a9f EG |
134 | { |
135 | unsigned long flags; | |
136 | u32 reg; | |
137 | ||
138 | spin_lock_irqsave(&q->lock, flags); | |
139 | ||
140 | if (q->need_update == 0) | |
141 | goto exit_unlock; | |
142 | ||
035f7ff2 | 143 | if (trans->cfg->base_params->shadow_reg_enable) { |
ab697a9f EG |
144 | /* shadow register enabled */ |
145 | /* Device expects a multiple of 8 */ | |
146 | q->write_actual = (q->write & ~0x7); | |
1042db2a | 147 | iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, q->write_actual); |
ab697a9f | 148 | } else { |
47107e84 DF |
149 | struct iwl_trans_pcie *trans_pcie = |
150 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
151 | ||
ab697a9f | 152 | /* If power-saving is in use, make sure device is awake */ |
01d651d4 | 153 | if (test_bit(STATUS_TPOWER_PMI, &trans_pcie->status)) { |
1042db2a | 154 | reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); |
ab697a9f EG |
155 | |
156 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
5a878bf6 | 157 | IWL_DEBUG_INFO(trans, |
ab697a9f EG |
158 | "Rx queue requesting wakeup," |
159 | " GP1 = 0x%x\n", reg); | |
1042db2a | 160 | iwl_set_bit(trans, CSR_GP_CNTRL, |
ab697a9f EG |
161 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
162 | goto exit_unlock; | |
163 | } | |
164 | ||
165 | q->write_actual = (q->write & ~0x7); | |
1042db2a | 166 | iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR, |
ab697a9f EG |
167 | q->write_actual); |
168 | ||
169 | /* Else device is assumed to be awake */ | |
170 | } else { | |
171 | /* Device expects a multiple of 8 */ | |
172 | q->write_actual = (q->write & ~0x7); | |
1042db2a | 173 | iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR, |
ab697a9f EG |
174 | q->write_actual); |
175 | } | |
176 | } | |
177 | q->need_update = 0; | |
178 | ||
179 | exit_unlock: | |
180 | spin_unlock_irqrestore(&q->lock, flags); | |
181 | } | |
182 | ||
183 | /** | |
184 | * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr | |
185 | */ | |
5a878bf6 | 186 | static inline __le32 iwlagn_dma_addr2rbd_ptr(dma_addr_t dma_addr) |
ab697a9f EG |
187 | { |
188 | return cpu_to_le32((u32)(dma_addr >> 8)); | |
189 | } | |
190 | ||
191 | /** | |
192 | * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool | |
193 | * | |
194 | * If there are slots in the RX queue that need to be restocked, | |
195 | * and we have free pre-allocated buffers, fill the ranks as much | |
196 | * as we can, pulling from rx_free. | |
197 | * | |
198 | * This moves the 'write' index forward to catch up with 'processed', and | |
199 | * also updates the memory address in the firmware to reference the new | |
200 | * target buffer. | |
201 | */ | |
5a878bf6 | 202 | static void iwlagn_rx_queue_restock(struct iwl_trans *trans) |
ab697a9f | 203 | { |
20d3b647 | 204 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
5a878bf6 | 205 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; |
ab697a9f EG |
206 | struct list_head *element; |
207 | struct iwl_rx_mem_buffer *rxb; | |
208 | unsigned long flags; | |
209 | ||
210 | spin_lock_irqsave(&rxq->lock, flags); | |
211 | while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) { | |
212 | /* The overwritten rxb must be a used one */ | |
213 | rxb = rxq->queue[rxq->write]; | |
214 | BUG_ON(rxb && rxb->page); | |
215 | ||
216 | /* Get next free Rx buffer, remove from free list */ | |
217 | element = rxq->rx_free.next; | |
218 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); | |
219 | list_del(element); | |
220 | ||
221 | /* Point to Rx buffer via next RBD in circular buffer */ | |
5a878bf6 | 222 | rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(rxb->page_dma); |
ab697a9f EG |
223 | rxq->queue[rxq->write] = rxb; |
224 | rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; | |
225 | rxq->free_count--; | |
226 | } | |
227 | spin_unlock_irqrestore(&rxq->lock, flags); | |
228 | /* If the pre-allocated buffer pool is dropping low, schedule to | |
229 | * refill it */ | |
230 | if (rxq->free_count <= RX_LOW_WATERMARK) | |
1ee158d8 | 231 | schedule_work(&trans_pcie->rx_replenish); |
ab697a9f EG |
232 | |
233 | ||
234 | /* If we've added more space for the firmware to place data, tell it. | |
235 | * Increment device's write pointer in multiples of 8. */ | |
236 | if (rxq->write_actual != (rxq->write & ~0x7)) { | |
237 | spin_lock_irqsave(&rxq->lock, flags); | |
238 | rxq->need_update = 1; | |
239 | spin_unlock_irqrestore(&rxq->lock, flags); | |
5a878bf6 | 240 | iwl_rx_queue_update_write_ptr(trans, rxq); |
ab697a9f EG |
241 | } |
242 | } | |
243 | ||
244 | /** | |
245 | * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free | |
246 | * | |
247 | * When moving to rx_free an SKB is allocated for the slot. | |
248 | * | |
249 | * Also restock the Rx queue via iwl_rx_queue_restock. | |
250 | * This is called as a scheduled work item (except for during initialization) | |
251 | */ | |
5a878bf6 | 252 | static void iwlagn_rx_allocate(struct iwl_trans *trans, gfp_t priority) |
ab697a9f | 253 | { |
20d3b647 | 254 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
5a878bf6 | 255 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; |
ab697a9f EG |
256 | struct list_head *element; |
257 | struct iwl_rx_mem_buffer *rxb; | |
258 | struct page *page; | |
259 | unsigned long flags; | |
260 | gfp_t gfp_mask = priority; | |
261 | ||
262 | while (1) { | |
263 | spin_lock_irqsave(&rxq->lock, flags); | |
264 | if (list_empty(&rxq->rx_used)) { | |
265 | spin_unlock_irqrestore(&rxq->lock, flags); | |
266 | return; | |
267 | } | |
268 | spin_unlock_irqrestore(&rxq->lock, flags); | |
269 | ||
270 | if (rxq->free_count > RX_LOW_WATERMARK) | |
271 | gfp_mask |= __GFP_NOWARN; | |
272 | ||
b2cf410c | 273 | if (trans_pcie->rx_page_order > 0) |
ab697a9f EG |
274 | gfp_mask |= __GFP_COMP; |
275 | ||
276 | /* Alloc a new receive buffer */ | |
20d3b647 | 277 | page = alloc_pages(gfp_mask, trans_pcie->rx_page_order); |
ab697a9f EG |
278 | if (!page) { |
279 | if (net_ratelimit()) | |
5a878bf6 | 280 | IWL_DEBUG_INFO(trans, "alloc_pages failed, " |
d6189124 | 281 | "order: %d\n", |
b2cf410c | 282 | trans_pcie->rx_page_order); |
ab697a9f EG |
283 | |
284 | if ((rxq->free_count <= RX_LOW_WATERMARK) && | |
285 | net_ratelimit()) | |
5a878bf6 | 286 | IWL_CRIT(trans, "Failed to alloc_pages with %s." |
ab697a9f EG |
287 | "Only %u free buffers remaining.\n", |
288 | priority == GFP_ATOMIC ? | |
289 | "GFP_ATOMIC" : "GFP_KERNEL", | |
290 | rxq->free_count); | |
291 | /* We don't reschedule replenish work here -- we will | |
292 | * call the restock method and if it still needs | |
293 | * more buffers it will schedule replenish */ | |
294 | return; | |
295 | } | |
296 | ||
297 | spin_lock_irqsave(&rxq->lock, flags); | |
298 | ||
299 | if (list_empty(&rxq->rx_used)) { | |
300 | spin_unlock_irqrestore(&rxq->lock, flags); | |
b2cf410c | 301 | __free_pages(page, trans_pcie->rx_page_order); |
ab697a9f EG |
302 | return; |
303 | } | |
304 | element = rxq->rx_used.next; | |
305 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); | |
306 | list_del(element); | |
307 | ||
308 | spin_unlock_irqrestore(&rxq->lock, flags); | |
309 | ||
310 | BUG_ON(rxb->page); | |
311 | rxb->page = page; | |
312 | /* Get physical address of the RB */ | |
20d3b647 JB |
313 | rxb->page_dma = |
314 | dma_map_page(trans->dev, page, 0, | |
315 | PAGE_SIZE << trans_pcie->rx_page_order, | |
316 | DMA_FROM_DEVICE); | |
ab697a9f EG |
317 | /* dma address must be no more than 36 bits */ |
318 | BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36)); | |
319 | /* and also 256 byte aligned! */ | |
320 | BUG_ON(rxb->page_dma & DMA_BIT_MASK(8)); | |
321 | ||
322 | spin_lock_irqsave(&rxq->lock, flags); | |
323 | ||
324 | list_add_tail(&rxb->list, &rxq->rx_free); | |
325 | rxq->free_count++; | |
326 | ||
327 | spin_unlock_irqrestore(&rxq->lock, flags); | |
328 | } | |
329 | } | |
330 | ||
5a878bf6 | 331 | void iwlagn_rx_replenish(struct iwl_trans *trans) |
ab697a9f | 332 | { |
7b11488f | 333 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
ab697a9f EG |
334 | unsigned long flags; |
335 | ||
5a878bf6 | 336 | iwlagn_rx_allocate(trans, GFP_KERNEL); |
ab697a9f | 337 | |
7b11488f | 338 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
5a878bf6 | 339 | iwlagn_rx_queue_restock(trans); |
7b11488f | 340 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
ab697a9f EG |
341 | } |
342 | ||
5a878bf6 | 343 | static void iwlagn_rx_replenish_now(struct iwl_trans *trans) |
ab697a9f | 344 | { |
5a878bf6 | 345 | iwlagn_rx_allocate(trans, GFP_ATOMIC); |
ab697a9f | 346 | |
5a878bf6 | 347 | iwlagn_rx_queue_restock(trans); |
ab697a9f EG |
348 | } |
349 | ||
350 | void iwl_bg_rx_replenish(struct work_struct *data) | |
351 | { | |
5a878bf6 EG |
352 | struct iwl_trans_pcie *trans_pcie = |
353 | container_of(data, struct iwl_trans_pcie, rx_replenish); | |
ab697a9f | 354 | |
1ee158d8 | 355 | iwlagn_rx_replenish(trans_pcie->trans); |
ab697a9f EG |
356 | } |
357 | ||
df2f3216 JB |
358 | static void iwl_rx_handle_rxbuf(struct iwl_trans *trans, |
359 | struct iwl_rx_mem_buffer *rxb) | |
360 | { | |
361 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
362 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
c6f600fc | 363 | struct iwl_tx_queue *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
df2f3216 | 364 | unsigned long flags; |
0c19744c | 365 | bool page_stolen = false; |
b2cf410c | 366 | int max_len = PAGE_SIZE << trans_pcie->rx_page_order; |
0c19744c | 367 | u32 offset = 0; |
df2f3216 JB |
368 | |
369 | if (WARN_ON(!rxb)) | |
370 | return; | |
371 | ||
0c19744c JB |
372 | dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE); |
373 | ||
374 | while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) { | |
375 | struct iwl_rx_packet *pkt; | |
376 | struct iwl_device_cmd *cmd; | |
377 | u16 sequence; | |
378 | bool reclaim; | |
379 | int index, cmd_index, err, len; | |
380 | struct iwl_rx_cmd_buffer rxcb = { | |
381 | ._offset = offset, | |
382 | ._page = rxb->page, | |
383 | ._page_stolen = false, | |
0d6c4a2e | 384 | .truesize = max_len, |
0c19744c JB |
385 | }; |
386 | ||
387 | pkt = rxb_addr(&rxcb); | |
388 | ||
389 | if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID)) | |
390 | break; | |
391 | ||
392 | IWL_DEBUG_RX(trans, "cmd at offset %d: %s (0x%.2x)\n", | |
d9fb6465 JB |
393 | rxcb._offset, |
394 | trans_pcie_get_cmd_string(trans_pcie, pkt->hdr.cmd), | |
395 | pkt->hdr.cmd); | |
0c19744c JB |
396 | |
397 | len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; | |
398 | len += sizeof(u32); /* account for status word */ | |
399 | trace_iwlwifi_dev_rx(trans->dev, pkt, len); | |
400 | ||
401 | /* Reclaim a command buffer only if this packet is a response | |
402 | * to a (driver-originated) command. | |
403 | * If the packet (e.g. Rx frame) originated from uCode, | |
404 | * there is no command buffer to reclaim. | |
405 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
406 | * but apparently a few don't get set; catch them here. */ | |
407 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME); | |
408 | if (reclaim) { | |
409 | int i; | |
410 | ||
411 | for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) { | |
412 | if (trans_pcie->no_reclaim_cmds[i] == | |
413 | pkt->hdr.cmd) { | |
414 | reclaim = false; | |
415 | break; | |
416 | } | |
d663ee73 JB |
417 | } |
418 | } | |
df2f3216 | 419 | |
0c19744c JB |
420 | sequence = le16_to_cpu(pkt->hdr.sequence); |
421 | index = SEQ_TO_INDEX(sequence); | |
422 | cmd_index = get_cmd_index(&txq->q, index); | |
423 | ||
424 | if (reclaim) | |
bf8440e6 | 425 | cmd = txq->entries[cmd_index].cmd; |
df2f3216 | 426 | else |
0c19744c JB |
427 | cmd = NULL; |
428 | ||
429 | err = iwl_op_mode_rx(trans->op_mode, &rxcb, cmd); | |
430 | ||
431 | /* | |
432 | * After here, we should always check rxcb._page_stolen, | |
433 | * if it is true then one of the handlers took the page. | |
434 | */ | |
435 | ||
436 | if (reclaim) { | |
437 | /* Invoke any callbacks, transfer the buffer to caller, | |
438 | * and fire off the (possibly) blocking | |
439 | * iwl_trans_send_cmd() | |
440 | * as we reclaim the driver command queue */ | |
441 | if (!rxcb._page_stolen) | |
442 | iwl_tx_cmd_complete(trans, &rxcb, err); | |
443 | else | |
444 | IWL_WARN(trans, "Claim null rxb?\n"); | |
445 | } | |
446 | ||
447 | page_stolen |= rxcb._page_stolen; | |
448 | offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN); | |
df2f3216 JB |
449 | } |
450 | ||
0c19744c JB |
451 | /* page was stolen from us -- free our reference */ |
452 | if (page_stolen) { | |
b2cf410c | 453 | __free_pages(rxb->page, trans_pcie->rx_page_order); |
df2f3216 | 454 | rxb->page = NULL; |
0c19744c | 455 | } |
df2f3216 JB |
456 | |
457 | /* Reuse the page if possible. For notification packets and | |
458 | * SKBs that fail to Rx correctly, add them back into the | |
459 | * rx_free list for reuse later. */ | |
460 | spin_lock_irqsave(&rxq->lock, flags); | |
461 | if (rxb->page != NULL) { | |
462 | rxb->page_dma = | |
463 | dma_map_page(trans->dev, rxb->page, 0, | |
20d3b647 JB |
464 | PAGE_SIZE << trans_pcie->rx_page_order, |
465 | DMA_FROM_DEVICE); | |
df2f3216 JB |
466 | list_add_tail(&rxb->list, &rxq->rx_free); |
467 | rxq->free_count++; | |
468 | } else | |
469 | list_add_tail(&rxb->list, &rxq->rx_used); | |
470 | spin_unlock_irqrestore(&rxq->lock, flags); | |
471 | } | |
472 | ||
ab697a9f EG |
473 | /** |
474 | * iwl_rx_handle - Main entry function for receiving responses from uCode | |
475 | * | |
476 | * Uses the priv->rx_handlers callback function array to invoke | |
477 | * the appropriate handlers, including command responses, | |
478 | * frame-received notifications, and other notifications. | |
479 | */ | |
5a878bf6 | 480 | static void iwl_rx_handle(struct iwl_trans *trans) |
ab697a9f | 481 | { |
df2f3216 | 482 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
5a878bf6 | 483 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; |
ab697a9f | 484 | u32 r, i; |
ab697a9f EG |
485 | u8 fill_rx = 0; |
486 | u32 count = 8; | |
487 | int total_empty; | |
488 | ||
489 | /* uCode's read index (stored in shared DRAM) indicates the last Rx | |
490 | * buffer that the driver may process (last buffer filled by ucode). */ | |
491 | r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; | |
492 | i = rxq->read; | |
493 | ||
494 | /* Rx interrupt, but nothing sent from uCode */ | |
495 | if (i == r) | |
726f23fd | 496 | IWL_DEBUG_RX(trans, "HW = SW = %d\n", r); |
ab697a9f EG |
497 | |
498 | /* calculate total frames need to be restock after handling RX */ | |
499 | total_empty = r - rxq->write_actual; | |
500 | if (total_empty < 0) | |
501 | total_empty += RX_QUEUE_SIZE; | |
502 | ||
503 | if (total_empty > (RX_QUEUE_SIZE / 2)) | |
504 | fill_rx = 1; | |
505 | ||
506 | while (i != r) { | |
48a2d66f | 507 | struct iwl_rx_mem_buffer *rxb; |
ab697a9f EG |
508 | |
509 | rxb = rxq->queue[i]; | |
ab697a9f EG |
510 | rxq->queue[i] = NULL; |
511 | ||
726f23fd EG |
512 | IWL_DEBUG_RX(trans, "rxbuf: HW = %d, SW = %d (%p)\n", |
513 | r, i, rxb); | |
df2f3216 | 514 | iwl_rx_handle_rxbuf(trans, rxb); |
ab697a9f EG |
515 | |
516 | i = (i + 1) & RX_QUEUE_MASK; | |
517 | /* If there are a lot of unused frames, | |
518 | * restock the Rx queue so ucode wont assert. */ | |
519 | if (fill_rx) { | |
520 | count++; | |
521 | if (count >= 8) { | |
522 | rxq->read = i; | |
5a878bf6 | 523 | iwlagn_rx_replenish_now(trans); |
ab697a9f EG |
524 | count = 0; |
525 | } | |
526 | } | |
527 | } | |
528 | ||
529 | /* Backtrack one entry */ | |
530 | rxq->read = i; | |
531 | if (fill_rx) | |
5a878bf6 | 532 | iwlagn_rx_replenish_now(trans); |
ab697a9f | 533 | else |
5a878bf6 | 534 | iwlagn_rx_queue_restock(trans); |
ab697a9f EG |
535 | } |
536 | ||
7ff94706 EG |
537 | /** |
538 | * iwl_irq_handle_error - called for HW or SW error interrupt from card | |
539 | */ | |
6bb78847 | 540 | static void iwl_irq_handle_error(struct iwl_trans *trans) |
7ff94706 EG |
541 | { |
542 | /* W/A for WiFi/WiMAX coex and WiMAX own the RF */ | |
035f7ff2 | 543 | if (trans->cfg->internal_wimax_coex && |
1042db2a | 544 | (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) & |
20d3b647 | 545 | APMS_CLK_VAL_MRB_FUNC_MODE) || |
1042db2a | 546 | (iwl_read_prph(trans, APMG_PS_CTRL_REG) & |
20d3b647 JB |
547 | APMG_PS_CTRL_VAL_RESET_REQ))) { |
548 | struct iwl_trans_pcie *trans_pcie = | |
549 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
74fda971 | 550 | |
74fda971 | 551 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); |
8a8bbdb4 | 552 | iwl_op_mode_wimax_active(trans->op_mode); |
69a10b29 | 553 | wake_up(&trans->wait_command_queue); |
7ff94706 EG |
554 | return; |
555 | } | |
556 | ||
6bb78847 EG |
557 | iwl_dump_csr(trans); |
558 | iwl_dump_fh(trans, NULL, false); | |
7ff94706 | 559 | |
bcb9321c | 560 | iwl_op_mode_nic_error(trans->op_mode); |
7ff94706 EG |
561 | } |
562 | ||
ab697a9f | 563 | /* tasklet for iwlagn interrupt */ |
0c325769 | 564 | void iwl_irq_tasklet(struct iwl_trans *trans) |
ab697a9f | 565 | { |
20d3b647 JB |
566 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
567 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; | |
ab697a9f EG |
568 | u32 inta = 0; |
569 | u32 handled = 0; | |
570 | unsigned long flags; | |
571 | u32 i; | |
572 | #ifdef CONFIG_IWLWIFI_DEBUG | |
573 | u32 inta_mask; | |
574 | #endif | |
575 | ||
7b11488f | 576 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
ab697a9f EG |
577 | |
578 | /* Ack/clear/reset pending uCode interrupts. | |
579 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
580 | */ | |
581 | /* There is a hardware bug in the interrupt mask function that some | |
582 | * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if | |
583 | * they are disabled in the CSR_INT_MASK register. Furthermore the | |
584 | * ICT interrupt handling mechanism has another bug that might cause | |
585 | * these unmasked interrupts fail to be detected. We workaround the | |
586 | * hardware bugs here by ACKing all the possible interrupts so that | |
587 | * interrupt coalescing can still be achieved. | |
588 | */ | |
1042db2a | 589 | iwl_write32(trans, CSR_INT, |
20d3b647 | 590 | trans_pcie->inta | ~trans_pcie->inta_mask); |
ab697a9f | 591 | |
0c325769 | 592 | inta = trans_pcie->inta; |
ab697a9f EG |
593 | |
594 | #ifdef CONFIG_IWLWIFI_DEBUG | |
a8bceb39 | 595 | if (iwl_have_debug_level(IWL_DL_ISR)) { |
ab697a9f | 596 | /* just for debug */ |
1042db2a | 597 | inta_mask = iwl_read32(trans, CSR_INT_MASK); |
0ca24daf | 598 | IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n", |
20d3b647 | 599 | inta, inta_mask); |
ab697a9f EG |
600 | } |
601 | #endif | |
602 | ||
0c325769 EG |
603 | /* saved interrupt in inta variable now we can reset trans_pcie->inta */ |
604 | trans_pcie->inta = 0; | |
ab697a9f | 605 | |
7b11488f | 606 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
b49ba04a | 607 | |
ab697a9f EG |
608 | /* Now service all interrupt bits discovered above. */ |
609 | if (inta & CSR_INT_BIT_HW_ERR) { | |
0c325769 | 610 | IWL_ERR(trans, "Hardware error detected. Restarting.\n"); |
ab697a9f EG |
611 | |
612 | /* Tell the device to stop sending interrupts */ | |
0c325769 | 613 | iwl_disable_interrupts(trans); |
ab697a9f | 614 | |
1f7b6172 | 615 | isr_stats->hw++; |
6bb78847 | 616 | iwl_irq_handle_error(trans); |
ab697a9f EG |
617 | |
618 | handled |= CSR_INT_BIT_HW_ERR; | |
619 | ||
620 | return; | |
621 | } | |
622 | ||
623 | #ifdef CONFIG_IWLWIFI_DEBUG | |
a8bceb39 | 624 | if (iwl_have_debug_level(IWL_DL_ISR)) { |
ab697a9f EG |
625 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
626 | if (inta & CSR_INT_BIT_SCD) { | |
0c325769 | 627 | IWL_DEBUG_ISR(trans, "Scheduler finished to transmit " |
ab697a9f | 628 | "the frame/frames.\n"); |
1f7b6172 | 629 | isr_stats->sch++; |
ab697a9f EG |
630 | } |
631 | ||
632 | /* Alive notification via Rx interrupt will do the real work */ | |
633 | if (inta & CSR_INT_BIT_ALIVE) { | |
0c325769 | 634 | IWL_DEBUG_ISR(trans, "Alive interrupt\n"); |
1f7b6172 | 635 | isr_stats->alive++; |
ab697a9f EG |
636 | } |
637 | } | |
638 | #endif | |
639 | /* Safely ignore these bits for debug checks below */ | |
640 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); | |
641 | ||
642 | /* HW RF KILL switch toggled */ | |
643 | if (inta & CSR_INT_BIT_RF_KILL) { | |
c9eec95c | 644 | bool hw_rfkill; |
ab697a9f | 645 | |
8d425517 | 646 | hw_rfkill = iwl_is_rfkill_set(trans); |
0c325769 | 647 | IWL_WARN(trans, "RF_KILL bit toggled to %s.\n", |
20d3b647 | 648 | hw_rfkill ? "disable radio" : "enable radio"); |
ab697a9f | 649 | |
1f7b6172 | 650 | isr_stats->rfkill++; |
ab697a9f | 651 | |
c9eec95c | 652 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); |
ab697a9f EG |
653 | |
654 | handled |= CSR_INT_BIT_RF_KILL; | |
655 | } | |
656 | ||
657 | /* Chip got too hot and stopped itself */ | |
658 | if (inta & CSR_INT_BIT_CT_KILL) { | |
0c325769 | 659 | IWL_ERR(trans, "Microcode CT kill error detected.\n"); |
1f7b6172 | 660 | isr_stats->ctkill++; |
ab697a9f EG |
661 | handled |= CSR_INT_BIT_CT_KILL; |
662 | } | |
663 | ||
664 | /* Error detected by uCode */ | |
665 | if (inta & CSR_INT_BIT_SW_ERR) { | |
0c325769 | 666 | IWL_ERR(trans, "Microcode SW error detected. " |
ab697a9f | 667 | " Restarting 0x%X.\n", inta); |
1f7b6172 | 668 | isr_stats->sw++; |
6bb78847 | 669 | iwl_irq_handle_error(trans); |
ab697a9f EG |
670 | handled |= CSR_INT_BIT_SW_ERR; |
671 | } | |
672 | ||
673 | /* uCode wakes up after power-down sleep */ | |
674 | if (inta & CSR_INT_BIT_WAKEUP) { | |
0c325769 EG |
675 | IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); |
676 | iwl_rx_queue_update_write_ptr(trans, &trans_pcie->rxq); | |
035f7ff2 | 677 | for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) |
fd656935 | 678 | iwl_txq_update_write_ptr(trans, |
8ad71bef | 679 | &trans_pcie->txq[i]); |
ab697a9f | 680 | |
1f7b6172 | 681 | isr_stats->wakeup++; |
ab697a9f EG |
682 | |
683 | handled |= CSR_INT_BIT_WAKEUP; | |
684 | } | |
685 | ||
686 | /* All uCode command responses, including Tx command responses, | |
687 | * Rx "responses" (frame-received notification), and other | |
688 | * notifications from uCode come through here*/ | |
689 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | | |
20d3b647 | 690 | CSR_INT_BIT_RX_PERIODIC)) { |
0c325769 | 691 | IWL_DEBUG_ISR(trans, "Rx interrupt\n"); |
ab697a9f EG |
692 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { |
693 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); | |
1042db2a | 694 | iwl_write32(trans, CSR_FH_INT_STATUS, |
ab697a9f EG |
695 | CSR_FH_INT_RX_MASK); |
696 | } | |
697 | if (inta & CSR_INT_BIT_RX_PERIODIC) { | |
698 | handled |= CSR_INT_BIT_RX_PERIODIC; | |
1042db2a | 699 | iwl_write32(trans, |
0c325769 | 700 | CSR_INT, CSR_INT_BIT_RX_PERIODIC); |
ab697a9f EG |
701 | } |
702 | /* Sending RX interrupt require many steps to be done in the | |
703 | * the device: | |
704 | * 1- write interrupt to current index in ICT table. | |
705 | * 2- dma RX frame. | |
706 | * 3- update RX shared data to indicate last write index. | |
707 | * 4- send interrupt. | |
708 | * This could lead to RX race, driver could receive RX interrupt | |
709 | * but the shared data changes does not reflect this; | |
710 | * periodic interrupt will detect any dangling Rx activity. | |
711 | */ | |
712 | ||
713 | /* Disable periodic interrupt; we use it as just a one-shot. */ | |
1042db2a | 714 | iwl_write8(trans, CSR_INT_PERIODIC_REG, |
ab697a9f | 715 | CSR_INT_PERIODIC_DIS); |
a5916977 GG |
716 | #ifdef CONFIG_IWLWIFI_IDI |
717 | iwl_amfh_rx_handler(); | |
718 | #else | |
0c325769 | 719 | iwl_rx_handle(trans); |
a5916977 | 720 | #endif |
ab697a9f EG |
721 | /* |
722 | * Enable periodic interrupt in 8 msec only if we received | |
723 | * real RX interrupt (instead of just periodic int), to catch | |
724 | * any dangling Rx interrupt. If it was just the periodic | |
725 | * interrupt, there was no dangling Rx activity, and no need | |
726 | * to extend the periodic interrupt; one-shot is enough. | |
727 | */ | |
728 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) | |
1042db2a | 729 | iwl_write8(trans, CSR_INT_PERIODIC_REG, |
20d3b647 | 730 | CSR_INT_PERIODIC_ENA); |
ab697a9f | 731 | |
1f7b6172 | 732 | isr_stats->rx++; |
ab697a9f EG |
733 | } |
734 | ||
735 | /* This "Tx" DMA channel is used only for loading uCode */ | |
736 | if (inta & CSR_INT_BIT_FH_TX) { | |
1042db2a | 737 | iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK); |
0c325769 | 738 | IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); |
1f7b6172 | 739 | isr_stats->tx++; |
ab697a9f EG |
740 | handled |= CSR_INT_BIT_FH_TX; |
741 | /* Wake up uCode load routine, now that load is complete */ | |
13df1aab JB |
742 | trans_pcie->ucode_write_complete = true; |
743 | wake_up(&trans_pcie->ucode_write_waitq); | |
ab697a9f EG |
744 | } |
745 | ||
746 | if (inta & ~handled) { | |
0c325769 | 747 | IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled); |
1f7b6172 | 748 | isr_stats->unhandled++; |
ab697a9f EG |
749 | } |
750 | ||
0c325769 EG |
751 | if (inta & ~(trans_pcie->inta_mask)) { |
752 | IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n", | |
753 | inta & ~trans_pcie->inta_mask); | |
ab697a9f EG |
754 | } |
755 | ||
756 | /* Re-enable all interrupts */ | |
757 | /* only Re-enable if disabled by irq */ | |
83626404 | 758 | if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status)) |
0c325769 | 759 | iwl_enable_interrupts(trans); |
ab697a9f | 760 | /* Re-enable RF_KILL if it occurred */ |
8722c899 SG |
761 | else if (handled & CSR_INT_BIT_RF_KILL) |
762 | iwl_enable_rfkill_int(trans); | |
ab697a9f EG |
763 | } |
764 | ||
1a361cd8 EG |
765 | /****************************************************************************** |
766 | * | |
767 | * ICT functions | |
768 | * | |
769 | ******************************************************************************/ | |
10667136 JB |
770 | |
771 | /* a device (PCI-E) page is 4096 bytes long */ | |
772 | #define ICT_SHIFT 12 | |
773 | #define ICT_SIZE (1 << ICT_SHIFT) | |
774 | #define ICT_COUNT (ICT_SIZE / sizeof(u32)) | |
1a361cd8 EG |
775 | |
776 | /* Free dram table */ | |
0c325769 | 777 | void iwl_free_isr_ict(struct iwl_trans *trans) |
1a361cd8 | 778 | { |
20d3b647 | 779 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
0c325769 | 780 | |
10667136 | 781 | if (trans_pcie->ict_tbl) { |
1042db2a | 782 | dma_free_coherent(trans->dev, ICT_SIZE, |
10667136 | 783 | trans_pcie->ict_tbl, |
0c325769 | 784 | trans_pcie->ict_tbl_dma); |
10667136 JB |
785 | trans_pcie->ict_tbl = NULL; |
786 | trans_pcie->ict_tbl_dma = 0; | |
1a361cd8 EG |
787 | } |
788 | } | |
789 | ||
790 | ||
10667136 JB |
791 | /* |
792 | * allocate dram shared table, it is an aligned memory | |
793 | * block of ICT_SIZE. | |
1a361cd8 EG |
794 | * also reset all data related to ICT table interrupt. |
795 | */ | |
0c325769 | 796 | int iwl_alloc_isr_ict(struct iwl_trans *trans) |
1a361cd8 | 797 | { |
20d3b647 | 798 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1a361cd8 | 799 | |
10667136 | 800 | trans_pcie->ict_tbl = |
1042db2a | 801 | dma_alloc_coherent(trans->dev, ICT_SIZE, |
10667136 JB |
802 | &trans_pcie->ict_tbl_dma, |
803 | GFP_KERNEL); | |
804 | if (!trans_pcie->ict_tbl) | |
1a361cd8 EG |
805 | return -ENOMEM; |
806 | ||
10667136 JB |
807 | /* just an API sanity check ... it is guaranteed to be aligned */ |
808 | if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) { | |
809 | iwl_free_isr_ict(trans); | |
810 | return -EINVAL; | |
811 | } | |
1a361cd8 | 812 | |
10667136 JB |
813 | IWL_DEBUG_ISR(trans, "ict dma addr %Lx\n", |
814 | (unsigned long long)trans_pcie->ict_tbl_dma); | |
1a361cd8 | 815 | |
10667136 | 816 | IWL_DEBUG_ISR(trans, "ict vir addr %p\n", trans_pcie->ict_tbl); |
1a361cd8 EG |
817 | |
818 | /* reset table and index to all 0 */ | |
10667136 | 819 | memset(trans_pcie->ict_tbl, 0, ICT_SIZE); |
0c325769 | 820 | trans_pcie->ict_index = 0; |
1a361cd8 EG |
821 | |
822 | /* add periodic RX interrupt */ | |
0c325769 | 823 | trans_pcie->inta_mask |= CSR_INT_BIT_RX_PERIODIC; |
1a361cd8 EG |
824 | return 0; |
825 | } | |
826 | ||
827 | /* Device is going up inform it about using ICT interrupt table, | |
828 | * also we need to tell the driver to start using ICT interrupt. | |
829 | */ | |
ed6a3803 | 830 | void iwl_reset_ict(struct iwl_trans *trans) |
1a361cd8 | 831 | { |
20d3b647 | 832 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1a361cd8 EG |
833 | u32 val; |
834 | unsigned long flags; | |
835 | ||
10667136 | 836 | if (!trans_pcie->ict_tbl) |
ed6a3803 | 837 | return; |
1a361cd8 | 838 | |
7b11488f | 839 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
0c325769 | 840 | iwl_disable_interrupts(trans); |
1a361cd8 | 841 | |
10667136 | 842 | memset(trans_pcie->ict_tbl, 0, ICT_SIZE); |
1a361cd8 | 843 | |
10667136 | 844 | val = trans_pcie->ict_tbl_dma >> ICT_SHIFT; |
1a361cd8 EG |
845 | |
846 | val |= CSR_DRAM_INT_TBL_ENABLE; | |
847 | val |= CSR_DRAM_INIT_TBL_WRAP_CHECK; | |
848 | ||
10667136 | 849 | IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val); |
1a361cd8 | 850 | |
1042db2a | 851 | iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val); |
0c325769 EG |
852 | trans_pcie->use_ict = true; |
853 | trans_pcie->ict_index = 0; | |
1042db2a | 854 | iwl_write32(trans, CSR_INT, trans_pcie->inta_mask); |
0c325769 | 855 | iwl_enable_interrupts(trans); |
7b11488f | 856 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
1a361cd8 EG |
857 | } |
858 | ||
859 | /* Device is going down disable ict interrupt usage */ | |
0c325769 | 860 | void iwl_disable_ict(struct iwl_trans *trans) |
1a361cd8 | 861 | { |
20d3b647 | 862 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1a361cd8 EG |
863 | unsigned long flags; |
864 | ||
7b11488f | 865 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
0c325769 | 866 | trans_pcie->use_ict = false; |
7b11488f | 867 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
1a361cd8 EG |
868 | } |
869 | ||
870 | static irqreturn_t iwl_isr(int irq, void *data) | |
871 | { | |
0c325769 EG |
872 | struct iwl_trans *trans = data; |
873 | struct iwl_trans_pcie *trans_pcie; | |
1a361cd8 EG |
874 | u32 inta, inta_mask; |
875 | unsigned long flags; | |
876 | #ifdef CONFIG_IWLWIFI_DEBUG | |
877 | u32 inta_fh; | |
878 | #endif | |
0c325769 | 879 | if (!trans) |
1a361cd8 EG |
880 | return IRQ_NONE; |
881 | ||
6c1011e1 | 882 | trace_iwlwifi_dev_irq(trans->dev); |
b80667ee | 883 | |
0c325769 EG |
884 | trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
885 | ||
7b11488f | 886 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
1a361cd8 EG |
887 | |
888 | /* Disable (but don't clear!) interrupts here to avoid | |
889 | * back-to-back ISRs and sporadic interrupts from our NIC. | |
890 | * If we have something to service, the tasklet will re-enable ints. | |
891 | * If we *don't* have something, we'll re-enable before leaving here. */ | |
1042db2a EG |
892 | inta_mask = iwl_read32(trans, CSR_INT_MASK); /* just for debug */ |
893 | iwl_write32(trans, CSR_INT_MASK, 0x00000000); | |
1a361cd8 EG |
894 | |
895 | /* Discover which interrupts are active/pending */ | |
1042db2a | 896 | inta = iwl_read32(trans, CSR_INT); |
1a361cd8 EG |
897 | |
898 | /* Ignore interrupt if there's nothing in NIC to service. | |
899 | * This may be due to IRQ shared with another device, | |
900 | * or due to sporadic interrupts thrown from our NIC. */ | |
901 | if (!inta) { | |
0c325769 | 902 | IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); |
1a361cd8 EG |
903 | goto none; |
904 | } | |
905 | ||
906 | if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { | |
907 | /* Hardware disappeared. It might have already raised | |
908 | * an interrupt */ | |
0c325769 | 909 | IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta); |
1a361cd8 EG |
910 | goto unplugged; |
911 | } | |
912 | ||
913 | #ifdef CONFIG_IWLWIFI_DEBUG | |
a8bceb39 | 914 | if (iwl_have_debug_level(IWL_DL_ISR)) { |
1042db2a | 915 | inta_fh = iwl_read32(trans, CSR_FH_INT_STATUS); |
0c325769 | 916 | IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x, " |
1a361cd8 EG |
917 | "fh 0x%08x\n", inta, inta_mask, inta_fh); |
918 | } | |
919 | #endif | |
920 | ||
0c325769 | 921 | trans_pcie->inta |= inta; |
1a361cd8 EG |
922 | /* iwl_irq_tasklet() will service interrupts and re-enable them */ |
923 | if (likely(inta)) | |
0c325769 | 924 | tasklet_schedule(&trans_pcie->irq_tasklet); |
83626404 | 925 | else if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) && |
20d3b647 | 926 | !trans_pcie->inta) |
0c325769 | 927 | iwl_enable_interrupts(trans); |
1a361cd8 EG |
928 | |
929 | unplugged: | |
7b11488f | 930 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
1a361cd8 EG |
931 | return IRQ_HANDLED; |
932 | ||
933 | none: | |
934 | /* re-enable interrupts here since we don't have anything to service. */ | |
935 | /* only Re-enable if disabled by irq and no schedules tasklet. */ | |
83626404 | 936 | if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) && |
20d3b647 | 937 | !trans_pcie->inta) |
0c325769 | 938 | iwl_enable_interrupts(trans); |
1a361cd8 | 939 | |
7b11488f | 940 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
1a361cd8 EG |
941 | return IRQ_NONE; |
942 | } | |
943 | ||
944 | /* interrupt handler using ict table, with this interrupt driver will | |
945 | * stop using INTA register to get device's interrupt, reading this register | |
946 | * is expensive, device will write interrupts in ICT dram table, increment | |
947 | * index then will fire interrupt to driver, driver will OR all ICT table | |
948 | * entries from current index up to table entry with 0 value. the result is | |
949 | * the interrupt we need to service, driver will set the entries back to 0 and | |
950 | * set index. | |
951 | */ | |
952 | irqreturn_t iwl_isr_ict(int irq, void *data) | |
953 | { | |
0c325769 EG |
954 | struct iwl_trans *trans = data; |
955 | struct iwl_trans_pcie *trans_pcie; | |
1a361cd8 EG |
956 | u32 inta, inta_mask; |
957 | u32 val = 0; | |
b80667ee | 958 | u32 read; |
1a361cd8 EG |
959 | unsigned long flags; |
960 | ||
0c325769 | 961 | if (!trans) |
1a361cd8 EG |
962 | return IRQ_NONE; |
963 | ||
0c325769 EG |
964 | trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
965 | ||
1a361cd8 EG |
966 | /* dram interrupt table not set yet, |
967 | * use legacy interrupt. | |
968 | */ | |
0c325769 | 969 | if (!trans_pcie->use_ict) |
1a361cd8 EG |
970 | return iwl_isr(irq, data); |
971 | ||
6c1011e1 | 972 | trace_iwlwifi_dev_irq(trans->dev); |
b80667ee | 973 | |
7b11488f | 974 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
1a361cd8 EG |
975 | |
976 | /* Disable (but don't clear!) interrupts here to avoid | |
977 | * back-to-back ISRs and sporadic interrupts from our NIC. | |
978 | * If we have something to service, the tasklet will re-enable ints. | |
979 | * If we *don't* have something, we'll re-enable before leaving here. | |
980 | */ | |
1042db2a EG |
981 | inta_mask = iwl_read32(trans, CSR_INT_MASK); /* just for debug */ |
982 | iwl_write32(trans, CSR_INT_MASK, 0x00000000); | |
1a361cd8 EG |
983 | |
984 | ||
985 | /* Ignore interrupt if there's nothing in NIC to service. | |
986 | * This may be due to IRQ shared with another device, | |
987 | * or due to sporadic interrupts thrown from our NIC. */ | |
b80667ee | 988 | read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); |
6c1011e1 | 989 | trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read); |
b80667ee | 990 | if (!read) { |
0c325769 | 991 | IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); |
1a361cd8 EG |
992 | goto none; |
993 | } | |
994 | ||
b80667ee JB |
995 | /* |
996 | * Collect all entries up to the first 0, starting from ict_index; | |
997 | * note we already read at ict_index. | |
998 | */ | |
999 | do { | |
1000 | val |= read; | |
0c325769 | 1001 | IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n", |
b80667ee | 1002 | trans_pcie->ict_index, read); |
0c325769 EG |
1003 | trans_pcie->ict_tbl[trans_pcie->ict_index] = 0; |
1004 | trans_pcie->ict_index = | |
1005 | iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT); | |
1a361cd8 | 1006 | |
b80667ee | 1007 | read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); |
6c1011e1 | 1008 | trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, |
b80667ee JB |
1009 | read); |
1010 | } while (read); | |
1a361cd8 EG |
1011 | |
1012 | /* We should not get this value, just ignore it. */ | |
1013 | if (val == 0xffffffff) | |
1014 | val = 0; | |
1015 | ||
1016 | /* | |
1017 | * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit | |
1018 | * (bit 15 before shifting it to 31) to clear when using interrupt | |
1019 | * coalescing. fortunately, bits 18 and 19 stay set when this happens | |
1020 | * so we use them to decide on the real state of the Rx bit. | |
1021 | * In order words, bit 15 is set if bit 18 or bit 19 are set. | |
1022 | */ | |
1023 | if (val & 0xC0000) | |
1024 | val |= 0x8000; | |
1025 | ||
1026 | inta = (0xff & val) | ((0xff00 & val) << 16); | |
0c325769 | 1027 | IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n", |
20d3b647 | 1028 | inta, inta_mask, val); |
1a361cd8 | 1029 | |
0c325769 EG |
1030 | inta &= trans_pcie->inta_mask; |
1031 | trans_pcie->inta |= inta; | |
1a361cd8 EG |
1032 | |
1033 | /* iwl_irq_tasklet() will service interrupts and re-enable them */ | |
1034 | if (likely(inta)) | |
0c325769 | 1035 | tasklet_schedule(&trans_pcie->irq_tasklet); |
83626404 | 1036 | else if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) && |
b80667ee | 1037 | !trans_pcie->inta) { |
1a361cd8 EG |
1038 | /* Allow interrupt if was disabled by this handler and |
1039 | * no tasklet was schedules, We should not enable interrupt, | |
1040 | * tasklet will enable it. | |
1041 | */ | |
0c325769 | 1042 | iwl_enable_interrupts(trans); |
1a361cd8 EG |
1043 | } |
1044 | ||
7b11488f | 1045 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
1a361cd8 EG |
1046 | return IRQ_HANDLED; |
1047 | ||
1048 | none: | |
1049 | /* re-enable interrupts here since we don't have anything to service. | |
1050 | * only Re-enable if disabled by irq. | |
1051 | */ | |
83626404 | 1052 | if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) && |
b80667ee | 1053 | !trans_pcie->inta) |
0c325769 | 1054 | iwl_enable_interrupts(trans); |
1a361cd8 | 1055 | |
7b11488f | 1056 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
1a361cd8 EG |
1057 | return IRQ_NONE; |
1058 | } |