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1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
fb4961db | 3 | * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved. |
1053d35f RR |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
1053d35f RR |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
fd4abac5 | 29 | #include <linux/etherdevice.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
253a634c | 31 | #include <linux/sched.h> |
253a634c | 32 | |
522376d2 EG |
33 | #include "iwl-debug.h" |
34 | #include "iwl-csr.h" | |
35 | #include "iwl-prph.h" | |
1053d35f | 36 | #include "iwl-io.h" |
522376d2 | 37 | #include "iwl-agn-hw.h" |
ed277c93 | 38 | #include "iwl-op-mode.h" |
c17d0681 | 39 | #include "iwl-trans-pcie-int.h" |
6238b008 JB |
40 | /* FIXME: need to abstract out TX command (once we know what it looks like) */ |
41 | #include "iwl-commands.h" | |
1053d35f | 42 | |
522376d2 EG |
43 | #define IWL_TX_CRC_SIZE 4 |
44 | #define IWL_TX_DELIMITER_SIZE 4 | |
45 | ||
48d42c42 EG |
46 | /** |
47 | * iwl_trans_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array | |
48 | */ | |
6d8f6eeb | 49 | void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans, |
48d42c42 EG |
50 | struct iwl_tx_queue *txq, |
51 | u16 byte_cnt) | |
52 | { | |
105183b1 | 53 | struct iwlagn_scd_bc_tbl *scd_bc_tbl; |
105183b1 EG |
54 | struct iwl_trans_pcie *trans_pcie = |
55 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
48d42c42 EG |
56 | int write_ptr = txq->q.write_ptr; |
57 | int txq_id = txq->q.id; | |
58 | u8 sec_ctl = 0; | |
59 | u8 sta_id = 0; | |
60 | u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; | |
61 | __le16 bc_ent; | |
132f98c2 | 62 | struct iwl_tx_cmd *tx_cmd = |
bf8440e6 | 63 | (void *) txq->entries[txq->q.write_ptr].cmd->payload; |
48d42c42 | 64 | |
105183b1 EG |
65 | scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; |
66 | ||
48d42c42 EG |
67 | WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX); |
68 | ||
132f98c2 EG |
69 | sta_id = tx_cmd->sta_id; |
70 | sec_ctl = tx_cmd->sec_ctl; | |
48d42c42 EG |
71 | |
72 | switch (sec_ctl & TX_CMD_SEC_MSK) { | |
73 | case TX_CMD_SEC_CCM: | |
74 | len += CCMP_MIC_LEN; | |
75 | break; | |
76 | case TX_CMD_SEC_TKIP: | |
77 | len += TKIP_ICV_LEN; | |
78 | break; | |
79 | case TX_CMD_SEC_WEP: | |
80 | len += WEP_IV_LEN + WEP_ICV_LEN; | |
81 | break; | |
82 | } | |
83 | ||
84 | bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12)); | |
85 | ||
86 | scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; | |
87 | ||
88 | if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
89 | scd_bc_tbl[txq_id]. | |
90 | tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; | |
91 | } | |
92 | ||
fd4abac5 TW |
93 | /** |
94 | * iwl_txq_update_write_ptr - Send new write index to hardware | |
95 | */ | |
fd656935 | 96 | void iwl_txq_update_write_ptr(struct iwl_trans *trans, struct iwl_tx_queue *txq) |
fd4abac5 TW |
97 | { |
98 | u32 reg = 0; | |
fd4abac5 TW |
99 | int txq_id = txq->q.id; |
100 | ||
101 | if (txq->need_update == 0) | |
7bfedc59 | 102 | return; |
fd4abac5 | 103 | |
035f7ff2 | 104 | if (trans->cfg->base_params->shadow_reg_enable) { |
f81c1f48 | 105 | /* shadow register enabled */ |
1042db2a | 106 | iwl_write32(trans, HBUS_TARG_WRPTR, |
f81c1f48 WYG |
107 | txq->q.write_ptr | (txq_id << 8)); |
108 | } else { | |
47107e84 DF |
109 | struct iwl_trans_pcie *trans_pcie = |
110 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
f81c1f48 | 111 | /* if we're trying to save power */ |
01d651d4 | 112 | if (test_bit(STATUS_TPOWER_PMI, &trans_pcie->status)) { |
f81c1f48 WYG |
113 | /* wake up nic if it's powered down ... |
114 | * uCode will wake up, and interrupt us again, so next | |
115 | * time we'll skip this part. */ | |
1042db2a | 116 | reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); |
fd4abac5 | 117 | |
f81c1f48 | 118 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { |
fd656935 | 119 | IWL_DEBUG_INFO(trans, |
f81c1f48 WYG |
120 | "Tx queue %d requesting wakeup," |
121 | " GP1 = 0x%x\n", txq_id, reg); | |
1042db2a | 122 | iwl_set_bit(trans, CSR_GP_CNTRL, |
f81c1f48 WYG |
123 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
124 | return; | |
125 | } | |
fd4abac5 | 126 | |
1042db2a | 127 | iwl_write_direct32(trans, HBUS_TARG_WRPTR, |
fd4abac5 | 128 | txq->q.write_ptr | (txq_id << 8)); |
fd4abac5 | 129 | |
f81c1f48 WYG |
130 | /* |
131 | * else not in power-save mode, | |
132 | * uCode will never sleep when we're | |
133 | * trying to tx (during RFKILL, we're not trying to tx). | |
134 | */ | |
135 | } else | |
1042db2a | 136 | iwl_write32(trans, HBUS_TARG_WRPTR, |
f81c1f48 WYG |
137 | txq->q.write_ptr | (txq_id << 8)); |
138 | } | |
fd4abac5 | 139 | txq->need_update = 0; |
fd4abac5 | 140 | } |
fd4abac5 | 141 | |
214d14d4 JB |
142 | static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
143 | { | |
144 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
145 | ||
146 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
147 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
148 | addr |= | |
149 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
150 | ||
151 | return addr; | |
152 | } | |
153 | ||
154 | static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) | |
155 | { | |
156 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
157 | ||
158 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
159 | } | |
160 | ||
161 | static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, | |
162 | dma_addr_t addr, u16 len) | |
163 | { | |
164 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
165 | u16 hi_n_len = len << 4; | |
166 | ||
167 | put_unaligned_le32(addr, &tb->lo); | |
168 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
169 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
170 | ||
171 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
172 | ||
173 | tfd->num_tbs = idx + 1; | |
174 | } | |
175 | ||
176 | static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd) | |
177 | { | |
178 | return tfd->num_tbs & 0x1f; | |
179 | } | |
180 | ||
6d8f6eeb | 181 | static void iwlagn_unmap_tfd(struct iwl_trans *trans, struct iwl_cmd_meta *meta, |
253a634c | 182 | struct iwl_tfd *tfd, enum dma_data_direction dma_dir) |
214d14d4 | 183 | { |
214d14d4 JB |
184 | int i; |
185 | int num_tbs; | |
186 | ||
214d14d4 JB |
187 | /* Sanity check on number of chunks */ |
188 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
189 | ||
190 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
6d8f6eeb | 191 | IWL_ERR(trans, "Too many chunks: %i\n", num_tbs); |
214d14d4 JB |
192 | /* @todo issue fatal error, it is quite serious situation */ |
193 | return; | |
194 | } | |
195 | ||
196 | /* Unmap tx_cmd */ | |
197 | if (num_tbs) | |
1042db2a | 198 | dma_unmap_single(trans->dev, |
4ce7cc2b JB |
199 | dma_unmap_addr(meta, mapping), |
200 | dma_unmap_len(meta, len), | |
795414db | 201 | DMA_BIDIRECTIONAL); |
214d14d4 JB |
202 | |
203 | /* Unmap chunks, if any. */ | |
204 | for (i = 1; i < num_tbs; i++) | |
1042db2a | 205 | dma_unmap_single(trans->dev, iwl_tfd_tb_get_addr(tfd, i), |
e815407d | 206 | iwl_tfd_tb_get_len(tfd, i), dma_dir); |
4ce7cc2b JB |
207 | } |
208 | ||
209 | /** | |
210 | * iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
6d8f6eeb | 211 | * @trans - transport private data |
4ce7cc2b | 212 | * @txq - tx queue |
1359ca4f | 213 | * @index - the index of the TFD to be freed |
39644e9a | 214 | *@dma_dir - the direction of the DMA mapping |
4ce7cc2b JB |
215 | * |
216 | * Does NOT advance any TFD circular buffer read/write indexes | |
217 | * Does NOT free the TFD itself (which is within circular buffer) | |
218 | */ | |
6d8f6eeb | 219 | void iwlagn_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq, |
39644e9a | 220 | int index, enum dma_data_direction dma_dir) |
4ce7cc2b JB |
221 | { |
222 | struct iwl_tfd *tfd_tmp = txq->tfds; | |
4ce7cc2b | 223 | |
015c15e1 JB |
224 | lockdep_assert_held(&txq->lock); |
225 | ||
bf8440e6 JB |
226 | iwlagn_unmap_tfd(trans, &txq->entries[index].meta, |
227 | &tfd_tmp[index], dma_dir); | |
214d14d4 JB |
228 | |
229 | /* free SKB */ | |
bf8440e6 | 230 | if (txq->entries) { |
214d14d4 JB |
231 | struct sk_buff *skb; |
232 | ||
bf8440e6 | 233 | skb = txq->entries[index].skb; |
214d14d4 | 234 | |
909e9b23 EG |
235 | /* Can be called from irqs-disabled context |
236 | * If skb is not NULL, it means that the whole queue is being | |
237 | * freed and that the queue is not empty - free the skb | |
238 | */ | |
214d14d4 | 239 | if (skb) { |
ed277c93 | 240 | iwl_op_mode_free_skb(trans->op_mode, skb); |
bf8440e6 | 241 | txq->entries[index].skb = NULL; |
214d14d4 JB |
242 | } |
243 | } | |
244 | } | |
245 | ||
6d8f6eeb | 246 | int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans, |
214d14d4 JB |
247 | struct iwl_tx_queue *txq, |
248 | dma_addr_t addr, u16 len, | |
4c42db0f | 249 | u8 reset) |
214d14d4 JB |
250 | { |
251 | struct iwl_queue *q; | |
252 | struct iwl_tfd *tfd, *tfd_tmp; | |
253 | u32 num_tbs; | |
254 | ||
255 | q = &txq->q; | |
4ce7cc2b | 256 | tfd_tmp = txq->tfds; |
214d14d4 JB |
257 | tfd = &tfd_tmp[q->write_ptr]; |
258 | ||
259 | if (reset) | |
260 | memset(tfd, 0, sizeof(*tfd)); | |
261 | ||
262 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
263 | ||
264 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
265 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
6d8f6eeb | 266 | IWL_ERR(trans, "Error can not send more than %d chunks\n", |
214d14d4 JB |
267 | IWL_NUM_OF_TBS); |
268 | return -EINVAL; | |
269 | } | |
270 | ||
271 | if (WARN_ON(addr & ~DMA_BIT_MASK(36))) | |
272 | return -EINVAL; | |
273 | ||
274 | if (unlikely(addr & ~IWL_TX_DMA_MASK)) | |
6d8f6eeb | 275 | IWL_ERR(trans, "Unaligned address = %llx\n", |
214d14d4 JB |
276 | (unsigned long long)addr); |
277 | ||
278 | iwl_tfd_set_tb(tfd, num_tbs, addr, len); | |
279 | ||
280 | return 0; | |
281 | } | |
282 | ||
fd4abac5 TW |
283 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
284 | * DMA services | |
285 | * | |
286 | * Theory of operation | |
287 | * | |
288 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
289 | * of buffer descriptors, each of which points to one or more data buffers for | |
290 | * the device to read from or fill. Driver and device exchange status of each | |
291 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
292 | * entries in each circular buffer, to protect against confusing empty and full | |
293 | * queue states. | |
294 | * | |
295 | * The device reads or writes the data in the queues via the device's several | |
296 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
297 | * | |
298 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
299 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
300 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
301 | * Tx queue resumed. | |
302 | * | |
fd4abac5 TW |
303 | ***************************************************/ |
304 | ||
305 | int iwl_queue_space(const struct iwl_queue *q) | |
306 | { | |
307 | int s = q->read_ptr - q->write_ptr; | |
308 | ||
309 | if (q->read_ptr > q->write_ptr) | |
310 | s -= q->n_bd; | |
311 | ||
312 | if (s <= 0) | |
313 | s += q->n_window; | |
314 | /* keep some reserve to not confuse empty and full situations */ | |
315 | s -= 2; | |
316 | if (s < 0) | |
317 | s = 0; | |
318 | return s; | |
319 | } | |
fd4abac5 | 320 | |
1053d35f RR |
321 | /** |
322 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes | |
323 | */ | |
6d8f6eeb | 324 | int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id) |
1053d35f RR |
325 | { |
326 | q->n_bd = count; | |
327 | q->n_window = slots_num; | |
328 | q->id = id; | |
329 | ||
330 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap | |
331 | * and iwl_queue_dec_wrap are broken. */ | |
3e41ace5 JB |
332 | if (WARN_ON(!is_power_of_2(count))) |
333 | return -EINVAL; | |
1053d35f RR |
334 | |
335 | /* slots_num must be power-of-two size, otherwise | |
336 | * get_cmd_index is broken. */ | |
3e41ace5 JB |
337 | if (WARN_ON(!is_power_of_2(slots_num))) |
338 | return -EINVAL; | |
1053d35f RR |
339 | |
340 | q->low_mark = q->n_window / 4; | |
341 | if (q->low_mark < 4) | |
342 | q->low_mark = 4; | |
343 | ||
344 | q->high_mark = q->n_window / 8; | |
345 | if (q->high_mark < 2) | |
346 | q->high_mark = 2; | |
347 | ||
348 | q->write_ptr = q->read_ptr = 0; | |
349 | ||
350 | return 0; | |
351 | } | |
352 | ||
6d8f6eeb | 353 | static void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_trans *trans, |
48d42c42 EG |
354 | struct iwl_tx_queue *txq) |
355 | { | |
105183b1 EG |
356 | struct iwl_trans_pcie *trans_pcie = |
357 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
6d8f6eeb | 358 | struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; |
48d42c42 EG |
359 | int txq_id = txq->q.id; |
360 | int read_ptr = txq->q.read_ptr; | |
361 | u8 sta_id = 0; | |
362 | __le16 bc_ent; | |
132f98c2 | 363 | struct iwl_tx_cmd *tx_cmd = |
bf8440e6 | 364 | (void *)txq->entries[txq->q.read_ptr].cmd->payload; |
48d42c42 EG |
365 | |
366 | WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); | |
367 | ||
c6f600fc | 368 | if (txq_id != trans_pcie->cmd_queue) |
132f98c2 | 369 | sta_id = tx_cmd->sta_id; |
48d42c42 EG |
370 | |
371 | bc_ent = cpu_to_le16(1 | (sta_id << 12)); | |
372 | scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; | |
373 | ||
374 | if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
375 | scd_bc_tbl[txq_id]. | |
376 | tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; | |
377 | } | |
378 | ||
6d8f6eeb | 379 | static int iwlagn_tx_queue_set_q2ratid(struct iwl_trans *trans, u16 ra_tid, |
48d42c42 EG |
380 | u16 txq_id) |
381 | { | |
382 | u32 tbl_dw_addr; | |
383 | u32 tbl_dw; | |
384 | u16 scd_q2ratid; | |
385 | ||
105183b1 EG |
386 | struct iwl_trans_pcie *trans_pcie = |
387 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
388 | ||
48d42c42 EG |
389 | scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; |
390 | ||
105183b1 | 391 | tbl_dw_addr = trans_pcie->scd_base_addr + |
48d42c42 EG |
392 | SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); |
393 | ||
1042db2a | 394 | tbl_dw = iwl_read_targ_mem(trans, tbl_dw_addr); |
48d42c42 EG |
395 | |
396 | if (txq_id & 0x1) | |
397 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); | |
398 | else | |
399 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); | |
400 | ||
1042db2a | 401 | iwl_write_targ_mem(trans, tbl_dw_addr, tbl_dw); |
48d42c42 EG |
402 | |
403 | return 0; | |
404 | } | |
405 | ||
6d8f6eeb | 406 | static void iwlagn_tx_queue_stop_scheduler(struct iwl_trans *trans, u16 txq_id) |
48d42c42 EG |
407 | { |
408 | /* Simply stop the queue, but don't change any configuration; | |
409 | * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ | |
1042db2a | 410 | iwl_write_prph(trans, |
48d42c42 EG |
411 | SCD_QUEUE_STATUS_BITS(txq_id), |
412 | (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)| | |
413 | (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); | |
414 | } | |
415 | ||
6d8f6eeb | 416 | void iwl_trans_set_wr_ptrs(struct iwl_trans *trans, |
48d42c42 EG |
417 | int txq_id, u32 index) |
418 | { | |
0ca24daf | 419 | IWL_DEBUG_TX_QUEUES(trans, "Q %d WrPtr: %d\n", txq_id, index & 0xff); |
1042db2a | 420 | iwl_write_direct32(trans, HBUS_TARG_WRPTR, |
48d42c42 | 421 | (index & 0xff) | (txq_id << 8)); |
1042db2a | 422 | iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), index); |
48d42c42 EG |
423 | } |
424 | ||
c91bd124 | 425 | void iwl_trans_tx_queue_set_status(struct iwl_trans *trans, |
9eae88fa JB |
426 | struct iwl_tx_queue *txq, |
427 | int tx_fifo_id, bool active) | |
48d42c42 EG |
428 | { |
429 | int txq_id = txq->q.id; | |
48d42c42 | 430 | |
1042db2a | 431 | iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id), |
48d42c42 EG |
432 | (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) | |
433 | (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) | | |
434 | (1 << SCD_QUEUE_STTS_REG_POS_WSL) | | |
435 | SCD_QUEUE_STTS_REG_MSK); | |
436 | ||
1dcedc8e | 437 | if (active) |
9eae88fa JB |
438 | IWL_DEBUG_TX_QUEUES(trans, "Activate queue %d on FIFO %d\n", |
439 | txq_id, tx_fifo_id); | |
1dcedc8e | 440 | else |
9eae88fa | 441 | IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id); |
76bc10fc EG |
442 | } |
443 | ||
9eae88fa JB |
444 | void iwl_trans_pcie_tx_agg_setup(struct iwl_trans *trans, int txq_id, int fifo, |
445 | int sta_id, int tid, int frame_limit, u16 ssn) | |
48d42c42 | 446 | { |
9eae88fa | 447 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
48d42c42 | 448 | unsigned long flags; |
9eae88fa | 449 | u16 ra_tid = BUILD_RAxTID(sta_id, tid); |
48d42c42 | 450 | |
9eae88fa JB |
451 | if (test_and_set_bit(txq_id, trans_pcie->queue_used)) |
452 | WARN_ONCE(1, "queue %d already used - expect issues", txq_id); | |
48d42c42 | 453 | |
7b11488f | 454 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
48d42c42 EG |
455 | |
456 | /* Stop this Tx queue before configuring it */ | |
6d8f6eeb | 457 | iwlagn_tx_queue_stop_scheduler(trans, txq_id); |
48d42c42 EG |
458 | |
459 | /* Map receiver-address / traffic-ID to this queue */ | |
6d8f6eeb | 460 | iwlagn_tx_queue_set_q2ratid(trans, ra_tid, txq_id); |
48d42c42 EG |
461 | |
462 | /* Set this queue as a chain-building queue */ | |
9eae88fa | 463 | iwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, BIT(txq_id)); |
48d42c42 EG |
464 | |
465 | /* enable aggregations for the queue */ | |
9eae88fa | 466 | iwl_set_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id)); |
48d42c42 EG |
467 | |
468 | /* Place first TFD at index corresponding to start sequence number. | |
469 | * Assumes that ssn_idx is valid (!= 0xFFF) */ | |
822e8b2a EG |
470 | trans_pcie->txq[txq_id].q.read_ptr = (ssn & 0xff); |
471 | trans_pcie->txq[txq_id].q.write_ptr = (ssn & 0xff); | |
472 | iwl_trans_set_wr_ptrs(trans, txq_id, ssn); | |
48d42c42 EG |
473 | |
474 | /* Set up Tx window size and frame limit for this queue */ | |
1042db2a | 475 | iwl_write_targ_mem(trans, trans_pcie->scd_base_addr + |
9eae88fa JB |
476 | SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), |
477 | ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
478 | SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
479 | ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
480 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
48d42c42 | 481 | |
1042db2a | 482 | iwl_set_bits_prph(trans, SCD_INTERRUPT_MASK, (1 << txq_id)); |
48d42c42 EG |
483 | |
484 | /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ | |
8ad71bef | 485 | iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id], |
9eae88fa | 486 | fifo, true); |
a0eaad71 | 487 | |
7b11488f | 488 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
48d42c42 EG |
489 | } |
490 | ||
9eae88fa | 491 | void iwl_trans_pcie_tx_agg_disable(struct iwl_trans *trans, int txq_id) |
288712a6 | 492 | { |
8ad71bef | 493 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
288712a6 | 494 | |
9eae88fa JB |
495 | if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) { |
496 | WARN_ONCE(1, "queue %d not used", txq_id); | |
497 | return; | |
48d42c42 EG |
498 | } |
499 | ||
bc237730 | 500 | iwlagn_tx_queue_stop_scheduler(trans, txq_id); |
7f01d567 | 501 | |
9eae88fa | 502 | iwl_clear_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id)); |
48d42c42 | 503 | |
bc237730 EG |
504 | trans_pcie->txq[txq_id].q.read_ptr = 0; |
505 | trans_pcie->txq[txq_id].q.write_ptr = 0; | |
bc237730 | 506 | iwl_trans_set_wr_ptrs(trans, txq_id, 0); |
48d42c42 | 507 | |
9eae88fa JB |
508 | iwl_clear_bits_prph(trans, SCD_INTERRUPT_MASK, BIT(txq_id)); |
509 | ||
510 | iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id], | |
511 | 0, false); | |
48d42c42 EG |
512 | } |
513 | ||
fd4abac5 TW |
514 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ |
515 | ||
516 | /** | |
517 | * iwl_enqueue_hcmd - enqueue a uCode command | |
518 | * @priv: device private data point | |
519 | * @cmd: a point to the ucode command structure | |
520 | * | |
521 | * The function returns < 0 values to indicate the operation is | |
522 | * failed. On success, it turns the index (> 0) of command in the | |
523 | * command queue. | |
524 | */ | |
6d8f6eeb | 525 | static int iwl_enqueue_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
fd4abac5 | 526 | { |
8ad71bef | 527 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
c6f600fc | 528 | struct iwl_tx_queue *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
fd4abac5 | 529 | struct iwl_queue *q = &txq->q; |
c2acea8e JB |
530 | struct iwl_device_cmd *out_cmd; |
531 | struct iwl_cmd_meta *out_meta; | |
fd4abac5 | 532 | dma_addr_t phys_addr; |
f3674227 | 533 | u32 idx; |
4ce7cc2b | 534 | u16 copy_size, cmd_size; |
4ce7cc2b JB |
535 | bool had_nocopy = false; |
536 | int i; | |
537 | u8 *cmd_dest; | |
538 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
539 | const void *trace_bufs[IWL_MAX_CMD_TFDS + 1] = {}; | |
540 | int trace_lens[IWL_MAX_CMD_TFDS + 1] = {}; | |
541 | int trace_idx; | |
542 | #endif | |
fd4abac5 | 543 | |
4ce7cc2b JB |
544 | copy_size = sizeof(out_cmd->hdr); |
545 | cmd_size = sizeof(out_cmd->hdr); | |
546 | ||
547 | /* need one for the header if the first is NOCOPY */ | |
548 | BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1); | |
549 | ||
550 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
551 | if (!cmd->len[i]) | |
552 | continue; | |
553 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { | |
554 | had_nocopy = true; | |
555 | } else { | |
556 | /* NOCOPY must not be followed by normal! */ | |
557 | if (WARN_ON(had_nocopy)) | |
558 | return -EINVAL; | |
559 | copy_size += cmd->len[i]; | |
560 | } | |
561 | cmd_size += cmd->len[i]; | |
562 | } | |
fd4abac5 | 563 | |
3e41ace5 JB |
564 | /* |
565 | * If any of the command structures end up being larger than | |
4ce7cc2b JB |
566 | * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically |
567 | * allocated into separate TFDs, then we will need to | |
568 | * increase the size of the buffers. | |
3e41ace5 | 569 | */ |
4ce7cc2b | 570 | if (WARN_ON(copy_size > TFD_MAX_PAYLOAD_SIZE)) |
3e41ace5 | 571 | return -EINVAL; |
fd4abac5 | 572 | |
015c15e1 | 573 | spin_lock_bh(&txq->lock); |
3598e177 | 574 | |
c2acea8e | 575 | if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { |
015c15e1 | 576 | spin_unlock_bh(&txq->lock); |
3598e177 | 577 | |
6d8f6eeb | 578 | IWL_ERR(trans, "No space in command queue\n"); |
0e781842 | 579 | iwl_op_mode_cmd_queue_full(trans->op_mode); |
fd4abac5 TW |
580 | return -ENOSPC; |
581 | } | |
582 | ||
4ce7cc2b | 583 | idx = get_cmd_index(q, q->write_ptr); |
bf8440e6 JB |
584 | out_cmd = txq->entries[idx].cmd; |
585 | out_meta = &txq->entries[idx].meta; | |
c2acea8e | 586 | |
8ce73f3a | 587 | memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ |
c2acea8e JB |
588 | if (cmd->flags & CMD_WANT_SKB) |
589 | out_meta->source = cmd; | |
fd4abac5 | 590 | |
4ce7cc2b | 591 | /* set up the header */ |
fd4abac5 | 592 | |
4ce7cc2b | 593 | out_cmd->hdr.cmd = cmd->id; |
fd4abac5 | 594 | out_cmd->hdr.flags = 0; |
cefeaa5f | 595 | out_cmd->hdr.sequence = |
c6f600fc | 596 | cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | |
cefeaa5f | 597 | INDEX_TO_SEQ(q->write_ptr)); |
4ce7cc2b JB |
598 | |
599 | /* and copy the data that needs to be copied */ | |
600 | ||
132f98c2 | 601 | cmd_dest = out_cmd->payload; |
4ce7cc2b JB |
602 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { |
603 | if (!cmd->len[i]) | |
604 | continue; | |
605 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) | |
606 | break; | |
607 | memcpy(cmd_dest, cmd->data[i], cmd->len[i]); | |
608 | cmd_dest += cmd->len[i]; | |
ded2ae7c | 609 | } |
4ce7cc2b | 610 | |
d9fb6465 JB |
611 | IWL_DEBUG_HC(trans, |
612 | "Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n", | |
613 | trans_pcie_get_cmd_string(trans_pcie, out_cmd->hdr.cmd), | |
614 | out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence), cmd_size, | |
615 | q->write_ptr, idx, trans_pcie->cmd_queue); | |
4ce7cc2b | 616 | |
1042db2a | 617 | phys_addr = dma_map_single(trans->dev, &out_cmd->hdr, copy_size, |
795414db | 618 | DMA_BIDIRECTIONAL); |
1042db2a | 619 | if (unlikely(dma_mapping_error(trans->dev, phys_addr))) { |
2c46f72e JB |
620 | idx = -ENOMEM; |
621 | goto out; | |
622 | } | |
623 | ||
2e724443 | 624 | dma_unmap_addr_set(out_meta, mapping, phys_addr); |
4ce7cc2b JB |
625 | dma_unmap_len_set(out_meta, len, copy_size); |
626 | ||
6d8f6eeb EG |
627 | iwlagn_txq_attach_buf_to_tfd(trans, txq, |
628 | phys_addr, copy_size, 1); | |
4ce7cc2b JB |
629 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING |
630 | trace_bufs[0] = &out_cmd->hdr; | |
631 | trace_lens[0] = copy_size; | |
632 | trace_idx = 1; | |
633 | #endif | |
634 | ||
635 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
636 | if (!cmd->len[i]) | |
637 | continue; | |
638 | if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY)) | |
639 | continue; | |
1042db2a | 640 | phys_addr = dma_map_single(trans->dev, |
6d8f6eeb | 641 | (void *)cmd->data[i], |
3be3fdb5 | 642 | cmd->len[i], DMA_BIDIRECTIONAL); |
1042db2a | 643 | if (dma_mapping_error(trans->dev, phys_addr)) { |
6d8f6eeb | 644 | iwlagn_unmap_tfd(trans, out_meta, |
e815407d | 645 | &txq->tfds[q->write_ptr], |
3be3fdb5 | 646 | DMA_BIDIRECTIONAL); |
4ce7cc2b JB |
647 | idx = -ENOMEM; |
648 | goto out; | |
649 | } | |
650 | ||
6d8f6eeb | 651 | iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr, |
4ce7cc2b JB |
652 | cmd->len[i], 0); |
653 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
654 | trace_bufs[trace_idx] = cmd->data[i]; | |
655 | trace_lens[trace_idx] = cmd->len[i]; | |
656 | trace_idx++; | |
657 | #endif | |
658 | } | |
df833b1d | 659 | |
afaf6b57 | 660 | out_meta->flags = cmd->flags; |
2c46f72e JB |
661 | |
662 | txq->need_update = 1; | |
663 | ||
4ce7cc2b JB |
664 | /* check that tracing gets all possible blocks */ |
665 | BUILD_BUG_ON(IWL_MAX_CMD_TFDS + 1 != 3); | |
666 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
6c1011e1 | 667 | trace_iwlwifi_dev_hcmd(trans->dev, cmd->flags, |
4ce7cc2b JB |
668 | trace_bufs[0], trace_lens[0], |
669 | trace_bufs[1], trace_lens[1], | |
670 | trace_bufs[2], trace_lens[2]); | |
671 | #endif | |
df833b1d | 672 | |
7c5ba4a8 JB |
673 | /* start timer if queue currently empty */ |
674 | if (q->read_ptr == q->write_ptr && trans_pcie->wd_timeout) | |
675 | mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout); | |
676 | ||
fd4abac5 TW |
677 | /* Increment and update queue's write index */ |
678 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
fd656935 | 679 | iwl_txq_update_write_ptr(trans, txq); |
fd4abac5 | 680 | |
2c46f72e | 681 | out: |
015c15e1 | 682 | spin_unlock_bh(&txq->lock); |
7bfedc59 | 683 | return idx; |
fd4abac5 TW |
684 | } |
685 | ||
7c5ba4a8 JB |
686 | static inline void iwl_queue_progress(struct iwl_trans_pcie *trans_pcie, |
687 | struct iwl_tx_queue *txq) | |
688 | { | |
689 | if (!trans_pcie->wd_timeout) | |
690 | return; | |
691 | ||
692 | /* | |
693 | * if empty delete timer, otherwise move timer forward | |
694 | * since we're making progress on this queue | |
695 | */ | |
696 | if (txq->q.read_ptr == txq->q.write_ptr) | |
697 | del_timer(&txq->stuck_timer); | |
698 | else | |
699 | mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout); | |
700 | } | |
701 | ||
17b88929 TW |
702 | /** |
703 | * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd | |
704 | * | |
705 | * When FW advances 'R' index, all entries between old and new 'R' index | |
706 | * need to be reclaimed. As result, some free space forms. If there is | |
707 | * enough free space (> low mark), wake the stack that feeds us. | |
708 | */ | |
3e10caeb EG |
709 | static void iwl_hcmd_queue_reclaim(struct iwl_trans *trans, int txq_id, |
710 | int idx) | |
17b88929 | 711 | { |
3e10caeb | 712 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
8ad71bef | 713 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; |
17b88929 TW |
714 | struct iwl_queue *q = &txq->q; |
715 | int nfreed = 0; | |
716 | ||
015c15e1 JB |
717 | lockdep_assert_held(&txq->lock); |
718 | ||
499b1883 | 719 | if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) { |
3e10caeb | 720 | IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), " |
2e5d04da DH |
721 | "index %d is out of range [0-%d] %d %d.\n", __func__, |
722 | txq_id, idx, q->n_bd, q->write_ptr, q->read_ptr); | |
17b88929 TW |
723 | return; |
724 | } | |
725 | ||
499b1883 TW |
726 | for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; |
727 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
17b88929 | 728 | |
499b1883 | 729 | if (nfreed++ > 0) { |
3e10caeb | 730 | IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", idx, |
17b88929 | 731 | q->write_ptr, q->read_ptr); |
bcb9321c | 732 | iwl_op_mode_nic_error(trans->op_mode); |
17b88929 | 733 | } |
da99c4b6 | 734 | |
17b88929 | 735 | } |
7c5ba4a8 JB |
736 | |
737 | iwl_queue_progress(trans_pcie, txq); | |
17b88929 TW |
738 | } |
739 | ||
740 | /** | |
741 | * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them | |
742 | * @rxb: Rx buffer to reclaim | |
247c61d6 EG |
743 | * @handler_status: return value of the handler of the command |
744 | * (put in setup_rx_handlers) | |
17b88929 TW |
745 | * |
746 | * If an Rx buffer has an async callback associated with it the callback | |
747 | * will be executed. The attached skb (if present) will only be freed | |
748 | * if the callback returns 1 | |
749 | */ | |
48a2d66f | 750 | void iwl_tx_cmd_complete(struct iwl_trans *trans, struct iwl_rx_cmd_buffer *rxb, |
247c61d6 | 751 | int handler_status) |
17b88929 | 752 | { |
2f301227 | 753 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
17b88929 TW |
754 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
755 | int txq_id = SEQ_TO_QUEUE(sequence); | |
756 | int index = SEQ_TO_INDEX(sequence); | |
17b88929 | 757 | int cmd_index; |
c2acea8e JB |
758 | struct iwl_device_cmd *cmd; |
759 | struct iwl_cmd_meta *meta; | |
8ad71bef | 760 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
c6f600fc | 761 | struct iwl_tx_queue *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
17b88929 TW |
762 | |
763 | /* If a Tx command is being handled and it isn't in the actual | |
764 | * command queue then there a command routing bug has been introduced | |
765 | * in the queue management code. */ | |
c6f600fc | 766 | if (WARN(txq_id != trans_pcie->cmd_queue, |
13bb9483 | 767 | "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", |
c6f600fc MV |
768 | txq_id, trans_pcie->cmd_queue, sequence, |
769 | trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr, | |
770 | trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) { | |
3e10caeb | 771 | iwl_print_hex_error(trans, pkt, 32); |
55d6a3cd | 772 | return; |
01ef9323 | 773 | } |
17b88929 | 774 | |
015c15e1 JB |
775 | spin_lock(&txq->lock); |
776 | ||
4ce7cc2b | 777 | cmd_index = get_cmd_index(&txq->q, index); |
bf8440e6 JB |
778 | cmd = txq->entries[cmd_index].cmd; |
779 | meta = &txq->entries[cmd_index].meta; | |
17b88929 | 780 | |
6d8f6eeb EG |
781 | iwlagn_unmap_tfd(trans, meta, &txq->tfds[index], |
782 | DMA_BIDIRECTIONAL); | |
c33de625 | 783 | |
17b88929 | 784 | /* Input error checking is done when commands are added to queue. */ |
c2acea8e | 785 | if (meta->flags & CMD_WANT_SKB) { |
48a2d66f | 786 | struct page *p = rxb_steal_page(rxb); |
65b94a4a | 787 | |
65b94a4a JB |
788 | meta->source->resp_pkt = pkt; |
789 | meta->source->_rx_page_addr = (unsigned long)page_address(p); | |
b2cf410c | 790 | meta->source->_rx_page_order = trans_pcie->rx_page_order; |
247c61d6 | 791 | meta->source->handler_status = handler_status; |
247c61d6 | 792 | } |
2624e96c | 793 | |
3e10caeb | 794 | iwl_hcmd_queue_reclaim(trans, txq_id, index); |
17b88929 | 795 | |
c2acea8e | 796 | if (!(meta->flags & CMD_ASYNC)) { |
74fda971 | 797 | if (!test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) { |
05c89b91 WYG |
798 | IWL_WARN(trans, |
799 | "HCMD_ACTIVE already clear for command %s\n", | |
d9fb6465 JB |
800 | trans_pcie_get_cmd_string(trans_pcie, |
801 | cmd->hdr.cmd)); | |
05c89b91 | 802 | } |
74fda971 | 803 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); |
6d8f6eeb | 804 | IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", |
d9fb6465 JB |
805 | trans_pcie_get_cmd_string(trans_pcie, |
806 | cmd->hdr.cmd)); | |
69a10b29 | 807 | wake_up(&trans->wait_command_queue); |
17b88929 | 808 | } |
3598e177 | 809 | |
dd487449 | 810 | meta->flags = 0; |
3598e177 | 811 | |
015c15e1 | 812 | spin_unlock(&txq->lock); |
17b88929 | 813 | } |
253a634c | 814 | |
253a634c EG |
815 | #define HOST_COMPLETE_TIMEOUT (2 * HZ) |
816 | ||
6d8f6eeb | 817 | static int iwl_send_cmd_async(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c | 818 | { |
d9fb6465 | 819 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
253a634c EG |
820 | int ret; |
821 | ||
822 | /* An asynchronous command can not expect an SKB to be set. */ | |
823 | if (WARN_ON(cmd->flags & CMD_WANT_SKB)) | |
824 | return -EINVAL; | |
825 | ||
253a634c | 826 | |
6d8f6eeb | 827 | ret = iwl_enqueue_hcmd(trans, cmd); |
253a634c | 828 | if (ret < 0) { |
721c32f7 | 829 | IWL_ERR(trans, |
b36b110c | 830 | "Error sending %s: enqueue_hcmd failed: %d\n", |
d9fb6465 | 831 | trans_pcie_get_cmd_string(trans_pcie, cmd->id), ret); |
253a634c EG |
832 | return ret; |
833 | } | |
834 | return 0; | |
835 | } | |
836 | ||
6d8f6eeb | 837 | static int iwl_send_cmd_sync(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c | 838 | { |
8ad71bef | 839 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
253a634c EG |
840 | int cmd_idx; |
841 | int ret; | |
842 | ||
6d8f6eeb | 843 | IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", |
d9fb6465 | 844 | trans_pcie_get_cmd_string(trans_pcie, cmd->id)); |
253a634c | 845 | |
2cc39c94 | 846 | if (WARN_ON(test_and_set_bit(STATUS_HCMD_ACTIVE, |
74fda971 | 847 | &trans_pcie->status))) { |
2cc39c94 | 848 | IWL_ERR(trans, "Command %s: a command is already active!\n", |
d9fb6465 | 849 | trans_pcie_get_cmd_string(trans_pcie, cmd->id)); |
2cc39c94 JB |
850 | return -EIO; |
851 | } | |
852 | ||
6d8f6eeb | 853 | IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", |
d9fb6465 | 854 | trans_pcie_get_cmd_string(trans_pcie, cmd->id)); |
253a634c | 855 | |
6d8f6eeb | 856 | cmd_idx = iwl_enqueue_hcmd(trans, cmd); |
253a634c EG |
857 | if (cmd_idx < 0) { |
858 | ret = cmd_idx; | |
74fda971 | 859 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); |
721c32f7 | 860 | IWL_ERR(trans, |
b36b110c | 861 | "Error sending %s: enqueue_hcmd failed: %d\n", |
d9fb6465 | 862 | trans_pcie_get_cmd_string(trans_pcie, cmd->id), ret); |
253a634c EG |
863 | return ret; |
864 | } | |
865 | ||
69a10b29 | 866 | ret = wait_event_timeout(trans->wait_command_queue, |
74fda971 | 867 | !test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status), |
253a634c EG |
868 | HOST_COMPLETE_TIMEOUT); |
869 | if (!ret) { | |
74fda971 | 870 | if (test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) { |
d10630af | 871 | struct iwl_tx_queue *txq = |
c6f600fc | 872 | &trans_pcie->txq[trans_pcie->cmd_queue]; |
d10630af WYG |
873 | struct iwl_queue *q = &txq->q; |
874 | ||
721c32f7 | 875 | IWL_ERR(trans, |
253a634c | 876 | "Error sending %s: time out after %dms.\n", |
d9fb6465 | 877 | trans_pcie_get_cmd_string(trans_pcie, cmd->id), |
253a634c EG |
878 | jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); |
879 | ||
721c32f7 | 880 | IWL_ERR(trans, |
d10630af WYG |
881 | "Current CMD queue read_ptr %d write_ptr %d\n", |
882 | q->read_ptr, q->write_ptr); | |
883 | ||
74fda971 | 884 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); |
d9fb6465 JB |
885 | IWL_DEBUG_INFO(trans, |
886 | "Clearing HCMD_ACTIVE for command %s\n", | |
887 | trans_pcie_get_cmd_string(trans_pcie, | |
888 | cmd->id)); | |
253a634c EG |
889 | ret = -ETIMEDOUT; |
890 | goto cancel; | |
891 | } | |
892 | } | |
893 | ||
65b94a4a | 894 | if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) { |
6d8f6eeb | 895 | IWL_ERR(trans, "Error: Response NULL in '%s'\n", |
d9fb6465 | 896 | trans_pcie_get_cmd_string(trans_pcie, cmd->id)); |
253a634c EG |
897 | ret = -EIO; |
898 | goto cancel; | |
899 | } | |
900 | ||
901 | return 0; | |
902 | ||
903 | cancel: | |
904 | if (cmd->flags & CMD_WANT_SKB) { | |
905 | /* | |
906 | * Cancel the CMD_WANT_SKB flag for the cmd in the | |
907 | * TX cmd queue. Otherwise in case the cmd comes | |
908 | * in later, it will possibly set an invalid | |
909 | * address (cmd->meta.source). | |
910 | */ | |
bf8440e6 JB |
911 | trans_pcie->txq[trans_pcie->cmd_queue]. |
912 | entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB; | |
253a634c | 913 | } |
9cac4943 | 914 | |
65b94a4a JB |
915 | if (cmd->resp_pkt) { |
916 | iwl_free_resp(cmd); | |
917 | cmd->resp_pkt = NULL; | |
253a634c EG |
918 | } |
919 | ||
920 | return ret; | |
921 | } | |
922 | ||
6d8f6eeb | 923 | int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c EG |
924 | { |
925 | if (cmd->flags & CMD_ASYNC) | |
6d8f6eeb | 926 | return iwl_send_cmd_async(trans, cmd); |
253a634c | 927 | |
6d8f6eeb | 928 | return iwl_send_cmd_sync(trans, cmd); |
253a634c EG |
929 | } |
930 | ||
a0eaad71 | 931 | /* Frees buffers until index _not_ inclusive */ |
464021ff EG |
932 | int iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index, |
933 | struct sk_buff_head *skbs) | |
a0eaad71 | 934 | { |
8ad71bef EG |
935 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
936 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; | |
a0eaad71 | 937 | struct iwl_queue *q = &txq->q; |
a0eaad71 | 938 | int last_to_free; |
464021ff | 939 | int freed = 0; |
a0eaad71 | 940 | |
39644e9a | 941 | /* This function is not meant to release cmd queue*/ |
c6f600fc | 942 | if (WARN_ON(txq_id == trans_pcie->cmd_queue)) |
39644e9a EG |
943 | return 0; |
944 | ||
015c15e1 JB |
945 | lockdep_assert_held(&txq->lock); |
946 | ||
a0eaad71 EG |
947 | /*Since we free until index _not_ inclusive, the one before index is |
948 | * the last we will free. This one must be used */ | |
949 | last_to_free = iwl_queue_dec_wrap(index, q->n_bd); | |
950 | ||
951 | if ((index >= q->n_bd) || | |
952 | (iwl_queue_used(q, last_to_free) == 0)) { | |
953 | IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), " | |
954 | "last_to_free %d is out of range [0-%d] %d %d.\n", | |
955 | __func__, txq_id, last_to_free, q->n_bd, | |
956 | q->write_ptr, q->read_ptr); | |
464021ff | 957 | return 0; |
a0eaad71 EG |
958 | } |
959 | ||
a0eaad71 | 960 | if (WARN_ON(!skb_queue_empty(skbs))) |
464021ff | 961 | return 0; |
a0eaad71 EG |
962 | |
963 | for (; | |
964 | q->read_ptr != index; | |
965 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
966 | ||
bf8440e6 | 967 | if (WARN_ON_ONCE(txq->entries[txq->q.read_ptr].skb == NULL)) |
a0eaad71 EG |
968 | continue; |
969 | ||
bf8440e6 | 970 | __skb_queue_tail(skbs, txq->entries[txq->q.read_ptr].skb); |
a0eaad71 | 971 | |
bf8440e6 | 972 | txq->entries[txq->q.read_ptr].skb = NULL; |
a0eaad71 | 973 | |
6d8f6eeb | 974 | iwlagn_txq_inval_byte_cnt_tbl(trans, txq); |
a0eaad71 | 975 | |
39644e9a | 976 | iwlagn_txq_free_tfd(trans, txq, txq->q.read_ptr, DMA_TO_DEVICE); |
464021ff | 977 | freed++; |
a0eaad71 | 978 | } |
7c5ba4a8 JB |
979 | |
980 | iwl_queue_progress(trans_pcie, txq); | |
981 | ||
464021ff | 982 | return freed; |
a0eaad71 | 983 | } |