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1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
4e318262 | 3 | * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved. |
1053d35f RR |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
1053d35f RR |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
fd4abac5 | 29 | #include <linux/etherdevice.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
253a634c | 31 | #include <linux/sched.h> |
253a634c | 32 | |
522376d2 EG |
33 | #include "iwl-debug.h" |
34 | #include "iwl-csr.h" | |
35 | #include "iwl-prph.h" | |
1053d35f | 36 | #include "iwl-io.h" |
522376d2 | 37 | #include "iwl-agn-hw.h" |
ed277c93 | 38 | #include "iwl-op-mode.h" |
c17d0681 | 39 | #include "iwl-trans-pcie-int.h" |
1053d35f | 40 | |
522376d2 EG |
41 | #define IWL_TX_CRC_SIZE 4 |
42 | #define IWL_TX_DELIMITER_SIZE 4 | |
43 | ||
48d42c42 EG |
44 | /** |
45 | * iwl_trans_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array | |
46 | */ | |
6d8f6eeb | 47 | void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans, |
48d42c42 EG |
48 | struct iwl_tx_queue *txq, |
49 | u16 byte_cnt) | |
50 | { | |
105183b1 | 51 | struct iwlagn_scd_bc_tbl *scd_bc_tbl; |
105183b1 EG |
52 | struct iwl_trans_pcie *trans_pcie = |
53 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
48d42c42 EG |
54 | int write_ptr = txq->q.write_ptr; |
55 | int txq_id = txq->q.id; | |
56 | u8 sec_ctl = 0; | |
57 | u8 sta_id = 0; | |
58 | u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; | |
59 | __le16 bc_ent; | |
132f98c2 EG |
60 | struct iwl_tx_cmd *tx_cmd = |
61 | (struct iwl_tx_cmd *) txq->cmd[txq->q.write_ptr]->payload; | |
48d42c42 | 62 | |
105183b1 EG |
63 | scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; |
64 | ||
48d42c42 EG |
65 | WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX); |
66 | ||
132f98c2 EG |
67 | sta_id = tx_cmd->sta_id; |
68 | sec_ctl = tx_cmd->sec_ctl; | |
48d42c42 EG |
69 | |
70 | switch (sec_ctl & TX_CMD_SEC_MSK) { | |
71 | case TX_CMD_SEC_CCM: | |
72 | len += CCMP_MIC_LEN; | |
73 | break; | |
74 | case TX_CMD_SEC_TKIP: | |
75 | len += TKIP_ICV_LEN; | |
76 | break; | |
77 | case TX_CMD_SEC_WEP: | |
78 | len += WEP_IV_LEN + WEP_ICV_LEN; | |
79 | break; | |
80 | } | |
81 | ||
82 | bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12)); | |
83 | ||
84 | scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; | |
85 | ||
86 | if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
87 | scd_bc_tbl[txq_id]. | |
88 | tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; | |
89 | } | |
90 | ||
fd4abac5 TW |
91 | /** |
92 | * iwl_txq_update_write_ptr - Send new write index to hardware | |
93 | */ | |
fd656935 | 94 | void iwl_txq_update_write_ptr(struct iwl_trans *trans, struct iwl_tx_queue *txq) |
fd4abac5 TW |
95 | { |
96 | u32 reg = 0; | |
fd4abac5 TW |
97 | int txq_id = txq->q.id; |
98 | ||
99 | if (txq->need_update == 0) | |
7bfedc59 | 100 | return; |
fd4abac5 | 101 | |
fd656935 | 102 | if (hw_params(trans).shadow_reg_enable) { |
f81c1f48 | 103 | /* shadow register enabled */ |
1042db2a | 104 | iwl_write32(trans, HBUS_TARG_WRPTR, |
f81c1f48 WYG |
105 | txq->q.write_ptr | (txq_id << 8)); |
106 | } else { | |
107 | /* if we're trying to save power */ | |
fd656935 | 108 | if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) { |
f81c1f48 WYG |
109 | /* wake up nic if it's powered down ... |
110 | * uCode will wake up, and interrupt us again, so next | |
111 | * time we'll skip this part. */ | |
1042db2a | 112 | reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); |
fd4abac5 | 113 | |
f81c1f48 | 114 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { |
fd656935 | 115 | IWL_DEBUG_INFO(trans, |
f81c1f48 WYG |
116 | "Tx queue %d requesting wakeup," |
117 | " GP1 = 0x%x\n", txq_id, reg); | |
1042db2a | 118 | iwl_set_bit(trans, CSR_GP_CNTRL, |
f81c1f48 WYG |
119 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
120 | return; | |
121 | } | |
fd4abac5 | 122 | |
1042db2a | 123 | iwl_write_direct32(trans, HBUS_TARG_WRPTR, |
fd4abac5 | 124 | txq->q.write_ptr | (txq_id << 8)); |
fd4abac5 | 125 | |
f81c1f48 WYG |
126 | /* |
127 | * else not in power-save mode, | |
128 | * uCode will never sleep when we're | |
129 | * trying to tx (during RFKILL, we're not trying to tx). | |
130 | */ | |
131 | } else | |
1042db2a | 132 | iwl_write32(trans, HBUS_TARG_WRPTR, |
f81c1f48 WYG |
133 | txq->q.write_ptr | (txq_id << 8)); |
134 | } | |
fd4abac5 | 135 | txq->need_update = 0; |
fd4abac5 | 136 | } |
fd4abac5 | 137 | |
214d14d4 JB |
138 | static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
139 | { | |
140 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
141 | ||
142 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
143 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
144 | addr |= | |
145 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
146 | ||
147 | return addr; | |
148 | } | |
149 | ||
150 | static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) | |
151 | { | |
152 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
153 | ||
154 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
155 | } | |
156 | ||
157 | static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, | |
158 | dma_addr_t addr, u16 len) | |
159 | { | |
160 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
161 | u16 hi_n_len = len << 4; | |
162 | ||
163 | put_unaligned_le32(addr, &tb->lo); | |
164 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
165 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
166 | ||
167 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
168 | ||
169 | tfd->num_tbs = idx + 1; | |
170 | } | |
171 | ||
172 | static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd) | |
173 | { | |
174 | return tfd->num_tbs & 0x1f; | |
175 | } | |
176 | ||
6d8f6eeb | 177 | static void iwlagn_unmap_tfd(struct iwl_trans *trans, struct iwl_cmd_meta *meta, |
253a634c | 178 | struct iwl_tfd *tfd, enum dma_data_direction dma_dir) |
214d14d4 | 179 | { |
214d14d4 JB |
180 | int i; |
181 | int num_tbs; | |
182 | ||
214d14d4 JB |
183 | /* Sanity check on number of chunks */ |
184 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
185 | ||
186 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
6d8f6eeb | 187 | IWL_ERR(trans, "Too many chunks: %i\n", num_tbs); |
214d14d4 JB |
188 | /* @todo issue fatal error, it is quite serious situation */ |
189 | return; | |
190 | } | |
191 | ||
192 | /* Unmap tx_cmd */ | |
193 | if (num_tbs) | |
1042db2a | 194 | dma_unmap_single(trans->dev, |
4ce7cc2b JB |
195 | dma_unmap_addr(meta, mapping), |
196 | dma_unmap_len(meta, len), | |
795414db | 197 | DMA_BIDIRECTIONAL); |
214d14d4 JB |
198 | |
199 | /* Unmap chunks, if any. */ | |
200 | for (i = 1; i < num_tbs; i++) | |
1042db2a | 201 | dma_unmap_single(trans->dev, iwl_tfd_tb_get_addr(tfd, i), |
e815407d | 202 | iwl_tfd_tb_get_len(tfd, i), dma_dir); |
4ce7cc2b JB |
203 | } |
204 | ||
205 | /** | |
206 | * iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
6d8f6eeb | 207 | * @trans - transport private data |
4ce7cc2b | 208 | * @txq - tx queue |
1359ca4f | 209 | * @index - the index of the TFD to be freed |
39644e9a | 210 | *@dma_dir - the direction of the DMA mapping |
4ce7cc2b JB |
211 | * |
212 | * Does NOT advance any TFD circular buffer read/write indexes | |
213 | * Does NOT free the TFD itself (which is within circular buffer) | |
214 | */ | |
6d8f6eeb | 215 | void iwlagn_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq, |
39644e9a | 216 | int index, enum dma_data_direction dma_dir) |
4ce7cc2b JB |
217 | { |
218 | struct iwl_tfd *tfd_tmp = txq->tfds; | |
4ce7cc2b | 219 | |
39644e9a | 220 | iwlagn_unmap_tfd(trans, &txq->meta[index], &tfd_tmp[index], dma_dir); |
214d14d4 JB |
221 | |
222 | /* free SKB */ | |
2c452297 | 223 | if (txq->skbs) { |
214d14d4 JB |
224 | struct sk_buff *skb; |
225 | ||
2c452297 | 226 | skb = txq->skbs[index]; |
214d14d4 | 227 | |
909e9b23 EG |
228 | /* Can be called from irqs-disabled context |
229 | * If skb is not NULL, it means that the whole queue is being | |
230 | * freed and that the queue is not empty - free the skb | |
231 | */ | |
214d14d4 | 232 | if (skb) { |
ed277c93 | 233 | iwl_op_mode_free_skb(trans->op_mode, skb); |
2c452297 | 234 | txq->skbs[index] = NULL; |
214d14d4 JB |
235 | } |
236 | } | |
237 | } | |
238 | ||
6d8f6eeb | 239 | int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans, |
214d14d4 JB |
240 | struct iwl_tx_queue *txq, |
241 | dma_addr_t addr, u16 len, | |
4c42db0f | 242 | u8 reset) |
214d14d4 JB |
243 | { |
244 | struct iwl_queue *q; | |
245 | struct iwl_tfd *tfd, *tfd_tmp; | |
246 | u32 num_tbs; | |
247 | ||
248 | q = &txq->q; | |
4ce7cc2b | 249 | tfd_tmp = txq->tfds; |
214d14d4 JB |
250 | tfd = &tfd_tmp[q->write_ptr]; |
251 | ||
252 | if (reset) | |
253 | memset(tfd, 0, sizeof(*tfd)); | |
254 | ||
255 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
256 | ||
257 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
258 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
6d8f6eeb | 259 | IWL_ERR(trans, "Error can not send more than %d chunks\n", |
214d14d4 JB |
260 | IWL_NUM_OF_TBS); |
261 | return -EINVAL; | |
262 | } | |
263 | ||
264 | if (WARN_ON(addr & ~DMA_BIT_MASK(36))) | |
265 | return -EINVAL; | |
266 | ||
267 | if (unlikely(addr & ~IWL_TX_DMA_MASK)) | |
6d8f6eeb | 268 | IWL_ERR(trans, "Unaligned address = %llx\n", |
214d14d4 JB |
269 | (unsigned long long)addr); |
270 | ||
271 | iwl_tfd_set_tb(tfd, num_tbs, addr, len); | |
272 | ||
273 | return 0; | |
274 | } | |
275 | ||
fd4abac5 TW |
276 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
277 | * DMA services | |
278 | * | |
279 | * Theory of operation | |
280 | * | |
281 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
282 | * of buffer descriptors, each of which points to one or more data buffers for | |
283 | * the device to read from or fill. Driver and device exchange status of each | |
284 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
285 | * entries in each circular buffer, to protect against confusing empty and full | |
286 | * queue states. | |
287 | * | |
288 | * The device reads or writes the data in the queues via the device's several | |
289 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
290 | * | |
291 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
292 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
293 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
294 | * Tx queue resumed. | |
295 | * | |
fd4abac5 TW |
296 | ***************************************************/ |
297 | ||
298 | int iwl_queue_space(const struct iwl_queue *q) | |
299 | { | |
300 | int s = q->read_ptr - q->write_ptr; | |
301 | ||
302 | if (q->read_ptr > q->write_ptr) | |
303 | s -= q->n_bd; | |
304 | ||
305 | if (s <= 0) | |
306 | s += q->n_window; | |
307 | /* keep some reserve to not confuse empty and full situations */ | |
308 | s -= 2; | |
309 | if (s < 0) | |
310 | s = 0; | |
311 | return s; | |
312 | } | |
fd4abac5 | 313 | |
1053d35f RR |
314 | /** |
315 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes | |
316 | */ | |
6d8f6eeb | 317 | int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id) |
1053d35f RR |
318 | { |
319 | q->n_bd = count; | |
320 | q->n_window = slots_num; | |
321 | q->id = id; | |
322 | ||
323 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap | |
324 | * and iwl_queue_dec_wrap are broken. */ | |
3e41ace5 JB |
325 | if (WARN_ON(!is_power_of_2(count))) |
326 | return -EINVAL; | |
1053d35f RR |
327 | |
328 | /* slots_num must be power-of-two size, otherwise | |
329 | * get_cmd_index is broken. */ | |
3e41ace5 JB |
330 | if (WARN_ON(!is_power_of_2(slots_num))) |
331 | return -EINVAL; | |
1053d35f RR |
332 | |
333 | q->low_mark = q->n_window / 4; | |
334 | if (q->low_mark < 4) | |
335 | q->low_mark = 4; | |
336 | ||
337 | q->high_mark = q->n_window / 8; | |
338 | if (q->high_mark < 2) | |
339 | q->high_mark = 2; | |
340 | ||
341 | q->write_ptr = q->read_ptr = 0; | |
342 | ||
343 | return 0; | |
344 | } | |
345 | ||
6d8f6eeb | 346 | static void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_trans *trans, |
48d42c42 EG |
347 | struct iwl_tx_queue *txq) |
348 | { | |
105183b1 EG |
349 | struct iwl_trans_pcie *trans_pcie = |
350 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
6d8f6eeb | 351 | struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; |
48d42c42 EG |
352 | int txq_id = txq->q.id; |
353 | int read_ptr = txq->q.read_ptr; | |
354 | u8 sta_id = 0; | |
355 | __le16 bc_ent; | |
132f98c2 EG |
356 | struct iwl_tx_cmd *tx_cmd = |
357 | (struct iwl_tx_cmd *) txq->cmd[txq->q.read_ptr]->payload; | |
48d42c42 EG |
358 | |
359 | WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); | |
360 | ||
6d8f6eeb | 361 | if (txq_id != trans->shrd->cmd_queue) |
132f98c2 | 362 | sta_id = tx_cmd->sta_id; |
48d42c42 EG |
363 | |
364 | bc_ent = cpu_to_le16(1 | (sta_id << 12)); | |
365 | scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; | |
366 | ||
367 | if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
368 | scd_bc_tbl[txq_id]. | |
369 | tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; | |
370 | } | |
371 | ||
6d8f6eeb | 372 | static int iwlagn_tx_queue_set_q2ratid(struct iwl_trans *trans, u16 ra_tid, |
48d42c42 EG |
373 | u16 txq_id) |
374 | { | |
375 | u32 tbl_dw_addr; | |
376 | u32 tbl_dw; | |
377 | u16 scd_q2ratid; | |
378 | ||
105183b1 EG |
379 | struct iwl_trans_pcie *trans_pcie = |
380 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
381 | ||
48d42c42 EG |
382 | scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; |
383 | ||
105183b1 | 384 | tbl_dw_addr = trans_pcie->scd_base_addr + |
48d42c42 EG |
385 | SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); |
386 | ||
1042db2a | 387 | tbl_dw = iwl_read_targ_mem(trans, tbl_dw_addr); |
48d42c42 EG |
388 | |
389 | if (txq_id & 0x1) | |
390 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); | |
391 | else | |
392 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); | |
393 | ||
1042db2a | 394 | iwl_write_targ_mem(trans, tbl_dw_addr, tbl_dw); |
48d42c42 EG |
395 | |
396 | return 0; | |
397 | } | |
398 | ||
6d8f6eeb | 399 | static void iwlagn_tx_queue_stop_scheduler(struct iwl_trans *trans, u16 txq_id) |
48d42c42 EG |
400 | { |
401 | /* Simply stop the queue, but don't change any configuration; | |
402 | * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ | |
1042db2a | 403 | iwl_write_prph(trans, |
48d42c42 EG |
404 | SCD_QUEUE_STATUS_BITS(txq_id), |
405 | (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)| | |
406 | (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); | |
407 | } | |
408 | ||
6d8f6eeb | 409 | void iwl_trans_set_wr_ptrs(struct iwl_trans *trans, |
48d42c42 EG |
410 | int txq_id, u32 index) |
411 | { | |
631b84c5 | 412 | IWL_DEBUG_TX_QUEUES(trans, "Q %d WrPtr: %d", txq_id, index & 0xff); |
1042db2a | 413 | iwl_write_direct32(trans, HBUS_TARG_WRPTR, |
48d42c42 | 414 | (index & 0xff) | (txq_id << 8)); |
1042db2a | 415 | iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), index); |
48d42c42 EG |
416 | } |
417 | ||
c91bd124 | 418 | void iwl_trans_tx_queue_set_status(struct iwl_trans *trans, |
48d42c42 EG |
419 | struct iwl_tx_queue *txq, |
420 | int tx_fifo_id, int scd_retry) | |
421 | { | |
8ad71bef | 422 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
48d42c42 | 423 | int txq_id = txq->q.id; |
c91bd124 | 424 | int active = |
8ad71bef | 425 | test_bit(txq_id, &trans_pcie->txq_ctx_active_msk) ? 1 : 0; |
48d42c42 | 426 | |
1042db2a | 427 | iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id), |
48d42c42 EG |
428 | (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) | |
429 | (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) | | |
430 | (1 << SCD_QUEUE_STTS_REG_POS_WSL) | | |
431 | SCD_QUEUE_STTS_REG_MSK); | |
432 | ||
433 | txq->sched_retry = scd_retry; | |
434 | ||
1dcedc8e EG |
435 | if (active) |
436 | IWL_DEBUG_TX_QUEUES(trans, "Activate %s Queue %d on FIFO %d\n", | |
437 | scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id); | |
438 | else | |
439 | IWL_DEBUG_TX_QUEUES(trans, "Deactivate %s Queue %d\n", | |
440 | scd_retry ? "BA" : "AC/CMD", txq_id); | |
48d42c42 EG |
441 | } |
442 | ||
e13c0c59 EG |
443 | static inline int get_fifo_from_tid(struct iwl_trans_pcie *trans_pcie, |
444 | u8 ctx, u16 tid) | |
ba562f71 | 445 | { |
e13c0c59 | 446 | const u8 *ac_to_fifo = trans_pcie->ac_to_fifo[ctx]; |
ba562f71 | 447 | if (likely(tid < ARRAY_SIZE(tid_to_ac))) |
e13c0c59 | 448 | return ac_to_fifo[tid_to_ac[tid]]; |
ba562f71 EG |
449 | |
450 | /* no support for TIDs 8-15 yet */ | |
451 | return -EINVAL; | |
452 | } | |
453 | ||
76bc10fc EG |
454 | static inline bool is_agg_txqid_valid(struct iwl_trans *trans, int txq_id) |
455 | { | |
456 | if (txq_id < IWLAGN_FIRST_AMPDU_QUEUE) | |
457 | return false; | |
458 | return txq_id < (IWLAGN_FIRST_AMPDU_QUEUE + | |
459 | hw_params(trans).num_ampdu_queues); | |
460 | } | |
461 | ||
c91bd124 EG |
462 | void iwl_trans_pcie_tx_agg_setup(struct iwl_trans *trans, |
463 | enum iwl_rxon_context_id ctx, int sta_id, | |
822e8b2a | 464 | int tid, int frame_limit, u16 ssn) |
48d42c42 | 465 | { |
822e8b2a | 466 | int tx_fifo, txq_id; |
48d42c42 EG |
467 | u16 ra_tid; |
468 | unsigned long flags; | |
48d42c42 | 469 | |
105183b1 EG |
470 | struct iwl_trans_pcie *trans_pcie = |
471 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
472 | ||
48d42c42 EG |
473 | if (WARN_ON(sta_id == IWL_INVALID_STATION)) |
474 | return; | |
5f85a789 | 475 | if (WARN_ON(tid >= IWL_MAX_TID_COUNT)) |
48d42c42 EG |
476 | return; |
477 | ||
e13c0c59 | 478 | tx_fifo = get_fifo_from_tid(trans_pcie, ctx, tid); |
ba562f71 EG |
479 | if (WARN_ON(tx_fifo < 0)) { |
480 | IWL_ERR(trans, "txq_agg_setup, bad fifo: %d\n", tx_fifo); | |
481 | return; | |
482 | } | |
483 | ||
76bc10fc EG |
484 | txq_id = trans_pcie->agg_txq[sta_id][tid]; |
485 | if (WARN_ON_ONCE(is_agg_txqid_valid(trans, txq_id) == false)) { | |
486 | IWL_ERR(trans, | |
487 | "queue number out of range: %d, must be %d to %d\n", | |
488 | txq_id, IWLAGN_FIRST_AMPDU_QUEUE, | |
489 | IWLAGN_FIRST_AMPDU_QUEUE + | |
490 | hw_params(trans).num_ampdu_queues - 1); | |
491 | return; | |
492 | } | |
48d42c42 EG |
493 | |
494 | ra_tid = BUILD_RAxTID(sta_id, tid); | |
495 | ||
7b11488f | 496 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
48d42c42 EG |
497 | |
498 | /* Stop this Tx queue before configuring it */ | |
6d8f6eeb | 499 | iwlagn_tx_queue_stop_scheduler(trans, txq_id); |
48d42c42 EG |
500 | |
501 | /* Map receiver-address / traffic-ID to this queue */ | |
6d8f6eeb | 502 | iwlagn_tx_queue_set_q2ratid(trans, ra_tid, txq_id); |
48d42c42 EG |
503 | |
504 | /* Set this queue as a chain-building queue */ | |
1042db2a | 505 | iwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, (1<<txq_id)); |
48d42c42 EG |
506 | |
507 | /* enable aggregations for the queue */ | |
1042db2a | 508 | iwl_set_bits_prph(trans, SCD_AGGR_SEL, (1<<txq_id)); |
48d42c42 EG |
509 | |
510 | /* Place first TFD at index corresponding to start sequence number. | |
511 | * Assumes that ssn_idx is valid (!= 0xFFF) */ | |
822e8b2a EG |
512 | trans_pcie->txq[txq_id].q.read_ptr = (ssn & 0xff); |
513 | trans_pcie->txq[txq_id].q.write_ptr = (ssn & 0xff); | |
514 | iwl_trans_set_wr_ptrs(trans, txq_id, ssn); | |
48d42c42 EG |
515 | |
516 | /* Set up Tx window size and frame limit for this queue */ | |
1042db2a | 517 | iwl_write_targ_mem(trans, trans_pcie->scd_base_addr + |
48d42c42 EG |
518 | SCD_CONTEXT_QUEUE_OFFSET(txq_id) + |
519 | sizeof(u32), | |
520 | ((frame_limit << | |
521 | SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
522 | SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
523 | ((frame_limit << | |
524 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
525 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
526 | ||
1042db2a | 527 | iwl_set_bits_prph(trans, SCD_INTERRUPT_MASK, (1 << txq_id)); |
48d42c42 EG |
528 | |
529 | /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ | |
8ad71bef | 530 | iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id], |
c91bd124 | 531 | tx_fifo, 1); |
48d42c42 | 532 | |
8ad71bef EG |
533 | trans_pcie->txq[txq_id].sta_id = sta_id; |
534 | trans_pcie->txq[txq_id].tid = tid; | |
a0eaad71 | 535 | |
7b11488f | 536 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
48d42c42 EG |
537 | } |
538 | ||
288712a6 EG |
539 | /* |
540 | * Find first available (lowest unused) Tx Queue, mark it "active". | |
541 | * Called only when finding queue for aggregation. | |
542 | * Should never return anything < 7, because they should already | |
543 | * be in use as EDCA AC (0-3), Command (4), reserved (5, 6) | |
544 | */ | |
545 | static int iwlagn_txq_ctx_activate_free(struct iwl_trans *trans) | |
546 | { | |
8ad71bef | 547 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
288712a6 EG |
548 | int txq_id; |
549 | ||
550 | for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) | |
551 | if (!test_and_set_bit(txq_id, | |
8ad71bef | 552 | &trans_pcie->txq_ctx_active_msk)) |
288712a6 EG |
553 | return txq_id; |
554 | return -1; | |
555 | } | |
556 | ||
557 | int iwl_trans_pcie_tx_agg_alloc(struct iwl_trans *trans, | |
3c69b595 | 558 | int sta_id, int tid) |
288712a6 | 559 | { |
8ad71bef | 560 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
143bb15d | 561 | int txq_id; |
288712a6 EG |
562 | |
563 | txq_id = iwlagn_txq_ctx_activate_free(trans); | |
564 | if (txq_id == -1) { | |
565 | IWL_ERR(trans, "No free aggregation queue available\n"); | |
566 | return -ENXIO; | |
567 | } | |
568 | ||
76bc10fc | 569 | trans_pcie->agg_txq[sta_id][tid] = txq_id; |
8ad71bef | 570 | iwl_set_swq_id(&trans_pcie->txq[txq_id], get_ac_from_tid(tid), txq_id); |
288712a6 | 571 | |
288712a6 EG |
572 | return 0; |
573 | } | |
7f01d567 | 574 | |
bc237730 | 575 | int iwl_trans_pcie_tx_agg_disable(struct iwl_trans *trans, int sta_id, int tid) |
48d42c42 | 576 | { |
8ad71bef | 577 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
76bc10fc | 578 | u8 txq_id = trans_pcie->agg_txq[sta_id][tid]; |
7f01d567 | 579 | |
76bc10fc | 580 | if (WARN_ON_ONCE(is_agg_txqid_valid(trans, txq_id) == false)) { |
7f01d567 | 581 | IWL_ERR(trans, |
48d42c42 EG |
582 | "queue number out of range: %d, must be %d to %d\n", |
583 | txq_id, IWLAGN_FIRST_AMPDU_QUEUE, | |
584 | IWLAGN_FIRST_AMPDU_QUEUE + | |
7f01d567 | 585 | hw_params(trans).num_ampdu_queues - 1); |
48d42c42 EG |
586 | return -EINVAL; |
587 | } | |
588 | ||
bc237730 | 589 | iwlagn_tx_queue_stop_scheduler(trans, txq_id); |
7f01d567 | 590 | |
1042db2a | 591 | iwl_clear_bits_prph(trans, SCD_AGGR_SEL, (1 << txq_id)); |
48d42c42 | 592 | |
76bc10fc | 593 | trans_pcie->agg_txq[sta_id][tid] = 0; |
bc237730 EG |
594 | trans_pcie->txq[txq_id].q.read_ptr = 0; |
595 | trans_pcie->txq[txq_id].q.write_ptr = 0; | |
596 | /* supposes that ssn_idx is valid (!= 0xFFF) */ | |
597 | iwl_trans_set_wr_ptrs(trans, txq_id, 0); | |
48d42c42 | 598 | |
1042db2a | 599 | iwl_clear_bits_prph(trans, SCD_INTERRUPT_MASK, (1 << txq_id)); |
bc237730 EG |
600 | iwl_txq_ctx_deactivate(trans_pcie, txq_id); |
601 | iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id], 0, 0); | |
48d42c42 EG |
602 | return 0; |
603 | } | |
604 | ||
fd4abac5 TW |
605 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ |
606 | ||
607 | /** | |
608 | * iwl_enqueue_hcmd - enqueue a uCode command | |
609 | * @priv: device private data point | |
610 | * @cmd: a point to the ucode command structure | |
611 | * | |
612 | * The function returns < 0 values to indicate the operation is | |
613 | * failed. On success, it turns the index (> 0) of command in the | |
614 | * command queue. | |
615 | */ | |
6d8f6eeb | 616 | static int iwl_enqueue_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
fd4abac5 | 617 | { |
8ad71bef EG |
618 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
619 | struct iwl_tx_queue *txq = &trans_pcie->txq[trans->shrd->cmd_queue]; | |
fd4abac5 | 620 | struct iwl_queue *q = &txq->q; |
c2acea8e JB |
621 | struct iwl_device_cmd *out_cmd; |
622 | struct iwl_cmd_meta *out_meta; | |
fd4abac5 | 623 | dma_addr_t phys_addr; |
fd4abac5 | 624 | unsigned long flags; |
f3674227 | 625 | u32 idx; |
4ce7cc2b | 626 | u16 copy_size, cmd_size; |
0975cc8f | 627 | bool is_ct_kill = false; |
4ce7cc2b JB |
628 | bool had_nocopy = false; |
629 | int i; | |
630 | u8 *cmd_dest; | |
631 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
632 | const void *trace_bufs[IWL_MAX_CMD_TFDS + 1] = {}; | |
633 | int trace_lens[IWL_MAX_CMD_TFDS + 1] = {}; | |
634 | int trace_idx; | |
635 | #endif | |
fd4abac5 | 636 | |
6d8f6eeb EG |
637 | if (test_bit(STATUS_FW_ERROR, &trans->shrd->status)) { |
638 | IWL_WARN(trans, "fw recovery, no hcmd send\n"); | |
3083d03c WYG |
639 | return -EIO; |
640 | } | |
641 | ||
fd656935 | 642 | if ((trans->shrd->ucode_owner == IWL_OWNERSHIP_TM) && |
eedb6e35 | 643 | !(cmd->flags & CMD_ON_DEMAND)) { |
6d8f6eeb | 644 | IWL_DEBUG_HC(trans, "tm own the uCode, no regular hcmd send\n"); |
eedb6e35 WYG |
645 | return -EIO; |
646 | } | |
647 | ||
4ce7cc2b JB |
648 | copy_size = sizeof(out_cmd->hdr); |
649 | cmd_size = sizeof(out_cmd->hdr); | |
650 | ||
651 | /* need one for the header if the first is NOCOPY */ | |
652 | BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1); | |
653 | ||
654 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
655 | if (!cmd->len[i]) | |
656 | continue; | |
657 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { | |
658 | had_nocopy = true; | |
659 | } else { | |
660 | /* NOCOPY must not be followed by normal! */ | |
661 | if (WARN_ON(had_nocopy)) | |
662 | return -EINVAL; | |
663 | copy_size += cmd->len[i]; | |
664 | } | |
665 | cmd_size += cmd->len[i]; | |
666 | } | |
fd4abac5 | 667 | |
3e41ace5 JB |
668 | /* |
669 | * If any of the command structures end up being larger than | |
4ce7cc2b JB |
670 | * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically |
671 | * allocated into separate TFDs, then we will need to | |
672 | * increase the size of the buffers. | |
3e41ace5 | 673 | */ |
4ce7cc2b | 674 | if (WARN_ON(copy_size > TFD_MAX_PAYLOAD_SIZE)) |
3e41ace5 | 675 | return -EINVAL; |
fd4abac5 | 676 | |
6d8f6eeb EG |
677 | if (iwl_is_rfkill(trans->shrd) || iwl_is_ctkill(trans->shrd)) { |
678 | IWL_WARN(trans, "Not sending command - %s KILL\n", | |
679 | iwl_is_rfkill(trans->shrd) ? "RF" : "CT"); | |
fd4abac5 TW |
680 | return -EIO; |
681 | } | |
7b21f00e | 682 | |
72012474 | 683 | spin_lock_irqsave(&trans->hcmd_lock, flags); |
3598e177 | 684 | |
c2acea8e | 685 | if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { |
72012474 | 686 | spin_unlock_irqrestore(&trans->hcmd_lock, flags); |
3598e177 | 687 | |
6d8f6eeb | 688 | IWL_ERR(trans, "No space in command queue\n"); |
fd656935 | 689 | is_ct_kill = iwl_check_for_ct_kill(priv(trans)); |
0975cc8f | 690 | if (!is_ct_kill) { |
6d8f6eeb | 691 | IWL_ERR(trans, "Restarting adapter queue is full\n"); |
bcb9321c | 692 | iwl_op_mode_nic_error(trans->op_mode); |
7812b167 | 693 | } |
fd4abac5 TW |
694 | return -ENOSPC; |
695 | } | |
696 | ||
4ce7cc2b | 697 | idx = get_cmd_index(q, q->write_ptr); |
da99c4b6 | 698 | out_cmd = txq->cmd[idx]; |
c2acea8e JB |
699 | out_meta = &txq->meta[idx]; |
700 | ||
8ce73f3a | 701 | memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ |
c2acea8e JB |
702 | if (cmd->flags & CMD_WANT_SKB) |
703 | out_meta->source = cmd; | |
fd4abac5 | 704 | |
4ce7cc2b | 705 | /* set up the header */ |
fd4abac5 | 706 | |
4ce7cc2b | 707 | out_cmd->hdr.cmd = cmd->id; |
fd4abac5 | 708 | out_cmd->hdr.flags = 0; |
cefeaa5f | 709 | out_cmd->hdr.sequence = |
6d8f6eeb | 710 | cpu_to_le16(QUEUE_TO_SEQ(trans->shrd->cmd_queue) | |
cefeaa5f | 711 | INDEX_TO_SEQ(q->write_ptr)); |
4ce7cc2b JB |
712 | |
713 | /* and copy the data that needs to be copied */ | |
714 | ||
132f98c2 | 715 | cmd_dest = out_cmd->payload; |
4ce7cc2b JB |
716 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { |
717 | if (!cmd->len[i]) | |
718 | continue; | |
719 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) | |
720 | break; | |
721 | memcpy(cmd_dest, cmd->data[i], cmd->len[i]); | |
722 | cmd_dest += cmd->len[i]; | |
ded2ae7c | 723 | } |
4ce7cc2b | 724 | |
6d8f6eeb | 725 | IWL_DEBUG_HC(trans, "Sending command %s (#%x), seq: 0x%04X, " |
4ce7cc2b JB |
726 | "%d bytes at %d[%d]:%d\n", |
727 | get_cmd_string(out_cmd->hdr.cmd), | |
728 | out_cmd->hdr.cmd, | |
729 | le16_to_cpu(out_cmd->hdr.sequence), cmd_size, | |
6d8f6eeb | 730 | q->write_ptr, idx, trans->shrd->cmd_queue); |
4ce7cc2b | 731 | |
1042db2a | 732 | phys_addr = dma_map_single(trans->dev, &out_cmd->hdr, copy_size, |
795414db | 733 | DMA_BIDIRECTIONAL); |
1042db2a | 734 | if (unlikely(dma_mapping_error(trans->dev, phys_addr))) { |
2c46f72e JB |
735 | idx = -ENOMEM; |
736 | goto out; | |
737 | } | |
738 | ||
2e724443 | 739 | dma_unmap_addr_set(out_meta, mapping, phys_addr); |
4ce7cc2b JB |
740 | dma_unmap_len_set(out_meta, len, copy_size); |
741 | ||
6d8f6eeb EG |
742 | iwlagn_txq_attach_buf_to_tfd(trans, txq, |
743 | phys_addr, copy_size, 1); | |
4ce7cc2b JB |
744 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING |
745 | trace_bufs[0] = &out_cmd->hdr; | |
746 | trace_lens[0] = copy_size; | |
747 | trace_idx = 1; | |
748 | #endif | |
749 | ||
750 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
751 | if (!cmd->len[i]) | |
752 | continue; | |
753 | if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY)) | |
754 | continue; | |
1042db2a | 755 | phys_addr = dma_map_single(trans->dev, |
6d8f6eeb | 756 | (void *)cmd->data[i], |
3be3fdb5 | 757 | cmd->len[i], DMA_BIDIRECTIONAL); |
1042db2a | 758 | if (dma_mapping_error(trans->dev, phys_addr)) { |
6d8f6eeb | 759 | iwlagn_unmap_tfd(trans, out_meta, |
e815407d | 760 | &txq->tfds[q->write_ptr], |
3be3fdb5 | 761 | DMA_BIDIRECTIONAL); |
4ce7cc2b JB |
762 | idx = -ENOMEM; |
763 | goto out; | |
764 | } | |
765 | ||
6d8f6eeb | 766 | iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr, |
4ce7cc2b JB |
767 | cmd->len[i], 0); |
768 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
769 | trace_bufs[trace_idx] = cmd->data[i]; | |
770 | trace_lens[trace_idx] = cmd->len[i]; | |
771 | trace_idx++; | |
772 | #endif | |
773 | } | |
df833b1d | 774 | |
afaf6b57 | 775 | out_meta->flags = cmd->flags; |
2c46f72e JB |
776 | |
777 | txq->need_update = 1; | |
778 | ||
4ce7cc2b JB |
779 | /* check that tracing gets all possible blocks */ |
780 | BUILD_BUG_ON(IWL_MAX_CMD_TFDS + 1 != 3); | |
781 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
fd656935 | 782 | trace_iwlwifi_dev_hcmd(priv(trans), cmd->flags, |
4ce7cc2b JB |
783 | trace_bufs[0], trace_lens[0], |
784 | trace_bufs[1], trace_lens[1], | |
785 | trace_bufs[2], trace_lens[2]); | |
786 | #endif | |
df833b1d | 787 | |
fd4abac5 TW |
788 | /* Increment and update queue's write index */ |
789 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
fd656935 | 790 | iwl_txq_update_write_ptr(trans, txq); |
fd4abac5 | 791 | |
2c46f72e | 792 | out: |
72012474 | 793 | spin_unlock_irqrestore(&trans->hcmd_lock, flags); |
7bfedc59 | 794 | return idx; |
fd4abac5 TW |
795 | } |
796 | ||
17b88929 TW |
797 | /** |
798 | * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd | |
799 | * | |
800 | * When FW advances 'R' index, all entries between old and new 'R' index | |
801 | * need to be reclaimed. As result, some free space forms. If there is | |
802 | * enough free space (> low mark), wake the stack that feeds us. | |
803 | */ | |
3e10caeb EG |
804 | static void iwl_hcmd_queue_reclaim(struct iwl_trans *trans, int txq_id, |
805 | int idx) | |
17b88929 | 806 | { |
3e10caeb | 807 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
8ad71bef | 808 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; |
17b88929 TW |
809 | struct iwl_queue *q = &txq->q; |
810 | int nfreed = 0; | |
811 | ||
499b1883 | 812 | if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) { |
3e10caeb | 813 | IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), " |
2e5d04da DH |
814 | "index %d is out of range [0-%d] %d %d.\n", __func__, |
815 | txq_id, idx, q->n_bd, q->write_ptr, q->read_ptr); | |
17b88929 TW |
816 | return; |
817 | } | |
818 | ||
499b1883 TW |
819 | for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; |
820 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
17b88929 | 821 | |
499b1883 | 822 | if (nfreed++ > 0) { |
3e10caeb | 823 | IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", idx, |
17b88929 | 824 | q->write_ptr, q->read_ptr); |
bcb9321c | 825 | iwl_op_mode_nic_error(trans->op_mode); |
17b88929 | 826 | } |
da99c4b6 | 827 | |
17b88929 TW |
828 | } |
829 | } | |
830 | ||
831 | /** | |
832 | * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them | |
833 | * @rxb: Rx buffer to reclaim | |
247c61d6 EG |
834 | * @handler_status: return value of the handler of the command |
835 | * (put in setup_rx_handlers) | |
17b88929 TW |
836 | * |
837 | * If an Rx buffer has an async callback associated with it the callback | |
838 | * will be executed. The attached skb (if present) will only be freed | |
839 | * if the callback returns 1 | |
840 | */ | |
247c61d6 EG |
841 | void iwl_tx_cmd_complete(struct iwl_trans *trans, struct iwl_rx_mem_buffer *rxb, |
842 | int handler_status) | |
17b88929 | 843 | { |
2f301227 | 844 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
17b88929 TW |
845 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
846 | int txq_id = SEQ_TO_QUEUE(sequence); | |
847 | int index = SEQ_TO_INDEX(sequence); | |
17b88929 | 848 | int cmd_index; |
c2acea8e JB |
849 | struct iwl_device_cmd *cmd; |
850 | struct iwl_cmd_meta *meta; | |
8ad71bef EG |
851 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
852 | struct iwl_tx_queue *txq = &trans_pcie->txq[trans->shrd->cmd_queue]; | |
3598e177 | 853 | unsigned long flags; |
17b88929 TW |
854 | |
855 | /* If a Tx command is being handled and it isn't in the actual | |
856 | * command queue then there a command routing bug has been introduced | |
857 | * in the queue management code. */ | |
6d8f6eeb | 858 | if (WARN(txq_id != trans->shrd->cmd_queue, |
13bb9483 | 859 | "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", |
6d8f6eeb | 860 | txq_id, trans->shrd->cmd_queue, sequence, |
8ad71bef EG |
861 | trans_pcie->txq[trans->shrd->cmd_queue].q.read_ptr, |
862 | trans_pcie->txq[trans->shrd->cmd_queue].q.write_ptr)) { | |
3e10caeb | 863 | iwl_print_hex_error(trans, pkt, 32); |
55d6a3cd | 864 | return; |
01ef9323 | 865 | } |
17b88929 | 866 | |
4ce7cc2b | 867 | cmd_index = get_cmd_index(&txq->q, index); |
dd487449 ZY |
868 | cmd = txq->cmd[cmd_index]; |
869 | meta = &txq->meta[cmd_index]; | |
17b88929 | 870 | |
282cdb32 JB |
871 | txq->time_stamp = jiffies; |
872 | ||
6d8f6eeb EG |
873 | iwlagn_unmap_tfd(trans, meta, &txq->tfds[index], |
874 | DMA_BIDIRECTIONAL); | |
c33de625 | 875 | |
17b88929 | 876 | /* Input error checking is done when commands are added to queue. */ |
c2acea8e | 877 | if (meta->flags & CMD_WANT_SKB) { |
2f301227 | 878 | meta->source->reply_page = (unsigned long)rxb_addr(rxb); |
247c61d6 | 879 | meta->source->handler_status = handler_status; |
2f301227 | 880 | rxb->page = NULL; |
247c61d6 | 881 | } |
2624e96c | 882 | |
72012474 | 883 | spin_lock_irqsave(&trans->hcmd_lock, flags); |
17b88929 | 884 | |
3e10caeb | 885 | iwl_hcmd_queue_reclaim(trans, txq_id, index); |
17b88929 | 886 | |
c2acea8e | 887 | if (!(meta->flags & CMD_ASYNC)) { |
05c89b91 WYG |
888 | if (!test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status)) { |
889 | IWL_WARN(trans, | |
890 | "HCMD_ACTIVE already clear for command %s\n", | |
891 | get_cmd_string(cmd->hdr.cmd)); | |
892 | } | |
6d8f6eeb EG |
893 | clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status); |
894 | IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", | |
d2dfe6df | 895 | get_cmd_string(cmd->hdr.cmd)); |
effd4d9a | 896 | wake_up(&trans->shrd->wait_command_queue); |
17b88929 | 897 | } |
3598e177 | 898 | |
dd487449 | 899 | meta->flags = 0; |
3598e177 | 900 | |
72012474 | 901 | spin_unlock_irqrestore(&trans->hcmd_lock, flags); |
17b88929 | 902 | } |
253a634c | 903 | |
253a634c EG |
904 | #define HOST_COMPLETE_TIMEOUT (2 * HZ) |
905 | ||
6d8f6eeb | 906 | static int iwl_send_cmd_async(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c EG |
907 | { |
908 | int ret; | |
909 | ||
910 | /* An asynchronous command can not expect an SKB to be set. */ | |
911 | if (WARN_ON(cmd->flags & CMD_WANT_SKB)) | |
912 | return -EINVAL; | |
913 | ||
253a634c | 914 | |
6d8f6eeb | 915 | if (test_bit(STATUS_EXIT_PENDING, &trans->shrd->status)) |
253a634c EG |
916 | return -EBUSY; |
917 | ||
6d8f6eeb | 918 | ret = iwl_enqueue_hcmd(trans, cmd); |
253a634c | 919 | if (ret < 0) { |
b36b110c TP |
920 | IWL_DEBUG_QUIET_RFKILL(trans, |
921 | "Error sending %s: enqueue_hcmd failed: %d\n", | |
253a634c EG |
922 | get_cmd_string(cmd->id), ret); |
923 | return ret; | |
924 | } | |
925 | return 0; | |
926 | } | |
927 | ||
6d8f6eeb | 928 | static int iwl_send_cmd_sync(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c | 929 | { |
8ad71bef | 930 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
253a634c EG |
931 | int cmd_idx; |
932 | int ret; | |
933 | ||
6d8f6eeb | 934 | lockdep_assert_held(&trans->shrd->mutex); |
253a634c | 935 | |
6d8f6eeb | 936 | IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", |
253a634c EG |
937 | get_cmd_string(cmd->id)); |
938 | ||
94b3c45c WYG |
939 | if (test_bit(STATUS_EXIT_PENDING, &trans->shrd->status)) |
940 | return -EBUSY; | |
941 | ||
942 | ||
943 | if (test_bit(STATUS_RF_KILL_HW, &trans->shrd->status)) { | |
944 | IWL_ERR(trans, "Command %s aborted: RF KILL Switch\n", | |
945 | get_cmd_string(cmd->id)); | |
946 | return -ECANCELED; | |
947 | } | |
948 | if (test_bit(STATUS_FW_ERROR, &trans->shrd->status)) { | |
949 | IWL_ERR(trans, "Command %s failed: FW Error\n", | |
950 | get_cmd_string(cmd->id)); | |
951 | return -EIO; | |
952 | } | |
6d8f6eeb EG |
953 | set_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status); |
954 | IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", | |
253a634c EG |
955 | get_cmd_string(cmd->id)); |
956 | ||
6d8f6eeb | 957 | cmd_idx = iwl_enqueue_hcmd(trans, cmd); |
253a634c EG |
958 | if (cmd_idx < 0) { |
959 | ret = cmd_idx; | |
6d8f6eeb | 960 | clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status); |
b36b110c TP |
961 | IWL_DEBUG_QUIET_RFKILL(trans, |
962 | "Error sending %s: enqueue_hcmd failed: %d\n", | |
253a634c EG |
963 | get_cmd_string(cmd->id), ret); |
964 | return ret; | |
965 | } | |
966 | ||
effd4d9a | 967 | ret = wait_event_timeout(trans->shrd->wait_command_queue, |
6d8f6eeb | 968 | !test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status), |
253a634c EG |
969 | HOST_COMPLETE_TIMEOUT); |
970 | if (!ret) { | |
6d8f6eeb | 971 | if (test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status)) { |
d10630af | 972 | struct iwl_tx_queue *txq = |
397ede37 | 973 | &trans_pcie->txq[trans->shrd->cmd_queue]; |
d10630af WYG |
974 | struct iwl_queue *q = &txq->q; |
975 | ||
b36b110c | 976 | IWL_DEBUG_QUIET_RFKILL(trans, |
253a634c EG |
977 | "Error sending %s: time out after %dms.\n", |
978 | get_cmd_string(cmd->id), | |
979 | jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); | |
980 | ||
b36b110c | 981 | IWL_DEBUG_QUIET_RFKILL(trans, |
d10630af WYG |
982 | "Current CMD queue read_ptr %d write_ptr %d\n", |
983 | q->read_ptr, q->write_ptr); | |
984 | ||
6d8f6eeb EG |
985 | clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status); |
986 | IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command" | |
253a634c EG |
987 | "%s\n", get_cmd_string(cmd->id)); |
988 | ret = -ETIMEDOUT; | |
989 | goto cancel; | |
990 | } | |
991 | } | |
992 | ||
253a634c | 993 | if ((cmd->flags & CMD_WANT_SKB) && !cmd->reply_page) { |
6d8f6eeb | 994 | IWL_ERR(trans, "Error: Response NULL in '%s'\n", |
253a634c EG |
995 | get_cmd_string(cmd->id)); |
996 | ret = -EIO; | |
997 | goto cancel; | |
998 | } | |
999 | ||
1000 | return 0; | |
1001 | ||
1002 | cancel: | |
1003 | if (cmd->flags & CMD_WANT_SKB) { | |
1004 | /* | |
1005 | * Cancel the CMD_WANT_SKB flag for the cmd in the | |
1006 | * TX cmd queue. Otherwise in case the cmd comes | |
1007 | * in later, it will possibly set an invalid | |
1008 | * address (cmd->meta.source). | |
1009 | */ | |
8ad71bef | 1010 | trans_pcie->txq[trans->shrd->cmd_queue].meta[cmd_idx].flags &= |
253a634c EG |
1011 | ~CMD_WANT_SKB; |
1012 | } | |
9cac4943 | 1013 | |
253a634c | 1014 | if (cmd->reply_page) { |
6d8f6eeb | 1015 | iwl_free_pages(trans->shrd, cmd->reply_page); |
253a634c EG |
1016 | cmd->reply_page = 0; |
1017 | } | |
1018 | ||
1019 | return ret; | |
1020 | } | |
1021 | ||
6d8f6eeb | 1022 | int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c EG |
1023 | { |
1024 | if (cmd->flags & CMD_ASYNC) | |
6d8f6eeb | 1025 | return iwl_send_cmd_async(trans, cmd); |
253a634c | 1026 | |
6d8f6eeb | 1027 | return iwl_send_cmd_sync(trans, cmd); |
253a634c EG |
1028 | } |
1029 | ||
a0eaad71 | 1030 | /* Frees buffers until index _not_ inclusive */ |
464021ff EG |
1031 | int iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index, |
1032 | struct sk_buff_head *skbs) | |
a0eaad71 | 1033 | { |
8ad71bef EG |
1034 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1035 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; | |
a0eaad71 | 1036 | struct iwl_queue *q = &txq->q; |
a0eaad71 | 1037 | int last_to_free; |
464021ff | 1038 | int freed = 0; |
a0eaad71 | 1039 | |
39644e9a EG |
1040 | /* This function is not meant to release cmd queue*/ |
1041 | if (WARN_ON(txq_id == trans->shrd->cmd_queue)) | |
1042 | return 0; | |
1043 | ||
a0eaad71 EG |
1044 | /*Since we free until index _not_ inclusive, the one before index is |
1045 | * the last we will free. This one must be used */ | |
1046 | last_to_free = iwl_queue_dec_wrap(index, q->n_bd); | |
1047 | ||
1048 | if ((index >= q->n_bd) || | |
1049 | (iwl_queue_used(q, last_to_free) == 0)) { | |
1050 | IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), " | |
1051 | "last_to_free %d is out of range [0-%d] %d %d.\n", | |
1052 | __func__, txq_id, last_to_free, q->n_bd, | |
1053 | q->write_ptr, q->read_ptr); | |
464021ff | 1054 | return 0; |
a0eaad71 EG |
1055 | } |
1056 | ||
a0eaad71 | 1057 | if (WARN_ON(!skb_queue_empty(skbs))) |
464021ff | 1058 | return 0; |
a0eaad71 EG |
1059 | |
1060 | for (; | |
1061 | q->read_ptr != index; | |
1062 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
1063 | ||
2c452297 | 1064 | if (WARN_ON_ONCE(txq->skbs[txq->q.read_ptr] == NULL)) |
a0eaad71 EG |
1065 | continue; |
1066 | ||
2c452297 | 1067 | __skb_queue_tail(skbs, txq->skbs[txq->q.read_ptr]); |
a0eaad71 | 1068 | |
2c452297 | 1069 | txq->skbs[txq->q.read_ptr] = NULL; |
a0eaad71 | 1070 | |
6d8f6eeb | 1071 | iwlagn_txq_inval_byte_cnt_tbl(trans, txq); |
a0eaad71 | 1072 | |
39644e9a | 1073 | iwlagn_txq_free_tfd(trans, txq, txq->q.read_ptr, DMA_TO_DEVICE); |
464021ff | 1074 | freed++; |
a0eaad71 | 1075 | } |
464021ff | 1076 | return freed; |
a0eaad71 | 1077 | } |