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1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
fb4961db | 3 | * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved. |
1053d35f RR |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
1053d35f RR |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
fd4abac5 | 29 | #include <linux/etherdevice.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
253a634c | 31 | #include <linux/sched.h> |
253a634c | 32 | |
522376d2 EG |
33 | #include "iwl-debug.h" |
34 | #include "iwl-csr.h" | |
35 | #include "iwl-prph.h" | |
1053d35f | 36 | #include "iwl-io.h" |
522376d2 | 37 | #include "iwl-agn-hw.h" |
ed277c93 | 38 | #include "iwl-op-mode.h" |
c17d0681 | 39 | #include "iwl-trans-pcie-int.h" |
6238b008 JB |
40 | /* FIXME: need to abstract out TX command (once we know what it looks like) */ |
41 | #include "iwl-commands.h" | |
1053d35f | 42 | |
522376d2 EG |
43 | #define IWL_TX_CRC_SIZE 4 |
44 | #define IWL_TX_DELIMITER_SIZE 4 | |
45 | ||
48d42c42 EG |
46 | /** |
47 | * iwl_trans_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array | |
48 | */ | |
6d8f6eeb | 49 | void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans, |
48d42c42 EG |
50 | struct iwl_tx_queue *txq, |
51 | u16 byte_cnt) | |
52 | { | |
105183b1 | 53 | struct iwlagn_scd_bc_tbl *scd_bc_tbl; |
105183b1 EG |
54 | struct iwl_trans_pcie *trans_pcie = |
55 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
48d42c42 EG |
56 | int write_ptr = txq->q.write_ptr; |
57 | int txq_id = txq->q.id; | |
58 | u8 sec_ctl = 0; | |
59 | u8 sta_id = 0; | |
60 | u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; | |
61 | __le16 bc_ent; | |
132f98c2 | 62 | struct iwl_tx_cmd *tx_cmd = |
bf8440e6 | 63 | (void *) txq->entries[txq->q.write_ptr].cmd->payload; |
48d42c42 | 64 | |
105183b1 EG |
65 | scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; |
66 | ||
48d42c42 EG |
67 | WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX); |
68 | ||
132f98c2 EG |
69 | sta_id = tx_cmd->sta_id; |
70 | sec_ctl = tx_cmd->sec_ctl; | |
48d42c42 EG |
71 | |
72 | switch (sec_ctl & TX_CMD_SEC_MSK) { | |
73 | case TX_CMD_SEC_CCM: | |
74 | len += CCMP_MIC_LEN; | |
75 | break; | |
76 | case TX_CMD_SEC_TKIP: | |
77 | len += TKIP_ICV_LEN; | |
78 | break; | |
79 | case TX_CMD_SEC_WEP: | |
80 | len += WEP_IV_LEN + WEP_ICV_LEN; | |
81 | break; | |
82 | } | |
83 | ||
84 | bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12)); | |
85 | ||
86 | scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; | |
87 | ||
88 | if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
89 | scd_bc_tbl[txq_id]. | |
90 | tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; | |
91 | } | |
92 | ||
fd4abac5 TW |
93 | /** |
94 | * iwl_txq_update_write_ptr - Send new write index to hardware | |
95 | */ | |
fd656935 | 96 | void iwl_txq_update_write_ptr(struct iwl_trans *trans, struct iwl_tx_queue *txq) |
fd4abac5 TW |
97 | { |
98 | u32 reg = 0; | |
fd4abac5 TW |
99 | int txq_id = txq->q.id; |
100 | ||
101 | if (txq->need_update == 0) | |
7bfedc59 | 102 | return; |
fd4abac5 | 103 | |
035f7ff2 | 104 | if (trans->cfg->base_params->shadow_reg_enable) { |
f81c1f48 | 105 | /* shadow register enabled */ |
1042db2a | 106 | iwl_write32(trans, HBUS_TARG_WRPTR, |
f81c1f48 WYG |
107 | txq->q.write_ptr | (txq_id << 8)); |
108 | } else { | |
47107e84 DF |
109 | struct iwl_trans_pcie *trans_pcie = |
110 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
f81c1f48 | 111 | /* if we're trying to save power */ |
01d651d4 | 112 | if (test_bit(STATUS_TPOWER_PMI, &trans_pcie->status)) { |
f81c1f48 WYG |
113 | /* wake up nic if it's powered down ... |
114 | * uCode will wake up, and interrupt us again, so next | |
115 | * time we'll skip this part. */ | |
1042db2a | 116 | reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); |
fd4abac5 | 117 | |
f81c1f48 | 118 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { |
fd656935 | 119 | IWL_DEBUG_INFO(trans, |
f81c1f48 WYG |
120 | "Tx queue %d requesting wakeup," |
121 | " GP1 = 0x%x\n", txq_id, reg); | |
1042db2a | 122 | iwl_set_bit(trans, CSR_GP_CNTRL, |
f81c1f48 WYG |
123 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
124 | return; | |
125 | } | |
fd4abac5 | 126 | |
1042db2a | 127 | iwl_write_direct32(trans, HBUS_TARG_WRPTR, |
fd4abac5 | 128 | txq->q.write_ptr | (txq_id << 8)); |
fd4abac5 | 129 | |
f81c1f48 WYG |
130 | /* |
131 | * else not in power-save mode, | |
132 | * uCode will never sleep when we're | |
133 | * trying to tx (during RFKILL, we're not trying to tx). | |
134 | */ | |
135 | } else | |
1042db2a | 136 | iwl_write32(trans, HBUS_TARG_WRPTR, |
f81c1f48 WYG |
137 | txq->q.write_ptr | (txq_id << 8)); |
138 | } | |
fd4abac5 | 139 | txq->need_update = 0; |
fd4abac5 | 140 | } |
fd4abac5 | 141 | |
214d14d4 JB |
142 | static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
143 | { | |
144 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
145 | ||
146 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
147 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
148 | addr |= | |
149 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
150 | ||
151 | return addr; | |
152 | } | |
153 | ||
154 | static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) | |
155 | { | |
156 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
157 | ||
158 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
159 | } | |
160 | ||
161 | static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, | |
162 | dma_addr_t addr, u16 len) | |
163 | { | |
164 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
165 | u16 hi_n_len = len << 4; | |
166 | ||
167 | put_unaligned_le32(addr, &tb->lo); | |
168 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
169 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
170 | ||
171 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
172 | ||
173 | tfd->num_tbs = idx + 1; | |
174 | } | |
175 | ||
176 | static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd) | |
177 | { | |
178 | return tfd->num_tbs & 0x1f; | |
179 | } | |
180 | ||
eec373f0 EG |
181 | static void iwl_unmap_tfd(struct iwl_trans *trans, struct iwl_cmd_meta *meta, |
182 | struct iwl_tfd *tfd, enum dma_data_direction dma_dir) | |
214d14d4 | 183 | { |
214d14d4 JB |
184 | int i; |
185 | int num_tbs; | |
186 | ||
214d14d4 JB |
187 | /* Sanity check on number of chunks */ |
188 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
189 | ||
190 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
6d8f6eeb | 191 | IWL_ERR(trans, "Too many chunks: %i\n", num_tbs); |
214d14d4 JB |
192 | /* @todo issue fatal error, it is quite serious situation */ |
193 | return; | |
194 | } | |
195 | ||
196 | /* Unmap tx_cmd */ | |
197 | if (num_tbs) | |
1042db2a | 198 | dma_unmap_single(trans->dev, |
4ce7cc2b JB |
199 | dma_unmap_addr(meta, mapping), |
200 | dma_unmap_len(meta, len), | |
795414db | 201 | DMA_BIDIRECTIONAL); |
214d14d4 JB |
202 | |
203 | /* Unmap chunks, if any. */ | |
204 | for (i = 1; i < num_tbs; i++) | |
1042db2a | 205 | dma_unmap_single(trans->dev, iwl_tfd_tb_get_addr(tfd, i), |
e815407d | 206 | iwl_tfd_tb_get_len(tfd, i), dma_dir); |
ebed633c EG |
207 | |
208 | tfd->num_tbs = 0; | |
4ce7cc2b JB |
209 | } |
210 | ||
211 | /** | |
bc2529c3 | 212 | * iwl_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] |
6d8f6eeb | 213 | * @trans - transport private data |
4ce7cc2b | 214 | * @txq - tx queue |
ebed633c | 215 | * @dma_dir - the direction of the DMA mapping |
4ce7cc2b JB |
216 | * |
217 | * Does NOT advance any TFD circular buffer read/write indexes | |
218 | * Does NOT free the TFD itself (which is within circular buffer) | |
219 | */ | |
bc2529c3 EG |
220 | void iwl_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq, |
221 | enum dma_data_direction dma_dir) | |
4ce7cc2b JB |
222 | { |
223 | struct iwl_tfd *tfd_tmp = txq->tfds; | |
4ce7cc2b | 224 | |
ebed633c EG |
225 | /* rd_ptr is bounded by n_bd and idx is bounded by n_window */ |
226 | int rd_ptr = txq->q.read_ptr; | |
227 | int idx = get_cmd_index(&txq->q, rd_ptr); | |
228 | ||
015c15e1 JB |
229 | lockdep_assert_held(&txq->lock); |
230 | ||
ebed633c | 231 | /* We have only q->n_window txq->entries, but we use q->n_bd tfds */ |
eec373f0 EG |
232 | iwl_unmap_tfd(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr], |
233 | dma_dir); | |
214d14d4 JB |
234 | |
235 | /* free SKB */ | |
bf8440e6 | 236 | if (txq->entries) { |
214d14d4 JB |
237 | struct sk_buff *skb; |
238 | ||
ebed633c | 239 | skb = txq->entries[idx].skb; |
214d14d4 | 240 | |
909e9b23 EG |
241 | /* Can be called from irqs-disabled context |
242 | * If skb is not NULL, it means that the whole queue is being | |
243 | * freed and that the queue is not empty - free the skb | |
244 | */ | |
214d14d4 | 245 | if (skb) { |
ed277c93 | 246 | iwl_op_mode_free_skb(trans->op_mode, skb); |
ebed633c | 247 | txq->entries[idx].skb = NULL; |
214d14d4 JB |
248 | } |
249 | } | |
250 | } | |
251 | ||
6d8f6eeb | 252 | int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans, |
214d14d4 JB |
253 | struct iwl_tx_queue *txq, |
254 | dma_addr_t addr, u16 len, | |
4c42db0f | 255 | u8 reset) |
214d14d4 JB |
256 | { |
257 | struct iwl_queue *q; | |
258 | struct iwl_tfd *tfd, *tfd_tmp; | |
259 | u32 num_tbs; | |
260 | ||
261 | q = &txq->q; | |
4ce7cc2b | 262 | tfd_tmp = txq->tfds; |
214d14d4 JB |
263 | tfd = &tfd_tmp[q->write_ptr]; |
264 | ||
265 | if (reset) | |
266 | memset(tfd, 0, sizeof(*tfd)); | |
267 | ||
268 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
269 | ||
270 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
271 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
6d8f6eeb | 272 | IWL_ERR(trans, "Error can not send more than %d chunks\n", |
214d14d4 JB |
273 | IWL_NUM_OF_TBS); |
274 | return -EINVAL; | |
275 | } | |
276 | ||
277 | if (WARN_ON(addr & ~DMA_BIT_MASK(36))) | |
278 | return -EINVAL; | |
279 | ||
280 | if (unlikely(addr & ~IWL_TX_DMA_MASK)) | |
6d8f6eeb | 281 | IWL_ERR(trans, "Unaligned address = %llx\n", |
214d14d4 JB |
282 | (unsigned long long)addr); |
283 | ||
284 | iwl_tfd_set_tb(tfd, num_tbs, addr, len); | |
285 | ||
286 | return 0; | |
287 | } | |
288 | ||
fd4abac5 TW |
289 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
290 | * DMA services | |
291 | * | |
292 | * Theory of operation | |
293 | * | |
294 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
295 | * of buffer descriptors, each of which points to one or more data buffers for | |
296 | * the device to read from or fill. Driver and device exchange status of each | |
297 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
298 | * entries in each circular buffer, to protect against confusing empty and full | |
299 | * queue states. | |
300 | * | |
301 | * The device reads or writes the data in the queues via the device's several | |
302 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
303 | * | |
304 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
305 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
306 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
307 | * Tx queue resumed. | |
308 | * | |
fd4abac5 TW |
309 | ***************************************************/ |
310 | ||
311 | int iwl_queue_space(const struct iwl_queue *q) | |
312 | { | |
313 | int s = q->read_ptr - q->write_ptr; | |
314 | ||
315 | if (q->read_ptr > q->write_ptr) | |
316 | s -= q->n_bd; | |
317 | ||
318 | if (s <= 0) | |
319 | s += q->n_window; | |
320 | /* keep some reserve to not confuse empty and full situations */ | |
321 | s -= 2; | |
322 | if (s < 0) | |
323 | s = 0; | |
324 | return s; | |
325 | } | |
fd4abac5 | 326 | |
1053d35f RR |
327 | /** |
328 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes | |
329 | */ | |
6d8f6eeb | 330 | int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id) |
1053d35f RR |
331 | { |
332 | q->n_bd = count; | |
333 | q->n_window = slots_num; | |
334 | q->id = id; | |
335 | ||
336 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap | |
337 | * and iwl_queue_dec_wrap are broken. */ | |
3e41ace5 JB |
338 | if (WARN_ON(!is_power_of_2(count))) |
339 | return -EINVAL; | |
1053d35f RR |
340 | |
341 | /* slots_num must be power-of-two size, otherwise | |
342 | * get_cmd_index is broken. */ | |
3e41ace5 JB |
343 | if (WARN_ON(!is_power_of_2(slots_num))) |
344 | return -EINVAL; | |
1053d35f RR |
345 | |
346 | q->low_mark = q->n_window / 4; | |
347 | if (q->low_mark < 4) | |
348 | q->low_mark = 4; | |
349 | ||
350 | q->high_mark = q->n_window / 8; | |
351 | if (q->high_mark < 2) | |
352 | q->high_mark = 2; | |
353 | ||
354 | q->write_ptr = q->read_ptr = 0; | |
355 | ||
356 | return 0; | |
357 | } | |
358 | ||
6d8f6eeb | 359 | static void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_trans *trans, |
48d42c42 EG |
360 | struct iwl_tx_queue *txq) |
361 | { | |
105183b1 EG |
362 | struct iwl_trans_pcie *trans_pcie = |
363 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
6d8f6eeb | 364 | struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; |
48d42c42 EG |
365 | int txq_id = txq->q.id; |
366 | int read_ptr = txq->q.read_ptr; | |
367 | u8 sta_id = 0; | |
368 | __le16 bc_ent; | |
132f98c2 | 369 | struct iwl_tx_cmd *tx_cmd = |
bf8440e6 | 370 | (void *)txq->entries[txq->q.read_ptr].cmd->payload; |
48d42c42 EG |
371 | |
372 | WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); | |
373 | ||
c6f600fc | 374 | if (txq_id != trans_pcie->cmd_queue) |
132f98c2 | 375 | sta_id = tx_cmd->sta_id; |
48d42c42 EG |
376 | |
377 | bc_ent = cpu_to_le16(1 | (sta_id << 12)); | |
378 | scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; | |
379 | ||
380 | if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
381 | scd_bc_tbl[txq_id]. | |
382 | tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; | |
383 | } | |
384 | ||
6d8f6eeb | 385 | static int iwlagn_tx_queue_set_q2ratid(struct iwl_trans *trans, u16 ra_tid, |
48d42c42 EG |
386 | u16 txq_id) |
387 | { | |
388 | u32 tbl_dw_addr; | |
389 | u32 tbl_dw; | |
390 | u16 scd_q2ratid; | |
391 | ||
105183b1 EG |
392 | struct iwl_trans_pcie *trans_pcie = |
393 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
394 | ||
48d42c42 EG |
395 | scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; |
396 | ||
105183b1 | 397 | tbl_dw_addr = trans_pcie->scd_base_addr + |
48d42c42 EG |
398 | SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); |
399 | ||
1042db2a | 400 | tbl_dw = iwl_read_targ_mem(trans, tbl_dw_addr); |
48d42c42 EG |
401 | |
402 | if (txq_id & 0x1) | |
403 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); | |
404 | else | |
405 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); | |
406 | ||
1042db2a | 407 | iwl_write_targ_mem(trans, tbl_dw_addr, tbl_dw); |
48d42c42 EG |
408 | |
409 | return 0; | |
410 | } | |
411 | ||
6d8f6eeb | 412 | static void iwlagn_tx_queue_stop_scheduler(struct iwl_trans *trans, u16 txq_id) |
48d42c42 EG |
413 | { |
414 | /* Simply stop the queue, but don't change any configuration; | |
415 | * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ | |
1042db2a | 416 | iwl_write_prph(trans, |
48d42c42 EG |
417 | SCD_QUEUE_STATUS_BITS(txq_id), |
418 | (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)| | |
419 | (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); | |
420 | } | |
421 | ||
6d8f6eeb | 422 | void iwl_trans_set_wr_ptrs(struct iwl_trans *trans, |
48d42c42 EG |
423 | int txq_id, u32 index) |
424 | { | |
0ca24daf | 425 | IWL_DEBUG_TX_QUEUES(trans, "Q %d WrPtr: %d\n", txq_id, index & 0xff); |
1042db2a | 426 | iwl_write_direct32(trans, HBUS_TARG_WRPTR, |
48d42c42 | 427 | (index & 0xff) | (txq_id << 8)); |
1042db2a | 428 | iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), index); |
48d42c42 EG |
429 | } |
430 | ||
c91bd124 | 431 | void iwl_trans_tx_queue_set_status(struct iwl_trans *trans, |
9eae88fa JB |
432 | struct iwl_tx_queue *txq, |
433 | int tx_fifo_id, bool active) | |
48d42c42 EG |
434 | { |
435 | int txq_id = txq->q.id; | |
48d42c42 | 436 | |
1042db2a | 437 | iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id), |
48d42c42 EG |
438 | (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) | |
439 | (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) | | |
440 | (1 << SCD_QUEUE_STTS_REG_POS_WSL) | | |
441 | SCD_QUEUE_STTS_REG_MSK); | |
442 | ||
1dcedc8e | 443 | if (active) |
9eae88fa JB |
444 | IWL_DEBUG_TX_QUEUES(trans, "Activate queue %d on FIFO %d\n", |
445 | txq_id, tx_fifo_id); | |
1dcedc8e | 446 | else |
9eae88fa | 447 | IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id); |
76bc10fc EG |
448 | } |
449 | ||
9eae88fa JB |
450 | void iwl_trans_pcie_tx_agg_setup(struct iwl_trans *trans, int txq_id, int fifo, |
451 | int sta_id, int tid, int frame_limit, u16 ssn) | |
48d42c42 | 452 | { |
9eae88fa | 453 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
48d42c42 | 454 | unsigned long flags; |
9eae88fa | 455 | u16 ra_tid = BUILD_RAxTID(sta_id, tid); |
48d42c42 | 456 | |
9eae88fa JB |
457 | if (test_and_set_bit(txq_id, trans_pcie->queue_used)) |
458 | WARN_ONCE(1, "queue %d already used - expect issues", txq_id); | |
48d42c42 | 459 | |
7b11488f | 460 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
48d42c42 EG |
461 | |
462 | /* Stop this Tx queue before configuring it */ | |
6d8f6eeb | 463 | iwlagn_tx_queue_stop_scheduler(trans, txq_id); |
48d42c42 EG |
464 | |
465 | /* Map receiver-address / traffic-ID to this queue */ | |
6d8f6eeb | 466 | iwlagn_tx_queue_set_q2ratid(trans, ra_tid, txq_id); |
48d42c42 EG |
467 | |
468 | /* Set this queue as a chain-building queue */ | |
9eae88fa | 469 | iwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, BIT(txq_id)); |
48d42c42 EG |
470 | |
471 | /* enable aggregations for the queue */ | |
9eae88fa | 472 | iwl_set_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id)); |
48d42c42 EG |
473 | |
474 | /* Place first TFD at index corresponding to start sequence number. | |
475 | * Assumes that ssn_idx is valid (!= 0xFFF) */ | |
822e8b2a EG |
476 | trans_pcie->txq[txq_id].q.read_ptr = (ssn & 0xff); |
477 | trans_pcie->txq[txq_id].q.write_ptr = (ssn & 0xff); | |
478 | iwl_trans_set_wr_ptrs(trans, txq_id, ssn); | |
48d42c42 EG |
479 | |
480 | /* Set up Tx window size and frame limit for this queue */ | |
1042db2a | 481 | iwl_write_targ_mem(trans, trans_pcie->scd_base_addr + |
9eae88fa JB |
482 | SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), |
483 | ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
484 | SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
485 | ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
486 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
48d42c42 | 487 | |
1042db2a | 488 | iwl_set_bits_prph(trans, SCD_INTERRUPT_MASK, (1 << txq_id)); |
48d42c42 EG |
489 | |
490 | /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ | |
8ad71bef | 491 | iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id], |
9eae88fa | 492 | fifo, true); |
a0eaad71 | 493 | |
7b11488f | 494 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
48d42c42 EG |
495 | } |
496 | ||
9eae88fa | 497 | void iwl_trans_pcie_tx_agg_disable(struct iwl_trans *trans, int txq_id) |
288712a6 | 498 | { |
8ad71bef | 499 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
288712a6 | 500 | |
9eae88fa JB |
501 | if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) { |
502 | WARN_ONCE(1, "queue %d not used", txq_id); | |
503 | return; | |
48d42c42 EG |
504 | } |
505 | ||
bc237730 | 506 | iwlagn_tx_queue_stop_scheduler(trans, txq_id); |
7f01d567 | 507 | |
9eae88fa | 508 | iwl_clear_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id)); |
48d42c42 | 509 | |
bc237730 EG |
510 | trans_pcie->txq[txq_id].q.read_ptr = 0; |
511 | trans_pcie->txq[txq_id].q.write_ptr = 0; | |
bc237730 | 512 | iwl_trans_set_wr_ptrs(trans, txq_id, 0); |
48d42c42 | 513 | |
9eae88fa JB |
514 | iwl_clear_bits_prph(trans, SCD_INTERRUPT_MASK, BIT(txq_id)); |
515 | ||
516 | iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id], | |
517 | 0, false); | |
48d42c42 EG |
518 | } |
519 | ||
fd4abac5 TW |
520 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ |
521 | ||
522 | /** | |
523 | * iwl_enqueue_hcmd - enqueue a uCode command | |
524 | * @priv: device private data point | |
525 | * @cmd: a point to the ucode command structure | |
526 | * | |
527 | * The function returns < 0 values to indicate the operation is | |
528 | * failed. On success, it turns the index (> 0) of command in the | |
529 | * command queue. | |
530 | */ | |
6d8f6eeb | 531 | static int iwl_enqueue_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
fd4abac5 | 532 | { |
8ad71bef | 533 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
c6f600fc | 534 | struct iwl_tx_queue *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
fd4abac5 | 535 | struct iwl_queue *q = &txq->q; |
c2acea8e JB |
536 | struct iwl_device_cmd *out_cmd; |
537 | struct iwl_cmd_meta *out_meta; | |
fd4abac5 | 538 | dma_addr_t phys_addr; |
f3674227 | 539 | u32 idx; |
4ce7cc2b | 540 | u16 copy_size, cmd_size; |
4ce7cc2b JB |
541 | bool had_nocopy = false; |
542 | int i; | |
543 | u8 *cmd_dest; | |
544 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
545 | const void *trace_bufs[IWL_MAX_CMD_TFDS + 1] = {}; | |
546 | int trace_lens[IWL_MAX_CMD_TFDS + 1] = {}; | |
547 | int trace_idx; | |
548 | #endif | |
fd4abac5 | 549 | |
4ce7cc2b JB |
550 | copy_size = sizeof(out_cmd->hdr); |
551 | cmd_size = sizeof(out_cmd->hdr); | |
552 | ||
553 | /* need one for the header if the first is NOCOPY */ | |
554 | BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1); | |
555 | ||
556 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
557 | if (!cmd->len[i]) | |
558 | continue; | |
559 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { | |
560 | had_nocopy = true; | |
561 | } else { | |
562 | /* NOCOPY must not be followed by normal! */ | |
563 | if (WARN_ON(had_nocopy)) | |
564 | return -EINVAL; | |
565 | copy_size += cmd->len[i]; | |
566 | } | |
567 | cmd_size += cmd->len[i]; | |
568 | } | |
fd4abac5 | 569 | |
3e41ace5 JB |
570 | /* |
571 | * If any of the command structures end up being larger than | |
4ce7cc2b JB |
572 | * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically |
573 | * allocated into separate TFDs, then we will need to | |
574 | * increase the size of the buffers. | |
3e41ace5 | 575 | */ |
4ce7cc2b | 576 | if (WARN_ON(copy_size > TFD_MAX_PAYLOAD_SIZE)) |
3e41ace5 | 577 | return -EINVAL; |
fd4abac5 | 578 | |
015c15e1 | 579 | spin_lock_bh(&txq->lock); |
3598e177 | 580 | |
c2acea8e | 581 | if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { |
015c15e1 | 582 | spin_unlock_bh(&txq->lock); |
3598e177 | 583 | |
6d8f6eeb | 584 | IWL_ERR(trans, "No space in command queue\n"); |
0e781842 | 585 | iwl_op_mode_cmd_queue_full(trans->op_mode); |
fd4abac5 TW |
586 | return -ENOSPC; |
587 | } | |
588 | ||
4ce7cc2b | 589 | idx = get_cmd_index(q, q->write_ptr); |
bf8440e6 JB |
590 | out_cmd = txq->entries[idx].cmd; |
591 | out_meta = &txq->entries[idx].meta; | |
c2acea8e | 592 | |
8ce73f3a | 593 | memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ |
c2acea8e JB |
594 | if (cmd->flags & CMD_WANT_SKB) |
595 | out_meta->source = cmd; | |
fd4abac5 | 596 | |
4ce7cc2b | 597 | /* set up the header */ |
fd4abac5 | 598 | |
4ce7cc2b | 599 | out_cmd->hdr.cmd = cmd->id; |
fd4abac5 | 600 | out_cmd->hdr.flags = 0; |
cefeaa5f | 601 | out_cmd->hdr.sequence = |
c6f600fc | 602 | cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | |
cefeaa5f | 603 | INDEX_TO_SEQ(q->write_ptr)); |
4ce7cc2b JB |
604 | |
605 | /* and copy the data that needs to be copied */ | |
606 | ||
132f98c2 | 607 | cmd_dest = out_cmd->payload; |
4ce7cc2b JB |
608 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { |
609 | if (!cmd->len[i]) | |
610 | continue; | |
611 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) | |
612 | break; | |
613 | memcpy(cmd_dest, cmd->data[i], cmd->len[i]); | |
614 | cmd_dest += cmd->len[i]; | |
ded2ae7c | 615 | } |
4ce7cc2b | 616 | |
d9fb6465 JB |
617 | IWL_DEBUG_HC(trans, |
618 | "Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n", | |
619 | trans_pcie_get_cmd_string(trans_pcie, out_cmd->hdr.cmd), | |
620 | out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence), cmd_size, | |
621 | q->write_ptr, idx, trans_pcie->cmd_queue); | |
4ce7cc2b | 622 | |
1042db2a | 623 | phys_addr = dma_map_single(trans->dev, &out_cmd->hdr, copy_size, |
795414db | 624 | DMA_BIDIRECTIONAL); |
1042db2a | 625 | if (unlikely(dma_mapping_error(trans->dev, phys_addr))) { |
2c46f72e JB |
626 | idx = -ENOMEM; |
627 | goto out; | |
628 | } | |
629 | ||
2e724443 | 630 | dma_unmap_addr_set(out_meta, mapping, phys_addr); |
4ce7cc2b JB |
631 | dma_unmap_len_set(out_meta, len, copy_size); |
632 | ||
6d8f6eeb EG |
633 | iwlagn_txq_attach_buf_to_tfd(trans, txq, |
634 | phys_addr, copy_size, 1); | |
4ce7cc2b JB |
635 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING |
636 | trace_bufs[0] = &out_cmd->hdr; | |
637 | trace_lens[0] = copy_size; | |
638 | trace_idx = 1; | |
639 | #endif | |
640 | ||
641 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
642 | if (!cmd->len[i]) | |
643 | continue; | |
644 | if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY)) | |
645 | continue; | |
1042db2a | 646 | phys_addr = dma_map_single(trans->dev, |
6d8f6eeb | 647 | (void *)cmd->data[i], |
3be3fdb5 | 648 | cmd->len[i], DMA_BIDIRECTIONAL); |
1042db2a | 649 | if (dma_mapping_error(trans->dev, phys_addr)) { |
eec373f0 EG |
650 | iwl_unmap_tfd(trans, out_meta, |
651 | &txq->tfds[q->write_ptr], | |
652 | DMA_BIDIRECTIONAL); | |
4ce7cc2b JB |
653 | idx = -ENOMEM; |
654 | goto out; | |
655 | } | |
656 | ||
6d8f6eeb | 657 | iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr, |
4ce7cc2b JB |
658 | cmd->len[i], 0); |
659 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
660 | trace_bufs[trace_idx] = cmd->data[i]; | |
661 | trace_lens[trace_idx] = cmd->len[i]; | |
662 | trace_idx++; | |
663 | #endif | |
664 | } | |
df833b1d | 665 | |
afaf6b57 | 666 | out_meta->flags = cmd->flags; |
2c46f72e JB |
667 | |
668 | txq->need_update = 1; | |
669 | ||
4ce7cc2b JB |
670 | /* check that tracing gets all possible blocks */ |
671 | BUILD_BUG_ON(IWL_MAX_CMD_TFDS + 1 != 3); | |
672 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
6c1011e1 | 673 | trace_iwlwifi_dev_hcmd(trans->dev, cmd->flags, |
4ce7cc2b JB |
674 | trace_bufs[0], trace_lens[0], |
675 | trace_bufs[1], trace_lens[1], | |
676 | trace_bufs[2], trace_lens[2]); | |
677 | #endif | |
df833b1d | 678 | |
7c5ba4a8 JB |
679 | /* start timer if queue currently empty */ |
680 | if (q->read_ptr == q->write_ptr && trans_pcie->wd_timeout) | |
681 | mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout); | |
682 | ||
fd4abac5 TW |
683 | /* Increment and update queue's write index */ |
684 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
fd656935 | 685 | iwl_txq_update_write_ptr(trans, txq); |
fd4abac5 | 686 | |
2c46f72e | 687 | out: |
015c15e1 | 688 | spin_unlock_bh(&txq->lock); |
7bfedc59 | 689 | return idx; |
fd4abac5 TW |
690 | } |
691 | ||
7c5ba4a8 JB |
692 | static inline void iwl_queue_progress(struct iwl_trans_pcie *trans_pcie, |
693 | struct iwl_tx_queue *txq) | |
694 | { | |
695 | if (!trans_pcie->wd_timeout) | |
696 | return; | |
697 | ||
698 | /* | |
699 | * if empty delete timer, otherwise move timer forward | |
700 | * since we're making progress on this queue | |
701 | */ | |
702 | if (txq->q.read_ptr == txq->q.write_ptr) | |
703 | del_timer(&txq->stuck_timer); | |
704 | else | |
705 | mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout); | |
706 | } | |
707 | ||
17b88929 TW |
708 | /** |
709 | * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd | |
710 | * | |
711 | * When FW advances 'R' index, all entries between old and new 'R' index | |
712 | * need to be reclaimed. As result, some free space forms. If there is | |
713 | * enough free space (> low mark), wake the stack that feeds us. | |
714 | */ | |
3e10caeb EG |
715 | static void iwl_hcmd_queue_reclaim(struct iwl_trans *trans, int txq_id, |
716 | int idx) | |
17b88929 | 717 | { |
3e10caeb | 718 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
8ad71bef | 719 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; |
17b88929 TW |
720 | struct iwl_queue *q = &txq->q; |
721 | int nfreed = 0; | |
722 | ||
015c15e1 JB |
723 | lockdep_assert_held(&txq->lock); |
724 | ||
499b1883 | 725 | if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) { |
3e10caeb | 726 | IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), " |
2e5d04da DH |
727 | "index %d is out of range [0-%d] %d %d.\n", __func__, |
728 | txq_id, idx, q->n_bd, q->write_ptr, q->read_ptr); | |
17b88929 TW |
729 | return; |
730 | } | |
731 | ||
499b1883 TW |
732 | for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; |
733 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
17b88929 | 734 | |
499b1883 | 735 | if (nfreed++ > 0) { |
3e10caeb | 736 | IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", idx, |
17b88929 | 737 | q->write_ptr, q->read_ptr); |
bcb9321c | 738 | iwl_op_mode_nic_error(trans->op_mode); |
17b88929 | 739 | } |
da99c4b6 | 740 | |
17b88929 | 741 | } |
7c5ba4a8 JB |
742 | |
743 | iwl_queue_progress(trans_pcie, txq); | |
17b88929 TW |
744 | } |
745 | ||
746 | /** | |
747 | * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them | |
748 | * @rxb: Rx buffer to reclaim | |
247c61d6 EG |
749 | * @handler_status: return value of the handler of the command |
750 | * (put in setup_rx_handlers) | |
17b88929 TW |
751 | * |
752 | * If an Rx buffer has an async callback associated with it the callback | |
753 | * will be executed. The attached skb (if present) will only be freed | |
754 | * if the callback returns 1 | |
755 | */ | |
48a2d66f | 756 | void iwl_tx_cmd_complete(struct iwl_trans *trans, struct iwl_rx_cmd_buffer *rxb, |
247c61d6 | 757 | int handler_status) |
17b88929 | 758 | { |
2f301227 | 759 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
17b88929 TW |
760 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
761 | int txq_id = SEQ_TO_QUEUE(sequence); | |
762 | int index = SEQ_TO_INDEX(sequence); | |
17b88929 | 763 | int cmd_index; |
c2acea8e JB |
764 | struct iwl_device_cmd *cmd; |
765 | struct iwl_cmd_meta *meta; | |
8ad71bef | 766 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
c6f600fc | 767 | struct iwl_tx_queue *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
17b88929 TW |
768 | |
769 | /* If a Tx command is being handled and it isn't in the actual | |
770 | * command queue then there a command routing bug has been introduced | |
771 | * in the queue management code. */ | |
c6f600fc | 772 | if (WARN(txq_id != trans_pcie->cmd_queue, |
13bb9483 | 773 | "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", |
c6f600fc MV |
774 | txq_id, trans_pcie->cmd_queue, sequence, |
775 | trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr, | |
776 | trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) { | |
3e10caeb | 777 | iwl_print_hex_error(trans, pkt, 32); |
55d6a3cd | 778 | return; |
01ef9323 | 779 | } |
17b88929 | 780 | |
015c15e1 JB |
781 | spin_lock(&txq->lock); |
782 | ||
4ce7cc2b | 783 | cmd_index = get_cmd_index(&txq->q, index); |
bf8440e6 JB |
784 | cmd = txq->entries[cmd_index].cmd; |
785 | meta = &txq->entries[cmd_index].meta; | |
17b88929 | 786 | |
eec373f0 | 787 | iwl_unmap_tfd(trans, meta, &txq->tfds[index], DMA_BIDIRECTIONAL); |
c33de625 | 788 | |
17b88929 | 789 | /* Input error checking is done when commands are added to queue. */ |
c2acea8e | 790 | if (meta->flags & CMD_WANT_SKB) { |
48a2d66f | 791 | struct page *p = rxb_steal_page(rxb); |
65b94a4a | 792 | |
65b94a4a JB |
793 | meta->source->resp_pkt = pkt; |
794 | meta->source->_rx_page_addr = (unsigned long)page_address(p); | |
b2cf410c | 795 | meta->source->_rx_page_order = trans_pcie->rx_page_order; |
247c61d6 | 796 | meta->source->handler_status = handler_status; |
247c61d6 | 797 | } |
2624e96c | 798 | |
3e10caeb | 799 | iwl_hcmd_queue_reclaim(trans, txq_id, index); |
17b88929 | 800 | |
c2acea8e | 801 | if (!(meta->flags & CMD_ASYNC)) { |
74fda971 | 802 | if (!test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) { |
05c89b91 WYG |
803 | IWL_WARN(trans, |
804 | "HCMD_ACTIVE already clear for command %s\n", | |
d9fb6465 JB |
805 | trans_pcie_get_cmd_string(trans_pcie, |
806 | cmd->hdr.cmd)); | |
05c89b91 | 807 | } |
74fda971 | 808 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); |
6d8f6eeb | 809 | IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", |
d9fb6465 JB |
810 | trans_pcie_get_cmd_string(trans_pcie, |
811 | cmd->hdr.cmd)); | |
69a10b29 | 812 | wake_up(&trans->wait_command_queue); |
17b88929 | 813 | } |
3598e177 | 814 | |
dd487449 | 815 | meta->flags = 0; |
3598e177 | 816 | |
015c15e1 | 817 | spin_unlock(&txq->lock); |
17b88929 | 818 | } |
253a634c | 819 | |
253a634c EG |
820 | #define HOST_COMPLETE_TIMEOUT (2 * HZ) |
821 | ||
6d8f6eeb | 822 | static int iwl_send_cmd_async(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c | 823 | { |
d9fb6465 | 824 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
253a634c EG |
825 | int ret; |
826 | ||
827 | /* An asynchronous command can not expect an SKB to be set. */ | |
828 | if (WARN_ON(cmd->flags & CMD_WANT_SKB)) | |
829 | return -EINVAL; | |
830 | ||
253a634c | 831 | |
6d8f6eeb | 832 | ret = iwl_enqueue_hcmd(trans, cmd); |
253a634c | 833 | if (ret < 0) { |
721c32f7 | 834 | IWL_ERR(trans, |
b36b110c | 835 | "Error sending %s: enqueue_hcmd failed: %d\n", |
d9fb6465 | 836 | trans_pcie_get_cmd_string(trans_pcie, cmd->id), ret); |
253a634c EG |
837 | return ret; |
838 | } | |
839 | return 0; | |
840 | } | |
841 | ||
6d8f6eeb | 842 | static int iwl_send_cmd_sync(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c | 843 | { |
8ad71bef | 844 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
253a634c EG |
845 | int cmd_idx; |
846 | int ret; | |
847 | ||
6d8f6eeb | 848 | IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", |
d9fb6465 | 849 | trans_pcie_get_cmd_string(trans_pcie, cmd->id)); |
253a634c | 850 | |
2cc39c94 | 851 | if (WARN_ON(test_and_set_bit(STATUS_HCMD_ACTIVE, |
74fda971 | 852 | &trans_pcie->status))) { |
2cc39c94 | 853 | IWL_ERR(trans, "Command %s: a command is already active!\n", |
d9fb6465 | 854 | trans_pcie_get_cmd_string(trans_pcie, cmd->id)); |
2cc39c94 JB |
855 | return -EIO; |
856 | } | |
857 | ||
6d8f6eeb | 858 | IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", |
d9fb6465 | 859 | trans_pcie_get_cmd_string(trans_pcie, cmd->id)); |
253a634c | 860 | |
6d8f6eeb | 861 | cmd_idx = iwl_enqueue_hcmd(trans, cmd); |
253a634c EG |
862 | if (cmd_idx < 0) { |
863 | ret = cmd_idx; | |
74fda971 | 864 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); |
721c32f7 | 865 | IWL_ERR(trans, |
b36b110c | 866 | "Error sending %s: enqueue_hcmd failed: %d\n", |
d9fb6465 | 867 | trans_pcie_get_cmd_string(trans_pcie, cmd->id), ret); |
253a634c EG |
868 | return ret; |
869 | } | |
870 | ||
69a10b29 | 871 | ret = wait_event_timeout(trans->wait_command_queue, |
74fda971 | 872 | !test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status), |
253a634c EG |
873 | HOST_COMPLETE_TIMEOUT); |
874 | if (!ret) { | |
74fda971 | 875 | if (test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) { |
d10630af | 876 | struct iwl_tx_queue *txq = |
c6f600fc | 877 | &trans_pcie->txq[trans_pcie->cmd_queue]; |
d10630af WYG |
878 | struct iwl_queue *q = &txq->q; |
879 | ||
721c32f7 | 880 | IWL_ERR(trans, |
253a634c | 881 | "Error sending %s: time out after %dms.\n", |
d9fb6465 | 882 | trans_pcie_get_cmd_string(trans_pcie, cmd->id), |
253a634c EG |
883 | jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); |
884 | ||
721c32f7 | 885 | IWL_ERR(trans, |
d10630af WYG |
886 | "Current CMD queue read_ptr %d write_ptr %d\n", |
887 | q->read_ptr, q->write_ptr); | |
888 | ||
74fda971 | 889 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); |
d9fb6465 JB |
890 | IWL_DEBUG_INFO(trans, |
891 | "Clearing HCMD_ACTIVE for command %s\n", | |
892 | trans_pcie_get_cmd_string(trans_pcie, | |
893 | cmd->id)); | |
253a634c EG |
894 | ret = -ETIMEDOUT; |
895 | goto cancel; | |
896 | } | |
897 | } | |
898 | ||
65b94a4a | 899 | if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) { |
6d8f6eeb | 900 | IWL_ERR(trans, "Error: Response NULL in '%s'\n", |
d9fb6465 | 901 | trans_pcie_get_cmd_string(trans_pcie, cmd->id)); |
253a634c EG |
902 | ret = -EIO; |
903 | goto cancel; | |
904 | } | |
905 | ||
906 | return 0; | |
907 | ||
908 | cancel: | |
909 | if (cmd->flags & CMD_WANT_SKB) { | |
910 | /* | |
911 | * Cancel the CMD_WANT_SKB flag for the cmd in the | |
912 | * TX cmd queue. Otherwise in case the cmd comes | |
913 | * in later, it will possibly set an invalid | |
914 | * address (cmd->meta.source). | |
915 | */ | |
bf8440e6 JB |
916 | trans_pcie->txq[trans_pcie->cmd_queue]. |
917 | entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB; | |
253a634c | 918 | } |
9cac4943 | 919 | |
65b94a4a JB |
920 | if (cmd->resp_pkt) { |
921 | iwl_free_resp(cmd); | |
922 | cmd->resp_pkt = NULL; | |
253a634c EG |
923 | } |
924 | ||
925 | return ret; | |
926 | } | |
927 | ||
6d8f6eeb | 928 | int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c EG |
929 | { |
930 | if (cmd->flags & CMD_ASYNC) | |
6d8f6eeb | 931 | return iwl_send_cmd_async(trans, cmd); |
253a634c | 932 | |
6d8f6eeb | 933 | return iwl_send_cmd_sync(trans, cmd); |
253a634c EG |
934 | } |
935 | ||
a0eaad71 | 936 | /* Frees buffers until index _not_ inclusive */ |
464021ff EG |
937 | int iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index, |
938 | struct sk_buff_head *skbs) | |
a0eaad71 | 939 | { |
8ad71bef EG |
940 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
941 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; | |
a0eaad71 | 942 | struct iwl_queue *q = &txq->q; |
a0eaad71 | 943 | int last_to_free; |
464021ff | 944 | int freed = 0; |
a0eaad71 | 945 | |
39644e9a | 946 | /* This function is not meant to release cmd queue*/ |
c6f600fc | 947 | if (WARN_ON(txq_id == trans_pcie->cmd_queue)) |
39644e9a EG |
948 | return 0; |
949 | ||
015c15e1 JB |
950 | lockdep_assert_held(&txq->lock); |
951 | ||
a0eaad71 EG |
952 | /*Since we free until index _not_ inclusive, the one before index is |
953 | * the last we will free. This one must be used */ | |
954 | last_to_free = iwl_queue_dec_wrap(index, q->n_bd); | |
955 | ||
956 | if ((index >= q->n_bd) || | |
957 | (iwl_queue_used(q, last_to_free) == 0)) { | |
958 | IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), " | |
959 | "last_to_free %d is out of range [0-%d] %d %d.\n", | |
960 | __func__, txq_id, last_to_free, q->n_bd, | |
961 | q->write_ptr, q->read_ptr); | |
464021ff | 962 | return 0; |
a0eaad71 EG |
963 | } |
964 | ||
a0eaad71 | 965 | if (WARN_ON(!skb_queue_empty(skbs))) |
464021ff | 966 | return 0; |
a0eaad71 EG |
967 | |
968 | for (; | |
969 | q->read_ptr != index; | |
970 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
971 | ||
bf8440e6 | 972 | if (WARN_ON_ONCE(txq->entries[txq->q.read_ptr].skb == NULL)) |
a0eaad71 EG |
973 | continue; |
974 | ||
bf8440e6 | 975 | __skb_queue_tail(skbs, txq->entries[txq->q.read_ptr].skb); |
a0eaad71 | 976 | |
bf8440e6 | 977 | txq->entries[txq->q.read_ptr].skb = NULL; |
a0eaad71 | 978 | |
6d8f6eeb | 979 | iwlagn_txq_inval_byte_cnt_tbl(trans, txq); |
a0eaad71 | 980 | |
bc2529c3 | 981 | iwl_txq_free_tfd(trans, txq, DMA_TO_DEVICE); |
464021ff | 982 | freed++; |
a0eaad71 | 983 | } |
7c5ba4a8 JB |
984 | |
985 | iwl_queue_progress(trans_pcie, txq); | |
986 | ||
464021ff | 987 | return freed; |
a0eaad71 | 988 | } |