Commit | Line | Data |
---|---|---|
1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
fb4961db | 3 | * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved. |
1053d35f RR |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
1053d35f RR |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
fd4abac5 | 29 | #include <linux/etherdevice.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
253a634c | 31 | #include <linux/sched.h> |
253a634c | 32 | |
522376d2 EG |
33 | #include "iwl-debug.h" |
34 | #include "iwl-csr.h" | |
35 | #include "iwl-prph.h" | |
1053d35f | 36 | #include "iwl-io.h" |
522376d2 | 37 | #include "iwl-agn-hw.h" |
ed277c93 | 38 | #include "iwl-op-mode.h" |
c17d0681 | 39 | #include "iwl-trans-pcie-int.h" |
1053d35f | 40 | |
522376d2 EG |
41 | #define IWL_TX_CRC_SIZE 4 |
42 | #define IWL_TX_DELIMITER_SIZE 4 | |
43 | ||
48d42c42 EG |
44 | /** |
45 | * iwl_trans_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array | |
46 | */ | |
6d8f6eeb | 47 | void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans, |
48d42c42 EG |
48 | struct iwl_tx_queue *txq, |
49 | u16 byte_cnt) | |
50 | { | |
105183b1 | 51 | struct iwlagn_scd_bc_tbl *scd_bc_tbl; |
105183b1 EG |
52 | struct iwl_trans_pcie *trans_pcie = |
53 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
48d42c42 EG |
54 | int write_ptr = txq->q.write_ptr; |
55 | int txq_id = txq->q.id; | |
56 | u8 sec_ctl = 0; | |
57 | u8 sta_id = 0; | |
58 | u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; | |
59 | __le16 bc_ent; | |
132f98c2 EG |
60 | struct iwl_tx_cmd *tx_cmd = |
61 | (struct iwl_tx_cmd *) txq->cmd[txq->q.write_ptr]->payload; | |
48d42c42 | 62 | |
105183b1 EG |
63 | scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; |
64 | ||
48d42c42 EG |
65 | WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX); |
66 | ||
132f98c2 EG |
67 | sta_id = tx_cmd->sta_id; |
68 | sec_ctl = tx_cmd->sec_ctl; | |
48d42c42 EG |
69 | |
70 | switch (sec_ctl & TX_CMD_SEC_MSK) { | |
71 | case TX_CMD_SEC_CCM: | |
72 | len += CCMP_MIC_LEN; | |
73 | break; | |
74 | case TX_CMD_SEC_TKIP: | |
75 | len += TKIP_ICV_LEN; | |
76 | break; | |
77 | case TX_CMD_SEC_WEP: | |
78 | len += WEP_IV_LEN + WEP_ICV_LEN; | |
79 | break; | |
80 | } | |
81 | ||
82 | bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12)); | |
83 | ||
84 | scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; | |
85 | ||
86 | if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
87 | scd_bc_tbl[txq_id]. | |
88 | tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; | |
89 | } | |
90 | ||
fd4abac5 TW |
91 | /** |
92 | * iwl_txq_update_write_ptr - Send new write index to hardware | |
93 | */ | |
fd656935 | 94 | void iwl_txq_update_write_ptr(struct iwl_trans *trans, struct iwl_tx_queue *txq) |
fd4abac5 TW |
95 | { |
96 | u32 reg = 0; | |
fd4abac5 TW |
97 | int txq_id = txq->q.id; |
98 | ||
99 | if (txq->need_update == 0) | |
7bfedc59 | 100 | return; |
fd4abac5 | 101 | |
0dde86b2 | 102 | if (cfg(trans)->base_params->shadow_reg_enable) { |
f81c1f48 | 103 | /* shadow register enabled */ |
1042db2a | 104 | iwl_write32(trans, HBUS_TARG_WRPTR, |
f81c1f48 WYG |
105 | txq->q.write_ptr | (txq_id << 8)); |
106 | } else { | |
47107e84 DF |
107 | struct iwl_trans_pcie *trans_pcie = |
108 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
f81c1f48 | 109 | /* if we're trying to save power */ |
47107e84 | 110 | if (test_bit(STATUS_POWER_PMI, &trans_pcie->status)) { |
f81c1f48 WYG |
111 | /* wake up nic if it's powered down ... |
112 | * uCode will wake up, and interrupt us again, so next | |
113 | * time we'll skip this part. */ | |
1042db2a | 114 | reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); |
fd4abac5 | 115 | |
f81c1f48 | 116 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { |
fd656935 | 117 | IWL_DEBUG_INFO(trans, |
f81c1f48 WYG |
118 | "Tx queue %d requesting wakeup," |
119 | " GP1 = 0x%x\n", txq_id, reg); | |
1042db2a | 120 | iwl_set_bit(trans, CSR_GP_CNTRL, |
f81c1f48 WYG |
121 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
122 | return; | |
123 | } | |
fd4abac5 | 124 | |
1042db2a | 125 | iwl_write_direct32(trans, HBUS_TARG_WRPTR, |
fd4abac5 | 126 | txq->q.write_ptr | (txq_id << 8)); |
fd4abac5 | 127 | |
f81c1f48 WYG |
128 | /* |
129 | * else not in power-save mode, | |
130 | * uCode will never sleep when we're | |
131 | * trying to tx (during RFKILL, we're not trying to tx). | |
132 | */ | |
133 | } else | |
1042db2a | 134 | iwl_write32(trans, HBUS_TARG_WRPTR, |
f81c1f48 WYG |
135 | txq->q.write_ptr | (txq_id << 8)); |
136 | } | |
fd4abac5 | 137 | txq->need_update = 0; |
fd4abac5 | 138 | } |
fd4abac5 | 139 | |
214d14d4 JB |
140 | static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
141 | { | |
142 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
143 | ||
144 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
145 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
146 | addr |= | |
147 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
148 | ||
149 | return addr; | |
150 | } | |
151 | ||
152 | static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) | |
153 | { | |
154 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
155 | ||
156 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
157 | } | |
158 | ||
159 | static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, | |
160 | dma_addr_t addr, u16 len) | |
161 | { | |
162 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
163 | u16 hi_n_len = len << 4; | |
164 | ||
165 | put_unaligned_le32(addr, &tb->lo); | |
166 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
167 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
168 | ||
169 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
170 | ||
171 | tfd->num_tbs = idx + 1; | |
172 | } | |
173 | ||
174 | static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd) | |
175 | { | |
176 | return tfd->num_tbs & 0x1f; | |
177 | } | |
178 | ||
6d8f6eeb | 179 | static void iwlagn_unmap_tfd(struct iwl_trans *trans, struct iwl_cmd_meta *meta, |
253a634c | 180 | struct iwl_tfd *tfd, enum dma_data_direction dma_dir) |
214d14d4 | 181 | { |
214d14d4 JB |
182 | int i; |
183 | int num_tbs; | |
184 | ||
214d14d4 JB |
185 | /* Sanity check on number of chunks */ |
186 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
187 | ||
188 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
6d8f6eeb | 189 | IWL_ERR(trans, "Too many chunks: %i\n", num_tbs); |
214d14d4 JB |
190 | /* @todo issue fatal error, it is quite serious situation */ |
191 | return; | |
192 | } | |
193 | ||
194 | /* Unmap tx_cmd */ | |
195 | if (num_tbs) | |
1042db2a | 196 | dma_unmap_single(trans->dev, |
4ce7cc2b JB |
197 | dma_unmap_addr(meta, mapping), |
198 | dma_unmap_len(meta, len), | |
795414db | 199 | DMA_BIDIRECTIONAL); |
214d14d4 JB |
200 | |
201 | /* Unmap chunks, if any. */ | |
202 | for (i = 1; i < num_tbs; i++) | |
1042db2a | 203 | dma_unmap_single(trans->dev, iwl_tfd_tb_get_addr(tfd, i), |
e815407d | 204 | iwl_tfd_tb_get_len(tfd, i), dma_dir); |
4ce7cc2b JB |
205 | } |
206 | ||
207 | /** | |
208 | * iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
6d8f6eeb | 209 | * @trans - transport private data |
4ce7cc2b | 210 | * @txq - tx queue |
1359ca4f | 211 | * @index - the index of the TFD to be freed |
39644e9a | 212 | *@dma_dir - the direction of the DMA mapping |
4ce7cc2b JB |
213 | * |
214 | * Does NOT advance any TFD circular buffer read/write indexes | |
215 | * Does NOT free the TFD itself (which is within circular buffer) | |
216 | */ | |
6d8f6eeb | 217 | void iwlagn_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq, |
39644e9a | 218 | int index, enum dma_data_direction dma_dir) |
4ce7cc2b JB |
219 | { |
220 | struct iwl_tfd *tfd_tmp = txq->tfds; | |
4ce7cc2b | 221 | |
015c15e1 JB |
222 | lockdep_assert_held(&txq->lock); |
223 | ||
39644e9a | 224 | iwlagn_unmap_tfd(trans, &txq->meta[index], &tfd_tmp[index], dma_dir); |
214d14d4 JB |
225 | |
226 | /* free SKB */ | |
2c452297 | 227 | if (txq->skbs) { |
214d14d4 JB |
228 | struct sk_buff *skb; |
229 | ||
2c452297 | 230 | skb = txq->skbs[index]; |
214d14d4 | 231 | |
909e9b23 EG |
232 | /* Can be called from irqs-disabled context |
233 | * If skb is not NULL, it means that the whole queue is being | |
234 | * freed and that the queue is not empty - free the skb | |
235 | */ | |
214d14d4 | 236 | if (skb) { |
ed277c93 | 237 | iwl_op_mode_free_skb(trans->op_mode, skb); |
2c452297 | 238 | txq->skbs[index] = NULL; |
214d14d4 JB |
239 | } |
240 | } | |
241 | } | |
242 | ||
6d8f6eeb | 243 | int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans, |
214d14d4 JB |
244 | struct iwl_tx_queue *txq, |
245 | dma_addr_t addr, u16 len, | |
4c42db0f | 246 | u8 reset) |
214d14d4 JB |
247 | { |
248 | struct iwl_queue *q; | |
249 | struct iwl_tfd *tfd, *tfd_tmp; | |
250 | u32 num_tbs; | |
251 | ||
252 | q = &txq->q; | |
4ce7cc2b | 253 | tfd_tmp = txq->tfds; |
214d14d4 JB |
254 | tfd = &tfd_tmp[q->write_ptr]; |
255 | ||
256 | if (reset) | |
257 | memset(tfd, 0, sizeof(*tfd)); | |
258 | ||
259 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
260 | ||
261 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
262 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
6d8f6eeb | 263 | IWL_ERR(trans, "Error can not send more than %d chunks\n", |
214d14d4 JB |
264 | IWL_NUM_OF_TBS); |
265 | return -EINVAL; | |
266 | } | |
267 | ||
268 | if (WARN_ON(addr & ~DMA_BIT_MASK(36))) | |
269 | return -EINVAL; | |
270 | ||
271 | if (unlikely(addr & ~IWL_TX_DMA_MASK)) | |
6d8f6eeb | 272 | IWL_ERR(trans, "Unaligned address = %llx\n", |
214d14d4 JB |
273 | (unsigned long long)addr); |
274 | ||
275 | iwl_tfd_set_tb(tfd, num_tbs, addr, len); | |
276 | ||
277 | return 0; | |
278 | } | |
279 | ||
fd4abac5 TW |
280 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
281 | * DMA services | |
282 | * | |
283 | * Theory of operation | |
284 | * | |
285 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
286 | * of buffer descriptors, each of which points to one or more data buffers for | |
287 | * the device to read from or fill. Driver and device exchange status of each | |
288 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
289 | * entries in each circular buffer, to protect against confusing empty and full | |
290 | * queue states. | |
291 | * | |
292 | * The device reads or writes the data in the queues via the device's several | |
293 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
294 | * | |
295 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
296 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
297 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
298 | * Tx queue resumed. | |
299 | * | |
fd4abac5 TW |
300 | ***************************************************/ |
301 | ||
302 | int iwl_queue_space(const struct iwl_queue *q) | |
303 | { | |
304 | int s = q->read_ptr - q->write_ptr; | |
305 | ||
306 | if (q->read_ptr > q->write_ptr) | |
307 | s -= q->n_bd; | |
308 | ||
309 | if (s <= 0) | |
310 | s += q->n_window; | |
311 | /* keep some reserve to not confuse empty and full situations */ | |
312 | s -= 2; | |
313 | if (s < 0) | |
314 | s = 0; | |
315 | return s; | |
316 | } | |
fd4abac5 | 317 | |
1053d35f RR |
318 | /** |
319 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes | |
320 | */ | |
6d8f6eeb | 321 | int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id) |
1053d35f RR |
322 | { |
323 | q->n_bd = count; | |
324 | q->n_window = slots_num; | |
325 | q->id = id; | |
326 | ||
327 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap | |
328 | * and iwl_queue_dec_wrap are broken. */ | |
3e41ace5 JB |
329 | if (WARN_ON(!is_power_of_2(count))) |
330 | return -EINVAL; | |
1053d35f RR |
331 | |
332 | /* slots_num must be power-of-two size, otherwise | |
333 | * get_cmd_index is broken. */ | |
3e41ace5 JB |
334 | if (WARN_ON(!is_power_of_2(slots_num))) |
335 | return -EINVAL; | |
1053d35f RR |
336 | |
337 | q->low_mark = q->n_window / 4; | |
338 | if (q->low_mark < 4) | |
339 | q->low_mark = 4; | |
340 | ||
341 | q->high_mark = q->n_window / 8; | |
342 | if (q->high_mark < 2) | |
343 | q->high_mark = 2; | |
344 | ||
345 | q->write_ptr = q->read_ptr = 0; | |
346 | ||
347 | return 0; | |
348 | } | |
349 | ||
6d8f6eeb | 350 | static void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_trans *trans, |
48d42c42 EG |
351 | struct iwl_tx_queue *txq) |
352 | { | |
105183b1 EG |
353 | struct iwl_trans_pcie *trans_pcie = |
354 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
6d8f6eeb | 355 | struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; |
48d42c42 EG |
356 | int txq_id = txq->q.id; |
357 | int read_ptr = txq->q.read_ptr; | |
358 | u8 sta_id = 0; | |
359 | __le16 bc_ent; | |
132f98c2 EG |
360 | struct iwl_tx_cmd *tx_cmd = |
361 | (struct iwl_tx_cmd *) txq->cmd[txq->q.read_ptr]->payload; | |
48d42c42 EG |
362 | |
363 | WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); | |
364 | ||
c6f600fc | 365 | if (txq_id != trans_pcie->cmd_queue) |
132f98c2 | 366 | sta_id = tx_cmd->sta_id; |
48d42c42 EG |
367 | |
368 | bc_ent = cpu_to_le16(1 | (sta_id << 12)); | |
369 | scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; | |
370 | ||
371 | if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
372 | scd_bc_tbl[txq_id]. | |
373 | tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; | |
374 | } | |
375 | ||
6d8f6eeb | 376 | static int iwlagn_tx_queue_set_q2ratid(struct iwl_trans *trans, u16 ra_tid, |
48d42c42 EG |
377 | u16 txq_id) |
378 | { | |
379 | u32 tbl_dw_addr; | |
380 | u32 tbl_dw; | |
381 | u16 scd_q2ratid; | |
382 | ||
105183b1 EG |
383 | struct iwl_trans_pcie *trans_pcie = |
384 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
385 | ||
48d42c42 EG |
386 | scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; |
387 | ||
105183b1 | 388 | tbl_dw_addr = trans_pcie->scd_base_addr + |
48d42c42 EG |
389 | SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); |
390 | ||
1042db2a | 391 | tbl_dw = iwl_read_targ_mem(trans, tbl_dw_addr); |
48d42c42 EG |
392 | |
393 | if (txq_id & 0x1) | |
394 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); | |
395 | else | |
396 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); | |
397 | ||
1042db2a | 398 | iwl_write_targ_mem(trans, tbl_dw_addr, tbl_dw); |
48d42c42 EG |
399 | |
400 | return 0; | |
401 | } | |
402 | ||
6d8f6eeb | 403 | static void iwlagn_tx_queue_stop_scheduler(struct iwl_trans *trans, u16 txq_id) |
48d42c42 EG |
404 | { |
405 | /* Simply stop the queue, but don't change any configuration; | |
406 | * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ | |
1042db2a | 407 | iwl_write_prph(trans, |
48d42c42 EG |
408 | SCD_QUEUE_STATUS_BITS(txq_id), |
409 | (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)| | |
410 | (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); | |
411 | } | |
412 | ||
6d8f6eeb | 413 | void iwl_trans_set_wr_ptrs(struct iwl_trans *trans, |
48d42c42 EG |
414 | int txq_id, u32 index) |
415 | { | |
0ca24daf | 416 | IWL_DEBUG_TX_QUEUES(trans, "Q %d WrPtr: %d\n", txq_id, index & 0xff); |
1042db2a | 417 | iwl_write_direct32(trans, HBUS_TARG_WRPTR, |
48d42c42 | 418 | (index & 0xff) | (txq_id << 8)); |
1042db2a | 419 | iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), index); |
48d42c42 EG |
420 | } |
421 | ||
c91bd124 | 422 | void iwl_trans_tx_queue_set_status(struct iwl_trans *trans, |
9eae88fa JB |
423 | struct iwl_tx_queue *txq, |
424 | int tx_fifo_id, bool active) | |
48d42c42 EG |
425 | { |
426 | int txq_id = txq->q.id; | |
48d42c42 | 427 | |
1042db2a | 428 | iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id), |
48d42c42 EG |
429 | (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) | |
430 | (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) | | |
431 | (1 << SCD_QUEUE_STTS_REG_POS_WSL) | | |
432 | SCD_QUEUE_STTS_REG_MSK); | |
433 | ||
1dcedc8e | 434 | if (active) |
9eae88fa JB |
435 | IWL_DEBUG_TX_QUEUES(trans, "Activate queue %d on FIFO %d\n", |
436 | txq_id, tx_fifo_id); | |
1dcedc8e | 437 | else |
9eae88fa | 438 | IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id); |
76bc10fc EG |
439 | } |
440 | ||
9eae88fa JB |
441 | void iwl_trans_pcie_tx_agg_setup(struct iwl_trans *trans, int txq_id, int fifo, |
442 | int sta_id, int tid, int frame_limit, u16 ssn) | |
48d42c42 | 443 | { |
9eae88fa | 444 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
48d42c42 | 445 | unsigned long flags; |
9eae88fa | 446 | u16 ra_tid = BUILD_RAxTID(sta_id, tid); |
48d42c42 | 447 | |
9eae88fa JB |
448 | if (test_and_set_bit(txq_id, trans_pcie->queue_used)) |
449 | WARN_ONCE(1, "queue %d already used - expect issues", txq_id); | |
48d42c42 | 450 | |
7b11488f | 451 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
48d42c42 EG |
452 | |
453 | /* Stop this Tx queue before configuring it */ | |
6d8f6eeb | 454 | iwlagn_tx_queue_stop_scheduler(trans, txq_id); |
48d42c42 EG |
455 | |
456 | /* Map receiver-address / traffic-ID to this queue */ | |
6d8f6eeb | 457 | iwlagn_tx_queue_set_q2ratid(trans, ra_tid, txq_id); |
48d42c42 EG |
458 | |
459 | /* Set this queue as a chain-building queue */ | |
9eae88fa | 460 | iwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, BIT(txq_id)); |
48d42c42 EG |
461 | |
462 | /* enable aggregations for the queue */ | |
9eae88fa | 463 | iwl_set_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id)); |
48d42c42 EG |
464 | |
465 | /* Place first TFD at index corresponding to start sequence number. | |
466 | * Assumes that ssn_idx is valid (!= 0xFFF) */ | |
822e8b2a EG |
467 | trans_pcie->txq[txq_id].q.read_ptr = (ssn & 0xff); |
468 | trans_pcie->txq[txq_id].q.write_ptr = (ssn & 0xff); | |
469 | iwl_trans_set_wr_ptrs(trans, txq_id, ssn); | |
48d42c42 EG |
470 | |
471 | /* Set up Tx window size and frame limit for this queue */ | |
1042db2a | 472 | iwl_write_targ_mem(trans, trans_pcie->scd_base_addr + |
9eae88fa JB |
473 | SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), |
474 | ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
475 | SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
476 | ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
477 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
48d42c42 | 478 | |
1042db2a | 479 | iwl_set_bits_prph(trans, SCD_INTERRUPT_MASK, (1 << txq_id)); |
48d42c42 EG |
480 | |
481 | /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ | |
8ad71bef | 482 | iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id], |
9eae88fa | 483 | fifo, true); |
a0eaad71 | 484 | |
7b11488f | 485 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
48d42c42 EG |
486 | } |
487 | ||
9eae88fa | 488 | void iwl_trans_pcie_tx_agg_disable(struct iwl_trans *trans, int txq_id) |
288712a6 | 489 | { |
8ad71bef | 490 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
288712a6 | 491 | |
9eae88fa JB |
492 | if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) { |
493 | WARN_ONCE(1, "queue %d not used", txq_id); | |
494 | return; | |
48d42c42 EG |
495 | } |
496 | ||
bc237730 | 497 | iwlagn_tx_queue_stop_scheduler(trans, txq_id); |
7f01d567 | 498 | |
9eae88fa | 499 | iwl_clear_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id)); |
48d42c42 | 500 | |
bc237730 EG |
501 | trans_pcie->txq[txq_id].q.read_ptr = 0; |
502 | trans_pcie->txq[txq_id].q.write_ptr = 0; | |
bc237730 | 503 | iwl_trans_set_wr_ptrs(trans, txq_id, 0); |
48d42c42 | 504 | |
9eae88fa JB |
505 | iwl_clear_bits_prph(trans, SCD_INTERRUPT_MASK, BIT(txq_id)); |
506 | ||
507 | iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id], | |
508 | 0, false); | |
48d42c42 EG |
509 | } |
510 | ||
fd4abac5 TW |
511 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ |
512 | ||
513 | /** | |
514 | * iwl_enqueue_hcmd - enqueue a uCode command | |
515 | * @priv: device private data point | |
516 | * @cmd: a point to the ucode command structure | |
517 | * | |
518 | * The function returns < 0 values to indicate the operation is | |
519 | * failed. On success, it turns the index (> 0) of command in the | |
520 | * command queue. | |
521 | */ | |
6d8f6eeb | 522 | static int iwl_enqueue_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
fd4abac5 | 523 | { |
8ad71bef | 524 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
c6f600fc | 525 | struct iwl_tx_queue *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
fd4abac5 | 526 | struct iwl_queue *q = &txq->q; |
c2acea8e JB |
527 | struct iwl_device_cmd *out_cmd; |
528 | struct iwl_cmd_meta *out_meta; | |
fd4abac5 | 529 | dma_addr_t phys_addr; |
f3674227 | 530 | u32 idx; |
4ce7cc2b | 531 | u16 copy_size, cmd_size; |
4ce7cc2b JB |
532 | bool had_nocopy = false; |
533 | int i; | |
534 | u8 *cmd_dest; | |
535 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
536 | const void *trace_bufs[IWL_MAX_CMD_TFDS + 1] = {}; | |
537 | int trace_lens[IWL_MAX_CMD_TFDS + 1] = {}; | |
538 | int trace_idx; | |
539 | #endif | |
fd4abac5 | 540 | |
4ce7cc2b JB |
541 | copy_size = sizeof(out_cmd->hdr); |
542 | cmd_size = sizeof(out_cmd->hdr); | |
543 | ||
544 | /* need one for the header if the first is NOCOPY */ | |
545 | BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1); | |
546 | ||
547 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
548 | if (!cmd->len[i]) | |
549 | continue; | |
550 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { | |
551 | had_nocopy = true; | |
552 | } else { | |
553 | /* NOCOPY must not be followed by normal! */ | |
554 | if (WARN_ON(had_nocopy)) | |
555 | return -EINVAL; | |
556 | copy_size += cmd->len[i]; | |
557 | } | |
558 | cmd_size += cmd->len[i]; | |
559 | } | |
fd4abac5 | 560 | |
3e41ace5 JB |
561 | /* |
562 | * If any of the command structures end up being larger than | |
4ce7cc2b JB |
563 | * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically |
564 | * allocated into separate TFDs, then we will need to | |
565 | * increase the size of the buffers. | |
3e41ace5 | 566 | */ |
4ce7cc2b | 567 | if (WARN_ON(copy_size > TFD_MAX_PAYLOAD_SIZE)) |
3e41ace5 | 568 | return -EINVAL; |
fd4abac5 | 569 | |
015c15e1 | 570 | spin_lock_bh(&txq->lock); |
3598e177 | 571 | |
c2acea8e | 572 | if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { |
015c15e1 | 573 | spin_unlock_bh(&txq->lock); |
3598e177 | 574 | |
6d8f6eeb | 575 | IWL_ERR(trans, "No space in command queue\n"); |
0e781842 | 576 | iwl_op_mode_cmd_queue_full(trans->op_mode); |
fd4abac5 TW |
577 | return -ENOSPC; |
578 | } | |
579 | ||
4ce7cc2b | 580 | idx = get_cmd_index(q, q->write_ptr); |
da99c4b6 | 581 | out_cmd = txq->cmd[idx]; |
c2acea8e JB |
582 | out_meta = &txq->meta[idx]; |
583 | ||
8ce73f3a | 584 | memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ |
c2acea8e JB |
585 | if (cmd->flags & CMD_WANT_SKB) |
586 | out_meta->source = cmd; | |
fd4abac5 | 587 | |
4ce7cc2b | 588 | /* set up the header */ |
fd4abac5 | 589 | |
4ce7cc2b | 590 | out_cmd->hdr.cmd = cmd->id; |
fd4abac5 | 591 | out_cmd->hdr.flags = 0; |
cefeaa5f | 592 | out_cmd->hdr.sequence = |
c6f600fc | 593 | cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | |
cefeaa5f | 594 | INDEX_TO_SEQ(q->write_ptr)); |
4ce7cc2b JB |
595 | |
596 | /* and copy the data that needs to be copied */ | |
597 | ||
132f98c2 | 598 | cmd_dest = out_cmd->payload; |
4ce7cc2b JB |
599 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { |
600 | if (!cmd->len[i]) | |
601 | continue; | |
602 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) | |
603 | break; | |
604 | memcpy(cmd_dest, cmd->data[i], cmd->len[i]); | |
605 | cmd_dest += cmd->len[i]; | |
ded2ae7c | 606 | } |
4ce7cc2b | 607 | |
6d8f6eeb | 608 | IWL_DEBUG_HC(trans, "Sending command %s (#%x), seq: 0x%04X, " |
4ce7cc2b JB |
609 | "%d bytes at %d[%d]:%d\n", |
610 | get_cmd_string(out_cmd->hdr.cmd), | |
611 | out_cmd->hdr.cmd, | |
612 | le16_to_cpu(out_cmd->hdr.sequence), cmd_size, | |
c6f600fc | 613 | q->write_ptr, idx, trans_pcie->cmd_queue); |
4ce7cc2b | 614 | |
1042db2a | 615 | phys_addr = dma_map_single(trans->dev, &out_cmd->hdr, copy_size, |
795414db | 616 | DMA_BIDIRECTIONAL); |
1042db2a | 617 | if (unlikely(dma_mapping_error(trans->dev, phys_addr))) { |
2c46f72e JB |
618 | idx = -ENOMEM; |
619 | goto out; | |
620 | } | |
621 | ||
2e724443 | 622 | dma_unmap_addr_set(out_meta, mapping, phys_addr); |
4ce7cc2b JB |
623 | dma_unmap_len_set(out_meta, len, copy_size); |
624 | ||
6d8f6eeb EG |
625 | iwlagn_txq_attach_buf_to_tfd(trans, txq, |
626 | phys_addr, copy_size, 1); | |
4ce7cc2b JB |
627 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING |
628 | trace_bufs[0] = &out_cmd->hdr; | |
629 | trace_lens[0] = copy_size; | |
630 | trace_idx = 1; | |
631 | #endif | |
632 | ||
633 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
634 | if (!cmd->len[i]) | |
635 | continue; | |
636 | if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY)) | |
637 | continue; | |
1042db2a | 638 | phys_addr = dma_map_single(trans->dev, |
6d8f6eeb | 639 | (void *)cmd->data[i], |
3be3fdb5 | 640 | cmd->len[i], DMA_BIDIRECTIONAL); |
1042db2a | 641 | if (dma_mapping_error(trans->dev, phys_addr)) { |
6d8f6eeb | 642 | iwlagn_unmap_tfd(trans, out_meta, |
e815407d | 643 | &txq->tfds[q->write_ptr], |
3be3fdb5 | 644 | DMA_BIDIRECTIONAL); |
4ce7cc2b JB |
645 | idx = -ENOMEM; |
646 | goto out; | |
647 | } | |
648 | ||
6d8f6eeb | 649 | iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr, |
4ce7cc2b JB |
650 | cmd->len[i], 0); |
651 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
652 | trace_bufs[trace_idx] = cmd->data[i]; | |
653 | trace_lens[trace_idx] = cmd->len[i]; | |
654 | trace_idx++; | |
655 | #endif | |
656 | } | |
df833b1d | 657 | |
afaf6b57 | 658 | out_meta->flags = cmd->flags; |
2c46f72e JB |
659 | |
660 | txq->need_update = 1; | |
661 | ||
4ce7cc2b JB |
662 | /* check that tracing gets all possible blocks */ |
663 | BUILD_BUG_ON(IWL_MAX_CMD_TFDS + 1 != 3); | |
664 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
6c1011e1 | 665 | trace_iwlwifi_dev_hcmd(trans->dev, cmd->flags, |
4ce7cc2b JB |
666 | trace_bufs[0], trace_lens[0], |
667 | trace_bufs[1], trace_lens[1], | |
668 | trace_bufs[2], trace_lens[2]); | |
669 | #endif | |
df833b1d | 670 | |
7c5ba4a8 JB |
671 | /* start timer if queue currently empty */ |
672 | if (q->read_ptr == q->write_ptr && trans_pcie->wd_timeout) | |
673 | mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout); | |
674 | ||
fd4abac5 TW |
675 | /* Increment and update queue's write index */ |
676 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
fd656935 | 677 | iwl_txq_update_write_ptr(trans, txq); |
fd4abac5 | 678 | |
2c46f72e | 679 | out: |
015c15e1 | 680 | spin_unlock_bh(&txq->lock); |
7bfedc59 | 681 | return idx; |
fd4abac5 TW |
682 | } |
683 | ||
7c5ba4a8 JB |
684 | static inline void iwl_queue_progress(struct iwl_trans_pcie *trans_pcie, |
685 | struct iwl_tx_queue *txq) | |
686 | { | |
687 | if (!trans_pcie->wd_timeout) | |
688 | return; | |
689 | ||
690 | /* | |
691 | * if empty delete timer, otherwise move timer forward | |
692 | * since we're making progress on this queue | |
693 | */ | |
694 | if (txq->q.read_ptr == txq->q.write_ptr) | |
695 | del_timer(&txq->stuck_timer); | |
696 | else | |
697 | mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout); | |
698 | } | |
699 | ||
17b88929 TW |
700 | /** |
701 | * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd | |
702 | * | |
703 | * When FW advances 'R' index, all entries between old and new 'R' index | |
704 | * need to be reclaimed. As result, some free space forms. If there is | |
705 | * enough free space (> low mark), wake the stack that feeds us. | |
706 | */ | |
3e10caeb EG |
707 | static void iwl_hcmd_queue_reclaim(struct iwl_trans *trans, int txq_id, |
708 | int idx) | |
17b88929 | 709 | { |
3e10caeb | 710 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
8ad71bef | 711 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; |
17b88929 TW |
712 | struct iwl_queue *q = &txq->q; |
713 | int nfreed = 0; | |
714 | ||
015c15e1 JB |
715 | lockdep_assert_held(&txq->lock); |
716 | ||
499b1883 | 717 | if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) { |
3e10caeb | 718 | IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), " |
2e5d04da DH |
719 | "index %d is out of range [0-%d] %d %d.\n", __func__, |
720 | txq_id, idx, q->n_bd, q->write_ptr, q->read_ptr); | |
17b88929 TW |
721 | return; |
722 | } | |
723 | ||
499b1883 TW |
724 | for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; |
725 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
17b88929 | 726 | |
499b1883 | 727 | if (nfreed++ > 0) { |
3e10caeb | 728 | IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", idx, |
17b88929 | 729 | q->write_ptr, q->read_ptr); |
bcb9321c | 730 | iwl_op_mode_nic_error(trans->op_mode); |
17b88929 | 731 | } |
da99c4b6 | 732 | |
17b88929 | 733 | } |
7c5ba4a8 JB |
734 | |
735 | iwl_queue_progress(trans_pcie, txq); | |
17b88929 TW |
736 | } |
737 | ||
738 | /** | |
739 | * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them | |
740 | * @rxb: Rx buffer to reclaim | |
247c61d6 EG |
741 | * @handler_status: return value of the handler of the command |
742 | * (put in setup_rx_handlers) | |
17b88929 TW |
743 | * |
744 | * If an Rx buffer has an async callback associated with it the callback | |
745 | * will be executed. The attached skb (if present) will only be freed | |
746 | * if the callback returns 1 | |
747 | */ | |
48a2d66f | 748 | void iwl_tx_cmd_complete(struct iwl_trans *trans, struct iwl_rx_cmd_buffer *rxb, |
247c61d6 | 749 | int handler_status) |
17b88929 | 750 | { |
2f301227 | 751 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
17b88929 TW |
752 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
753 | int txq_id = SEQ_TO_QUEUE(sequence); | |
754 | int index = SEQ_TO_INDEX(sequence); | |
17b88929 | 755 | int cmd_index; |
c2acea8e JB |
756 | struct iwl_device_cmd *cmd; |
757 | struct iwl_cmd_meta *meta; | |
8ad71bef | 758 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
c6f600fc | 759 | struct iwl_tx_queue *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
17b88929 TW |
760 | |
761 | /* If a Tx command is being handled and it isn't in the actual | |
762 | * command queue then there a command routing bug has been introduced | |
763 | * in the queue management code. */ | |
c6f600fc | 764 | if (WARN(txq_id != trans_pcie->cmd_queue, |
13bb9483 | 765 | "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", |
c6f600fc MV |
766 | txq_id, trans_pcie->cmd_queue, sequence, |
767 | trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr, | |
768 | trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) { | |
3e10caeb | 769 | iwl_print_hex_error(trans, pkt, 32); |
55d6a3cd | 770 | return; |
01ef9323 | 771 | } |
17b88929 | 772 | |
015c15e1 JB |
773 | spin_lock(&txq->lock); |
774 | ||
4ce7cc2b | 775 | cmd_index = get_cmd_index(&txq->q, index); |
dd487449 ZY |
776 | cmd = txq->cmd[cmd_index]; |
777 | meta = &txq->meta[cmd_index]; | |
17b88929 | 778 | |
6d8f6eeb EG |
779 | iwlagn_unmap_tfd(trans, meta, &txq->tfds[index], |
780 | DMA_BIDIRECTIONAL); | |
c33de625 | 781 | |
17b88929 | 782 | /* Input error checking is done when commands are added to queue. */ |
c2acea8e | 783 | if (meta->flags & CMD_WANT_SKB) { |
48a2d66f | 784 | struct page *p = rxb_steal_page(rxb); |
65b94a4a | 785 | |
65b94a4a JB |
786 | meta->source->resp_pkt = pkt; |
787 | meta->source->_rx_page_addr = (unsigned long)page_address(p); | |
b2cf410c | 788 | meta->source->_rx_page_order = trans_pcie->rx_page_order; |
247c61d6 | 789 | meta->source->handler_status = handler_status; |
247c61d6 | 790 | } |
2624e96c | 791 | |
3e10caeb | 792 | iwl_hcmd_queue_reclaim(trans, txq_id, index); |
17b88929 | 793 | |
c2acea8e | 794 | if (!(meta->flags & CMD_ASYNC)) { |
74fda971 | 795 | if (!test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) { |
05c89b91 WYG |
796 | IWL_WARN(trans, |
797 | "HCMD_ACTIVE already clear for command %s\n", | |
798 | get_cmd_string(cmd->hdr.cmd)); | |
799 | } | |
74fda971 | 800 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); |
6d8f6eeb | 801 | IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", |
d2dfe6df | 802 | get_cmd_string(cmd->hdr.cmd)); |
69a10b29 | 803 | wake_up(&trans->wait_command_queue); |
17b88929 | 804 | } |
3598e177 | 805 | |
dd487449 | 806 | meta->flags = 0; |
3598e177 | 807 | |
015c15e1 | 808 | spin_unlock(&txq->lock); |
17b88929 | 809 | } |
253a634c | 810 | |
253a634c EG |
811 | #define HOST_COMPLETE_TIMEOUT (2 * HZ) |
812 | ||
6d8f6eeb | 813 | static int iwl_send_cmd_async(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c EG |
814 | { |
815 | int ret; | |
816 | ||
817 | /* An asynchronous command can not expect an SKB to be set. */ | |
818 | if (WARN_ON(cmd->flags & CMD_WANT_SKB)) | |
819 | return -EINVAL; | |
820 | ||
253a634c | 821 | |
6d8f6eeb | 822 | ret = iwl_enqueue_hcmd(trans, cmd); |
253a634c | 823 | if (ret < 0) { |
721c32f7 | 824 | IWL_ERR(trans, |
b36b110c | 825 | "Error sending %s: enqueue_hcmd failed: %d\n", |
253a634c EG |
826 | get_cmd_string(cmd->id), ret); |
827 | return ret; | |
828 | } | |
829 | return 0; | |
830 | } | |
831 | ||
6d8f6eeb | 832 | static int iwl_send_cmd_sync(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c | 833 | { |
8ad71bef | 834 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
253a634c EG |
835 | int cmd_idx; |
836 | int ret; | |
837 | ||
6d8f6eeb | 838 | IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", |
253a634c EG |
839 | get_cmd_string(cmd->id)); |
840 | ||
2cc39c94 | 841 | if (WARN_ON(test_and_set_bit(STATUS_HCMD_ACTIVE, |
74fda971 | 842 | &trans_pcie->status))) { |
2cc39c94 JB |
843 | IWL_ERR(trans, "Command %s: a command is already active!\n", |
844 | get_cmd_string(cmd->id)); | |
845 | return -EIO; | |
846 | } | |
847 | ||
6d8f6eeb | 848 | IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", |
253a634c EG |
849 | get_cmd_string(cmd->id)); |
850 | ||
6d8f6eeb | 851 | cmd_idx = iwl_enqueue_hcmd(trans, cmd); |
253a634c EG |
852 | if (cmd_idx < 0) { |
853 | ret = cmd_idx; | |
74fda971 | 854 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); |
721c32f7 | 855 | IWL_ERR(trans, |
b36b110c | 856 | "Error sending %s: enqueue_hcmd failed: %d\n", |
253a634c EG |
857 | get_cmd_string(cmd->id), ret); |
858 | return ret; | |
859 | } | |
860 | ||
69a10b29 | 861 | ret = wait_event_timeout(trans->wait_command_queue, |
74fda971 | 862 | !test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status), |
253a634c EG |
863 | HOST_COMPLETE_TIMEOUT); |
864 | if (!ret) { | |
74fda971 | 865 | if (test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) { |
d10630af | 866 | struct iwl_tx_queue *txq = |
c6f600fc | 867 | &trans_pcie->txq[trans_pcie->cmd_queue]; |
d10630af WYG |
868 | struct iwl_queue *q = &txq->q; |
869 | ||
721c32f7 | 870 | IWL_ERR(trans, |
253a634c EG |
871 | "Error sending %s: time out after %dms.\n", |
872 | get_cmd_string(cmd->id), | |
873 | jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); | |
874 | ||
721c32f7 | 875 | IWL_ERR(trans, |
d10630af WYG |
876 | "Current CMD queue read_ptr %d write_ptr %d\n", |
877 | q->read_ptr, q->write_ptr); | |
878 | ||
74fda971 | 879 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); |
6d8f6eeb | 880 | IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command" |
253a634c EG |
881 | "%s\n", get_cmd_string(cmd->id)); |
882 | ret = -ETIMEDOUT; | |
883 | goto cancel; | |
884 | } | |
885 | } | |
886 | ||
65b94a4a | 887 | if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) { |
6d8f6eeb | 888 | IWL_ERR(trans, "Error: Response NULL in '%s'\n", |
253a634c EG |
889 | get_cmd_string(cmd->id)); |
890 | ret = -EIO; | |
891 | goto cancel; | |
892 | } | |
893 | ||
894 | return 0; | |
895 | ||
896 | cancel: | |
897 | if (cmd->flags & CMD_WANT_SKB) { | |
898 | /* | |
899 | * Cancel the CMD_WANT_SKB flag for the cmd in the | |
900 | * TX cmd queue. Otherwise in case the cmd comes | |
901 | * in later, it will possibly set an invalid | |
902 | * address (cmd->meta.source). | |
903 | */ | |
c6f600fc | 904 | trans_pcie->txq[trans_pcie->cmd_queue].meta[cmd_idx].flags &= |
253a634c EG |
905 | ~CMD_WANT_SKB; |
906 | } | |
9cac4943 | 907 | |
65b94a4a JB |
908 | if (cmd->resp_pkt) { |
909 | iwl_free_resp(cmd); | |
910 | cmd->resp_pkt = NULL; | |
253a634c EG |
911 | } |
912 | ||
913 | return ret; | |
914 | } | |
915 | ||
6d8f6eeb | 916 | int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c EG |
917 | { |
918 | if (cmd->flags & CMD_ASYNC) | |
6d8f6eeb | 919 | return iwl_send_cmd_async(trans, cmd); |
253a634c | 920 | |
6d8f6eeb | 921 | return iwl_send_cmd_sync(trans, cmd); |
253a634c EG |
922 | } |
923 | ||
a0eaad71 | 924 | /* Frees buffers until index _not_ inclusive */ |
464021ff EG |
925 | int iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index, |
926 | struct sk_buff_head *skbs) | |
a0eaad71 | 927 | { |
8ad71bef EG |
928 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
929 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; | |
a0eaad71 | 930 | struct iwl_queue *q = &txq->q; |
a0eaad71 | 931 | int last_to_free; |
464021ff | 932 | int freed = 0; |
a0eaad71 | 933 | |
39644e9a | 934 | /* This function is not meant to release cmd queue*/ |
c6f600fc | 935 | if (WARN_ON(txq_id == trans_pcie->cmd_queue)) |
39644e9a EG |
936 | return 0; |
937 | ||
015c15e1 JB |
938 | lockdep_assert_held(&txq->lock); |
939 | ||
a0eaad71 EG |
940 | /*Since we free until index _not_ inclusive, the one before index is |
941 | * the last we will free. This one must be used */ | |
942 | last_to_free = iwl_queue_dec_wrap(index, q->n_bd); | |
943 | ||
944 | if ((index >= q->n_bd) || | |
945 | (iwl_queue_used(q, last_to_free) == 0)) { | |
946 | IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), " | |
947 | "last_to_free %d is out of range [0-%d] %d %d.\n", | |
948 | __func__, txq_id, last_to_free, q->n_bd, | |
949 | q->write_ptr, q->read_ptr); | |
464021ff | 950 | return 0; |
a0eaad71 EG |
951 | } |
952 | ||
a0eaad71 | 953 | if (WARN_ON(!skb_queue_empty(skbs))) |
464021ff | 954 | return 0; |
a0eaad71 EG |
955 | |
956 | for (; | |
957 | q->read_ptr != index; | |
958 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
959 | ||
2c452297 | 960 | if (WARN_ON_ONCE(txq->skbs[txq->q.read_ptr] == NULL)) |
a0eaad71 EG |
961 | continue; |
962 | ||
2c452297 | 963 | __skb_queue_tail(skbs, txq->skbs[txq->q.read_ptr]); |
a0eaad71 | 964 | |
2c452297 | 965 | txq->skbs[txq->q.read_ptr] = NULL; |
a0eaad71 | 966 | |
6d8f6eeb | 967 | iwlagn_txq_inval_byte_cnt_tbl(trans, txq); |
a0eaad71 | 968 | |
39644e9a | 969 | iwlagn_txq_free_tfd(trans, txq, txq->q.read_ptr, DMA_TO_DEVICE); |
464021ff | 970 | freed++; |
a0eaad71 | 971 | } |
7c5ba4a8 JB |
972 | |
973 | iwl_queue_progress(trans_pcie, txq); | |
974 | ||
464021ff | 975 | return freed; |
a0eaad71 | 976 | } |