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ab697a9f EG |
1 | /****************************************************************************** |
2 | * | |
3 | * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. | |
4 | * | |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
25 | * Intel Linux Wireless <ilw@linux.intel.com> | |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
27 | * | |
28 | *****************************************************************************/ | |
29 | #include <linux/sched.h> | |
30 | #include <linux/wait.h> | |
1a361cd8 | 31 | #include <linux/gfp.h> |
ab697a9f EG |
32 | |
33 | #include "iwl-dev.h" | |
34 | #include "iwl-agn.h" | |
35 | #include "iwl-core.h" | |
36 | #include "iwl-io.h" | |
37 | #include "iwl-helpers.h" | |
38 | #include "iwl-trans-int-pcie.h" | |
39 | ||
40 | /****************************************************************************** | |
41 | * | |
42 | * RX path functions | |
43 | * | |
44 | ******************************************************************************/ | |
45 | ||
46 | /* | |
47 | * Rx theory of operation | |
48 | * | |
49 | * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs), | |
50 | * each of which point to Receive Buffers to be filled by the NIC. These get | |
51 | * used not only for Rx frames, but for any command response or notification | |
52 | * from the NIC. The driver and NIC manage the Rx buffers by means | |
53 | * of indexes into the circular buffer. | |
54 | * | |
55 | * Rx Queue Indexes | |
56 | * The host/firmware share two index registers for managing the Rx buffers. | |
57 | * | |
58 | * The READ index maps to the first position that the firmware may be writing | |
59 | * to -- the driver can read up to (but not including) this position and get | |
60 | * good data. | |
61 | * The READ index is managed by the firmware once the card is enabled. | |
62 | * | |
63 | * The WRITE index maps to the last position the driver has read from -- the | |
64 | * position preceding WRITE is the last slot the firmware can place a packet. | |
65 | * | |
66 | * The queue is empty (no good data) if WRITE = READ - 1, and is full if | |
67 | * WRITE = READ. | |
68 | * | |
69 | * During initialization, the host sets up the READ queue position to the first | |
70 | * INDEX position, and WRITE to the last (READ - 1 wrapped) | |
71 | * | |
72 | * When the firmware places a packet in a buffer, it will advance the READ index | |
73 | * and fire the RX interrupt. The driver can then query the READ index and | |
74 | * process as many packets as possible, moving the WRITE index forward as it | |
75 | * resets the Rx queue buffers with new memory. | |
76 | * | |
77 | * The management in the driver is as follows: | |
78 | * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When | |
79 | * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled | |
80 | * to replenish the iwl->rxq->rx_free. | |
81 | * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the | |
82 | * iwl->rxq is replenished and the READ INDEX is updated (updating the | |
83 | * 'processed' and 'read' driver indexes as well) | |
84 | * + A received packet is processed and handed to the kernel network stack, | |
85 | * detached from the iwl->rxq. The driver 'processed' index is updated. | |
86 | * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free | |
87 | * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ | |
88 | * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there | |
89 | * were enough free buffers and RX_STALLED is set it is cleared. | |
90 | * | |
91 | * | |
92 | * Driver sequence: | |
93 | * | |
94 | * iwl_rx_queue_alloc() Allocates rx_free | |
95 | * iwl_rx_replenish() Replenishes rx_free list from rx_used, and calls | |
96 | * iwl_rx_queue_restock | |
97 | * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx | |
98 | * queue, updates firmware pointers, and updates | |
99 | * the WRITE index. If insufficient rx_free buffers | |
100 | * are available, schedules iwl_rx_replenish | |
101 | * | |
102 | * -- enable interrupts -- | |
103 | * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the | |
104 | * READ INDEX, detaching the SKB from the pool. | |
105 | * Moves the packet buffer from queue to rx_used. | |
106 | * Calls iwl_rx_queue_restock to refill any empty | |
107 | * slots. | |
108 | * ... | |
109 | * | |
110 | */ | |
111 | ||
112 | /** | |
113 | * iwl_rx_queue_space - Return number of free slots available in queue. | |
114 | */ | |
115 | static int iwl_rx_queue_space(const struct iwl_rx_queue *q) | |
116 | { | |
117 | int s = q->read - q->write; | |
118 | if (s <= 0) | |
119 | s += RX_QUEUE_SIZE; | |
120 | /* keep some buffer to not confuse full and empty queue */ | |
121 | s -= 2; | |
122 | if (s < 0) | |
123 | s = 0; | |
124 | return s; | |
125 | } | |
126 | ||
127 | /** | |
128 | * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue | |
129 | */ | |
5a878bf6 | 130 | void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans, |
ab697a9f EG |
131 | struct iwl_rx_queue *q) |
132 | { | |
5a878bf6 | 133 | struct iwl_priv *priv = priv(trans); |
ab697a9f EG |
134 | unsigned long flags; |
135 | u32 reg; | |
136 | ||
137 | spin_lock_irqsave(&q->lock, flags); | |
138 | ||
139 | if (q->need_update == 0) | |
140 | goto exit_unlock; | |
141 | ||
142 | if (priv->cfg->base_params->shadow_reg_enable) { | |
143 | /* shadow register enabled */ | |
144 | /* Device expects a multiple of 8 */ | |
145 | q->write_actual = (q->write & ~0x7); | |
146 | iwl_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write_actual); | |
147 | } else { | |
148 | /* If power-saving is in use, make sure device is awake */ | |
5a878bf6 | 149 | if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) { |
ab697a9f EG |
150 | reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); |
151 | ||
152 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
5a878bf6 | 153 | IWL_DEBUG_INFO(trans, |
ab697a9f EG |
154 | "Rx queue requesting wakeup," |
155 | " GP1 = 0x%x\n", reg); | |
156 | iwl_set_bit(priv, CSR_GP_CNTRL, | |
157 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
158 | goto exit_unlock; | |
159 | } | |
160 | ||
161 | q->write_actual = (q->write & ~0x7); | |
162 | iwl_write_direct32(priv, FH_RSCSR_CHNL0_WPTR, | |
163 | q->write_actual); | |
164 | ||
165 | /* Else device is assumed to be awake */ | |
166 | } else { | |
167 | /* Device expects a multiple of 8 */ | |
168 | q->write_actual = (q->write & ~0x7); | |
169 | iwl_write_direct32(priv, FH_RSCSR_CHNL0_WPTR, | |
170 | q->write_actual); | |
171 | } | |
172 | } | |
173 | q->need_update = 0; | |
174 | ||
175 | exit_unlock: | |
176 | spin_unlock_irqrestore(&q->lock, flags); | |
177 | } | |
178 | ||
179 | /** | |
180 | * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr | |
181 | */ | |
5a878bf6 | 182 | static inline __le32 iwlagn_dma_addr2rbd_ptr(dma_addr_t dma_addr) |
ab697a9f EG |
183 | { |
184 | return cpu_to_le32((u32)(dma_addr >> 8)); | |
185 | } | |
186 | ||
187 | /** | |
188 | * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool | |
189 | * | |
190 | * If there are slots in the RX queue that need to be restocked, | |
191 | * and we have free pre-allocated buffers, fill the ranks as much | |
192 | * as we can, pulling from rx_free. | |
193 | * | |
194 | * This moves the 'write' index forward to catch up with 'processed', and | |
195 | * also updates the memory address in the firmware to reference the new | |
196 | * target buffer. | |
197 | */ | |
5a878bf6 | 198 | static void iwlagn_rx_queue_restock(struct iwl_trans *trans) |
ab697a9f | 199 | { |
5a878bf6 EG |
200 | struct iwl_trans_pcie *trans_pcie = |
201 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
202 | ||
203 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
ab697a9f EG |
204 | struct list_head *element; |
205 | struct iwl_rx_mem_buffer *rxb; | |
206 | unsigned long flags; | |
207 | ||
208 | spin_lock_irqsave(&rxq->lock, flags); | |
209 | while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) { | |
210 | /* The overwritten rxb must be a used one */ | |
211 | rxb = rxq->queue[rxq->write]; | |
212 | BUG_ON(rxb && rxb->page); | |
213 | ||
214 | /* Get next free Rx buffer, remove from free list */ | |
215 | element = rxq->rx_free.next; | |
216 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); | |
217 | list_del(element); | |
218 | ||
219 | /* Point to Rx buffer via next RBD in circular buffer */ | |
5a878bf6 | 220 | rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(rxb->page_dma); |
ab697a9f EG |
221 | rxq->queue[rxq->write] = rxb; |
222 | rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; | |
223 | rxq->free_count--; | |
224 | } | |
225 | spin_unlock_irqrestore(&rxq->lock, flags); | |
226 | /* If the pre-allocated buffer pool is dropping low, schedule to | |
227 | * refill it */ | |
228 | if (rxq->free_count <= RX_LOW_WATERMARK) | |
5a878bf6 | 229 | queue_work(trans->shrd->workqueue, &trans_pcie->rx_replenish); |
ab697a9f EG |
230 | |
231 | ||
232 | /* If we've added more space for the firmware to place data, tell it. | |
233 | * Increment device's write pointer in multiples of 8. */ | |
234 | if (rxq->write_actual != (rxq->write & ~0x7)) { | |
235 | spin_lock_irqsave(&rxq->lock, flags); | |
236 | rxq->need_update = 1; | |
237 | spin_unlock_irqrestore(&rxq->lock, flags); | |
5a878bf6 | 238 | iwl_rx_queue_update_write_ptr(trans, rxq); |
ab697a9f EG |
239 | } |
240 | } | |
241 | ||
242 | /** | |
243 | * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free | |
244 | * | |
245 | * When moving to rx_free an SKB is allocated for the slot. | |
246 | * | |
247 | * Also restock the Rx queue via iwl_rx_queue_restock. | |
248 | * This is called as a scheduled work item (except for during initialization) | |
249 | */ | |
5a878bf6 | 250 | static void iwlagn_rx_allocate(struct iwl_trans *trans, gfp_t priority) |
ab697a9f | 251 | { |
5a878bf6 EG |
252 | struct iwl_trans_pcie *trans_pcie = |
253 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
254 | ||
255 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
ab697a9f EG |
256 | struct list_head *element; |
257 | struct iwl_rx_mem_buffer *rxb; | |
258 | struct page *page; | |
259 | unsigned long flags; | |
260 | gfp_t gfp_mask = priority; | |
261 | ||
262 | while (1) { | |
263 | spin_lock_irqsave(&rxq->lock, flags); | |
264 | if (list_empty(&rxq->rx_used)) { | |
265 | spin_unlock_irqrestore(&rxq->lock, flags); | |
266 | return; | |
267 | } | |
268 | spin_unlock_irqrestore(&rxq->lock, flags); | |
269 | ||
270 | if (rxq->free_count > RX_LOW_WATERMARK) | |
271 | gfp_mask |= __GFP_NOWARN; | |
272 | ||
5a878bf6 | 273 | if (hw_params(trans).rx_page_order > 0) |
ab697a9f EG |
274 | gfp_mask |= __GFP_COMP; |
275 | ||
276 | /* Alloc a new receive buffer */ | |
d6189124 | 277 | page = alloc_pages(gfp_mask, |
5a878bf6 | 278 | hw_params(trans).rx_page_order); |
ab697a9f EG |
279 | if (!page) { |
280 | if (net_ratelimit()) | |
5a878bf6 | 281 | IWL_DEBUG_INFO(trans, "alloc_pages failed, " |
d6189124 | 282 | "order: %d\n", |
5a878bf6 | 283 | hw_params(trans).rx_page_order); |
ab697a9f EG |
284 | |
285 | if ((rxq->free_count <= RX_LOW_WATERMARK) && | |
286 | net_ratelimit()) | |
5a878bf6 | 287 | IWL_CRIT(trans, "Failed to alloc_pages with %s." |
ab697a9f EG |
288 | "Only %u free buffers remaining.\n", |
289 | priority == GFP_ATOMIC ? | |
290 | "GFP_ATOMIC" : "GFP_KERNEL", | |
291 | rxq->free_count); | |
292 | /* We don't reschedule replenish work here -- we will | |
293 | * call the restock method and if it still needs | |
294 | * more buffers it will schedule replenish */ | |
295 | return; | |
296 | } | |
297 | ||
298 | spin_lock_irqsave(&rxq->lock, flags); | |
299 | ||
300 | if (list_empty(&rxq->rx_used)) { | |
301 | spin_unlock_irqrestore(&rxq->lock, flags); | |
5a878bf6 | 302 | __free_pages(page, hw_params(trans).rx_page_order); |
ab697a9f EG |
303 | return; |
304 | } | |
305 | element = rxq->rx_used.next; | |
306 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); | |
307 | list_del(element); | |
308 | ||
309 | spin_unlock_irqrestore(&rxq->lock, flags); | |
310 | ||
311 | BUG_ON(rxb->page); | |
312 | rxb->page = page; | |
313 | /* Get physical address of the RB */ | |
5a878bf6 EG |
314 | rxb->page_dma = dma_map_page(bus(trans)->dev, page, 0, |
315 | PAGE_SIZE << hw_params(trans).rx_page_order, | |
ab697a9f EG |
316 | DMA_FROM_DEVICE); |
317 | /* dma address must be no more than 36 bits */ | |
318 | BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36)); | |
319 | /* and also 256 byte aligned! */ | |
320 | BUG_ON(rxb->page_dma & DMA_BIT_MASK(8)); | |
321 | ||
322 | spin_lock_irqsave(&rxq->lock, flags); | |
323 | ||
324 | list_add_tail(&rxb->list, &rxq->rx_free); | |
325 | rxq->free_count++; | |
326 | ||
327 | spin_unlock_irqrestore(&rxq->lock, flags); | |
328 | } | |
329 | } | |
330 | ||
5a878bf6 | 331 | void iwlagn_rx_replenish(struct iwl_trans *trans) |
ab697a9f EG |
332 | { |
333 | unsigned long flags; | |
334 | ||
5a878bf6 | 335 | iwlagn_rx_allocate(trans, GFP_KERNEL); |
ab697a9f | 336 | |
5a878bf6 EG |
337 | spin_lock_irqsave(&trans->shrd->lock, flags); |
338 | iwlagn_rx_queue_restock(trans); | |
339 | spin_unlock_irqrestore(&trans->shrd->lock, flags); | |
ab697a9f EG |
340 | } |
341 | ||
5a878bf6 | 342 | static void iwlagn_rx_replenish_now(struct iwl_trans *trans) |
ab697a9f | 343 | { |
5a878bf6 | 344 | iwlagn_rx_allocate(trans, GFP_ATOMIC); |
ab697a9f | 345 | |
5a878bf6 | 346 | iwlagn_rx_queue_restock(trans); |
ab697a9f EG |
347 | } |
348 | ||
349 | void iwl_bg_rx_replenish(struct work_struct *data) | |
350 | { | |
5a878bf6 EG |
351 | struct iwl_trans_pcie *trans_pcie = |
352 | container_of(data, struct iwl_trans_pcie, rx_replenish); | |
353 | struct iwl_trans *trans = trans_pcie->trans; | |
ab697a9f | 354 | |
5a878bf6 | 355 | if (test_bit(STATUS_EXIT_PENDING, &trans->shrd->status)) |
ab697a9f EG |
356 | return; |
357 | ||
5a878bf6 EG |
358 | mutex_lock(&trans->shrd->mutex); |
359 | iwlagn_rx_replenish(trans); | |
360 | mutex_unlock(&trans->shrd->mutex); | |
ab697a9f EG |
361 | } |
362 | ||
363 | /** | |
364 | * iwl_rx_handle - Main entry function for receiving responses from uCode | |
365 | * | |
366 | * Uses the priv->rx_handlers callback function array to invoke | |
367 | * the appropriate handlers, including command responses, | |
368 | * frame-received notifications, and other notifications. | |
369 | */ | |
5a878bf6 | 370 | static void iwl_rx_handle(struct iwl_trans *trans) |
ab697a9f EG |
371 | { |
372 | struct iwl_rx_mem_buffer *rxb; | |
373 | struct iwl_rx_packet *pkt; | |
5a878bf6 EG |
374 | struct iwl_trans_pcie *trans_pcie = |
375 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
376 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
ab697a9f EG |
377 | u32 r, i; |
378 | int reclaim; | |
379 | unsigned long flags; | |
380 | u8 fill_rx = 0; | |
381 | u32 count = 8; | |
382 | int total_empty; | |
383 | ||
384 | /* uCode's read index (stored in shared DRAM) indicates the last Rx | |
385 | * buffer that the driver may process (last buffer filled by ucode). */ | |
386 | r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; | |
387 | i = rxq->read; | |
388 | ||
389 | /* Rx interrupt, but nothing sent from uCode */ | |
390 | if (i == r) | |
5a878bf6 | 391 | IWL_DEBUG_RX(trans, "r = %d, i = %d\n", r, i); |
ab697a9f EG |
392 | |
393 | /* calculate total frames need to be restock after handling RX */ | |
394 | total_empty = r - rxq->write_actual; | |
395 | if (total_empty < 0) | |
396 | total_empty += RX_QUEUE_SIZE; | |
397 | ||
398 | if (total_empty > (RX_QUEUE_SIZE / 2)) | |
399 | fill_rx = 1; | |
400 | ||
401 | while (i != r) { | |
402 | int len; | |
403 | ||
404 | rxb = rxq->queue[i]; | |
405 | ||
406 | /* If an RXB doesn't have a Rx queue slot associated with it, | |
407 | * then a bug has been introduced in the queue refilling | |
408 | * routines -- catch it here */ | |
409 | if (WARN_ON(rxb == NULL)) { | |
410 | i = (i + 1) & RX_QUEUE_MASK; | |
411 | continue; | |
412 | } | |
413 | ||
414 | rxq->queue[i] = NULL; | |
415 | ||
5a878bf6 EG |
416 | dma_unmap_page(bus(trans)->dev, rxb->page_dma, |
417 | PAGE_SIZE << hw_params(trans).rx_page_order, | |
ab697a9f EG |
418 | DMA_FROM_DEVICE); |
419 | pkt = rxb_addr(rxb); | |
420 | ||
5a878bf6 | 421 | IWL_DEBUG_RX(trans, "r = %d, i = %d, %s, 0x%02x\n", r, |
ab697a9f EG |
422 | i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); |
423 | ||
424 | len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; | |
425 | len += sizeof(u32); /* account for status word */ | |
5a878bf6 | 426 | trace_iwlwifi_dev_rx(priv(trans), pkt, len); |
ab697a9f EG |
427 | |
428 | /* Reclaim a command buffer only if this packet is a response | |
429 | * to a (driver-originated) command. | |
430 | * If the packet (e.g. Rx frame) originated from uCode, | |
431 | * there is no command buffer to reclaim. | |
432 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
433 | * but apparently a few don't get set; catch them here. */ | |
434 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
435 | (pkt->hdr.cmd != REPLY_RX_PHY_CMD) && | |
436 | (pkt->hdr.cmd != REPLY_RX) && | |
437 | (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) && | |
438 | (pkt->hdr.cmd != REPLY_COMPRESSED_BA) && | |
439 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && | |
440 | (pkt->hdr.cmd != REPLY_TX); | |
441 | ||
5a878bf6 | 442 | iwl_rx_dispatch(priv(trans), rxb); |
ab697a9f EG |
443 | |
444 | /* | |
445 | * XXX: After here, we should always check rxb->page | |
446 | * against NULL before touching it or its virtual | |
447 | * memory (pkt). Because some rx_handler might have | |
448 | * already taken or freed the pages. | |
449 | */ | |
450 | ||
451 | if (reclaim) { | |
452 | /* Invoke any callbacks, transfer the buffer to caller, | |
453 | * and fire off the (possibly) blocking | |
e6bb4c9c | 454 | * iwl_trans_send_cmd() |
ab697a9f EG |
455 | * as we reclaim the driver command queue */ |
456 | if (rxb->page) | |
5a878bf6 | 457 | iwl_tx_cmd_complete(priv(trans), rxb); |
ab697a9f | 458 | else |
5a878bf6 | 459 | IWL_WARN(trans, "Claim null rxb?\n"); |
ab697a9f EG |
460 | } |
461 | ||
462 | /* Reuse the page if possible. For notification packets and | |
463 | * SKBs that fail to Rx correctly, add them back into the | |
464 | * rx_free list for reuse later. */ | |
465 | spin_lock_irqsave(&rxq->lock, flags); | |
466 | if (rxb->page != NULL) { | |
5a878bf6 | 467 | rxb->page_dma = dma_map_page(bus(trans)->dev, rxb->page, |
d6189124 | 468 | 0, PAGE_SIZE << |
5a878bf6 | 469 | hw_params(trans).rx_page_order, |
ab697a9f EG |
470 | DMA_FROM_DEVICE); |
471 | list_add_tail(&rxb->list, &rxq->rx_free); | |
472 | rxq->free_count++; | |
473 | } else | |
474 | list_add_tail(&rxb->list, &rxq->rx_used); | |
475 | ||
476 | spin_unlock_irqrestore(&rxq->lock, flags); | |
477 | ||
478 | i = (i + 1) & RX_QUEUE_MASK; | |
479 | /* If there are a lot of unused frames, | |
480 | * restock the Rx queue so ucode wont assert. */ | |
481 | if (fill_rx) { | |
482 | count++; | |
483 | if (count >= 8) { | |
484 | rxq->read = i; | |
5a878bf6 | 485 | iwlagn_rx_replenish_now(trans); |
ab697a9f EG |
486 | count = 0; |
487 | } | |
488 | } | |
489 | } | |
490 | ||
491 | /* Backtrack one entry */ | |
492 | rxq->read = i; | |
493 | if (fill_rx) | |
5a878bf6 | 494 | iwlagn_rx_replenish_now(trans); |
ab697a9f | 495 | else |
5a878bf6 | 496 | iwlagn_rx_queue_restock(trans); |
ab697a9f EG |
497 | } |
498 | ||
499 | /* tasklet for iwlagn interrupt */ | |
500 | void iwl_irq_tasklet(struct iwl_priv *priv) | |
501 | { | |
502 | u32 inta = 0; | |
503 | u32 handled = 0; | |
504 | unsigned long flags; | |
505 | u32 i; | |
506 | #ifdef CONFIG_IWLWIFI_DEBUG | |
507 | u32 inta_mask; | |
508 | #endif | |
509 | ||
10b15e6f | 510 | spin_lock_irqsave(&priv->shrd->lock, flags); |
ab697a9f EG |
511 | |
512 | /* Ack/clear/reset pending uCode interrupts. | |
513 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
514 | */ | |
515 | /* There is a hardware bug in the interrupt mask function that some | |
516 | * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if | |
517 | * they are disabled in the CSR_INT_MASK register. Furthermore the | |
518 | * ICT interrupt handling mechanism has another bug that might cause | |
519 | * these unmasked interrupts fail to be detected. We workaround the | |
520 | * hardware bugs here by ACKing all the possible interrupts so that | |
521 | * interrupt coalescing can still be achieved. | |
522 | */ | |
898ed67b | 523 | iwl_write32(priv, CSR_INT, priv->inta | ~priv->inta_mask); |
ab697a9f | 524 | |
898ed67b | 525 | inta = priv->inta; |
ab697a9f EG |
526 | |
527 | #ifdef CONFIG_IWLWIFI_DEBUG | |
8f470ce3 | 528 | if (iwl_get_debug_level(priv->shrd) & IWL_DL_ISR) { |
ab697a9f EG |
529 | /* just for debug */ |
530 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
531 | IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ", | |
532 | inta, inta_mask); | |
533 | } | |
534 | #endif | |
535 | ||
10b15e6f | 536 | spin_unlock_irqrestore(&priv->shrd->lock, flags); |
ab697a9f | 537 | |
898ed67b WYG |
538 | /* saved interrupt in inta variable now we can reset priv->inta */ |
539 | priv->inta = 0; | |
ab697a9f EG |
540 | |
541 | /* Now service all interrupt bits discovered above. */ | |
542 | if (inta & CSR_INT_BIT_HW_ERR) { | |
543 | IWL_ERR(priv, "Hardware error detected. Restarting.\n"); | |
544 | ||
545 | /* Tell the device to stop sending interrupts */ | |
546 | iwl_disable_interrupts(priv); | |
547 | ||
548 | priv->isr_stats.hw++; | |
549 | iwl_irq_handle_error(priv); | |
550 | ||
551 | handled |= CSR_INT_BIT_HW_ERR; | |
552 | ||
553 | return; | |
554 | } | |
555 | ||
556 | #ifdef CONFIG_IWLWIFI_DEBUG | |
8f470ce3 | 557 | if (iwl_get_debug_level(priv->shrd) & (IWL_DL_ISR)) { |
ab697a9f EG |
558 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
559 | if (inta & CSR_INT_BIT_SCD) { | |
560 | IWL_DEBUG_ISR(priv, "Scheduler finished to transmit " | |
561 | "the frame/frames.\n"); | |
562 | priv->isr_stats.sch++; | |
563 | } | |
564 | ||
565 | /* Alive notification via Rx interrupt will do the real work */ | |
566 | if (inta & CSR_INT_BIT_ALIVE) { | |
567 | IWL_DEBUG_ISR(priv, "Alive interrupt\n"); | |
568 | priv->isr_stats.alive++; | |
569 | } | |
570 | } | |
571 | #endif | |
572 | /* Safely ignore these bits for debug checks below */ | |
573 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); | |
574 | ||
575 | /* HW RF KILL switch toggled */ | |
576 | if (inta & CSR_INT_BIT_RF_KILL) { | |
577 | int hw_rf_kill = 0; | |
578 | if (!(iwl_read32(priv, CSR_GP_CNTRL) & | |
579 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) | |
580 | hw_rf_kill = 1; | |
581 | ||
582 | IWL_WARN(priv, "RF_KILL bit toggled to %s.\n", | |
583 | hw_rf_kill ? "disable radio" : "enable radio"); | |
584 | ||
585 | priv->isr_stats.rfkill++; | |
586 | ||
587 | /* driver only loads ucode once setting the interface up. | |
588 | * the driver allows loading the ucode even if the radio | |
589 | * is killed. Hence update the killswitch state here. The | |
590 | * rfkill handler will care about restarting if needed. | |
591 | */ | |
63013ae3 | 592 | if (!test_bit(STATUS_ALIVE, &priv->shrd->status)) { |
ab697a9f | 593 | if (hw_rf_kill) |
63013ae3 | 594 | set_bit(STATUS_RF_KILL_HW, &priv->shrd->status); |
ab697a9f | 595 | else |
63013ae3 EG |
596 | clear_bit(STATUS_RF_KILL_HW, |
597 | &priv->shrd->status); | |
ab697a9f EG |
598 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill); |
599 | } | |
600 | ||
601 | handled |= CSR_INT_BIT_RF_KILL; | |
602 | } | |
603 | ||
604 | /* Chip got too hot and stopped itself */ | |
605 | if (inta & CSR_INT_BIT_CT_KILL) { | |
606 | IWL_ERR(priv, "Microcode CT kill error detected.\n"); | |
607 | priv->isr_stats.ctkill++; | |
608 | handled |= CSR_INT_BIT_CT_KILL; | |
609 | } | |
610 | ||
611 | /* Error detected by uCode */ | |
612 | if (inta & CSR_INT_BIT_SW_ERR) { | |
613 | IWL_ERR(priv, "Microcode SW error detected. " | |
614 | " Restarting 0x%X.\n", inta); | |
615 | priv->isr_stats.sw++; | |
616 | iwl_irq_handle_error(priv); | |
617 | handled |= CSR_INT_BIT_SW_ERR; | |
618 | } | |
619 | ||
620 | /* uCode wakes up after power-down sleep */ | |
621 | if (inta & CSR_INT_BIT_WAKEUP) { | |
5a878bf6 EG |
622 | struct iwl_trans_pcie *trans_pcie = |
623 | IWL_TRANS_GET_PCIE_TRANS(trans(priv)); | |
ab697a9f | 624 | IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); |
5a878bf6 | 625 | iwl_rx_queue_update_write_ptr(trans(priv), &trans_pcie->rxq); |
d6189124 | 626 | for (i = 0; i < hw_params(priv).max_txq_num; i++) |
ab697a9f EG |
627 | iwl_txq_update_write_ptr(priv, &priv->txq[i]); |
628 | ||
629 | priv->isr_stats.wakeup++; | |
630 | ||
631 | handled |= CSR_INT_BIT_WAKEUP; | |
632 | } | |
633 | ||
634 | /* All uCode command responses, including Tx command responses, | |
635 | * Rx "responses" (frame-received notification), and other | |
636 | * notifications from uCode come through here*/ | |
637 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | | |
638 | CSR_INT_BIT_RX_PERIODIC)) { | |
639 | IWL_DEBUG_ISR(priv, "Rx interrupt\n"); | |
640 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | |
641 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); | |
642 | iwl_write32(priv, CSR_FH_INT_STATUS, | |
643 | CSR_FH_INT_RX_MASK); | |
644 | } | |
645 | if (inta & CSR_INT_BIT_RX_PERIODIC) { | |
646 | handled |= CSR_INT_BIT_RX_PERIODIC; | |
647 | iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC); | |
648 | } | |
649 | /* Sending RX interrupt require many steps to be done in the | |
650 | * the device: | |
651 | * 1- write interrupt to current index in ICT table. | |
652 | * 2- dma RX frame. | |
653 | * 3- update RX shared data to indicate last write index. | |
654 | * 4- send interrupt. | |
655 | * This could lead to RX race, driver could receive RX interrupt | |
656 | * but the shared data changes does not reflect this; | |
657 | * periodic interrupt will detect any dangling Rx activity. | |
658 | */ | |
659 | ||
660 | /* Disable periodic interrupt; we use it as just a one-shot. */ | |
661 | iwl_write8(priv, CSR_INT_PERIODIC_REG, | |
662 | CSR_INT_PERIODIC_DIS); | |
5a878bf6 | 663 | iwl_rx_handle(trans(priv)); |
ab697a9f EG |
664 | |
665 | /* | |
666 | * Enable periodic interrupt in 8 msec only if we received | |
667 | * real RX interrupt (instead of just periodic int), to catch | |
668 | * any dangling Rx interrupt. If it was just the periodic | |
669 | * interrupt, there was no dangling Rx activity, and no need | |
670 | * to extend the periodic interrupt; one-shot is enough. | |
671 | */ | |
672 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) | |
673 | iwl_write8(priv, CSR_INT_PERIODIC_REG, | |
674 | CSR_INT_PERIODIC_ENA); | |
675 | ||
676 | priv->isr_stats.rx++; | |
677 | } | |
678 | ||
679 | /* This "Tx" DMA channel is used only for loading uCode */ | |
680 | if (inta & CSR_INT_BIT_FH_TX) { | |
681 | iwl_write32(priv, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK); | |
682 | IWL_DEBUG_ISR(priv, "uCode load interrupt\n"); | |
683 | priv->isr_stats.tx++; | |
684 | handled |= CSR_INT_BIT_FH_TX; | |
685 | /* Wake up uCode load routine, now that load is complete */ | |
686 | priv->ucode_write_complete = 1; | |
687 | wake_up_interruptible(&priv->wait_command_queue); | |
688 | } | |
689 | ||
690 | if (inta & ~handled) { | |
691 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); | |
692 | priv->isr_stats.unhandled++; | |
693 | } | |
694 | ||
695 | if (inta & ~(priv->inta_mask)) { | |
696 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", | |
697 | inta & ~priv->inta_mask); | |
698 | } | |
699 | ||
700 | /* Re-enable all interrupts */ | |
701 | /* only Re-enable if disabled by irq */ | |
63013ae3 | 702 | if (test_bit(STATUS_INT_ENABLED, &priv->shrd->status)) |
ab697a9f EG |
703 | iwl_enable_interrupts(priv); |
704 | /* Re-enable RF_KILL if it occurred */ | |
705 | else if (handled & CSR_INT_BIT_RF_KILL) | |
706 | iwl_enable_rfkill_int(priv); | |
707 | } | |
708 | ||
1a361cd8 EG |
709 | /****************************************************************************** |
710 | * | |
711 | * ICT functions | |
712 | * | |
713 | ******************************************************************************/ | |
714 | #define ICT_COUNT (PAGE_SIZE/sizeof(u32)) | |
715 | ||
716 | /* Free dram table */ | |
717 | void iwl_free_isr_ict(struct iwl_priv *priv) | |
718 | { | |
898ed67b | 719 | if (priv->ict_tbl_vir) { |
d5934110 | 720 | dma_free_coherent(priv->bus->dev, |
1a361cd8 | 721 | (sizeof(u32) * ICT_COUNT) + PAGE_SIZE, |
898ed67b WYG |
722 | priv->ict_tbl_vir, |
723 | priv->ict_tbl_dma); | |
724 | priv->ict_tbl_vir = NULL; | |
725 | memset(&priv->ict_tbl_dma, 0, | |
726 | sizeof(priv->ict_tbl_dma)); | |
727 | memset(&priv->aligned_ict_tbl_dma, 0, | |
728 | sizeof(priv->aligned_ict_tbl_dma)); | |
1a361cd8 EG |
729 | } |
730 | } | |
731 | ||
732 | ||
733 | /* allocate dram shared table it is a PAGE_SIZE aligned | |
734 | * also reset all data related to ICT table interrupt. | |
735 | */ | |
736 | int iwl_alloc_isr_ict(struct iwl_priv *priv) | |
737 | { | |
738 | ||
739 | /* allocate shrared data table */ | |
898ed67b | 740 | priv->ict_tbl_vir = |
d5934110 | 741 | dma_alloc_coherent(priv->bus->dev, |
1a361cd8 | 742 | (sizeof(u32) * ICT_COUNT) + PAGE_SIZE, |
898ed67b WYG |
743 | &priv->ict_tbl_dma, GFP_KERNEL); |
744 | if (!priv->ict_tbl_vir) | |
1a361cd8 EG |
745 | return -ENOMEM; |
746 | ||
747 | /* align table to PAGE_SIZE boundary */ | |
898ed67b WYG |
748 | priv->aligned_ict_tbl_dma = |
749 | ALIGN(priv->ict_tbl_dma, PAGE_SIZE); | |
1a361cd8 EG |
750 | |
751 | IWL_DEBUG_ISR(priv, "ict dma addr %Lx dma aligned %Lx diff %d\n", | |
898ed67b WYG |
752 | (unsigned long long)priv->ict_tbl_dma, |
753 | (unsigned long long)priv->aligned_ict_tbl_dma, | |
754 | (int)(priv->aligned_ict_tbl_dma - | |
755 | priv->ict_tbl_dma)); | |
1a361cd8 | 756 | |
898ed67b WYG |
757 | priv->ict_tbl = priv->ict_tbl_vir + |
758 | (priv->aligned_ict_tbl_dma - | |
759 | priv->ict_tbl_dma); | |
1a361cd8 EG |
760 | |
761 | IWL_DEBUG_ISR(priv, "ict vir addr %p vir aligned %p diff %d\n", | |
898ed67b WYG |
762 | priv->ict_tbl, priv->ict_tbl_vir, |
763 | (int)(priv->aligned_ict_tbl_dma - | |
764 | priv->ict_tbl_dma)); | |
1a361cd8 EG |
765 | |
766 | /* reset table and index to all 0 */ | |
898ed67b | 767 | memset(priv->ict_tbl_vir, 0, |
1a361cd8 | 768 | (sizeof(u32) * ICT_COUNT) + PAGE_SIZE); |
898ed67b | 769 | priv->ict_index = 0; |
1a361cd8 EG |
770 | |
771 | /* add periodic RX interrupt */ | |
772 | priv->inta_mask |= CSR_INT_BIT_RX_PERIODIC; | |
773 | return 0; | |
774 | } | |
775 | ||
776 | /* Device is going up inform it about using ICT interrupt table, | |
777 | * also we need to tell the driver to start using ICT interrupt. | |
778 | */ | |
779 | int iwl_reset_ict(struct iwl_priv *priv) | |
780 | { | |
781 | u32 val; | |
782 | unsigned long flags; | |
783 | ||
898ed67b | 784 | if (!priv->ict_tbl_vir) |
1a361cd8 EG |
785 | return 0; |
786 | ||
10b15e6f | 787 | spin_lock_irqsave(&priv->shrd->lock, flags); |
1a361cd8 EG |
788 | iwl_disable_interrupts(priv); |
789 | ||
898ed67b | 790 | memset(&priv->ict_tbl[0], 0, sizeof(u32) * ICT_COUNT); |
1a361cd8 | 791 | |
898ed67b | 792 | val = priv->aligned_ict_tbl_dma >> PAGE_SHIFT; |
1a361cd8 EG |
793 | |
794 | val |= CSR_DRAM_INT_TBL_ENABLE; | |
795 | val |= CSR_DRAM_INIT_TBL_WRAP_CHECK; | |
796 | ||
797 | IWL_DEBUG_ISR(priv, "CSR_DRAM_INT_TBL_REG =0x%X " | |
798 | "aligned dma address %Lx\n", | |
799 | val, | |
898ed67b | 800 | (unsigned long long)priv->aligned_ict_tbl_dma); |
1a361cd8 EG |
801 | |
802 | iwl_write32(priv, CSR_DRAM_INT_TBL_REG, val); | |
898ed67b WYG |
803 | priv->use_ict = true; |
804 | priv->ict_index = 0; | |
1a361cd8 EG |
805 | iwl_write32(priv, CSR_INT, priv->inta_mask); |
806 | iwl_enable_interrupts(priv); | |
10b15e6f | 807 | spin_unlock_irqrestore(&priv->shrd->lock, flags); |
1a361cd8 EG |
808 | |
809 | return 0; | |
810 | } | |
811 | ||
812 | /* Device is going down disable ict interrupt usage */ | |
813 | void iwl_disable_ict(struct iwl_priv *priv) | |
814 | { | |
815 | unsigned long flags; | |
816 | ||
10b15e6f | 817 | spin_lock_irqsave(&priv->shrd->lock, flags); |
898ed67b | 818 | priv->use_ict = false; |
10b15e6f | 819 | spin_unlock_irqrestore(&priv->shrd->lock, flags); |
1a361cd8 EG |
820 | } |
821 | ||
822 | static irqreturn_t iwl_isr(int irq, void *data) | |
823 | { | |
824 | struct iwl_priv *priv = data; | |
825 | u32 inta, inta_mask; | |
826 | unsigned long flags; | |
827 | #ifdef CONFIG_IWLWIFI_DEBUG | |
828 | u32 inta_fh; | |
829 | #endif | |
830 | if (!priv) | |
831 | return IRQ_NONE; | |
832 | ||
10b15e6f | 833 | spin_lock_irqsave(&priv->shrd->lock, flags); |
1a361cd8 EG |
834 | |
835 | /* Disable (but don't clear!) interrupts here to avoid | |
836 | * back-to-back ISRs and sporadic interrupts from our NIC. | |
837 | * If we have something to service, the tasklet will re-enable ints. | |
838 | * If we *don't* have something, we'll re-enable before leaving here. */ | |
839 | inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */ | |
840 | iwl_write32(priv, CSR_INT_MASK, 0x00000000); | |
841 | ||
842 | /* Discover which interrupts are active/pending */ | |
843 | inta = iwl_read32(priv, CSR_INT); | |
844 | ||
845 | /* Ignore interrupt if there's nothing in NIC to service. | |
846 | * This may be due to IRQ shared with another device, | |
847 | * or due to sporadic interrupts thrown from our NIC. */ | |
848 | if (!inta) { | |
849 | IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n"); | |
850 | goto none; | |
851 | } | |
852 | ||
853 | if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { | |
854 | /* Hardware disappeared. It might have already raised | |
855 | * an interrupt */ | |
856 | IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta); | |
857 | goto unplugged; | |
858 | } | |
859 | ||
860 | #ifdef CONFIG_IWLWIFI_DEBUG | |
8f470ce3 | 861 | if (iwl_get_debug_level(priv->shrd) & (IWL_DL_ISR)) { |
1a361cd8 EG |
862 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); |
863 | IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, " | |
864 | "fh 0x%08x\n", inta, inta_mask, inta_fh); | |
865 | } | |
866 | #endif | |
867 | ||
898ed67b | 868 | priv->inta |= inta; |
1a361cd8 EG |
869 | /* iwl_irq_tasklet() will service interrupts and re-enable them */ |
870 | if (likely(inta)) | |
871 | tasklet_schedule(&priv->irq_tasklet); | |
63013ae3 | 872 | else if (test_bit(STATUS_INT_ENABLED, &priv->shrd->status) && |
898ed67b | 873 | !priv->inta) |
1a361cd8 EG |
874 | iwl_enable_interrupts(priv); |
875 | ||
876 | unplugged: | |
10b15e6f | 877 | spin_unlock_irqrestore(&priv->shrd->lock, flags); |
1a361cd8 EG |
878 | return IRQ_HANDLED; |
879 | ||
880 | none: | |
881 | /* re-enable interrupts here since we don't have anything to service. */ | |
882 | /* only Re-enable if disabled by irq and no schedules tasklet. */ | |
63013ae3 | 883 | if (test_bit(STATUS_INT_ENABLED, &priv->shrd->status) && !priv->inta) |
1a361cd8 EG |
884 | iwl_enable_interrupts(priv); |
885 | ||
10b15e6f | 886 | spin_unlock_irqrestore(&priv->shrd->lock, flags); |
1a361cd8 EG |
887 | return IRQ_NONE; |
888 | } | |
889 | ||
890 | /* interrupt handler using ict table, with this interrupt driver will | |
891 | * stop using INTA register to get device's interrupt, reading this register | |
892 | * is expensive, device will write interrupts in ICT dram table, increment | |
893 | * index then will fire interrupt to driver, driver will OR all ICT table | |
894 | * entries from current index up to table entry with 0 value. the result is | |
895 | * the interrupt we need to service, driver will set the entries back to 0 and | |
896 | * set index. | |
897 | */ | |
898 | irqreturn_t iwl_isr_ict(int irq, void *data) | |
899 | { | |
900 | struct iwl_priv *priv = data; | |
901 | u32 inta, inta_mask; | |
902 | u32 val = 0; | |
903 | unsigned long flags; | |
904 | ||
905 | if (!priv) | |
906 | return IRQ_NONE; | |
907 | ||
908 | /* dram interrupt table not set yet, | |
909 | * use legacy interrupt. | |
910 | */ | |
898ed67b | 911 | if (!priv->use_ict) |
1a361cd8 EG |
912 | return iwl_isr(irq, data); |
913 | ||
10b15e6f | 914 | spin_lock_irqsave(&priv->shrd->lock, flags); |
1a361cd8 EG |
915 | |
916 | /* Disable (but don't clear!) interrupts here to avoid | |
917 | * back-to-back ISRs and sporadic interrupts from our NIC. | |
918 | * If we have something to service, the tasklet will re-enable ints. | |
919 | * If we *don't* have something, we'll re-enable before leaving here. | |
920 | */ | |
921 | inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */ | |
922 | iwl_write32(priv, CSR_INT_MASK, 0x00000000); | |
923 | ||
924 | ||
925 | /* Ignore interrupt if there's nothing in NIC to service. | |
926 | * This may be due to IRQ shared with another device, | |
927 | * or due to sporadic interrupts thrown from our NIC. */ | |
898ed67b | 928 | if (!priv->ict_tbl[priv->ict_index]) { |
1a361cd8 EG |
929 | IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n"); |
930 | goto none; | |
931 | } | |
932 | ||
933 | /* read all entries that not 0 start with ict_index */ | |
898ed67b | 934 | while (priv->ict_tbl[priv->ict_index]) { |
1a361cd8 | 935 | |
898ed67b | 936 | val |= le32_to_cpu(priv->ict_tbl[priv->ict_index]); |
1a361cd8 | 937 | IWL_DEBUG_ISR(priv, "ICT index %d value 0x%08X\n", |
898ed67b | 938 | priv->ict_index, |
1a361cd8 | 939 | le32_to_cpu( |
898ed67b WYG |
940 | priv->ict_tbl[priv->ict_index])); |
941 | priv->ict_tbl[priv->ict_index] = 0; | |
942 | priv->ict_index = iwl_queue_inc_wrap(priv->ict_index, | |
1a361cd8 EG |
943 | ICT_COUNT); |
944 | ||
945 | } | |
946 | ||
947 | /* We should not get this value, just ignore it. */ | |
948 | if (val == 0xffffffff) | |
949 | val = 0; | |
950 | ||
951 | /* | |
952 | * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit | |
953 | * (bit 15 before shifting it to 31) to clear when using interrupt | |
954 | * coalescing. fortunately, bits 18 and 19 stay set when this happens | |
955 | * so we use them to decide on the real state of the Rx bit. | |
956 | * In order words, bit 15 is set if bit 18 or bit 19 are set. | |
957 | */ | |
958 | if (val & 0xC0000) | |
959 | val |= 0x8000; | |
960 | ||
961 | inta = (0xff & val) | ((0xff00 & val) << 16); | |
962 | IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n", | |
963 | inta, inta_mask, val); | |
964 | ||
965 | inta &= priv->inta_mask; | |
898ed67b | 966 | priv->inta |= inta; |
1a361cd8 EG |
967 | |
968 | /* iwl_irq_tasklet() will service interrupts and re-enable them */ | |
969 | if (likely(inta)) | |
970 | tasklet_schedule(&priv->irq_tasklet); | |
63013ae3 | 971 | else if (test_bit(STATUS_INT_ENABLED, &priv->shrd->status) && |
898ed67b | 972 | !priv->inta) { |
1a361cd8 EG |
973 | /* Allow interrupt if was disabled by this handler and |
974 | * no tasklet was schedules, We should not enable interrupt, | |
975 | * tasklet will enable it. | |
976 | */ | |
977 | iwl_enable_interrupts(priv); | |
978 | } | |
979 | ||
10b15e6f | 980 | spin_unlock_irqrestore(&priv->shrd->lock, flags); |
1a361cd8 EG |
981 | return IRQ_HANDLED; |
982 | ||
983 | none: | |
984 | /* re-enable interrupts here since we don't have anything to service. | |
985 | * only Re-enable if disabled by irq. | |
986 | */ | |
63013ae3 | 987 | if (test_bit(STATUS_INT_ENABLED, &priv->shrd->status) && !priv->inta) |
1a361cd8 EG |
988 | iwl_enable_interrupts(priv); |
989 | ||
10b15e6f | 990 | spin_unlock_irqrestore(&priv->shrd->lock, flags); |
1a361cd8 EG |
991 | return IRQ_NONE; |
992 | } |