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1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
901069c7 | 3 | * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. |
1053d35f RR |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
1053d35f RR |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
fd4abac5 | 29 | #include <linux/etherdevice.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
253a634c | 31 | #include <linux/sched.h> |
1053d35f | 32 | #include <net/mac80211.h> |
253a634c | 33 | |
214d14d4 | 34 | #include "iwl-agn.h" |
1053d35f RR |
35 | #include "iwl-dev.h" |
36 | #include "iwl-core.h" | |
1053d35f RR |
37 | #include "iwl-io.h" |
38 | #include "iwl-helpers.h" | |
253a634c | 39 | #include "iwl-trans-int-pcie.h" |
1053d35f | 40 | |
48d42c42 EG |
41 | /** |
42 | * iwl_trans_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array | |
43 | */ | |
44 | void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_priv *priv, | |
45 | struct iwl_tx_queue *txq, | |
46 | u16 byte_cnt) | |
47 | { | |
48 | struct iwlagn_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr; | |
49 | int write_ptr = txq->q.write_ptr; | |
50 | int txq_id = txq->q.id; | |
51 | u8 sec_ctl = 0; | |
52 | u8 sta_id = 0; | |
53 | u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; | |
54 | __le16 bc_ent; | |
55 | ||
56 | WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX); | |
57 | ||
58 | sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id; | |
59 | sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl; | |
60 | ||
61 | switch (sec_ctl & TX_CMD_SEC_MSK) { | |
62 | case TX_CMD_SEC_CCM: | |
63 | len += CCMP_MIC_LEN; | |
64 | break; | |
65 | case TX_CMD_SEC_TKIP: | |
66 | len += TKIP_ICV_LEN; | |
67 | break; | |
68 | case TX_CMD_SEC_WEP: | |
69 | len += WEP_IV_LEN + WEP_ICV_LEN; | |
70 | break; | |
71 | } | |
72 | ||
73 | bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12)); | |
74 | ||
75 | scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; | |
76 | ||
77 | if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
78 | scd_bc_tbl[txq_id]. | |
79 | tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; | |
80 | } | |
81 | ||
fd4abac5 TW |
82 | /** |
83 | * iwl_txq_update_write_ptr - Send new write index to hardware | |
84 | */ | |
7bfedc59 | 85 | void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq) |
fd4abac5 TW |
86 | { |
87 | u32 reg = 0; | |
fd4abac5 TW |
88 | int txq_id = txq->q.id; |
89 | ||
90 | if (txq->need_update == 0) | |
7bfedc59 | 91 | return; |
fd4abac5 | 92 | |
f81c1f48 WYG |
93 | if (priv->cfg->base_params->shadow_reg_enable) { |
94 | /* shadow register enabled */ | |
95 | iwl_write32(priv, HBUS_TARG_WRPTR, | |
96 | txq->q.write_ptr | (txq_id << 8)); | |
97 | } else { | |
98 | /* if we're trying to save power */ | |
63013ae3 | 99 | if (test_bit(STATUS_POWER_PMI, &priv->shrd->status)) { |
f81c1f48 WYG |
100 | /* wake up nic if it's powered down ... |
101 | * uCode will wake up, and interrupt us again, so next | |
102 | * time we'll skip this part. */ | |
103 | reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); | |
fd4abac5 | 104 | |
f81c1f48 WYG |
105 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { |
106 | IWL_DEBUG_INFO(priv, | |
107 | "Tx queue %d requesting wakeup," | |
108 | " GP1 = 0x%x\n", txq_id, reg); | |
109 | iwl_set_bit(priv, CSR_GP_CNTRL, | |
110 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
111 | return; | |
112 | } | |
fd4abac5 | 113 | |
f81c1f48 | 114 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, |
fd4abac5 | 115 | txq->q.write_ptr | (txq_id << 8)); |
fd4abac5 | 116 | |
f81c1f48 WYG |
117 | /* |
118 | * else not in power-save mode, | |
119 | * uCode will never sleep when we're | |
120 | * trying to tx (during RFKILL, we're not trying to tx). | |
121 | */ | |
122 | } else | |
123 | iwl_write32(priv, HBUS_TARG_WRPTR, | |
124 | txq->q.write_ptr | (txq_id << 8)); | |
125 | } | |
fd4abac5 | 126 | txq->need_update = 0; |
fd4abac5 | 127 | } |
fd4abac5 | 128 | |
214d14d4 JB |
129 | static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
130 | { | |
131 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
132 | ||
133 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
134 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
135 | addr |= | |
136 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
137 | ||
138 | return addr; | |
139 | } | |
140 | ||
141 | static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) | |
142 | { | |
143 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
144 | ||
145 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
146 | } | |
147 | ||
148 | static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, | |
149 | dma_addr_t addr, u16 len) | |
150 | { | |
151 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
152 | u16 hi_n_len = len << 4; | |
153 | ||
154 | put_unaligned_le32(addr, &tb->lo); | |
155 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
156 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
157 | ||
158 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
159 | ||
160 | tfd->num_tbs = idx + 1; | |
161 | } | |
162 | ||
163 | static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd) | |
164 | { | |
165 | return tfd->num_tbs & 0x1f; | |
166 | } | |
167 | ||
4ce7cc2b | 168 | static void iwlagn_unmap_tfd(struct iwl_priv *priv, struct iwl_cmd_meta *meta, |
253a634c | 169 | struct iwl_tfd *tfd, enum dma_data_direction dma_dir) |
214d14d4 | 170 | { |
214d14d4 JB |
171 | int i; |
172 | int num_tbs; | |
173 | ||
214d14d4 JB |
174 | /* Sanity check on number of chunks */ |
175 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
176 | ||
177 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
178 | IWL_ERR(priv, "Too many chunks: %i\n", num_tbs); | |
179 | /* @todo issue fatal error, it is quite serious situation */ | |
180 | return; | |
181 | } | |
182 | ||
183 | /* Unmap tx_cmd */ | |
184 | if (num_tbs) | |
d5934110 | 185 | dma_unmap_single(priv->bus->dev, |
4ce7cc2b JB |
186 | dma_unmap_addr(meta, mapping), |
187 | dma_unmap_len(meta, len), | |
795414db | 188 | DMA_BIDIRECTIONAL); |
214d14d4 JB |
189 | |
190 | /* Unmap chunks, if any. */ | |
191 | for (i = 1; i < num_tbs; i++) | |
d5934110 | 192 | dma_unmap_single(priv->bus->dev, iwl_tfd_tb_get_addr(tfd, i), |
e815407d | 193 | iwl_tfd_tb_get_len(tfd, i), dma_dir); |
4ce7cc2b JB |
194 | } |
195 | ||
196 | /** | |
197 | * iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
198 | * @priv - driver private data | |
199 | * @txq - tx queue | |
1359ca4f | 200 | * @index - the index of the TFD to be freed |
4ce7cc2b JB |
201 | * |
202 | * Does NOT advance any TFD circular buffer read/write indexes | |
203 | * Does NOT free the TFD itself (which is within circular buffer) | |
204 | */ | |
1359ca4f EG |
205 | void iwlagn_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq, |
206 | int index) | |
4ce7cc2b JB |
207 | { |
208 | struct iwl_tfd *tfd_tmp = txq->tfds; | |
4ce7cc2b | 209 | |
e815407d | 210 | iwlagn_unmap_tfd(priv, &txq->meta[index], &tfd_tmp[index], |
3be3fdb5 | 211 | DMA_TO_DEVICE); |
214d14d4 JB |
212 | |
213 | /* free SKB */ | |
214 | if (txq->txb) { | |
215 | struct sk_buff *skb; | |
216 | ||
1359ca4f | 217 | skb = txq->txb[index].skb; |
214d14d4 JB |
218 | |
219 | /* can be called from irqs-disabled context */ | |
220 | if (skb) { | |
221 | dev_kfree_skb_any(skb); | |
1359ca4f | 222 | txq->txb[index].skb = NULL; |
214d14d4 JB |
223 | } |
224 | } | |
225 | } | |
226 | ||
227 | int iwlagn_txq_attach_buf_to_tfd(struct iwl_priv *priv, | |
228 | struct iwl_tx_queue *txq, | |
229 | dma_addr_t addr, u16 len, | |
4c42db0f | 230 | u8 reset) |
214d14d4 JB |
231 | { |
232 | struct iwl_queue *q; | |
233 | struct iwl_tfd *tfd, *tfd_tmp; | |
234 | u32 num_tbs; | |
235 | ||
236 | q = &txq->q; | |
4ce7cc2b | 237 | tfd_tmp = txq->tfds; |
214d14d4 JB |
238 | tfd = &tfd_tmp[q->write_ptr]; |
239 | ||
240 | if (reset) | |
241 | memset(tfd, 0, sizeof(*tfd)); | |
242 | ||
243 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
244 | ||
245 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
246 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
247 | IWL_ERR(priv, "Error can not send more than %d chunks\n", | |
248 | IWL_NUM_OF_TBS); | |
249 | return -EINVAL; | |
250 | } | |
251 | ||
252 | if (WARN_ON(addr & ~DMA_BIT_MASK(36))) | |
253 | return -EINVAL; | |
254 | ||
255 | if (unlikely(addr & ~IWL_TX_DMA_MASK)) | |
256 | IWL_ERR(priv, "Unaligned address = %llx\n", | |
257 | (unsigned long long)addr); | |
258 | ||
259 | iwl_tfd_set_tb(tfd, num_tbs, addr, len); | |
260 | ||
261 | return 0; | |
262 | } | |
263 | ||
fd4abac5 TW |
264 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
265 | * DMA services | |
266 | * | |
267 | * Theory of operation | |
268 | * | |
269 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
270 | * of buffer descriptors, each of which points to one or more data buffers for | |
271 | * the device to read from or fill. Driver and device exchange status of each | |
272 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
273 | * entries in each circular buffer, to protect against confusing empty and full | |
274 | * queue states. | |
275 | * | |
276 | * The device reads or writes the data in the queues via the device's several | |
277 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
278 | * | |
279 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
280 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
281 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
282 | * Tx queue resumed. | |
283 | * | |
fd4abac5 TW |
284 | ***************************************************/ |
285 | ||
286 | int iwl_queue_space(const struct iwl_queue *q) | |
287 | { | |
288 | int s = q->read_ptr - q->write_ptr; | |
289 | ||
290 | if (q->read_ptr > q->write_ptr) | |
291 | s -= q->n_bd; | |
292 | ||
293 | if (s <= 0) | |
294 | s += q->n_window; | |
295 | /* keep some reserve to not confuse empty and full situations */ | |
296 | s -= 2; | |
297 | if (s < 0) | |
298 | s = 0; | |
299 | return s; | |
300 | } | |
fd4abac5 | 301 | |
1053d35f RR |
302 | /** |
303 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes | |
304 | */ | |
02aca585 | 305 | int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q, |
1053d35f RR |
306 | int count, int slots_num, u32 id) |
307 | { | |
308 | q->n_bd = count; | |
309 | q->n_window = slots_num; | |
310 | q->id = id; | |
311 | ||
312 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap | |
313 | * and iwl_queue_dec_wrap are broken. */ | |
3e41ace5 JB |
314 | if (WARN_ON(!is_power_of_2(count))) |
315 | return -EINVAL; | |
1053d35f RR |
316 | |
317 | /* slots_num must be power-of-two size, otherwise | |
318 | * get_cmd_index is broken. */ | |
3e41ace5 JB |
319 | if (WARN_ON(!is_power_of_2(slots_num))) |
320 | return -EINVAL; | |
1053d35f RR |
321 | |
322 | q->low_mark = q->n_window / 4; | |
323 | if (q->low_mark < 4) | |
324 | q->low_mark = 4; | |
325 | ||
326 | q->high_mark = q->n_window / 8; | |
327 | if (q->high_mark < 2) | |
328 | q->high_mark = 2; | |
329 | ||
330 | q->write_ptr = q->read_ptr = 0; | |
331 | ||
332 | return 0; | |
333 | } | |
334 | ||
04e1cabe | 335 | static void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_priv *priv, |
48d42c42 EG |
336 | struct iwl_tx_queue *txq) |
337 | { | |
338 | struct iwlagn_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr; | |
339 | int txq_id = txq->q.id; | |
340 | int read_ptr = txq->q.read_ptr; | |
341 | u8 sta_id = 0; | |
342 | __le16 bc_ent; | |
343 | ||
344 | WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); | |
345 | ||
cefeaa5f | 346 | if (txq_id != priv->shrd->cmd_queue) |
48d42c42 EG |
347 | sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id; |
348 | ||
349 | bc_ent = cpu_to_le16(1 | (sta_id << 12)); | |
350 | scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; | |
351 | ||
352 | if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
353 | scd_bc_tbl[txq_id]. | |
354 | tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; | |
355 | } | |
356 | ||
357 | static int iwlagn_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid, | |
358 | u16 txq_id) | |
359 | { | |
360 | u32 tbl_dw_addr; | |
361 | u32 tbl_dw; | |
362 | u16 scd_q2ratid; | |
363 | ||
364 | scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; | |
365 | ||
366 | tbl_dw_addr = priv->scd_base_addr + | |
367 | SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); | |
368 | ||
369 | tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr); | |
370 | ||
371 | if (txq_id & 0x1) | |
372 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); | |
373 | else | |
374 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); | |
375 | ||
376 | iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw); | |
377 | ||
378 | return 0; | |
379 | } | |
380 | ||
381 | static void iwlagn_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id) | |
382 | { | |
383 | /* Simply stop the queue, but don't change any configuration; | |
384 | * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ | |
385 | iwl_write_prph(priv, | |
386 | SCD_QUEUE_STATUS_BITS(txq_id), | |
387 | (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)| | |
388 | (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); | |
389 | } | |
390 | ||
391 | void iwl_trans_set_wr_ptrs(struct iwl_priv *priv, | |
392 | int txq_id, u32 index) | |
393 | { | |
394 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, | |
395 | (index & 0xff) | (txq_id << 8)); | |
396 | iwl_write_prph(priv, SCD_QUEUE_RDPTR(txq_id), index); | |
397 | } | |
398 | ||
399 | void iwl_trans_tx_queue_set_status(struct iwl_priv *priv, | |
400 | struct iwl_tx_queue *txq, | |
401 | int tx_fifo_id, int scd_retry) | |
402 | { | |
403 | int txq_id = txq->q.id; | |
404 | int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0; | |
405 | ||
406 | iwl_write_prph(priv, SCD_QUEUE_STATUS_BITS(txq_id), | |
407 | (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) | | |
408 | (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) | | |
409 | (1 << SCD_QUEUE_STTS_REG_POS_WSL) | | |
410 | SCD_QUEUE_STTS_REG_MSK); | |
411 | ||
412 | txq->sched_retry = scd_retry; | |
413 | ||
414 | IWL_DEBUG_INFO(priv, "%s %s Queue %d on FIFO %d\n", | |
415 | active ? "Activate" : "Deactivate", | |
416 | scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id); | |
417 | } | |
418 | ||
e6bb4c9c | 419 | void iwl_trans_pcie_txq_agg_setup(struct iwl_priv *priv, int sta_id, int tid, |
48d42c42 EG |
420 | int frame_limit) |
421 | { | |
422 | int tx_fifo, txq_id, ssn_idx; | |
423 | u16 ra_tid; | |
424 | unsigned long flags; | |
425 | struct iwl_tid_data *tid_data; | |
426 | ||
427 | if (WARN_ON(sta_id == IWL_INVALID_STATION)) | |
428 | return; | |
429 | if (WARN_ON(tid >= MAX_TID_COUNT)) | |
430 | return; | |
431 | ||
f39c95e8 | 432 | spin_lock_irqsave(&priv->shrd->sta_lock, flags); |
48d42c42 EG |
433 | tid_data = &priv->stations[sta_id].tid[tid]; |
434 | ssn_idx = SEQ_TO_SN(tid_data->seq_number); | |
435 | txq_id = tid_data->agg.txq_id; | |
436 | tx_fifo = tid_data->agg.tx_fifo; | |
f39c95e8 | 437 | spin_unlock_irqrestore(&priv->shrd->sta_lock, flags); |
48d42c42 EG |
438 | |
439 | ra_tid = BUILD_RAxTID(sta_id, tid); | |
440 | ||
10b15e6f | 441 | spin_lock_irqsave(&priv->shrd->lock, flags); |
48d42c42 EG |
442 | |
443 | /* Stop this Tx queue before configuring it */ | |
444 | iwlagn_tx_queue_stop_scheduler(priv, txq_id); | |
445 | ||
446 | /* Map receiver-address / traffic-ID to this queue */ | |
447 | iwlagn_tx_queue_set_q2ratid(priv, ra_tid, txq_id); | |
448 | ||
449 | /* Set this queue as a chain-building queue */ | |
450 | iwl_set_bits_prph(priv, SCD_QUEUECHAIN_SEL, (1<<txq_id)); | |
451 | ||
452 | /* enable aggregations for the queue */ | |
453 | iwl_set_bits_prph(priv, SCD_AGGR_SEL, (1<<txq_id)); | |
454 | ||
455 | /* Place first TFD at index corresponding to start sequence number. | |
456 | * Assumes that ssn_idx is valid (!= 0xFFF) */ | |
457 | priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); | |
458 | priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); | |
459 | iwl_trans_set_wr_ptrs(priv, txq_id, ssn_idx); | |
460 | ||
461 | /* Set up Tx window size and frame limit for this queue */ | |
462 | iwl_write_targ_mem(priv, priv->scd_base_addr + | |
463 | SCD_CONTEXT_QUEUE_OFFSET(txq_id) + | |
464 | sizeof(u32), | |
465 | ((frame_limit << | |
466 | SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
467 | SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
468 | ((frame_limit << | |
469 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
470 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
471 | ||
472 | iwl_set_bits_prph(priv, SCD_INTERRUPT_MASK, (1 << txq_id)); | |
473 | ||
474 | /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ | |
475 | iwl_trans_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1); | |
476 | ||
a0eaad71 EG |
477 | priv->txq[txq_id].sta_id = sta_id; |
478 | priv->txq[txq_id].tid = tid; | |
479 | ||
10b15e6f | 480 | spin_unlock_irqrestore(&priv->shrd->lock, flags); |
48d42c42 EG |
481 | } |
482 | ||
e6bb4c9c | 483 | int iwl_trans_pcie_txq_agg_disable(struct iwl_priv *priv, u16 txq_id, |
48d42c42 EG |
484 | u16 ssn_idx, u8 tx_fifo) |
485 | { | |
486 | if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) || | |
487 | (IWLAGN_FIRST_AMPDU_QUEUE + | |
488 | priv->cfg->base_params->num_of_ampdu_queues <= txq_id)) { | |
489 | IWL_ERR(priv, | |
490 | "queue number out of range: %d, must be %d to %d\n", | |
491 | txq_id, IWLAGN_FIRST_AMPDU_QUEUE, | |
492 | IWLAGN_FIRST_AMPDU_QUEUE + | |
493 | priv->cfg->base_params->num_of_ampdu_queues - 1); | |
494 | return -EINVAL; | |
495 | } | |
496 | ||
497 | iwlagn_tx_queue_stop_scheduler(priv, txq_id); | |
498 | ||
499 | iwl_clear_bits_prph(priv, SCD_AGGR_SEL, (1 << txq_id)); | |
500 | ||
501 | priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); | |
502 | priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); | |
503 | /* supposes that ssn_idx is valid (!= 0xFFF) */ | |
504 | iwl_trans_set_wr_ptrs(priv, txq_id, ssn_idx); | |
505 | ||
506 | iwl_clear_bits_prph(priv, SCD_INTERRUPT_MASK, (1 << txq_id)); | |
507 | iwl_txq_ctx_deactivate(priv, txq_id); | |
508 | iwl_trans_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0); | |
509 | ||
510 | return 0; | |
511 | } | |
512 | ||
fd4abac5 TW |
513 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ |
514 | ||
515 | /** | |
516 | * iwl_enqueue_hcmd - enqueue a uCode command | |
517 | * @priv: device private data point | |
518 | * @cmd: a point to the ucode command structure | |
519 | * | |
520 | * The function returns < 0 values to indicate the operation is | |
521 | * failed. On success, it turns the index (> 0) of command in the | |
522 | * command queue. | |
523 | */ | |
253a634c | 524 | static int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd) |
fd4abac5 | 525 | { |
cefeaa5f | 526 | struct iwl_tx_queue *txq = &priv->txq[priv->shrd->cmd_queue]; |
fd4abac5 | 527 | struct iwl_queue *q = &txq->q; |
c2acea8e JB |
528 | struct iwl_device_cmd *out_cmd; |
529 | struct iwl_cmd_meta *out_meta; | |
fd4abac5 | 530 | dma_addr_t phys_addr; |
fd4abac5 | 531 | unsigned long flags; |
f3674227 | 532 | u32 idx; |
4ce7cc2b | 533 | u16 copy_size, cmd_size; |
0975cc8f | 534 | bool is_ct_kill = false; |
4ce7cc2b JB |
535 | bool had_nocopy = false; |
536 | int i; | |
537 | u8 *cmd_dest; | |
538 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
539 | const void *trace_bufs[IWL_MAX_CMD_TFDS + 1] = {}; | |
540 | int trace_lens[IWL_MAX_CMD_TFDS + 1] = {}; | |
541 | int trace_idx; | |
542 | #endif | |
fd4abac5 | 543 | |
63013ae3 | 544 | if (test_bit(STATUS_FW_ERROR, &priv->shrd->status)) { |
3083d03c WYG |
545 | IWL_WARN(priv, "fw recovery, no hcmd send\n"); |
546 | return -EIO; | |
547 | } | |
548 | ||
eedb6e35 WYG |
549 | if ((priv->ucode_owner == IWL_OWNERSHIP_TM) && |
550 | !(cmd->flags & CMD_ON_DEMAND)) { | |
551 | IWL_DEBUG_HC(priv, "tm own the uCode, no regular hcmd send\n"); | |
552 | return -EIO; | |
553 | } | |
554 | ||
4ce7cc2b JB |
555 | copy_size = sizeof(out_cmd->hdr); |
556 | cmd_size = sizeof(out_cmd->hdr); | |
557 | ||
558 | /* need one for the header if the first is NOCOPY */ | |
559 | BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1); | |
560 | ||
561 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
562 | if (!cmd->len[i]) | |
563 | continue; | |
564 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { | |
565 | had_nocopy = true; | |
566 | } else { | |
567 | /* NOCOPY must not be followed by normal! */ | |
568 | if (WARN_ON(had_nocopy)) | |
569 | return -EINVAL; | |
570 | copy_size += cmd->len[i]; | |
571 | } | |
572 | cmd_size += cmd->len[i]; | |
573 | } | |
fd4abac5 | 574 | |
3e41ace5 JB |
575 | /* |
576 | * If any of the command structures end up being larger than | |
4ce7cc2b JB |
577 | * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically |
578 | * allocated into separate TFDs, then we will need to | |
579 | * increase the size of the buffers. | |
3e41ace5 | 580 | */ |
4ce7cc2b | 581 | if (WARN_ON(copy_size > TFD_MAX_PAYLOAD_SIZE)) |
3e41ace5 | 582 | return -EINVAL; |
fd4abac5 | 583 | |
7812b167 | 584 | if (iwl_is_rfkill(priv) || iwl_is_ctkill(priv)) { |
f2f21b49 RC |
585 | IWL_WARN(priv, "Not sending command - %s KILL\n", |
586 | iwl_is_rfkill(priv) ? "RF" : "CT"); | |
fd4abac5 TW |
587 | return -EIO; |
588 | } | |
7b21f00e | 589 | |
3598e177 SG |
590 | spin_lock_irqsave(&priv->hcmd_lock, flags); |
591 | ||
c2acea8e | 592 | if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { |
3598e177 SG |
593 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); |
594 | ||
2d237f71 | 595 | IWL_ERR(priv, "No space in command queue\n"); |
f42e7662 | 596 | is_ct_kill = iwl_check_for_ct_kill(priv); |
0975cc8f | 597 | if (!is_ct_kill) { |
7812b167 | 598 | IWL_ERR(priv, "Restarting adapter due to queue full\n"); |
e649437f | 599 | iwlagn_fw_error(priv, false); |
7812b167 | 600 | } |
fd4abac5 TW |
601 | return -ENOSPC; |
602 | } | |
603 | ||
4ce7cc2b | 604 | idx = get_cmd_index(q, q->write_ptr); |
da99c4b6 | 605 | out_cmd = txq->cmd[idx]; |
c2acea8e JB |
606 | out_meta = &txq->meta[idx]; |
607 | ||
8ce73f3a | 608 | memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ |
c2acea8e JB |
609 | if (cmd->flags & CMD_WANT_SKB) |
610 | out_meta->source = cmd; | |
611 | if (cmd->flags & CMD_ASYNC) | |
612 | out_meta->callback = cmd->callback; | |
fd4abac5 | 613 | |
4ce7cc2b | 614 | /* set up the header */ |
fd4abac5 | 615 | |
4ce7cc2b | 616 | out_cmd->hdr.cmd = cmd->id; |
fd4abac5 | 617 | out_cmd->hdr.flags = 0; |
cefeaa5f EG |
618 | out_cmd->hdr.sequence = |
619 | cpu_to_le16(QUEUE_TO_SEQ(priv->shrd->cmd_queue) | | |
620 | INDEX_TO_SEQ(q->write_ptr)); | |
4ce7cc2b JB |
621 | |
622 | /* and copy the data that needs to be copied */ | |
623 | ||
624 | cmd_dest = &out_cmd->cmd.payload[0]; | |
625 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
626 | if (!cmd->len[i]) | |
627 | continue; | |
628 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) | |
629 | break; | |
630 | memcpy(cmd_dest, cmd->data[i], cmd->len[i]); | |
631 | cmd_dest += cmd->len[i]; | |
ded2ae7c | 632 | } |
4ce7cc2b JB |
633 | |
634 | IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, " | |
635 | "%d bytes at %d[%d]:%d\n", | |
636 | get_cmd_string(out_cmd->hdr.cmd), | |
637 | out_cmd->hdr.cmd, | |
638 | le16_to_cpu(out_cmd->hdr.sequence), cmd_size, | |
cefeaa5f | 639 | q->write_ptr, idx, priv->shrd->cmd_queue); |
4ce7cc2b | 640 | |
d5934110 | 641 | phys_addr = dma_map_single(priv->bus->dev, &out_cmd->hdr, copy_size, |
795414db | 642 | DMA_BIDIRECTIONAL); |
d5934110 | 643 | if (unlikely(dma_mapping_error(priv->bus->dev, phys_addr))) { |
2c46f72e JB |
644 | idx = -ENOMEM; |
645 | goto out; | |
646 | } | |
647 | ||
2e724443 | 648 | dma_unmap_addr_set(out_meta, mapping, phys_addr); |
4ce7cc2b JB |
649 | dma_unmap_len_set(out_meta, len, copy_size); |
650 | ||
651 | iwlagn_txq_attach_buf_to_tfd(priv, txq, phys_addr, copy_size, 1); | |
652 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
653 | trace_bufs[0] = &out_cmd->hdr; | |
654 | trace_lens[0] = copy_size; | |
655 | trace_idx = 1; | |
656 | #endif | |
657 | ||
658 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
659 | if (!cmd->len[i]) | |
660 | continue; | |
661 | if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY)) | |
662 | continue; | |
d5934110 | 663 | phys_addr = dma_map_single(priv->bus->dev, (void *)cmd->data[i], |
3be3fdb5 | 664 | cmd->len[i], DMA_BIDIRECTIONAL); |
d5934110 | 665 | if (dma_mapping_error(priv->bus->dev, phys_addr)) { |
4ce7cc2b | 666 | iwlagn_unmap_tfd(priv, out_meta, |
e815407d | 667 | &txq->tfds[q->write_ptr], |
3be3fdb5 | 668 | DMA_BIDIRECTIONAL); |
4ce7cc2b JB |
669 | idx = -ENOMEM; |
670 | goto out; | |
671 | } | |
672 | ||
673 | iwlagn_txq_attach_buf_to_tfd(priv, txq, phys_addr, | |
674 | cmd->len[i], 0); | |
675 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
676 | trace_bufs[trace_idx] = cmd->data[i]; | |
677 | trace_lens[trace_idx] = cmd->len[i]; | |
678 | trace_idx++; | |
679 | #endif | |
680 | } | |
df833b1d | 681 | |
afaf6b57 | 682 | out_meta->flags = cmd->flags; |
2c46f72e JB |
683 | |
684 | txq->need_update = 1; | |
685 | ||
4ce7cc2b JB |
686 | /* check that tracing gets all possible blocks */ |
687 | BUILD_BUG_ON(IWL_MAX_CMD_TFDS + 1 != 3); | |
688 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
689 | trace_iwlwifi_dev_hcmd(priv, cmd->flags, | |
690 | trace_bufs[0], trace_lens[0], | |
691 | trace_bufs[1], trace_lens[1], | |
692 | trace_bufs[2], trace_lens[2]); | |
693 | #endif | |
df833b1d | 694 | |
fd4abac5 TW |
695 | /* Increment and update queue's write index */ |
696 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
7bfedc59 | 697 | iwl_txq_update_write_ptr(priv, txq); |
fd4abac5 | 698 | |
2c46f72e | 699 | out: |
fd4abac5 | 700 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); |
7bfedc59 | 701 | return idx; |
fd4abac5 TW |
702 | } |
703 | ||
17b88929 TW |
704 | /** |
705 | * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd | |
706 | * | |
707 | * When FW advances 'R' index, all entries between old and new 'R' index | |
708 | * need to be reclaimed. As result, some free space forms. If there is | |
709 | * enough free space (> low mark), wake the stack that feeds us. | |
710 | */ | |
20ba2861 | 711 | static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, int idx) |
17b88929 TW |
712 | { |
713 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
714 | struct iwl_queue *q = &txq->q; | |
715 | int nfreed = 0; | |
716 | ||
499b1883 | 717 | if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) { |
2e5d04da DH |
718 | IWL_ERR(priv, "%s: Read index for DMA queue txq id (%d), " |
719 | "index %d is out of range [0-%d] %d %d.\n", __func__, | |
720 | txq_id, idx, q->n_bd, q->write_ptr, q->read_ptr); | |
17b88929 TW |
721 | return; |
722 | } | |
723 | ||
499b1883 TW |
724 | for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; |
725 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
17b88929 | 726 | |
499b1883 | 727 | if (nfreed++ > 0) { |
15b1687c | 728 | IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx, |
17b88929 | 729 | q->write_ptr, q->read_ptr); |
e649437f | 730 | iwlagn_fw_error(priv, false); |
17b88929 | 731 | } |
da99c4b6 | 732 | |
17b88929 TW |
733 | } |
734 | } | |
735 | ||
736 | /** | |
737 | * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them | |
738 | * @rxb: Rx buffer to reclaim | |
739 | * | |
740 | * If an Rx buffer has an async callback associated with it the callback | |
741 | * will be executed. The attached skb (if present) will only be freed | |
742 | * if the callback returns 1 | |
743 | */ | |
744 | void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb) | |
745 | { | |
2f301227 | 746 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
17b88929 TW |
747 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
748 | int txq_id = SEQ_TO_QUEUE(sequence); | |
749 | int index = SEQ_TO_INDEX(sequence); | |
17b88929 | 750 | int cmd_index; |
c2acea8e JB |
751 | struct iwl_device_cmd *cmd; |
752 | struct iwl_cmd_meta *meta; | |
cefeaa5f | 753 | struct iwl_tx_queue *txq = &priv->txq[priv->shrd->cmd_queue]; |
3598e177 | 754 | unsigned long flags; |
17b88929 TW |
755 | |
756 | /* If a Tx command is being handled and it isn't in the actual | |
757 | * command queue then there a command routing bug has been introduced | |
758 | * in the queue management code. */ | |
cefeaa5f | 759 | if (WARN(txq_id != priv->shrd->cmd_queue, |
13bb9483 | 760 | "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", |
cefeaa5f EG |
761 | txq_id, priv->shrd->cmd_queue, sequence, |
762 | priv->txq[priv->shrd->cmd_queue].q.read_ptr, | |
763 | priv->txq[priv->shrd->cmd_queue].q.write_ptr)) { | |
ec741164 | 764 | iwl_print_hex_error(priv, pkt, 32); |
55d6a3cd | 765 | return; |
01ef9323 | 766 | } |
17b88929 | 767 | |
4ce7cc2b | 768 | cmd_index = get_cmd_index(&txq->q, index); |
dd487449 ZY |
769 | cmd = txq->cmd[cmd_index]; |
770 | meta = &txq->meta[cmd_index]; | |
17b88929 | 771 | |
3be3fdb5 | 772 | iwlagn_unmap_tfd(priv, meta, &txq->tfds[index], DMA_BIDIRECTIONAL); |
c33de625 | 773 | |
17b88929 | 774 | /* Input error checking is done when commands are added to queue. */ |
c2acea8e | 775 | if (meta->flags & CMD_WANT_SKB) { |
2f301227 ZY |
776 | meta->source->reply_page = (unsigned long)rxb_addr(rxb); |
777 | rxb->page = NULL; | |
2624e96c SG |
778 | } else if (meta->callback) |
779 | meta->callback(priv, cmd, pkt); | |
780 | ||
781 | spin_lock_irqsave(&priv->hcmd_lock, flags); | |
17b88929 | 782 | |
20ba2861 | 783 | iwl_hcmd_queue_reclaim(priv, txq_id, index); |
17b88929 | 784 | |
c2acea8e | 785 | if (!(meta->flags & CMD_ASYNC)) { |
63013ae3 | 786 | clear_bit(STATUS_HCMD_ACTIVE, &priv->shrd->status); |
91dd6c27 | 787 | IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command %s\n", |
d2dfe6df | 788 | get_cmd_string(cmd->hdr.cmd)); |
17b88929 TW |
789 | wake_up_interruptible(&priv->wait_command_queue); |
790 | } | |
3598e177 | 791 | |
dd487449 | 792 | meta->flags = 0; |
3598e177 SG |
793 | |
794 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); | |
17b88929 | 795 | } |
253a634c EG |
796 | |
797 | const char *get_cmd_string(u8 cmd) | |
798 | { | |
799 | switch (cmd) { | |
800 | IWL_CMD(REPLY_ALIVE); | |
801 | IWL_CMD(REPLY_ERROR); | |
802 | IWL_CMD(REPLY_RXON); | |
803 | IWL_CMD(REPLY_RXON_ASSOC); | |
804 | IWL_CMD(REPLY_QOS_PARAM); | |
805 | IWL_CMD(REPLY_RXON_TIMING); | |
806 | IWL_CMD(REPLY_ADD_STA); | |
807 | IWL_CMD(REPLY_REMOVE_STA); | |
808 | IWL_CMD(REPLY_REMOVE_ALL_STA); | |
809 | IWL_CMD(REPLY_TXFIFO_FLUSH); | |
810 | IWL_CMD(REPLY_WEPKEY); | |
811 | IWL_CMD(REPLY_TX); | |
812 | IWL_CMD(REPLY_LEDS_CMD); | |
813 | IWL_CMD(REPLY_TX_LINK_QUALITY_CMD); | |
814 | IWL_CMD(COEX_PRIORITY_TABLE_CMD); | |
815 | IWL_CMD(COEX_MEDIUM_NOTIFICATION); | |
816 | IWL_CMD(COEX_EVENT_CMD); | |
817 | IWL_CMD(REPLY_QUIET_CMD); | |
818 | IWL_CMD(REPLY_CHANNEL_SWITCH); | |
819 | IWL_CMD(CHANNEL_SWITCH_NOTIFICATION); | |
820 | IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD); | |
821 | IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION); | |
822 | IWL_CMD(POWER_TABLE_CMD); | |
823 | IWL_CMD(PM_SLEEP_NOTIFICATION); | |
824 | IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC); | |
825 | IWL_CMD(REPLY_SCAN_CMD); | |
826 | IWL_CMD(REPLY_SCAN_ABORT_CMD); | |
827 | IWL_CMD(SCAN_START_NOTIFICATION); | |
828 | IWL_CMD(SCAN_RESULTS_NOTIFICATION); | |
829 | IWL_CMD(SCAN_COMPLETE_NOTIFICATION); | |
830 | IWL_CMD(BEACON_NOTIFICATION); | |
831 | IWL_CMD(REPLY_TX_BEACON); | |
832 | IWL_CMD(WHO_IS_AWAKE_NOTIFICATION); | |
833 | IWL_CMD(QUIET_NOTIFICATION); | |
834 | IWL_CMD(REPLY_TX_PWR_TABLE_CMD); | |
835 | IWL_CMD(MEASURE_ABORT_NOTIFICATION); | |
836 | IWL_CMD(REPLY_BT_CONFIG); | |
837 | IWL_CMD(REPLY_STATISTICS_CMD); | |
838 | IWL_CMD(STATISTICS_NOTIFICATION); | |
839 | IWL_CMD(REPLY_CARD_STATE_CMD); | |
840 | IWL_CMD(CARD_STATE_NOTIFICATION); | |
841 | IWL_CMD(MISSED_BEACONS_NOTIFICATION); | |
842 | IWL_CMD(REPLY_CT_KILL_CONFIG_CMD); | |
843 | IWL_CMD(SENSITIVITY_CMD); | |
844 | IWL_CMD(REPLY_PHY_CALIBRATION_CMD); | |
845 | IWL_CMD(REPLY_RX_PHY_CMD); | |
846 | IWL_CMD(REPLY_RX_MPDU_CMD); | |
847 | IWL_CMD(REPLY_RX); | |
848 | IWL_CMD(REPLY_COMPRESSED_BA); | |
849 | IWL_CMD(CALIBRATION_CFG_CMD); | |
850 | IWL_CMD(CALIBRATION_RES_NOTIFICATION); | |
851 | IWL_CMD(CALIBRATION_COMPLETE_NOTIFICATION); | |
852 | IWL_CMD(REPLY_TX_POWER_DBM_CMD); | |
853 | IWL_CMD(TEMPERATURE_NOTIFICATION); | |
854 | IWL_CMD(TX_ANT_CONFIGURATION_CMD); | |
855 | IWL_CMD(REPLY_BT_COEX_PROFILE_NOTIF); | |
856 | IWL_CMD(REPLY_BT_COEX_PRIO_TABLE); | |
857 | IWL_CMD(REPLY_BT_COEX_PROT_ENV); | |
858 | IWL_CMD(REPLY_WIPAN_PARAMS); | |
859 | IWL_CMD(REPLY_WIPAN_RXON); | |
860 | IWL_CMD(REPLY_WIPAN_RXON_TIMING); | |
861 | IWL_CMD(REPLY_WIPAN_RXON_ASSOC); | |
862 | IWL_CMD(REPLY_WIPAN_QOS_PARAM); | |
863 | IWL_CMD(REPLY_WIPAN_WEPKEY); | |
864 | IWL_CMD(REPLY_WIPAN_P2P_CHANNEL_SWITCH); | |
865 | IWL_CMD(REPLY_WIPAN_NOA_NOTIFICATION); | |
866 | IWL_CMD(REPLY_WIPAN_DEACTIVATION_COMPLETE); | |
c8ac61cf JB |
867 | IWL_CMD(REPLY_WOWLAN_PATTERNS); |
868 | IWL_CMD(REPLY_WOWLAN_WAKEUP_FILTER); | |
869 | IWL_CMD(REPLY_WOWLAN_TSC_RSC_PARAMS); | |
870 | IWL_CMD(REPLY_WOWLAN_TKIP_PARAMS); | |
871 | IWL_CMD(REPLY_WOWLAN_KEK_KCK_MATERIAL); | |
872 | IWL_CMD(REPLY_WOWLAN_GET_STATUS); | |
253a634c EG |
873 | default: |
874 | return "UNKNOWN"; | |
875 | ||
876 | } | |
877 | } | |
878 | ||
879 | #define HOST_COMPLETE_TIMEOUT (2 * HZ) | |
880 | ||
881 | static void iwl_generic_cmd_callback(struct iwl_priv *priv, | |
882 | struct iwl_device_cmd *cmd, | |
883 | struct iwl_rx_packet *pkt) | |
884 | { | |
885 | if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) { | |
886 | IWL_ERR(priv, "Bad return from %s (0x%08X)\n", | |
887 | get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags); | |
888 | return; | |
889 | } | |
890 | ||
891 | #ifdef CONFIG_IWLWIFI_DEBUG | |
892 | switch (cmd->hdr.cmd) { | |
893 | case REPLY_TX_LINK_QUALITY_CMD: | |
894 | case SENSITIVITY_CMD: | |
895 | IWL_DEBUG_HC_DUMP(priv, "back from %s (0x%08X)\n", | |
896 | get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags); | |
897 | break; | |
898 | default: | |
899 | IWL_DEBUG_HC(priv, "back from %s (0x%08X)\n", | |
900 | get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags); | |
901 | } | |
902 | #endif | |
903 | } | |
904 | ||
905 | static int iwl_send_cmd_async(struct iwl_priv *priv, struct iwl_host_cmd *cmd) | |
906 | { | |
907 | int ret; | |
908 | ||
909 | /* An asynchronous command can not expect an SKB to be set. */ | |
910 | if (WARN_ON(cmd->flags & CMD_WANT_SKB)) | |
911 | return -EINVAL; | |
912 | ||
913 | /* Assign a generic callback if one is not provided */ | |
914 | if (!cmd->callback) | |
915 | cmd->callback = iwl_generic_cmd_callback; | |
916 | ||
63013ae3 | 917 | if (test_bit(STATUS_EXIT_PENDING, &priv->shrd->status)) |
253a634c EG |
918 | return -EBUSY; |
919 | ||
920 | ret = iwl_enqueue_hcmd(priv, cmd); | |
921 | if (ret < 0) { | |
922 | IWL_ERR(priv, "Error sending %s: enqueue_hcmd failed: %d\n", | |
923 | get_cmd_string(cmd->id), ret); | |
924 | return ret; | |
925 | } | |
926 | return 0; | |
927 | } | |
928 | ||
929 | static int iwl_send_cmd_sync(struct iwl_priv *priv, struct iwl_host_cmd *cmd) | |
930 | { | |
931 | int cmd_idx; | |
932 | int ret; | |
933 | ||
6ac2f839 | 934 | lockdep_assert_held(&priv->shrd->mutex); |
253a634c EG |
935 | |
936 | /* A synchronous command can not have a callback set. */ | |
937 | if (WARN_ON(cmd->callback)) | |
938 | return -EINVAL; | |
939 | ||
940 | IWL_DEBUG_INFO(priv, "Attempting to send sync command %s\n", | |
941 | get_cmd_string(cmd->id)); | |
942 | ||
63013ae3 | 943 | set_bit(STATUS_HCMD_ACTIVE, &priv->shrd->status); |
253a634c EG |
944 | IWL_DEBUG_INFO(priv, "Setting HCMD_ACTIVE for command %s\n", |
945 | get_cmd_string(cmd->id)); | |
946 | ||
947 | cmd_idx = iwl_enqueue_hcmd(priv, cmd); | |
948 | if (cmd_idx < 0) { | |
949 | ret = cmd_idx; | |
63013ae3 | 950 | clear_bit(STATUS_HCMD_ACTIVE, &priv->shrd->status); |
253a634c EG |
951 | IWL_ERR(priv, "Error sending %s: enqueue_hcmd failed: %d\n", |
952 | get_cmd_string(cmd->id), ret); | |
953 | return ret; | |
954 | } | |
955 | ||
956 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, | |
63013ae3 | 957 | !test_bit(STATUS_HCMD_ACTIVE, &priv->shrd->status), |
253a634c EG |
958 | HOST_COMPLETE_TIMEOUT); |
959 | if (!ret) { | |
63013ae3 | 960 | if (test_bit(STATUS_HCMD_ACTIVE, &priv->shrd->status)) { |
253a634c EG |
961 | IWL_ERR(priv, |
962 | "Error sending %s: time out after %dms.\n", | |
963 | get_cmd_string(cmd->id), | |
964 | jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); | |
965 | ||
63013ae3 | 966 | clear_bit(STATUS_HCMD_ACTIVE, &priv->shrd->status); |
253a634c EG |
967 | IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command" |
968 | "%s\n", get_cmd_string(cmd->id)); | |
969 | ret = -ETIMEDOUT; | |
970 | goto cancel; | |
971 | } | |
972 | } | |
973 | ||
63013ae3 | 974 | if (test_bit(STATUS_RF_KILL_HW, &priv->shrd->status)) { |
253a634c EG |
975 | IWL_ERR(priv, "Command %s aborted: RF KILL Switch\n", |
976 | get_cmd_string(cmd->id)); | |
977 | ret = -ECANCELED; | |
978 | goto fail; | |
979 | } | |
63013ae3 | 980 | if (test_bit(STATUS_FW_ERROR, &priv->shrd->status)) { |
253a634c EG |
981 | IWL_ERR(priv, "Command %s failed: FW Error\n", |
982 | get_cmd_string(cmd->id)); | |
983 | ret = -EIO; | |
984 | goto fail; | |
985 | } | |
986 | if ((cmd->flags & CMD_WANT_SKB) && !cmd->reply_page) { | |
987 | IWL_ERR(priv, "Error: Response NULL in '%s'\n", | |
988 | get_cmd_string(cmd->id)); | |
989 | ret = -EIO; | |
990 | goto cancel; | |
991 | } | |
992 | ||
993 | return 0; | |
994 | ||
995 | cancel: | |
996 | if (cmd->flags & CMD_WANT_SKB) { | |
997 | /* | |
998 | * Cancel the CMD_WANT_SKB flag for the cmd in the | |
999 | * TX cmd queue. Otherwise in case the cmd comes | |
1000 | * in later, it will possibly set an invalid | |
1001 | * address (cmd->meta.source). | |
1002 | */ | |
cefeaa5f | 1003 | priv->txq[priv->shrd->cmd_queue].meta[cmd_idx].flags &= |
253a634c EG |
1004 | ~CMD_WANT_SKB; |
1005 | } | |
1006 | fail: | |
1007 | if (cmd->reply_page) { | |
1008 | iwl_free_pages(priv, cmd->reply_page); | |
1009 | cmd->reply_page = 0; | |
1010 | } | |
1011 | ||
1012 | return ret; | |
1013 | } | |
1014 | ||
e6bb4c9c | 1015 | int iwl_trans_pcie_send_cmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd) |
253a634c EG |
1016 | { |
1017 | if (cmd->flags & CMD_ASYNC) | |
1018 | return iwl_send_cmd_async(priv, cmd); | |
1019 | ||
1020 | return iwl_send_cmd_sync(priv, cmd); | |
1021 | } | |
1022 | ||
e6bb4c9c EG |
1023 | int iwl_trans_pcie_send_cmd_pdu(struct iwl_priv *priv, u8 id, u32 flags, |
1024 | u16 len, const void *data) | |
253a634c EG |
1025 | { |
1026 | struct iwl_host_cmd cmd = { | |
1027 | .id = id, | |
1028 | .len = { len, }, | |
1029 | .data = { data, }, | |
1030 | .flags = flags, | |
1031 | }; | |
1032 | ||
e6bb4c9c | 1033 | return iwl_trans_pcie_send_cmd(priv, &cmd); |
253a634c | 1034 | } |
a0eaad71 EG |
1035 | |
1036 | /* Frees buffers until index _not_ inclusive */ | |
1037 | void iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index, | |
1038 | struct sk_buff_head *skbs) | |
a0eaad71 EG |
1039 | { |
1040 | struct iwl_tx_queue *txq = &priv(trans)->txq[txq_id]; | |
1041 | struct iwl_queue *q = &txq->q; | |
1042 | struct iwl_tx_info *tx_info; | |
1043 | struct ieee80211_tx_info *info; | |
1044 | int last_to_free; | |
1045 | ||
1046 | /*Since we free until index _not_ inclusive, the one before index is | |
1047 | * the last we will free. This one must be used */ | |
1048 | last_to_free = iwl_queue_dec_wrap(index, q->n_bd); | |
1049 | ||
1050 | if ((index >= q->n_bd) || | |
1051 | (iwl_queue_used(q, last_to_free) == 0)) { | |
1052 | IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), " | |
1053 | "last_to_free %d is out of range [0-%d] %d %d.\n", | |
1054 | __func__, txq_id, last_to_free, q->n_bd, | |
1055 | q->write_ptr, q->read_ptr); | |
1056 | return; | |
1057 | } | |
1058 | ||
1059 | IWL_DEBUG_TX_REPLY(trans, "reclaim: [%d, %d, %d]\n", txq_id, | |
1060 | q->read_ptr, index); | |
1061 | ||
1062 | if (WARN_ON(!skb_queue_empty(skbs))) | |
1063 | return; | |
1064 | ||
1065 | for (; | |
1066 | q->read_ptr != index; | |
1067 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
1068 | ||
1069 | tx_info = &txq->txb[txq->q.read_ptr]; | |
1070 | ||
1071 | if (WARN_ON_ONCE(tx_info->skb == NULL)) | |
1072 | continue; | |
1073 | ||
1074 | info = IEEE80211_SKB_CB(tx_info->skb); | |
1075 | info->driver_data[0] = tx_info->ctx; | |
1076 | ||
1077 | __skb_queue_tail(skbs, tx_info->skb); | |
1078 | ||
1079 | tx_info->skb = NULL; | |
1080 | ||
1081 | iwlagn_txq_inval_byte_cnt_tbl(priv(trans), txq); | |
1082 | ||
1083 | iwlagn_txq_free_tfd(priv(trans), txq, txq->q.read_ptr); | |
1084 | } | |
1085 | } |