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iwlagn: move isr_statistics to transport layer
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-trans-tx-pcie.c
CommitLineData
1053d35f
RR		 1/******************************************************************************
2 *
901069c7 3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
1053d35f
RR		 4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
1053d35f
RR		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
fd4abac5 29#include <linux/etherdevice.h>
5a0e3ad6 30#include <linux/slab.h>
253a634c 31#include <linux/sched.h>
1053d35f 32#include <net/mac80211.h>
253a634c 33
214d14d4 34#include "iwl-agn.h"
1053d35f
RR		 35#include "iwl-dev.h"
36#include "iwl-core.h"
1053d35f
RR		 37#include "iwl-io.h"
38#include "iwl-helpers.h"
253a634c 39#include "iwl-trans-int-pcie.h"
1053d35f 40
48d42c42
EG		 41/**
42 * iwl_trans_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
43 */
44void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
45 struct iwl_tx_queue *txq,
46 u16 byte_cnt)
47{
48 struct iwlagn_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
49 int write_ptr = txq->q.write_ptr;
50 int txq_id = txq->q.id;
51 u8 sec_ctl = 0;
52 u8 sta_id = 0;
53 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
54 __le16 bc_ent;
55
56 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
57
58 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
59 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
60
61 switch (sec_ctl & TX_CMD_SEC_MSK) {
62 case TX_CMD_SEC_CCM:
63 len += CCMP_MIC_LEN;
64 break;
65 case TX_CMD_SEC_TKIP:
66 len += TKIP_ICV_LEN;
67 break;
68 case TX_CMD_SEC_WEP:
69 len += WEP_IV_LEN + WEP_ICV_LEN;
70 break;
71 }
72
73 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
74
75 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
76
77 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
78 scd_bc_tbl[txq_id].
79 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
80}
81
fd4abac5
TW		 82/**
83 * iwl_txq_update_write_ptr - Send new write index to hardware
84 */
7bfedc59 85void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
fd4abac5
TW		 86{
87 u32 reg = 0;
fd4abac5
TW		 88 int txq_id = txq->q.id;
89
90 if (txq->need_update == 0)
7bfedc59 91 return;
fd4abac5 92
f81c1f48
WYG		 93 if (priv->cfg->base_params->shadow_reg_enable) {
94 /* shadow register enabled */
95 iwl_write32(priv, HBUS_TARG_WRPTR,
96 txq->q.write_ptr | (txq_id << 8));
97 } else {
98 /* if we're trying to save power */
63013ae3 99 if (test_bit(STATUS_POWER_PMI, &priv->shrd->status)) {
f81c1f48
WYG		 100 /* wake up nic if it's powered down ...
101 * uCode will wake up, and interrupt us again, so next
102 * time we'll skip this part. */
103 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
fd4abac5 104
f81c1f48
WYG		 105 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
106 IWL_DEBUG_INFO(priv,
107 "Tx queue %d requesting wakeup,"
108 " GP1 = 0x%x\n", txq_id, reg);
109 iwl_set_bit(priv, CSR_GP_CNTRL,
110 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
111 return;
112 }
fd4abac5 113
f81c1f48 114 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
fd4abac5 115 txq->q.write_ptr | (txq_id << 8));
fd4abac5 116
f81c1f48
WYG		 117 /*
118 * else not in power-save mode,
119 * uCode will never sleep when we're
120 * trying to tx (during RFKILL, we're not trying to tx).
121 */
122 } else
123 iwl_write32(priv, HBUS_TARG_WRPTR,
124 txq->q.write_ptr | (txq_id << 8));
125 }
fd4abac5 126 txq->need_update = 0;
fd4abac5 127}
fd4abac5 128
214d14d4
JB		 129static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
130{
131 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
132
133 dma_addr_t addr = get_unaligned_le32(&tb->lo);
134 if (sizeof(dma_addr_t) > sizeof(u32))
135 addr |=
136 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
137
138 return addr;
139}
140
141static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
142{
143 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
144
145 return le16_to_cpu(tb->hi_n_len) >> 4;
146}
147
148static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
149 dma_addr_t addr, u16 len)
150{
151 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
152 u16 hi_n_len = len << 4;
153
154 put_unaligned_le32(addr, &tb->lo);
155 if (sizeof(dma_addr_t) > sizeof(u32))
156 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
157
158 tb->hi_n_len = cpu_to_le16(hi_n_len);
159
160 tfd->num_tbs = idx + 1;
161}
162
163static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
164{
165 return tfd->num_tbs & 0x1f;
166}
167
4ce7cc2b 168static void iwlagn_unmap_tfd(struct iwl_priv *priv, struct iwl_cmd_meta *meta,
253a634c 169 struct iwl_tfd *tfd, enum dma_data_direction dma_dir)
214d14d4 170{
214d14d4
JB		 171 int i;
172 int num_tbs;
173
214d14d4
JB		 174 /* Sanity check on number of chunks */
175 num_tbs = iwl_tfd_get_num_tbs(tfd);
176
177 if (num_tbs >= IWL_NUM_OF_TBS) {
178 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
179 /* @todo issue fatal error, it is quite serious situation */
180 return;
181 }
182
183 /* Unmap tx_cmd */
184 if (num_tbs)
d5934110 185 dma_unmap_single(priv->bus->dev,
4ce7cc2b
JB		 186 dma_unmap_addr(meta, mapping),
187 dma_unmap_len(meta, len),
795414db 188 DMA_BIDIRECTIONAL);
214d14d4
JB		 189
190 /* Unmap chunks, if any. */
191 for (i = 1; i < num_tbs; i++)
d5934110 192 dma_unmap_single(priv->bus->dev, iwl_tfd_tb_get_addr(tfd, i),
e815407d 193 iwl_tfd_tb_get_len(tfd, i), dma_dir);
4ce7cc2b
JB		 194}
195
196/**
197 * iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
198 * @priv - driver private data
199 * @txq - tx queue
1359ca4f 200 * @index - the index of the TFD to be freed
4ce7cc2b
JB		 201 *
202 * Does NOT advance any TFD circular buffer read/write indexes
203 * Does NOT free the TFD itself (which is within circular buffer)
204 */
1359ca4f
EG		 205void iwlagn_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq,
206 int index)
4ce7cc2b
JB		 207{
208 struct iwl_tfd *tfd_tmp = txq->tfds;
4ce7cc2b 209
e815407d 210 iwlagn_unmap_tfd(priv, &txq->meta[index], &tfd_tmp[index],
3be3fdb5 211 DMA_TO_DEVICE);
214d14d4
JB		 212
213 /* free SKB */
214 if (txq->txb) {
215 struct sk_buff *skb;
216
1359ca4f 217 skb = txq->txb[index].skb;
214d14d4
JB		 218
219 /* can be called from irqs-disabled context */
220 if (skb) {
221 dev_kfree_skb_any(skb);
1359ca4f 222 txq->txb[index].skb = NULL;
214d14d4
JB		 223 }
224 }
225}
226
227int iwlagn_txq_attach_buf_to_tfd(struct iwl_priv *priv,
228 struct iwl_tx_queue *txq,
229 dma_addr_t addr, u16 len,
4c42db0f 230 u8 reset)
214d14d4
JB		 231{
232 struct iwl_queue *q;
233 struct iwl_tfd *tfd, *tfd_tmp;
234 u32 num_tbs;
235
236 q = &txq->q;
4ce7cc2b 237 tfd_tmp = txq->tfds;
214d14d4
JB		 238 tfd = &tfd_tmp[q->write_ptr];
239
240 if (reset)
241 memset(tfd, 0, sizeof(*tfd));
242
243 num_tbs = iwl_tfd_get_num_tbs(tfd);
244
245 /* Each TFD can point to a maximum 20 Tx buffers */
246 if (num_tbs >= IWL_NUM_OF_TBS) {
247 IWL_ERR(priv, "Error can not send more than %d chunks\n",
248 IWL_NUM_OF_TBS);
249 return -EINVAL;
250 }
251
252 if (WARN_ON(addr & ~DMA_BIT_MASK(36)))
253 return -EINVAL;
254
255 if (unlikely(addr & ~IWL_TX_DMA_MASK))
256 IWL_ERR(priv, "Unaligned address = %llx\n",
257 (unsigned long long)addr);
258
259 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
260
261 return 0;
262}
263
fd4abac5
TW		 264/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
265 * DMA services
266 *
267 * Theory of operation
268 *
269 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
270 * of buffer descriptors, each of which points to one or more data buffers for
271 * the device to read from or fill. Driver and device exchange status of each
272 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
273 * entries in each circular buffer, to protect against confusing empty and full
274 * queue states.
275 *
276 * The device reads or writes the data in the queues via the device's several
277 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
278 *
279 * For Tx queue, there are low mark and high mark limits. If, after queuing
280 * the packet for Tx, free space become < low mark, Tx queue stopped. When
281 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
282 * Tx queue resumed.
283 *
fd4abac5
TW		 284 ***************************************************/
285
286int iwl_queue_space(const struct iwl_queue *q)
287{
288 int s = q->read_ptr - q->write_ptr;
289
290 if (q->read_ptr > q->write_ptr)
291 s -= q->n_bd;
292
293 if (s <= 0)
294 s += q->n_window;
295 /* keep some reserve to not confuse empty and full situations */
296 s -= 2;
297 if (s < 0)
298 s = 0;
299 return s;
300}
fd4abac5 301
1053d35f
RR		 302/**
303 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
304 */
02aca585 305int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
1053d35f
RR		 306 int count, int slots_num, u32 id)
307{
308 q->n_bd = count;
309 q->n_window = slots_num;
310 q->id = id;
311
312 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
313 * and iwl_queue_dec_wrap are broken. */
3e41ace5
JB		 314 if (WARN_ON(!is_power_of_2(count)))
315 return -EINVAL;
1053d35f
RR		 316
317 /* slots_num must be power-of-two size, otherwise
318 * get_cmd_index is broken. */
3e41ace5
JB		 319 if (WARN_ON(!is_power_of_2(slots_num)))
320 return -EINVAL;
1053d35f
RR		 321
322 q->low_mark = q->n_window / 4;
323 if (q->low_mark < 4)
324 q->low_mark = 4;
325
326 q->high_mark = q->n_window / 8;
327 if (q->high_mark < 2)
328 q->high_mark = 2;
329
330 q->write_ptr = q->read_ptr = 0;
331
332 return 0;
333}
334
48d42c42 335/*TODO: this functions should NOT be exported from trans module - export it
392f8b78
EG		 336 * until the reclaim flow will be brought to the transport module too.
337 * Add a declaration to make sparse happy */
338void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
339 struct iwl_tx_queue *txq);
340
48d42c42
EG		 341void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
342 struct iwl_tx_queue *txq)
343{
344 struct iwlagn_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
345 int txq_id = txq->q.id;
346 int read_ptr = txq->q.read_ptr;
347 u8 sta_id = 0;
348 __le16 bc_ent;
349
350 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
351
cefeaa5f 352 if (txq_id != priv->shrd->cmd_queue)
48d42c42
EG		 353 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
354
355 bc_ent = cpu_to_le16(1 | (sta_id << 12));
356 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
357
358 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
359 scd_bc_tbl[txq_id].
360 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
361}
362
363static int iwlagn_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
364 u16 txq_id)
365{
366 u32 tbl_dw_addr;
367 u32 tbl_dw;
368 u16 scd_q2ratid;
369
370 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
371
372 tbl_dw_addr = priv->scd_base_addr +
373 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
374
375 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
376
377 if (txq_id & 0x1)
378 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
379 else
380 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
381
382 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
383
384 return 0;
385}
386
387static void iwlagn_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
388{
389 /* Simply stop the queue, but don't change any configuration;
390 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
391 iwl_write_prph(priv,
392 SCD_QUEUE_STATUS_BITS(txq_id),
393 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
394 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
395}
396
397void iwl_trans_set_wr_ptrs(struct iwl_priv *priv,
398 int txq_id, u32 index)
399{
400 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
401 (index & 0xff) | (txq_id << 8));
402 iwl_write_prph(priv, SCD_QUEUE_RDPTR(txq_id), index);
403}
404
405void iwl_trans_tx_queue_set_status(struct iwl_priv *priv,
406 struct iwl_tx_queue *txq,
407 int tx_fifo_id, int scd_retry)
408{
409 int txq_id = txq->q.id;
410 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
411
412 iwl_write_prph(priv, SCD_QUEUE_STATUS_BITS(txq_id),
413 (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
414 (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
415 (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
416 SCD_QUEUE_STTS_REG_MSK);
417
418 txq->sched_retry = scd_retry;
419
420 IWL_DEBUG_INFO(priv, "%s %s Queue %d on FIFO %d\n",
421 active ? "Activate" : "Deactivate",
422 scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id);
423}
424
e6bb4c9c 425void iwl_trans_pcie_txq_agg_setup(struct iwl_priv *priv, int sta_id, int tid,
48d42c42
EG		 426 int frame_limit)
427{
428 int tx_fifo, txq_id, ssn_idx;
429 u16 ra_tid;
430 unsigned long flags;
431 struct iwl_tid_data *tid_data;
432
433 if (WARN_ON(sta_id == IWL_INVALID_STATION))
434 return;
435 if (WARN_ON(tid >= MAX_TID_COUNT))
436 return;
437
f39c95e8 438 spin_lock_irqsave(&priv->shrd->sta_lock, flags);
48d42c42
EG		 439 tid_data = &priv->stations[sta_id].tid[tid];
440 ssn_idx = SEQ_TO_SN(tid_data->seq_number);
441 txq_id = tid_data->agg.txq_id;
442 tx_fifo = tid_data->agg.tx_fifo;
f39c95e8 443 spin_unlock_irqrestore(&priv->shrd->sta_lock, flags);
48d42c42
EG		 444
445 ra_tid = BUILD_RAxTID(sta_id, tid);
446
10b15e6f 447 spin_lock_irqsave(&priv->shrd->lock, flags);
48d42c42
EG		 448
449 /* Stop this Tx queue before configuring it */
450 iwlagn_tx_queue_stop_scheduler(priv, txq_id);
451
452 /* Map receiver-address / traffic-ID to this queue */
453 iwlagn_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
454
455 /* Set this queue as a chain-building queue */
456 iwl_set_bits_prph(priv, SCD_QUEUECHAIN_SEL, (1<<txq_id));
457
458 /* enable aggregations for the queue */
459 iwl_set_bits_prph(priv, SCD_AGGR_SEL, (1<<txq_id));
460
461 /* Place first TFD at index corresponding to start sequence number.
462 * Assumes that ssn_idx is valid (!= 0xFFF) */
463 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
464 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
465 iwl_trans_set_wr_ptrs(priv, txq_id, ssn_idx);
466
467 /* Set up Tx window size and frame limit for this queue */
468 iwl_write_targ_mem(priv, priv->scd_base_addr +
469 SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
470 sizeof(u32),
471 ((frame_limit <<
472 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
473 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
474 ((frame_limit <<
475 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
476 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
477
478 iwl_set_bits_prph(priv, SCD_INTERRUPT_MASK, (1 << txq_id));
479
480 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
481 iwl_trans_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
482
10b15e6f 483 spin_unlock_irqrestore(&priv->shrd->lock, flags);
48d42c42
EG		 484}
485
e6bb4c9c 486int iwl_trans_pcie_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
48d42c42
EG		 487 u16 ssn_idx, u8 tx_fifo)
488{
489 if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) ||
490 (IWLAGN_FIRST_AMPDU_QUEUE +
491 priv->cfg->base_params->num_of_ampdu_queues <= txq_id)) {
492 IWL_ERR(priv,
493 "queue number out of range: %d, must be %d to %d\n",
494 txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
495 IWLAGN_FIRST_AMPDU_QUEUE +
496 priv->cfg->base_params->num_of_ampdu_queues - 1);
497 return -EINVAL;
498 }
499
500 iwlagn_tx_queue_stop_scheduler(priv, txq_id);
501
502 iwl_clear_bits_prph(priv, SCD_AGGR_SEL, (1 << txq_id));
503
504 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
505 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
506 /* supposes that ssn_idx is valid (!= 0xFFF) */
507 iwl_trans_set_wr_ptrs(priv, txq_id, ssn_idx);
508
509 iwl_clear_bits_prph(priv, SCD_INTERRUPT_MASK, (1 << txq_id));
510 iwl_txq_ctx_deactivate(priv, txq_id);
511 iwl_trans_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
512
513 return 0;
514}
515
fd4abac5
TW		 516/*************** HOST COMMAND QUEUE FUNCTIONS *****/
517
518/**
519 * iwl_enqueue_hcmd - enqueue a uCode command
520 * @priv: device private data point
521 * @cmd: a point to the ucode command structure
522 *
523 * The function returns < 0 values to indicate the operation is
524 * failed. On success, it turns the index (> 0) of command in the
525 * command queue.
526 */
253a634c 527static int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
fd4abac5 528{
cefeaa5f 529 struct iwl_tx_queue *txq = &priv->txq[priv->shrd->cmd_queue];
fd4abac5 530 struct iwl_queue *q = &txq->q;
c2acea8e
JB		 531 struct iwl_device_cmd *out_cmd;
532 struct iwl_cmd_meta *out_meta;
fd4abac5 533 dma_addr_t phys_addr;
fd4abac5 534 unsigned long flags;
f3674227 535 u32 idx;
4ce7cc2b 536 u16 copy_size, cmd_size;
0975cc8f 537 bool is_ct_kill = false;
4ce7cc2b
JB		 538 bool had_nocopy = false;
539 int i;
540 u8 *cmd_dest;
541#ifdef CONFIG_IWLWIFI_DEVICE_TRACING
542 const void *trace_bufs[IWL_MAX_CMD_TFDS + 1] = {};
543 int trace_lens[IWL_MAX_CMD_TFDS + 1] = {};
544 int trace_idx;
545#endif
fd4abac5 546
63013ae3 547 if (test_bit(STATUS_FW_ERROR, &priv->shrd->status)) {
3083d03c
WYG		 548 IWL_WARN(priv, "fw recovery, no hcmd send\n");
549 return -EIO;
550 }
551
eedb6e35
WYG		 552 if ((priv->ucode_owner == IWL_OWNERSHIP_TM) &&
553 !(cmd->flags & CMD_ON_DEMAND)) {
554 IWL_DEBUG_HC(priv, "tm own the uCode, no regular hcmd send\n");
555 return -EIO;
556 }
557
4ce7cc2b
JB		 558 copy_size = sizeof(out_cmd->hdr);
559 cmd_size = sizeof(out_cmd->hdr);
560
561 /* need one for the header if the first is NOCOPY */
562 BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1);
563
564 for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
565 if (!cmd->len[i])
566 continue;
567 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
568 had_nocopy = true;
569 } else {
570 /* NOCOPY must not be followed by normal! */
571 if (WARN_ON(had_nocopy))
572 return -EINVAL;
573 copy_size += cmd->len[i];
574 }
575 cmd_size += cmd->len[i];
576 }
fd4abac5 577
3e41ace5
JB		 578 /*
579 * If any of the command structures end up being larger than
4ce7cc2b
JB		 580 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
581 * allocated into separate TFDs, then we will need to
582 * increase the size of the buffers.
3e41ace5 583 */
4ce7cc2b 584 if (WARN_ON(copy_size > TFD_MAX_PAYLOAD_SIZE))
3e41ace5 585 return -EINVAL;
fd4abac5 586
7812b167 587 if (iwl_is_rfkill(priv) || iwl_is_ctkill(priv)) {
f2f21b49
RC		 588 IWL_WARN(priv, "Not sending command - %s KILL\n",
589 iwl_is_rfkill(priv) ? "RF" : "CT");
fd4abac5
TW		 590 return -EIO;
591 }
7b21f00e 592
3598e177
SG		 593 spin_lock_irqsave(&priv->hcmd_lock, flags);
594
c2acea8e 595 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
3598e177
SG		 596 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
597
2d237f71 598 IWL_ERR(priv, "No space in command queue\n");
f42e7662 599 is_ct_kill = iwl_check_for_ct_kill(priv);
0975cc8f 600 if (!is_ct_kill) {
7812b167 601 IWL_ERR(priv, "Restarting adapter due to queue full\n");
e649437f 602 iwlagn_fw_error(priv, false);
7812b167 603 }
fd4abac5
TW		 604 return -ENOSPC;
605 }
606
4ce7cc2b 607 idx = get_cmd_index(q, q->write_ptr);
da99c4b6 608 out_cmd = txq->cmd[idx];
c2acea8e
JB		 609 out_meta = &txq->meta[idx];
610
8ce73f3a 611 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
c2acea8e
JB		 612 if (cmd->flags & CMD_WANT_SKB)
613 out_meta->source = cmd;
614 if (cmd->flags & CMD_ASYNC)
615 out_meta->callback = cmd->callback;
fd4abac5 616
4ce7cc2b 617 /* set up the header */
fd4abac5 618
4ce7cc2b 619 out_cmd->hdr.cmd = cmd->id;
fd4abac5 620 out_cmd->hdr.flags = 0;
cefeaa5f
EG		 621 out_cmd->hdr.sequence =
622 cpu_to_le16(QUEUE_TO_SEQ(priv->shrd->cmd_queue) |
623 INDEX_TO_SEQ(q->write_ptr));
4ce7cc2b
JB		 624
625 /* and copy the data that needs to be copied */
626
627 cmd_dest = &out_cmd->cmd.payload[0];
628 for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
629 if (!cmd->len[i])
630 continue;
631 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY)
632 break;
633 memcpy(cmd_dest, cmd->data[i], cmd->len[i]);
634 cmd_dest += cmd->len[i];
ded2ae7c 635 }
4ce7cc2b
JB		 636
637 IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, "
638 "%d bytes at %d[%d]:%d\n",
639 get_cmd_string(out_cmd->hdr.cmd),
640 out_cmd->hdr.cmd,
641 le16_to_cpu(out_cmd->hdr.sequence), cmd_size,
cefeaa5f 642 q->write_ptr, idx, priv->shrd->cmd_queue);
4ce7cc2b 643
d5934110 644 phys_addr = dma_map_single(priv->bus->dev, &out_cmd->hdr, copy_size,
795414db 645 DMA_BIDIRECTIONAL);
d5934110 646 if (unlikely(dma_mapping_error(priv->bus->dev, phys_addr))) {
2c46f72e
JB		 647 idx = -ENOMEM;
648 goto out;
649 }
650
2e724443 651 dma_unmap_addr_set(out_meta, mapping, phys_addr);
4ce7cc2b
JB		 652 dma_unmap_len_set(out_meta, len, copy_size);
653
654 iwlagn_txq_attach_buf_to_tfd(priv, txq, phys_addr, copy_size, 1);
655#ifdef CONFIG_IWLWIFI_DEVICE_TRACING
656 trace_bufs[0] = &out_cmd->hdr;
657 trace_lens[0] = copy_size;
658 trace_idx = 1;
659#endif
660
661 for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
662 if (!cmd->len[i])
663 continue;
664 if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY))
665 continue;
d5934110 666 phys_addr = dma_map_single(priv->bus->dev, (void *)cmd->data[i],
3be3fdb5 667 cmd->len[i], DMA_BIDIRECTIONAL);
d5934110 668 if (dma_mapping_error(priv->bus->dev, phys_addr)) {
4ce7cc2b 669 iwlagn_unmap_tfd(priv, out_meta,
e815407d 670 &txq->tfds[q->write_ptr],
3be3fdb5 671 DMA_BIDIRECTIONAL);
4ce7cc2b
JB		 672 idx = -ENOMEM;
673 goto out;
674 }
675
676 iwlagn_txq_attach_buf_to_tfd(priv, txq, phys_addr,
677 cmd->len[i], 0);
678#ifdef CONFIG_IWLWIFI_DEVICE_TRACING
679 trace_bufs[trace_idx] = cmd->data[i];
680 trace_lens[trace_idx] = cmd->len[i];
681 trace_idx++;
682#endif
683 }
df833b1d 684
afaf6b57 685 out_meta->flags = cmd->flags;
2c46f72e
JB		 686
687 txq->need_update = 1;
688
4ce7cc2b
JB		 689 /* check that tracing gets all possible blocks */
690 BUILD_BUG_ON(IWL_MAX_CMD_TFDS + 1 != 3);
691#ifdef CONFIG_IWLWIFI_DEVICE_TRACING
692 trace_iwlwifi_dev_hcmd(priv, cmd->flags,
693 trace_bufs[0], trace_lens[0],
694 trace_bufs[1], trace_lens[1],
695 trace_bufs[2], trace_lens[2]);
696#endif
df833b1d 697
fd4abac5
TW		 698 /* Increment and update queue's write index */
699 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
7bfedc59 700 iwl_txq_update_write_ptr(priv, txq);
fd4abac5 701
2c46f72e 702 out:
fd4abac5 703 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
7bfedc59 704 return idx;
fd4abac5
TW		 705}
706
17b88929
TW		 707/**
708 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
709 *
710 * When FW advances 'R' index, all entries between old and new 'R' index
711 * need to be reclaimed. As result, some free space forms. If there is
712 * enough free space (> low mark), wake the stack that feeds us.
713 */
20ba2861 714static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, int idx)
17b88929
TW		 715{
716 struct iwl_tx_queue *txq = &priv->txq[txq_id];
717 struct iwl_queue *q = &txq->q;
718 int nfreed = 0;
719
499b1883 720 if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
2e5d04da
DH		 721 IWL_ERR(priv, "%s: Read index for DMA queue txq id (%d), "
722 "index %d is out of range [0-%d] %d %d.\n", __func__,
723 txq_id, idx, q->n_bd, q->write_ptr, q->read_ptr);
17b88929
TW		 724 return;
725 }
726
499b1883
TW		 727 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
728 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
17b88929 729
499b1883 730 if (nfreed++ > 0) {
15b1687c 731 IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx,
17b88929 732 q->write_ptr, q->read_ptr);
e649437f 733 iwlagn_fw_error(priv, false);
17b88929 734 }
da99c4b6 735
17b88929
TW		 736 }
737}
738
739/**
740 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
741 * @rxb: Rx buffer to reclaim
742 *
743 * If an Rx buffer has an async callback associated with it the callback
744 * will be executed. The attached skb (if present) will only be freed
745 * if the callback returns 1
746 */
747void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
748{
2f301227 749 struct iwl_rx_packet *pkt = rxb_addr(rxb);
17b88929
TW		 750 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
751 int txq_id = SEQ_TO_QUEUE(sequence);
752 int index = SEQ_TO_INDEX(sequence);
17b88929 753 int cmd_index;
c2acea8e
JB		 754 struct iwl_device_cmd *cmd;
755 struct iwl_cmd_meta *meta;
cefeaa5f 756 struct iwl_tx_queue *txq = &priv->txq[priv->shrd->cmd_queue];
3598e177 757 unsigned long flags;
17b88929
TW		 758
759 /* If a Tx command is being handled and it isn't in the actual
760 * command queue then there a command routing bug has been introduced
761 * in the queue management code. */
cefeaa5f 762 if (WARN(txq_id != priv->shrd->cmd_queue,
13bb9483 763 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
cefeaa5f
EG		 764 txq_id, priv->shrd->cmd_queue, sequence,
765 priv->txq[priv->shrd->cmd_queue].q.read_ptr,
766 priv->txq[priv->shrd->cmd_queue].q.write_ptr)) {
ec741164 767 iwl_print_hex_error(priv, pkt, 32);
55d6a3cd 768 return;
01ef9323 769 }
17b88929 770
4ce7cc2b 771 cmd_index = get_cmd_index(&txq->q, index);
dd487449
ZY		 772 cmd = txq->cmd[cmd_index];
773 meta = &txq->meta[cmd_index];
17b88929 774
3be3fdb5 775 iwlagn_unmap_tfd(priv, meta, &txq->tfds[index], DMA_BIDIRECTIONAL);
c33de625 776
17b88929 777 /* Input error checking is done when commands are added to queue. */
c2acea8e 778 if (meta->flags & CMD_WANT_SKB) {
2f301227
ZY		 779 meta->source->reply_page = (unsigned long)rxb_addr(rxb);
780 rxb->page = NULL;
2624e96c
SG		 781 } else if (meta->callback)
782 meta->callback(priv, cmd, pkt);
783
784 spin_lock_irqsave(&priv->hcmd_lock, flags);
17b88929 785
20ba2861 786 iwl_hcmd_queue_reclaim(priv, txq_id, index);
17b88929 787
c2acea8e 788 if (!(meta->flags & CMD_ASYNC)) {
63013ae3 789 clear_bit(STATUS_HCMD_ACTIVE, &priv->shrd->status);
91dd6c27 790 IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command %s\n",
d2dfe6df 791 get_cmd_string(cmd->hdr.cmd));
17b88929
TW		 792 wake_up_interruptible(&priv->wait_command_queue);
793 }
3598e177 794
dd487449 795 meta->flags = 0;
3598e177
SG		 796
797 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
17b88929 798}
253a634c
EG		 799
800const char *get_cmd_string(u8 cmd)
801{
802 switch (cmd) {
803 IWL_CMD(REPLY_ALIVE);
804 IWL_CMD(REPLY_ERROR);
805 IWL_CMD(REPLY_RXON);
806 IWL_CMD(REPLY_RXON_ASSOC);
807 IWL_CMD(REPLY_QOS_PARAM);
808 IWL_CMD(REPLY_RXON_TIMING);
809 IWL_CMD(REPLY_ADD_STA);
810 IWL_CMD(REPLY_REMOVE_STA);
811 IWL_CMD(REPLY_REMOVE_ALL_STA);
812 IWL_CMD(REPLY_TXFIFO_FLUSH);
813 IWL_CMD(REPLY_WEPKEY);
814 IWL_CMD(REPLY_TX);
815 IWL_CMD(REPLY_LEDS_CMD);
816 IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
817 IWL_CMD(COEX_PRIORITY_TABLE_CMD);
818 IWL_CMD(COEX_MEDIUM_NOTIFICATION);
819 IWL_CMD(COEX_EVENT_CMD);
820 IWL_CMD(REPLY_QUIET_CMD);
821 IWL_CMD(REPLY_CHANNEL_SWITCH);
822 IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
823 IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
824 IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
825 IWL_CMD(POWER_TABLE_CMD);
826 IWL_CMD(PM_SLEEP_NOTIFICATION);
827 IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
828 IWL_CMD(REPLY_SCAN_CMD);
829 IWL_CMD(REPLY_SCAN_ABORT_CMD);
830 IWL_CMD(SCAN_START_NOTIFICATION);
831 IWL_CMD(SCAN_RESULTS_NOTIFICATION);
832 IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
833 IWL_CMD(BEACON_NOTIFICATION);
834 IWL_CMD(REPLY_TX_BEACON);
835 IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
836 IWL_CMD(QUIET_NOTIFICATION);
837 IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
838 IWL_CMD(MEASURE_ABORT_NOTIFICATION);
839 IWL_CMD(REPLY_BT_CONFIG);
840 IWL_CMD(REPLY_STATISTICS_CMD);
841 IWL_CMD(STATISTICS_NOTIFICATION);
842 IWL_CMD(REPLY_CARD_STATE_CMD);
843 IWL_CMD(CARD_STATE_NOTIFICATION);
844 IWL_CMD(MISSED_BEACONS_NOTIFICATION);
845 IWL_CMD(REPLY_CT_KILL_CONFIG_CMD);
846 IWL_CMD(SENSITIVITY_CMD);
847 IWL_CMD(REPLY_PHY_CALIBRATION_CMD);
848 IWL_CMD(REPLY_RX_PHY_CMD);
849 IWL_CMD(REPLY_RX_MPDU_CMD);
850 IWL_CMD(REPLY_RX);
851 IWL_CMD(REPLY_COMPRESSED_BA);
852 IWL_CMD(CALIBRATION_CFG_CMD);
853 IWL_CMD(CALIBRATION_RES_NOTIFICATION);
854 IWL_CMD(CALIBRATION_COMPLETE_NOTIFICATION);
855 IWL_CMD(REPLY_TX_POWER_DBM_CMD);
856 IWL_CMD(TEMPERATURE_NOTIFICATION);
857 IWL_CMD(TX_ANT_CONFIGURATION_CMD);
858 IWL_CMD(REPLY_BT_COEX_PROFILE_NOTIF);
859 IWL_CMD(REPLY_BT_COEX_PRIO_TABLE);
860 IWL_CMD(REPLY_BT_COEX_PROT_ENV);
861 IWL_CMD(REPLY_WIPAN_PARAMS);
862 IWL_CMD(REPLY_WIPAN_RXON);
863 IWL_CMD(REPLY_WIPAN_RXON_TIMING);
864 IWL_CMD(REPLY_WIPAN_RXON_ASSOC);
865 IWL_CMD(REPLY_WIPAN_QOS_PARAM);
866 IWL_CMD(REPLY_WIPAN_WEPKEY);
867 IWL_CMD(REPLY_WIPAN_P2P_CHANNEL_SWITCH);
868 IWL_CMD(REPLY_WIPAN_NOA_NOTIFICATION);
869 IWL_CMD(REPLY_WIPAN_DEACTIVATION_COMPLETE);
c8ac61cf
JB		 870 IWL_CMD(REPLY_WOWLAN_PATTERNS);
871 IWL_CMD(REPLY_WOWLAN_WAKEUP_FILTER);
872 IWL_CMD(REPLY_WOWLAN_TSC_RSC_PARAMS);
873 IWL_CMD(REPLY_WOWLAN_TKIP_PARAMS);
874 IWL_CMD(REPLY_WOWLAN_KEK_KCK_MATERIAL);
875 IWL_CMD(REPLY_WOWLAN_GET_STATUS);
253a634c
EG		 876 default:
877 return "UNKNOWN";
878
879 }
880}
881
882#define HOST_COMPLETE_TIMEOUT (2 * HZ)
883
884static void iwl_generic_cmd_callback(struct iwl_priv *priv,
885 struct iwl_device_cmd *cmd,
886 struct iwl_rx_packet *pkt)
887{
888 if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
889 IWL_ERR(priv, "Bad return from %s (0x%08X)\n",
890 get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
891 return;
892 }
893
894#ifdef CONFIG_IWLWIFI_DEBUG
895 switch (cmd->hdr.cmd) {
896 case REPLY_TX_LINK_QUALITY_CMD:
897 case SENSITIVITY_CMD:
898 IWL_DEBUG_HC_DUMP(priv, "back from %s (0x%08X)\n",
899 get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
900 break;
901 default:
902 IWL_DEBUG_HC(priv, "back from %s (0x%08X)\n",
903 get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
904 }
905#endif
906}
907
908static int iwl_send_cmd_async(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
909{
910 int ret;
911
912 /* An asynchronous command can not expect an SKB to be set. */
913 if (WARN_ON(cmd->flags & CMD_WANT_SKB))
914 return -EINVAL;
915
916 /* Assign a generic callback if one is not provided */
917 if (!cmd->callback)
918 cmd->callback = iwl_generic_cmd_callback;
919
63013ae3 920 if (test_bit(STATUS_EXIT_PENDING, &priv->shrd->status))
253a634c
EG		 921 return -EBUSY;
922
923 ret = iwl_enqueue_hcmd(priv, cmd);
924 if (ret < 0) {
925 IWL_ERR(priv, "Error sending %s: enqueue_hcmd failed: %d\n",
926 get_cmd_string(cmd->id), ret);
927 return ret;
928 }
929 return 0;
930}
931
932static int iwl_send_cmd_sync(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
933{
934 int cmd_idx;
935 int ret;
936
6ac2f839 937 lockdep_assert_held(&priv->shrd->mutex);
253a634c
EG		 938
939 /* A synchronous command can not have a callback set. */
940 if (WARN_ON(cmd->callback))
941 return -EINVAL;
942
943 IWL_DEBUG_INFO(priv, "Attempting to send sync command %s\n",
944 get_cmd_string(cmd->id));
945
63013ae3 946 set_bit(STATUS_HCMD_ACTIVE, &priv->shrd->status);
253a634c
EG		 947 IWL_DEBUG_INFO(priv, "Setting HCMD_ACTIVE for command %s\n",
948 get_cmd_string(cmd->id));
949
950 cmd_idx = iwl_enqueue_hcmd(priv, cmd);
951 if (cmd_idx < 0) {
952 ret = cmd_idx;
63013ae3 953 clear_bit(STATUS_HCMD_ACTIVE, &priv->shrd->status);
253a634c
EG		 954 IWL_ERR(priv, "Error sending %s: enqueue_hcmd failed: %d\n",
955 get_cmd_string(cmd->id), ret);
956 return ret;
957 }
958
959 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
63013ae3 960 !test_bit(STATUS_HCMD_ACTIVE, &priv->shrd->status),
253a634c
EG		 961 HOST_COMPLETE_TIMEOUT);
962 if (!ret) {
63013ae3 963 if (test_bit(STATUS_HCMD_ACTIVE, &priv->shrd->status)) {
253a634c
EG		 964 IWL_ERR(priv,
965 "Error sending %s: time out after %dms.\n",
966 get_cmd_string(cmd->id),
967 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
968
63013ae3 969 clear_bit(STATUS_HCMD_ACTIVE, &priv->shrd->status);
253a634c
EG		 970 IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command"
971 "%s\n", get_cmd_string(cmd->id));
972 ret = -ETIMEDOUT;
973 goto cancel;
974 }
975 }
976
63013ae3 977 if (test_bit(STATUS_RF_KILL_HW, &priv->shrd->status)) {
253a634c
EG		 978 IWL_ERR(priv, "Command %s aborted: RF KILL Switch\n",
979 get_cmd_string(cmd->id));
980 ret = -ECANCELED;
981 goto fail;
982 }
63013ae3 983 if (test_bit(STATUS_FW_ERROR, &priv->shrd->status)) {
253a634c
EG		 984 IWL_ERR(priv, "Command %s failed: FW Error\n",
985 get_cmd_string(cmd->id));
986 ret = -EIO;
987 goto fail;
988 }
989 if ((cmd->flags & CMD_WANT_SKB) && !cmd->reply_page) {
990 IWL_ERR(priv, "Error: Response NULL in '%s'\n",
991 get_cmd_string(cmd->id));
992 ret = -EIO;
993 goto cancel;
994 }
995
996 return 0;
997
998cancel:
999 if (cmd->flags & CMD_WANT_SKB) {
1000 /*
1001 * Cancel the CMD_WANT_SKB flag for the cmd in the
1002 * TX cmd queue. Otherwise in case the cmd comes
1003 * in later, it will possibly set an invalid
1004 * address (cmd->meta.source).
1005 */
cefeaa5f 1006 priv->txq[priv->shrd->cmd_queue].meta[cmd_idx].flags &=
253a634c
EG		 1007 ~CMD_WANT_SKB;
1008 }
1009fail:
1010 if (cmd->reply_page) {
1011 iwl_free_pages(priv, cmd->reply_page);
1012 cmd->reply_page = 0;
1013 }
1014
1015 return ret;
1016}
1017
e6bb4c9c 1018int iwl_trans_pcie_send_cmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
253a634c
EG		 1019{
1020 if (cmd->flags & CMD_ASYNC)
1021 return iwl_send_cmd_async(priv, cmd);
1022
1023 return iwl_send_cmd_sync(priv, cmd);
1024}
1025
e6bb4c9c
EG		 1026int iwl_trans_pcie_send_cmd_pdu(struct iwl_priv *priv, u8 id, u32 flags,
1027 u16 len, const void *data)
253a634c
EG		 1028{
1029 struct iwl_host_cmd cmd = {
1030 .id = id,
1031 .len = { len, },
1032 .data = { data, },
1033 .flags = flags,
1034 };
1035
e6bb4c9c 1036 return iwl_trans_pcie_send_cmd(priv, &cmd);
253a634c 1037}
Linux kernel - Deliverables
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