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c85eb619 EG |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
51368bf7 | 8 | * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved. |
8d193ca2 | 9 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH |
c85eb619 EG |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of version 2 of the GNU General Public License as | |
13 | * published by the Free Software Foundation. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but | |
16 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
23 | * USA | |
24 | * | |
25 | * The full GNU General Public License is included in this distribution | |
410dc5aa | 26 | * in the file called COPYING. |
c85eb619 EG |
27 | * |
28 | * Contact Information: | |
29 | * Intel Linux Wireless <ilw@linux.intel.com> | |
30 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
31 | * | |
32 | * BSD LICENSE | |
33 | * | |
51368bf7 | 34 | * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. |
8d193ca2 | 35 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH |
c85eb619 EG |
36 | * All rights reserved. |
37 | * | |
38 | * Redistribution and use in source and binary forms, with or without | |
39 | * modification, are permitted provided that the following conditions | |
40 | * are met: | |
41 | * | |
42 | * * Redistributions of source code must retain the above copyright | |
43 | * notice, this list of conditions and the following disclaimer. | |
44 | * * Redistributions in binary form must reproduce the above copyright | |
45 | * notice, this list of conditions and the following disclaimer in | |
46 | * the documentation and/or other materials provided with the | |
47 | * distribution. | |
48 | * * Neither the name Intel Corporation nor the names of its | |
49 | * contributors may be used to endorse or promote products derived | |
50 | * from this software without specific prior written permission. | |
51 | * | |
52 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
53 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
54 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
55 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
56 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
57 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
58 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
59 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
60 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
61 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
62 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
63 | * | |
64 | *****************************************************************************/ | |
41c50542 EG |
65 | #ifndef __iwl_trans_h__ |
66 | #define __iwl_trans_h__ | |
253a634c | 67 | |
e679378d | 68 | #include <linux/ieee80211.h> |
930dfd5f | 69 | #include <linux/mm.h> /* for page_address */ |
2bfb5092 | 70 | #include <linux/lockdep.h> |
a72b8b08 | 71 | |
69655ebf | 72 | #include "iwl-debug.h" |
6238b008 JB |
73 | #include "iwl-config.h" |
74 | #include "iwl-fw.h" | |
2a988e98 | 75 | #include "iwl-op-mode.h" |
87e5666c | 76 | |
60396183 EG |
77 | /** |
78 | * DOC: Transport layer - what is it ? | |
79 | * | |
0d365ae5 | 80 | * The transport layer is the layer that deals with the HW directly. It provides |
60396183 EG |
81 | * an abstraction of the underlying HW to the upper layer. The transport layer |
82 | * doesn't provide any policy, algorithm or anything of this kind, but only | |
0d365ae5 | 83 | * mechanisms to make the HW do something. It is not completely stateless but |
60396183 EG |
84 | * close to it. |
85 | * We will have an implementation for each different supported bus. | |
86 | */ | |
87 | ||
88 | /** | |
89 | * DOC: Life cycle of the transport layer | |
90 | * | |
91 | * The transport layer has a very precise life cycle. | |
92 | * | |
93 | * 1) A helper function is called during the module initialization and | |
94 | * registers the bus driver's ops with the transport's alloc function. | |
95 | * 2) Bus's probe calls to the transport layer's allocation functions. | |
96 | * Of course this function is bus specific. | |
97 | * 3) This allocation functions will spawn the upper layer which will | |
98 | * register mac80211. | |
99 | * | |
100 | * 4) At some point (i.e. mac80211's start call), the op_mode will call | |
101 | * the following sequence: | |
102 | * start_hw | |
103 | * start_fw | |
104 | * | |
105 | * 5) Then when finished (or reset): | |
a4082843 | 106 | * stop_device |
60396183 EG |
107 | * |
108 | * 6) Eventually, the free function will be called. | |
109 | */ | |
110 | ||
60396183 EG |
111 | /** |
112 | * DOC: Host command section | |
113 | * | |
0d365ae5 | 114 | * A host command is a command issued by the upper layer to the fw. There are |
60396183 EG |
115 | * several versions of fw that have several APIs. The transport layer is |
116 | * completely agnostic to these differences. | |
0d365ae5 | 117 | * The transport does provide helper functionality (i.e. SYNC / ASYNC mode), |
60396183 | 118 | */ |
f8d7c1a1 JB |
119 | #define SEQ_TO_QUEUE(s) (((s) >> 8) & 0x1f) |
120 | #define QUEUE_TO_SEQ(q) (((q) & 0x1f) << 8) | |
121 | #define SEQ_TO_INDEX(s) ((s) & 0xff) | |
122 | #define INDEX_TO_SEQ(i) ((i) & 0xff) | |
123 | #define SEQ_RX_FRAME cpu_to_le16(0x8000) | |
124 | ||
ab02165c AE |
125 | /* |
126 | * those functions retrieve specific information from | |
127 | * the id field in the iwl_host_cmd struct which contains | |
128 | * the command id, the group id and the version of the command | |
129 | * and vice versa | |
130 | */ | |
131 | static inline u8 iwl_cmd_opcode(u32 cmdid) | |
132 | { | |
133 | return cmdid & 0xFF; | |
134 | } | |
135 | ||
136 | static inline u8 iwl_cmd_groupid(u32 cmdid) | |
137 | { | |
138 | return ((cmdid & 0xFF00) >> 8); | |
139 | } | |
140 | ||
141 | static inline u8 iwl_cmd_version(u32 cmdid) | |
142 | { | |
143 | return ((cmdid & 0xFF0000) >> 16); | |
144 | } | |
145 | ||
146 | static inline u32 iwl_cmd_id(u8 opcode, u8 groupid, u8 version) | |
147 | { | |
148 | return opcode + (groupid << 8) + (version << 16); | |
149 | } | |
150 | ||
6eb031d2 SS |
151 | /* make u16 wide id out of u8 group and opcode */ |
152 | #define WIDE_ID(grp, opcode) ((grp << 8) | opcode) | |
153 | ||
88742c9e JB |
154 | /* due to the conversion, this group is special; new groups |
155 | * should be defined in the appropriate fw-api header files | |
156 | */ | |
157 | #define IWL_ALWAYS_LONG_GROUP 1 | |
158 | ||
f8d7c1a1 JB |
159 | /** |
160 | * struct iwl_cmd_header | |
161 | * | |
162 | * This header format appears in the beginning of each command sent from the | |
163 | * driver, and each response/notification received from uCode. | |
164 | */ | |
165 | struct iwl_cmd_header { | |
166 | u8 cmd; /* Command ID: REPLY_RXON, etc. */ | |
ab02165c | 167 | u8 group_id; |
f8d7c1a1 JB |
168 | /* |
169 | * The driver sets up the sequence number to values of its choosing. | |
170 | * uCode does not use this value, but passes it back to the driver | |
171 | * when sending the response to each driver-originated command, so | |
172 | * the driver can match the response to the command. Since the values | |
173 | * don't get used by uCode, the driver may set up an arbitrary format. | |
174 | * | |
175 | * There is one exception: uCode sets bit 15 when it originates | |
176 | * the response/notification, i.e. when the response/notification | |
177 | * is not a direct response to a command sent by the driver. For | |
178 | * example, uCode issues REPLY_RX when it sends a received frame | |
179 | * to the driver; it is not a direct response to any driver command. | |
180 | * | |
181 | * The Linux driver uses the following format: | |
182 | * | |
183 | * 0:7 tfd index - position within TX queue | |
184 | * 8:12 TX queue id | |
185 | * 13:14 reserved | |
186 | * 15 unsolicited RX or uCode-originated notification | |
187 | */ | |
188 | __le16 sequence; | |
189 | } __packed; | |
190 | ||
ab02165c AE |
191 | /** |
192 | * struct iwl_cmd_header_wide | |
193 | * | |
194 | * This header format appears in the beginning of each command sent from the | |
195 | * driver, and each response/notification received from uCode. | |
196 | * this is the wide version that contains more information about the command | |
197 | * like length, version and command type | |
198 | */ | |
199 | struct iwl_cmd_header_wide { | |
200 | u8 cmd; | |
201 | u8 group_id; | |
202 | __le16 sequence; | |
203 | __le16 length; | |
204 | u8 reserved; | |
205 | u8 version; | |
206 | } __packed; | |
207 | ||
f8d7c1a1 | 208 | #define FH_RSCSR_FRAME_SIZE_MSK 0x00003FFF /* bits 0-13 */ |
0c19744c JB |
209 | #define FH_RSCSR_FRAME_INVALID 0x55550000 |
210 | #define FH_RSCSR_FRAME_ALIGN 0x40 | |
f8d7c1a1 JB |
211 | |
212 | struct iwl_rx_packet { | |
213 | /* | |
214 | * The first 4 bytes of the RX frame header contain both the RX frame | |
215 | * size and some flags. | |
216 | * Bit fields: | |
217 | * 31: flag flush RB request | |
218 | * 30: flag ignore TC (terminal counter) request | |
219 | * 29: flag fast IRQ request | |
220 | * 28-14: Reserved | |
221 | * 13-00: RX frame size | |
222 | */ | |
223 | __le32 len_n_flags; | |
224 | struct iwl_cmd_header hdr; | |
225 | u8 data[]; | |
226 | } __packed; | |
522376d2 | 227 | |
65b30348 JB |
228 | static inline u32 iwl_rx_packet_len(const struct iwl_rx_packet *pkt) |
229 | { | |
230 | return le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; | |
231 | } | |
232 | ||
233 | static inline u32 iwl_rx_packet_payload_len(const struct iwl_rx_packet *pkt) | |
234 | { | |
235 | return iwl_rx_packet_len(pkt) - sizeof(pkt->hdr); | |
236 | } | |
237 | ||
60396183 EG |
238 | /** |
239 | * enum CMD_MODE - how to send the host commands ? | |
240 | * | |
e89044d7 | 241 | * @CMD_ASYNC: Return right away and don't wait for the response |
a1022927 EG |
242 | * @CMD_WANT_SKB: Not valid with CMD_ASYNC. The caller needs the buffer of |
243 | * the response. The caller needs to call iwl_free_resp when done. | |
98ee7783 | 244 | * @CMD_HIGH_PRIO: The command is high priority - it goes to the front of the |
0d365ae5 | 245 | * command queue, but after other high priority commands. Valid only |
98ee7783 AN |
246 | * with CMD_ASYNC. |
247 | * @CMD_SEND_IN_IDLE: The command should be sent even when the trans is idle. | |
248 | * @CMD_MAKE_TRANS_IDLE: The command response should mark the trans as idle. | |
249 | * @CMD_WAKE_UP_TRANS: The command response should wake up the trans | |
250 | * (i.e. mark it as non-idle). | |
60396183 EG |
251 | */ |
252 | enum CMD_MODE { | |
4a4ee101 JB |
253 | CMD_ASYNC = BIT(0), |
254 | CMD_WANT_SKB = BIT(1), | |
4f59334b | 255 | CMD_SEND_IN_RFKILL = BIT(2), |
98ee7783 AN |
256 | CMD_HIGH_PRIO = BIT(3), |
257 | CMD_SEND_IN_IDLE = BIT(4), | |
258 | CMD_MAKE_TRANS_IDLE = BIT(5), | |
259 | CMD_WAKE_UP_TRANS = BIT(6), | |
522376d2 EG |
260 | }; |
261 | ||
262 | #define DEF_CMD_PAYLOAD_SIZE 320 | |
263 | ||
264 | /** | |
265 | * struct iwl_device_cmd | |
266 | * | |
267 | * For allocation of the command and tx queues, this establishes the overall | |
268 | * size of the largest command we send to uCode, except for commands that | |
269 | * aren't fully copied and use other TFD space. | |
270 | */ | |
271 | struct iwl_device_cmd { | |
ab02165c AE |
272 | union { |
273 | struct { | |
274 | struct iwl_cmd_header hdr; /* uCode API */ | |
275 | u8 payload[DEF_CMD_PAYLOAD_SIZE]; | |
276 | }; | |
277 | struct { | |
278 | struct iwl_cmd_header_wide hdr_wide; | |
279 | u8 payload_wide[DEF_CMD_PAYLOAD_SIZE - | |
280 | sizeof(struct iwl_cmd_header_wide) + | |
281 | sizeof(struct iwl_cmd_header)]; | |
282 | }; | |
283 | }; | |
522376d2 EG |
284 | } __packed; |
285 | ||
286 | #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd)) | |
287 | ||
1afbfb60 JB |
288 | /* |
289 | * number of transfer buffers (fragments) per transmit frame descriptor; | |
290 | * this is just the driver's idea, the hardware supports 20 | |
291 | */ | |
292 | #define IWL_MAX_CMD_TBS_PER_TFD 2 | |
522376d2 | 293 | |
60396183 EG |
294 | /** |
295 | * struct iwl_hcmd_dataflag - flag for each one of the chunks of the command | |
296 | * | |
f4feb8ac | 297 | * @IWL_HCMD_DFL_NOCOPY: By default, the command is copied to the host command's |
60396183 | 298 | * ring. The transport layer doesn't map the command's buffer to DMA, but |
e89044d7 | 299 | * rather copies it to a previously allocated DMA buffer. This flag tells |
60396183 | 300 | * the transport layer not to copy the command, but to map the existing |
3e2c1592 JB |
301 | * buffer (that is passed in) instead. This saves the memcpy and allows |
302 | * commands that are bigger than the fixed buffer to be submitted. | |
303 | * Note that a TFD entry after a NOCOPY one cannot be a normal copied one. | |
f4feb8ac JB |
304 | * @IWL_HCMD_DFL_DUP: Only valid without NOCOPY, duplicate the memory for this |
305 | * chunk internally and free it again after the command completes. This | |
306 | * can (currently) be used only once per command. | |
3e2c1592 | 307 | * Note that a TFD entry after a DUP one cannot be a normal copied one. |
60396183 | 308 | */ |
522376d2 EG |
309 | enum iwl_hcmd_dataflag { |
310 | IWL_HCMD_DFL_NOCOPY = BIT(0), | |
f4feb8ac | 311 | IWL_HCMD_DFL_DUP = BIT(1), |
522376d2 EG |
312 | }; |
313 | ||
314 | /** | |
315 | * struct iwl_host_cmd - Host command to the uCode | |
60396183 | 316 | * |
522376d2 | 317 | * @data: array of chunks that composes the data of the host command |
65b94a4a JB |
318 | * @resp_pkt: response packet, if %CMD_WANT_SKB was set |
319 | * @_rx_page_order: (internally used to free response packet) | |
320 | * @_rx_page_addr: (internally used to free response packet) | |
60396183 | 321 | * @flags: can be CMD_* |
e89044d7 | 322 | * @len: array of the lengths of the chunks in data |
60396183 | 323 | * @dataflags: IWL_HCMD_DFL_* |
ab02165c AE |
324 | * @id: command id of the host command, for wide commands encoding the |
325 | * version and group as well | |
522376d2 EG |
326 | */ |
327 | struct iwl_host_cmd { | |
1afbfb60 | 328 | const void *data[IWL_MAX_CMD_TBS_PER_TFD]; |
65b94a4a JB |
329 | struct iwl_rx_packet *resp_pkt; |
330 | unsigned long _rx_page_addr; | |
331 | u32 _rx_page_order; | |
247c61d6 | 332 | |
522376d2 | 333 | u32 flags; |
ab02165c | 334 | u32 id; |
1afbfb60 JB |
335 | u16 len[IWL_MAX_CMD_TBS_PER_TFD]; |
336 | u8 dataflags[IWL_MAX_CMD_TBS_PER_TFD]; | |
522376d2 | 337 | }; |
41c50542 | 338 | |
65b94a4a JB |
339 | static inline void iwl_free_resp(struct iwl_host_cmd *cmd) |
340 | { | |
341 | free_pages(cmd->_rx_page_addr, cmd->_rx_page_order); | |
342 | } | |
343 | ||
930dfd5f JB |
344 | struct iwl_rx_cmd_buffer { |
345 | struct page *_page; | |
0c19744c JB |
346 | int _offset; |
347 | bool _page_stolen; | |
d13f1862 | 348 | u32 _rx_page_order; |
ed90542b | 349 | unsigned int truesize; |
930dfd5f JB |
350 | }; |
351 | ||
352 | static inline void *rxb_addr(struct iwl_rx_cmd_buffer *r) | |
353 | { | |
0c19744c JB |
354 | return (void *)((unsigned long)page_address(r->_page) + r->_offset); |
355 | } | |
356 | ||
357 | static inline int rxb_offset(struct iwl_rx_cmd_buffer *r) | |
358 | { | |
359 | return r->_offset; | |
930dfd5f JB |
360 | } |
361 | ||
362 | static inline struct page *rxb_steal_page(struct iwl_rx_cmd_buffer *r) | |
363 | { | |
0c19744c JB |
364 | r->_page_stolen = true; |
365 | get_page(r->_page); | |
366 | return r->_page; | |
930dfd5f JB |
367 | } |
368 | ||
d13f1862 EG |
369 | static inline void iwl_free_rxb(struct iwl_rx_cmd_buffer *r) |
370 | { | |
371 | __free_pages(r->_page, r->_rx_page_order); | |
372 | } | |
373 | ||
d663ee73 JB |
374 | #define MAX_NO_RECLAIM_CMDS 6 |
375 | ||
ff110c8f GG |
376 | #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo)))) |
377 | ||
9eae88fa JB |
378 | /* |
379 | * Maximum number of HW queues the transport layer | |
380 | * currently supports | |
381 | */ | |
382 | #define IWL_MAX_HW_QUEUES 32 | |
b04db9ac EG |
383 | #define IWL_MAX_TID_COUNT 8 |
384 | #define IWL_FRAME_LIMIT 64 | |
9eae88fa | 385 | |
ddaf5a5b JB |
386 | /** |
387 | * enum iwl_wowlan_status - WoWLAN image/device status | |
388 | * @IWL_D3_STATUS_ALIVE: firmware is still running after resume | |
389 | * @IWL_D3_STATUS_RESET: device was reset while suspended | |
390 | */ | |
391 | enum iwl_d3_status { | |
392 | IWL_D3_STATUS_ALIVE, | |
393 | IWL_D3_STATUS_RESET, | |
394 | }; | |
395 | ||
eb7ff77e AN |
396 | /** |
397 | * enum iwl_trans_status: transport status flags | |
398 | * @STATUS_SYNC_HCMD_ACTIVE: a SYNC command is being processed | |
399 | * @STATUS_DEVICE_ENABLED: APM is enabled | |
400 | * @STATUS_TPOWER_PMI: the device might be asleep (need to wake it up) | |
401 | * @STATUS_INT_ENABLED: interrupts are enabled | |
402 | * @STATUS_RFKILL: the HW RFkill switch is in KILL position | |
403 | * @STATUS_FW_ERROR: the fw is in error state | |
98ee7783 AN |
404 | * @STATUS_TRANS_GOING_IDLE: shutting down the trans, only special commands |
405 | * are sent | |
406 | * @STATUS_TRANS_IDLE: the trans is idle - general commands are not to be sent | |
eb7ff77e AN |
407 | */ |
408 | enum iwl_trans_status { | |
409 | STATUS_SYNC_HCMD_ACTIVE, | |
410 | STATUS_DEVICE_ENABLED, | |
411 | STATUS_TPOWER_PMI, | |
412 | STATUS_INT_ENABLED, | |
413 | STATUS_RFKILL, | |
414 | STATUS_FW_ERROR, | |
98ee7783 AN |
415 | STATUS_TRANS_GOING_IDLE, |
416 | STATUS_TRANS_IDLE, | |
eb7ff77e AN |
417 | }; |
418 | ||
92d743ae MV |
419 | /** |
420 | * struct iwl_trans_config - transport configuration | |
421 | * | |
422 | * @op_mode: pointer to the upper layer. | |
c6f600fc MV |
423 | * @cmd_queue: the index of the command queue. |
424 | * Must be set before start_fw. | |
b04db9ac | 425 | * @cmd_fifo: the fifo for host commands |
4cf677fd | 426 | * @cmd_q_wdg_timeout: the timeout of the watchdog timer for the command queue. |
d663ee73 JB |
427 | * @no_reclaim_cmds: Some devices erroneously don't set the |
428 | * SEQ_RX_FRAME bit on some notifications, this is the | |
429 | * list of such notifications to filter. Max length is | |
430 | * %MAX_NO_RECLAIM_CMDS. | |
431 | * @n_no_reclaim_cmds: # of commands in list | |
b2cf410c JB |
432 | * @rx_buf_size_8k: 8 kB RX buffer size needed for A-MSDUs, |
433 | * if unset 4k will be the RX buffer size | |
046db346 EG |
434 | * @bc_table_dword: set to true if the BC table expects the byte count to be |
435 | * in DWORD (as opposed to bytes) | |
3a736bcb | 436 | * @scd_set_active: should the transport configure the SCD for HCMD queue |
ab02165c | 437 | * @wide_cmd_header: firmware supports wide host command header |
d9fb6465 JB |
438 | * @command_names: array of command names, must be 256 entries |
439 | * (one for each command); for debugging only | |
b4821767 LK |
440 | * @sdio_adma_addr: the default address to set for the ADMA in SDIO mode until |
441 | * we get the ALIVE from the uCode | |
92d743ae MV |
442 | */ |
443 | struct iwl_trans_config { | |
444 | struct iwl_op_mode *op_mode; | |
9eae88fa | 445 | |
c6f600fc | 446 | u8 cmd_queue; |
b04db9ac | 447 | u8 cmd_fifo; |
4cf677fd | 448 | unsigned int cmd_q_wdg_timeout; |
d663ee73 | 449 | const u8 *no_reclaim_cmds; |
84cf0e62 | 450 | unsigned int n_no_reclaim_cmds; |
b2cf410c JB |
451 | |
452 | bool rx_buf_size_8k; | |
046db346 | 453 | bool bc_table_dword; |
3a736bcb | 454 | bool scd_set_active; |
ab02165c | 455 | bool wide_cmd_header; |
e5209263 | 456 | const char *const *command_names; |
b4821767 LK |
457 | |
458 | u32 sdio_adma_addr; | |
92d743ae MV |
459 | }; |
460 | ||
48eb7b34 EG |
461 | struct iwl_trans_dump_data { |
462 | u32 len; | |
463 | u8 data[]; | |
464 | }; | |
465 | ||
87ce05a2 EG |
466 | struct iwl_trans; |
467 | ||
fea7795f JB |
468 | struct iwl_trans_txq_scd_cfg { |
469 | u8 fifo; | |
470 | s8 sta_id; | |
471 | u8 tid; | |
64ba8930 | 472 | bool aggregate; |
fea7795f JB |
473 | int frame_limit; |
474 | }; | |
475 | ||
41c50542 EG |
476 | /** |
477 | * struct iwl_trans_ops - transport specific operations | |
60396183 EG |
478 | * |
479 | * All the handlers MUST be implemented | |
480 | * | |
8d193ca2 EH |
481 | * @start_hw: starts the HW. If low_power is true, the NIC needs to be taken |
482 | * out of a low power state. From that point on, the HW can send | |
483 | * interrupts. May sleep. | |
a4082843 | 484 | * @op_mode_leave: Turn off the HW RF kill indication if on |
60396183 | 485 | * May sleep |
cf614297 | 486 | * @start_fw: allocates and inits all the resources for the transport |
60396183 EG |
487 | * layer. Also kick a fw image. |
488 | * May sleep | |
adca1235 EG |
489 | * @fw_alive: called when the fw sends alive notification. If the fw provides |
490 | * the SCD base address in SRAM, then provide it here, or 0 otherwise. | |
60396183 | 491 | * May sleep |
a4082843 | 492 | * @stop_device: stops the whole device (embedded CPU put to reset) and stops |
8d193ca2 EH |
493 | * the HW. If low_power is true, the NIC will be put in low power state. |
494 | * From that point on, the HW will be stopped but will still issue an | |
495 | * interrupt if the HW RF kill switch is triggered. | |
496 | * This callback must do the right thing and not crash even if %start_hw() | |
497 | * was called but not &start_fw(). May sleep. | |
ddaf5a5b | 498 | * @d3_suspend: put the device into the correct mode for WoWLAN during |
2dd4f9f7 JB |
499 | * suspend. This is optional, if not implemented WoWLAN will not be |
500 | * supported. This callback may sleep. | |
ddaf5a5b JB |
501 | * @d3_resume: resume the device after WoWLAN, enabling the opmode to |
502 | * talk to the WoWLAN image to get its status. This is optional, if not | |
503 | * implemented WoWLAN will not be supported. This callback may sleep. | |
f946b529 EG |
504 | * @send_cmd:send a host command. Must return -ERFKILL if RFkill is asserted. |
505 | * If RFkill is asserted in the middle of a SYNC host command, it must | |
506 | * return -ERFKILL straight away. | |
a1022927 | 507 | * May sleep only if CMD_ASYNC is not set |
41c50542 | 508 | * @tx: send an skb |
60396183 | 509 | * Must be atomic |
a0eaad71 | 510 | * @reclaim: free packet until ssn. Returns a list of freed packets. |
60396183 | 511 | * Must be atomic |
b04db9ac EG |
512 | * @txq_enable: setup a queue. To setup an AC queue, use the |
513 | * iwl_trans_ac_txq_enable wrapper. fw_alive must have been called before | |
d4578ea8 JB |
514 | * this one. The op_mode must not configure the HCMD queue. The scheduler |
515 | * configuration may be %NULL, in which case the hardware will not be | |
516 | * configured. May sleep. | |
d0624be6 | 517 | * @txq_disable: de-configure a Tx queue to send AMPDUs |
b0b46192 | 518 | * Must be atomic |
3cafdbe6 | 519 | * @wait_tx_queue_empty: wait until tx queues are empty. May sleep. |
e0b8d405 EG |
520 | * @freeze_txq_timer: prevents the timer of the queue from firing until the |
521 | * queue is set to awake. Must be atomic. | |
87e5666c EG |
522 | * @dbgfs_register: add the dbgfs files under this directory. Files will be |
523 | * automatically deleted. | |
03905495 EG |
524 | * @write8: write a u8 to a register at offset ofs from the BAR |
525 | * @write32: write a u32 to a register at offset ofs from the BAR | |
526 | * @read32: read a u32 register at offset ofs from the BAR | |
6a06b6c1 EG |
527 | * @read_prph: read a DWORD from a periphery register |
528 | * @write_prph: write a DWORD to a periphery register | |
4fd442db | 529 | * @read_mem: read device's SRAM in DWORD |
01387ffd EG |
530 | * @write_mem: write device's SRAM in DWORD. If %buf is %NULL, then the memory |
531 | * will be zeroed. | |
c6f600fc | 532 | * @configure: configure parameters required by the transport layer from |
3dc420be EG |
533 | * the op_mode. May be called several times before start_fw, can't be |
534 | * called after that. | |
47107e84 | 535 | * @set_pmi: set the power pmi state |
e56b04ef LE |
536 | * @grab_nic_access: wake the NIC to be able to access non-HBUS regs. |
537 | * Sleeping is not allowed between grab_nic_access and | |
538 | * release_nic_access. | |
539 | * @release_nic_access: let the NIC go to sleep. The "flags" parameter | |
540 | * must be the same one that was sent before to the grab_nic_access. | |
e139dc4a | 541 | * @set_bits_mask - set SRAM register according to value and mask. |
440c411d EP |
542 | * @ref: grab a reference to the transport/FW layers, disallowing |
543 | * certain low power states | |
544 | * @unref: release a reference previously taken with @ref. Note that | |
545 | * initially the reference count is 1, making an initial @unref | |
546 | * necessary to allow low power states. | |
48eb7b34 EG |
547 | * @dump_data: return a vmalloc'ed buffer with debug data, maybe containing last |
548 | * TX'ed commands and similar. The buffer will be vfree'd by the caller. | |
4d075007 | 549 | * Note that the transport must fill in the proper file headers. |
41c50542 EG |
550 | */ |
551 | struct iwl_trans_ops { | |
552 | ||
8d193ca2 | 553 | int (*start_hw)(struct iwl_trans *iwl_trans, bool low_power); |
a4082843 | 554 | void (*op_mode_leave)(struct iwl_trans *iwl_trans); |
6ae02f3e EG |
555 | int (*start_fw)(struct iwl_trans *trans, const struct fw_img *fw, |
556 | bool run_in_rfkill); | |
91479b64 EH |
557 | int (*update_sf)(struct iwl_trans *trans, |
558 | struct iwl_sf_region *st_fwrd_space); | |
adca1235 | 559 | void (*fw_alive)(struct iwl_trans *trans, u32 scd_addr); |
8d193ca2 | 560 | void (*stop_device)(struct iwl_trans *trans, bool low_power); |
41c50542 | 561 | |
debff618 JB |
562 | void (*d3_suspend)(struct iwl_trans *trans, bool test); |
563 | int (*d3_resume)(struct iwl_trans *trans, enum iwl_d3_status *status, | |
564 | bool test); | |
2dd4f9f7 | 565 | |
6d8f6eeb | 566 | int (*send_cmd)(struct iwl_trans *trans, struct iwl_host_cmd *cmd); |
41c50542 | 567 | |
e13c0c59 | 568 | int (*tx)(struct iwl_trans *trans, struct sk_buff *skb, |
9eae88fa JB |
569 | struct iwl_device_cmd *dev_cmd, int queue); |
570 | void (*reclaim)(struct iwl_trans *trans, int queue, int ssn, | |
571 | struct sk_buff_head *skbs); | |
572 | ||
fea7795f | 573 | void (*txq_enable)(struct iwl_trans *trans, int queue, u16 ssn, |
4cf677fd EG |
574 | const struct iwl_trans_txq_scd_cfg *cfg, |
575 | unsigned int queue_wdg_timeout); | |
d4578ea8 JB |
576 | void (*txq_disable)(struct iwl_trans *trans, int queue, |
577 | bool configure_scd); | |
41c50542 | 578 | |
87e5666c | 579 | int (*dbgfs_register)(struct iwl_trans *trans, struct dentry* dir); |
3cafdbe6 | 580 | int (*wait_tx_queue_empty)(struct iwl_trans *trans, u32 txq_bm); |
e0b8d405 EG |
581 | void (*freeze_txq_timer)(struct iwl_trans *trans, unsigned long txqs, |
582 | bool freeze); | |
5fdda047 | 583 | |
03905495 EG |
584 | void (*write8)(struct iwl_trans *trans, u32 ofs, u8 val); |
585 | void (*write32)(struct iwl_trans *trans, u32 ofs, u32 val); | |
586 | u32 (*read32)(struct iwl_trans *trans, u32 ofs); | |
6a06b6c1 EG |
587 | u32 (*read_prph)(struct iwl_trans *trans, u32 ofs); |
588 | void (*write_prph)(struct iwl_trans *trans, u32 ofs, u32 val); | |
4fd442db EG |
589 | int (*read_mem)(struct iwl_trans *trans, u32 addr, |
590 | void *buf, int dwords); | |
591 | int (*write_mem)(struct iwl_trans *trans, u32 addr, | |
bf0fd5da | 592 | const void *buf, int dwords); |
c6f600fc MV |
593 | void (*configure)(struct iwl_trans *trans, |
594 | const struct iwl_trans_config *trans_cfg); | |
47107e84 | 595 | void (*set_pmi)(struct iwl_trans *trans, bool state); |
e56b04ef LE |
596 | bool (*grab_nic_access)(struct iwl_trans *trans, bool silent, |
597 | unsigned long *flags); | |
598 | void (*release_nic_access)(struct iwl_trans *trans, | |
599 | unsigned long *flags); | |
e139dc4a LE |
600 | void (*set_bits_mask)(struct iwl_trans *trans, u32 reg, u32 mask, |
601 | u32 value); | |
440c411d EP |
602 | void (*ref)(struct iwl_trans *trans); |
603 | void (*unref)(struct iwl_trans *trans); | |
c43fe907 | 604 | int (*suspend)(struct iwl_trans *trans); |
8e551e50 | 605 | void (*resume)(struct iwl_trans *trans); |
4d075007 | 606 | |
48eb7b34 | 607 | struct iwl_trans_dump_data *(*dump_data)(struct iwl_trans *trans); |
41c50542 EG |
608 | }; |
609 | ||
69655ebf EG |
610 | /** |
611 | * enum iwl_trans_state - state of the transport layer | |
612 | * | |
613 | * @IWL_TRANS_NO_FW: no fw has sent an alive response | |
614 | * @IWL_TRANS_FW_ALIVE: a fw has sent an alive response | |
615 | */ | |
616 | enum iwl_trans_state { | |
617 | IWL_TRANS_NO_FW = 0, | |
618 | IWL_TRANS_FW_ALIVE = 1, | |
619 | }; | |
620 | ||
0f8f93d6 EP |
621 | /** |
622 | * enum iwl_d0i3_mode - d0i3 mode | |
623 | * | |
624 | * @IWL_D0I3_MODE_OFF - d0i3 is disabled | |
625 | * @IWL_D0I3_MODE_ON_IDLE - enter d0i3 when device is idle | |
626 | * (e.g. no active references) | |
627 | * @IWL_D0I3_MODE_ON_SUSPEND - enter d0i3 only on suspend | |
628 | * (in case of 'any' trigger) | |
629 | */ | |
630 | enum iwl_d0i3_mode { | |
631 | IWL_D0I3_MODE_OFF = 0, | |
632 | IWL_D0I3_MODE_ON_IDLE, | |
633 | IWL_D0I3_MODE_ON_SUSPEND, | |
634 | }; | |
635 | ||
6fbfae8e EG |
636 | /** |
637 | * struct iwl_trans - transport common data | |
60396183 | 638 | * |
6fbfae8e | 639 | * @ops - pointer to iwl_trans_ops |
ed277c93 | 640 | * @op_mode - pointer to the op_mode |
035f7ff2 | 641 | * @cfg - pointer to the configuration |
eb7ff77e | 642 | * @status: a bit-mask of transport status flags |
a42a1844 | 643 | * @dev - pointer to struct device * that represents the device |
0d365ae5 | 644 | * @hw_id: a u32 with the ID of the device / sub-device. |
60396183 | 645 | * Set during transport allocation. |
9ca85961 | 646 | * @hw_id_str: a string with info about HW ID. Set during transport allocation. |
f6d0e9be | 647 | * @pm_support: set to true in start_hw if link pm is supported |
9180ac50 | 648 | * @ltr_enabled: set to true if the LTR is enabled |
59c647b6 EG |
649 | * @dev_cmd_pool: pool for Tx cmd allocation - for internal use only. |
650 | * The user should use iwl_trans_{alloc,free}_tx_cmd. | |
651 | * @dev_cmd_headroom: room needed for the transport's private use before the | |
652 | * device_cmd for Tx - for internal use only | |
653 | * The user should use iwl_trans_{alloc,free}_tx_cmd. | |
f042c2eb JB |
654 | * @rx_mpdu_cmd: MPDU RX command ID, must be assigned by opmode before |
655 | * starting the firmware, used for tracing | |
656 | * @rx_mpdu_cmd_hdr_size: used for tracing, amount of data before the | |
657 | * start of the 802.11 header in the @rx_mpdu_cmd | |
bcb079a1 | 658 | * @dflt_pwr_limit: default power limit fetched from the platform (ACPI) |
09e350f7 LK |
659 | * @dbg_dest_tlv: points to the destination TLV for debug |
660 | * @dbg_conf_tlv: array of pointers to configuration TLVs for debug | |
d2709ad7 | 661 | * @dbg_trigger_tlv: array of pointers to triggers TLVs for debug |
09e350f7 | 662 | * @dbg_dest_reg_num: num of reg_ops in %dbg_dest_tlv |
6fbfae8e | 663 | */ |
41c50542 EG |
664 | struct iwl_trans { |
665 | const struct iwl_trans_ops *ops; | |
ed277c93 | 666 | struct iwl_op_mode *op_mode; |
035f7ff2 | 667 | const struct iwl_cfg *cfg; |
69655ebf | 668 | enum iwl_trans_state state; |
eb7ff77e | 669 | unsigned long status; |
e6bb4c9c | 670 | |
a42a1844 | 671 | struct device *dev; |
08079a49 | 672 | u32 hw_rev; |
99673ee5 | 673 | u32 hw_id; |
9ca85961 | 674 | char hw_id_str[52]; |
a42a1844 | 675 | |
f042c2eb JB |
676 | u8 rx_mpdu_cmd, rx_mpdu_cmd_hdr_size; |
677 | ||
f6d0e9be | 678 | bool pm_support; |
9180ac50 | 679 | bool ltr_enabled; |
97b52cfd | 680 | |
59c647b6 EG |
681 | /* The following fields are internal only */ |
682 | struct kmem_cache *dev_cmd_pool; | |
683 | size_t dev_cmd_headroom; | |
3ec45882 | 684 | char dev_cmd_pool_name[50]; |
59c647b6 | 685 | |
9da987ac MV |
686 | struct dentry *dbgfs_dir; |
687 | ||
2bfb5092 JB |
688 | #ifdef CONFIG_LOCKDEP |
689 | struct lockdep_map sync_cmd_lockdep_map; | |
690 | #endif | |
691 | ||
bcb079a1 IY |
692 | u64 dflt_pwr_limit; |
693 | ||
09e350f7 | 694 | const struct iwl_fw_dbg_dest_tlv *dbg_dest_tlv; |
d2709ad7 EG |
695 | const struct iwl_fw_dbg_conf_tlv *dbg_conf_tlv[FW_DBG_CONF_MAX]; |
696 | struct iwl_fw_dbg_trigger_tlv * const *dbg_trigger_tlv; | |
09e350f7 LK |
697 | u8 dbg_dest_reg_num; |
698 | ||
0f8f93d6 EP |
699 | enum iwl_d0i3_mode d0i3_mode; |
700 | ||
54154618 EP |
701 | bool wowlan_d0i3; |
702 | ||
e6bb4c9c EG |
703 | /* pointer to trans specific struct */ |
704 | /*Ensure that this pointer will always be aligned to sizeof pointer */ | |
cbe6ab4e | 705 | char trans_specific[0] __aligned(sizeof(void *)); |
41c50542 EG |
706 | }; |
707 | ||
ed277c93 | 708 | static inline void iwl_trans_configure(struct iwl_trans *trans, |
92d743ae | 709 | const struct iwl_trans_config *trans_cfg) |
ed277c93 | 710 | { |
92d743ae | 711 | trans->op_mode = trans_cfg->op_mode; |
c6f600fc MV |
712 | |
713 | trans->ops->configure(trans, trans_cfg); | |
ed277c93 EG |
714 | } |
715 | ||
8d193ca2 | 716 | static inline int _iwl_trans_start_hw(struct iwl_trans *trans, bool low_power) |
e6bb4c9c | 717 | { |
60396183 EG |
718 | might_sleep(); |
719 | ||
8d193ca2 EH |
720 | return trans->ops->start_hw(trans, low_power); |
721 | } | |
722 | ||
723 | static inline int iwl_trans_start_hw(struct iwl_trans *trans) | |
724 | { | |
725 | return trans->ops->start_hw(trans, true); | |
e6bb4c9c EG |
726 | } |
727 | ||
a4082843 | 728 | static inline void iwl_trans_op_mode_leave(struct iwl_trans *trans) |
cc56feb2 | 729 | { |
60396183 EG |
730 | might_sleep(); |
731 | ||
a4082843 AN |
732 | if (trans->ops->op_mode_leave) |
733 | trans->ops->op_mode_leave(trans); | |
69655ebf | 734 | |
a4082843 | 735 | trans->op_mode = NULL; |
b4991f3f | 736 | |
69655ebf | 737 | trans->state = IWL_TRANS_NO_FW; |
cc56feb2 EG |
738 | } |
739 | ||
adca1235 | 740 | static inline void iwl_trans_fw_alive(struct iwl_trans *trans, u32 scd_addr) |
ed6a3803 | 741 | { |
60396183 EG |
742 | might_sleep(); |
743 | ||
69655ebf | 744 | trans->state = IWL_TRANS_FW_ALIVE; |
b04db9ac | 745 | |
adca1235 | 746 | trans->ops->fw_alive(trans, scd_addr); |
ed6a3803 EG |
747 | } |
748 | ||
0692fe41 | 749 | static inline int iwl_trans_start_fw(struct iwl_trans *trans, |
6ae02f3e EG |
750 | const struct fw_img *fw, |
751 | bool run_in_rfkill) | |
bdfbf092 | 752 | { |
cf614297 EG |
753 | might_sleep(); |
754 | ||
f042c2eb JB |
755 | WARN_ON_ONCE(!trans->rx_mpdu_cmd); |
756 | ||
efbf6e3b | 757 | clear_bit(STATUS_FW_ERROR, &trans->status); |
6ae02f3e | 758 | return trans->ops->start_fw(trans, fw, run_in_rfkill); |
bdfbf092 EG |
759 | } |
760 | ||
91479b64 EH |
761 | static inline int iwl_trans_update_sf(struct iwl_trans *trans, |
762 | struct iwl_sf_region *st_fwrd_space) | |
763 | { | |
764 | might_sleep(); | |
765 | ||
766 | if (trans->ops->update_sf) | |
767 | return trans->ops->update_sf(trans, st_fwrd_space); | |
768 | ||
769 | return 0; | |
770 | } | |
771 | ||
8d193ca2 EH |
772 | static inline void _iwl_trans_stop_device(struct iwl_trans *trans, |
773 | bool low_power) | |
bdfbf092 | 774 | { |
60396183 EG |
775 | might_sleep(); |
776 | ||
8d193ca2 | 777 | trans->ops->stop_device(trans, low_power); |
69655ebf EG |
778 | |
779 | trans->state = IWL_TRANS_NO_FW; | |
bdfbf092 EG |
780 | } |
781 | ||
8d193ca2 EH |
782 | static inline void iwl_trans_stop_device(struct iwl_trans *trans) |
783 | { | |
784 | _iwl_trans_stop_device(trans, true); | |
785 | } | |
786 | ||
debff618 | 787 | static inline void iwl_trans_d3_suspend(struct iwl_trans *trans, bool test) |
ddaf5a5b JB |
788 | { |
789 | might_sleep(); | |
debff618 | 790 | trans->ops->d3_suspend(trans, test); |
ddaf5a5b JB |
791 | } |
792 | ||
793 | static inline int iwl_trans_d3_resume(struct iwl_trans *trans, | |
debff618 JB |
794 | enum iwl_d3_status *status, |
795 | bool test) | |
2dd4f9f7 JB |
796 | { |
797 | might_sleep(); | |
debff618 | 798 | return trans->ops->d3_resume(trans, status, test); |
2dd4f9f7 JB |
799 | } |
800 | ||
440c411d EP |
801 | static inline void iwl_trans_ref(struct iwl_trans *trans) |
802 | { | |
803 | if (trans->ops->ref) | |
804 | trans->ops->ref(trans); | |
805 | } | |
806 | ||
807 | static inline void iwl_trans_unref(struct iwl_trans *trans) | |
808 | { | |
809 | if (trans->ops->unref) | |
810 | trans->ops->unref(trans); | |
811 | } | |
812 | ||
c43fe907 | 813 | static inline int iwl_trans_suspend(struct iwl_trans *trans) |
8e551e50 | 814 | { |
c43fe907 EP |
815 | if (!trans->ops->suspend) |
816 | return 0; | |
817 | ||
818 | return trans->ops->suspend(trans); | |
8e551e50 EP |
819 | } |
820 | ||
821 | static inline void iwl_trans_resume(struct iwl_trans *trans) | |
822 | { | |
823 | if (trans->ops->resume) | |
824 | trans->ops->resume(trans); | |
825 | } | |
826 | ||
48eb7b34 EG |
827 | static inline struct iwl_trans_dump_data * |
828 | iwl_trans_dump_data(struct iwl_trans *trans) | |
4d075007 JB |
829 | { |
830 | if (!trans->ops->dump_data) | |
48eb7b34 EG |
831 | return NULL; |
832 | return trans->ops->dump_data(trans); | |
4d075007 | 833 | } |
4d075007 | 834 | |
e6bb4c9c | 835 | static inline int iwl_trans_send_cmd(struct iwl_trans *trans, |
2bfb5092 | 836 | struct iwl_host_cmd *cmd) |
bdfbf092 | 837 | { |
2bfb5092 JB |
838 | int ret; |
839 | ||
fba1c627 EG |
840 | if (unlikely(!(cmd->flags & CMD_SEND_IN_RFKILL) && |
841 | test_bit(STATUS_RFKILL, &trans->status))) | |
842 | return -ERFKILL; | |
843 | ||
3fc07953 AN |
844 | if (unlikely(test_bit(STATUS_FW_ERROR, &trans->status))) |
845 | return -EIO; | |
846 | ||
f39a52bf | 847 | if (unlikely(trans->state != IWL_TRANS_FW_ALIVE)) { |
3c6acb61 | 848 | IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); |
8ca95995 EG |
849 | return -EIO; |
850 | } | |
69655ebf | 851 | |
2bfb5092 JB |
852 | if (!(cmd->flags & CMD_ASYNC)) |
853 | lock_map_acquire_read(&trans->sync_cmd_lockdep_map); | |
854 | ||
855 | ret = trans->ops->send_cmd(trans, cmd); | |
856 | ||
857 | if (!(cmd->flags & CMD_ASYNC)) | |
858 | lock_map_release(&trans->sync_cmd_lockdep_map); | |
859 | ||
860 | return ret; | |
bdfbf092 EG |
861 | } |
862 | ||
59c647b6 EG |
863 | static inline struct iwl_device_cmd * |
864 | iwl_trans_alloc_tx_cmd(struct iwl_trans *trans) | |
865 | { | |
866 | u8 *dev_cmd_ptr = kmem_cache_alloc(trans->dev_cmd_pool, GFP_ATOMIC); | |
867 | ||
868 | if (unlikely(dev_cmd_ptr == NULL)) | |
869 | return NULL; | |
870 | ||
871 | return (struct iwl_device_cmd *) | |
872 | (dev_cmd_ptr + trans->dev_cmd_headroom); | |
873 | } | |
874 | ||
875 | static inline void iwl_trans_free_tx_cmd(struct iwl_trans *trans, | |
876 | struct iwl_device_cmd *dev_cmd) | |
877 | { | |
878 | u8 *dev_cmd_ptr = (u8 *)dev_cmd - trans->dev_cmd_headroom; | |
879 | ||
880 | kmem_cache_free(trans->dev_cmd_pool, dev_cmd_ptr); | |
881 | } | |
882 | ||
e6bb4c9c | 883 | static inline int iwl_trans_tx(struct iwl_trans *trans, struct sk_buff *skb, |
9eae88fa | 884 | struct iwl_device_cmd *dev_cmd, int queue) |
a0eaad71 | 885 | { |
3fc07953 AN |
886 | if (unlikely(test_bit(STATUS_FW_ERROR, &trans->status))) |
887 | return -EIO; | |
888 | ||
f39a52bf | 889 | if (unlikely(trans->state != IWL_TRANS_FW_ALIVE)) |
3c6acb61 | 890 | IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); |
69655ebf | 891 | |
9eae88fa | 892 | return trans->ops->tx(trans, skb, dev_cmd, queue); |
a0eaad71 EG |
893 | } |
894 | ||
9eae88fa JB |
895 | static inline void iwl_trans_reclaim(struct iwl_trans *trans, int queue, |
896 | int ssn, struct sk_buff_head *skbs) | |
48d42c42 | 897 | { |
f39a52bf | 898 | if (unlikely(trans->state != IWL_TRANS_FW_ALIVE)) |
3c6acb61 | 899 | IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); |
69655ebf | 900 | |
9eae88fa | 901 | trans->ops->reclaim(trans, queue, ssn, skbs); |
48d42c42 EG |
902 | } |
903 | ||
d4578ea8 JB |
904 | static inline void iwl_trans_txq_disable(struct iwl_trans *trans, int queue, |
905 | bool configure_scd) | |
288712a6 | 906 | { |
d4578ea8 JB |
907 | trans->ops->txq_disable(trans, queue, configure_scd); |
908 | } | |
909 | ||
910 | static inline void | |
911 | iwl_trans_txq_enable_cfg(struct iwl_trans *trans, int queue, u16 ssn, | |
4cf677fd EG |
912 | const struct iwl_trans_txq_scd_cfg *cfg, |
913 | unsigned int queue_wdg_timeout) | |
d4578ea8 JB |
914 | { |
915 | might_sleep(); | |
916 | ||
917 | if (unlikely((trans->state != IWL_TRANS_FW_ALIVE))) | |
918 | IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); | |
919 | ||
4cf677fd | 920 | trans->ops->txq_enable(trans, queue, ssn, cfg, queue_wdg_timeout); |
288712a6 EG |
921 | } |
922 | ||
4beaf6c2 EG |
923 | static inline void iwl_trans_txq_enable(struct iwl_trans *trans, int queue, |
924 | int fifo, int sta_id, int tid, | |
4cf677fd EG |
925 | int frame_limit, u16 ssn, |
926 | unsigned int queue_wdg_timeout) | |
48d42c42 | 927 | { |
fea7795f JB |
928 | struct iwl_trans_txq_scd_cfg cfg = { |
929 | .fifo = fifo, | |
930 | .sta_id = sta_id, | |
931 | .tid = tid, | |
932 | .frame_limit = frame_limit, | |
64ba8930 | 933 | .aggregate = sta_id >= 0, |
fea7795f JB |
934 | }; |
935 | ||
4cf677fd | 936 | iwl_trans_txq_enable_cfg(trans, queue, ssn, &cfg, queue_wdg_timeout); |
48d42c42 EG |
937 | } |
938 | ||
4cf677fd EG |
939 | static inline |
940 | void iwl_trans_ac_txq_enable(struct iwl_trans *trans, int queue, int fifo, | |
941 | unsigned int queue_wdg_timeout) | |
b04db9ac | 942 | { |
d4578ea8 JB |
943 | struct iwl_trans_txq_scd_cfg cfg = { |
944 | .fifo = fifo, | |
945 | .sta_id = -1, | |
946 | .tid = IWL_MAX_TID_COUNT, | |
947 | .frame_limit = IWL_FRAME_LIMIT, | |
64ba8930 | 948 | .aggregate = false, |
d4578ea8 JB |
949 | }; |
950 | ||
4cf677fd | 951 | iwl_trans_txq_enable_cfg(trans, queue, 0, &cfg, queue_wdg_timeout); |
d4578ea8 JB |
952 | } |
953 | ||
e0b8d405 EG |
954 | static inline void iwl_trans_freeze_txq_timer(struct iwl_trans *trans, |
955 | unsigned long txqs, | |
956 | bool freeze) | |
957 | { | |
958 | if (unlikely(trans->state != IWL_TRANS_FW_ALIVE)) | |
959 | IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); | |
960 | ||
961 | if (trans->ops->freeze_txq_timer) | |
962 | trans->ops->freeze_txq_timer(trans, txqs, freeze); | |
963 | } | |
964 | ||
3cafdbe6 | 965 | static inline int iwl_trans_wait_tx_queue_empty(struct iwl_trans *trans, |
4cf677fd | 966 | u32 txqs) |
5f178cd2 | 967 | { |
f39a52bf | 968 | if (unlikely(trans->state != IWL_TRANS_FW_ALIVE)) |
3c6acb61 | 969 | IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); |
69655ebf | 970 | |
4cf677fd | 971 | return trans->ops->wait_tx_queue_empty(trans, txqs); |
5f178cd2 EG |
972 | } |
973 | ||
87e5666c | 974 | static inline int iwl_trans_dbgfs_register(struct iwl_trans *trans, |
4fd442db | 975 | struct dentry *dir) |
87e5666c EG |
976 | { |
977 | return trans->ops->dbgfs_register(trans, dir); | |
978 | } | |
979 | ||
03905495 EG |
980 | static inline void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val) |
981 | { | |
982 | trans->ops->write8(trans, ofs, val); | |
983 | } | |
984 | ||
985 | static inline void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val) | |
986 | { | |
987 | trans->ops->write32(trans, ofs, val); | |
988 | } | |
989 | ||
990 | static inline u32 iwl_trans_read32(struct iwl_trans *trans, u32 ofs) | |
991 | { | |
992 | return trans->ops->read32(trans, ofs); | |
993 | } | |
994 | ||
6a06b6c1 EG |
995 | static inline u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs) |
996 | { | |
997 | return trans->ops->read_prph(trans, ofs); | |
998 | } | |
999 | ||
1000 | static inline void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs, | |
1001 | u32 val) | |
1002 | { | |
1003 | return trans->ops->write_prph(trans, ofs, val); | |
1004 | } | |
1005 | ||
4fd442db EG |
1006 | static inline int iwl_trans_read_mem(struct iwl_trans *trans, u32 addr, |
1007 | void *buf, int dwords) | |
1008 | { | |
1009 | return trans->ops->read_mem(trans, addr, buf, dwords); | |
1010 | } | |
1011 | ||
1012 | #define iwl_trans_read_mem_bytes(trans, addr, buf, bufsize) \ | |
1013 | do { \ | |
1014 | if (__builtin_constant_p(bufsize)) \ | |
1015 | BUILD_BUG_ON((bufsize) % sizeof(u32)); \ | |
1016 | iwl_trans_read_mem(trans, addr, buf, (bufsize) / sizeof(u32));\ | |
1017 | } while (0) | |
1018 | ||
1019 | static inline u32 iwl_trans_read_mem32(struct iwl_trans *trans, u32 addr) | |
1020 | { | |
1021 | u32 value; | |
1022 | ||
1023 | if (WARN_ON(iwl_trans_read_mem(trans, addr, &value, 1))) | |
1024 | return 0xa5a5a5a5; | |
1025 | ||
1026 | return value; | |
1027 | } | |
1028 | ||
1029 | static inline int iwl_trans_write_mem(struct iwl_trans *trans, u32 addr, | |
bf0fd5da | 1030 | const void *buf, int dwords) |
4fd442db EG |
1031 | { |
1032 | return trans->ops->write_mem(trans, addr, buf, dwords); | |
1033 | } | |
1034 | ||
1035 | static inline u32 iwl_trans_write_mem32(struct iwl_trans *trans, u32 addr, | |
1036 | u32 val) | |
1037 | { | |
1038 | return iwl_trans_write_mem(trans, addr, &val, 1); | |
1039 | } | |
1040 | ||
47107e84 DF |
1041 | static inline void iwl_trans_set_pmi(struct iwl_trans *trans, bool state) |
1042 | { | |
128cb89e AN |
1043 | if (trans->ops->set_pmi) |
1044 | trans->ops->set_pmi(trans, state); | |
47107e84 DF |
1045 | } |
1046 | ||
e139dc4a LE |
1047 | static inline void |
1048 | iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg, u32 mask, u32 value) | |
1049 | { | |
1050 | trans->ops->set_bits_mask(trans, reg, mask, value); | |
1051 | } | |
1052 | ||
e56b04ef | 1053 | #define iwl_trans_grab_nic_access(trans, silent, flags) \ |
abae2386 | 1054 | __cond_lock(nic_access, \ |
e56b04ef | 1055 | likely((trans)->ops->grab_nic_access(trans, silent, flags))) |
7a65d170 | 1056 | |
abae2386 | 1057 | static inline void __releases(nic_access) |
e56b04ef | 1058 | iwl_trans_release_nic_access(struct iwl_trans *trans, unsigned long *flags) |
7a65d170 | 1059 | { |
e56b04ef | 1060 | trans->ops->release_nic_access(trans, flags); |
abae2386 | 1061 | __release(nic_access); |
7a65d170 EG |
1062 | } |
1063 | ||
2a988e98 AN |
1064 | static inline void iwl_trans_fw_error(struct iwl_trans *trans) |
1065 | { | |
1066 | if (WARN_ON_ONCE(!trans->op_mode)) | |
1067 | return; | |
1068 | ||
1069 | /* prevent double restarts due to the same erroneous FW */ | |
1070 | if (!test_and_set_bit(STATUS_FW_ERROR, &trans->status)) | |
1071 | iwl_op_mode_nic_error(trans->op_mode); | |
1072 | } | |
1073 | ||
7b501d10 JB |
1074 | /***************************************************** |
1075 | * transport helper functions | |
1076 | *****************************************************/ | |
1077 | struct iwl_trans *iwl_trans_alloc(unsigned int priv_size, | |
1078 | struct device *dev, | |
1079 | const struct iwl_cfg *cfg, | |
1080 | const struct iwl_trans_ops *ops, | |
1081 | size_t dev_cmd_headroom); | |
1082 | void iwl_trans_free(struct iwl_trans *trans); | |
1083 | ||
b52e7ea1 | 1084 | /***************************************************** |
d1ff5253 | 1085 | * driver (transport) register/unregister functions |
b52e7ea1 | 1086 | ******************************************************/ |
36a79223 EG |
1087 | int __must_check iwl_pci_register_driver(void); |
1088 | void iwl_pci_unregister_driver(void); | |
b52e7ea1 | 1089 | |
41c50542 | 1090 | #endif /* __iwl_trans_h__ */ |