iwlagn: remove bootstrap code
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-tx.c
CommitLineData
1053d35f
RR
1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
1053d35f
RR
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
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RR
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
fd4abac5 30#include <linux/etherdevice.h>
d43c36dc 31#include <linux/sched.h>
5a0e3ad6 32#include <linux/slab.h>
1053d35f
RR
33#include <net/mac80211.h>
34#include "iwl-eeprom.h"
35#include "iwl-dev.h"
36#include "iwl-core.h"
37#include "iwl-sta.h"
38#include "iwl-io.h"
39#include "iwl-helpers.h"
40
fd4abac5
TW
41/**
42 * iwl_txq_update_write_ptr - Send new write index to hardware
43 */
7bfedc59 44void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
fd4abac5
TW
45{
46 u32 reg = 0;
fd4abac5
TW
47 int txq_id = txq->q.id;
48
49 if (txq->need_update == 0)
7bfedc59 50 return;
fd4abac5 51
f81c1f48
WYG
52 if (priv->cfg->base_params->shadow_reg_enable) {
53 /* shadow register enabled */
54 iwl_write32(priv, HBUS_TARG_WRPTR,
55 txq->q.write_ptr | (txq_id << 8));
56 } else {
57 /* if we're trying to save power */
58 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
59 /* wake up nic if it's powered down ...
60 * uCode will wake up, and interrupt us again, so next
61 * time we'll skip this part. */
62 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
fd4abac5 63
f81c1f48
WYG
64 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
65 IWL_DEBUG_INFO(priv,
66 "Tx queue %d requesting wakeup,"
67 " GP1 = 0x%x\n", txq_id, reg);
68 iwl_set_bit(priv, CSR_GP_CNTRL,
69 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
70 return;
71 }
fd4abac5 72
f81c1f48 73 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
fd4abac5 74 txq->q.write_ptr | (txq_id << 8));
fd4abac5 75
f81c1f48
WYG
76 /*
77 * else not in power-save mode,
78 * uCode will never sleep when we're
79 * trying to tx (during RFKILL, we're not trying to tx).
80 */
81 } else
82 iwl_write32(priv, HBUS_TARG_WRPTR,
83 txq->q.write_ptr | (txq_id << 8));
84 }
fd4abac5 85 txq->need_update = 0;
fd4abac5 86}
fd4abac5 87
387f3381
SG
88/**
89 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
90 */
91void iwl_tx_queue_unmap(struct iwl_priv *priv, int txq_id)
92{
93 struct iwl_tx_queue *txq = &priv->txq[txq_id];
94 struct iwl_queue *q = &txq->q;
95
96 if (q->n_bd == 0)
97 return;
98
99 while (q->write_ptr != q->read_ptr) {
100 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
101 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
102 }
103}
104
1053d35f
RR
105/**
106 * iwl_tx_queue_free - Deallocate DMA queue.
107 * @txq: Transmit queue to deallocate.
108 *
109 * Empty queue by removing and destroying all BD's.
110 * Free all buffers.
111 * 0-fill, but do not free "txq" descriptor structure.
112 */
a8e74e27 113void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
1053d35f 114{
da99c4b6 115 struct iwl_tx_queue *txq = &priv->txq[txq_id];
f36d04ab 116 struct device *dev = &priv->pci_dev->dev;
71c55d90 117 int i;
1053d35f 118
387f3381 119 iwl_tx_queue_unmap(priv, txq_id);
1053d35f 120
1053d35f 121 /* De-alloc array of command/tx buffers */
961ba60a 122 for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
da99c4b6 123 kfree(txq->cmd[i]);
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RR
124
125 /* De-alloc circular buffer of TFDs */
126 if (txq->q.n_bd)
f36d04ab
SG
127 dma_free_coherent(dev, priv->hw_params.tfd_size *
128 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
1053d35f
RR
129
130 /* De-alloc array of per-TFD driver data */
131 kfree(txq->txb);
132 txq->txb = NULL;
133
c2acea8e
JB
134 /* deallocate arrays */
135 kfree(txq->cmd);
136 kfree(txq->meta);
137 txq->cmd = NULL;
138 txq->meta = NULL;
139
1053d35f
RR
140 /* 0-fill queue descriptor structure */
141 memset(txq, 0, sizeof(*txq));
142}
961ba60a
TW
143
144/**
387f3381 145 * iwl_cmd_queue_unmap - Unmap any remaining DMA mappings from command queue
961ba60a 146 */
387f3381 147void iwl_cmd_queue_unmap(struct iwl_priv *priv)
961ba60a 148{
13bb9483 149 struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
961ba60a 150 struct iwl_queue *q = &txq->q;
71c55d90 151 int i;
961ba60a
TW
152
153 if (q->n_bd == 0)
154 return;
155
387f3381 156 while (q->read_ptr != q->write_ptr) {
dd487449
ZY
157 i = get_cmd_index(q, q->read_ptr, 0);
158
3598e177 159 if (txq->meta[i].flags & CMD_MAPPED) {
387f3381
SG
160 pci_unmap_single(priv->pci_dev,
161 dma_unmap_addr(&txq->meta[i], mapping),
162 dma_unmap_len(&txq->meta[i], len),
163 PCI_DMA_BIDIRECTIONAL);
3598e177
SG
164 txq->meta[i].flags = 0;
165 }
dd487449 166
3598e177 167 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
dd487449 168 }
387f3381 169
3598e177
SG
170 i = q->n_window;
171 if (txq->meta[i].flags & CMD_MAPPED) {
dd487449 172 pci_unmap_single(priv->pci_dev,
2e724443
FT
173 dma_unmap_addr(&txq->meta[i], mapping),
174 dma_unmap_len(&txq->meta[i], len),
dd487449 175 PCI_DMA_BIDIRECTIONAL);
3598e177 176 txq->meta[i].flags = 0;
dd487449 177 }
387f3381
SG
178}
179
180/**
181 * iwl_cmd_queue_free - Deallocate DMA queue.
182 * @txq: Transmit queue to deallocate.
183 *
184 * Empty queue by removing and destroying all BD's.
185 * Free all buffers.
186 * 0-fill, but do not free "txq" descriptor structure.
187 */
188void iwl_cmd_queue_free(struct iwl_priv *priv)
189{
190 struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
191 struct device *dev = &priv->pci_dev->dev;
192 int i;
193
194 iwl_cmd_queue_unmap(priv);
dd487449 195
961ba60a
TW
196 /* De-alloc array of command/tx buffers */
197 for (i = 0; i <= TFD_CMD_SLOTS; i++)
198 kfree(txq->cmd[i]);
199
200 /* De-alloc circular buffer of TFDs */
201 if (txq->q.n_bd)
f36d04ab
SG
202 dma_free_coherent(dev, priv->hw_params.tfd_size * txq->q.n_bd,
203 txq->tfds, txq->q.dma_addr);
961ba60a 204
28142986
RC
205 /* deallocate arrays */
206 kfree(txq->cmd);
207 kfree(txq->meta);
208 txq->cmd = NULL;
209 txq->meta = NULL;
210
961ba60a
TW
211 /* 0-fill queue descriptor structure */
212 memset(txq, 0, sizeof(*txq));
213}
3e5d238f 214
fd4abac5
TW
215/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
216 * DMA services
217 *
218 * Theory of operation
219 *
220 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
221 * of buffer descriptors, each of which points to one or more data buffers for
222 * the device to read from or fill. Driver and device exchange status of each
223 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
224 * entries in each circular buffer, to protect against confusing empty and full
225 * queue states.
226 *
227 * The device reads or writes the data in the queues via the device's several
228 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
229 *
230 * For Tx queue, there are low mark and high mark limits. If, after queuing
231 * the packet for Tx, free space become < low mark, Tx queue stopped. When
232 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
233 * Tx queue resumed.
234 *
235 * See more detailed info in iwl-4965-hw.h.
236 ***************************************************/
237
238int iwl_queue_space(const struct iwl_queue *q)
239{
240 int s = q->read_ptr - q->write_ptr;
241
242 if (q->read_ptr > q->write_ptr)
243 s -= q->n_bd;
244
245 if (s <= 0)
246 s += q->n_window;
247 /* keep some reserve to not confuse empty and full situations */
248 s -= 2;
249 if (s < 0)
250 s = 0;
251 return s;
252}
fd4abac5
TW
253
254
1053d35f
RR
255/**
256 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
257 */
443cfd45 258static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
1053d35f
RR
259 int count, int slots_num, u32 id)
260{
261 q->n_bd = count;
262 q->n_window = slots_num;
263 q->id = id;
264
265 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
266 * and iwl_queue_dec_wrap are broken. */
267 BUG_ON(!is_power_of_2(count));
268
269 /* slots_num must be power-of-two size, otherwise
270 * get_cmd_index is broken. */
271 BUG_ON(!is_power_of_2(slots_num));
272
273 q->low_mark = q->n_window / 4;
274 if (q->low_mark < 4)
275 q->low_mark = 4;
276
277 q->high_mark = q->n_window / 8;
278 if (q->high_mark < 2)
279 q->high_mark = 2;
280
281 q->write_ptr = q->read_ptr = 0;
282
283 return 0;
284}
285
286/**
287 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
288 */
289static int iwl_tx_queue_alloc(struct iwl_priv *priv,
16466903 290 struct iwl_tx_queue *txq, u32 id)
1053d35f 291{
f36d04ab 292 struct device *dev = &priv->pci_dev->dev;
3978e5bc 293 size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
1053d35f
RR
294
295 /* Driver private data, only for Tx (not command) queues,
296 * not shared with device. */
13bb9483 297 if (id != priv->cmd_queue) {
519c7c41 298 txq->txb = kzalloc(sizeof(txq->txb[0]) *
1053d35f
RR
299 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
300 if (!txq->txb) {
15b1687c 301 IWL_ERR(priv, "kmalloc for auxiliary BD "
1053d35f
RR
302 "structures failed\n");
303 goto error;
304 }
3978e5bc 305 } else {
1053d35f 306 txq->txb = NULL;
3978e5bc 307 }
1053d35f
RR
308
309 /* Circular buffer of transmit frame descriptors (TFDs),
310 * shared with device */
f36d04ab
SG
311 txq->tfds = dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr,
312 GFP_KERNEL);
499b1883 313 if (!txq->tfds) {
3978e5bc 314 IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz);
1053d35f
RR
315 goto error;
316 }
317 txq->q.id = id;
318
319 return 0;
320
321 error:
322 kfree(txq->txb);
323 txq->txb = NULL;
324
325 return -ENOMEM;
326}
327
1053d35f
RR
328/**
329 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
330 */
a8e74e27
SO
331int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
332 int slots_num, u32 txq_id)
1053d35f 333{
da99c4b6 334 int i, len;
73b7d742 335 int ret;
c2acea8e 336 int actual_slots = slots_num;
1053d35f
RR
337
338 /*
339 * Alloc buffer array for commands (Tx or other types of commands).
13bb9483 340 * For the command queue (#4/#9), allocate command space + one big
1053d35f
RR
341 * command for scan, since scan command is very huge; the system will
342 * not have two scans at the same time, so only one is needed.
343 * For normal Tx queues (all other queues), no super-size command
344 * space is needed.
345 */
13bb9483 346 if (txq_id == priv->cmd_queue)
c2acea8e
JB
347 actual_slots++;
348
349 txq->meta = kzalloc(sizeof(struct iwl_cmd_meta) * actual_slots,
350 GFP_KERNEL);
351 txq->cmd = kzalloc(sizeof(struct iwl_device_cmd *) * actual_slots,
352 GFP_KERNEL);
353
354 if (!txq->meta || !txq->cmd)
355 goto out_free_arrays;
356
357 len = sizeof(struct iwl_device_cmd);
358 for (i = 0; i < actual_slots; i++) {
359 /* only happens for cmd queue */
360 if (i == slots_num)
89612124 361 len = IWL_MAX_CMD_SIZE;
da99c4b6 362
49898852 363 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
da99c4b6 364 if (!txq->cmd[i])
73b7d742 365 goto err;
da99c4b6 366 }
1053d35f
RR
367
368 /* Alloc driver data array and TFD circular buffer */
73b7d742
TW
369 ret = iwl_tx_queue_alloc(priv, txq, txq_id);
370 if (ret)
371 goto err;
1053d35f 372
1053d35f
RR
373 txq->need_update = 0;
374
1a716557 375 /*
ea9b307f
JB
376 * For the default queues 0-3, set up the swq_id
377 * already -- all others need to get one later
378 * (if they need one at all).
1a716557 379 */
ea9b307f
JB
380 if (txq_id < 4)
381 iwl_set_swq_id(txq, txq_id, txq_id);
45af8195 382
1053d35f
RR
383 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
384 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
385 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
386
387 /* Initialize queue's high/low-water marks, and head/tail indexes */
388 iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
389
390 /* Tell device where to find queue */
a8e74e27 391 priv->cfg->ops->lib->txq_init(priv, txq);
1053d35f
RR
392
393 return 0;
73b7d742 394err:
c2acea8e 395 for (i = 0; i < actual_slots; i++)
73b7d742 396 kfree(txq->cmd[i]);
c2acea8e
JB
397out_free_arrays:
398 kfree(txq->meta);
399 kfree(txq->cmd);
73b7d742 400
73b7d742 401 return -ENOMEM;
1053d35f 402}
a8e74e27 403
de0f60ea
ZY
404void iwl_tx_queue_reset(struct iwl_priv *priv, struct iwl_tx_queue *txq,
405 int slots_num, u32 txq_id)
406{
407 int actual_slots = slots_num;
408
13bb9483 409 if (txq_id == priv->cmd_queue)
de0f60ea
ZY
410 actual_slots++;
411
412 memset(txq->meta, 0, sizeof(struct iwl_cmd_meta) * actual_slots);
413
414 txq->need_update = 0;
415
416 /* Initialize queue's high/low-water marks, and head/tail indexes */
417 iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
418
419 /* Tell device where to find queue */
420 priv->cfg->ops->lib->txq_init(priv, txq);
421}
de0f60ea 422
fd4abac5
TW
423/*************** HOST COMMAND QUEUE FUNCTIONS *****/
424
425/**
426 * iwl_enqueue_hcmd - enqueue a uCode command
427 * @priv: device private data point
428 * @cmd: a point to the ucode command structure
429 *
430 * The function returns < 0 values to indicate the operation is
431 * failed. On success, it turns the index (> 0) of command in the
432 * command queue.
433 */
434int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
435{
13bb9483 436 struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
fd4abac5 437 struct iwl_queue *q = &txq->q;
c2acea8e
JB
438 struct iwl_device_cmd *out_cmd;
439 struct iwl_cmd_meta *out_meta;
fd4abac5 440 dma_addr_t phys_addr;
fd4abac5 441 unsigned long flags;
7bfedc59 442 int len;
f3674227
TW
443 u32 idx;
444 u16 fix_size;
0975cc8f 445 bool is_ct_kill = false;
fd4abac5
TW
446
447 cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
448 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
449
450 /* If any of the command structures end up being larger than
451 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
89612124
AK
452 * we will need to increase the size of the TFD entries
453 * Also, check to see if command buffer should not exceed the size
454 * of device_cmd and max_cmd_size. */
fd4abac5 455 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
c2acea8e 456 !(cmd->flags & CMD_SIZE_HUGE));
89612124 457 BUG_ON(fix_size > IWL_MAX_CMD_SIZE);
fd4abac5 458
7812b167 459 if (iwl_is_rfkill(priv) || iwl_is_ctkill(priv)) {
f2f21b49
RC
460 IWL_WARN(priv, "Not sending command - %s KILL\n",
461 iwl_is_rfkill(priv) ? "RF" : "CT");
fd4abac5
TW
462 return -EIO;
463 }
464
3598e177
SG
465 spin_lock_irqsave(&priv->hcmd_lock, flags);
466
c2acea8e 467 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
3598e177
SG
468 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
469
2d237f71 470 IWL_ERR(priv, "No space in command queue\n");
0975cc8f
WYG
471 if (priv->cfg->ops->lib->tt_ops.ct_kill_check) {
472 is_ct_kill =
473 priv->cfg->ops->lib->tt_ops.ct_kill_check(priv);
474 }
475 if (!is_ct_kill) {
7812b167
WYG
476 IWL_ERR(priv, "Restarting adapter due to queue full\n");
477 queue_work(priv->workqueue, &priv->restart);
478 }
fd4abac5
TW
479 return -ENOSPC;
480 }
481
c2acea8e 482 idx = get_cmd_index(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE);
da99c4b6 483 out_cmd = txq->cmd[idx];
c2acea8e
JB
484 out_meta = &txq->meta[idx];
485
3598e177
SG
486 if (WARN_ON(out_meta->flags & CMD_MAPPED)) {
487 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
488 return -ENOSPC;
489 }
490
8ce73f3a 491 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
3598e177 492 out_meta->flags = cmd->flags | CMD_MAPPED;
c2acea8e
JB
493 if (cmd->flags & CMD_WANT_SKB)
494 out_meta->source = cmd;
495 if (cmd->flags & CMD_ASYNC)
496 out_meta->callback = cmd->callback;
fd4abac5
TW
497
498 out_cmd->hdr.cmd = cmd->id;
fd4abac5
TW
499 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
500
501 /* At this point, the out_cmd now has all of the incoming cmd
502 * information */
503
504 out_cmd->hdr.flags = 0;
13bb9483 505 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(priv->cmd_queue) |
fd4abac5 506 INDEX_TO_SEQ(q->write_ptr));
c2acea8e 507 if (cmd->flags & CMD_SIZE_HUGE)
9734cb23 508 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
c2acea8e 509 len = sizeof(struct iwl_device_cmd);
89612124
AK
510 if (idx == TFD_CMD_SLOTS)
511 len = IWL_MAX_CMD_SIZE;
fd4abac5 512
ded2ae7c
EK
513#ifdef CONFIG_IWLWIFI_DEBUG
514 switch (out_cmd->hdr.cmd) {
515 case REPLY_TX_LINK_QUALITY_CMD:
516 case SENSITIVITY_CMD:
e1623446 517 IWL_DEBUG_HC_DUMP(priv, "Sending command %s (#%x), seq: 0x%04X, "
ded2ae7c
EK
518 "%d bytes at %d[%d]:%d\n",
519 get_cmd_string(out_cmd->hdr.cmd),
520 out_cmd->hdr.cmd,
521 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
13bb9483
JB
522 q->write_ptr, idx, priv->cmd_queue);
523 break;
ded2ae7c 524 default:
e1623446 525 IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, "
ded2ae7c
EK
526 "%d bytes at %d[%d]:%d\n",
527 get_cmd_string(out_cmd->hdr.cmd),
528 out_cmd->hdr.cmd,
529 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
13bb9483 530 q->write_ptr, idx, priv->cmd_queue);
ded2ae7c
EK
531 }
532#endif
fd4abac5
TW
533 txq->need_update = 1;
534
518099a8
SO
535 if (priv->cfg->ops->lib->txq_update_byte_cnt_tbl)
536 /* Set up entry in queue's byte count circular buffer */
537 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0);
fd4abac5 538
df833b1d
RC
539 phys_addr = pci_map_single(priv->pci_dev, &out_cmd->hdr,
540 fix_size, PCI_DMA_BIDIRECTIONAL);
2e724443
FT
541 dma_unmap_addr_set(out_meta, mapping, phys_addr);
542 dma_unmap_len_set(out_meta, len, fix_size);
df833b1d 543
be1a71a1
JB
544 trace_iwlwifi_dev_hcmd(priv, &out_cmd->hdr, fix_size, cmd->flags);
545
df833b1d
RC
546 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
547 phys_addr, fix_size, 1,
548 U32_PAD(cmd->len));
549
fd4abac5
TW
550 /* Increment and update queue's write index */
551 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
7bfedc59 552 iwl_txq_update_write_ptr(priv, txq);
fd4abac5
TW
553
554 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
7bfedc59 555 return idx;
fd4abac5
TW
556}
557
17b88929
TW
558/**
559 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
560 *
561 * When FW advances 'R' index, all entries between old and new 'R' index
562 * need to be reclaimed. As result, some free space forms. If there is
563 * enough free space (> low mark), wake the stack that feeds us.
564 */
499b1883
TW
565static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id,
566 int idx, int cmd_idx)
17b88929
TW
567{
568 struct iwl_tx_queue *txq = &priv->txq[txq_id];
569 struct iwl_queue *q = &txq->q;
570 int nfreed = 0;
571
499b1883 572 if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
15b1687c 573 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
17b88929 574 "is out of range [0-%d] %d %d.\n", txq_id,
499b1883 575 idx, q->n_bd, q->write_ptr, q->read_ptr);
17b88929
TW
576 return;
577 }
578
499b1883
TW
579 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
580 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
17b88929 581
499b1883 582 if (nfreed++ > 0) {
15b1687c 583 IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx,
17b88929
TW
584 q->write_ptr, q->read_ptr);
585 queue_work(priv->workqueue, &priv->restart);
586 }
da99c4b6 587
17b88929
TW
588 }
589}
590
591/**
592 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
593 * @rxb: Rx buffer to reclaim
594 *
595 * If an Rx buffer has an async callback associated with it the callback
596 * will be executed. The attached skb (if present) will only be freed
597 * if the callback returns 1
598 */
599void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
600{
2f301227 601 struct iwl_rx_packet *pkt = rxb_addr(rxb);
17b88929
TW
602 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
603 int txq_id = SEQ_TO_QUEUE(sequence);
604 int index = SEQ_TO_INDEX(sequence);
17b88929 605 int cmd_index;
9734cb23 606 bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
c2acea8e
JB
607 struct iwl_device_cmd *cmd;
608 struct iwl_cmd_meta *meta;
13bb9483 609 struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
3598e177
SG
610 unsigned long flags;
611 void (*callback) (struct iwl_priv *priv, struct iwl_device_cmd *cmd,
612 struct iwl_rx_packet *pkt);
613
17b88929
TW
614
615 /* If a Tx command is being handled and it isn't in the actual
616 * command queue then there a command routing bug has been introduced
617 * in the queue management code. */
13bb9483
JB
618 if (WARN(txq_id != priv->cmd_queue,
619 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
620 txq_id, priv->cmd_queue, sequence,
621 priv->txq[priv->cmd_queue].q.read_ptr,
622 priv->txq[priv->cmd_queue].q.write_ptr)) {
ec741164 623 iwl_print_hex_error(priv, pkt, 32);
55d6a3cd 624 return;
01ef9323 625 }
17b88929 626
3598e177
SG
627 spin_lock_irqsave(&priv->hcmd_lock, flags);
628
dd487449
ZY
629 cmd_index = get_cmd_index(&txq->q, index, huge);
630 cmd = txq->cmd[cmd_index];
631 meta = &txq->meta[cmd_index];
17b88929 632
c33de625 633 pci_unmap_single(priv->pci_dev,
2e724443
FT
634 dma_unmap_addr(meta, mapping),
635 dma_unmap_len(meta, len),
c33de625
RC
636 PCI_DMA_BIDIRECTIONAL);
637
3598e177 638 callback = NULL;
17b88929 639 /* Input error checking is done when commands are added to queue. */
c2acea8e 640 if (meta->flags & CMD_WANT_SKB) {
2f301227
ZY
641 meta->source->reply_page = (unsigned long)rxb_addr(rxb);
642 rxb->page = NULL;
3598e177
SG
643 } else
644 callback = meta->callback;
17b88929 645
499b1883 646 iwl_hcmd_queue_reclaim(priv, txq_id, index, cmd_index);
17b88929 647
c2acea8e 648 if (!(meta->flags & CMD_ASYNC)) {
17b88929 649 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
91dd6c27 650 IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command %s\n",
d2dfe6df 651 get_cmd_string(cmd->hdr.cmd));
17b88929
TW
652 wake_up_interruptible(&priv->wait_command_queue);
653 }
3598e177
SG
654
655 /* Mark as unmapped */
dd487449 656 meta->flags = 0;
3598e177
SG
657
658 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
659
660 if (callback)
661 callback(priv, cmd, pkt);
17b88929 662}
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