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1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
901069c7 | 3 | * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. |
1053d35f RR |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
1053d35f RR |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
fd4abac5 | 30 | #include <linux/etherdevice.h> |
d43c36dc | 31 | #include <linux/sched.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
1053d35f RR |
33 | #include <net/mac80211.h> |
34 | #include "iwl-eeprom.h" | |
214d14d4 | 35 | #include "iwl-agn.h" |
1053d35f RR |
36 | #include "iwl-dev.h" |
37 | #include "iwl-core.h" | |
38 | #include "iwl-sta.h" | |
39 | #include "iwl-io.h" | |
40 | #include "iwl-helpers.h" | |
41 | ||
fd4abac5 TW |
42 | /** |
43 | * iwl_txq_update_write_ptr - Send new write index to hardware | |
44 | */ | |
7bfedc59 | 45 | void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq) |
fd4abac5 TW |
46 | { |
47 | u32 reg = 0; | |
fd4abac5 TW |
48 | int txq_id = txq->q.id; |
49 | ||
50 | if (txq->need_update == 0) | |
7bfedc59 | 51 | return; |
fd4abac5 | 52 | |
f81c1f48 WYG |
53 | if (priv->cfg->base_params->shadow_reg_enable) { |
54 | /* shadow register enabled */ | |
55 | iwl_write32(priv, HBUS_TARG_WRPTR, | |
56 | txq->q.write_ptr | (txq_id << 8)); | |
57 | } else { | |
58 | /* if we're trying to save power */ | |
59 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { | |
60 | /* wake up nic if it's powered down ... | |
61 | * uCode will wake up, and interrupt us again, so next | |
62 | * time we'll skip this part. */ | |
63 | reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); | |
fd4abac5 | 64 | |
f81c1f48 WYG |
65 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { |
66 | IWL_DEBUG_INFO(priv, | |
67 | "Tx queue %d requesting wakeup," | |
68 | " GP1 = 0x%x\n", txq_id, reg); | |
69 | iwl_set_bit(priv, CSR_GP_CNTRL, | |
70 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
71 | return; | |
72 | } | |
fd4abac5 | 73 | |
f81c1f48 | 74 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, |
fd4abac5 | 75 | txq->q.write_ptr | (txq_id << 8)); |
fd4abac5 | 76 | |
f81c1f48 WYG |
77 | /* |
78 | * else not in power-save mode, | |
79 | * uCode will never sleep when we're | |
80 | * trying to tx (during RFKILL, we're not trying to tx). | |
81 | */ | |
82 | } else | |
83 | iwl_write32(priv, HBUS_TARG_WRPTR, | |
84 | txq->q.write_ptr | (txq_id << 8)); | |
85 | } | |
fd4abac5 | 86 | txq->need_update = 0; |
fd4abac5 | 87 | } |
fd4abac5 | 88 | |
214d14d4 JB |
89 | static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
90 | { | |
91 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
92 | ||
93 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
94 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
95 | addr |= | |
96 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
97 | ||
98 | return addr; | |
99 | } | |
100 | ||
101 | static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) | |
102 | { | |
103 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
104 | ||
105 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
106 | } | |
107 | ||
108 | static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, | |
109 | dma_addr_t addr, u16 len) | |
110 | { | |
111 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
112 | u16 hi_n_len = len << 4; | |
113 | ||
114 | put_unaligned_le32(addr, &tb->lo); | |
115 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
116 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
117 | ||
118 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
119 | ||
120 | tfd->num_tbs = idx + 1; | |
121 | } | |
122 | ||
123 | static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd) | |
124 | { | |
125 | return tfd->num_tbs & 0x1f; | |
126 | } | |
127 | ||
4ce7cc2b JB |
128 | static void iwlagn_unmap_tfd(struct iwl_priv *priv, struct iwl_cmd_meta *meta, |
129 | struct iwl_tfd *tfd) | |
214d14d4 | 130 | { |
214d14d4 | 131 | struct pci_dev *dev = priv->pci_dev; |
214d14d4 JB |
132 | int i; |
133 | int num_tbs; | |
134 | ||
214d14d4 JB |
135 | /* Sanity check on number of chunks */ |
136 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
137 | ||
138 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
139 | IWL_ERR(priv, "Too many chunks: %i\n", num_tbs); | |
140 | /* @todo issue fatal error, it is quite serious situation */ | |
141 | return; | |
142 | } | |
143 | ||
144 | /* Unmap tx_cmd */ | |
145 | if (num_tbs) | |
146 | pci_unmap_single(dev, | |
4ce7cc2b JB |
147 | dma_unmap_addr(meta, mapping), |
148 | dma_unmap_len(meta, len), | |
214d14d4 JB |
149 | PCI_DMA_BIDIRECTIONAL); |
150 | ||
151 | /* Unmap chunks, if any. */ | |
152 | for (i = 1; i < num_tbs; i++) | |
153 | pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i), | |
154 | iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE); | |
4ce7cc2b JB |
155 | } |
156 | ||
157 | /** | |
158 | * iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
159 | * @priv - driver private data | |
160 | * @txq - tx queue | |
161 | * | |
162 | * Does NOT advance any TFD circular buffer read/write indexes | |
163 | * Does NOT free the TFD itself (which is within circular buffer) | |
164 | */ | |
165 | void iwlagn_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq) | |
166 | { | |
167 | struct iwl_tfd *tfd_tmp = txq->tfds; | |
168 | int index = txq->q.read_ptr; | |
169 | ||
170 | iwlagn_unmap_tfd(priv, &txq->meta[index], &tfd_tmp[index]); | |
214d14d4 JB |
171 | |
172 | /* free SKB */ | |
173 | if (txq->txb) { | |
174 | struct sk_buff *skb; | |
175 | ||
176 | skb = txq->txb[txq->q.read_ptr].skb; | |
177 | ||
178 | /* can be called from irqs-disabled context */ | |
179 | if (skb) { | |
180 | dev_kfree_skb_any(skb); | |
181 | txq->txb[txq->q.read_ptr].skb = NULL; | |
182 | } | |
183 | } | |
184 | } | |
185 | ||
186 | int iwlagn_txq_attach_buf_to_tfd(struct iwl_priv *priv, | |
187 | struct iwl_tx_queue *txq, | |
188 | dma_addr_t addr, u16 len, | |
4c42db0f | 189 | u8 reset) |
214d14d4 JB |
190 | { |
191 | struct iwl_queue *q; | |
192 | struct iwl_tfd *tfd, *tfd_tmp; | |
193 | u32 num_tbs; | |
194 | ||
195 | q = &txq->q; | |
4ce7cc2b | 196 | tfd_tmp = txq->tfds; |
214d14d4 JB |
197 | tfd = &tfd_tmp[q->write_ptr]; |
198 | ||
199 | if (reset) | |
200 | memset(tfd, 0, sizeof(*tfd)); | |
201 | ||
202 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
203 | ||
204 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
205 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
206 | IWL_ERR(priv, "Error can not send more than %d chunks\n", | |
207 | IWL_NUM_OF_TBS); | |
208 | return -EINVAL; | |
209 | } | |
210 | ||
211 | if (WARN_ON(addr & ~DMA_BIT_MASK(36))) | |
212 | return -EINVAL; | |
213 | ||
214 | if (unlikely(addr & ~IWL_TX_DMA_MASK)) | |
215 | IWL_ERR(priv, "Unaligned address = %llx\n", | |
216 | (unsigned long long)addr); | |
217 | ||
218 | iwl_tfd_set_tb(tfd, num_tbs, addr, len); | |
219 | ||
220 | return 0; | |
221 | } | |
222 | ||
223 | /* | |
224 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
225 | * given Tx queue, and enable the DMA channel used for that queue. | |
226 | * | |
227 | * supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA | |
228 | * channels supported in hardware. | |
229 | */ | |
230 | static int iwlagn_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq) | |
231 | { | |
232 | int txq_id = txq->q.id; | |
233 | ||
234 | /* Circular buffer (TFD queue in DRAM) physical base address */ | |
235 | iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id), | |
236 | txq->q.dma_addr >> 8); | |
237 | ||
238 | return 0; | |
239 | } | |
240 | ||
387f3381 SG |
241 | /** |
242 | * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's | |
243 | */ | |
244 | void iwl_tx_queue_unmap(struct iwl_priv *priv, int txq_id) | |
245 | { | |
246 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
247 | struct iwl_queue *q = &txq->q; | |
248 | ||
249 | if (q->n_bd == 0) | |
250 | return; | |
251 | ||
252 | while (q->write_ptr != q->read_ptr) { | |
214d14d4 | 253 | iwlagn_txq_free_tfd(priv, txq); |
387f3381 SG |
254 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd); |
255 | } | |
256 | } | |
257 | ||
1053d35f RR |
258 | /** |
259 | * iwl_tx_queue_free - Deallocate DMA queue. | |
260 | * @txq: Transmit queue to deallocate. | |
261 | * | |
262 | * Empty queue by removing and destroying all BD's. | |
263 | * Free all buffers. | |
264 | * 0-fill, but do not free "txq" descriptor structure. | |
265 | */ | |
a8e74e27 | 266 | void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id) |
1053d35f | 267 | { |
da99c4b6 | 268 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; |
f36d04ab | 269 | struct device *dev = &priv->pci_dev->dev; |
71c55d90 | 270 | int i; |
1053d35f | 271 | |
387f3381 | 272 | iwl_tx_queue_unmap(priv, txq_id); |
1053d35f | 273 | |
1053d35f | 274 | /* De-alloc array of command/tx buffers */ |
961ba60a | 275 | for (i = 0; i < TFD_TX_CMD_SLOTS; i++) |
da99c4b6 | 276 | kfree(txq->cmd[i]); |
1053d35f RR |
277 | |
278 | /* De-alloc circular buffer of TFDs */ | |
279 | if (txq->q.n_bd) | |
f36d04ab SG |
280 | dma_free_coherent(dev, priv->hw_params.tfd_size * |
281 | txq->q.n_bd, txq->tfds, txq->q.dma_addr); | |
1053d35f RR |
282 | |
283 | /* De-alloc array of per-TFD driver data */ | |
284 | kfree(txq->txb); | |
285 | txq->txb = NULL; | |
286 | ||
c2acea8e JB |
287 | /* deallocate arrays */ |
288 | kfree(txq->cmd); | |
289 | kfree(txq->meta); | |
290 | txq->cmd = NULL; | |
291 | txq->meta = NULL; | |
292 | ||
1053d35f RR |
293 | /* 0-fill queue descriptor structure */ |
294 | memset(txq, 0, sizeof(*txq)); | |
295 | } | |
961ba60a TW |
296 | |
297 | /** | |
387f3381 | 298 | * iwl_cmd_queue_unmap - Unmap any remaining DMA mappings from command queue |
961ba60a | 299 | */ |
387f3381 | 300 | void iwl_cmd_queue_unmap(struct iwl_priv *priv) |
961ba60a | 301 | { |
13bb9483 | 302 | struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue]; |
961ba60a | 303 | struct iwl_queue *q = &txq->q; |
71c55d90 | 304 | int i; |
961ba60a TW |
305 | |
306 | if (q->n_bd == 0) | |
307 | return; | |
308 | ||
387f3381 | 309 | while (q->read_ptr != q->write_ptr) { |
4ce7cc2b | 310 | i = get_cmd_index(q, q->read_ptr); |
dd487449 | 311 | |
3598e177 | 312 | if (txq->meta[i].flags & CMD_MAPPED) { |
387f3381 SG |
313 | pci_unmap_single(priv->pci_dev, |
314 | dma_unmap_addr(&txq->meta[i], mapping), | |
315 | dma_unmap_len(&txq->meta[i], len), | |
316 | PCI_DMA_BIDIRECTIONAL); | |
3598e177 SG |
317 | txq->meta[i].flags = 0; |
318 | } | |
dd487449 | 319 | |
3598e177 | 320 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd); |
dd487449 | 321 | } |
387f3381 SG |
322 | } |
323 | ||
324 | /** | |
325 | * iwl_cmd_queue_free - Deallocate DMA queue. | |
326 | * @txq: Transmit queue to deallocate. | |
327 | * | |
328 | * Empty queue by removing and destroying all BD's. | |
329 | * Free all buffers. | |
330 | * 0-fill, but do not free "txq" descriptor structure. | |
331 | */ | |
332 | void iwl_cmd_queue_free(struct iwl_priv *priv) | |
333 | { | |
334 | struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue]; | |
335 | struct device *dev = &priv->pci_dev->dev; | |
336 | int i; | |
337 | ||
338 | iwl_cmd_queue_unmap(priv); | |
dd487449 | 339 | |
961ba60a | 340 | /* De-alloc array of command/tx buffers */ |
4ce7cc2b | 341 | for (i = 0; i < TFD_CMD_SLOTS; i++) |
961ba60a TW |
342 | kfree(txq->cmd[i]); |
343 | ||
344 | /* De-alloc circular buffer of TFDs */ | |
345 | if (txq->q.n_bd) | |
f36d04ab SG |
346 | dma_free_coherent(dev, priv->hw_params.tfd_size * txq->q.n_bd, |
347 | txq->tfds, txq->q.dma_addr); | |
961ba60a | 348 | |
28142986 RC |
349 | /* deallocate arrays */ |
350 | kfree(txq->cmd); | |
351 | kfree(txq->meta); | |
352 | txq->cmd = NULL; | |
353 | txq->meta = NULL; | |
354 | ||
961ba60a TW |
355 | /* 0-fill queue descriptor structure */ |
356 | memset(txq, 0, sizeof(*txq)); | |
357 | } | |
3e5d238f | 358 | |
fd4abac5 TW |
359 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
360 | * DMA services | |
361 | * | |
362 | * Theory of operation | |
363 | * | |
364 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
365 | * of buffer descriptors, each of which points to one or more data buffers for | |
366 | * the device to read from or fill. Driver and device exchange status of each | |
367 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
368 | * entries in each circular buffer, to protect against confusing empty and full | |
369 | * queue states. | |
370 | * | |
371 | * The device reads or writes the data in the queues via the device's several | |
372 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
373 | * | |
374 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
375 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
376 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
377 | * Tx queue resumed. | |
378 | * | |
fd4abac5 TW |
379 | ***************************************************/ |
380 | ||
381 | int iwl_queue_space(const struct iwl_queue *q) | |
382 | { | |
383 | int s = q->read_ptr - q->write_ptr; | |
384 | ||
385 | if (q->read_ptr > q->write_ptr) | |
386 | s -= q->n_bd; | |
387 | ||
388 | if (s <= 0) | |
389 | s += q->n_window; | |
390 | /* keep some reserve to not confuse empty and full situations */ | |
391 | s -= 2; | |
392 | if (s < 0) | |
393 | s = 0; | |
394 | return s; | |
395 | } | |
fd4abac5 TW |
396 | |
397 | ||
1053d35f RR |
398 | /** |
399 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes | |
400 | */ | |
443cfd45 | 401 | static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q, |
1053d35f RR |
402 | int count, int slots_num, u32 id) |
403 | { | |
404 | q->n_bd = count; | |
405 | q->n_window = slots_num; | |
406 | q->id = id; | |
407 | ||
408 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap | |
409 | * and iwl_queue_dec_wrap are broken. */ | |
3e41ace5 JB |
410 | if (WARN_ON(!is_power_of_2(count))) |
411 | return -EINVAL; | |
1053d35f RR |
412 | |
413 | /* slots_num must be power-of-two size, otherwise | |
414 | * get_cmd_index is broken. */ | |
3e41ace5 JB |
415 | if (WARN_ON(!is_power_of_2(slots_num))) |
416 | return -EINVAL; | |
1053d35f RR |
417 | |
418 | q->low_mark = q->n_window / 4; | |
419 | if (q->low_mark < 4) | |
420 | q->low_mark = 4; | |
421 | ||
422 | q->high_mark = q->n_window / 8; | |
423 | if (q->high_mark < 2) | |
424 | q->high_mark = 2; | |
425 | ||
426 | q->write_ptr = q->read_ptr = 0; | |
427 | ||
428 | return 0; | |
429 | } | |
430 | ||
431 | /** | |
432 | * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue | |
433 | */ | |
434 | static int iwl_tx_queue_alloc(struct iwl_priv *priv, | |
16466903 | 435 | struct iwl_tx_queue *txq, u32 id) |
1053d35f | 436 | { |
f36d04ab | 437 | struct device *dev = &priv->pci_dev->dev; |
3978e5bc | 438 | size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX; |
1053d35f RR |
439 | |
440 | /* Driver private data, only for Tx (not command) queues, | |
441 | * not shared with device. */ | |
13bb9483 | 442 | if (id != priv->cmd_queue) { |
519c7c41 | 443 | txq->txb = kzalloc(sizeof(txq->txb[0]) * |
1053d35f RR |
444 | TFD_QUEUE_SIZE_MAX, GFP_KERNEL); |
445 | if (!txq->txb) { | |
15b1687c | 446 | IWL_ERR(priv, "kmalloc for auxiliary BD " |
1053d35f RR |
447 | "structures failed\n"); |
448 | goto error; | |
449 | } | |
3978e5bc | 450 | } else { |
1053d35f | 451 | txq->txb = NULL; |
3978e5bc | 452 | } |
1053d35f RR |
453 | |
454 | /* Circular buffer of transmit frame descriptors (TFDs), | |
455 | * shared with device */ | |
f36d04ab SG |
456 | txq->tfds = dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr, |
457 | GFP_KERNEL); | |
499b1883 | 458 | if (!txq->tfds) { |
3978e5bc | 459 | IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz); |
1053d35f RR |
460 | goto error; |
461 | } | |
462 | txq->q.id = id; | |
463 | ||
464 | return 0; | |
465 | ||
466 | error: | |
467 | kfree(txq->txb); | |
468 | txq->txb = NULL; | |
469 | ||
470 | return -ENOMEM; | |
471 | } | |
472 | ||
1053d35f RR |
473 | /** |
474 | * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue | |
475 | */ | |
a8e74e27 SO |
476 | int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq, |
477 | int slots_num, u32 txq_id) | |
1053d35f | 478 | { |
da99c4b6 | 479 | int i, len; |
73b7d742 | 480 | int ret; |
c2acea8e | 481 | |
4ce7cc2b | 482 | txq->meta = kzalloc(sizeof(struct iwl_cmd_meta) * slots_num, |
c2acea8e | 483 | GFP_KERNEL); |
4ce7cc2b | 484 | txq->cmd = kzalloc(sizeof(struct iwl_device_cmd *) * slots_num, |
c2acea8e JB |
485 | GFP_KERNEL); |
486 | ||
487 | if (!txq->meta || !txq->cmd) | |
488 | goto out_free_arrays; | |
489 | ||
490 | len = sizeof(struct iwl_device_cmd); | |
4ce7cc2b | 491 | for (i = 0; i < slots_num; i++) { |
49898852 | 492 | txq->cmd[i] = kmalloc(len, GFP_KERNEL); |
da99c4b6 | 493 | if (!txq->cmd[i]) |
73b7d742 | 494 | goto err; |
da99c4b6 | 495 | } |
1053d35f RR |
496 | |
497 | /* Alloc driver data array and TFD circular buffer */ | |
73b7d742 TW |
498 | ret = iwl_tx_queue_alloc(priv, txq, txq_id); |
499 | if (ret) | |
500 | goto err; | |
1053d35f | 501 | |
1053d35f RR |
502 | txq->need_update = 0; |
503 | ||
1a716557 | 504 | /* |
ea9b307f JB |
505 | * For the default queues 0-3, set up the swq_id |
506 | * already -- all others need to get one later | |
507 | * (if they need one at all). | |
1a716557 | 508 | */ |
ea9b307f JB |
509 | if (txq_id < 4) |
510 | iwl_set_swq_id(txq, txq_id, txq_id); | |
45af8195 | 511 | |
1053d35f RR |
512 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise |
513 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ | |
514 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); | |
515 | ||
516 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
3e41ace5 JB |
517 | ret = iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id); |
518 | if (ret) | |
519 | return ret; | |
1053d35f RR |
520 | |
521 | /* Tell device where to find queue */ | |
214d14d4 | 522 | iwlagn_tx_queue_init(priv, txq); |
1053d35f RR |
523 | |
524 | return 0; | |
73b7d742 | 525 | err: |
4ce7cc2b | 526 | for (i = 0; i < slots_num; i++) |
73b7d742 | 527 | kfree(txq->cmd[i]); |
c2acea8e JB |
528 | out_free_arrays: |
529 | kfree(txq->meta); | |
530 | kfree(txq->cmd); | |
73b7d742 | 531 | |
73b7d742 | 532 | return -ENOMEM; |
1053d35f | 533 | } |
a8e74e27 | 534 | |
de0f60ea ZY |
535 | void iwl_tx_queue_reset(struct iwl_priv *priv, struct iwl_tx_queue *txq, |
536 | int slots_num, u32 txq_id) | |
537 | { | |
538 | int actual_slots = slots_num; | |
539 | ||
13bb9483 | 540 | if (txq_id == priv->cmd_queue) |
de0f60ea ZY |
541 | actual_slots++; |
542 | ||
543 | memset(txq->meta, 0, sizeof(struct iwl_cmd_meta) * actual_slots); | |
544 | ||
545 | txq->need_update = 0; | |
546 | ||
547 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
548 | iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id); | |
549 | ||
550 | /* Tell device where to find queue */ | |
214d14d4 | 551 | iwlagn_tx_queue_init(priv, txq); |
de0f60ea | 552 | } |
de0f60ea | 553 | |
fd4abac5 TW |
554 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ |
555 | ||
556 | /** | |
557 | * iwl_enqueue_hcmd - enqueue a uCode command | |
558 | * @priv: device private data point | |
559 | * @cmd: a point to the ucode command structure | |
560 | * | |
561 | * The function returns < 0 values to indicate the operation is | |
562 | * failed. On success, it turns the index (> 0) of command in the | |
563 | * command queue. | |
564 | */ | |
565 | int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd) | |
566 | { | |
13bb9483 | 567 | struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue]; |
fd4abac5 | 568 | struct iwl_queue *q = &txq->q; |
c2acea8e JB |
569 | struct iwl_device_cmd *out_cmd; |
570 | struct iwl_cmd_meta *out_meta; | |
fd4abac5 | 571 | dma_addr_t phys_addr; |
fd4abac5 | 572 | unsigned long flags; |
f3674227 | 573 | u32 idx; |
4ce7cc2b | 574 | u16 copy_size, cmd_size; |
0975cc8f | 575 | bool is_ct_kill = false; |
4ce7cc2b JB |
576 | bool had_nocopy = false; |
577 | int i; | |
578 | u8 *cmd_dest; | |
579 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
580 | const void *trace_bufs[IWL_MAX_CMD_TFDS + 1] = {}; | |
581 | int trace_lens[IWL_MAX_CMD_TFDS + 1] = {}; | |
582 | int trace_idx; | |
583 | #endif | |
fd4abac5 | 584 | |
3083d03c WYG |
585 | if (test_bit(STATUS_FW_ERROR, &priv->status)) { |
586 | IWL_WARN(priv, "fw recovery, no hcmd send\n"); | |
587 | return -EIO; | |
588 | } | |
589 | ||
4ce7cc2b JB |
590 | copy_size = sizeof(out_cmd->hdr); |
591 | cmd_size = sizeof(out_cmd->hdr); | |
592 | ||
593 | /* need one for the header if the first is NOCOPY */ | |
594 | BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1); | |
595 | ||
596 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
597 | if (!cmd->len[i]) | |
598 | continue; | |
599 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { | |
600 | had_nocopy = true; | |
601 | } else { | |
602 | /* NOCOPY must not be followed by normal! */ | |
603 | if (WARN_ON(had_nocopy)) | |
604 | return -EINVAL; | |
605 | copy_size += cmd->len[i]; | |
606 | } | |
607 | cmd_size += cmd->len[i]; | |
608 | } | |
fd4abac5 | 609 | |
3e41ace5 JB |
610 | /* |
611 | * If any of the command structures end up being larger than | |
4ce7cc2b JB |
612 | * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically |
613 | * allocated into separate TFDs, then we will need to | |
614 | * increase the size of the buffers. | |
3e41ace5 | 615 | */ |
4ce7cc2b | 616 | if (WARN_ON(copy_size > TFD_MAX_PAYLOAD_SIZE)) |
3e41ace5 | 617 | return -EINVAL; |
fd4abac5 | 618 | |
7812b167 | 619 | if (iwl_is_rfkill(priv) || iwl_is_ctkill(priv)) { |
f2f21b49 RC |
620 | IWL_WARN(priv, "Not sending command - %s KILL\n", |
621 | iwl_is_rfkill(priv) ? "RF" : "CT"); | |
fd4abac5 TW |
622 | return -EIO; |
623 | } | |
7b21f00e | 624 | |
3598e177 SG |
625 | spin_lock_irqsave(&priv->hcmd_lock, flags); |
626 | ||
c2acea8e | 627 | if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { |
3598e177 SG |
628 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); |
629 | ||
2d237f71 | 630 | IWL_ERR(priv, "No space in command queue\n"); |
f42e7662 | 631 | is_ct_kill = iwl_check_for_ct_kill(priv); |
0975cc8f | 632 | if (!is_ct_kill) { |
7812b167 | 633 | IWL_ERR(priv, "Restarting adapter due to queue full\n"); |
e649437f | 634 | iwlagn_fw_error(priv, false); |
7812b167 | 635 | } |
fd4abac5 TW |
636 | return -ENOSPC; |
637 | } | |
638 | ||
4ce7cc2b | 639 | idx = get_cmd_index(q, q->write_ptr); |
da99c4b6 | 640 | out_cmd = txq->cmd[idx]; |
c2acea8e JB |
641 | out_meta = &txq->meta[idx]; |
642 | ||
3598e177 SG |
643 | if (WARN_ON(out_meta->flags & CMD_MAPPED)) { |
644 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); | |
645 | return -ENOSPC; | |
646 | } | |
647 | ||
8ce73f3a | 648 | memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ |
c2acea8e JB |
649 | if (cmd->flags & CMD_WANT_SKB) |
650 | out_meta->source = cmd; | |
651 | if (cmd->flags & CMD_ASYNC) | |
652 | out_meta->callback = cmd->callback; | |
fd4abac5 | 653 | |
4ce7cc2b | 654 | /* set up the header */ |
fd4abac5 | 655 | |
4ce7cc2b | 656 | out_cmd->hdr.cmd = cmd->id; |
fd4abac5 | 657 | out_cmd->hdr.flags = 0; |
13bb9483 | 658 | out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(priv->cmd_queue) | |
4ce7cc2b JB |
659 | INDEX_TO_SEQ(q->write_ptr)); |
660 | ||
661 | /* and copy the data that needs to be copied */ | |
662 | ||
663 | cmd_dest = &out_cmd->cmd.payload[0]; | |
664 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
665 | if (!cmd->len[i]) | |
666 | continue; | |
667 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) | |
668 | break; | |
669 | memcpy(cmd_dest, cmd->data[i], cmd->len[i]); | |
670 | cmd_dest += cmd->len[i]; | |
ded2ae7c | 671 | } |
4ce7cc2b JB |
672 | |
673 | IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, " | |
674 | "%d bytes at %d[%d]:%d\n", | |
675 | get_cmd_string(out_cmd->hdr.cmd), | |
676 | out_cmd->hdr.cmd, | |
677 | le16_to_cpu(out_cmd->hdr.sequence), cmd_size, | |
678 | q->write_ptr, idx, priv->cmd_queue); | |
679 | ||
df833b1d | 680 | phys_addr = pci_map_single(priv->pci_dev, &out_cmd->hdr, |
4ce7cc2b | 681 | copy_size, PCI_DMA_BIDIRECTIONAL); |
2c46f72e JB |
682 | if (unlikely(pci_dma_mapping_error(priv->pci_dev, phys_addr))) { |
683 | idx = -ENOMEM; | |
684 | goto out; | |
685 | } | |
686 | ||
2e724443 | 687 | dma_unmap_addr_set(out_meta, mapping, phys_addr); |
4ce7cc2b JB |
688 | dma_unmap_len_set(out_meta, len, copy_size); |
689 | ||
690 | iwlagn_txq_attach_buf_to_tfd(priv, txq, phys_addr, copy_size, 1); | |
691 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
692 | trace_bufs[0] = &out_cmd->hdr; | |
693 | trace_lens[0] = copy_size; | |
694 | trace_idx = 1; | |
695 | #endif | |
696 | ||
697 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
698 | if (!cmd->len[i]) | |
699 | continue; | |
700 | if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY)) | |
701 | continue; | |
702 | phys_addr = pci_map_single(priv->pci_dev, (void *)cmd->data[i], | |
703 | cmd->len[i], PCI_DMA_TODEVICE); | |
704 | if (pci_dma_mapping_error(priv->pci_dev, phys_addr)) { | |
705 | iwlagn_unmap_tfd(priv, out_meta, | |
706 | &txq->tfds[q->write_ptr]); | |
707 | idx = -ENOMEM; | |
708 | goto out; | |
709 | } | |
710 | ||
711 | iwlagn_txq_attach_buf_to_tfd(priv, txq, phys_addr, | |
712 | cmd->len[i], 0); | |
713 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
714 | trace_bufs[trace_idx] = cmd->data[i]; | |
715 | trace_lens[trace_idx] = cmd->len[i]; | |
716 | trace_idx++; | |
717 | #endif | |
718 | } | |
df833b1d | 719 | |
2c46f72e JB |
720 | out_meta->flags = cmd->flags | CMD_MAPPED; |
721 | ||
722 | txq->need_update = 1; | |
723 | ||
4ce7cc2b JB |
724 | /* check that tracing gets all possible blocks */ |
725 | BUILD_BUG_ON(IWL_MAX_CMD_TFDS + 1 != 3); | |
726 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
727 | trace_iwlwifi_dev_hcmd(priv, cmd->flags, | |
728 | trace_bufs[0], trace_lens[0], | |
729 | trace_bufs[1], trace_lens[1], | |
730 | trace_bufs[2], trace_lens[2]); | |
731 | #endif | |
df833b1d | 732 | |
fd4abac5 TW |
733 | /* Increment and update queue's write index */ |
734 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
7bfedc59 | 735 | iwl_txq_update_write_ptr(priv, txq); |
fd4abac5 | 736 | |
2c46f72e | 737 | out: |
fd4abac5 | 738 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); |
7bfedc59 | 739 | return idx; |
fd4abac5 TW |
740 | } |
741 | ||
17b88929 TW |
742 | /** |
743 | * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd | |
744 | * | |
745 | * When FW advances 'R' index, all entries between old and new 'R' index | |
746 | * need to be reclaimed. As result, some free space forms. If there is | |
747 | * enough free space (> low mark), wake the stack that feeds us. | |
748 | */ | |
20ba2861 | 749 | static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, int idx) |
17b88929 TW |
750 | { |
751 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
752 | struct iwl_queue *q = &txq->q; | |
753 | int nfreed = 0; | |
754 | ||
499b1883 | 755 | if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) { |
15b1687c | 756 | IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, " |
17b88929 | 757 | "is out of range [0-%d] %d %d.\n", txq_id, |
499b1883 | 758 | idx, q->n_bd, q->write_ptr, q->read_ptr); |
17b88929 TW |
759 | return; |
760 | } | |
761 | ||
499b1883 TW |
762 | for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; |
763 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
17b88929 | 764 | |
499b1883 | 765 | if (nfreed++ > 0) { |
15b1687c | 766 | IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx, |
17b88929 | 767 | q->write_ptr, q->read_ptr); |
e649437f | 768 | iwlagn_fw_error(priv, false); |
17b88929 | 769 | } |
da99c4b6 | 770 | |
17b88929 TW |
771 | } |
772 | } | |
773 | ||
774 | /** | |
775 | * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them | |
776 | * @rxb: Rx buffer to reclaim | |
777 | * | |
778 | * If an Rx buffer has an async callback associated with it the callback | |
779 | * will be executed. The attached skb (if present) will only be freed | |
780 | * if the callback returns 1 | |
781 | */ | |
782 | void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb) | |
783 | { | |
2f301227 | 784 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
17b88929 TW |
785 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
786 | int txq_id = SEQ_TO_QUEUE(sequence); | |
787 | int index = SEQ_TO_INDEX(sequence); | |
17b88929 | 788 | int cmd_index; |
c2acea8e JB |
789 | struct iwl_device_cmd *cmd; |
790 | struct iwl_cmd_meta *meta; | |
13bb9483 | 791 | struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue]; |
3598e177 | 792 | unsigned long flags; |
17b88929 TW |
793 | |
794 | /* If a Tx command is being handled and it isn't in the actual | |
795 | * command queue then there a command routing bug has been introduced | |
796 | * in the queue management code. */ | |
13bb9483 JB |
797 | if (WARN(txq_id != priv->cmd_queue, |
798 | "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", | |
799 | txq_id, priv->cmd_queue, sequence, | |
800 | priv->txq[priv->cmd_queue].q.read_ptr, | |
801 | priv->txq[priv->cmd_queue].q.write_ptr)) { | |
ec741164 | 802 | iwl_print_hex_error(priv, pkt, 32); |
55d6a3cd | 803 | return; |
01ef9323 | 804 | } |
17b88929 | 805 | |
4ce7cc2b | 806 | cmd_index = get_cmd_index(&txq->q, index); |
dd487449 ZY |
807 | cmd = txq->cmd[cmd_index]; |
808 | meta = &txq->meta[cmd_index]; | |
17b88929 | 809 | |
4ce7cc2b | 810 | iwlagn_unmap_tfd(priv, meta, &txq->tfds[index]); |
c33de625 | 811 | |
17b88929 | 812 | /* Input error checking is done when commands are added to queue. */ |
c2acea8e | 813 | if (meta->flags & CMD_WANT_SKB) { |
2f301227 ZY |
814 | meta->source->reply_page = (unsigned long)rxb_addr(rxb); |
815 | rxb->page = NULL; | |
2624e96c SG |
816 | } else if (meta->callback) |
817 | meta->callback(priv, cmd, pkt); | |
818 | ||
819 | spin_lock_irqsave(&priv->hcmd_lock, flags); | |
17b88929 | 820 | |
20ba2861 | 821 | iwl_hcmd_queue_reclaim(priv, txq_id, index); |
17b88929 | 822 | |
c2acea8e | 823 | if (!(meta->flags & CMD_ASYNC)) { |
17b88929 | 824 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); |
91dd6c27 | 825 | IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command %s\n", |
d2dfe6df | 826 | get_cmd_string(cmd->hdr.cmd)); |
17b88929 TW |
827 | wake_up_interruptible(&priv->wait_command_queue); |
828 | } | |
3598e177 SG |
829 | |
830 | /* Mark as unmapped */ | |
dd487449 | 831 | meta->flags = 0; |
3598e177 SG |
832 | |
833 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); | |
17b88929 | 834 | } |