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1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
901069c7 | 3 | * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. |
1053d35f RR |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
1053d35f RR |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
fd4abac5 | 30 | #include <linux/etherdevice.h> |
d43c36dc | 31 | #include <linux/sched.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
1053d35f RR |
33 | #include <net/mac80211.h> |
34 | #include "iwl-eeprom.h" | |
214d14d4 | 35 | #include "iwl-agn.h" |
1053d35f RR |
36 | #include "iwl-dev.h" |
37 | #include "iwl-core.h" | |
38 | #include "iwl-sta.h" | |
39 | #include "iwl-io.h" | |
40 | #include "iwl-helpers.h" | |
41 | ||
fd4abac5 TW |
42 | /** |
43 | * iwl_txq_update_write_ptr - Send new write index to hardware | |
44 | */ | |
7bfedc59 | 45 | void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq) |
fd4abac5 TW |
46 | { |
47 | u32 reg = 0; | |
fd4abac5 TW |
48 | int txq_id = txq->q.id; |
49 | ||
50 | if (txq->need_update == 0) | |
7bfedc59 | 51 | return; |
fd4abac5 | 52 | |
f81c1f48 WYG |
53 | if (priv->cfg->base_params->shadow_reg_enable) { |
54 | /* shadow register enabled */ | |
55 | iwl_write32(priv, HBUS_TARG_WRPTR, | |
56 | txq->q.write_ptr | (txq_id << 8)); | |
57 | } else { | |
58 | /* if we're trying to save power */ | |
59 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { | |
60 | /* wake up nic if it's powered down ... | |
61 | * uCode will wake up, and interrupt us again, so next | |
62 | * time we'll skip this part. */ | |
63 | reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); | |
fd4abac5 | 64 | |
f81c1f48 WYG |
65 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { |
66 | IWL_DEBUG_INFO(priv, | |
67 | "Tx queue %d requesting wakeup," | |
68 | " GP1 = 0x%x\n", txq_id, reg); | |
69 | iwl_set_bit(priv, CSR_GP_CNTRL, | |
70 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
71 | return; | |
72 | } | |
fd4abac5 | 73 | |
f81c1f48 | 74 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, |
fd4abac5 | 75 | txq->q.write_ptr | (txq_id << 8)); |
fd4abac5 | 76 | |
f81c1f48 WYG |
77 | /* |
78 | * else not in power-save mode, | |
79 | * uCode will never sleep when we're | |
80 | * trying to tx (during RFKILL, we're not trying to tx). | |
81 | */ | |
82 | } else | |
83 | iwl_write32(priv, HBUS_TARG_WRPTR, | |
84 | txq->q.write_ptr | (txq_id << 8)); | |
85 | } | |
fd4abac5 | 86 | txq->need_update = 0; |
fd4abac5 | 87 | } |
fd4abac5 | 88 | |
214d14d4 JB |
89 | static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
90 | { | |
91 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
92 | ||
93 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
94 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
95 | addr |= | |
96 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
97 | ||
98 | return addr; | |
99 | } | |
100 | ||
101 | static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) | |
102 | { | |
103 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
104 | ||
105 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
106 | } | |
107 | ||
108 | static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, | |
109 | dma_addr_t addr, u16 len) | |
110 | { | |
111 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
112 | u16 hi_n_len = len << 4; | |
113 | ||
114 | put_unaligned_le32(addr, &tb->lo); | |
115 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
116 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
117 | ||
118 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
119 | ||
120 | tfd->num_tbs = idx + 1; | |
121 | } | |
122 | ||
123 | static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd) | |
124 | { | |
125 | return tfd->num_tbs & 0x1f; | |
126 | } | |
127 | ||
4ce7cc2b | 128 | static void iwlagn_unmap_tfd(struct iwl_priv *priv, struct iwl_cmd_meta *meta, |
3be3fdb5 | 129 | struct iwl_tfd *tfd, enum dma_data_direction dma_dir) |
214d14d4 | 130 | { |
214d14d4 JB |
131 | int i; |
132 | int num_tbs; | |
133 | ||
214d14d4 JB |
134 | /* Sanity check on number of chunks */ |
135 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
136 | ||
137 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
138 | IWL_ERR(priv, "Too many chunks: %i\n", num_tbs); | |
139 | /* @todo issue fatal error, it is quite serious situation */ | |
140 | return; | |
141 | } | |
142 | ||
143 | /* Unmap tx_cmd */ | |
144 | if (num_tbs) | |
795414db | 145 | dma_unmap_single(priv->bus.dev, |
4ce7cc2b JB |
146 | dma_unmap_addr(meta, mapping), |
147 | dma_unmap_len(meta, len), | |
795414db | 148 | DMA_BIDIRECTIONAL); |
214d14d4 JB |
149 | |
150 | /* Unmap chunks, if any. */ | |
151 | for (i = 1; i < num_tbs; i++) | |
795414db | 152 | dma_unmap_single(priv->bus.dev, iwl_tfd_tb_get_addr(tfd, i), |
e815407d | 153 | iwl_tfd_tb_get_len(tfd, i), dma_dir); |
4ce7cc2b JB |
154 | } |
155 | ||
156 | /** | |
157 | * iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
158 | * @priv - driver private data | |
159 | * @txq - tx queue | |
1359ca4f | 160 | * @index - the index of the TFD to be freed |
4ce7cc2b JB |
161 | * |
162 | * Does NOT advance any TFD circular buffer read/write indexes | |
163 | * Does NOT free the TFD itself (which is within circular buffer) | |
164 | */ | |
1359ca4f EG |
165 | void iwlagn_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq, |
166 | int index) | |
4ce7cc2b JB |
167 | { |
168 | struct iwl_tfd *tfd_tmp = txq->tfds; | |
4ce7cc2b | 169 | |
e815407d | 170 | iwlagn_unmap_tfd(priv, &txq->meta[index], &tfd_tmp[index], |
3be3fdb5 | 171 | DMA_TO_DEVICE); |
214d14d4 JB |
172 | |
173 | /* free SKB */ | |
174 | if (txq->txb) { | |
175 | struct sk_buff *skb; | |
176 | ||
1359ca4f | 177 | skb = txq->txb[index].skb; |
214d14d4 JB |
178 | |
179 | /* can be called from irqs-disabled context */ | |
180 | if (skb) { | |
181 | dev_kfree_skb_any(skb); | |
1359ca4f | 182 | txq->txb[index].skb = NULL; |
214d14d4 JB |
183 | } |
184 | } | |
185 | } | |
186 | ||
187 | int iwlagn_txq_attach_buf_to_tfd(struct iwl_priv *priv, | |
188 | struct iwl_tx_queue *txq, | |
189 | dma_addr_t addr, u16 len, | |
4c42db0f | 190 | u8 reset) |
214d14d4 JB |
191 | { |
192 | struct iwl_queue *q; | |
193 | struct iwl_tfd *tfd, *tfd_tmp; | |
194 | u32 num_tbs; | |
195 | ||
196 | q = &txq->q; | |
4ce7cc2b | 197 | tfd_tmp = txq->tfds; |
214d14d4 JB |
198 | tfd = &tfd_tmp[q->write_ptr]; |
199 | ||
200 | if (reset) | |
201 | memset(tfd, 0, sizeof(*tfd)); | |
202 | ||
203 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
204 | ||
205 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
206 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
207 | IWL_ERR(priv, "Error can not send more than %d chunks\n", | |
208 | IWL_NUM_OF_TBS); | |
209 | return -EINVAL; | |
210 | } | |
211 | ||
212 | if (WARN_ON(addr & ~DMA_BIT_MASK(36))) | |
213 | return -EINVAL; | |
214 | ||
215 | if (unlikely(addr & ~IWL_TX_DMA_MASK)) | |
216 | IWL_ERR(priv, "Unaligned address = %llx\n", | |
217 | (unsigned long long)addr); | |
218 | ||
219 | iwl_tfd_set_tb(tfd, num_tbs, addr, len); | |
220 | ||
221 | return 0; | |
222 | } | |
223 | ||
fd4abac5 TW |
224 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
225 | * DMA services | |
226 | * | |
227 | * Theory of operation | |
228 | * | |
229 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
230 | * of buffer descriptors, each of which points to one or more data buffers for | |
231 | * the device to read from or fill. Driver and device exchange status of each | |
232 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
233 | * entries in each circular buffer, to protect against confusing empty and full | |
234 | * queue states. | |
235 | * | |
236 | * The device reads or writes the data in the queues via the device's several | |
237 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
238 | * | |
239 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
240 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
241 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
242 | * Tx queue resumed. | |
243 | * | |
fd4abac5 TW |
244 | ***************************************************/ |
245 | ||
246 | int iwl_queue_space(const struct iwl_queue *q) | |
247 | { | |
248 | int s = q->read_ptr - q->write_ptr; | |
249 | ||
250 | if (q->read_ptr > q->write_ptr) | |
251 | s -= q->n_bd; | |
252 | ||
253 | if (s <= 0) | |
254 | s += q->n_window; | |
255 | /* keep some reserve to not confuse empty and full situations */ | |
256 | s -= 2; | |
257 | if (s < 0) | |
258 | s = 0; | |
259 | return s; | |
260 | } | |
fd4abac5 | 261 | |
1053d35f RR |
262 | /** |
263 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes | |
264 | */ | |
02aca585 | 265 | int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q, |
1053d35f RR |
266 | int count, int slots_num, u32 id) |
267 | { | |
268 | q->n_bd = count; | |
269 | q->n_window = slots_num; | |
270 | q->id = id; | |
271 | ||
272 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap | |
273 | * and iwl_queue_dec_wrap are broken. */ | |
3e41ace5 JB |
274 | if (WARN_ON(!is_power_of_2(count))) |
275 | return -EINVAL; | |
1053d35f RR |
276 | |
277 | /* slots_num must be power-of-two size, otherwise | |
278 | * get_cmd_index is broken. */ | |
3e41ace5 JB |
279 | if (WARN_ON(!is_power_of_2(slots_num))) |
280 | return -EINVAL; | |
1053d35f RR |
281 | |
282 | q->low_mark = q->n_window / 4; | |
283 | if (q->low_mark < 4) | |
284 | q->low_mark = 4; | |
285 | ||
286 | q->high_mark = q->n_window / 8; | |
287 | if (q->high_mark < 2) | |
288 | q->high_mark = 2; | |
289 | ||
290 | q->write_ptr = q->read_ptr = 0; | |
291 | ||
292 | return 0; | |
293 | } | |
294 | ||
fd4abac5 TW |
295 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ |
296 | ||
297 | /** | |
298 | * iwl_enqueue_hcmd - enqueue a uCode command | |
299 | * @priv: device private data point | |
300 | * @cmd: a point to the ucode command structure | |
301 | * | |
302 | * The function returns < 0 values to indicate the operation is | |
303 | * failed. On success, it turns the index (> 0) of command in the | |
304 | * command queue. | |
305 | */ | |
306 | int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd) | |
307 | { | |
13bb9483 | 308 | struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue]; |
fd4abac5 | 309 | struct iwl_queue *q = &txq->q; |
c2acea8e JB |
310 | struct iwl_device_cmd *out_cmd; |
311 | struct iwl_cmd_meta *out_meta; | |
fd4abac5 | 312 | dma_addr_t phys_addr; |
fd4abac5 | 313 | unsigned long flags; |
f3674227 | 314 | u32 idx; |
4ce7cc2b | 315 | u16 copy_size, cmd_size; |
0975cc8f | 316 | bool is_ct_kill = false; |
4ce7cc2b JB |
317 | bool had_nocopy = false; |
318 | int i; | |
319 | u8 *cmd_dest; | |
320 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
321 | const void *trace_bufs[IWL_MAX_CMD_TFDS + 1] = {}; | |
322 | int trace_lens[IWL_MAX_CMD_TFDS + 1] = {}; | |
323 | int trace_idx; | |
324 | #endif | |
fd4abac5 | 325 | |
3083d03c WYG |
326 | if (test_bit(STATUS_FW_ERROR, &priv->status)) { |
327 | IWL_WARN(priv, "fw recovery, no hcmd send\n"); | |
328 | return -EIO; | |
329 | } | |
330 | ||
eedb6e35 WYG |
331 | if ((priv->ucode_owner == IWL_OWNERSHIP_TM) && |
332 | !(cmd->flags & CMD_ON_DEMAND)) { | |
333 | IWL_DEBUG_HC(priv, "tm own the uCode, no regular hcmd send\n"); | |
334 | return -EIO; | |
335 | } | |
336 | ||
4ce7cc2b JB |
337 | copy_size = sizeof(out_cmd->hdr); |
338 | cmd_size = sizeof(out_cmd->hdr); | |
339 | ||
340 | /* need one for the header if the first is NOCOPY */ | |
341 | BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1); | |
342 | ||
343 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
344 | if (!cmd->len[i]) | |
345 | continue; | |
346 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { | |
347 | had_nocopy = true; | |
348 | } else { | |
349 | /* NOCOPY must not be followed by normal! */ | |
350 | if (WARN_ON(had_nocopy)) | |
351 | return -EINVAL; | |
352 | copy_size += cmd->len[i]; | |
353 | } | |
354 | cmd_size += cmd->len[i]; | |
355 | } | |
fd4abac5 | 356 | |
3e41ace5 JB |
357 | /* |
358 | * If any of the command structures end up being larger than | |
4ce7cc2b JB |
359 | * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically |
360 | * allocated into separate TFDs, then we will need to | |
361 | * increase the size of the buffers. | |
3e41ace5 | 362 | */ |
4ce7cc2b | 363 | if (WARN_ON(copy_size > TFD_MAX_PAYLOAD_SIZE)) |
3e41ace5 | 364 | return -EINVAL; |
fd4abac5 | 365 | |
7812b167 | 366 | if (iwl_is_rfkill(priv) || iwl_is_ctkill(priv)) { |
f2f21b49 RC |
367 | IWL_WARN(priv, "Not sending command - %s KILL\n", |
368 | iwl_is_rfkill(priv) ? "RF" : "CT"); | |
fd4abac5 TW |
369 | return -EIO; |
370 | } | |
7b21f00e | 371 | |
3598e177 SG |
372 | spin_lock_irqsave(&priv->hcmd_lock, flags); |
373 | ||
c2acea8e | 374 | if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { |
3598e177 SG |
375 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); |
376 | ||
2d237f71 | 377 | IWL_ERR(priv, "No space in command queue\n"); |
f42e7662 | 378 | is_ct_kill = iwl_check_for_ct_kill(priv); |
0975cc8f | 379 | if (!is_ct_kill) { |
7812b167 | 380 | IWL_ERR(priv, "Restarting adapter due to queue full\n"); |
e649437f | 381 | iwlagn_fw_error(priv, false); |
7812b167 | 382 | } |
fd4abac5 TW |
383 | return -ENOSPC; |
384 | } | |
385 | ||
4ce7cc2b | 386 | idx = get_cmd_index(q, q->write_ptr); |
da99c4b6 | 387 | out_cmd = txq->cmd[idx]; |
c2acea8e JB |
388 | out_meta = &txq->meta[idx]; |
389 | ||
8ce73f3a | 390 | memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ |
c2acea8e JB |
391 | if (cmd->flags & CMD_WANT_SKB) |
392 | out_meta->source = cmd; | |
393 | if (cmd->flags & CMD_ASYNC) | |
394 | out_meta->callback = cmd->callback; | |
fd4abac5 | 395 | |
4ce7cc2b | 396 | /* set up the header */ |
fd4abac5 | 397 | |
4ce7cc2b | 398 | out_cmd->hdr.cmd = cmd->id; |
fd4abac5 | 399 | out_cmd->hdr.flags = 0; |
13bb9483 | 400 | out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(priv->cmd_queue) | |
4ce7cc2b JB |
401 | INDEX_TO_SEQ(q->write_ptr)); |
402 | ||
403 | /* and copy the data that needs to be copied */ | |
404 | ||
405 | cmd_dest = &out_cmd->cmd.payload[0]; | |
406 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
407 | if (!cmd->len[i]) | |
408 | continue; | |
409 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) | |
410 | break; | |
411 | memcpy(cmd_dest, cmd->data[i], cmd->len[i]); | |
412 | cmd_dest += cmd->len[i]; | |
ded2ae7c | 413 | } |
4ce7cc2b JB |
414 | |
415 | IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, " | |
416 | "%d bytes at %d[%d]:%d\n", | |
417 | get_cmd_string(out_cmd->hdr.cmd), | |
418 | out_cmd->hdr.cmd, | |
419 | le16_to_cpu(out_cmd->hdr.sequence), cmd_size, | |
420 | q->write_ptr, idx, priv->cmd_queue); | |
421 | ||
795414db EG |
422 | phys_addr = dma_map_single(priv->bus.dev, &out_cmd->hdr, copy_size, |
423 | DMA_BIDIRECTIONAL); | |
424 | if (unlikely(dma_mapping_error(priv->bus.dev, phys_addr))) { | |
2c46f72e JB |
425 | idx = -ENOMEM; |
426 | goto out; | |
427 | } | |
428 | ||
2e724443 | 429 | dma_unmap_addr_set(out_meta, mapping, phys_addr); |
4ce7cc2b JB |
430 | dma_unmap_len_set(out_meta, len, copy_size); |
431 | ||
432 | iwlagn_txq_attach_buf_to_tfd(priv, txq, phys_addr, copy_size, 1); | |
433 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
434 | trace_bufs[0] = &out_cmd->hdr; | |
435 | trace_lens[0] = copy_size; | |
436 | trace_idx = 1; | |
437 | #endif | |
438 | ||
439 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
440 | if (!cmd->len[i]) | |
441 | continue; | |
442 | if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY)) | |
443 | continue; | |
795414db | 444 | phys_addr = dma_map_single(priv->bus.dev, (void *)cmd->data[i], |
3be3fdb5 | 445 | cmd->len[i], DMA_BIDIRECTIONAL); |
795414db | 446 | if (dma_mapping_error(priv->bus.dev, phys_addr)) { |
4ce7cc2b | 447 | iwlagn_unmap_tfd(priv, out_meta, |
e815407d | 448 | &txq->tfds[q->write_ptr], |
3be3fdb5 | 449 | DMA_BIDIRECTIONAL); |
4ce7cc2b JB |
450 | idx = -ENOMEM; |
451 | goto out; | |
452 | } | |
453 | ||
454 | iwlagn_txq_attach_buf_to_tfd(priv, txq, phys_addr, | |
455 | cmd->len[i], 0); | |
456 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
457 | trace_bufs[trace_idx] = cmd->data[i]; | |
458 | trace_lens[trace_idx] = cmd->len[i]; | |
459 | trace_idx++; | |
460 | #endif | |
461 | } | |
df833b1d | 462 | |
afaf6b57 | 463 | out_meta->flags = cmd->flags; |
2c46f72e JB |
464 | |
465 | txq->need_update = 1; | |
466 | ||
4ce7cc2b JB |
467 | /* check that tracing gets all possible blocks */ |
468 | BUILD_BUG_ON(IWL_MAX_CMD_TFDS + 1 != 3); | |
469 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
470 | trace_iwlwifi_dev_hcmd(priv, cmd->flags, | |
471 | trace_bufs[0], trace_lens[0], | |
472 | trace_bufs[1], trace_lens[1], | |
473 | trace_bufs[2], trace_lens[2]); | |
474 | #endif | |
df833b1d | 475 | |
fd4abac5 TW |
476 | /* Increment and update queue's write index */ |
477 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
7bfedc59 | 478 | iwl_txq_update_write_ptr(priv, txq); |
fd4abac5 | 479 | |
2c46f72e | 480 | out: |
fd4abac5 | 481 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); |
7bfedc59 | 482 | return idx; |
fd4abac5 TW |
483 | } |
484 | ||
17b88929 TW |
485 | /** |
486 | * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd | |
487 | * | |
488 | * When FW advances 'R' index, all entries between old and new 'R' index | |
489 | * need to be reclaimed. As result, some free space forms. If there is | |
490 | * enough free space (> low mark), wake the stack that feeds us. | |
491 | */ | |
20ba2861 | 492 | static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, int idx) |
17b88929 TW |
493 | { |
494 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
495 | struct iwl_queue *q = &txq->q; | |
496 | int nfreed = 0; | |
497 | ||
499b1883 | 498 | if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) { |
2e5d04da DH |
499 | IWL_ERR(priv, "%s: Read index for DMA queue txq id (%d), " |
500 | "index %d is out of range [0-%d] %d %d.\n", __func__, | |
501 | txq_id, idx, q->n_bd, q->write_ptr, q->read_ptr); | |
17b88929 TW |
502 | return; |
503 | } | |
504 | ||
499b1883 TW |
505 | for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; |
506 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
17b88929 | 507 | |
499b1883 | 508 | if (nfreed++ > 0) { |
15b1687c | 509 | IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx, |
17b88929 | 510 | q->write_ptr, q->read_ptr); |
e649437f | 511 | iwlagn_fw_error(priv, false); |
17b88929 | 512 | } |
da99c4b6 | 513 | |
17b88929 TW |
514 | } |
515 | } | |
516 | ||
517 | /** | |
518 | * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them | |
519 | * @rxb: Rx buffer to reclaim | |
520 | * | |
521 | * If an Rx buffer has an async callback associated with it the callback | |
522 | * will be executed. The attached skb (if present) will only be freed | |
523 | * if the callback returns 1 | |
524 | */ | |
525 | void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb) | |
526 | { | |
2f301227 | 527 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
17b88929 TW |
528 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
529 | int txq_id = SEQ_TO_QUEUE(sequence); | |
530 | int index = SEQ_TO_INDEX(sequence); | |
17b88929 | 531 | int cmd_index; |
c2acea8e JB |
532 | struct iwl_device_cmd *cmd; |
533 | struct iwl_cmd_meta *meta; | |
13bb9483 | 534 | struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue]; |
3598e177 | 535 | unsigned long flags; |
17b88929 TW |
536 | |
537 | /* If a Tx command is being handled and it isn't in the actual | |
538 | * command queue then there a command routing bug has been introduced | |
539 | * in the queue management code. */ | |
13bb9483 JB |
540 | if (WARN(txq_id != priv->cmd_queue, |
541 | "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", | |
542 | txq_id, priv->cmd_queue, sequence, | |
543 | priv->txq[priv->cmd_queue].q.read_ptr, | |
544 | priv->txq[priv->cmd_queue].q.write_ptr)) { | |
ec741164 | 545 | iwl_print_hex_error(priv, pkt, 32); |
55d6a3cd | 546 | return; |
01ef9323 | 547 | } |
17b88929 | 548 | |
4ce7cc2b | 549 | cmd_index = get_cmd_index(&txq->q, index); |
dd487449 ZY |
550 | cmd = txq->cmd[cmd_index]; |
551 | meta = &txq->meta[cmd_index]; | |
17b88929 | 552 | |
3be3fdb5 | 553 | iwlagn_unmap_tfd(priv, meta, &txq->tfds[index], DMA_BIDIRECTIONAL); |
c33de625 | 554 | |
17b88929 | 555 | /* Input error checking is done when commands are added to queue. */ |
c2acea8e | 556 | if (meta->flags & CMD_WANT_SKB) { |
2f301227 ZY |
557 | meta->source->reply_page = (unsigned long)rxb_addr(rxb); |
558 | rxb->page = NULL; | |
2624e96c SG |
559 | } else if (meta->callback) |
560 | meta->callback(priv, cmd, pkt); | |
561 | ||
562 | spin_lock_irqsave(&priv->hcmd_lock, flags); | |
17b88929 | 563 | |
20ba2861 | 564 | iwl_hcmd_queue_reclaim(priv, txq_id, index); |
17b88929 | 565 | |
c2acea8e | 566 | if (!(meta->flags & CMD_ASYNC)) { |
17b88929 | 567 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); |
91dd6c27 | 568 | IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command %s\n", |
d2dfe6df | 569 | get_cmd_string(cmd->hdr.cmd)); |
17b88929 TW |
570 | wake_up_interruptible(&priv->wait_command_queue); |
571 | } | |
3598e177 | 572 | |
dd487449 | 573 | meta->flags = 0; |
3598e177 SG |
574 | |
575 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); | |
17b88929 | 576 | } |