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792bc3cb WYG |
1 | /****************************************************************************** |
2 | * | |
3 | * GPL LICENSE SUMMARY | |
4 | * | |
4e318262 | 5 | * Copyright(c) 2008 - 2012 Intel Corporation. All rights reserved. |
792bc3cb WYG |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of version 2 of the GNU General Public License as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
19 | * USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution | |
22 | * in the file called LICENSE.GPL. | |
23 | * | |
24 | * Contact Information: | |
25 | * Intel Linux Wireless <ilw@linux.intel.com> | |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
30 | #include <linux/kernel.h> | |
792bc3cb WYG |
31 | #include <linux/init.h> |
32 | ||
33 | #include "iwl-dev.h" | |
34 | #include "iwl-core.h" | |
81b8176e | 35 | #include "iwl-io.h" |
19e6cda0 | 36 | #include "iwl-agn-hw.h" |
741a6266 | 37 | #include "iwl-agn.h" |
0de76736 | 38 | #include "iwl-agn-calib.h" |
bdfbf092 | 39 | #include "iwl-trans.h" |
dda61a44 | 40 | #include "iwl-fh.h" |
d0f76d68 | 41 | #include "iwl-op-mode.h" |
741a6266 | 42 | |
f4012413 WYG |
43 | static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = { |
44 | {COEX_CU_UNASSOC_IDLE_RP, COEX_CU_UNASSOC_IDLE_WP, | |
45 | 0, COEX_UNASSOC_IDLE_FLAGS}, | |
46 | {COEX_CU_UNASSOC_MANUAL_SCAN_RP, COEX_CU_UNASSOC_MANUAL_SCAN_WP, | |
47 | 0, COEX_UNASSOC_MANUAL_SCAN_FLAGS}, | |
48 | {COEX_CU_UNASSOC_AUTO_SCAN_RP, COEX_CU_UNASSOC_AUTO_SCAN_WP, | |
49 | 0, COEX_UNASSOC_AUTO_SCAN_FLAGS}, | |
50 | {COEX_CU_CALIBRATION_RP, COEX_CU_CALIBRATION_WP, | |
51 | 0, COEX_CALIBRATION_FLAGS}, | |
52 | {COEX_CU_PERIODIC_CALIBRATION_RP, COEX_CU_PERIODIC_CALIBRATION_WP, | |
53 | 0, COEX_PERIODIC_CALIBRATION_FLAGS}, | |
54 | {COEX_CU_CONNECTION_ESTAB_RP, COEX_CU_CONNECTION_ESTAB_WP, | |
55 | 0, COEX_CONNECTION_ESTAB_FLAGS}, | |
56 | {COEX_CU_ASSOCIATED_IDLE_RP, COEX_CU_ASSOCIATED_IDLE_WP, | |
57 | 0, COEX_ASSOCIATED_IDLE_FLAGS}, | |
58 | {COEX_CU_ASSOC_MANUAL_SCAN_RP, COEX_CU_ASSOC_MANUAL_SCAN_WP, | |
59 | 0, COEX_ASSOC_MANUAL_SCAN_FLAGS}, | |
60 | {COEX_CU_ASSOC_AUTO_SCAN_RP, COEX_CU_ASSOC_AUTO_SCAN_WP, | |
61 | 0, COEX_ASSOC_AUTO_SCAN_FLAGS}, | |
62 | {COEX_CU_ASSOC_ACTIVE_LEVEL_RP, COEX_CU_ASSOC_ACTIVE_LEVEL_WP, | |
63 | 0, COEX_ASSOC_ACTIVE_LEVEL_FLAGS}, | |
64 | {COEX_CU_RF_ON_RP, COEX_CU_RF_ON_WP, 0, COEX_CU_RF_ON_FLAGS}, | |
65 | {COEX_CU_RF_OFF_RP, COEX_CU_RF_OFF_WP, 0, COEX_RF_OFF_FLAGS}, | |
66 | {COEX_CU_STAND_ALONE_DEBUG_RP, COEX_CU_STAND_ALONE_DEBUG_WP, | |
67 | 0, COEX_STAND_ALONE_DEBUG_FLAGS}, | |
68 | {COEX_CU_IPAN_ASSOC_LEVEL_RP, COEX_CU_IPAN_ASSOC_LEVEL_WP, | |
69 | 0, COEX_IPAN_ASSOC_LEVEL_FLAGS}, | |
70 | {COEX_CU_RSRVD1_RP, COEX_CU_RSRVD1_WP, 0, COEX_RSRVD1_FLAGS}, | |
71 | {COEX_CU_RSRVD2_RP, COEX_CU_RSRVD2_WP, 0, COEX_RSRVD2_FLAGS} | |
72 | }; | |
73 | ||
de7f5f92 DF |
74 | /****************************************************************************** |
75 | * | |
76 | * uCode download functions | |
77 | * | |
78 | ******************************************************************************/ | |
79 | ||
0692fe41 JB |
80 | static inline const struct fw_img * |
81 | iwl_get_ucode_image(struct iwl_priv *priv, enum iwl_ucode_type ucode_type) | |
8929c24b DF |
82 | { |
83 | switch (ucode_type) { | |
84 | case IWL_UCODE_INIT: | |
0692fe41 | 85 | return &priv->fw->ucode_init; |
8929c24b | 86 | case IWL_UCODE_WOWLAN: |
0692fe41 | 87 | return &priv->fw->ucode_wowlan; |
8929c24b | 88 | case IWL_UCODE_REGULAR: |
0692fe41 | 89 | return &priv->fw->ucode_rt; |
8929c24b DF |
90 | case IWL_UCODE_NONE: |
91 | break; | |
92 | } | |
93 | return NULL; | |
94 | } | |
95 | ||
741a6266 WYG |
96 | /* |
97 | * Calibration | |
98 | */ | |
e1991885 | 99 | static int iwl_set_Xtal_calib(struct iwl_priv *priv) |
741a6266 WYG |
100 | { |
101 | struct iwl_calib_xtal_freq_cmd cmd; | |
102 | __le16 *xtal_calib = | |
e1991885 | 103 | (__le16 *)iwl_eeprom_query_addr(priv->shrd, EEPROM_XTAL); |
741a6266 | 104 | |
1f8bf039 | 105 | iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD); |
741a6266 WYG |
106 | cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]); |
107 | cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]); | |
e1991885 | 108 | return iwl_calib_set(priv, (void *)&cmd, sizeof(cmd)); |
741a6266 WYG |
109 | } |
110 | ||
e1991885 | 111 | static int iwl_set_temperature_offset_calib(struct iwl_priv *priv) |
bf53f939 SZ |
112 | { |
113 | struct iwl_calib_temperature_offset_cmd cmd; | |
114 | __le16 *offset_calib = | |
e1991885 | 115 | (__le16 *)iwl_eeprom_query_addr(priv->shrd, |
ab36eab2 | 116 | EEPROM_RAW_TEMPERATURE); |
1f8bf039 WYG |
117 | |
118 | memset(&cmd, 0, sizeof(cmd)); | |
119 | iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD); | |
456fc37e | 120 | memcpy(&cmd.radio_sensor_offset, offset_calib, sizeof(*offset_calib)); |
bf53f939 SZ |
121 | if (!(cmd.radio_sensor_offset)) |
122 | cmd.radio_sensor_offset = DEFAULT_RADIO_SENSOR_OFFSET; | |
1f8bf039 | 123 | |
e1991885 | 124 | IWL_DEBUG_CALIB(priv, "Radio sensor offset: %d\n", |
2e277996 | 125 | le16_to_cpu(cmd.radio_sensor_offset)); |
e1991885 | 126 | return iwl_calib_set(priv, (void *)&cmd, sizeof(cmd)); |
bf53f939 SZ |
127 | } |
128 | ||
e1991885 | 129 | static int iwl_set_temperature_offset_calib_v2(struct iwl_priv *priv) |
c6f30347 WYG |
130 | { |
131 | struct iwl_calib_temperature_offset_v2_cmd cmd; | |
e1991885 | 132 | __le16 *offset_calib_high = (__le16 *)iwl_eeprom_query_addr(priv->shrd, |
c6f30347 WYG |
133 | EEPROM_KELVIN_TEMPERATURE); |
134 | __le16 *offset_calib_low = | |
e1991885 | 135 | (__le16 *)iwl_eeprom_query_addr(priv->shrd, |
ab36eab2 | 136 | EEPROM_RAW_TEMPERATURE); |
7d8f2d50 | 137 | struct iwl_eeprom_calib_hdr *hdr; |
c6f30347 WYG |
138 | |
139 | memset(&cmd, 0, sizeof(cmd)); | |
140 | iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD); | |
e1991885 | 141 | hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv->shrd, |
7d8f2d50 | 142 | EEPROM_CALIB_ALL); |
c6f30347 | 143 | memcpy(&cmd.radio_sensor_offset_high, offset_calib_high, |
00085006 | 144 | sizeof(*offset_calib_high)); |
c6f30347 | 145 | memcpy(&cmd.radio_sensor_offset_low, offset_calib_low, |
00085006 | 146 | sizeof(*offset_calib_low)); |
c6f30347 | 147 | if (!(cmd.radio_sensor_offset_low)) { |
e1991885 | 148 | IWL_DEBUG_CALIB(priv, "no info in EEPROM, use default\n"); |
c6f30347 WYG |
149 | cmd.radio_sensor_offset_low = DEFAULT_RADIO_SENSOR_OFFSET; |
150 | cmd.radio_sensor_offset_high = DEFAULT_RADIO_SENSOR_OFFSET; | |
151 | } | |
7d8f2d50 WYG |
152 | memcpy(&cmd.burntVoltageRef, &hdr->voltage, |
153 | sizeof(hdr->voltage)); | |
c6f30347 | 154 | |
e1991885 | 155 | IWL_DEBUG_CALIB(priv, "Radio sensor offset high: %d\n", |
c6f30347 | 156 | le16_to_cpu(cmd.radio_sensor_offset_high)); |
e1991885 | 157 | IWL_DEBUG_CALIB(priv, "Radio sensor offset low: %d\n", |
c6f30347 | 158 | le16_to_cpu(cmd.radio_sensor_offset_low)); |
e1991885 | 159 | IWL_DEBUG_CALIB(priv, "Voltage Ref: %d\n", |
c6f30347 WYG |
160 | le16_to_cpu(cmd.burntVoltageRef)); |
161 | ||
e1991885 | 162 | return iwl_calib_set(priv, (void *)&cmd, sizeof(cmd)); |
c6f30347 WYG |
163 | } |
164 | ||
e1991885 | 165 | static int iwl_send_calib_cfg(struct iwl_priv *priv) |
741a6266 WYG |
166 | { |
167 | struct iwl_calib_cfg_cmd calib_cfg_cmd; | |
168 | struct iwl_host_cmd cmd = { | |
169 | .id = CALIBRATION_CFG_CMD, | |
3fa50738 JB |
170 | .len = { sizeof(struct iwl_calib_cfg_cmd), }, |
171 | .data = { &calib_cfg_cmd, }, | |
741a6266 WYG |
172 | }; |
173 | ||
174 | memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd)); | |
175 | calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL; | |
176 | calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL; | |
177 | calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL; | |
df2a4dc8 WYG |
178 | calib_cfg_cmd.ucd_calib_cfg.flags = |
179 | IWL_CALIB_CFG_FLAG_SEND_COMPLETE_NTFY_MSK; | |
741a6266 | 180 | |
e10a0533 | 181 | return iwl_dvm_send_cmd(priv, &cmd); |
741a6266 WYG |
182 | } |
183 | ||
247c61d6 | 184 | int iwlagn_rx_calib_result(struct iwl_priv *priv, |
48a2d66f | 185 | struct iwl_rx_cmd_buffer *rxb, |
247c61d6 | 186 | struct iwl_device_cmd *cmd) |
741a6266 WYG |
187 | { |
188 | struct iwl_rx_packet *pkt = rxb_addr(rxb); | |
f8d7c1a1 | 189 | struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->data; |
741a6266 | 190 | int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; |
741a6266 WYG |
191 | |
192 | /* reduce the size of the length field itself */ | |
193 | len -= 4; | |
194 | ||
e1991885 | 195 | if (iwl_calib_set(priv, hdr, len)) |
f02c2fd3 JB |
196 | IWL_ERR(priv, "Failed to record calibration data %d\n", |
197 | hdr->op_code); | |
198 | ||
247c61d6 | 199 | return 0; |
741a6266 WYG |
200 | } |
201 | ||
e1991885 | 202 | int iwl_init_alive_start(struct iwl_priv *priv) |
741a6266 | 203 | { |
ca7966c8 | 204 | int ret; |
741a6266 | 205 | |
e1991885 JB |
206 | if (cfg(priv)->bt_params && |
207 | cfg(priv)->bt_params->advanced_bt_coexist) { | |
f7322f8f WYG |
208 | /* |
209 | * Tell uCode we are ready to perform calibration | |
210 | * need to perform this before any calibration | |
211 | * no need to close the envlope since we are going | |
212 | * to load the runtime uCode later. | |
213 | */ | |
e1991885 | 214 | ret = iwl_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN, |
f7322f8f | 215 | BT_COEX_PRIO_TBL_EVT_INIT_CALIB2); |
ca7966c8 JB |
216 | if (ret) |
217 | return ret; | |
f7322f8f WYG |
218 | |
219 | } | |
ca7966c8 | 220 | |
e1991885 | 221 | ret = iwl_send_calib_cfg(priv); |
ca7966c8 JB |
222 | if (ret) |
223 | return ret; | |
bf53f939 SZ |
224 | |
225 | /** | |
226 | * temperature offset calibration is only needed for runtime ucode, | |
227 | * so prepare the value now. | |
228 | */ | |
e1991885 JB |
229 | if (cfg(priv)->need_temp_offset_calib) { |
230 | if (cfg(priv)->temp_offset_v2) | |
231 | return iwl_set_temperature_offset_calib_v2(priv); | |
c6f30347 | 232 | else |
e1991885 | 233 | return iwl_set_temperature_offset_calib(priv); |
c6f30347 | 234 | } |
741a6266 | 235 | |
ca7966c8 | 236 | return 0; |
741a6266 WYG |
237 | } |
238 | ||
e1991885 | 239 | static int iwl_send_wimax_coex(struct iwl_priv *priv) |
f4012413 WYG |
240 | { |
241 | struct iwl_wimax_coex_cmd coex_cmd; | |
242 | ||
e1991885 | 243 | if (cfg(priv)->base_params->support_wimax_coexist) { |
f4012413 WYG |
244 | /* UnMask wake up src at associated sleep */ |
245 | coex_cmd.flags = COEX_FLAGS_ASSOC_WA_UNMASK_MSK; | |
246 | ||
247 | /* UnMask wake up src at unassociated sleep */ | |
248 | coex_cmd.flags |= COEX_FLAGS_UNASSOC_WA_UNMASK_MSK; | |
249 | memcpy(coex_cmd.sta_prio, cu_priorities, | |
250 | sizeof(struct iwl_wimax_coex_event_entry) * | |
251 | COEX_NUM_OF_EVENTS); | |
252 | ||
253 | /* enabling the coexistence feature */ | |
254 | coex_cmd.flags |= COEX_FLAGS_COEX_ENABLE_MSK; | |
255 | ||
256 | /* enabling the priorities tables */ | |
257 | coex_cmd.flags |= COEX_FLAGS_STA_TABLE_VALID_MSK; | |
258 | } else { | |
259 | /* coexistence is disabled */ | |
260 | memset(&coex_cmd, 0, sizeof(coex_cmd)); | |
261 | } | |
e10a0533 | 262 | return iwl_dvm_send_cmd_pdu(priv, |
e419d62d | 263 | COEX_PRIORITY_TABLE_CMD, CMD_SYNC, |
f4012413 WYG |
264 | sizeof(coex_cmd), &coex_cmd); |
265 | } | |
266 | ||
66128b14 | 267 | static const u8 iwl_bt_prio_tbl[BT_COEX_PRIO_TBL_EVT_MAX] = { |
aeb4a2ee WYG |
268 | ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) | |
269 | (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)), | |
270 | ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) | | |
271 | (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)), | |
272 | ((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) | | |
273 | (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)), | |
274 | ((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) | | |
275 | (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)), | |
276 | ((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) | | |
277 | (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)), | |
278 | ((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) | | |
279 | (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)), | |
280 | ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) | | |
281 | (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)), | |
282 | ((BT_COEX_PRIO_TBL_PRIO_COEX_OFF << IWL_BT_COEX_PRIO_TBL_PRIO_POS) | | |
283 | (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)), | |
284 | ((BT_COEX_PRIO_TBL_PRIO_COEX_ON << IWL_BT_COEX_PRIO_TBL_PRIO_POS) | | |
285 | (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)), | |
286 | 0, 0, 0, 0, 0, 0, 0 | |
287 | }; | |
288 | ||
e1991885 | 289 | void iwl_send_prio_tbl(struct iwl_priv *priv) |
aeb4a2ee WYG |
290 | { |
291 | struct iwl_bt_coex_prio_table_cmd prio_tbl_cmd; | |
292 | ||
66128b14 DF |
293 | memcpy(prio_tbl_cmd.prio_tbl, iwl_bt_prio_tbl, |
294 | sizeof(iwl_bt_prio_tbl)); | |
e10a0533 | 295 | if (iwl_dvm_send_cmd_pdu(priv, |
e419d62d | 296 | REPLY_BT_COEX_PRIO_TABLE, CMD_SYNC, |
aeb4a2ee | 297 | sizeof(prio_tbl_cmd), &prio_tbl_cmd)) |
e1991885 | 298 | IWL_ERR(priv, "failed to send BT prio tbl command\n"); |
aeb4a2ee WYG |
299 | } |
300 | ||
e1991885 | 301 | int iwl_send_bt_env(struct iwl_priv *priv, u8 action, u8 type) |
aeb4a2ee WYG |
302 | { |
303 | struct iwl_bt_coex_prot_env_cmd env_cmd; | |
ca7966c8 | 304 | int ret; |
aeb4a2ee WYG |
305 | |
306 | env_cmd.action = action; | |
307 | env_cmd.type = type; | |
e10a0533 | 308 | ret = iwl_dvm_send_cmd_pdu(priv, |
e419d62d | 309 | REPLY_BT_COEX_PROT_ENV, CMD_SYNC, |
ca7966c8 JB |
310 | sizeof(env_cmd), &env_cmd); |
311 | if (ret) | |
e1991885 | 312 | IWL_ERR(priv, "failed to send BT env command\n"); |
ca7966c8 | 313 | return ret; |
aeb4a2ee WYG |
314 | } |
315 | ||
316 | ||
e1991885 | 317 | static int iwl_alive_notify(struct iwl_priv *priv) |
741a6266 | 318 | { |
7415952f | 319 | int ret; |
741a6266 | 320 | |
dfa2bdba EG |
321 | if (!priv->tx_cmd_pool) |
322 | priv->tx_cmd_pool = | |
66128b14 | 323 | kmem_cache_create("iwl_dev_cmd", |
dfa2bdba EG |
324 | sizeof(struct iwl_device_cmd), |
325 | sizeof(void *), 0, NULL); | |
326 | ||
327 | if (!priv->tx_cmd_pool) | |
328 | return -ENOMEM; | |
329 | ||
e1991885 | 330 | iwl_trans_fw_alive(trans(priv)); |
e755f882 JB |
331 | |
332 | priv->passive_no_rx = false; | |
333 | priv->transport_queue_stop = 0; | |
e7cad69c | 334 | |
e1991885 | 335 | ret = iwl_send_wimax_coex(priv); |
7415952f WYG |
336 | if (ret) |
337 | return ret; | |
338 | ||
38622419 | 339 | if (!cfg(priv)->no_xtal_calib) { |
e1991885 | 340 | ret = iwl_set_Xtal_calib(priv); |
93b64105 JB |
341 | if (ret) |
342 | return ret; | |
343 | } | |
741a6266 | 344 | |
e1991885 | 345 | return iwl_send_calib_results(priv); |
741a6266 | 346 | } |
db41dd27 WYG |
347 | |
348 | ||
349 | /** | |
350 | * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host, | |
351 | * using sample data 100 bytes apart. If these sample points are good, | |
352 | * it's a pretty good bet that everything between them is good, too. | |
353 | */ | |
e1991885 | 354 | static int iwl_verify_inst_sparse(struct iwl_priv *priv, |
0692fe41 | 355 | const struct fw_desc *fw_desc) |
db41dd27 | 356 | { |
35b1d92d JB |
357 | __le32 *image = (__le32 *)fw_desc->v_addr; |
358 | u32 len = fw_desc->len; | |
db41dd27 | 359 | u32 val; |
db41dd27 WYG |
360 | u32 i; |
361 | ||
e1991885 | 362 | IWL_DEBUG_FW(priv, "ucode inst image size is %u\n", len); |
db41dd27 WYG |
363 | |
364 | for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) { | |
365 | /* read data comes through single port, auto-incr addr */ | |
366 | /* NOTE: Use the debugless read so we don't flood kernel log | |
367 | * if IWL_DL_IO is set */ | |
e1991885 | 368 | iwl_write_direct32(trans(priv), HBUS_TARG_MEM_RADDR, |
db41dd27 | 369 | i + IWLAGN_RTC_INST_LOWER_BOUND); |
e1991885 | 370 | val = iwl_read32(trans(priv), HBUS_TARG_MEM_RDAT); |
fb66216f JB |
371 | if (val != le32_to_cpu(*image)) |
372 | return -EIO; | |
db41dd27 WYG |
373 | } |
374 | ||
fb66216f | 375 | return 0; |
db41dd27 WYG |
376 | } |
377 | ||
e1991885 | 378 | static void iwl_print_mismatch_inst(struct iwl_priv *priv, |
0692fe41 | 379 | const struct fw_desc *fw_desc) |
db41dd27 | 380 | { |
35b1d92d JB |
381 | __le32 *image = (__le32 *)fw_desc->v_addr; |
382 | u32 len = fw_desc->len; | |
db41dd27 | 383 | u32 val; |
fb66216f JB |
384 | u32 offs; |
385 | int errors = 0; | |
db41dd27 | 386 | |
e1991885 | 387 | IWL_DEBUG_FW(priv, "ucode inst image size is %u\n", len); |
db41dd27 | 388 | |
e1991885 | 389 | iwl_write_direct32(trans(priv), HBUS_TARG_MEM_RADDR, |
db41dd27 WYG |
390 | IWLAGN_RTC_INST_LOWER_BOUND); |
391 | ||
fb66216f JB |
392 | for (offs = 0; |
393 | offs < len && errors < 20; | |
394 | offs += sizeof(u32), image++) { | |
db41dd27 | 395 | /* read data comes through single port, auto-incr addr */ |
e1991885 | 396 | val = iwl_read32(trans(priv), HBUS_TARG_MEM_RDAT); |
db41dd27 | 397 | if (val != le32_to_cpu(*image)) { |
e1991885 | 398 | IWL_ERR(priv, "uCode INST section at " |
fb66216f JB |
399 | "offset 0x%x, is 0x%x, s/b 0x%x\n", |
400 | offs, val, le32_to_cpu(*image)); | |
401 | errors++; | |
db41dd27 WYG |
402 | } |
403 | } | |
db41dd27 WYG |
404 | } |
405 | ||
406 | /** | |
407 | * iwl_verify_ucode - determine which instruction image is in SRAM, | |
408 | * and verify its contents | |
409 | */ | |
e1991885 | 410 | static int iwl_verify_ucode(struct iwl_priv *priv, |
de7f5f92 | 411 | enum iwl_ucode_type ucode_type) |
db41dd27 | 412 | { |
0692fe41 | 413 | const struct fw_img *img = iwl_get_ucode_image(priv, ucode_type); |
baa00056 DF |
414 | |
415 | if (!img) { | |
e1991885 | 416 | IWL_ERR(priv, "Invalid ucode requested (%d)\n", ucode_type); |
baa00056 DF |
417 | return -EINVAL; |
418 | } | |
419 | ||
e1991885 JB |
420 | if (!iwl_verify_inst_sparse(priv, &img->code)) { |
421 | IWL_DEBUG_FW(priv, "uCode is good in inst SRAM\n"); | |
db41dd27 WYG |
422 | return 0; |
423 | } | |
424 | ||
e1991885 | 425 | IWL_ERR(priv, "UCODE IMAGE IN INSTRUCTION SRAM NOT VALID!!\n"); |
fb66216f | 426 | |
e1991885 | 427 | iwl_print_mismatch_inst(priv, &img->code); |
fb66216f | 428 | return -EIO; |
db41dd27 | 429 | } |
ca7966c8 | 430 | |
69a679b0 | 431 | struct iwl_alive_data { |
ca7966c8 JB |
432 | bool valid; |
433 | u8 subtype; | |
434 | }; | |
435 | ||
4bd14dd5 | 436 | static void iwl_alive_fn(struct iwl_notif_wait_data *notif_wait, |
ca7966c8 JB |
437 | struct iwl_rx_packet *pkt, |
438 | void *data) | |
439 | { | |
4bd14dd5 JB |
440 | struct iwl_priv *priv = |
441 | container_of(notif_wait, struct iwl_priv, notif_wait); | |
69a679b0 | 442 | struct iwl_alive_data *alive_data = data; |
ca7966c8 JB |
443 | struct iwl_alive_resp *palive; |
444 | ||
f8d7c1a1 | 445 | palive = (void *)pkt->data; |
ca7966c8 | 446 | |
e1991885 | 447 | IWL_DEBUG_FW(priv, "Alive ucode status 0x%08X revision " |
ca7966c8 JB |
448 | "0x%01X 0x%01X\n", |
449 | palive->is_valid, palive->ver_type, | |
450 | palive->ver_subtype); | |
451 | ||
e1991885 | 452 | priv->shrd->device_pointers.error_event_table = |
ca7966c8 | 453 | le32_to_cpu(palive->error_event_table_ptr); |
e1991885 | 454 | priv->shrd->device_pointers.log_event_table = |
ca7966c8 JB |
455 | le32_to_cpu(palive->log_event_table_ptr); |
456 | ||
457 | alive_data->subtype = palive->ver_subtype; | |
458 | alive_data->valid = palive->is_valid == UCODE_VALID_OK; | |
459 | } | |
460 | ||
461 | #define UCODE_ALIVE_TIMEOUT HZ | |
462 | #define UCODE_CALIB_TIMEOUT (2*HZ) | |
463 | ||
e1991885 | 464 | int iwl_load_ucode_wait_alive(struct iwl_priv *priv, |
de7f5f92 | 465 | enum iwl_ucode_type ucode_type) |
ca7966c8 JB |
466 | { |
467 | struct iwl_notification_wait alive_wait; | |
69a679b0 | 468 | struct iwl_alive_data alive_data; |
0692fe41 | 469 | const struct fw_img *fw; |
ca7966c8 | 470 | int ret; |
de7f5f92 | 471 | enum iwl_ucode_type old_type; |
ca7966c8 | 472 | |
e1991885 JB |
473 | old_type = priv->shrd->ucode_type; |
474 | priv->shrd->ucode_type = ucode_type; | |
475 | fw = iwl_get_ucode_image(priv, ucode_type); | |
ca7966c8 | 476 | |
cf614297 EG |
477 | if (!fw) |
478 | return -EINVAL; | |
479 | ||
4bd14dd5 | 480 | iwl_init_notification_wait(&priv->notif_wait, &alive_wait, REPLY_ALIVE, |
f4720893 JB |
481 | iwl_alive_fn, &alive_data); |
482 | ||
e1991885 | 483 | ret = iwl_trans_start_fw(trans(priv), fw); |
ca7966c8 | 484 | if (ret) { |
e1991885 | 485 | priv->shrd->ucode_type = old_type; |
4bd14dd5 | 486 | iwl_remove_notification(&priv->notif_wait, &alive_wait); |
ca7966c8 JB |
487 | return ret; |
488 | } | |
489 | ||
ca7966c8 JB |
490 | /* |
491 | * Some things may run in the background now, but we | |
492 | * just wait for the ALIVE notification here. | |
493 | */ | |
4bd14dd5 | 494 | ret = iwl_wait_notification(&priv->notif_wait, &alive_wait, |
dd5fe104 | 495 | UCODE_ALIVE_TIMEOUT); |
ca7966c8 | 496 | if (ret) { |
e1991885 | 497 | priv->shrd->ucode_type = old_type; |
ca7966c8 JB |
498 | return ret; |
499 | } | |
500 | ||
501 | if (!alive_data.valid) { | |
e1991885 JB |
502 | IWL_ERR(priv, "Loaded ucode is not valid!\n"); |
503 | priv->shrd->ucode_type = old_type; | |
ca7966c8 JB |
504 | return -EIO; |
505 | } | |
506 | ||
c8ac61cf JB |
507 | /* |
508 | * This step takes a long time (60-80ms!!) and | |
509 | * WoWLAN image should be loaded quickly, so | |
510 | * skip it for WoWLAN. | |
511 | */ | |
512 | if (ucode_type != IWL_UCODE_WOWLAN) { | |
e1991885 | 513 | ret = iwl_verify_ucode(priv, ucode_type); |
c8ac61cf | 514 | if (ret) { |
e1991885 | 515 | priv->shrd->ucode_type = old_type; |
c8ac61cf JB |
516 | return ret; |
517 | } | |
ca7966c8 | 518 | |
c8ac61cf JB |
519 | /* delay a bit to give rfkill time to run */ |
520 | msleep(5); | |
521 | } | |
ca7966c8 | 522 | |
e1991885 | 523 | ret = iwl_alive_notify(priv); |
ca7966c8 | 524 | if (ret) { |
e1991885 | 525 | IWL_WARN(priv, |
ca7966c8 | 526 | "Could not complete ALIVE transition: %d\n", ret); |
e1991885 | 527 | priv->shrd->ucode_type = old_type; |
ca7966c8 JB |
528 | return ret; |
529 | } | |
530 | ||
531 | return 0; | |
532 | } | |
533 | ||
e1991885 | 534 | int iwl_run_init_ucode(struct iwl_priv *priv) |
ca7966c8 JB |
535 | { |
536 | struct iwl_notification_wait calib_wait; | |
537 | int ret; | |
538 | ||
b1eea297 | 539 | lockdep_assert_held(&priv->mutex); |
ca7966c8 JB |
540 | |
541 | /* No init ucode required? Curious, but maybe ok */ | |
0692fe41 | 542 | if (!priv->fw->ucode_init.code.len) |
ca7966c8 JB |
543 | return 0; |
544 | ||
e1991885 | 545 | if (priv->shrd->ucode_type != IWL_UCODE_NONE) |
ca7966c8 JB |
546 | return 0; |
547 | ||
4bd14dd5 | 548 | iwl_init_notification_wait(&priv->notif_wait, &calib_wait, |
ca7966c8 JB |
549 | CALIBRATION_COMPLETE_NOTIFICATION, |
550 | NULL, NULL); | |
551 | ||
552 | /* Will also start the device */ | |
e1991885 | 553 | ret = iwl_load_ucode_wait_alive(priv, IWL_UCODE_INIT); |
ca7966c8 JB |
554 | if (ret) |
555 | goto error; | |
556 | ||
e1991885 | 557 | ret = iwl_init_alive_start(priv); |
ca7966c8 JB |
558 | if (ret) |
559 | goto error; | |
560 | ||
561 | /* | |
562 | * Some things may run in the background now, but we | |
563 | * just wait for the calibration complete notification. | |
564 | */ | |
4bd14dd5 | 565 | ret = iwl_wait_notification(&priv->notif_wait, &calib_wait, |
dd5fe104 | 566 | UCODE_CALIB_TIMEOUT); |
ca7966c8 JB |
567 | |
568 | goto out; | |
569 | ||
570 | error: | |
4bd14dd5 | 571 | iwl_remove_notification(&priv->notif_wait, &calib_wait); |
ca7966c8 JB |
572 | out: |
573 | /* Whatever happened, stop the device */ | |
e1991885 | 574 | iwl_trans_stop_device(trans(priv)); |
ca7966c8 JB |
575 | return ret; |
576 | } |