iwlwifi: support NVM access (EEPROM/OTP)
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl3945-base.c
CommitLineData
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1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
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4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
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26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
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30#include <linux/kernel.h>
31#include <linux/module.h>
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32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
36#include <linux/skbuff.h>
37#include <linux/netdevice.h>
38#include <linux/wireless.h>
39#include <linux/firmware.h>
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40#include <linux/etherdevice.h>
41#include <linux/if_arp.h>
42
43#include <net/ieee80211_radiotap.h>
7e272fcf 44#include <net/lib80211.h>
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45#include <net/mac80211.h>
46
47#include <asm/div64.h>
48
a3139c59
SO
49#define DRV_NAME "iwl3945"
50
dbb6654c
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51#include "iwl-fh.h"
52#include "iwl-3945-fh.h"
600c0e11 53#include "iwl-commands.h"
17f841cd 54#include "iwl-sta.h"
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55#include "iwl-3945.h"
56#include "iwl-helpers.h"
5747d47f 57#include "iwl-core.h"
d20b3c65 58#include "iwl-dev.h"
b481de9c 59
b481de9c
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60/*
61 * module name, copyright, version, etc.
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62 */
63
64#define DRV_DESCRIPTION \
65"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
66
d08853a3 67#ifdef CONFIG_IWLWIFI_DEBUG
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68#define VD "d"
69#else
70#define VD
71#endif
72
c8b0e6e1 73#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
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74#define VS "s"
75#else
76#define VS
77#endif
78
eaa686c3 79#define IWL39_VERSION "1.2.26k" VD VS
01f8162a 80#define DRV_COPYRIGHT "Copyright(c) 2003-2009 Intel Corporation"
a7b75207 81#define DRV_AUTHOR "<ilw@linux.intel.com>"
eaa686c3 82#define DRV_VERSION IWL39_VERSION
b481de9c 83
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84
85MODULE_DESCRIPTION(DRV_DESCRIPTION);
86MODULE_VERSION(DRV_VERSION);
a7b75207 87MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
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88MODULE_LICENSE("GPL");
89
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90 /* module parameters */
91struct iwl_mod_params iwl3945_mod_params = {
92 .num_of_queues = IWL39_MAX_NUM_QUEUES,
9c74d9fb 93 .sw_crypto = 1,
af48d048 94 .restart_fw = 1,
df878d8f
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95 /* the rest are 0 by default */
96};
97
b481de9c 98/*************** STATION TABLE MANAGEMENT ****
9fbab516 99 * mac80211 should be examined to determine if sta_info is duplicating
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100 * the functionality provided here
101 */
102
103/**************************************************************/
01ebd063 104#if 0 /* temporary disable till we add real remove station */
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105/**
106 * iwl3945_remove_station - Remove driver's knowledge of station.
107 *
108 * NOTE: This does not remove station from device's station table.
109 */
4a8a4322 110static u8 iwl3945_remove_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
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111{
112 int index = IWL_INVALID_STATION;
113 int i;
114 unsigned long flags;
115
116 spin_lock_irqsave(&priv->sta_lock, flags);
117
118 if (is_ap)
119 index = IWL_AP_ID;
120 else if (is_broadcast_ether_addr(addr))
3832ec9d 121 index = priv->hw_params.bcast_sta_id;
b481de9c 122 else
3832ec9d 123 for (i = IWL_STA_ID; i < priv->hw_params.max_stations; i++)
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124 if (priv->stations_39[i].used &&
125 !compare_ether_addr(priv->stations_39[i].sta.sta.addr,
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126 addr)) {
127 index = i;
128 break;
129 }
130
131 if (unlikely(index == IWL_INVALID_STATION))
132 goto out;
133
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134 if (priv->stations_39[index].used) {
135 priv->stations_39[index].used = 0;
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136 priv->num_stations--;
137 }
138
139 BUG_ON(priv->num_stations < 0);
140
141out:
142 spin_unlock_irqrestore(&priv->sta_lock, flags);
143 return 0;
144}
556f8db7 145#endif
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146
147/**
148 * iwl3945_clear_stations_table - Clear the driver's station table
149 *
150 * NOTE: This does not clear or otherwise alter the device's station table.
151 */
e0158e61 152void iwl3945_clear_stations_table(struct iwl_priv *priv)
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153{
154 unsigned long flags;
155
156 spin_lock_irqsave(&priv->sta_lock, flags);
157
158 priv->num_stations = 0;
f2c7e521 159 memset(priv->stations_39, 0, sizeof(priv->stations_39));
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160
161 spin_unlock_irqrestore(&priv->sta_lock, flags);
162}
163
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164/**
165 * iwl3945_add_station - Add station to station tables in driver and device
166 */
06fd3d86 167u8 iwl3945_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap, u8 flags, struct ieee80211_sta_ht_cap *ht_info)
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168{
169 int i;
170 int index = IWL_INVALID_STATION;
bb8c093b 171 struct iwl3945_station_entry *station;
b481de9c 172 unsigned long flags_spin;
c14c521e 173 u8 rate;
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174
175 spin_lock_irqsave(&priv->sta_lock, flags_spin);
176 if (is_ap)
177 index = IWL_AP_ID;
178 else if (is_broadcast_ether_addr(addr))
3832ec9d 179 index = priv->hw_params.bcast_sta_id;
b481de9c 180 else
3832ec9d 181 for (i = IWL_STA_ID; i < priv->hw_params.max_stations; i++) {
f2c7e521 182 if (!compare_ether_addr(priv->stations_39[i].sta.sta.addr,
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183 addr)) {
184 index = i;
185 break;
186 }
187
f2c7e521 188 if (!priv->stations_39[i].used &&
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189 index == IWL_INVALID_STATION)
190 index = i;
191 }
192
01ebd063 193 /* These two conditions has the same outcome but keep them separate
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194 since they have different meaning */
195 if (unlikely(index == IWL_INVALID_STATION)) {
196 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
197 return index;
198 }
199
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200 if (priv->stations_39[index].used &&
201 !compare_ether_addr(priv->stations_39[index].sta.sta.addr, addr)) {
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202 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
203 return index;
204 }
205
e1623446 206 IWL_DEBUG_ASSOC(priv, "Add STA ID %d: %pM\n", index, addr);
f2c7e521 207 station = &priv->stations_39[index];
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208 station->used = 1;
209 priv->num_stations++;
210
6440adb5 211 /* Set up the REPLY_ADD_STA command to send to device */
bb8c093b 212 memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
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213 memcpy(station->sta.sta.addr, addr, ETH_ALEN);
214 station->sta.mode = 0;
215 station->sta.sta.sta_id = index;
216 station->sta.station_flags = 0;
217
8318d78a 218 if (priv->band == IEEE80211_BAND_5GHZ)
69946333
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219 rate = IWL_RATE_6M_PLCP;
220 else
221 rate = IWL_RATE_1M_PLCP;
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222
223 /* Turn on both antennas for the station... */
224 station->sta.rate_n_flags =
bb8c093b 225 iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
c14c521e 226
b481de9c 227 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
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228
229 /* Add station to device's station table */
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230 iwl_send_add_sta(priv,
231 (struct iwl_addsta_cmd *)&station->sta, flags);
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232 return index;
233
234}
235
7e4bca5e
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236/**
237 * iwl3945_get_antenna_flags - Get antenna flags for RXON command
238 * @priv: eeprom and antenna fields are used to determine antenna flags
239 *
240 * priv->eeprom39 is used to determine if antenna AUX/MAIN are reversed
241 * iwl3945_mod_params.antenna specifies the antenna diversity mode:
242 *
243 * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
244 * IWL_ANTENNA_MAIN - Force MAIN antenna
245 * IWL_ANTENNA_AUX - Force AUX antenna
246 */
247__le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv)
248{
249 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
250
251 switch (iwl3945_mod_params.antenna) {
252 case IWL_ANTENNA_DIVERSITY:
253 return 0;
254
255 case IWL_ANTENNA_MAIN:
256 if (eeprom->antenna_switch_type)
257 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
258 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
259
260 case IWL_ANTENNA_AUX:
261 if (eeprom->antenna_switch_type)
262 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
263 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
264 }
265
266 /* bad antenna selector value */
267 IWL_ERR(priv, "Bad antenna selector value (0x%x)\n",
268 iwl3945_mod_params.antenna);
269
270 return 0; /* "diversity" is default if error */
271}
272
6e21f15c 273static int iwl3945_set_ccmp_dynamic_key_info(struct iwl_priv *priv,
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274 struct ieee80211_key_conf *keyconf,
275 u8 sta_id)
276{
277 unsigned long flags;
278 __le16 key_flags = 0;
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279 int ret;
280
281 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
282 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
283
284 if (sta_id == priv->hw_params.bcast_sta_id)
285 key_flags |= STA_KEY_MULTICAST_MSK;
286
287 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
288 keyconf->hw_key_idx = keyconf->keyidx;
289 key_flags &= ~STA_KEY_FLG_INVALID;
b481de9c 290
b481de9c 291 spin_lock_irqsave(&priv->sta_lock, flags);
f2c7e521
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292 priv->stations_39[sta_id].keyinfo.alg = keyconf->alg;
293 priv->stations_39[sta_id].keyinfo.keylen = keyconf->keylen;
294 memcpy(priv->stations_39[sta_id].keyinfo.key, keyconf->key,
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295 keyconf->keylen);
296
f2c7e521 297 memcpy(priv->stations_39[sta_id].sta.key.key, keyconf->key,
b481de9c 298 keyconf->keylen);
6e21f15c 299
43da9192 300 if ((priv->stations_39[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK)
6e21f15c 301 == STA_KEY_FLG_NO_ENC)
43da9192 302 priv->stations_39[sta_id].sta.key.key_offset =
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303 iwl_get_free_ucode_key_index(priv);
304 /* else, we are overriding an existing key => no need to allocated room
305 * in uCode. */
306
43da9192 307 WARN(priv->stations_39[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
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308 "no space for a new key");
309
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310 priv->stations_39[sta_id].sta.key.key_flags = key_flags;
311 priv->stations_39[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
312 priv->stations_39[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
b481de9c 313
6e21f15c
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314 IWL_DEBUG_INFO(priv, "hwcrypto: modify ucode station key info\n");
315
316 ret = iwl_send_add_sta(priv,
317 (struct iwl_addsta_cmd *)&priv->stations_39[sta_id].sta, CMD_ASYNC);
318
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319 spin_unlock_irqrestore(&priv->sta_lock, flags);
320
6e21f15c
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321 return ret;
322}
323
324static int iwl3945_set_tkip_dynamic_key_info(struct iwl_priv *priv,
325 struct ieee80211_key_conf *keyconf,
326 u8 sta_id)
327{
328 return -EOPNOTSUPP;
329}
330
331static int iwl3945_set_wep_dynamic_key_info(struct iwl_priv *priv,
332 struct ieee80211_key_conf *keyconf,
333 u8 sta_id)
334{
335 return -EOPNOTSUPP;
b481de9c
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336}
337
4a8a4322 338static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id)
b481de9c
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339{
340 unsigned long flags;
341
342 spin_lock_irqsave(&priv->sta_lock, flags);
bed420d9 343 memset(&priv->stations_39[sta_id].keyinfo, 0, sizeof(struct iwl_hw_key));
f2c7e521 344 memset(&priv->stations_39[sta_id].sta.key, 0,
4c897253 345 sizeof(struct iwl4965_keyinfo));
f2c7e521
AK
346 priv->stations_39[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
347 priv->stations_39[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
348 priv->stations_39[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
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349 spin_unlock_irqrestore(&priv->sta_lock, flags);
350
e1623446 351 IWL_DEBUG_INFO(priv, "hwcrypto: clear ucode station key info\n");
17f841cd
SO
352 iwl_send_add_sta(priv,
353 (struct iwl_addsta_cmd *)&priv->stations_39[sta_id].sta, 0);
b481de9c
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354 return 0;
355}
356
fa11d525 357static int iwl3945_set_dynamic_key(struct iwl_priv *priv,
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358 struct ieee80211_key_conf *keyconf, u8 sta_id)
359{
360 int ret = 0;
361
362 keyconf->hw_key_idx = HW_KEY_DYNAMIC;
363
364 switch (keyconf->alg) {
365 case ALG_CCMP:
366 ret = iwl3945_set_ccmp_dynamic_key_info(priv, keyconf, sta_id);
367 break;
368 case ALG_TKIP:
369 ret = iwl3945_set_tkip_dynamic_key_info(priv, keyconf, sta_id);
370 break;
371 case ALG_WEP:
372 ret = iwl3945_set_wep_dynamic_key_info(priv, keyconf, sta_id);
373 break;
374 default:
1e680233 375 IWL_ERR(priv, "Unknown alg: %s alg = %d\n", __func__, keyconf->alg);
6e21f15c
AK
376 ret = -EINVAL;
377 }
378
379 IWL_DEBUG_WEP(priv, "Set dynamic key: alg= %d len=%d idx=%d sta=%d ret=%d\n",
380 keyconf->alg, keyconf->keylen, keyconf->keyidx,
381 sta_id, ret);
382
383 return ret;
384}
385
386static int iwl3945_remove_static_key(struct iwl_priv *priv)
387{
388 int ret = -EOPNOTSUPP;
389
390 return ret;
391}
392
393static int iwl3945_set_static_key(struct iwl_priv *priv,
394 struct ieee80211_key_conf *key)
395{
396 if (key->alg == ALG_WEP)
397 return -EOPNOTSUPP;
398
399 IWL_ERR(priv, "Static key invalid: alg %d\n", key->alg);
400 return -EINVAL;
401}
402
4a8a4322 403static void iwl3945_clear_free_frames(struct iwl_priv *priv)
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404{
405 struct list_head *element;
406
e1623446 407 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
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408 priv->frames_count);
409
410 while (!list_empty(&priv->free_frames)) {
411 element = priv->free_frames.next;
412 list_del(element);
bb8c093b 413 kfree(list_entry(element, struct iwl3945_frame, list));
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414 priv->frames_count--;
415 }
416
417 if (priv->frames_count) {
39aadf8c 418 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
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419 priv->frames_count);
420 priv->frames_count = 0;
421 }
422}
423
4a8a4322 424static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv)
b481de9c 425{
bb8c093b 426 struct iwl3945_frame *frame;
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427 struct list_head *element;
428 if (list_empty(&priv->free_frames)) {
429 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
430 if (!frame) {
15b1687c 431 IWL_ERR(priv, "Could not allocate frame!\n");
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432 return NULL;
433 }
434
435 priv->frames_count++;
436 return frame;
437 }
438
439 element = priv->free_frames.next;
440 list_del(element);
bb8c093b 441 return list_entry(element, struct iwl3945_frame, list);
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442}
443
4a8a4322 444static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame)
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445{
446 memset(frame, 0, sizeof(*frame));
447 list_add(&frame->list, &priv->free_frames);
448}
449
4a8a4322 450unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv,
b481de9c 451 struct ieee80211_hdr *hdr,
73ec1cc2 452 int left)
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453{
454
8ccde88a 455 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB
456 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
457 (priv->iw_mode != NL80211_IFTYPE_AP)))
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458 return 0;
459
460 if (priv->ibss_beacon->len > left)
461 return 0;
462
463 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
464
465 return priv->ibss_beacon->len;
466}
467
4a8a4322 468static int iwl3945_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 469{
bb8c093b 470 struct iwl3945_frame *frame;
b481de9c
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471 unsigned int frame_size;
472 int rc;
473 u8 rate;
474
bb8c093b 475 frame = iwl3945_get_free_frame(priv);
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476
477 if (!frame) {
15b1687c 478 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
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479 "command.\n");
480 return -ENOMEM;
481 }
482
8ccde88a 483 rate = iwl_rate_get_lowest_plcp(priv);
b481de9c 484
bb8c093b 485 frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 486
518099a8 487 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
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488 &frame->u.cmd[0]);
489
bb8c093b 490 iwl3945_free_frame(priv, frame);
b481de9c
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491
492 return rc;
493}
494
4a8a4322 495static void iwl3945_unset_hw_params(struct iwl_priv *priv)
b481de9c 496{
3832ec9d 497 if (priv->shared_virt)
b481de9c 498 pci_free_consistent(priv->pci_dev,
bb8c093b 499 sizeof(struct iwl3945_shared),
3832ec9d
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500 priv->shared_virt,
501 priv->shared_phys);
b481de9c
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502}
503
b481de9c 504#define MAX_UCODE_BEACON_INTERVAL 1024
c1b4aa3f 505#define INTEL_CONN_LISTEN_INTERVAL cpu_to_le16(0xA)
b481de9c 506
bb8c093b 507static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
b481de9c
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508{
509 u16 new_val = 0;
510 u16 beacon_factor = 0;
511
512 beacon_factor =
513 (beacon_val + MAX_UCODE_BEACON_INTERVAL)
514 / MAX_UCODE_BEACON_INTERVAL;
515 new_val = beacon_val / beacon_factor;
516
517 return cpu_to_le16(new_val);
518}
519
4a8a4322 520static void iwl3945_setup_rxon_timing(struct iwl_priv *priv)
b481de9c
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521{
522 u64 interval_tm_unit;
523 u64 tsf, result;
524 unsigned long flags;
525 struct ieee80211_conf *conf = NULL;
526 u16 beacon_int = 0;
527
528 conf = ieee80211_get_hw_conf(priv->hw);
529
530 spin_lock_irqsave(&priv->lock, flags);
28afaf91 531 priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
b481de9c
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532 priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
533
28afaf91 534 tsf = priv->timestamp;
b481de9c
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535
536 beacon_int = priv->beacon_int;
537 spin_unlock_irqrestore(&priv->lock, flags);
538
05c914fe 539 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
b481de9c
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540 if (beacon_int == 0) {
541 priv->rxon_timing.beacon_interval = cpu_to_le16(100);
542 priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
543 } else {
544 priv->rxon_timing.beacon_interval =
545 cpu_to_le16(beacon_int);
546 priv->rxon_timing.beacon_interval =
bb8c093b 547 iwl3945_adjust_beacon_interval(
b481de9c
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548 le16_to_cpu(priv->rxon_timing.beacon_interval));
549 }
550
551 priv->rxon_timing.atim_window = 0;
552 } else {
553 priv->rxon_timing.beacon_interval =
57c4d7b4
JB
554 iwl3945_adjust_beacon_interval(
555 priv->vif->bss_conf.beacon_int);
b481de9c
ZY
556 /* TODO: we need to get atim_window from upper stack
557 * for now we set to 0 */
558 priv->rxon_timing.atim_window = 0;
559 }
560
561 interval_tm_unit =
562 (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
563 result = do_div(tsf, interval_tm_unit);
564 priv->rxon_timing.beacon_init_val =
565 cpu_to_le32((u32) ((u64) interval_tm_unit - result));
566
e1623446
TW
567 IWL_DEBUG_ASSOC(priv,
568 "beacon interval %d beacon timer %d beacon tim %d\n",
b481de9c
ZY
569 le16_to_cpu(priv->rxon_timing.beacon_interval),
570 le32_to_cpu(priv->rxon_timing.beacon_init_val),
571 le16_to_cpu(priv->rxon_timing.atim_window));
572}
573
4a8a4322 574static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv,
e039fa4a 575 struct ieee80211_tx_info *info,
c2d79b48 576 struct iwl_cmd *cmd,
b481de9c 577 struct sk_buff *skb_frag,
6e21f15c 578 int sta_id)
b481de9c 579{
e52119c5 580 struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
bed420d9 581 struct iwl_hw_key *keyinfo = &priv->stations_39[sta_id].keyinfo;
b481de9c
ZY
582
583 switch (keyinfo->alg) {
584 case ALG_CCMP:
e52119c5
WT
585 tx->sec_ctl = TX_CMD_SEC_CCM;
586 memcpy(tx->key, keyinfo->key, keyinfo->keylen);
e1623446 587 IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
b481de9c
ZY
588 break;
589
590 case ALG_TKIP:
b481de9c
ZY
591 break;
592
593 case ALG_WEP:
e52119c5 594 tx->sec_ctl = TX_CMD_SEC_WEP |
e039fa4a 595 (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
b481de9c
ZY
596
597 if (keyinfo->keylen == 13)
e52119c5 598 tx->sec_ctl |= TX_CMD_SEC_KEY128;
b481de9c 599
e52119c5 600 memcpy(&tx->key[3], keyinfo->key, keyinfo->keylen);
b481de9c 601
e1623446 602 IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
e039fa4a 603 "with key %d\n", info->control.hw_key->hw_key_idx);
b481de9c
ZY
604 break;
605
b481de9c 606 default:
978785a3 607 IWL_ERR(priv, "Unknown encode alg %d\n", keyinfo->alg);
b481de9c
ZY
608 break;
609 }
610}
611
612/*
613 * handle build REPLY_TX command notification.
614 */
4a8a4322 615static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv,
c2d79b48 616 struct iwl_cmd *cmd,
e039fa4a 617 struct ieee80211_tx_info *info,
e52119c5 618 struct ieee80211_hdr *hdr, u8 std_id)
b481de9c 619{
e52119c5
WT
620 struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
621 __le32 tx_flags = tx->tx_flags;
fd7c8a40 622 __le16 fc = hdr->frame_control;
e6a9854b 623 u8 rc_flags = info->control.rates[0].flags;
b481de9c 624
e52119c5 625 tx->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e039fa4a 626 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
b481de9c 627 tx_flags |= TX_CMD_FLG_ACK_MSK;
fd7c8a40 628 if (ieee80211_is_mgmt(fc))
b481de9c 629 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
fd7c8a40 630 if (ieee80211_is_probe_resp(fc) &&
b481de9c
ZY
631 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
632 tx_flags |= TX_CMD_FLG_TSF_MSK;
633 } else {
634 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
635 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
636 }
637
e52119c5 638 tx->sta_id = std_id;
8b7b1e05 639 if (ieee80211_has_morefrags(fc))
b481de9c
ZY
640 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
641
fd7c8a40
HH
642 if (ieee80211_is_data_qos(fc)) {
643 u8 *qc = ieee80211_get_qos_ctl(hdr);
e52119c5 644 tx->tid_tspec = qc[0] & 0xf;
b481de9c 645 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 646 } else {
b481de9c 647 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 648 }
b481de9c 649
e6a9854b 650 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
b481de9c
ZY
651 tx_flags |= TX_CMD_FLG_RTS_MSK;
652 tx_flags &= ~TX_CMD_FLG_CTS_MSK;
e6a9854b 653 } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
b481de9c
ZY
654 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
655 tx_flags |= TX_CMD_FLG_CTS_MSK;
656 }
657
658 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
659 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
660
661 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
fd7c8a40
HH
662 if (ieee80211_is_mgmt(fc)) {
663 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
e52119c5 664 tx->timeout.pm_frame_timeout = cpu_to_le16(3);
b481de9c 665 else
e52119c5 666 tx->timeout.pm_frame_timeout = cpu_to_le16(2);
ab53d8af 667 } else {
e52119c5 668 tx->timeout.pm_frame_timeout = 0;
5c8df2d5 669#ifdef CONFIG_IWLWIFI_LEDS
ab53d8af
MA
670 priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
671#endif
672 }
b481de9c 673
e52119c5
WT
674 tx->driver_txop = 0;
675 tx->tx_flags = tx_flags;
676 tx->next_frame_len = 0;
b481de9c
ZY
677}
678
b481de9c
ZY
679/*
680 * start REPLY_TX command process
681 */
4a8a4322 682static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
b481de9c
ZY
683{
684 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
e039fa4a 685 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
e52119c5 686 struct iwl3945_tx_cmd *tx;
188cf6c7 687 struct iwl_tx_queue *txq = NULL;
d20b3c65 688 struct iwl_queue *q = NULL;
e52119c5 689 struct iwl_cmd *out_cmd = NULL;
b481de9c
ZY
690 dma_addr_t phys_addr;
691 dma_addr_t txcmd_phys;
e52119c5 692 int txq_id = skb_get_queue_mapping(skb);
df833b1d 693 u16 len, idx, len_org, hdr_len; /* TODO: len_org is not used */
54dbb525
TW
694 u8 id;
695 u8 unicast;
b481de9c 696 u8 sta_id;
54dbb525 697 u8 tid = 0;
b481de9c 698 u16 seq_number = 0;
fd7c8a40 699 __le16 fc;
b481de9c 700 u8 wait_write_ptr = 0;
54dbb525 701 u8 *qc = NULL;
b481de9c
ZY
702 unsigned long flags;
703 int rc;
704
705 spin_lock_irqsave(&priv->lock, flags);
775a6e27 706 if (iwl_is_rfkill(priv)) {
e1623446 707 IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
b481de9c
ZY
708 goto drop_unlock;
709 }
710
e039fa4a 711 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
15b1687c 712 IWL_ERR(priv, "ERROR: No TX rate available.\n");
b481de9c
ZY
713 goto drop_unlock;
714 }
715
716 unicast = !is_multicast_ether_addr(hdr->addr1);
717 id = 0;
718
fd7c8a40 719 fc = hdr->frame_control;
b481de9c 720
d08853a3 721#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c 722 if (ieee80211_is_auth(fc))
e1623446 723 IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
fd7c8a40 724 else if (ieee80211_is_assoc_req(fc))
e1623446 725 IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
fd7c8a40 726 else if (ieee80211_is_reassoc_req(fc))
e1623446 727 IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
b481de9c
ZY
728#endif
729
7878a5a4 730 /* drop all data frame if we are not associated */
914233d6 731 if (ieee80211_is_data(fc) &&
279b05d4 732 (!iwl_is_monitor_mode(priv)) && /* packet injection */
8ccde88a 733 (!iwl_is_associated(priv) ||
05c914fe 734 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
e1623446 735 IWL_DEBUG_DROP(priv, "Dropping - !iwl_is_associated\n");
b481de9c
ZY
736 goto drop_unlock;
737 }
738
739 spin_unlock_irqrestore(&priv->lock, flags);
740
7294ec95 741 hdr_len = ieee80211_hdrlen(fc);
6440adb5
CB
742
743 /* Find (or create) index into station table for destination station */
f5d30266 744 sta_id = iwl_get_sta_id(priv, hdr);
b481de9c 745 if (sta_id == IWL_INVALID_STATION) {
e1623446 746 IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
e174961c 747 hdr->addr1);
b481de9c
ZY
748 goto drop;
749 }
750
e1623446 751 IWL_DEBUG_RATE(priv, "station Id %d\n", sta_id);
b481de9c 752
fd7c8a40
HH
753 if (ieee80211_is_data_qos(fc)) {
754 qc = ieee80211_get_qos_ctl(hdr);
7294ec95 755 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
f2c7e521 756 seq_number = priv->stations_39[sta_id].tid[tid].seq_number &
b481de9c
ZY
757 IEEE80211_SCTL_SEQ;
758 hdr->seq_ctrl = cpu_to_le16(seq_number) |
759 (hdr->seq_ctrl &
c1b4aa3f 760 cpu_to_le16(IEEE80211_SCTL_FRAG));
b481de9c
ZY
761 seq_number += 0x10;
762 }
6440adb5
CB
763
764 /* Descriptor for chosen Tx queue */
188cf6c7 765 txq = &priv->txq[txq_id];
b481de9c
ZY
766 q = &txq->q;
767
768 spin_lock_irqsave(&priv->lock, flags);
769
fc4b6853 770 idx = get_cmd_index(q, q->write_ptr, 0);
b481de9c 771
6440adb5 772 /* Set up driver data for this TFD */
dbb6654c 773 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
fc4b6853 774 txq->txb[q->write_ptr].skb[0] = skb;
6440adb5
CB
775
776 /* Init first empty entry in queue's array of Tx/cmd buffers */
188cf6c7 777 out_cmd = txq->cmd[idx];
e52119c5 778 tx = (struct iwl3945_tx_cmd *)out_cmd->cmd.payload;
b481de9c 779 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
e52119c5 780 memset(tx, 0, sizeof(*tx));
6440adb5
CB
781
782 /*
783 * Set up the Tx-command (not MAC!) header.
784 * Store the chosen Tx queue and TFD index within the sequence field;
785 * after Tx, uCode's Tx response will return this value so driver can
786 * locate the frame within the tx queue and do post-tx processing.
787 */
b481de9c
ZY
788 out_cmd->hdr.cmd = REPLY_TX;
789 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
fc4b6853 790 INDEX_TO_SEQ(q->write_ptr)));
6440adb5
CB
791
792 /* Copy MAC header from skb into command buffer */
e52119c5 793 memcpy(tx->hdr, hdr, hdr_len);
b481de9c 794
df833b1d
RC
795
796 if (info->control.hw_key)
797 iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, sta_id);
798
799 /* TODO need this for burst mode later on */
800 iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, sta_id);
801
802 /* set is_hcca to 0; it probably will never be implemented */
803 iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
804
805 /* Total # bytes to be transmitted */
806 len = (u16)skb->len;
807 tx->len = cpu_to_le16(len);
808
809
810 tx->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
811 tx->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
812
813 if (!ieee80211_has_morefrags(hdr->frame_control)) {
814 txq->need_update = 1;
815 if (qc)
816 priv->stations_39[sta_id].tid[tid].seq_number = seq_number;
817 } else {
818 wait_write_ptr = 1;
819 txq->need_update = 0;
820 }
821
822 IWL_DEBUG_TX(priv, "sequence nr = 0X%x \n",
823 le16_to_cpu(out_cmd->hdr.sequence));
824 IWL_DEBUG_TX(priv, "tx_flags = 0X%x \n", le32_to_cpu(tx->tx_flags));
825 iwl_print_hex_dump(priv, IWL_DL_TX, tx, sizeof(*tx));
826 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx->hdr,
827 ieee80211_hdrlen(fc));
828
6440adb5
CB
829 /*
830 * Use the first empty entry in this queue's command buffer array
831 * to contain the Tx command and MAC header concatenated together
832 * (payload data will be in another buffer).
833 * Size of this varies, due to varying MAC header length.
834 * If end is not dword aligned, we'll have 2 extra bytes at the end
835 * of the MAC header (device reads on dword boundaries).
836 * We'll tell device about this padding later.
837 */
3832ec9d 838 len = sizeof(struct iwl3945_tx_cmd) +
4c897253 839 sizeof(struct iwl_cmd_header) + hdr_len;
b481de9c
ZY
840
841 len_org = len;
842 len = (len + 3) & ~3;
843
844 if (len_org != len)
845 len_org = 1;
846 else
847 len_org = 0;
848
6440adb5
CB
849 /* Physical address of this Tx command's header (not MAC header!),
850 * within command buffer array. */
df833b1d
RC
851 txcmd_phys = pci_map_single(priv->pci_dev, &out_cmd->hdr,
852 len, PCI_DMA_TODEVICE);
853 /* we do not map meta data ... so we can safely access address to
854 * provide to unmap command*/
188cf6c7 855 pci_unmap_addr_set(&out_cmd->meta, mapping, txcmd_phys);
df833b1d 856 pci_unmap_len_set(&out_cmd->meta, len, len);
b481de9c 857
6440adb5
CB
858 /* Add buffer containing Tx command and MAC(!) header to TFD's
859 * first entry */
7aaa1d79
SO
860 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
861 txcmd_phys, len, 1, 0);
b481de9c 862
b481de9c 863
6440adb5
CB
864 /* Set up TFD's 2nd entry to point directly to remainder of skb,
865 * if any (802.11 null frames have no payload). */
b481de9c
ZY
866 len = skb->len - hdr_len;
867 if (len) {
868 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
869 len, PCI_DMA_TODEVICE);
7aaa1d79
SO
870 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
871 phys_addr, len,
872 0, U32_PAD(len));
b481de9c
ZY
873 }
874
b481de9c 875
6440adb5 876 /* Tell device the write index *just past* this latest filled TFD */
c54b679d 877 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
4f3602c8 878 rc = iwl_txq_update_write_ptr(priv, txq);
b481de9c
ZY
879 spin_unlock_irqrestore(&priv->lock, flags);
880
881 if (rc)
882 return rc;
883
d20b3c65 884 if ((iwl_queue_space(q) < q->high_mark)
b481de9c
ZY
885 && priv->mac80211_registered) {
886 if (wait_write_ptr) {
887 spin_lock_irqsave(&priv->lock, flags);
888 txq->need_update = 1;
4f3602c8 889 iwl_txq_update_write_ptr(priv, txq);
b481de9c
ZY
890 spin_unlock_irqrestore(&priv->lock, flags);
891 }
892
e4e72fb4 893 iwl_stop_queue(priv, skb_get_queue_mapping(skb));
b481de9c
ZY
894 }
895
896 return 0;
897
898drop_unlock:
899 spin_unlock_irqrestore(&priv->lock, flags);
900drop:
901 return -1;
902}
903
c8b0e6e1 904#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY
905
906#include "iwl-spectrum.h"
907
908#define BEACON_TIME_MASK_LOW 0x00FFFFFF
909#define BEACON_TIME_MASK_HIGH 0xFF000000
910#define TIME_UNIT 1024
911
912/*
913 * extended beacon time format
914 * time in usec will be changed into a 32-bit value in 8:24 format
915 * the high 1 byte is the beacon counts
916 * the lower 3 bytes is the time in usec within one beacon interval
917 */
918
bb8c093b 919static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
b481de9c
ZY
920{
921 u32 quot;
922 u32 rem;
923 u32 interval = beacon_interval * 1024;
924
925 if (!interval || !usec)
926 return 0;
927
928 quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
929 rem = (usec % interval) & BEACON_TIME_MASK_LOW;
930
931 return (quot << 24) + rem;
932}
933
934/* base is usually what we get from ucode with each received frame,
935 * the same as HW timer counter counting down
936 */
937
bb8c093b 938static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
b481de9c
ZY
939{
940 u32 base_low = base & BEACON_TIME_MASK_LOW;
941 u32 addon_low = addon & BEACON_TIME_MASK_LOW;
942 u32 interval = beacon_interval * TIME_UNIT;
943 u32 res = (base & BEACON_TIME_MASK_HIGH) +
944 (addon & BEACON_TIME_MASK_HIGH);
945
946 if (base_low > addon_low)
947 res += base_low - addon_low;
948 else if (base_low < addon_low) {
949 res += interval + base_low - addon_low;
950 res += (1 << 24);
951 } else
952 res += (1 << 24);
953
954 return cpu_to_le32(res);
955}
956
4a8a4322 957static int iwl3945_get_measurement(struct iwl_priv *priv,
b481de9c
ZY
958 struct ieee80211_measurement_params *params,
959 u8 type)
960{
600c0e11 961 struct iwl_spectrum_cmd spectrum;
3d24a9f7 962 struct iwl_rx_packet *res;
c2d79b48 963 struct iwl_host_cmd cmd = {
b481de9c
ZY
964 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
965 .data = (void *)&spectrum,
966 .meta.flags = CMD_WANT_SKB,
967 };
968 u32 add_time = le64_to_cpu(params->start_time);
969 int rc;
970 int spectrum_resp_status;
971 int duration = le16_to_cpu(params->duration);
972
8ccde88a 973 if (iwl_is_associated(priv))
b481de9c 974 add_time =
bb8c093b 975 iwl3945_usecs_to_beacons(
b481de9c
ZY
976 le64_to_cpu(params->start_time) - priv->last_tsf,
977 le16_to_cpu(priv->rxon_timing.beacon_interval));
978
979 memset(&spectrum, 0, sizeof(spectrum));
980
981 spectrum.channel_count = cpu_to_le16(1);
982 spectrum.flags =
983 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
984 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
985 cmd.len = sizeof(spectrum);
986 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
987
8ccde88a 988 if (iwl_is_associated(priv))
b481de9c 989 spectrum.start_time =
bb8c093b 990 iwl3945_add_beacon_time(priv->last_beacon_time,
b481de9c
ZY
991 add_time,
992 le16_to_cpu(priv->rxon_timing.beacon_interval));
993 else
994 spectrum.start_time = 0;
995
996 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
997 spectrum.channels[0].channel = params->channel;
998 spectrum.channels[0].type = type;
8ccde88a 999 if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
b481de9c
ZY
1000 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
1001 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
1002
518099a8 1003 rc = iwl_send_cmd_sync(priv, &cmd);
b481de9c
ZY
1004 if (rc)
1005 return rc;
1006
3d24a9f7 1007 res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
b481de9c 1008 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
15b1687c 1009 IWL_ERR(priv, "Bad return from REPLY_RX_ON_ASSOC command\n");
b481de9c
ZY
1010 rc = -EIO;
1011 }
1012
1013 spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
1014 switch (spectrum_resp_status) {
1015 case 0: /* Command will be handled */
1016 if (res->u.spectrum.id != 0xff) {
e1623446 1017 IWL_DEBUG_INFO(priv, "Replaced existing measurement: %d\n",
bc434dd2 1018 res->u.spectrum.id);
b481de9c
ZY
1019 priv->measurement_status &= ~MEASUREMENT_READY;
1020 }
1021 priv->measurement_status |= MEASUREMENT_ACTIVE;
1022 rc = 0;
1023 break;
1024
1025 case 1: /* Command will not be handled */
1026 rc = -EAGAIN;
1027 break;
1028 }
1029
1030 dev_kfree_skb_any(cmd.meta.u.skb);
1031
1032 return rc;
1033}
1034#endif
1035
4a8a4322 1036static void iwl3945_rx_reply_alive(struct iwl_priv *priv,
6100b588 1037 struct iwl_rx_mem_buffer *rxb)
b481de9c 1038{
3d24a9f7
TW
1039 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
1040 struct iwl_alive_resp *palive;
b481de9c
ZY
1041 struct delayed_work *pwork;
1042
1043 palive = &pkt->u.alive_frame;
1044
e1623446 1045 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY
1046 "0x%01X 0x%01X\n",
1047 palive->is_valid, palive->ver_type,
1048 palive->ver_subtype);
1049
1050 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 1051 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
3d24a9f7
TW
1052 memcpy(&priv->card_alive_init, &pkt->u.alive_frame,
1053 sizeof(struct iwl_alive_resp));
b481de9c
ZY
1054 pwork = &priv->init_alive_start;
1055 } else {
e1623446 1056 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 1057 memcpy(&priv->card_alive, &pkt->u.alive_frame,
3d24a9f7 1058 sizeof(struct iwl_alive_resp));
b481de9c 1059 pwork = &priv->alive_start;
bb8c093b 1060 iwl3945_disable_events(priv);
b481de9c
ZY
1061 }
1062
1063 /* We delay the ALIVE response by 5ms to
1064 * give the HW RF Kill time to activate... */
1065 if (palive->is_valid == UCODE_VALID_OK)
1066 queue_delayed_work(priv->workqueue, pwork,
1067 msecs_to_jiffies(5));
1068 else
39aadf8c 1069 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY
1070}
1071
4a8a4322 1072static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv,
6100b588 1073 struct iwl_rx_mem_buffer *rxb)
b481de9c 1074{
c7e035a9 1075#ifdef CONFIG_IWLWIFI_DEBUG
3d24a9f7 1076 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
c7e035a9 1077#endif
b481de9c 1078
e1623446 1079 IWL_DEBUG_RX(priv, "Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
b481de9c
ZY
1080 return;
1081}
1082
bb8c093b 1083static void iwl3945_bg_beacon_update(struct work_struct *work)
b481de9c 1084{
4a8a4322
AK
1085 struct iwl_priv *priv =
1086 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY
1087 struct sk_buff *beacon;
1088
1089 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 1090 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY
1091
1092 if (!beacon) {
15b1687c 1093 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY
1094 return;
1095 }
1096
1097 mutex_lock(&priv->mutex);
1098 /* new beacon skb is allocated every time; dispose previous.*/
1099 if (priv->ibss_beacon)
1100 dev_kfree_skb(priv->ibss_beacon);
1101
1102 priv->ibss_beacon = beacon;
1103 mutex_unlock(&priv->mutex);
1104
bb8c093b 1105 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
1106}
1107
4a8a4322 1108static void iwl3945_rx_beacon_notif(struct iwl_priv *priv,
6100b588 1109 struct iwl_rx_mem_buffer *rxb)
b481de9c 1110{
d08853a3 1111#ifdef CONFIG_IWLWIFI_DEBUG
3d24a9f7 1112 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
bb8c093b 1113 struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
b481de9c
ZY
1114 u8 rate = beacon->beacon_notify_hdr.rate;
1115
e1623446 1116 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c
ZY
1117 "tsf %d %d rate %d\n",
1118 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
1119 beacon->beacon_notify_hdr.failure_frame,
1120 le32_to_cpu(beacon->ibss_mgr_status),
1121 le32_to_cpu(beacon->high_tsf),
1122 le32_to_cpu(beacon->low_tsf), rate);
1123#endif
1124
05c914fe 1125 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY
1126 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
1127 queue_work(priv->workqueue, &priv->beacon_update);
1128}
1129
b481de9c
ZY
1130/* Handle notification from uCode that card's power state is changing
1131 * due to software, hardware, or critical temperature RFKILL */
4a8a4322 1132static void iwl3945_rx_card_state_notif(struct iwl_priv *priv,
6100b588 1133 struct iwl_rx_mem_buffer *rxb)
b481de9c 1134{
3d24a9f7 1135 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY
1136 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
1137 unsigned long status = priv->status;
1138
e1623446 1139 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
b481de9c
ZY
1140 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
1141 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
1142
5d49f498 1143 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
1144 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1145
1146 if (flags & HW_CARD_DISABLED)
1147 set_bit(STATUS_RF_KILL_HW, &priv->status);
1148 else
1149 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1150
1151
1152 if (flags & SW_CARD_DISABLED)
1153 set_bit(STATUS_RF_KILL_SW, &priv->status);
1154 else
1155 clear_bit(STATUS_RF_KILL_SW, &priv->status);
1156
af0053d6 1157 iwl_scan_cancel(priv);
b481de9c
ZY
1158
1159 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
1160 test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
1161 (test_bit(STATUS_RF_KILL_SW, &status) !=
1162 test_bit(STATUS_RF_KILL_SW, &priv->status)))
1163 queue_work(priv->workqueue, &priv->rf_kill);
1164 else
1165 wake_up_interruptible(&priv->wait_command_queue);
1166}
1167
1168/**
bb8c093b 1169 * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY
1170 *
1171 * Setup the RX handlers for each of the reply types sent from the uCode
1172 * to the host.
1173 *
1174 * This function chains into the hardware specific files for them to setup
1175 * any hardware specific handlers as well.
1176 */
4a8a4322 1177static void iwl3945_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 1178{
bb8c093b
CH
1179 priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
1180 priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
261b9c33 1181 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
8ccde88a 1182 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
030f05ed 1183 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 1184 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
030f05ed 1185 iwl_rx_pm_debug_statistics_notif;
bb8c093b 1186 priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
b481de9c 1187
9fbab516
BC
1188 /*
1189 * The same handler is used for both the REPLY to a discrete
1190 * statistics request from the host as well as for the periodic
1191 * statistics notifications (after received beacons) from the uCode.
b481de9c 1192 */
bb8c093b
CH
1193 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
1194 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
b481de9c 1195
261b9c33 1196 iwl_setup_spectrum_handlers(priv);
cade0eb2 1197 iwl_setup_rx_scan_handlers(priv);
bb8c093b 1198 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
b481de9c 1199
9fbab516 1200 /* Set up hardware specific Rx handlers */
bb8c093b 1201 iwl3945_hw_rx_handler_setup(priv);
b481de9c
ZY
1202}
1203
b481de9c
ZY
1204/************************** RX-FUNCTIONS ****************************/
1205/*
1206 * Rx theory of operation
1207 *
1208 * The host allocates 32 DMA target addresses and passes the host address
1209 * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
1210 * 0 to 31
1211 *
1212 * Rx Queue Indexes
1213 * The host/firmware share two index registers for managing the Rx buffers.
1214 *
1215 * The READ index maps to the first position that the firmware may be writing
1216 * to -- the driver can read up to (but not including) this position and get
1217 * good data.
1218 * The READ index is managed by the firmware once the card is enabled.
1219 *
1220 * The WRITE index maps to the last position the driver has read from -- the
1221 * position preceding WRITE is the last slot the firmware can place a packet.
1222 *
1223 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
1224 * WRITE = READ.
1225 *
9fbab516 1226 * During initialization, the host sets up the READ queue position to the first
b481de9c
ZY
1227 * INDEX position, and WRITE to the last (READ - 1 wrapped)
1228 *
9fbab516 1229 * When the firmware places a packet in a buffer, it will advance the READ index
b481de9c
ZY
1230 * and fire the RX interrupt. The driver can then query the READ index and
1231 * process as many packets as possible, moving the WRITE index forward as it
1232 * resets the Rx queue buffers with new memory.
1233 *
1234 * The management in the driver is as follows:
1235 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
1236 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
01ebd063 1237 * to replenish the iwl->rxq->rx_free.
bb8c093b 1238 * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
b481de9c
ZY
1239 * iwl->rxq is replenished and the READ INDEX is updated (updating the
1240 * 'processed' and 'read' driver indexes as well)
1241 * + A received packet is processed and handed to the kernel network stack,
1242 * detached from the iwl->rxq. The driver 'processed' index is updated.
1243 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
1244 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
1245 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
1246 * were enough free buffers and RX_STALLED is set it is cleared.
1247 *
1248 *
1249 * Driver sequence:
1250 *
9fbab516 1251 * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
bb8c093b 1252 * iwl3945_rx_queue_restock
9fbab516 1253 * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
b481de9c
ZY
1254 * queue, updates firmware pointers, and updates
1255 * the WRITE index. If insufficient rx_free buffers
bb8c093b 1256 * are available, schedules iwl3945_rx_replenish
b481de9c
ZY
1257 *
1258 * -- enable interrupts --
6100b588 1259 * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the
b481de9c
ZY
1260 * READ INDEX, detaching the SKB from the pool.
1261 * Moves the packet buffer from queue to rx_used.
bb8c093b 1262 * Calls iwl3945_rx_queue_restock to refill any empty
b481de9c
ZY
1263 * slots.
1264 * ...
1265 *
1266 */
1267
b481de9c 1268/**
9fbab516 1269 * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
b481de9c 1270 */
4a8a4322 1271static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv,
b481de9c
ZY
1272 dma_addr_t dma_addr)
1273{
1274 return cpu_to_le32((u32)dma_addr);
1275}
1276
1277/**
bb8c093b 1278 * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
b481de9c 1279 *
9fbab516 1280 * If there are slots in the RX queue that need to be restocked,
b481de9c 1281 * and we have free pre-allocated buffers, fill the ranks as much
9fbab516 1282 * as we can, pulling from rx_free.
b481de9c
ZY
1283 *
1284 * This moves the 'write' index forward to catch up with 'processed', and
1285 * also updates the memory address in the firmware to reference the new
1286 * target buffer.
1287 */
4a8a4322 1288static int iwl3945_rx_queue_restock(struct iwl_priv *priv)
b481de9c 1289{
cc2f362c 1290 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c 1291 struct list_head *element;
6100b588 1292 struct iwl_rx_mem_buffer *rxb;
b481de9c
ZY
1293 unsigned long flags;
1294 int write, rc;
1295
1296 spin_lock_irqsave(&rxq->lock, flags);
1297 write = rxq->write & ~0x7;
37d68317 1298 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
6440adb5 1299 /* Get next free Rx buffer, remove from free list */
b481de9c 1300 element = rxq->rx_free.next;
6100b588 1301 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
b481de9c 1302 list_del(element);
6440adb5
CB
1303
1304 /* Point to Rx buffer via next RBD in circular buffer */
6100b588 1305 rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->real_dma_addr);
b481de9c
ZY
1306 rxq->queue[rxq->write] = rxb;
1307 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
1308 rxq->free_count--;
1309 }
1310 spin_unlock_irqrestore(&rxq->lock, flags);
1311 /* If the pre-allocated buffer pool is dropping low, schedule to
1312 * refill it */
1313 if (rxq->free_count <= RX_LOW_WATERMARK)
1314 queue_work(priv->workqueue, &priv->rx_replenish);
1315
1316
6440adb5
CB
1317 /* If we've added more space for the firmware to place data, tell it.
1318 * Increment device's write pointer in multiples of 8. */
b481de9c
ZY
1319 if ((write != (rxq->write & ~0x7))
1320 || (abs(rxq->write - rxq->read) > 7)) {
1321 spin_lock_irqsave(&rxq->lock, flags);
1322 rxq->need_update = 1;
1323 spin_unlock_irqrestore(&rxq->lock, flags);
141c43a3 1324 rc = iwl_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY
1325 if (rc)
1326 return rc;
1327 }
1328
1329 return 0;
1330}
1331
1332/**
bb8c093b 1333 * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
b481de9c
ZY
1334 *
1335 * When moving to rx_free an SKB is allocated for the slot.
1336 *
bb8c093b 1337 * Also restock the Rx queue via iwl3945_rx_queue_restock.
01ebd063 1338 * This is called as a scheduled work item (except for during initialization)
b481de9c 1339 */
4a8a4322 1340static void iwl3945_rx_allocate(struct iwl_priv *priv)
b481de9c 1341{
cc2f362c 1342 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c 1343 struct list_head *element;
6100b588 1344 struct iwl_rx_mem_buffer *rxb;
b481de9c 1345 unsigned long flags;
72240498
AK
1346
1347 while (1) {
1348 spin_lock_irqsave(&rxq->lock, flags);
1349
1350 if (list_empty(&rxq->rx_used)) {
1351 spin_unlock_irqrestore(&rxq->lock, flags);
1352 return;
1353 }
1354
b481de9c 1355 element = rxq->rx_used.next;
6100b588 1356 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
72240498
AK
1357 list_del(element);
1358 spin_unlock_irqrestore(&rxq->lock, flags);
6440adb5
CB
1359
1360 /* Alloc a new receive buffer */
b481de9c 1361 rxb->skb =
1e33dc64 1362 alloc_skb(priv->hw_params.rx_buf_size,
72240498 1363 GFP_KERNEL);
b481de9c
ZY
1364 if (!rxb->skb) {
1365 if (net_ratelimit())
978785a3 1366 IWL_CRIT(priv, ": Can not allocate SKB buffers\n");
b481de9c
ZY
1367 /* We don't reschedule replenish work here -- we will
1368 * call the restock method and if it still needs
1369 * more buffers it will schedule replenish */
1370 break;
1371 }
12342c47
ZY
1372
1373 /* If radiotap head is required, reserve some headroom here.
1374 * The physical head count is a variable rx_stats->phy_count.
1375 * We reserve 4 bytes here. Plus these extra bytes, the
1376 * headroom of the physical head should be enough for the
1377 * radiotap head that iwl3945 supported. See iwl3945_rt.
1378 */
1379 skb_reserve(rxb->skb, 4);
1380
6440adb5 1381 /* Get physical address of RB/SKB */
1e33dc64
WT
1382 rxb->real_dma_addr = pci_map_single(priv->pci_dev,
1383 rxb->skb->data,
1384 priv->hw_params.rx_buf_size,
1385 PCI_DMA_FROMDEVICE);
72240498
AK
1386
1387 spin_lock_irqsave(&rxq->lock, flags);
b481de9c 1388 list_add_tail(&rxb->list, &rxq->rx_free);
72240498 1389 priv->alloc_rxb_skb++;
b481de9c 1390 rxq->free_count++;
72240498 1391 spin_unlock_irqrestore(&rxq->lock, flags);
b481de9c 1392 }
5c0eef96
MA
1393}
1394
df833b1d
RC
1395void iwl3945_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
1396{
1397 unsigned long flags;
1398 int i;
1399 spin_lock_irqsave(&rxq->lock, flags);
1400 INIT_LIST_HEAD(&rxq->rx_free);
1401 INIT_LIST_HEAD(&rxq->rx_used);
1402 /* Fill the rx_used queue with _all_ of the Rx buffers */
1403 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
1404 /* In the reset function, these buffers may have been allocated
1405 * to an SKB, so we need to unmap and free potential storage */
1406 if (rxq->pool[i].skb != NULL) {
1407 pci_unmap_single(priv->pci_dev,
1408 rxq->pool[i].real_dma_addr,
1409 priv->hw_params.rx_buf_size,
1410 PCI_DMA_FROMDEVICE);
1411 priv->alloc_rxb_skb--;
1412 dev_kfree_skb(rxq->pool[i].skb);
1413 rxq->pool[i].skb = NULL;
1414 }
1415 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
1416 }
1417
1418 /* Set us so that we have processed and used all buffers, but have
1419 * not restocked the Rx queue with fresh buffers */
1420 rxq->read = rxq->write = 0;
1421 rxq->free_count = 0;
1422 spin_unlock_irqrestore(&rxq->lock, flags);
1423}
df833b1d 1424
5c0eef96
MA
1425void iwl3945_rx_replenish(void *data)
1426{
4a8a4322 1427 struct iwl_priv *priv = data;
5c0eef96
MA
1428 unsigned long flags;
1429
1430 iwl3945_rx_allocate(priv);
b481de9c
ZY
1431
1432 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 1433 iwl3945_rx_queue_restock(priv);
b481de9c
ZY
1434 spin_unlock_irqrestore(&priv->lock, flags);
1435}
1436
df833b1d
RC
1437/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
1438 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
1439 * This free routine walks the list of POOL entries and if SKB is set to
1440 * non NULL it is unmapped and freed
1441 */
1442static void iwl3945_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
1443{
1444 int i;
1445 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
1446 if (rxq->pool[i].skb != NULL) {
1447 pci_unmap_single(priv->pci_dev,
1448 rxq->pool[i].real_dma_addr,
1449 priv->hw_params.rx_buf_size,
1450 PCI_DMA_FROMDEVICE);
1451 dev_kfree_skb(rxq->pool[i].skb);
1452 }
1453 }
1454
1455 pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
1456 rxq->dma_addr);
1457 pci_free_consistent(priv->pci_dev, sizeof(struct iwl_rb_status),
1458 rxq->rb_stts, rxq->rb_stts_dma);
1459 rxq->bd = NULL;
1460 rxq->rb_stts = NULL;
1461}
df833b1d
RC
1462
1463
b481de9c
ZY
1464/* Convert linear signal-to-noise ratio into dB */
1465static u8 ratio2dB[100] = {
1466/* 0 1 2 3 4 5 6 7 8 9 */
1467 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
1468 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
1469 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
1470 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
1471 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
1472 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
1473 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
1474 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
1475 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
1476 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
1477};
1478
1479/* Calculates a relative dB value from a ratio of linear
1480 * (i.e. not dB) signal levels.
1481 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
bb8c093b 1482int iwl3945_calc_db_from_ratio(int sig_ratio)
b481de9c 1483{
221c80cf
AB
1484 /* 1000:1 or higher just report as 60 dB */
1485 if (sig_ratio >= 1000)
b481de9c
ZY
1486 return 60;
1487
221c80cf 1488 /* 100:1 or higher, divide by 10 and use table,
b481de9c 1489 * add 20 dB to make up for divide by 10 */
221c80cf 1490 if (sig_ratio >= 100)
3ac7f146 1491 return 20 + (int)ratio2dB[sig_ratio/10];
b481de9c
ZY
1492
1493 /* We shouldn't see this */
1494 if (sig_ratio < 1)
1495 return 0;
1496
1497 /* Use table for ratios 1:1 - 99:1 */
1498 return (int)ratio2dB[sig_ratio];
1499}
1500
1501#define PERFECT_RSSI (-20) /* dBm */
1502#define WORST_RSSI (-95) /* dBm */
1503#define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
1504
1505/* Calculate an indication of rx signal quality (a percentage, not dBm!).
1506 * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
1507 * about formulas used below. */
bb8c093b 1508int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
b481de9c
ZY
1509{
1510 int sig_qual;
1511 int degradation = PERFECT_RSSI - rssi_dbm;
1512
1513 /* If we get a noise measurement, use signal-to-noise ratio (SNR)
1514 * as indicator; formula is (signal dbm - noise dbm).
1515 * SNR at or above 40 is a great signal (100%).
1516 * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
1517 * Weakest usable signal is usually 10 - 15 dB SNR. */
1518 if (noise_dbm) {
1519 if (rssi_dbm - noise_dbm >= 40)
1520 return 100;
1521 else if (rssi_dbm < noise_dbm)
1522 return 0;
1523 sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
1524
1525 /* Else use just the signal level.
1526 * This formula is a least squares fit of data points collected and
1527 * compared with a reference system that had a percentage (%) display
1528 * for signal quality. */
1529 } else
1530 sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
1531 (15 * RSSI_RANGE + 62 * degradation)) /
1532 (RSSI_RANGE * RSSI_RANGE);
1533
1534 if (sig_qual > 100)
1535 sig_qual = 100;
1536 else if (sig_qual < 1)
1537 sig_qual = 0;
1538
1539 return sig_qual;
1540}
1541
1542/**
9fbab516 1543 * iwl3945_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
1544 *
1545 * Uses the priv->rx_handlers callback function array to invoke
1546 * the appropriate handlers, including command responses,
1547 * frame-received notifications, and other notifications.
1548 */
4a8a4322 1549static void iwl3945_rx_handle(struct iwl_priv *priv)
b481de9c 1550{
6100b588 1551 struct iwl_rx_mem_buffer *rxb;
3d24a9f7 1552 struct iwl_rx_packet *pkt;
cc2f362c 1553 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
1554 u32 r, i;
1555 int reclaim;
1556 unsigned long flags;
5c0eef96 1557 u8 fill_rx = 0;
d68ab680 1558 u32 count = 8;
b481de9c 1559
6440adb5
CB
1560 /* uCode's read index (stored in shared DRAM) indicates the last Rx
1561 * buffer that the driver may process (last buffer filled by ucode). */
8cd812bc 1562 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY
1563 i = rxq->read;
1564
37d68317 1565 if (iwl_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
5c0eef96 1566 fill_rx = 1;
b481de9c
ZY
1567 /* Rx interrupt, but nothing sent from uCode */
1568 if (i == r)
e1623446 1569 IWL_DEBUG(priv, IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
b481de9c
ZY
1570
1571 while (i != r) {
1572 rxb = rxq->queue[i];
1573
9fbab516 1574 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
1575 * then a bug has been introduced in the queue refilling
1576 * routines -- catch it here */
1577 BUG_ON(rxb == NULL);
1578
1579 rxq->queue[i] = NULL;
1580
df833b1d
RC
1581 pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
1582 priv->hw_params.rx_buf_size,
1583 PCI_DMA_FROMDEVICE);
3d24a9f7 1584 pkt = (struct iwl_rx_packet *)rxb->skb->data;
b481de9c
ZY
1585
1586 /* Reclaim a command buffer only if this packet is a response
1587 * to a (driver-originated) command.
1588 * If the packet (e.g. Rx frame) originated from uCode,
1589 * there is no command buffer to reclaim.
1590 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1591 * but apparently a few don't get set; catch them here. */
1592 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
1593 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
1594 (pkt->hdr.cmd != REPLY_TX);
1595
1596 /* Based on type of command response or notification,
1597 * handle those that need handling via function in
bb8c093b 1598 * rx_handlers table. See iwl3945_setup_rx_handlers() */
b481de9c 1599 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 1600 IWL_DEBUG(priv, IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR,
b481de9c
ZY
1601 "r = %d, i = %d, %s, 0x%02x\n", r, i,
1602 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
1603 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
86ddbf62 1604 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
b481de9c
ZY
1605 } else {
1606 /* No handling needed */
e1623446 1607 IWL_DEBUG(priv, IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR,
b481de9c
ZY
1608 "r %d i %d No handler needed for %s, 0x%02x\n",
1609 r, i, get_cmd_string(pkt->hdr.cmd),
1610 pkt->hdr.cmd);
1611 }
1612
1613 if (reclaim) {
9fbab516 1614 /* Invoke any callbacks, transfer the skb to caller, and
518099a8 1615 * fire off the (possibly) blocking iwl_send_cmd()
b481de9c
ZY
1616 * as we reclaim the driver command queue */
1617 if (rxb && rxb->skb)
732587ab 1618 iwl_tx_cmd_complete(priv, rxb);
b481de9c 1619 else
39aadf8c 1620 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY
1621 }
1622
1623 /* For now we just don't re-use anything. We can tweak this
1624 * later to try and re-use notification packets and SKBs that
1625 * fail to Rx correctly */
1626 if (rxb->skb != NULL) {
1627 priv->alloc_rxb_skb--;
1628 dev_kfree_skb_any(rxb->skb);
1629 rxb->skb = NULL;
1630 }
1631
b481de9c
ZY
1632 spin_lock_irqsave(&rxq->lock, flags);
1633 list_add_tail(&rxb->list, &priv->rxq.rx_used);
1634 spin_unlock_irqrestore(&rxq->lock, flags);
1635 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
1636 /* If there are a lot of unused frames,
1637 * restock the Rx queue so ucode won't assert. */
1638 if (fill_rx) {
1639 count++;
1640 if (count >= 8) {
1641 priv->rxq.read = i;
72240498 1642 iwl3945_rx_queue_restock(priv);
5c0eef96
MA
1643 count = 0;
1644 }
1645 }
b481de9c
ZY
1646 }
1647
1648 /* Backtrack one entry */
1649 priv->rxq.read = i;
bb8c093b 1650 iwl3945_rx_queue_restock(priv);
b481de9c
ZY
1651}
1652
0359facc 1653/* call this function to flush any scheduled tasklet */
4a8a4322 1654static inline void iwl_synchronize_irq(struct iwl_priv *priv)
0359facc 1655{
a96a27f9 1656 /* wait to make sure we flush pending tasklet*/
0359facc
MA
1657 synchronize_irq(priv->pci_dev->irq);
1658 tasklet_kill(&priv->irq_tasklet);
1659}
1660
b481de9c
ZY
1661static const char *desc_lookup(int i)
1662{
1663 switch (i) {
1664 case 1:
1665 return "FAIL";
1666 case 2:
1667 return "BAD_PARAM";
1668 case 3:
1669 return "BAD_CHECKSUM";
1670 case 4:
1671 return "NMI_INTERRUPT";
1672 case 5:
1673 return "SYSASSERT";
1674 case 6:
1675 return "FATAL_ERROR";
1676 }
1677
1678 return "UNKNOWN";
1679}
1680
1681#define ERROR_START_OFFSET (1 * sizeof(u32))
1682#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1683
4a8a4322 1684static void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
b481de9c
ZY
1685{
1686 u32 i;
1687 u32 desc, time, count, base, data1;
1688 u32 blink1, blink2, ilink1, ilink2;
1689 int rc;
1690
1691 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1692
bb8c093b 1693 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 1694 IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
b481de9c
ZY
1695 return;
1696 }
1697
5d49f498 1698 rc = iwl_grab_nic_access(priv);
b481de9c 1699 if (rc) {
39aadf8c 1700 IWL_WARN(priv, "Can not read from adapter at this time.\n");
b481de9c
ZY
1701 return;
1702 }
1703
5d49f498 1704 count = iwl_read_targ_mem(priv, base);
b481de9c
ZY
1705
1706 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
15b1687c
WT
1707 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1708 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1709 priv->status, count);
b481de9c
ZY
1710 }
1711
15b1687c 1712 IWL_ERR(priv, "Desc Time asrtPC blink2 "
b481de9c
ZY
1713 "ilink1 nmiPC Line\n");
1714 for (i = ERROR_START_OFFSET;
1715 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
1716 i += ERROR_ELEM_SIZE) {
5d49f498 1717 desc = iwl_read_targ_mem(priv, base + i);
b481de9c 1718 time =
5d49f498 1719 iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32));
b481de9c 1720 blink1 =
5d49f498 1721 iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32));
b481de9c 1722 blink2 =
5d49f498 1723 iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32));
b481de9c 1724 ilink1 =
5d49f498 1725 iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32));
b481de9c 1726 ilink2 =
5d49f498 1727 iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32));
b481de9c 1728 data1 =
5d49f498 1729 iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32));
b481de9c 1730
15b1687c
WT
1731 IWL_ERR(priv,
1732 "%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
1733 desc_lookup(desc), desc, time, blink1, blink2,
1734 ilink1, ilink2, data1);
b481de9c
ZY
1735 }
1736
5d49f498 1737 iwl_release_nic_access(priv);
b481de9c
ZY
1738
1739}
1740
f58177b9 1741#define EVENT_START_OFFSET (6 * sizeof(u32))
b481de9c
ZY
1742
1743/**
bb8c093b 1744 * iwl3945_print_event_log - Dump error event log to syslog
b481de9c 1745 *
5d49f498 1746 * NOTE: Must be called with iwl_grab_nic_access() already obtained!
b481de9c 1747 */
4a8a4322 1748static void iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
b481de9c
ZY
1749 u32 num_events, u32 mode)
1750{
1751 u32 i;
1752 u32 base; /* SRAM byte address of event log header */
1753 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1754 u32 ptr; /* SRAM byte address of log data */
1755 u32 ev, time, data; /* event log data */
1756
1757 if (num_events == 0)
1758 return;
1759
1760 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1761
1762 if (mode == 0)
1763 event_size = 2 * sizeof(u32);
1764 else
1765 event_size = 3 * sizeof(u32);
1766
1767 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1768
1769 /* "time" is actually "data" for mode 0 (no timestamp).
1770 * place event id # at far right for easier visual parsing. */
1771 for (i = 0; i < num_events; i++) {
5d49f498 1772 ev = iwl_read_targ_mem(priv, ptr);
b481de9c 1773 ptr += sizeof(u32);
5d49f498 1774 time = iwl_read_targ_mem(priv, ptr);
b481de9c 1775 ptr += sizeof(u32);
15b1687c
WT
1776 if (mode == 0) {
1777 /* data, ev */
1778 IWL_ERR(priv, "0x%08x\t%04u\n", time, ev);
1779 } else {
5d49f498 1780 data = iwl_read_targ_mem(priv, ptr);
b481de9c 1781 ptr += sizeof(u32);
15b1687c 1782 IWL_ERR(priv, "%010u\t0x%08x\t%04u\n", time, data, ev);
b481de9c
ZY
1783 }
1784 }
1785}
1786
4a8a4322 1787static void iwl3945_dump_nic_event_log(struct iwl_priv *priv)
b481de9c
ZY
1788{
1789 int rc;
1790 u32 base; /* SRAM byte address of event log header */
1791 u32 capacity; /* event log capacity in # entries */
1792 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1793 u32 num_wraps; /* # times uCode wrapped to top of log */
1794 u32 next_entry; /* index of next entry to be written by uCode */
1795 u32 size; /* # entries that we'll print */
1796
1797 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 1798 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 1799 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
b481de9c
ZY
1800 return;
1801 }
1802
5d49f498 1803 rc = iwl_grab_nic_access(priv);
b481de9c 1804 if (rc) {
39aadf8c 1805 IWL_WARN(priv, "Can not read from adapter at this time.\n");
b481de9c
ZY
1806 return;
1807 }
1808
1809 /* event log header */
5d49f498
AK
1810 capacity = iwl_read_targ_mem(priv, base);
1811 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1812 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1813 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
b481de9c
ZY
1814
1815 size = num_wraps ? capacity : next_entry;
1816
1817 /* bail out if nothing in log */
1818 if (size == 0) {
15b1687c 1819 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
5d49f498 1820 iwl_release_nic_access(priv);
b481de9c
ZY
1821 return;
1822 }
1823
15b1687c 1824 IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
b481de9c
ZY
1825 size, num_wraps);
1826
1827 /* if uCode has wrapped back to top of log, start at the oldest entry,
1828 * i.e the next one that uCode would fill. */
1829 if (num_wraps)
bb8c093b 1830 iwl3945_print_event_log(priv, next_entry,
b481de9c
ZY
1831 capacity - next_entry, mode);
1832
1833 /* (then/else) start at top of log */
bb8c093b 1834 iwl3945_print_event_log(priv, 0, next_entry, mode);
b481de9c 1835
5d49f498 1836 iwl_release_nic_access(priv);
b481de9c
ZY
1837}
1838
4a8a4322 1839static void iwl3945_irq_tasklet(struct iwl_priv *priv)
b481de9c
ZY
1840{
1841 u32 inta, handled = 0;
1842 u32 inta_fh;
1843 unsigned long flags;
d08853a3 1844#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
1845 u32 inta_mask;
1846#endif
1847
1848 spin_lock_irqsave(&priv->lock, flags);
1849
1850 /* Ack/clear/reset pending uCode interrupts.
1851 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1852 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
5d49f498
AK
1853 inta = iwl_read32(priv, CSR_INT);
1854 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY
1855
1856 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1857 * Any new interrupts that happen after this, either while we're
1858 * in this tasklet, or later, will show up in next ISR/tasklet. */
5d49f498
AK
1859 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1860 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 1861
d08853a3 1862#ifdef CONFIG_IWLWIFI_DEBUG
40b8ec0b 1863 if (priv->debug_level & IWL_DL_ISR) {
9fbab516 1864 /* just for debug */
5d49f498 1865 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 1866 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY
1867 inta, inta_mask, inta_fh);
1868 }
1869#endif
1870
1871 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1872 * atomic, make sure that inta covers all the interrupts that
1873 * we've discovered, even if FH interrupt came in just after
1874 * reading CSR_INT. */
6f83eaa1 1875 if (inta_fh & CSR39_FH_INT_RX_MASK)
b481de9c 1876 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 1877 if (inta_fh & CSR39_FH_INT_TX_MASK)
b481de9c
ZY
1878 inta |= CSR_INT_BIT_FH_TX;
1879
1880 /* Now service all interrupt bits discovered above. */
1881 if (inta & CSR_INT_BIT_HW_ERR) {
15b1687c 1882 IWL_ERR(priv, "Microcode HW error detected. Restarting.\n");
b481de9c
ZY
1883
1884 /* Tell the device to stop sending interrupts */
ed3b932e 1885 iwl_disable_interrupts(priv);
b481de9c 1886
86ddbf62 1887 priv->isr_stats.hw++;
8ccde88a 1888 iwl_irq_handle_error(priv);
b481de9c
ZY
1889
1890 handled |= CSR_INT_BIT_HW_ERR;
1891
1892 spin_unlock_irqrestore(&priv->lock, flags);
1893
1894 return;
1895 }
1896
d08853a3 1897#ifdef CONFIG_IWLWIFI_DEBUG
40b8ec0b 1898 if (priv->debug_level & (IWL_DL_ISR)) {
b481de9c 1899 /* NIC fires this, but we don't use it, redundant with WAKEUP */
86ddbf62 1900 if (inta & CSR_INT_BIT_SCD) {
e1623446 1901 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1902 "the frame/frames.\n");
86ddbf62
AK
1903 priv->isr_stats.sch++;
1904 }
b481de9c
ZY
1905
1906 /* Alive notification via Rx interrupt will do the real work */
86ddbf62 1907 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 1908 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
86ddbf62
AK
1909 priv->isr_stats.alive++;
1910 }
b481de9c
ZY
1911 }
1912#endif
1913 /* Safely ignore these bits for debug checks below */
25c03d8e 1914 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1915
b481de9c
ZY
1916 /* Error detected by uCode */
1917 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT
1918 IWL_ERR(priv, "Microcode SW error detected. "
1919 "Restarting 0x%X.\n", inta);
86ddbf62
AK
1920 priv->isr_stats.sw++;
1921 priv->isr_stats.sw_err = inta;
8ccde88a 1922 iwl_irq_handle_error(priv);
b481de9c
ZY
1923 handled |= CSR_INT_BIT_SW_ERR;
1924 }
1925
1926 /* uCode wakes up after power-down sleep */
1927 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1928 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
141c43a3 1929 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
4f3602c8
SO
1930 iwl_txq_update_write_ptr(priv, &priv->txq[0]);
1931 iwl_txq_update_write_ptr(priv, &priv->txq[1]);
1932 iwl_txq_update_write_ptr(priv, &priv->txq[2]);
1933 iwl_txq_update_write_ptr(priv, &priv->txq[3]);
1934 iwl_txq_update_write_ptr(priv, &priv->txq[4]);
1935 iwl_txq_update_write_ptr(priv, &priv->txq[5]);
b481de9c 1936
86ddbf62 1937 priv->isr_stats.wakeup++;
b481de9c
ZY
1938 handled |= CSR_INT_BIT_WAKEUP;
1939 }
1940
1941 /* All uCode command responses, including Tx command responses,
1942 * Rx "responses" (frame-received notification), and other
1943 * notifications from uCode come through here*/
1944 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
bb8c093b 1945 iwl3945_rx_handle(priv);
86ddbf62 1946 priv->isr_stats.rx++;
b481de9c
ZY
1947 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1948 }
1949
1950 if (inta & CSR_INT_BIT_FH_TX) {
e1623446 1951 IWL_DEBUG_ISR(priv, "Tx interrupt\n");
86ddbf62 1952 priv->isr_stats.tx++;
b481de9c 1953
5d49f498
AK
1954 iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
1955 if (!iwl_grab_nic_access(priv)) {
1956 iwl_write_direct32(priv, FH39_TCSR_CREDIT
bddadf86 1957 (FH39_SRVC_CHNL), 0x0);
5d49f498 1958 iwl_release_nic_access(priv);
b481de9c
ZY
1959 }
1960 handled |= CSR_INT_BIT_FH_TX;
1961 }
1962
86ddbf62 1963 if (inta & ~handled) {
15b1687c 1964 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
86ddbf62
AK
1965 priv->isr_stats.unhandled++;
1966 }
b481de9c
ZY
1967
1968 if (inta & ~CSR_INI_SET_MASK) {
39aadf8c 1969 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
b481de9c 1970 inta & ~CSR_INI_SET_MASK);
39aadf8c 1971 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY
1972 }
1973
1974 /* Re-enable all interrupts */
0359facc
MA
1975 /* only Re-enable if disabled by irq */
1976 if (test_bit(STATUS_INT_ENABLED, &priv->status))
ed3b932e 1977 iwl_enable_interrupts(priv);
b481de9c 1978
d08853a3 1979#ifdef CONFIG_IWLWIFI_DEBUG
40b8ec0b 1980 if (priv->debug_level & (IWL_DL_ISR)) {
5d49f498
AK
1981 inta = iwl_read32(priv, CSR_INT);
1982 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1983 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1984 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY
1985 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1986 }
1987#endif
1988 spin_unlock_irqrestore(&priv->lock, flags);
1989}
1990
4a8a4322 1991static int iwl3945_get_channels_for_scan(struct iwl_priv *priv,
8318d78a 1992 enum ieee80211_band band,
f9340520 1993 u8 is_active, u8 n_probes,
bb8c093b 1994 struct iwl3945_scan_channel *scan_ch)
b481de9c
ZY
1995{
1996 const struct ieee80211_channel *channels = NULL;
8318d78a 1997 const struct ieee80211_supported_band *sband;
d20b3c65 1998 const struct iwl_channel_info *ch_info;
b481de9c
ZY
1999 u16 passive_dwell = 0;
2000 u16 active_dwell = 0;
2001 int added, i;
2002
cbba18c6 2003 sband = iwl_get_hw_mode(priv, band);
8318d78a 2004 if (!sband)
b481de9c
ZY
2005 return 0;
2006
8318d78a 2007 channels = sband->channels;
b481de9c 2008
77fecfb8
SO
2009 active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
2010 passive_dwell = iwl_get_passive_dwell_time(priv, band);
b481de9c 2011
8f4807a1
AK
2012 if (passive_dwell <= active_dwell)
2013 passive_dwell = active_dwell + 1;
2014
8318d78a 2015 for (i = 0, added = 0; i < sband->n_channels; i++) {
182e2e66
JB
2016 if (channels[i].flags & IEEE80211_CHAN_DISABLED)
2017 continue;
2018
8318d78a 2019 scan_ch->channel = channels[i].hw_value;
b481de9c 2020
e6148917 2021 ch_info = iwl_get_channel_info(priv, band, scan_ch->channel);
b481de9c 2022 if (!is_channel_valid(ch_info)) {
e1623446 2023 IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
b481de9c
ZY
2024 scan_ch->channel);
2025 continue;
2026 }
2027
011a0330
AK
2028 scan_ch->active_dwell = cpu_to_le16(active_dwell);
2029 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
2030 /* If passive , set up for auto-switch
2031 * and use long active_dwell time.
2032 */
b481de9c 2033 if (!is_active || is_channel_passive(ch_info) ||
011a0330 2034 (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
b481de9c 2035 scan_ch->type = 0; /* passive */
011a0330
AK
2036 if (IWL_UCODE_API(priv->ucode_ver) == 1)
2037 scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
2038 } else {
b481de9c 2039 scan_ch->type = 1; /* active */
011a0330 2040 }
b481de9c 2041
011a0330
AK
2042 /* Set direct probe bits. These may be used both for active
2043 * scan channels (probes gets sent right away),
2044 * or for passive channels (probes get se sent only after
2045 * hearing clear Rx packet).*/
2046 if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
2047 if (n_probes)
0d21044e 2048 scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes);
011a0330
AK
2049 } else {
2050 /* uCode v1 does not allow setting direct probe bits on
2051 * passive channel. */
2052 if ((scan_ch->type & 1) && n_probes)
0d21044e 2053 scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes);
011a0330 2054 }
b481de9c 2055
9fbab516 2056 /* Set txpower levels to defaults */
b481de9c
ZY
2057 scan_ch->tpc.dsp_atten = 110;
2058 /* scan_pwr_info->tpc.dsp_atten; */
2059
2060 /*scan_pwr_info->tpc.tx_gain; */
8318d78a 2061 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY
2062 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
2063 else {
2064 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
2065 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
9fbab516 2066 * power level:
8a1b0245 2067 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
b481de9c
ZY
2068 */
2069 }
2070
e1623446 2071 IWL_DEBUG_SCAN(priv, "Scanning %d [%s %d]\n",
b481de9c
ZY
2072 scan_ch->channel,
2073 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
2074 (scan_ch->type & 1) ?
2075 active_dwell : passive_dwell);
2076
2077 scan_ch++;
2078 added++;
2079 }
2080
e1623446 2081 IWL_DEBUG_SCAN(priv, "total channels to scan %d \n", added);
b481de9c
ZY
2082 return added;
2083}
2084
4a8a4322 2085static void iwl3945_init_hw_rates(struct iwl_priv *priv,
b481de9c
ZY
2086 struct ieee80211_rate *rates)
2087{
2088 int i;
2089
2090 for (i = 0; i < IWL_RATE_COUNT; i++) {
8318d78a
JB
2091 rates[i].bitrate = iwl3945_rates[i].ieee * 5;
2092 rates[i].hw_value = i; /* Rate scaling will work on indexes */
2093 rates[i].hw_value_short = i;
2094 rates[i].flags = 0;
d9829a67 2095 if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
b481de9c 2096 /*
8318d78a 2097 * If CCK != 1M then set short preamble rate flag.
b481de9c 2098 */
bb8c093b 2099 rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
8318d78a 2100 0 : IEEE80211_RATE_SHORT_PREAMBLE;
b481de9c 2101 }
b481de9c
ZY
2102 }
2103}
2104
b481de9c
ZY
2105/******************************************************************************
2106 *
2107 * uCode download functions
2108 *
2109 ******************************************************************************/
2110
4a8a4322 2111static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 2112{
98c92211
TW
2113 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
2114 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
2115 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
2116 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
2117 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
2118 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY
2119}
2120
2121/**
bb8c093b 2122 * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
b481de9c
ZY
2123 * looking at all data.
2124 */
4a8a4322 2125static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len)
b481de9c
ZY
2126{
2127 u32 val;
2128 u32 save_len = len;
2129 int rc = 0;
2130 u32 errcnt;
2131
e1623446 2132 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b481de9c 2133
5d49f498 2134 rc = iwl_grab_nic_access(priv);
b481de9c
ZY
2135 if (rc)
2136 return rc;
2137
5d49f498 2138 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 2139 IWL39_RTC_INST_LOWER_BOUND);
b481de9c
ZY
2140
2141 errcnt = 0;
2142 for (; len > 0; len -= sizeof(u32), image++) {
2143 /* read data comes through single port, auto-incr addr */
2144 /* NOTE: Use the debugless read so we don't flood kernel log
2145 * if IWL_DL_IO is set */
5d49f498 2146 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c 2147 if (val != le32_to_cpu(*image)) {
15b1687c 2148 IWL_ERR(priv, "uCode INST section is invalid at "
b481de9c
ZY
2149 "offset 0x%x, is 0x%x, s/b 0x%x\n",
2150 save_len - len, val, le32_to_cpu(*image));
2151 rc = -EIO;
2152 errcnt++;
2153 if (errcnt >= 20)
2154 break;
2155 }
2156 }
2157
5d49f498 2158 iwl_release_nic_access(priv);
b481de9c
ZY
2159
2160 if (!errcnt)
e1623446
TW
2161 IWL_DEBUG_INFO(priv,
2162 "ucode image in INSTRUCTION memory is good\n");
b481de9c
ZY
2163
2164 return rc;
2165}
2166
2167
2168/**
bb8c093b 2169 * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
b481de9c
ZY
2170 * using sample data 100 bytes apart. If these sample points are good,
2171 * it's a pretty good bet that everything between them is good, too.
2172 */
4a8a4322 2173static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
b481de9c
ZY
2174{
2175 u32 val;
2176 int rc = 0;
2177 u32 errcnt = 0;
2178 u32 i;
2179
e1623446 2180 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b481de9c 2181
5d49f498 2182 rc = iwl_grab_nic_access(priv);
b481de9c
ZY
2183 if (rc)
2184 return rc;
2185
2186 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
2187 /* read data comes through single port, auto-incr addr */
2188 /* NOTE: Use the debugless read so we don't flood kernel log
2189 * if IWL_DL_IO is set */
5d49f498 2190 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 2191 i + IWL39_RTC_INST_LOWER_BOUND);
5d49f498 2192 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY
2193 if (val != le32_to_cpu(*image)) {
2194#if 0 /* Enable this if you want to see details */
15b1687c 2195 IWL_ERR(priv, "uCode INST section is invalid at "
b481de9c
ZY
2196 "offset 0x%x, is 0x%x, s/b 0x%x\n",
2197 i, val, *image);
2198#endif
2199 rc = -EIO;
2200 errcnt++;
2201 if (errcnt >= 3)
2202 break;
2203 }
2204 }
2205
5d49f498 2206 iwl_release_nic_access(priv);
b481de9c
ZY
2207
2208 return rc;
2209}
2210
2211
2212/**
bb8c093b 2213 * iwl3945_verify_ucode - determine which instruction image is in SRAM,
b481de9c
ZY
2214 * and verify its contents
2215 */
4a8a4322 2216static int iwl3945_verify_ucode(struct iwl_priv *priv)
b481de9c
ZY
2217{
2218 __le32 *image;
2219 u32 len;
2220 int rc = 0;
2221
2222 /* Try bootstrap */
2223 image = (__le32 *)priv->ucode_boot.v_addr;
2224 len = priv->ucode_boot.len;
bb8c093b 2225 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c 2226 if (rc == 0) {
e1623446 2227 IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
b481de9c
ZY
2228 return 0;
2229 }
2230
2231 /* Try initialize */
2232 image = (__le32 *)priv->ucode_init.v_addr;
2233 len = priv->ucode_init.len;
bb8c093b 2234 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c 2235 if (rc == 0) {
e1623446 2236 IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
b481de9c
ZY
2237 return 0;
2238 }
2239
2240 /* Try runtime/protocol */
2241 image = (__le32 *)priv->ucode_code.v_addr;
2242 len = priv->ucode_code.len;
bb8c093b 2243 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c 2244 if (rc == 0) {
e1623446 2245 IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
b481de9c
ZY
2246 return 0;
2247 }
2248
15b1687c 2249 IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
b481de9c 2250
9fbab516
BC
2251 /* Since nothing seems to match, show first several data entries in
2252 * instruction SRAM, so maybe visual inspection will give a clue.
2253 * Selection of bootstrap image (vs. other images) is arbitrary. */
b481de9c
ZY
2254 image = (__le32 *)priv->ucode_boot.v_addr;
2255 len = priv->ucode_boot.len;
bb8c093b 2256 rc = iwl3945_verify_inst_full(priv, image, len);
b481de9c
ZY
2257
2258 return rc;
2259}
2260
4a8a4322 2261static void iwl3945_nic_start(struct iwl_priv *priv)
b481de9c
ZY
2262{
2263 /* Remove all resets to allow NIC to operate */
5d49f498 2264 iwl_write32(priv, CSR_RESET, 0);
b481de9c
ZY
2265}
2266
2267/**
bb8c093b 2268 * iwl3945_read_ucode - Read uCode images from disk file.
b481de9c
ZY
2269 *
2270 * Copy into buffers for card to fetch via bus-mastering
2271 */
4a8a4322 2272static int iwl3945_read_ucode(struct iwl_priv *priv)
b481de9c 2273{
a78fe754 2274 struct iwl_ucode *ucode;
a0987a8d 2275 int ret = -EINVAL, index;
b481de9c
ZY
2276 const struct firmware *ucode_raw;
2277 /* firmware file name contains uCode/driver compatibility version */
a0987a8d
RC
2278 const char *name_pre = priv->cfg->fw_name_pre;
2279 const unsigned int api_max = priv->cfg->ucode_api_max;
2280 const unsigned int api_min = priv->cfg->ucode_api_min;
2281 char buf[25];
b481de9c
ZY
2282 u8 *src;
2283 size_t len;
a0987a8d 2284 u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
b481de9c
ZY
2285
2286 /* Ask kernel firmware_class module to get the boot firmware off disk.
2287 * request_firmware() is synchronous, file is in memory on return. */
a0987a8d
RC
2288 for (index = api_max; index >= api_min; index--) {
2289 sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
2290 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
2291 if (ret < 0) {
15b1687c 2292 IWL_ERR(priv, "%s firmware file req failed: %d\n",
a0987a8d
RC
2293 buf, ret);
2294 if (ret == -ENOENT)
2295 continue;
2296 else
2297 goto error;
2298 } else {
2299 if (index < api_max)
15b1687c
WT
2300 IWL_ERR(priv, "Loaded firmware %s, "
2301 "which is deprecated. "
2302 " Please use API v%u instead.\n",
a0987a8d 2303 buf, api_max);
e1623446
TW
2304 IWL_DEBUG_INFO(priv, "Got firmware '%s' file "
2305 "(%zd bytes) from disk\n",
a0987a8d
RC
2306 buf, ucode_raw->size);
2307 break;
2308 }
b481de9c
ZY
2309 }
2310
a0987a8d
RC
2311 if (ret < 0)
2312 goto error;
b481de9c
ZY
2313
2314 /* Make sure that we got at least our header! */
2315 if (ucode_raw->size < sizeof(*ucode)) {
15b1687c 2316 IWL_ERR(priv, "File size way too small!\n");
90e759d1 2317 ret = -EINVAL;
b481de9c
ZY
2318 goto err_release;
2319 }
2320
2321 /* Data from ucode file: header followed by uCode images */
2322 ucode = (void *)ucode_raw->data;
2323
c02b3acd 2324 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 2325 api_ver = IWL_UCODE_API(priv->ucode_ver);
b481de9c
ZY
2326 inst_size = le32_to_cpu(ucode->inst_size);
2327 data_size = le32_to_cpu(ucode->data_size);
2328 init_size = le32_to_cpu(ucode->init_size);
2329 init_data_size = le32_to_cpu(ucode->init_data_size);
2330 boot_size = le32_to_cpu(ucode->boot_size);
2331
a0987a8d
RC
2332 /* api_ver should match the api version forming part of the
2333 * firmware filename ... but we don't check for that and only rely
877d0310 2334 * on the API version read from firmware header from here on forward */
a0987a8d
RC
2335
2336 if (api_ver < api_min || api_ver > api_max) {
15b1687c 2337 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC
2338 "Driver supports v%u, firmware is v%u.\n",
2339 api_max, api_ver);
2340 priv->ucode_ver = 0;
2341 ret = -EINVAL;
2342 goto err_release;
2343 }
2344 if (api_ver != api_max)
15b1687c 2345 IWL_ERR(priv, "Firmware has old API version. Expected %u, "
a0987a8d
RC
2346 "got %u. New firmware can be obtained "
2347 "from http://www.intellinuxwireless.org.\n",
2348 api_max, api_ver);
2349
978785a3
TW
2350 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
2351 IWL_UCODE_MAJOR(priv->ucode_ver),
2352 IWL_UCODE_MINOR(priv->ucode_ver),
2353 IWL_UCODE_API(priv->ucode_ver),
2354 IWL_UCODE_SERIAL(priv->ucode_ver));
2355
e1623446 2356 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
a0987a8d 2357 priv->ucode_ver);
e1623446
TW
2358 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
2359 inst_size);
2360 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
2361 data_size);
2362 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
2363 init_size);
2364 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
2365 init_data_size);
2366 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
2367 boot_size);
b481de9c 2368
a0987a8d 2369
b481de9c
ZY
2370 /* Verify size of file vs. image size info in file's header */
2371 if (ucode_raw->size < sizeof(*ucode) +
2372 inst_size + data_size + init_size +
2373 init_data_size + boot_size) {
2374
e1623446
TW
2375 IWL_DEBUG_INFO(priv, "uCode file size %zd too small\n",
2376 ucode_raw->size);
90e759d1 2377 ret = -EINVAL;
b481de9c
ZY
2378 goto err_release;
2379 }
2380
2381 /* Verify that uCode images will fit in card's SRAM */
250bdd21 2382 if (inst_size > IWL39_MAX_INST_SIZE) {
e1623446 2383 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
90e759d1
TW
2384 inst_size);
2385 ret = -EINVAL;
b481de9c
ZY
2386 goto err_release;
2387 }
2388
250bdd21 2389 if (data_size > IWL39_MAX_DATA_SIZE) {
e1623446 2390 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
90e759d1
TW
2391 data_size);
2392 ret = -EINVAL;
b481de9c
ZY
2393 goto err_release;
2394 }
250bdd21 2395 if (init_size > IWL39_MAX_INST_SIZE) {
e1623446
TW
2396 IWL_DEBUG_INFO(priv,
2397 "uCode init instr len %d too large to fit in\n",
90e759d1
TW
2398 init_size);
2399 ret = -EINVAL;
b481de9c
ZY
2400 goto err_release;
2401 }
250bdd21 2402 if (init_data_size > IWL39_MAX_DATA_SIZE) {
e1623446
TW
2403 IWL_DEBUG_INFO(priv,
2404 "uCode init data len %d too large to fit in\n",
90e759d1
TW
2405 init_data_size);
2406 ret = -EINVAL;
b481de9c
ZY
2407 goto err_release;
2408 }
250bdd21 2409 if (boot_size > IWL39_MAX_BSM_SIZE) {
e1623446
TW
2410 IWL_DEBUG_INFO(priv,
2411 "uCode boot instr len %d too large to fit in\n",
90e759d1
TW
2412 boot_size);
2413 ret = -EINVAL;
b481de9c
ZY
2414 goto err_release;
2415 }
2416
2417 /* Allocate ucode buffers for card's bus-master loading ... */
2418
2419 /* Runtime instructions and 2 copies of data:
2420 * 1) unmodified from disk
2421 * 2) backup cache for save/restore during power-downs */
2422 priv->ucode_code.len = inst_size;
98c92211 2423 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY
2424
2425 priv->ucode_data.len = data_size;
98c92211 2426 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY
2427
2428 priv->ucode_data_backup.len = data_size;
98c92211 2429 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 2430
90e759d1
TW
2431 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2432 !priv->ucode_data_backup.v_addr)
2433 goto err_pci_alloc;
b481de9c
ZY
2434
2435 /* Initialization instructions and data */
90e759d1
TW
2436 if (init_size && init_data_size) {
2437 priv->ucode_init.len = init_size;
98c92211 2438 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW
2439
2440 priv->ucode_init_data.len = init_data_size;
98c92211 2441 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW
2442
2443 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2444 goto err_pci_alloc;
2445 }
b481de9c
ZY
2446
2447 /* Bootstrap (instructions only, no data) */
90e759d1
TW
2448 if (boot_size) {
2449 priv->ucode_boot.len = boot_size;
98c92211 2450 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 2451
90e759d1
TW
2452 if (!priv->ucode_boot.v_addr)
2453 goto err_pci_alloc;
2454 }
b481de9c
ZY
2455
2456 /* Copy images into buffers for card's bus-master reads ... */
2457
2458 /* Runtime instructions (first block of data in file) */
2459 src = &ucode->data[0];
2460 len = priv->ucode_code.len;
e1623446
TW
2461 IWL_DEBUG_INFO(priv,
2462 "Copying (but not loading) uCode instr len %zd\n", len);
b481de9c 2463 memcpy(priv->ucode_code.v_addr, src, len);
e1623446 2464 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY
2465 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2466
2467 /* Runtime data (2nd block)
bb8c093b 2468 * NOTE: Copy into backup buffer will be done in iwl3945_up() */
b481de9c
ZY
2469 src = &ucode->data[inst_size];
2470 len = priv->ucode_data.len;
e1623446
TW
2471 IWL_DEBUG_INFO(priv,
2472 "Copying (but not loading) uCode data len %zd\n", len);
b481de9c
ZY
2473 memcpy(priv->ucode_data.v_addr, src, len);
2474 memcpy(priv->ucode_data_backup.v_addr, src, len);
2475
2476 /* Initialization instructions (3rd block) */
2477 if (init_size) {
2478 src = &ucode->data[inst_size + data_size];
2479 len = priv->ucode_init.len;
e1623446
TW
2480 IWL_DEBUG_INFO(priv,
2481 "Copying (but not loading) init instr len %zd\n", len);
b481de9c
ZY
2482 memcpy(priv->ucode_init.v_addr, src, len);
2483 }
2484
2485 /* Initialization data (4th block) */
2486 if (init_data_size) {
2487 src = &ucode->data[inst_size + data_size + init_size];
2488 len = priv->ucode_init_data.len;
e1623446
TW
2489 IWL_DEBUG_INFO(priv,
2490 "Copying (but not loading) init data len %zd\n", len);
b481de9c
ZY
2491 memcpy(priv->ucode_init_data.v_addr, src, len);
2492 }
2493
2494 /* Bootstrap instructions (5th block) */
2495 src = &ucode->data[inst_size + data_size + init_size + init_data_size];
2496 len = priv->ucode_boot.len;
e1623446
TW
2497 IWL_DEBUG_INFO(priv,
2498 "Copying (but not loading) boot instr len %zd\n", len);
b481de9c
ZY
2499 memcpy(priv->ucode_boot.v_addr, src, len);
2500
2501 /* We have our copies now, allow OS release its copies */
2502 release_firmware(ucode_raw);
2503 return 0;
2504
2505 err_pci_alloc:
15b1687c 2506 IWL_ERR(priv, "failed to allocate pci memory\n");
90e759d1 2507 ret = -ENOMEM;
bb8c093b 2508 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY
2509
2510 err_release:
2511 release_firmware(ucode_raw);
2512
2513 error:
90e759d1 2514 return ret;
b481de9c
ZY
2515}
2516
2517
2518/**
bb8c093b 2519 * iwl3945_set_ucode_ptrs - Set uCode address location
b481de9c
ZY
2520 *
2521 * Tell initialization uCode where to find runtime uCode.
2522 *
2523 * BSM registers initially contain pointers to initialization uCode.
2524 * We need to replace them to load runtime uCode inst and data,
2525 * and to save runtime data when powering down.
2526 */
4a8a4322 2527static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv)
b481de9c
ZY
2528{
2529 dma_addr_t pinst;
2530 dma_addr_t pdata;
2531 int rc = 0;
2532 unsigned long flags;
2533
2534 /* bits 31:0 for 3945 */
2535 pinst = priv->ucode_code.p_addr;
2536 pdata = priv->ucode_data_backup.p_addr;
2537
2538 spin_lock_irqsave(&priv->lock, flags);
5d49f498 2539 rc = iwl_grab_nic_access(priv);
b481de9c
ZY
2540 if (rc) {
2541 spin_unlock_irqrestore(&priv->lock, flags);
2542 return rc;
2543 }
2544
2545 /* Tell bootstrap uCode where to find image to load */
5d49f498
AK
2546 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2547 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2548 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
b481de9c
ZY
2549 priv->ucode_data.len);
2550
a96a27f9 2551 /* Inst byte count must be last to set up, bit 31 signals uCode
b481de9c 2552 * that all new ptr/size info is in place */
5d49f498 2553 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
b481de9c
ZY
2554 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
2555
5d49f498 2556 iwl_release_nic_access(priv);
b481de9c
ZY
2557
2558 spin_unlock_irqrestore(&priv->lock, flags);
2559
e1623446 2560 IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n");
b481de9c
ZY
2561
2562 return rc;
2563}
2564
2565/**
bb8c093b 2566 * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
b481de9c
ZY
2567 *
2568 * Called after REPLY_ALIVE notification received from "initialize" uCode.
2569 *
b481de9c 2570 * Tell "initialize" uCode to go ahead and load the runtime uCode.
9fbab516 2571 */
4a8a4322 2572static void iwl3945_init_alive_start(struct iwl_priv *priv)
b481de9c
ZY
2573{
2574 /* Check alive response for "valid" sign from uCode */
2575 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
2576 /* We had an error bringing up the hardware, so take it
2577 * all the way back down so we can try again */
e1623446 2578 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
b481de9c
ZY
2579 goto restart;
2580 }
2581
2582 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
2583 * This is a paranoid check, because we would not have gotten the
2584 * "initialize" alive if code weren't properly loaded. */
bb8c093b 2585 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY
2586 /* Runtime instruction load was bad;
2587 * take it all the way back down so we can try again */
e1623446 2588 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
b481de9c
ZY
2589 goto restart;
2590 }
2591
2592 /* Send pointers to protocol/runtime uCode image ... init code will
2593 * load and launch runtime uCode, which will send us another "Alive"
2594 * notification. */
e1623446 2595 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
bb8c093b 2596 if (iwl3945_set_ucode_ptrs(priv)) {
b481de9c
ZY
2597 /* Runtime instruction load won't happen;
2598 * take it all the way back down so we can try again */
e1623446 2599 IWL_DEBUG_INFO(priv, "Couldn't set up uCode pointers.\n");
b481de9c
ZY
2600 goto restart;
2601 }
2602 return;
2603
2604 restart:
2605 queue_work(priv->workqueue, &priv->restart);
2606}
2607
b481de9c 2608/**
bb8c093b 2609 * iwl3945_alive_start - called after REPLY_ALIVE notification received
b481de9c 2610 * from protocol/runtime uCode (initialization uCode's
bb8c093b 2611 * Alive gets handled by iwl3945_init_alive_start()).
b481de9c 2612 */
4a8a4322 2613static void iwl3945_alive_start(struct iwl_priv *priv)
b481de9c
ZY
2614{
2615 int rc = 0;
2616 int thermal_spin = 0;
2617 u32 rfkill;
2618
e1623446 2619 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY
2620
2621 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2622 /* We had an error bringing up the hardware, so take it
2623 * all the way back down so we can try again */
e1623446 2624 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY
2625 goto restart;
2626 }
2627
2628 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2629 * This is a paranoid check, because we would not have gotten the
2630 * "runtime" alive if code weren't properly loaded. */
bb8c093b 2631 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY
2632 /* Runtime instruction load was bad;
2633 * take it all the way back down so we can try again */
e1623446 2634 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY
2635 goto restart;
2636 }
2637
40ace5b3 2638 priv->cfg->ops->smgmt->clear_station_table(priv);
b481de9c 2639
5d49f498 2640 rc = iwl_grab_nic_access(priv);
b481de9c 2641 if (rc) {
39aadf8c 2642 IWL_WARN(priv, "Can not read RFKILL status from adapter\n");
b481de9c
ZY
2643 return;
2644 }
2645
5d49f498 2646 rfkill = iwl_read_prph(priv, APMG_RFKILL_REG);
e1623446 2647 IWL_DEBUG_INFO(priv, "RFKILL status: 0x%x\n", rfkill);
5d49f498 2648 iwl_release_nic_access(priv);
b481de9c
ZY
2649
2650 if (rfkill & 0x1) {
2651 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a96a27f9 2652 /* if RFKILL is not on, then wait for thermal
b481de9c 2653 * sensor in adapter to kick in */
bb8c093b 2654 while (iwl3945_hw_get_temperature(priv) == 0) {
b481de9c
ZY
2655 thermal_spin++;
2656 udelay(10);
2657 }
2658
2659 if (thermal_spin)
e1623446 2660 IWL_DEBUG_INFO(priv, "Thermal calibration took %dus\n",
b481de9c
ZY
2661 thermal_spin * 10);
2662 } else
2663 set_bit(STATUS_RF_KILL_HW, &priv->status);
2664
9fbab516 2665 /* After the ALIVE response, we can send commands to 3945 uCode */
b481de9c
ZY
2666 set_bit(STATUS_ALIVE, &priv->status);
2667
775a6e27 2668 if (iwl_is_rfkill(priv))
b481de9c
ZY
2669 return;
2670
36d6825b 2671 ieee80211_wake_queues(priv->hw);
b481de9c
ZY
2672
2673 priv->active_rate = priv->rates_mask;
2674 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
2675
d25aabb0 2676 iwl_power_update_mode(priv, false);
b481de9c 2677
8ccde88a 2678 if (iwl_is_associated(priv)) {
bb8c093b 2679 struct iwl3945_rxon_cmd *active_rxon =
8ccde88a 2680 (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
b481de9c 2681
8ccde88a
SO
2682 memcpy(&priv->staging_rxon, &priv->active_rxon,
2683 sizeof(priv->staging_rxon));
b481de9c
ZY
2684 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2685 } else {
2686 /* Initialize our rx_config data */
8ccde88a 2687 iwl_connection_init_rx_config(priv, priv->iw_mode);
b481de9c
ZY
2688 }
2689
9fbab516 2690 /* Configure Bluetooth device coexistence support */
17f841cd 2691 iwl_send_bt_config(priv);
b481de9c
ZY
2692
2693 /* Configure the adapter for unassociated operation */
e0158e61 2694 iwlcore_commit_rxon(priv);
b481de9c 2695
b481de9c
ZY
2696 iwl3945_reg_txpower_periodic(priv);
2697
fe00b5a5
RC
2698 iwl3945_led_register(priv);
2699
e1623446 2700 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 2701 set_bit(STATUS_READY, &priv->status);
5a66926a 2702 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 2703
9bdf5eca
MA
2704 /* reassociate for ADHOC mode */
2705 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
2706 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
2707 priv->vif);
2708 if (beacon)
9944b938 2709 iwl_mac_beacon_update(priv->hw, beacon);
9bdf5eca
MA
2710 }
2711
f45c2714 2712 if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
727882d6 2713 iwl_set_mode(priv, priv->iw_mode);
f45c2714 2714
b481de9c
ZY
2715 return;
2716
2717 restart:
2718 queue_work(priv->workqueue, &priv->restart);
2719}
2720
4a8a4322 2721static void iwl3945_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 2722
4a8a4322 2723static void __iwl3945_down(struct iwl_priv *priv)
b481de9c
ZY
2724{
2725 unsigned long flags;
2726 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2727 struct ieee80211_conf *conf = NULL;
2728
e1623446 2729 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c
ZY
2730
2731 conf = ieee80211_get_hw_conf(priv->hw);
2732
2733 if (!exit_pending)
2734 set_bit(STATUS_EXIT_PENDING, &priv->status);
2735
ab53d8af 2736 iwl3945_led_unregister(priv);
40ace5b3 2737 priv->cfg->ops->smgmt->clear_station_table(priv);
b481de9c
ZY
2738
2739 /* Unblock any waiting calls */
2740 wake_up_interruptible_all(&priv->wait_command_queue);
2741
b481de9c
ZY
2742 /* Wipe out the EXIT_PENDING status bit if we are not actually
2743 * exiting the module */
2744 if (!exit_pending)
2745 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2746
2747 /* stop and reset the on-board processor */
5d49f498 2748 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY
2749
2750 /* tell the device to stop sending interrupts */
0359facc 2751 spin_lock_irqsave(&priv->lock, flags);
ed3b932e 2752 iwl_disable_interrupts(priv);
0359facc
MA
2753 spin_unlock_irqrestore(&priv->lock, flags);
2754 iwl_synchronize_irq(priv);
b481de9c
ZY
2755
2756 if (priv->mac80211_registered)
2757 ieee80211_stop_queues(priv->hw);
2758
bb8c093b 2759 /* If we have not previously called iwl3945_init() then
6da3a13e 2760 * clear all bits but the RF Kill bits and return */
775a6e27 2761 if (!iwl_is_init(priv)) {
b481de9c
ZY
2762 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2763 STATUS_RF_KILL_HW |
2764 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
2765 STATUS_RF_KILL_SW |
9788864e
RC
2766 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2767 STATUS_GEO_CONFIGURED |
ebef2008
AK
2768 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2769 STATUS_EXIT_PENDING;
b481de9c
ZY
2770 goto exit;
2771 }
2772
6da3a13e
WYG
2773 /* ...otherwise clear out all the status bits but the RF Kill
2774 * bits and continue taking the NIC down. */
b481de9c
ZY
2775 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2776 STATUS_RF_KILL_HW |
2777 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
2778 STATUS_RF_KILL_SW |
9788864e
RC
2779 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2780 STATUS_GEO_CONFIGURED |
b481de9c 2781 test_bit(STATUS_FW_ERROR, &priv->status) <<
ebef2008
AK
2782 STATUS_FW_ERROR |
2783 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2784 STATUS_EXIT_PENDING;
b481de9c 2785
e9414b6b 2786 priv->cfg->ops->lib->apm_ops.reset(priv);
b481de9c 2787 spin_lock_irqsave(&priv->lock, flags);
5d49f498 2788 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY
2789 spin_unlock_irqrestore(&priv->lock, flags);
2790
bb8c093b
CH
2791 iwl3945_hw_txq_ctx_stop(priv);
2792 iwl3945_hw_rxq_stop(priv);
b481de9c
ZY
2793
2794 spin_lock_irqsave(&priv->lock, flags);
5d49f498
AK
2795 if (!iwl_grab_nic_access(priv)) {
2796 iwl_write_prph(priv, APMG_CLK_DIS_REG,
b481de9c 2797 APMG_CLK_VAL_DMA_CLK_RQT);
5d49f498 2798 iwl_release_nic_access(priv);
b481de9c
ZY
2799 }
2800 spin_unlock_irqrestore(&priv->lock, flags);
2801
2802 udelay(5);
2803
6da3a13e 2804 if (exit_pending)
e9414b6b
AM
2805 priv->cfg->ops->lib->apm_ops.stop(priv);
2806 else
2807 priv->cfg->ops->lib->apm_ops.reset(priv);
2808
b481de9c 2809 exit:
3d24a9f7 2810 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY
2811
2812 if (priv->ibss_beacon)
2813 dev_kfree_skb(priv->ibss_beacon);
2814 priv->ibss_beacon = NULL;
2815
2816 /* clear out any free frames */
bb8c093b 2817 iwl3945_clear_free_frames(priv);
b481de9c
ZY
2818}
2819
4a8a4322 2820static void iwl3945_down(struct iwl_priv *priv)
b481de9c
ZY
2821{
2822 mutex_lock(&priv->mutex);
bb8c093b 2823 __iwl3945_down(priv);
b481de9c 2824 mutex_unlock(&priv->mutex);
b24d22b1 2825
bb8c093b 2826 iwl3945_cancel_deferred_work(priv);
b481de9c
ZY
2827}
2828
2829#define MAX_HW_RESTARTS 5
2830
4a8a4322 2831static int __iwl3945_up(struct iwl_priv *priv)
b481de9c
ZY
2832{
2833 int rc, i;
2834
2835 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 2836 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY
2837 return -EIO;
2838 }
2839
2840 if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
39aadf8c 2841 IWL_WARN(priv, "Radio disabled by SW RF kill (module "
b481de9c 2842 "parameter)\n");
e655b9f0
ZY
2843 return -ENODEV;
2844 }
2845
e903fbd4 2846 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 2847 IWL_ERR(priv, "ucode not available for device bring up\n");
e903fbd4
RC
2848 return -EIO;
2849 }
2850
e655b9f0 2851 /* If platform's RF_KILL switch is NOT set to KILL */
5d49f498 2852 if (iwl_read32(priv, CSR_GP_CNTRL) &
e655b9f0
ZY
2853 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2854 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2855 else {
2856 set_bit(STATUS_RF_KILL_HW, &priv->status);
6da3a13e
WYG
2857 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2858 return -ENODEV;
b481de9c 2859 }
80fcc9e2 2860
5d49f498 2861 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 2862
bb8c093b 2863 rc = iwl3945_hw_nic_init(priv);
b481de9c 2864 if (rc) {
15b1687c 2865 IWL_ERR(priv, "Unable to int nic\n");
b481de9c
ZY
2866 return rc;
2867 }
2868
2869 /* make sure rfkill handshake bits are cleared */
5d49f498
AK
2870 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2871 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY
2872 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2873
2874 /* clear (again), then enable host interrupts */
5d49f498 2875 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
ed3b932e 2876 iwl_enable_interrupts(priv);
b481de9c
ZY
2877
2878 /* really make sure rfkill handshake bits are cleared */
5d49f498
AK
2879 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2880 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
2881
2882 /* Copy original ucode data image from disk into backup cache.
2883 * This will be used to initialize the on-board processor's
2884 * data SRAM for a clean start when the runtime program first loads. */
2885 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 2886 priv->ucode_data.len);
b481de9c 2887
e655b9f0
ZY
2888 /* We return success when we resume from suspend and rf_kill is on. */
2889 if (test_bit(STATUS_RF_KILL_HW, &priv->status))
2890 return 0;
2891
b481de9c
ZY
2892 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2893
40ace5b3 2894 priv->cfg->ops->smgmt->clear_station_table(priv);
b481de9c
ZY
2895
2896 /* load bootstrap state machine,
2897 * load bootstrap program into processor's memory,
2898 * prepare to load the "initialize" uCode */
0164b9b4 2899 priv->cfg->ops->lib->load_ucode(priv);
b481de9c
ZY
2900
2901 if (rc) {
15b1687c
WT
2902 IWL_ERR(priv,
2903 "Unable to set up bootstrap uCode: %d\n", rc);
b481de9c
ZY
2904 continue;
2905 }
2906
2907 /* start card; "initialize" will load runtime ucode */
bb8c093b 2908 iwl3945_nic_start(priv);
b481de9c 2909
e1623446 2910 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY
2911
2912 return 0;
2913 }
2914
2915 set_bit(STATUS_EXIT_PENDING, &priv->status);
bb8c093b 2916 __iwl3945_down(priv);
ebef2008 2917 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY
2918
2919 /* tried to restart and config the device for as long as our
2920 * patience could withstand */
15b1687c 2921 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY
2922 return -EIO;
2923}
2924
2925
2926/*****************************************************************************
2927 *
2928 * Workqueue callbacks
2929 *
2930 *****************************************************************************/
2931
bb8c093b 2932static void iwl3945_bg_init_alive_start(struct work_struct *data)
b481de9c 2933{
4a8a4322
AK
2934 struct iwl_priv *priv =
2935 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY
2936
2937 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2938 return;
2939
2940 mutex_lock(&priv->mutex);
bb8c093b 2941 iwl3945_init_alive_start(priv);
b481de9c
ZY
2942 mutex_unlock(&priv->mutex);
2943}
2944
bb8c093b 2945static void iwl3945_bg_alive_start(struct work_struct *data)
b481de9c 2946{
4a8a4322
AK
2947 struct iwl_priv *priv =
2948 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY
2949
2950 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2951 return;
2952
2953 mutex_lock(&priv->mutex);
bb8c093b 2954 iwl3945_alive_start(priv);
b481de9c
ZY
2955 mutex_unlock(&priv->mutex);
2956}
2957
2663516d
HS
2958static void iwl3945_rfkill_poll(struct work_struct *data)
2959{
2960 struct iwl_priv *priv =
2961 container_of(data, struct iwl_priv, rfkill_poll.work);
2962 unsigned long status = priv->status;
2963
2964 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2965 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2966 else
2967 set_bit(STATUS_RF_KILL_HW, &priv->status);
2968
2969 if (test_bit(STATUS_RF_KILL_HW, &status) != test_bit(STATUS_RF_KILL_HW, &priv->status))
2970 queue_work(priv->workqueue, &priv->rf_kill);
2971
2972 queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
2973 round_jiffies_relative(2 * HZ));
2974
2975}
2976
b481de9c 2977#define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
bb8c093b 2978static void iwl3945_bg_request_scan(struct work_struct *data)
b481de9c 2979{
4a8a4322
AK
2980 struct iwl_priv *priv =
2981 container_of(data, struct iwl_priv, request_scan);
c2d79b48 2982 struct iwl_host_cmd cmd = {
b481de9c 2983 .id = REPLY_SCAN_CMD,
bb8c093b 2984 .len = sizeof(struct iwl3945_scan_cmd),
b481de9c
ZY
2985 .meta.flags = CMD_SIZE_HUGE,
2986 };
2987 int rc = 0;
bb8c093b 2988 struct iwl3945_scan_cmd *scan;
b481de9c 2989 struct ieee80211_conf *conf = NULL;
1ecf9fc1 2990 u8 n_probes = 0;
8318d78a 2991 enum ieee80211_band band;
1ecf9fc1 2992 bool is_active = false;
b481de9c
ZY
2993
2994 conf = ieee80211_get_hw_conf(priv->hw);
2995
2996 mutex_lock(&priv->mutex);
2997
775a6e27 2998 if (!iwl_is_ready(priv)) {
39aadf8c 2999 IWL_WARN(priv, "request scan called when driver not ready.\n");
b481de9c
ZY
3000 goto done;
3001 }
3002
a96a27f9 3003 /* Make sure the scan wasn't canceled before this queued work
b481de9c
ZY
3004 * was given the chance to run... */
3005 if (!test_bit(STATUS_SCANNING, &priv->status))
3006 goto done;
3007
3008 /* This should never be called or scheduled if there is currently
3009 * a scan active in the hardware. */
3010 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
e1623446
TW
3011 IWL_DEBUG_INFO(priv, "Multiple concurrent scan requests "
3012 "Ignoring second request.\n");
b481de9c
ZY
3013 rc = -EIO;
3014 goto done;
3015 }
3016
3017 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
e1623446 3018 IWL_DEBUG_SCAN(priv, "Aborting scan due to device shutdown\n");
b481de9c
ZY
3019 goto done;
3020 }
3021
3022 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
e1623446
TW
3023 IWL_DEBUG_HC(priv,
3024 "Scan request while abort pending. Queuing.\n");
b481de9c
ZY
3025 goto done;
3026 }
3027
775a6e27 3028 if (iwl_is_rfkill(priv)) {
e1623446 3029 IWL_DEBUG_HC(priv, "Aborting scan due to RF Kill activation\n");
b481de9c
ZY
3030 goto done;
3031 }
3032
3033 if (!test_bit(STATUS_READY, &priv->status)) {
e1623446
TW
3034 IWL_DEBUG_HC(priv,
3035 "Scan request while uninitialized. Queuing.\n");
b481de9c
ZY
3036 goto done;
3037 }
3038
3039 if (!priv->scan_bands) {
e1623446 3040 IWL_DEBUG_HC(priv, "Aborting scan due to no requested bands\n");
b481de9c
ZY
3041 goto done;
3042 }
3043
805cee5b
WT
3044 if (!priv->scan) {
3045 priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
b481de9c 3046 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
805cee5b 3047 if (!priv->scan) {
b481de9c
ZY
3048 rc = -ENOMEM;
3049 goto done;
3050 }
3051 }
805cee5b 3052 scan = priv->scan;
bb8c093b 3053 memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
b481de9c
ZY
3054
3055 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
3056 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
3057
8ccde88a 3058 if (iwl_is_associated(priv)) {
b481de9c
ZY
3059 u16 interval = 0;
3060 u32 extra;
3061 u32 suspend_time = 100;
3062 u32 scan_suspend_time = 100;
3063 unsigned long flags;
3064
e1623446 3065 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
b481de9c
ZY
3066
3067 spin_lock_irqsave(&priv->lock, flags);
3068 interval = priv->beacon_int;
3069 spin_unlock_irqrestore(&priv->lock, flags);
3070
3071 scan->suspend_time = 0;
15e869d8 3072 scan->max_out_time = cpu_to_le32(200 * 1024);
b481de9c
ZY
3073 if (!interval)
3074 interval = suspend_time;
3075 /*
3076 * suspend time format:
3077 * 0-19: beacon interval in usec (time before exec.)
3078 * 20-23: 0
3079 * 24-31: number of beacons (suspend between channels)
3080 */
3081
3082 extra = (suspend_time / interval) << 24;
3083 scan_suspend_time = 0xFF0FFFFF &
3084 (extra | ((suspend_time % interval) * 1024));
3085
3086 scan->suspend_time = cpu_to_le32(scan_suspend_time);
e1623446 3087 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
b481de9c
ZY
3088 scan_suspend_time, interval);
3089 }
3090
1ecf9fc1
JB
3091 if (priv->scan_request->n_ssids) {
3092 int i, p = 0;
3093 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
3094 for (i = 0; i < priv->scan_request->n_ssids; i++) {
3095 /* always does wildcard anyway */
3096 if (!priv->scan_request->ssids[i].ssid_len)
3097 continue;
3098 scan->direct_scan[p].id = WLAN_EID_SSID;
3099 scan->direct_scan[p].len =
3100 priv->scan_request->ssids[i].ssid_len;
3101 memcpy(scan->direct_scan[p].ssid,
3102 priv->scan_request->ssids[i].ssid,
3103 priv->scan_request->ssids[i].ssid_len);
3104 n_probes++;
3105 p++;
3106 }
3107 is_active = true;
f9340520 3108 } else
1ecf9fc1 3109 IWL_DEBUG_SCAN(priv, "Kicking off passive scan.\n");
b481de9c
ZY
3110
3111 /* We don't build a direct scan probe request; the uCode will do
3112 * that based on the direct_mask added to each channel entry */
b481de9c 3113 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
3832ec9d 3114 scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY
3115 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
3116
3117 /* flags + rate selection */
3118
66b5004d 3119 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
b481de9c
ZY
3120 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
3121 scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
3122 scan->good_CRC_th = 0;
8318d78a 3123 band = IEEE80211_BAND_2GHZ;
66b5004d 3124 } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
b481de9c 3125 scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
b097ad29
JB
3126 /*
3127 * If active scaning is requested but a certain channel
3128 * is marked passive, we can do active scanning if we
3129 * detect transmissions.
3130 */
3131 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH : 0;
8318d78a 3132 band = IEEE80211_BAND_5GHZ;
66b5004d 3133 } else {
39aadf8c 3134 IWL_WARN(priv, "Invalid scan band count\n");
b481de9c
ZY
3135 goto done;
3136 }
3137
77fecfb8 3138 scan->tx_cmd.len = cpu_to_le16(
1ecf9fc1
JB
3139 iwl_fill_probe_req(priv,
3140 (struct ieee80211_mgmt *)scan->data,
3141 priv->scan_request->ie,
3142 priv->scan_request->ie_len,
3143 IWL_MAX_SCAN_SIZE - sizeof(*scan)));
77fecfb8 3144
b481de9c
ZY
3145 /* select Rx antennas */
3146 scan->flags |= iwl3945_get_antenna_flags(priv);
3147
279b05d4 3148 if (iwl_is_monitor_mode(priv))
b481de9c
ZY
3149 scan->filter_flags = RXON_FILTER_PROMISC_MSK;
3150
f9340520 3151 scan->channel_count =
1ecf9fc1 3152 iwl3945_get_channels_for_scan(priv, band, is_active, n_probes,
f9340520 3153 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
b481de9c 3154
14b54336 3155 if (scan->channel_count == 0) {
e1623446 3156 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
14b54336
RC
3157 goto done;
3158 }
3159
b481de9c 3160 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
bb8c093b 3161 scan->channel_count * sizeof(struct iwl3945_scan_channel);
b481de9c
ZY
3162 cmd.data = scan;
3163 scan->len = cpu_to_le16(cmd.len);
3164
3165 set_bit(STATUS_SCAN_HW, &priv->status);
518099a8 3166 rc = iwl_send_cmd_sync(priv, &cmd);
b481de9c
ZY
3167 if (rc)
3168 goto done;
3169
3170 queue_delayed_work(priv->workqueue, &priv->scan_check,
3171 IWL_SCAN_CHECK_WATCHDOG);
3172
3173 mutex_unlock(&priv->mutex);
3174 return;
3175
3176 done:
2420ebc1
MA
3177 /* can not perform scan make sure we clear scanning
3178 * bits from status so next scan request can be performed.
3179 * if we dont clear scanning status bit here all next scan
3180 * will fail
3181 */
3182 clear_bit(STATUS_SCAN_HW, &priv->status);
3183 clear_bit(STATUS_SCANNING, &priv->status);
3184
01ebd063 3185 /* inform mac80211 scan aborted */
b481de9c
ZY
3186 queue_work(priv->workqueue, &priv->scan_completed);
3187 mutex_unlock(&priv->mutex);
3188}
3189
bb8c093b 3190static void iwl3945_bg_up(struct work_struct *data)
b481de9c 3191{
4a8a4322 3192 struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
b481de9c
ZY
3193
3194 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3195 return;
3196
3197 mutex_lock(&priv->mutex);
bb8c093b 3198 __iwl3945_up(priv);
b481de9c 3199 mutex_unlock(&priv->mutex);
c0af96a6 3200 iwl_rfkill_set_hw_state(priv);
b481de9c
ZY
3201}
3202
bb8c093b 3203static void iwl3945_bg_restart(struct work_struct *data)
b481de9c 3204{
4a8a4322 3205 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY
3206
3207 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3208 return;
3209
19cc1087
JB
3210 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
3211 mutex_lock(&priv->mutex);
3212 priv->vif = NULL;
3213 priv->is_open = 0;
3214 mutex_unlock(&priv->mutex);
3215 iwl3945_down(priv);
3216 ieee80211_restart_hw(priv->hw);
3217 } else {
3218 iwl3945_down(priv);
3219 queue_work(priv->workqueue, &priv->up);
3220 }
b481de9c
ZY
3221}
3222
bb8c093b 3223static void iwl3945_bg_rx_replenish(struct work_struct *data)
b481de9c 3224{
4a8a4322
AK
3225 struct iwl_priv *priv =
3226 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY
3227
3228 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3229 return;
3230
3231 mutex_lock(&priv->mutex);
bb8c093b 3232 iwl3945_rx_replenish(priv);
b481de9c
ZY
3233 mutex_unlock(&priv->mutex);
3234}
3235
7878a5a4
MA
3236#define IWL_DELAY_NEXT_SCAN (HZ*2)
3237
5bbe233b 3238void iwl3945_post_associate(struct iwl_priv *priv)
b481de9c 3239{
b481de9c
ZY
3240 int rc = 0;
3241 struct ieee80211_conf *conf = NULL;
3242
05c914fe 3243 if (priv->iw_mode == NL80211_IFTYPE_AP) {
15b1687c 3244 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY
3245 return;
3246 }
3247
3248
e1623446 3249 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
8ccde88a 3250 priv->assoc_id, priv->active_rxon.bssid_addr);
b481de9c
ZY
3251
3252 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3253 return;
3254
322a9811 3255 if (!priv->vif || !priv->is_open)
6ef89d0a 3256 return;
322a9811 3257
af0053d6 3258 iwl_scan_cancel_timeout(priv, 200);
15e869d8 3259
b481de9c
ZY
3260 conf = ieee80211_get_hw_conf(priv->hw);
3261
8ccde88a 3262 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 3263 iwlcore_commit_rxon(priv);
b481de9c 3264
28afaf91 3265 memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
bb8c093b 3266 iwl3945_setup_rxon_timing(priv);
518099a8 3267 rc = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY
3268 sizeof(priv->rxon_timing), &priv->rxon_timing);
3269 if (rc)
39aadf8c 3270 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
3271 "Attempting to continue.\n");
3272
8ccde88a 3273 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c 3274
8ccde88a 3275 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
b481de9c 3276
e1623446 3277 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
b481de9c
ZY
3278 priv->assoc_id, priv->beacon_int);
3279
3280 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
8ccde88a 3281 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 3282 else
8ccde88a 3283 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 3284
8ccde88a 3285 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
b481de9c 3286 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
8ccde88a 3287 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
b481de9c 3288 else
8ccde88a 3289 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c 3290
05c914fe 3291 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
8ccde88a 3292 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c
ZY
3293
3294 }
3295
e0158e61 3296 iwlcore_commit_rxon(priv);
b481de9c
ZY
3297
3298 switch (priv->iw_mode) {
05c914fe 3299 case NL80211_IFTYPE_STATION:
bb8c093b 3300 iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
b481de9c
ZY
3301 break;
3302
05c914fe 3303 case NL80211_IFTYPE_ADHOC:
b481de9c 3304
ce546fd2 3305 priv->assoc_id = 1;
06fd3d86 3306 priv->cfg->ops->smgmt->add_station(priv, priv->bssid, 0, 0, NULL);
b481de9c 3307 iwl3945_sync_sta(priv, IWL_STA_ID,
8318d78a 3308 (priv->band == IEEE80211_BAND_5GHZ) ?
b481de9c
ZY
3309 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
3310 CMD_ASYNC);
bb8c093b
CH
3311 iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
3312 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
3313
3314 break;
3315
3316 default:
15b1687c 3317 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3ac7f146 3318 __func__, priv->iw_mode);
b481de9c
ZY
3319 break;
3320 }
3321
14d2aac5 3322 iwl_activate_qos(priv, 0);
292ae174 3323
7878a5a4
MA
3324 /* we have just associated, don't start scan too early */
3325 priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
cd56d331
AK
3326}
3327
b481de9c
ZY
3328/*****************************************************************************
3329 *
3330 * mac80211 entry point functions
3331 *
3332 *****************************************************************************/
3333
5a66926a
ZY
3334#define UCODE_READY_TIMEOUT (2 * HZ)
3335
bb8c093b 3336static int iwl3945_mac_start(struct ieee80211_hw *hw)
b481de9c 3337{
4a8a4322 3338 struct iwl_priv *priv = hw->priv;
5a66926a 3339 int ret;
b481de9c 3340
e1623446 3341 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY
3342
3343 /* we should be verifying the device is ready to be opened */
3344 mutex_lock(&priv->mutex);
3345
8ccde88a 3346 memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
5a66926a
ZY
3347 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
3348 * ucode filename and max sizes are card-specific. */
3349
3350 if (!priv->ucode_code.len) {
3351 ret = iwl3945_read_ucode(priv);
3352 if (ret) {
15b1687c 3353 IWL_ERR(priv, "Could not read microcode: %d\n", ret);
5a66926a
ZY
3354 mutex_unlock(&priv->mutex);
3355 goto out_release_irq;
3356 }
3357 }
b481de9c 3358
e655b9f0 3359 ret = __iwl3945_up(priv);
b481de9c
ZY
3360
3361 mutex_unlock(&priv->mutex);
5a66926a 3362
c0af96a6 3363 iwl_rfkill_set_hw_state(priv);
80fcc9e2 3364
e655b9f0
ZY
3365 if (ret)
3366 goto out_release_irq;
3367
e1623446 3368 IWL_DEBUG_INFO(priv, "Start UP work.\n");
e655b9f0 3369
5a66926a
ZY
3370 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
3371 * mac80211 will not be run successfully. */
3372 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3373 test_bit(STATUS_READY, &priv->status),
3374 UCODE_READY_TIMEOUT);
3375 if (!ret) {
3376 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c
WT
3377 IWL_ERR(priv,
3378 "Wait for START_ALIVE timeout after %dms.\n",
3379 jiffies_to_msecs(UCODE_READY_TIMEOUT));
5a66926a
ZY
3380 ret = -ETIMEDOUT;
3381 goto out_release_irq;
3382 }
3383 }
3384
2663516d
HS
3385 /* ucode is running and will send rfkill notifications,
3386 * no need to poll the killswitch state anymore */
3387 cancel_delayed_work(&priv->rfkill_poll);
3388
e655b9f0 3389 priv->is_open = 1;
e1623446 3390 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 3391 return 0;
5a66926a
ZY
3392
3393out_release_irq:
e655b9f0 3394 priv->is_open = 0;
e1623446 3395 IWL_DEBUG_MAC80211(priv, "leave - failed\n");
5a66926a 3396 return ret;
b481de9c
ZY
3397}
3398
bb8c093b 3399static void iwl3945_mac_stop(struct ieee80211_hw *hw)
b481de9c 3400{
4a8a4322 3401 struct iwl_priv *priv = hw->priv;
b481de9c 3402
e1623446 3403 IWL_DEBUG_MAC80211(priv, "enter\n");
6ef89d0a 3404
e655b9f0 3405 if (!priv->is_open) {
e1623446 3406 IWL_DEBUG_MAC80211(priv, "leave - skip\n");
e655b9f0
ZY
3407 return;
3408 }
3409
b481de9c 3410 priv->is_open = 0;
5a66926a 3411
775a6e27 3412 if (iwl_is_ready_rf(priv)) {
e655b9f0
ZY
3413 /* stop mac, cancel any scan request and clear
3414 * RXON_FILTER_ASSOC_MSK BIT
3415 */
5a66926a 3416 mutex_lock(&priv->mutex);
af0053d6 3417 iwl_scan_cancel_timeout(priv, 100);
fde3571f 3418 mutex_unlock(&priv->mutex);
fde3571f
MA
3419 }
3420
5a66926a
ZY
3421 iwl3945_down(priv);
3422
3423 flush_workqueue(priv->workqueue);
2663516d
HS
3424
3425 /* start polling the killswitch state again */
3426 queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
3427 round_jiffies_relative(2 * HZ));
6ef89d0a 3428
e1623446 3429 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
3430}
3431
e039fa4a 3432static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 3433{
4a8a4322 3434 struct iwl_priv *priv = hw->priv;
b481de9c 3435
e1623446 3436 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3437
e1623446 3438 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 3439 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 3440
e039fa4a 3441 if (iwl3945_tx_skb(priv, skb))
b481de9c
ZY
3442 dev_kfree_skb_any(skb);
3443
e1623446 3444 IWL_DEBUG_MAC80211(priv, "leave\n");
637f8837 3445 return NETDEV_TX_OK;
b481de9c
ZY
3446}
3447
60690a6a 3448void iwl3945_config_ap(struct iwl_priv *priv)
b481de9c
ZY
3449{
3450 int rc = 0;
3451
d986bcd1 3452 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY
3453 return;
3454
3455 /* The following should be done only at AP bring up */
8ccde88a 3456 if (!(iwl_is_associated(priv))) {
b481de9c
ZY
3457
3458 /* RXON - unassoc (to set timing command) */
8ccde88a 3459 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 3460 iwlcore_commit_rxon(priv);
b481de9c
ZY
3461
3462 /* RXON Timing */
28afaf91 3463 memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
bb8c093b 3464 iwl3945_setup_rxon_timing(priv);
518099a8
SO
3465 rc = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
3466 sizeof(priv->rxon_timing),
3467 &priv->rxon_timing);
b481de9c 3468 if (rc)
39aadf8c 3469 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
3470 "Attempting to continue.\n");
3471
3472 /* FIXME: what should be the assoc_id for AP? */
8ccde88a 3473 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
b481de9c 3474 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
8ccde88a 3475 priv->staging_rxon.flags |=
b481de9c
ZY
3476 RXON_FLG_SHORT_PREAMBLE_MSK;
3477 else
8ccde88a 3478 priv->staging_rxon.flags &=
b481de9c
ZY
3479 ~RXON_FLG_SHORT_PREAMBLE_MSK;
3480
8ccde88a 3481 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
b481de9c
ZY
3482 if (priv->assoc_capability &
3483 WLAN_CAPABILITY_SHORT_SLOT_TIME)
8ccde88a 3484 priv->staging_rxon.flags |=
b481de9c
ZY
3485 RXON_FLG_SHORT_SLOT_MSK;
3486 else
8ccde88a 3487 priv->staging_rxon.flags &=
b481de9c
ZY
3488 ~RXON_FLG_SHORT_SLOT_MSK;
3489
05c914fe 3490 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
8ccde88a 3491 priv->staging_rxon.flags &=
b481de9c
ZY
3492 ~RXON_FLG_SHORT_SLOT_MSK;
3493 }
3494 /* restore RXON assoc */
8ccde88a 3495 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
e0158e61 3496 iwlcore_commit_rxon(priv);
06fd3d86 3497 priv->cfg->ops->smgmt->add_station(priv, iwl_bcast_addr, 0, 0, NULL);
556f8db7 3498 }
bb8c093b 3499 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
3500
3501 /* FIXME - we need to add code here to detect a totally new
3502 * configuration, reset the AP, unassoc, rxon timing, assoc,
3503 * clear sta table, add BCAST sta... */
3504}
3505
bb8c093b 3506static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB
3507 struct ieee80211_vif *vif,
3508 struct ieee80211_sta *sta,
3509 struct ieee80211_key_conf *key)
b481de9c 3510{
4a8a4322 3511 struct iwl_priv *priv = hw->priv;
dc822b5d 3512 const u8 *addr;
6e21f15c
AK
3513 int ret = 0;
3514 u8 sta_id = IWL_INVALID_STATION;
3515 u8 static_key;
b481de9c 3516
e1623446 3517 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3518
df878d8f 3519 if (iwl3945_mod_params.sw_crypto) {
e1623446 3520 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY
3521 return -EOPNOTSUPP;
3522 }
3523
42986796 3524 addr = sta ? sta->addr : iwl_bcast_addr;
6e21f15c
AK
3525 static_key = !iwl_is_associated(priv);
3526
3527 if (!static_key) {
40ace5b3 3528 sta_id = priv->cfg->ops->smgmt->find_station(priv, addr);
6e21f15c 3529 if (sta_id == IWL_INVALID_STATION) {
12514396 3530 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
6e21f15c
AK
3531 addr);
3532 return -EINVAL;
3533 }
b481de9c
ZY
3534 }
3535
3536 mutex_lock(&priv->mutex);
af0053d6 3537 iwl_scan_cancel_timeout(priv, 100);
6e21f15c 3538 mutex_unlock(&priv->mutex);
15e869d8 3539
b481de9c 3540 switch (cmd) {
6e21f15c
AK
3541 case SET_KEY:
3542 if (static_key)
3543 ret = iwl3945_set_static_key(priv, key);
3544 else
3545 ret = iwl3945_set_dynamic_key(priv, key, sta_id);
3546 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY
3547 break;
3548 case DISABLE_KEY:
6e21f15c
AK
3549 if (static_key)
3550 ret = iwl3945_remove_static_key(priv);
3551 else
3552 ret = iwl3945_clear_sta_key_info(priv, sta_id);
3553 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY
3554 break;
3555 default:
42986796 3556 ret = -EINVAL;
b481de9c
ZY
3557 }
3558
e1623446 3559 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 3560
42986796 3561 return ret;
b481de9c
ZY
3562}
3563
b481de9c
ZY
3564/*****************************************************************************
3565 *
3566 * sysfs attributes
3567 *
3568 *****************************************************************************/
3569
d08853a3 3570#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
3571
3572/*
3573 * The following adds a new attribute to the sysfs representation
3574 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
3575 * used for controlling the debug level.
3576 *
3577 * See the level definitions in iwl for details.
3578 */
40b8ec0b
SO
3579static ssize_t show_debug_level(struct device *d,
3580 struct device_attribute *attr, char *buf)
b481de9c 3581{
928841b1 3582 struct iwl_priv *priv = dev_get_drvdata(d);
40b8ec0b
SO
3583
3584 return sprintf(buf, "0x%08X\n", priv->debug_level);
b481de9c 3585}
40b8ec0b
SO
3586static ssize_t store_debug_level(struct device *d,
3587 struct device_attribute *attr,
b481de9c
ZY
3588 const char *buf, size_t count)
3589{
928841b1 3590 struct iwl_priv *priv = dev_get_drvdata(d);
40b8ec0b
SO
3591 unsigned long val;
3592 int ret;
b481de9c 3593
40b8ec0b
SO
3594 ret = strict_strtoul(buf, 0, &val);
3595 if (ret)
978785a3 3596 IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf);
b481de9c 3597 else
40b8ec0b 3598 priv->debug_level = val;
b481de9c
ZY
3599
3600 return strnlen(buf, count);
3601}
3602
40b8ec0b
SO
3603static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
3604 show_debug_level, store_debug_level);
b481de9c 3605
d08853a3 3606#endif /* CONFIG_IWLWIFI_DEBUG */
b481de9c 3607
b481de9c
ZY
3608static ssize_t show_temperature(struct device *d,
3609 struct device_attribute *attr, char *buf)
3610{
928841b1 3611 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3612
775a6e27 3613 if (!iwl_is_alive(priv))
b481de9c
ZY
3614 return -EAGAIN;
3615
bb8c093b 3616 return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
b481de9c
ZY
3617}
3618
3619static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
3620
b481de9c
ZY
3621static ssize_t show_tx_power(struct device *d,
3622 struct device_attribute *attr, char *buf)
3623{
928841b1 3624 struct iwl_priv *priv = dev_get_drvdata(d);
62ea9c5b 3625 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
b481de9c
ZY
3626}
3627
3628static ssize_t store_tx_power(struct device *d,
3629 struct device_attribute *attr,
3630 const char *buf, size_t count)
3631{
928841b1 3632 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3633 char *p = (char *)buf;
3634 u32 val;
3635
3636 val = simple_strtoul(p, &p, 10);
3637 if (p == buf)
978785a3 3638 IWL_INFO(priv, ": %s is not in decimal form.\n", buf);
b481de9c 3639 else
bb8c093b 3640 iwl3945_hw_reg_set_txpower(priv, val);
b481de9c
ZY
3641
3642 return count;
3643}
3644
3645static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
3646
3647static ssize_t show_flags(struct device *d,
3648 struct device_attribute *attr, char *buf)
3649{
928841b1 3650 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3651
8ccde88a 3652 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
b481de9c
ZY
3653}
3654
3655static ssize_t store_flags(struct device *d,
3656 struct device_attribute *attr,
3657 const char *buf, size_t count)
3658{
928841b1 3659 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3660 u32 flags = simple_strtoul(buf, NULL, 0);
3661
3662 mutex_lock(&priv->mutex);
8ccde88a 3663 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
b481de9c 3664 /* Cancel any currently running scans... */
af0053d6 3665 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 3666 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 3667 else {
e1623446 3668 IWL_DEBUG_INFO(priv, "Committing rxon.flags = 0x%04X\n",
b481de9c 3669 flags);
8ccde88a 3670 priv->staging_rxon.flags = cpu_to_le32(flags);
e0158e61 3671 iwlcore_commit_rxon(priv);
b481de9c
ZY
3672 }
3673 }
3674 mutex_unlock(&priv->mutex);
3675
3676 return count;
3677}
3678
3679static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
3680
3681static ssize_t show_filter_flags(struct device *d,
3682 struct device_attribute *attr, char *buf)
3683{
928841b1 3684 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3685
3686 return sprintf(buf, "0x%04X\n",
8ccde88a 3687 le32_to_cpu(priv->active_rxon.filter_flags));
b481de9c
ZY
3688}
3689
3690static ssize_t store_filter_flags(struct device *d,
3691 struct device_attribute *attr,
3692 const char *buf, size_t count)
3693{
928841b1 3694 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3695 u32 filter_flags = simple_strtoul(buf, NULL, 0);
3696
3697 mutex_lock(&priv->mutex);
8ccde88a 3698 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
b481de9c 3699 /* Cancel any currently running scans... */
af0053d6 3700 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 3701 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 3702 else {
e1623446 3703 IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
b481de9c 3704 "0x%04X\n", filter_flags);
8ccde88a 3705 priv->staging_rxon.filter_flags =
b481de9c 3706 cpu_to_le32(filter_flags);
e0158e61 3707 iwlcore_commit_rxon(priv);
b481de9c
ZY
3708 }
3709 }
3710 mutex_unlock(&priv->mutex);
3711
3712 return count;
3713}
3714
3715static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
3716 store_filter_flags);
3717
c8b0e6e1 3718#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY
3719
3720static ssize_t show_measurement(struct device *d,
3721 struct device_attribute *attr, char *buf)
3722{
4a8a4322 3723 struct iwl_priv *priv = dev_get_drvdata(d);
600c0e11 3724 struct iwl_spectrum_notification measure_report;
b481de9c 3725 u32 size = sizeof(measure_report), len = 0, ofs = 0;
3ac7f146 3726 u8 *data = (u8 *)&measure_report;
b481de9c
ZY
3727 unsigned long flags;
3728
3729 spin_lock_irqsave(&priv->lock, flags);
3730 if (!(priv->measurement_status & MEASUREMENT_READY)) {
3731 spin_unlock_irqrestore(&priv->lock, flags);
3732 return 0;
3733 }
3734 memcpy(&measure_report, &priv->measure_report, size);
3735 priv->measurement_status = 0;
3736 spin_unlock_irqrestore(&priv->lock, flags);
3737
3738 while (size && (PAGE_SIZE - len)) {
3739 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3740 PAGE_SIZE - len, 1);
3741 len = strlen(buf);
3742 if (PAGE_SIZE - len)
3743 buf[len++] = '\n';
3744
3745 ofs += 16;
3746 size -= min(size, 16U);
3747 }
3748
3749 return len;
3750}
3751
3752static ssize_t store_measurement(struct device *d,
3753 struct device_attribute *attr,
3754 const char *buf, size_t count)
3755{
4a8a4322 3756 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3757 struct ieee80211_measurement_params params = {
8ccde88a 3758 .channel = le16_to_cpu(priv->active_rxon.channel),
b481de9c
ZY
3759 .start_time = cpu_to_le64(priv->last_tsf),
3760 .duration = cpu_to_le16(1),
3761 };
3762 u8 type = IWL_MEASURE_BASIC;
3763 u8 buffer[32];
3764 u8 channel;
3765
3766 if (count) {
3767 char *p = buffer;
3768 strncpy(buffer, buf, min(sizeof(buffer), count));
3769 channel = simple_strtoul(p, NULL, 0);
3770 if (channel)
3771 params.channel = channel;
3772
3773 p = buffer;
3774 while (*p && *p != ' ')
3775 p++;
3776 if (*p)
3777 type = simple_strtoul(p + 1, NULL, 0);
3778 }
3779
e1623446 3780 IWL_DEBUG_INFO(priv, "Invoking measurement of type %d on "
b481de9c 3781 "channel %d (for '%s')\n", type, params.channel, buf);
bb8c093b 3782 iwl3945_get_measurement(priv, &params, type);
b481de9c
ZY
3783
3784 return count;
3785}
3786
3787static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
3788 show_measurement, store_measurement);
c8b0e6e1 3789#endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
b481de9c 3790
b481de9c
ZY
3791static ssize_t store_retry_rate(struct device *d,
3792 struct device_attribute *attr,
3793 const char *buf, size_t count)
3794{
4a8a4322 3795 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3796
3797 priv->retry_rate = simple_strtoul(buf, NULL, 0);
3798 if (priv->retry_rate <= 0)
3799 priv->retry_rate = 1;
3800
3801 return count;
3802}
3803
3804static ssize_t show_retry_rate(struct device *d,
3805 struct device_attribute *attr, char *buf)
3806{
4a8a4322 3807 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3808 return sprintf(buf, "%d", priv->retry_rate);
3809}
3810
3811static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
3812 store_retry_rate);
3813
d25aabb0 3814
b481de9c
ZY
3815static ssize_t store_power_level(struct device *d,
3816 struct device_attribute *attr,
3817 const char *buf, size_t count)
3818{
4a8a4322 3819 struct iwl_priv *priv = dev_get_drvdata(d);
d25aabb0
WT
3820 int ret;
3821 unsigned long mode;
3822
b481de9c 3823
b481de9c
ZY
3824 mutex_lock(&priv->mutex);
3825
d25aabb0
WT
3826 ret = strict_strtoul(buf, 10, &mode);
3827 if (ret)
3828 goto out;
b481de9c 3829
d25aabb0
WT
3830 ret = iwl_power_set_user_mode(priv, mode);
3831 if (ret) {
3832 IWL_DEBUG_MAC80211(priv, "failed setting power mode.\n");
3833 goto out;
b481de9c 3834 }
d25aabb0 3835 ret = count;
b481de9c
ZY
3836
3837 out:
3838 mutex_unlock(&priv->mutex);
d25aabb0 3839 return ret;
b481de9c
ZY
3840}
3841
d25aabb0
WT
3842static ssize_t show_power_level(struct device *d,
3843 struct device_attribute *attr, char *buf)
3844{
3845 struct iwl_priv *priv = dev_get_drvdata(d);
3846 int mode = priv->power_data.user_power_setting;
d25aabb0
WT
3847 int level = priv->power_data.power_mode;
3848 char *p = buf;
3849
7af2c460
JB
3850 p += sprintf(p, "INDEX:%d\t", level);
3851 p += sprintf(p, "USER:%d\n", mode);
d25aabb0
WT
3852 return p - buf + 1;
3853}
3854
3855static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR,
3856 show_power_level, store_power_level);
3857
b481de9c
ZY
3858#define MAX_WX_STRING 80
3859
3860/* Values are in microsecond */
3861static const s32 timeout_duration[] = {
3862 350000,
3863 250000,
3864 75000,
3865 37000,
3866 25000,
3867};
3868static const s32 period_duration[] = {
3869 400000,
3870 700000,
3871 1000000,
3872 1000000,
3873 1000000
3874};
3875
b481de9c
ZY
3876static ssize_t show_channels(struct device *d,
3877 struct device_attribute *attr, char *buf)
3878{
8318d78a
JB
3879 /* all this shit doesn't belong into sysfs anyway */
3880 return 0;
b481de9c
ZY
3881}
3882
3883static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
3884
3885static ssize_t show_statistics(struct device *d,
3886 struct device_attribute *attr, char *buf)
3887{
4a8a4322 3888 struct iwl_priv *priv = dev_get_drvdata(d);
bb8c093b 3889 u32 size = sizeof(struct iwl3945_notif_statistics);
b481de9c 3890 u32 len = 0, ofs = 0;
f2c7e521 3891 u8 *data = (u8 *)&priv->statistics_39;
b481de9c
ZY
3892 int rc = 0;
3893
775a6e27 3894 if (!iwl_is_alive(priv))
b481de9c
ZY
3895 return -EAGAIN;
3896
3897 mutex_lock(&priv->mutex);
17f841cd 3898 rc = iwl_send_statistics_request(priv, 0);
b481de9c
ZY
3899 mutex_unlock(&priv->mutex);
3900
3901 if (rc) {
3902 len = sprintf(buf,
3903 "Error sending statistics request: 0x%08X\n", rc);
3904 return len;
3905 }
3906
3907 while (size && (PAGE_SIZE - len)) {
3908 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3909 PAGE_SIZE - len, 1);
3910 len = strlen(buf);
3911 if (PAGE_SIZE - len)
3912 buf[len++] = '\n';
3913
3914 ofs += 16;
3915 size -= min(size, 16U);
3916 }
3917
3918 return len;
3919}
3920
3921static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
3922
3923static ssize_t show_antenna(struct device *d,
3924 struct device_attribute *attr, char *buf)
3925{
4a8a4322 3926 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3927
775a6e27 3928 if (!iwl_is_alive(priv))
b481de9c
ZY
3929 return -EAGAIN;
3930
7e4bca5e 3931 return sprintf(buf, "%d\n", iwl3945_mod_params.antenna);
b481de9c
ZY
3932}
3933
3934static ssize_t store_antenna(struct device *d,
3935 struct device_attribute *attr,
3936 const char *buf, size_t count)
3937{
7530f85f 3938 struct iwl_priv *priv __maybe_unused = dev_get_drvdata(d);
b481de9c 3939 int ant;
b481de9c
ZY
3940
3941 if (count == 0)
3942 return 0;
3943
3944 if (sscanf(buf, "%1i", &ant) != 1) {
e1623446 3945 IWL_DEBUG_INFO(priv, "not in hex or decimal form.\n");
b481de9c
ZY
3946 return count;
3947 }
3948
3949 if ((ant >= 0) && (ant <= 2)) {
e1623446 3950 IWL_DEBUG_INFO(priv, "Setting antenna select to %d.\n", ant);
7e4bca5e 3951 iwl3945_mod_params.antenna = (enum iwl3945_antenna)ant;
b481de9c 3952 } else
e1623446 3953 IWL_DEBUG_INFO(priv, "Bad antenna select value %d.\n", ant);
b481de9c
ZY
3954
3955
3956 return count;
3957}
3958
3959static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
3960
3961static ssize_t show_status(struct device *d,
3962 struct device_attribute *attr, char *buf)
3963{
928841b1 3964 struct iwl_priv *priv = dev_get_drvdata(d);
775a6e27 3965 if (!iwl_is_alive(priv))
b481de9c
ZY
3966 return -EAGAIN;
3967 return sprintf(buf, "0x%08x\n", (int)priv->status);
3968}
3969
3970static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
3971
3972static ssize_t dump_error_log(struct device *d,
3973 struct device_attribute *attr,
3974 const char *buf, size_t count)
3975{
928841b1 3976 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3977 char *p = (char *)buf;
3978
3979 if (p[0] == '1')
928841b1 3980 iwl3945_dump_nic_error_log(priv);
b481de9c
ZY
3981
3982 return strnlen(buf, count);
3983}
3984
3985static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
3986
3987static ssize_t dump_event_log(struct device *d,
3988 struct device_attribute *attr,
3989 const char *buf, size_t count)
3990{
928841b1 3991 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3992 char *p = (char *)buf;
3993
3994 if (p[0] == '1')
928841b1 3995 iwl3945_dump_nic_event_log(priv);
b481de9c
ZY
3996
3997 return strnlen(buf, count);
3998}
3999
4000static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
4001
4002/*****************************************************************************
4003 *
a96a27f9 4004 * driver setup and tear down
b481de9c
ZY
4005 *
4006 *****************************************************************************/
4007
4a8a4322 4008static void iwl3945_setup_deferred_work(struct iwl_priv *priv)
b481de9c 4009{
d21050c7 4010 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY
4011
4012 init_waitqueue_head(&priv->wait_command_queue);
4013
bb8c093b
CH
4014 INIT_WORK(&priv->up, iwl3945_bg_up);
4015 INIT_WORK(&priv->restart, iwl3945_bg_restart);
4016 INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
c0af96a6 4017 INIT_WORK(&priv->rf_kill, iwl_bg_rf_kill);
bb8c093b 4018 INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
bb8c093b
CH
4019 INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
4020 INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
2663516d 4021 INIT_DELAYED_WORK(&priv->rfkill_poll, iwl3945_rfkill_poll);
77fecfb8
SO
4022 INIT_WORK(&priv->scan_completed, iwl_bg_scan_completed);
4023 INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
4024 INIT_WORK(&priv->abort_scan, iwl_bg_abort_scan);
4025 INIT_DELAYED_WORK(&priv->scan_check, iwl_bg_scan_check);
bb8c093b
CH
4026
4027 iwl3945_hw_setup_deferred_work(priv);
b481de9c
ZY
4028
4029 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
bb8c093b 4030 iwl3945_irq_tasklet, (unsigned long)priv);
b481de9c
ZY
4031}
4032
4a8a4322 4033static void iwl3945_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 4034{
bb8c093b 4035 iwl3945_hw_cancel_deferred_work(priv);
b481de9c 4036
e47eb6ad 4037 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY
4038 cancel_delayed_work(&priv->scan_check);
4039 cancel_delayed_work(&priv->alive_start);
b481de9c
ZY
4040 cancel_work_sync(&priv->beacon_update);
4041}
4042
bb8c093b 4043static struct attribute *iwl3945_sysfs_entries[] = {
b481de9c
ZY
4044 &dev_attr_antenna.attr,
4045 &dev_attr_channels.attr,
4046 &dev_attr_dump_errors.attr,
4047 &dev_attr_dump_events.attr,
4048 &dev_attr_flags.attr,
4049 &dev_attr_filter_flags.attr,
c8b0e6e1 4050#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY
4051 &dev_attr_measurement.attr,
4052#endif
4053 &dev_attr_power_level.attr,
b481de9c 4054 &dev_attr_retry_rate.attr,
b481de9c
ZY
4055 &dev_attr_statistics.attr,
4056 &dev_attr_status.attr,
4057 &dev_attr_temperature.attr,
b481de9c 4058 &dev_attr_tx_power.attr,
d08853a3 4059#ifdef CONFIG_IWLWIFI_DEBUG
40b8ec0b
SO
4060 &dev_attr_debug_level.attr,
4061#endif
b481de9c
ZY
4062 NULL
4063};
4064
bb8c093b 4065static struct attribute_group iwl3945_attribute_group = {
b481de9c 4066 .name = NULL, /* put in device directory */
bb8c093b 4067 .attrs = iwl3945_sysfs_entries,
b481de9c
ZY
4068};
4069
bb8c093b
CH
4070static struct ieee80211_ops iwl3945_hw_ops = {
4071 .tx = iwl3945_mac_tx,
4072 .start = iwl3945_mac_start,
4073 .stop = iwl3945_mac_stop,
cbb6ab94 4074 .add_interface = iwl_mac_add_interface,
d8052319 4075 .remove_interface = iwl_mac_remove_interface,
4808368d 4076 .config = iwl_mac_config,
8ccde88a 4077 .configure_filter = iwl_configure_filter,
bb8c093b 4078 .set_key = iwl3945_mac_set_key,
aa89f31e 4079 .get_tx_stats = iwl_mac_get_tx_stats,
488829f1 4080 .conf_tx = iwl_mac_conf_tx,
bd564261 4081 .reset_tsf = iwl_mac_reset_tsf,
5bbe233b 4082 .bss_info_changed = iwl_bss_info_changed,
e9dde6f6 4083 .hw_scan = iwl_mac_hw_scan
b481de9c
ZY
4084};
4085
e52119c5 4086static int iwl3945_init_drv(struct iwl_priv *priv)
90a30a02
KA
4087{
4088 int ret;
e6148917 4089 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
90a30a02
KA
4090
4091 priv->retry_rate = 1;
4092 priv->ibss_beacon = NULL;
4093
4094 spin_lock_init(&priv->lock);
90a30a02
KA
4095 spin_lock_init(&priv->sta_lock);
4096 spin_lock_init(&priv->hcmd_lock);
4097
4098 INIT_LIST_HEAD(&priv->free_frames);
4099
4100 mutex_init(&priv->mutex);
4101
4102 /* Clear the driver's (not device's) station table */
40ace5b3 4103 priv->cfg->ops->smgmt->clear_station_table(priv);
90a30a02
KA
4104
4105 priv->data_retry_limit = -1;
4106 priv->ieee_channels = NULL;
4107 priv->ieee_rates = NULL;
4108 priv->band = IEEE80211_BAND_2GHZ;
4109
4110 priv->iw_mode = NL80211_IFTYPE_STATION;
4111
4112 iwl_reset_qos(priv);
4113
4114 priv->qos_data.qos_active = 0;
4115 priv->qos_data.qos_cap.val = 0;
4116
4117 priv->rates_mask = IWL_RATES_MASK;
d25aabb0
WT
4118 /* If power management is turned on, default to CAM mode */
4119 priv->power_mode = IWL_POWER_MODE_CAM;
62ea9c5b 4120 priv->tx_power_user_lmt = IWL_DEFAULT_TX_POWER;
90a30a02 4121
e6148917
SO
4122 if (eeprom->version < EEPROM_3945_EEPROM_VERSION) {
4123 IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n",
4124 eeprom->version);
4125 ret = -EINVAL;
4126 goto err;
4127 }
4128 ret = iwl_init_channel_map(priv);
90a30a02
KA
4129 if (ret) {
4130 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
4131 goto err;
4132 }
4133
e6148917
SO
4134 /* Set up txpower settings in driver for all channels */
4135 if (iwl3945_txpower_set_from_eeprom(priv)) {
4136 ret = -EIO;
4137 goto err_free_channel_map;
4138 }
4139
534166de 4140 ret = iwlcore_init_geos(priv);
90a30a02
KA
4141 if (ret) {
4142 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
4143 goto err_free_channel_map;
4144 }
534166de
SO
4145 iwl3945_init_hw_rates(priv, priv->ieee_rates);
4146
2a4ddaab
AK
4147 return 0;
4148
4149err_free_channel_map:
4150 iwl_free_channel_map(priv);
4151err:
4152 return ret;
4153}
4154
4155static int iwl3945_setup_mac(struct iwl_priv *priv)
4156{
4157 int ret;
4158 struct ieee80211_hw *hw = priv->hw;
4159
4160 hw->rate_control_algorithm = "iwl-3945-rs";
4161 hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
4162
4163 /* Tell mac80211 our characteristics */
4164 hw->flags = IEEE80211_HW_SIGNAL_DBM |
b1c6019b
MA
4165 IEEE80211_HW_NOISE_DBM |
4166 IEEE80211_HW_SPECTRUM_MGMT;
2a4ddaab
AK
4167
4168 hw->wiphy->interface_modes =
4169 BIT(NL80211_IFTYPE_STATION) |
4170 BIT(NL80211_IFTYPE_ADHOC);
4171
4172 hw->wiphy->custom_regulatory = true;
4173
1ecf9fc1
JB
4174 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX_3945;
4175 /* we create the 802.11 header and a zero-length SSID element */
4176 hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
d60cc91a 4177
2a4ddaab
AK
4178 /* Default value; 4 EDCA QOS priorities */
4179 hw->queues = 4;
4180
534166de
SO
4181 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
4182 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
4183 &priv->bands[IEEE80211_BAND_2GHZ];
2a4ddaab 4184
534166de
SO
4185 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
4186 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
4187 &priv->bands[IEEE80211_BAND_5GHZ];
90a30a02 4188
2a4ddaab
AK
4189 ret = ieee80211_register_hw(priv->hw);
4190 if (ret) {
4191 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
4192 return ret;
4193 }
4194 priv->mac80211_registered = 1;
90a30a02 4195
2a4ddaab 4196 return 0;
90a30a02
KA
4197}
4198
bb8c093b 4199static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY
4200{
4201 int err = 0;
4a8a4322 4202 struct iwl_priv *priv;
b481de9c 4203 struct ieee80211_hw *hw;
c0f20d91 4204 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
e6148917 4205 struct iwl3945_eeprom *eeprom;
0359facc 4206 unsigned long flags;
b481de9c 4207
cee53ddb
KA
4208 /***********************
4209 * 1. Allocating HW data
4210 * ********************/
4211
b481de9c
ZY
4212 /* mac80211 allocates memory for this device instance, including
4213 * space for this driver's private structure */
90a30a02 4214 hw = iwl_alloc_all(cfg, &iwl3945_hw_ops);
b481de9c 4215 if (hw == NULL) {
a3139c59 4216 printk(KERN_ERR DRV_NAME "Can not allocate network device\n");
b481de9c
ZY
4217 err = -ENOMEM;
4218 goto out;
4219 }
b481de9c 4220 priv = hw->priv;
90a30a02 4221 SET_IEEE80211_DEV(hw, &pdev->dev);
6440adb5 4222
df878d8f
KA
4223 if ((iwl3945_mod_params.num_of_queues > IWL39_MAX_NUM_QUEUES) ||
4224 (iwl3945_mod_params.num_of_queues < IWL_MIN_NUM_QUEUES)) {
15b1687c
WT
4225 IWL_ERR(priv,
4226 "invalid queues_num, should be between %d and %d\n",
4227 IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES);
a3139c59 4228 err = -EINVAL;
c8f16138 4229 goto out_ieee80211_free_hw;
a3139c59
SO
4230 }
4231
90a30a02
KA
4232 /*
4233 * Disabling hardware scan means that mac80211 will perform scans
4234 * "the hard way", rather than using device's scan.
4235 */
df878d8f 4236 if (iwl3945_mod_params.disable_hw_scan) {
e1623446 4237 IWL_DEBUG_INFO(priv, "Disabling hw_scan\n");
40b8ec0b
SO
4238 iwl3945_hw_ops.hw_scan = NULL;
4239 }
4240
90a30a02 4241
e1623446 4242 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
90a30a02
KA
4243 priv->cfg = cfg;
4244 priv->pci_dev = pdev;
cee53ddb 4245
d08853a3 4246#ifdef CONFIG_IWLWIFI_DEBUG
df878d8f 4247 priv->debug_level = iwl3945_mod_params.debug;
b481de9c
ZY
4248 atomic_set(&priv->restrict_refcnt, 0);
4249#endif
b481de9c 4250
cee53ddb
KA
4251 /***************************
4252 * 2. Initializing PCI bus
4253 * *************************/
b481de9c
ZY
4254 if (pci_enable_device(pdev)) {
4255 err = -ENODEV;
4256 goto out_ieee80211_free_hw;
4257 }
4258
4259 pci_set_master(pdev);
4260
284901a9 4261 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
b481de9c 4262 if (!err)
284901a9 4263 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
b481de9c 4264 if (err) {
978785a3 4265 IWL_WARN(priv, "No suitable DMA available.\n");
b481de9c
ZY
4266 goto out_pci_disable_device;
4267 }
4268
4269 pci_set_drvdata(pdev, priv);
4270 err = pci_request_regions(pdev, DRV_NAME);
4271 if (err)
4272 goto out_pci_disable_device;
6440adb5 4273
cee53ddb
KA
4274 /***********************
4275 * 3. Read REV Register
4276 * ********************/
b481de9c
ZY
4277 priv->hw_base = pci_iomap(pdev, 0, 0);
4278 if (!priv->hw_base) {
4279 err = -ENODEV;
4280 goto out_pci_release_regions;
4281 }
4282
e1623446 4283 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
b481de9c 4284 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 4285 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
b481de9c 4286
cee53ddb
KA
4287 /* We disable the RETRY_TIMEOUT register (0x41) to keep
4288 * PCI Tx retries from interfering with C3 CPU state */
4289 pci_write_config_byte(pdev, 0x41, 0x00);
b481de9c 4290
90a30a02
KA
4291 /* amp init */
4292 err = priv->cfg->ops->lib->apm_ops.init(priv);
cee53ddb 4293 if (err < 0) {
d5df2a16 4294 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
90a30a02 4295 goto out_iounmap;
cee53ddb 4296 }
b481de9c 4297
cee53ddb
KA
4298 /***********************
4299 * 4. Read EEPROM
4300 * ********************/
90a30a02 4301
cee53ddb 4302 /* Read the EEPROM */
e6148917 4303 err = iwl_eeprom_init(priv);
cee53ddb 4304 if (err) {
15b1687c 4305 IWL_ERR(priv, "Unable to init EEPROM\n");
c8f16138 4306 goto out_iounmap;
cee53ddb
KA
4307 }
4308 /* MAC Address location in EEPROM same for 3945/4965 */
e6148917
SO
4309 eeprom = (struct iwl3945_eeprom *)priv->eeprom;
4310 memcpy(priv->mac_addr, eeprom->mac_address, ETH_ALEN);
e1623446 4311 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
cee53ddb 4312 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
b481de9c 4313
cee53ddb
KA
4314 /***********************
4315 * 5. Setup HW Constants
4316 * ********************/
b481de9c 4317 /* Device-specific setup */
3832ec9d 4318 if (iwl3945_hw_set_hw_params(priv)) {
15b1687c 4319 IWL_ERR(priv, "failed to set hw settings\n");
c8f16138 4320 goto out_eeprom_free;
b481de9c
ZY
4321 }
4322
cee53ddb
KA
4323 /***********************
4324 * 6. Setup priv
4325 * ********************/
cee53ddb 4326
90a30a02 4327 err = iwl3945_init_drv(priv);
b481de9c 4328 if (err) {
90a30a02 4329 IWL_ERR(priv, "initializing driver failed\n");
c8f16138 4330 goto out_unset_hw_params;
b481de9c
ZY
4331 }
4332
978785a3
TW
4333 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n",
4334 priv->cfg->name);
cee53ddb 4335
cee53ddb 4336 /***********************
09f9bf79 4337 * 7. Setup Services
cee53ddb
KA
4338 * ********************/
4339
4340 spin_lock_irqsave(&priv->lock, flags);
ed3b932e 4341 iwl_disable_interrupts(priv);
cee53ddb
KA
4342 spin_unlock_irqrestore(&priv->lock, flags);
4343
2663516d
HS
4344 pci_enable_msi(priv->pci_dev);
4345
f17d08a6 4346 err = request_irq(priv->pci_dev->irq, iwl_isr, IRQF_SHARED,
2663516d
HS
4347 DRV_NAME, priv);
4348 if (err) {
4349 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4350 goto out_disable_msi;
4351 }
4352
cee53ddb 4353 err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
849e0dce 4354 if (err) {
15b1687c 4355 IWL_ERR(priv, "failed to create sysfs device attributes\n");
90a30a02 4356 goto out_release_irq;
849e0dce 4357 }
849e0dce 4358
8ccde88a
SO
4359 iwl_set_rxon_channel(priv,
4360 &priv->bands[IEEE80211_BAND_2GHZ].channels[5]);
cee53ddb
KA
4361 iwl3945_setup_deferred_work(priv);
4362 iwl3945_setup_rx_handlers(priv);
4363
cee53ddb 4364 /*********************************
09f9bf79 4365 * 8. Setup and Register mac80211
cee53ddb
KA
4366 * *******************************/
4367
2a4ddaab 4368 iwl_enable_interrupts(priv);
b481de9c 4369
2a4ddaab
AK
4370 err = iwl3945_setup_mac(priv);
4371 if (err)
4372 goto out_remove_sysfs;
cee53ddb 4373
a75fbe8d
AK
4374 err = iwl_dbgfs_register(priv, DRV_NAME);
4375 if (err)
4376 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
4377
c0af96a6 4378 err = iwl_rfkill_init(priv);
ebef2008 4379 if (err)
15b1687c 4380 IWL_ERR(priv, "Unable to initialize RFKILL system. "
ebef2008 4381 "Ignoring error: %d\n", err);
2a4ddaab
AK
4382 else
4383 iwl_rfkill_set_hw_state(priv);
ebef2008 4384
2663516d
HS
4385 /* Start monitoring the killswitch */
4386 queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
4387 2 * HZ);
4388
b481de9c
ZY
4389 return 0;
4390
cee53ddb 4391 out_remove_sysfs:
c8f16138
RC
4392 destroy_workqueue(priv->workqueue);
4393 priv->workqueue = NULL;
cee53ddb 4394 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 4395 out_release_irq:
2663516d 4396 free_irq(priv->pci_dev->irq, priv);
2663516d
HS
4397 out_disable_msi:
4398 pci_disable_msi(priv->pci_dev);
c8f16138
RC
4399 iwlcore_free_geos(priv);
4400 iwl_free_channel_map(priv);
4401 out_unset_hw_params:
4402 iwl3945_unset_hw_params(priv);
4403 out_eeprom_free:
4404 iwl_eeprom_free(priv);
b481de9c
ZY
4405 out_iounmap:
4406 pci_iounmap(pdev, priv->hw_base);
4407 out_pci_release_regions:
4408 pci_release_regions(pdev);
4409 out_pci_disable_device:
b481de9c 4410 pci_set_drvdata(pdev, NULL);
623d563e 4411 pci_disable_device(pdev);
b481de9c
ZY
4412 out_ieee80211_free_hw:
4413 ieee80211_free_hw(priv->hw);
4414 out:
4415 return err;
4416}
4417
c83dbf68 4418static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
b481de9c 4419{
4a8a4322 4420 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 4421 unsigned long flags;
b481de9c
ZY
4422
4423 if (!priv)
4424 return;
4425
e1623446 4426 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 4427
a75fbe8d
AK
4428 iwl_dbgfs_unregister(priv);
4429
b481de9c 4430 set_bit(STATUS_EXIT_PENDING, &priv->status);
b24d22b1 4431
d552bfb6
KA
4432 if (priv->mac80211_registered) {
4433 ieee80211_unregister_hw(priv->hw);
4434 priv->mac80211_registered = 0;
4435 } else {
4436 iwl3945_down(priv);
4437 }
b481de9c 4438
0359facc
MA
4439 /* make sure we flush any pending irq or
4440 * tasklet for the driver
4441 */
4442 spin_lock_irqsave(&priv->lock, flags);
ed3b932e 4443 iwl_disable_interrupts(priv);
0359facc
MA
4444 spin_unlock_irqrestore(&priv->lock, flags);
4445
4446 iwl_synchronize_irq(priv);
4447
bb8c093b 4448 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 4449
c0af96a6 4450 iwl_rfkill_unregister(priv);
71d449b5 4451 cancel_delayed_work_sync(&priv->rfkill_poll);
2663516d 4452
bb8c093b 4453 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY
4454
4455 if (priv->rxq.bd)
df833b1d 4456 iwl3945_rx_queue_free(priv, &priv->rxq);
bb8c093b 4457 iwl3945_hw_txq_ctx_free(priv);
b481de9c 4458
3832ec9d 4459 iwl3945_unset_hw_params(priv);
40ace5b3 4460 priv->cfg->ops->smgmt->clear_station_table(priv);
b481de9c 4461
6ef89d0a
MA
4462 /*netif_stop_queue(dev); */
4463 flush_workqueue(priv->workqueue);
4464
bb8c093b 4465 /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
b481de9c
ZY
4466 * priv->workqueue... so we can't take down the workqueue
4467 * until now... */
4468 destroy_workqueue(priv->workqueue);
4469 priv->workqueue = NULL;
4470
2663516d
HS
4471 free_irq(pdev->irq, priv);
4472 pci_disable_msi(pdev);
4473
b481de9c
ZY
4474 pci_iounmap(pdev, priv->hw_base);
4475 pci_release_regions(pdev);
4476 pci_disable_device(pdev);
4477 pci_set_drvdata(pdev, NULL);
4478
e6148917 4479 iwl_free_channel_map(priv);
534166de 4480 iwlcore_free_geos(priv);
805cee5b 4481 kfree(priv->scan);
b481de9c
ZY
4482 if (priv->ibss_beacon)
4483 dev_kfree_skb(priv->ibss_beacon);
4484
4485 ieee80211_free_hw(priv->hw);
4486}
4487
b481de9c
ZY
4488
4489/*****************************************************************************
4490 *
4491 * driver and module entry point
4492 *
4493 *****************************************************************************/
4494
bb8c093b 4495static struct pci_driver iwl3945_driver = {
b481de9c 4496 .name = DRV_NAME,
bb8c093b
CH
4497 .id_table = iwl3945_hw_card_ids,
4498 .probe = iwl3945_pci_probe,
4499 .remove = __devexit_p(iwl3945_pci_remove),
b481de9c 4500#ifdef CONFIG_PM
6da3a13e
WYG
4501 .suspend = iwl_pci_suspend,
4502 .resume = iwl_pci_resume,
b481de9c
ZY
4503#endif
4504};
4505
bb8c093b 4506static int __init iwl3945_init(void)
b481de9c
ZY
4507{
4508
4509 int ret;
4510 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
4511 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2
RC
4512
4513 ret = iwl3945_rate_control_register();
4514 if (ret) {
a3139c59
SO
4515 printk(KERN_ERR DRV_NAME
4516 "Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC
4517 return ret;
4518 }
4519
bb8c093b 4520 ret = pci_register_driver(&iwl3945_driver);
b481de9c 4521 if (ret) {
a3139c59 4522 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
897e1cf2 4523 goto error_register;
b481de9c 4524 }
b481de9c
ZY
4525
4526 return ret;
897e1cf2 4527
897e1cf2
RC
4528error_register:
4529 iwl3945_rate_control_unregister();
4530 return ret;
b481de9c
ZY
4531}
4532
bb8c093b 4533static void __exit iwl3945_exit(void)
b481de9c 4534{
bb8c093b 4535 pci_unregister_driver(&iwl3945_driver);
897e1cf2 4536 iwl3945_rate_control_unregister();
b481de9c
ZY
4537}
4538
a0987a8d 4539MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
25cb6cad 4540
df878d8f 4541module_param_named(antenna, iwl3945_mod_params.antenna, int, 0444);
b481de9c 4542MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
9c74d9fb
SO
4543module_param_named(swcrypto, iwl3945_mod_params.sw_crypto, int, 0444);
4544MODULE_PARM_DESC(swcrypto,
4545 "using software crypto (default 1 [software])\n");
df878d8f 4546module_param_named(debug, iwl3945_mod_params.debug, uint, 0444);
b481de9c 4547MODULE_PARM_DESC(debug, "debug output mask");
df878d8f 4548module_param_named(disable_hw_scan, iwl3945_mod_params.disable_hw_scan, int, 0444);
b481de9c
ZY
4549MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
4550
df878d8f 4551module_param_named(queues_num, iwl3945_mod_params.num_of_queues, int, 0444);
b481de9c
ZY
4552MODULE_PARM_DESC(queues_num, "number of hw queues.");
4553
af48d048
SO
4554module_param_named(fw_restart3945, iwl3945_mod_params.restart_fw, int, 0444);
4555MODULE_PARM_DESC(fw_restart3945, "restart firmware in case of error");
4556
bb8c093b
CH
4557module_exit(iwl3945_exit);
4558module_init(iwl3945_init);
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