iwlwifi: rename ibss_beacon variable
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl3945-base.c
CommitLineData
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1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
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4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
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26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
c96c31e4
JP
30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
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32#include <linux/kernel.h>
33#include <linux/module.h>
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34#include <linux/init.h>
35#include <linux/pci.h>
1a7123cd 36#include <linux/pci-aspm.h>
5a0e3ad6 37#include <linux/slab.h>
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38#include <linux/dma-mapping.h>
39#include <linux/delay.h>
d43c36dc 40#include <linux/sched.h>
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41#include <linux/skbuff.h>
42#include <linux/netdevice.h>
43#include <linux/wireless.h>
44#include <linux/firmware.h>
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45#include <linux/etherdevice.h>
46#include <linux/if_arp.h>
47
48#include <net/ieee80211_radiotap.h>
49#include <net/mac80211.h>
50
51#include <asm/div64.h>
52
a3139c59
SO
53#define DRV_NAME "iwl3945"
54
dbb6654c
WT
55#include "iwl-fh.h"
56#include "iwl-3945-fh.h"
600c0e11 57#include "iwl-commands.h"
17f841cd 58#include "iwl-sta.h"
b481de9c 59#include "iwl-3945.h"
5747d47f 60#include "iwl-core.h"
4a6547c7 61#include "iwl-helpers.h"
d20b3c65 62#include "iwl-dev.h"
81963d68 63#include "iwl-spectrum.h"
b481de9c 64
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65/*
66 * module name, copyright, version, etc.
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67 */
68
69#define DRV_DESCRIPTION \
70"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
71
d08853a3 72#ifdef CONFIG_IWLWIFI_DEBUG
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73#define VD "d"
74#else
75#define VD
76#endif
77
81963d68
RC
78/*
79 * add "s" to indicate spectrum measurement included.
80 * we add it here to be consistent with previous releases in which
81 * this was configurable.
82 */
83#define DRV_VERSION IWLWIFI_VERSION VD "s"
1f447808 84#define DRV_COPYRIGHT "Copyright(c) 2003-2010 Intel Corporation"
a7b75207 85#define DRV_AUTHOR "<ilw@linux.intel.com>"
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86
87MODULE_DESCRIPTION(DRV_DESCRIPTION);
88MODULE_VERSION(DRV_VERSION);
a7b75207 89MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
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90MODULE_LICENSE("GPL");
91
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92 /* module parameters */
93struct iwl_mod_params iwl3945_mod_params = {
9c74d9fb 94 .sw_crypto = 1,
af48d048 95 .restart_fw = 1,
df878d8f
KA
96 /* the rest are 0 by default */
97};
98
7e4bca5e
SO
99/**
100 * iwl3945_get_antenna_flags - Get antenna flags for RXON command
101 * @priv: eeprom and antenna fields are used to determine antenna flags
102 *
103 * priv->eeprom39 is used to determine if antenna AUX/MAIN are reversed
104 * iwl3945_mod_params.antenna specifies the antenna diversity mode:
105 *
106 * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
107 * IWL_ANTENNA_MAIN - Force MAIN antenna
108 * IWL_ANTENNA_AUX - Force AUX antenna
109 */
110__le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv)
111{
112 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
113
114 switch (iwl3945_mod_params.antenna) {
115 case IWL_ANTENNA_DIVERSITY:
116 return 0;
117
118 case IWL_ANTENNA_MAIN:
119 if (eeprom->antenna_switch_type)
120 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
121 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
122
123 case IWL_ANTENNA_AUX:
124 if (eeprom->antenna_switch_type)
125 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
126 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
127 }
128
129 /* bad antenna selector value */
130 IWL_ERR(priv, "Bad antenna selector value (0x%x)\n",
131 iwl3945_mod_params.antenna);
132
133 return 0; /* "diversity" is default if error */
134}
135
6e21f15c 136static int iwl3945_set_ccmp_dynamic_key_info(struct iwl_priv *priv,
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137 struct ieee80211_key_conf *keyconf,
138 u8 sta_id)
139{
140 unsigned long flags;
141 __le16 key_flags = 0;
6e21f15c
AK
142 int ret;
143
144 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
145 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
146
a194e324 147 if (sta_id == priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id)
6e21f15c
AK
148 key_flags |= STA_KEY_MULTICAST_MSK;
149
150 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
151 keyconf->hw_key_idx = keyconf->keyidx;
152 key_flags &= ~STA_KEY_FLG_INVALID;
b481de9c 153
b481de9c 154 spin_lock_irqsave(&priv->sta_lock, flags);
97359d12 155 priv->stations[sta_id].keyinfo.cipher = keyconf->cipher;
c587de0b
TW
156 priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
157 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
b481de9c
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158 keyconf->keylen);
159
c587de0b 160 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
b481de9c 161 keyconf->keylen);
6e21f15c 162
c587de0b 163 if ((priv->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK)
6e21f15c 164 == STA_KEY_FLG_NO_ENC)
c587de0b 165 priv->stations[sta_id].sta.key.key_offset =
6e21f15c
AK
166 iwl_get_free_ucode_key_index(priv);
167 /* else, we are overriding an existing key => no need to allocated room
168 * in uCode. */
169
c587de0b 170 WARN(priv->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
6e21f15c
AK
171 "no space for a new key");
172
c587de0b
TW
173 priv->stations[sta_id].sta.key.key_flags = key_flags;
174 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
175 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
b481de9c 176
6e21f15c
AK
177 IWL_DEBUG_INFO(priv, "hwcrypto: modify ucode station key info\n");
178
c587de0b 179 ret = iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
6e21f15c 180
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181 spin_unlock_irqrestore(&priv->sta_lock, flags);
182
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AK
183 return ret;
184}
185
186static int iwl3945_set_tkip_dynamic_key_info(struct iwl_priv *priv,
187 struct ieee80211_key_conf *keyconf,
188 u8 sta_id)
189{
190 return -EOPNOTSUPP;
191}
192
193static int iwl3945_set_wep_dynamic_key_info(struct iwl_priv *priv,
194 struct ieee80211_key_conf *keyconf,
195 u8 sta_id)
196{
197 return -EOPNOTSUPP;
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198}
199
4a8a4322 200static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id)
b481de9c
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201{
202 unsigned long flags;
9c5ac091 203 struct iwl_addsta_cmd sta_cmd;
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204
205 spin_lock_irqsave(&priv->sta_lock, flags);
c587de0b
TW
206 memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl_hw_key));
207 memset(&priv->stations[sta_id].sta.key, 0,
4c897253 208 sizeof(struct iwl4965_keyinfo));
c587de0b
TW
209 priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
210 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
211 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
9c5ac091 212 memcpy(&sta_cmd, &priv->stations[sta_id].sta, sizeof(struct iwl_addsta_cmd));
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213 spin_unlock_irqrestore(&priv->sta_lock, flags);
214
e1623446 215 IWL_DEBUG_INFO(priv, "hwcrypto: clear ucode station key info\n");
9c5ac091 216 return iwl_send_add_sta(priv, &sta_cmd, CMD_SYNC);
b481de9c
ZY
217}
218
fa11d525 219static int iwl3945_set_dynamic_key(struct iwl_priv *priv,
6e21f15c
AK
220 struct ieee80211_key_conf *keyconf, u8 sta_id)
221{
222 int ret = 0;
223
224 keyconf->hw_key_idx = HW_KEY_DYNAMIC;
225
97359d12
JB
226 switch (keyconf->cipher) {
227 case WLAN_CIPHER_SUITE_CCMP:
6e21f15c
AK
228 ret = iwl3945_set_ccmp_dynamic_key_info(priv, keyconf, sta_id);
229 break;
97359d12 230 case WLAN_CIPHER_SUITE_TKIP:
6e21f15c
AK
231 ret = iwl3945_set_tkip_dynamic_key_info(priv, keyconf, sta_id);
232 break;
97359d12
JB
233 case WLAN_CIPHER_SUITE_WEP40:
234 case WLAN_CIPHER_SUITE_WEP104:
6e21f15c
AK
235 ret = iwl3945_set_wep_dynamic_key_info(priv, keyconf, sta_id);
236 break;
237 default:
97359d12
JB
238 IWL_ERR(priv, "Unknown alg: %s alg=%x\n", __func__,
239 keyconf->cipher);
6e21f15c
AK
240 ret = -EINVAL;
241 }
242
97359d12
JB
243 IWL_DEBUG_WEP(priv, "Set dynamic key: alg=%x len=%d idx=%d sta=%d ret=%d\n",
244 keyconf->cipher, keyconf->keylen, keyconf->keyidx,
6e21f15c
AK
245 sta_id, ret);
246
247 return ret;
248}
249
250static int iwl3945_remove_static_key(struct iwl_priv *priv)
251{
252 int ret = -EOPNOTSUPP;
253
254 return ret;
255}
256
257static int iwl3945_set_static_key(struct iwl_priv *priv,
258 struct ieee80211_key_conf *key)
259{
97359d12
JB
260 if (key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
261 key->cipher == WLAN_CIPHER_SUITE_WEP104)
6e21f15c
AK
262 return -EOPNOTSUPP;
263
97359d12 264 IWL_ERR(priv, "Static key invalid: cipher %x\n", key->cipher);
6e21f15c
AK
265 return -EINVAL;
266}
267
4a8a4322 268static void iwl3945_clear_free_frames(struct iwl_priv *priv)
b481de9c
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269{
270 struct list_head *element;
271
e1623446 272 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
b481de9c
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273 priv->frames_count);
274
275 while (!list_empty(&priv->free_frames)) {
276 element = priv->free_frames.next;
277 list_del(element);
bb8c093b 278 kfree(list_entry(element, struct iwl3945_frame, list));
b481de9c
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279 priv->frames_count--;
280 }
281
282 if (priv->frames_count) {
39aadf8c 283 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
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284 priv->frames_count);
285 priv->frames_count = 0;
286 }
287}
288
4a8a4322 289static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv)
b481de9c 290{
bb8c093b 291 struct iwl3945_frame *frame;
b481de9c
ZY
292 struct list_head *element;
293 if (list_empty(&priv->free_frames)) {
294 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
295 if (!frame) {
15b1687c 296 IWL_ERR(priv, "Could not allocate frame!\n");
b481de9c
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297 return NULL;
298 }
299
300 priv->frames_count++;
301 return frame;
302 }
303
304 element = priv->free_frames.next;
305 list_del(element);
bb8c093b 306 return list_entry(element, struct iwl3945_frame, list);
b481de9c
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307}
308
4a8a4322 309static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame)
b481de9c
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310{
311 memset(frame, 0, sizeof(*frame));
312 list_add(&frame->list, &priv->free_frames);
313}
314
4a8a4322 315unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv,
b481de9c 316 struct ieee80211_hdr *hdr,
73ec1cc2 317 int left)
b481de9c
ZY
318{
319
12e934dc 320 if (!iwl_is_associated(priv, IWL_RXON_CTX_BSS) || !priv->beacon_skb)
b481de9c
ZY
321 return 0;
322
12e934dc 323 if (priv->beacon_skb->len > left)
b481de9c
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324 return 0;
325
12e934dc 326 memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len);
b481de9c 327
12e934dc 328 return priv->beacon_skb->len;
b481de9c
ZY
329}
330
4a8a4322 331static int iwl3945_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 332{
bb8c093b 333 struct iwl3945_frame *frame;
b481de9c
ZY
334 unsigned int frame_size;
335 int rc;
336 u8 rate;
337
bb8c093b 338 frame = iwl3945_get_free_frame(priv);
b481de9c
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339
340 if (!frame) {
15b1687c 341 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
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342 "command.\n");
343 return -ENOMEM;
344 }
345
76d04815
JB
346 rate = iwl_rate_get_lowest_plcp(priv,
347 &priv->contexts[IWL_RXON_CTX_BSS]);
b481de9c 348
bb8c093b 349 frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 350
518099a8 351 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
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352 &frame->u.cmd[0]);
353
bb8c093b 354 iwl3945_free_frame(priv, frame);
b481de9c
ZY
355
356 return rc;
357}
358
4a8a4322 359static void iwl3945_unset_hw_params(struct iwl_priv *priv)
b481de9c 360{
ee525d13 361 if (priv->_3945.shared_virt)
f36d04ab
SG
362 dma_free_coherent(&priv->pci_dev->dev,
363 sizeof(struct iwl3945_shared),
ee525d13
JB
364 priv->_3945.shared_virt,
365 priv->_3945.shared_phys);
b481de9c
ZY
366}
367
4a8a4322 368static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv,
e039fa4a 369 struct ieee80211_tx_info *info,
c2acea8e 370 struct iwl_device_cmd *cmd,
b481de9c 371 struct sk_buff *skb_frag,
6e21f15c 372 int sta_id)
b481de9c 373{
9744c91f 374 struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
c587de0b 375 struct iwl_hw_key *keyinfo = &priv->stations[sta_id].keyinfo;
b481de9c 376
97359d12
JB
377 tx_cmd->sec_ctl = 0;
378
379 switch (keyinfo->cipher) {
380 case WLAN_CIPHER_SUITE_CCMP:
9744c91f
AK
381 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
382 memcpy(tx_cmd->key, keyinfo->key, keyinfo->keylen);
e1623446 383 IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
b481de9c
ZY
384 break;
385
97359d12 386 case WLAN_CIPHER_SUITE_TKIP:
b481de9c
ZY
387 break;
388
97359d12
JB
389 case WLAN_CIPHER_SUITE_WEP104:
390 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
391 /* fall through */
392 case WLAN_CIPHER_SUITE_WEP40:
393 tx_cmd->sec_ctl |= TX_CMD_SEC_WEP |
e039fa4a 394 (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
b481de9c 395
9744c91f 396 memcpy(&tx_cmd->key[3], keyinfo->key, keyinfo->keylen);
b481de9c 397
e1623446 398 IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
e039fa4a 399 "with key %d\n", info->control.hw_key->hw_key_idx);
b481de9c
ZY
400 break;
401
b481de9c 402 default:
97359d12 403 IWL_ERR(priv, "Unknown encode cipher %x\n", keyinfo->cipher);
b481de9c
ZY
404 break;
405 }
406}
407
408/*
409 * handle build REPLY_TX command notification.
410 */
4a8a4322 411static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv,
c2acea8e 412 struct iwl_device_cmd *cmd,
e039fa4a 413 struct ieee80211_tx_info *info,
e52119c5 414 struct ieee80211_hdr *hdr, u8 std_id)
b481de9c 415{
9744c91f
AK
416 struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
417 __le32 tx_flags = tx_cmd->tx_flags;
fd7c8a40 418 __le16 fc = hdr->frame_control;
b481de9c 419
9744c91f 420 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e039fa4a 421 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
b481de9c 422 tx_flags |= TX_CMD_FLG_ACK_MSK;
fd7c8a40 423 if (ieee80211_is_mgmt(fc))
b481de9c 424 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
fd7c8a40 425 if (ieee80211_is_probe_resp(fc) &&
b481de9c
ZY
426 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
427 tx_flags |= TX_CMD_FLG_TSF_MSK;
428 } else {
429 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
430 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
431 }
432
9744c91f 433 tx_cmd->sta_id = std_id;
8b7b1e05 434 if (ieee80211_has_morefrags(fc))
b481de9c
ZY
435 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
436
fd7c8a40
HH
437 if (ieee80211_is_data_qos(fc)) {
438 u8 *qc = ieee80211_get_qos_ctl(hdr);
9744c91f 439 tx_cmd->tid_tspec = qc[0] & 0xf;
b481de9c 440 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 441 } else {
b481de9c 442 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 443 }
b481de9c 444
94597ab2 445 priv->cfg->ops->utils->tx_cmd_protection(priv, info, fc, &tx_flags);
b481de9c
ZY
446
447 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
fd7c8a40
HH
448 if (ieee80211_is_mgmt(fc)) {
449 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
9744c91f 450 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
b481de9c 451 else
9744c91f 452 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
ab53d8af 453 } else {
9744c91f 454 tx_cmd->timeout.pm_frame_timeout = 0;
ab53d8af 455 }
b481de9c 456
9744c91f
AK
457 tx_cmd->driver_txop = 0;
458 tx_cmd->tx_flags = tx_flags;
459 tx_cmd->next_frame_len = 0;
b481de9c
ZY
460}
461
b481de9c
ZY
462/*
463 * start REPLY_TX command process
464 */
4a8a4322 465static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
b481de9c
ZY
466{
467 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
e039fa4a 468 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
9744c91f 469 struct iwl3945_tx_cmd *tx_cmd;
188cf6c7 470 struct iwl_tx_queue *txq = NULL;
d20b3c65 471 struct iwl_queue *q = NULL;
c2acea8e
JB
472 struct iwl_device_cmd *out_cmd;
473 struct iwl_cmd_meta *out_meta;
b481de9c
ZY
474 dma_addr_t phys_addr;
475 dma_addr_t txcmd_phys;
e52119c5 476 int txq_id = skb_get_queue_mapping(skb);
df833b1d 477 u16 len, idx, len_org, hdr_len; /* TODO: len_org is not used */
54dbb525
TW
478 u8 id;
479 u8 unicast;
b481de9c 480 u8 sta_id;
54dbb525 481 u8 tid = 0;
fd7c8a40 482 __le16 fc;
b481de9c
ZY
483 u8 wait_write_ptr = 0;
484 unsigned long flags;
b481de9c
ZY
485
486 spin_lock_irqsave(&priv->lock, flags);
775a6e27 487 if (iwl_is_rfkill(priv)) {
e1623446 488 IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
b481de9c
ZY
489 goto drop_unlock;
490 }
491
e039fa4a 492 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
15b1687c 493 IWL_ERR(priv, "ERROR: No TX rate available.\n");
b481de9c
ZY
494 goto drop_unlock;
495 }
496
497 unicast = !is_multicast_ether_addr(hdr->addr1);
498 id = 0;
499
fd7c8a40 500 fc = hdr->frame_control;
b481de9c 501
d08853a3 502#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c 503 if (ieee80211_is_auth(fc))
e1623446 504 IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
fd7c8a40 505 else if (ieee80211_is_assoc_req(fc))
e1623446 506 IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
fd7c8a40 507 else if (ieee80211_is_reassoc_req(fc))
e1623446 508 IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
b481de9c
ZY
509#endif
510
b481de9c
ZY
511 spin_unlock_irqrestore(&priv->lock, flags);
512
7294ec95 513 hdr_len = ieee80211_hdrlen(fc);
6440adb5 514
2a87c26b 515 /* Find index into station table for destination station */
a194e324
JB
516 sta_id = iwl_sta_id_or_broadcast(
517 priv, &priv->contexts[IWL_RXON_CTX_BSS],
518 info->control.sta);
b481de9c 519 if (sta_id == IWL_INVALID_STATION) {
e1623446 520 IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
e174961c 521 hdr->addr1);
b481de9c
ZY
522 goto drop;
523 }
524
e1623446 525 IWL_DEBUG_RATE(priv, "station Id %d\n", sta_id);
b481de9c 526
fd7c8a40 527 if (ieee80211_is_data_qos(fc)) {
f862a236 528 u8 *qc = ieee80211_get_qos_ctl(hdr);
7294ec95 529 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
e6a6cf4c
RC
530 if (unlikely(tid >= MAX_TID_COUNT))
531 goto drop;
b481de9c 532 }
6440adb5
CB
533
534 /* Descriptor for chosen Tx queue */
188cf6c7 535 txq = &priv->txq[txq_id];
b481de9c
ZY
536 q = &txq->q;
537
dc57a303
ZY
538 if ((iwl_queue_space(q) < q->high_mark))
539 goto drop;
540
b481de9c
ZY
541 spin_lock_irqsave(&priv->lock, flags);
542
fc4b6853 543 idx = get_cmd_index(q, q->write_ptr, 0);
b481de9c 544
6440adb5 545 /* Set up driver data for this TFD */
dbb6654c 546 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
ff0d91c3 547 txq->txb[q->write_ptr].skb = skb;
c90cbbbd 548 txq->txb[q->write_ptr].ctx = &priv->contexts[IWL_RXON_CTX_BSS];
6440adb5
CB
549
550 /* Init first empty entry in queue's array of Tx/cmd buffers */
188cf6c7 551 out_cmd = txq->cmd[idx];
c2acea8e 552 out_meta = &txq->meta[idx];
9744c91f 553 tx_cmd = (struct iwl3945_tx_cmd *)out_cmd->cmd.payload;
b481de9c 554 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
9744c91f 555 memset(tx_cmd, 0, sizeof(*tx_cmd));
6440adb5
CB
556
557 /*
558 * Set up the Tx-command (not MAC!) header.
559 * Store the chosen Tx queue and TFD index within the sequence field;
560 * after Tx, uCode's Tx response will return this value so driver can
561 * locate the frame within the tx queue and do post-tx processing.
562 */
b481de9c
ZY
563 out_cmd->hdr.cmd = REPLY_TX;
564 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
fc4b6853 565 INDEX_TO_SEQ(q->write_ptr)));
6440adb5
CB
566
567 /* Copy MAC header from skb into command buffer */
9744c91f 568 memcpy(tx_cmd->hdr, hdr, hdr_len);
b481de9c 569
df833b1d
RC
570
571 if (info->control.hw_key)
572 iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, sta_id);
573
574 /* TODO need this for burst mode later on */
575 iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, sta_id);
576
577 /* set is_hcca to 0; it probably will never be implemented */
578 iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
579
580 /* Total # bytes to be transmitted */
581 len = (u16)skb->len;
9744c91f 582 tx_cmd->len = cpu_to_le16(len);
df833b1d 583
20594eb0 584 iwl_dbg_log_tx_data_frame(priv, len, hdr);
22fdf3c9 585 iwl_update_stats(priv, true, fc, len);
9744c91f
AK
586 tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
587 tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
df833b1d
RC
588
589 if (!ieee80211_has_morefrags(hdr->frame_control)) {
590 txq->need_update = 1;
df833b1d
RC
591 } else {
592 wait_write_ptr = 1;
593 txq->need_update = 0;
594 }
595
91dd6c27 596 IWL_DEBUG_TX(priv, "sequence nr = 0X%x\n",
df833b1d 597 le16_to_cpu(out_cmd->hdr.sequence));
91dd6c27 598 IWL_DEBUG_TX(priv, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
9744c91f
AK
599 iwl_print_hex_dump(priv, IWL_DL_TX, tx_cmd, sizeof(*tx_cmd));
600 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr,
df833b1d
RC
601 ieee80211_hdrlen(fc));
602
6440adb5
CB
603 /*
604 * Use the first empty entry in this queue's command buffer array
605 * to contain the Tx command and MAC header concatenated together
606 * (payload data will be in another buffer).
607 * Size of this varies, due to varying MAC header length.
608 * If end is not dword aligned, we'll have 2 extra bytes at the end
609 * of the MAC header (device reads on dword boundaries).
610 * We'll tell device about this padding later.
611 */
3832ec9d 612 len = sizeof(struct iwl3945_tx_cmd) +
4c897253 613 sizeof(struct iwl_cmd_header) + hdr_len;
b481de9c
ZY
614
615 len_org = len;
616 len = (len + 3) & ~3;
617
618 if (len_org != len)
619 len_org = 1;
620 else
621 len_org = 0;
622
6440adb5
CB
623 /* Physical address of this Tx command's header (not MAC header!),
624 * within command buffer array. */
df833b1d
RC
625 txcmd_phys = pci_map_single(priv->pci_dev, &out_cmd->hdr,
626 len, PCI_DMA_TODEVICE);
627 /* we do not map meta data ... so we can safely access address to
628 * provide to unmap command*/
2e724443
FT
629 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
630 dma_unmap_len_set(out_meta, len, len);
b481de9c 631
6440adb5
CB
632 /* Add buffer containing Tx command and MAC(!) header to TFD's
633 * first entry */
7aaa1d79
SO
634 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
635 txcmd_phys, len, 1, 0);
b481de9c 636
b481de9c 637
6440adb5
CB
638 /* Set up TFD's 2nd entry to point directly to remainder of skb,
639 * if any (802.11 null frames have no payload). */
b481de9c
ZY
640 len = skb->len - hdr_len;
641 if (len) {
642 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
643 len, PCI_DMA_TODEVICE);
7aaa1d79
SO
644 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
645 phys_addr, len,
646 0, U32_PAD(len));
b481de9c
ZY
647 }
648
b481de9c 649
6440adb5 650 /* Tell device the write index *just past* this latest filled TFD */
c54b679d 651 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
7bfedc59 652 iwl_txq_update_write_ptr(priv, txq);
b481de9c
ZY
653 spin_unlock_irqrestore(&priv->lock, flags);
654
d20b3c65 655 if ((iwl_queue_space(q) < q->high_mark)
b481de9c
ZY
656 && priv->mac80211_registered) {
657 if (wait_write_ptr) {
658 spin_lock_irqsave(&priv->lock, flags);
659 txq->need_update = 1;
4f3602c8 660 iwl_txq_update_write_ptr(priv, txq);
b481de9c
ZY
661 spin_unlock_irqrestore(&priv->lock, flags);
662 }
663
e4e72fb4 664 iwl_stop_queue(priv, skb_get_queue_mapping(skb));
b481de9c
ZY
665 }
666
667 return 0;
668
669drop_unlock:
670 spin_unlock_irqrestore(&priv->lock, flags);
671drop:
672 return -1;
673}
674
4a8a4322 675static int iwl3945_get_measurement(struct iwl_priv *priv,
b481de9c
ZY
676 struct ieee80211_measurement_params *params,
677 u8 type)
678{
600c0e11 679 struct iwl_spectrum_cmd spectrum;
2f301227 680 struct iwl_rx_packet *pkt;
c2d79b48 681 struct iwl_host_cmd cmd = {
b481de9c
ZY
682 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
683 .data = (void *)&spectrum,
c2acea8e 684 .flags = CMD_WANT_SKB,
b481de9c
ZY
685 };
686 u32 add_time = le64_to_cpu(params->start_time);
687 int rc;
688 int spectrum_resp_status;
689 int duration = le16_to_cpu(params->duration);
246ed355 690 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
b481de9c 691
246ed355 692 if (iwl_is_associated(priv, IWL_RXON_CTX_BSS))
a0ee74cf 693 add_time = iwl_usecs_to_beacons(priv,
e99f168c 694 le64_to_cpu(params->start_time) - priv->_3945.last_tsf,
246ed355 695 le16_to_cpu(ctx->timing.beacon_interval));
b481de9c
ZY
696
697 memset(&spectrum, 0, sizeof(spectrum));
698
699 spectrum.channel_count = cpu_to_le16(1);
700 spectrum.flags =
701 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
702 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
703 cmd.len = sizeof(spectrum);
704 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
705
246ed355 706 if (iwl_is_associated(priv, IWL_RXON_CTX_BSS))
b481de9c 707 spectrum.start_time =
a0ee74cf
WYG
708 iwl_add_beacon_time(priv,
709 priv->_3945.last_beacon_time, add_time,
246ed355 710 le16_to_cpu(ctx->timing.beacon_interval));
b481de9c
ZY
711 else
712 spectrum.start_time = 0;
713
714 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
715 spectrum.channels[0].channel = params->channel;
716 spectrum.channels[0].type = type;
246ed355 717 if (ctx->active.flags & RXON_FLG_BAND_24G_MSK)
b481de9c
ZY
718 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
719 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
720
518099a8 721 rc = iwl_send_cmd_sync(priv, &cmd);
b481de9c
ZY
722 if (rc)
723 return rc;
724
2f301227
ZY
725 pkt = (struct iwl_rx_packet *)cmd.reply_page;
726 if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
15b1687c 727 IWL_ERR(priv, "Bad return from REPLY_RX_ON_ASSOC command\n");
b481de9c
ZY
728 rc = -EIO;
729 }
730
2f301227 731 spectrum_resp_status = le16_to_cpu(pkt->u.spectrum.status);
b481de9c
ZY
732 switch (spectrum_resp_status) {
733 case 0: /* Command will be handled */
2f301227 734 if (pkt->u.spectrum.id != 0xff) {
e1623446 735 IWL_DEBUG_INFO(priv, "Replaced existing measurement: %d\n",
2f301227 736 pkt->u.spectrum.id);
b481de9c
ZY
737 priv->measurement_status &= ~MEASUREMENT_READY;
738 }
739 priv->measurement_status |= MEASUREMENT_ACTIVE;
740 rc = 0;
741 break;
742
743 case 1: /* Command will not be handled */
744 rc = -EAGAIN;
745 break;
746 }
747
64a76b50 748 iwl_free_pages(priv, cmd.reply_page);
b481de9c
ZY
749
750 return rc;
751}
b481de9c 752
4a8a4322 753static void iwl3945_rx_reply_alive(struct iwl_priv *priv,
6100b588 754 struct iwl_rx_mem_buffer *rxb)
b481de9c 755{
2f301227 756 struct iwl_rx_packet *pkt = rxb_addr(rxb);
3d24a9f7 757 struct iwl_alive_resp *palive;
b481de9c
ZY
758 struct delayed_work *pwork;
759
760 palive = &pkt->u.alive_frame;
761
e1623446 762 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY
763 "0x%01X 0x%01X\n",
764 palive->is_valid, palive->ver_type,
765 palive->ver_subtype);
766
767 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 768 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
3d24a9f7
TW
769 memcpy(&priv->card_alive_init, &pkt->u.alive_frame,
770 sizeof(struct iwl_alive_resp));
b481de9c
ZY
771 pwork = &priv->init_alive_start;
772 } else {
e1623446 773 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 774 memcpy(&priv->card_alive, &pkt->u.alive_frame,
3d24a9f7 775 sizeof(struct iwl_alive_resp));
b481de9c 776 pwork = &priv->alive_start;
bb8c093b 777 iwl3945_disable_events(priv);
b481de9c
ZY
778 }
779
780 /* We delay the ALIVE response by 5ms to
781 * give the HW RF Kill time to activate... */
782 if (palive->is_valid == UCODE_VALID_OK)
783 queue_delayed_work(priv->workqueue, pwork,
784 msecs_to_jiffies(5));
785 else
39aadf8c 786 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY
787}
788
4a8a4322 789static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv,
6100b588 790 struct iwl_rx_mem_buffer *rxb)
b481de9c 791{
c7e035a9 792#ifdef CONFIG_IWLWIFI_DEBUG
2f301227 793 struct iwl_rx_packet *pkt = rxb_addr(rxb);
c7e035a9 794#endif
b481de9c 795
e1623446 796 IWL_DEBUG_RX(priv, "Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
b481de9c
ZY
797}
798
bb8c093b 799static void iwl3945_bg_beacon_update(struct work_struct *work)
b481de9c 800{
4a8a4322
AK
801 struct iwl_priv *priv =
802 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY
803 struct sk_buff *beacon;
804
805 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
8bd413e6
JB
806 beacon = ieee80211_beacon_get(priv->hw,
807 priv->contexts[IWL_RXON_CTX_BSS].vif);
b481de9c
ZY
808
809 if (!beacon) {
15b1687c 810 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY
811 return;
812 }
813
814 mutex_lock(&priv->mutex);
815 /* new beacon skb is allocated every time; dispose previous.*/
12e934dc
JB
816 if (priv->beacon_skb)
817 dev_kfree_skb(priv->beacon_skb);
b481de9c 818
12e934dc 819 priv->beacon_skb = beacon;
b481de9c
ZY
820 mutex_unlock(&priv->mutex);
821
bb8c093b 822 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
823}
824
4a8a4322 825static void iwl3945_rx_beacon_notif(struct iwl_priv *priv,
6100b588 826 struct iwl_rx_mem_buffer *rxb)
b481de9c 827{
2f301227 828 struct iwl_rx_packet *pkt = rxb_addr(rxb);
bb8c093b 829 struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
a85d7cca 830#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
831 u8 rate = beacon->beacon_notify_hdr.rate;
832
e1623446 833 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c
ZY
834 "tsf %d %d rate %d\n",
835 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
836 beacon->beacon_notify_hdr.failure_frame,
837 le32_to_cpu(beacon->ibss_mgr_status),
838 le32_to_cpu(beacon->high_tsf),
839 le32_to_cpu(beacon->low_tsf), rate);
840#endif
841
a85d7cca
JB
842 priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
843
05c914fe 844 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY
845 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
846 queue_work(priv->workqueue, &priv->beacon_update);
847}
848
b481de9c
ZY
849/* Handle notification from uCode that card's power state is changing
850 * due to software, hardware, or critical temperature RFKILL */
4a8a4322 851static void iwl3945_rx_card_state_notif(struct iwl_priv *priv,
6100b588 852 struct iwl_rx_mem_buffer *rxb)
b481de9c 853{
2f301227 854 struct iwl_rx_packet *pkt = rxb_addr(rxb);
b481de9c
ZY
855 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
856 unsigned long status = priv->status;
857
4c423a2b 858 IWL_WARN(priv, "Card state received: HW:%s SW:%s\n",
b481de9c
ZY
859 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
860 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
861
5d49f498 862 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
863 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
864
865 if (flags & HW_CARD_DISABLED)
866 set_bit(STATUS_RF_KILL_HW, &priv->status);
867 else
868 clear_bit(STATUS_RF_KILL_HW, &priv->status);
869
870
af0053d6 871 iwl_scan_cancel(priv);
b481de9c
ZY
872
873 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB
874 test_bit(STATUS_RF_KILL_HW, &priv->status)))
875 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
876 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY
877 else
878 wake_up_interruptible(&priv->wait_command_queue);
879}
880
881/**
bb8c093b 882 * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY
883 *
884 * Setup the RX handlers for each of the reply types sent from the uCode
885 * to the host.
886 *
887 * This function chains into the hardware specific files for them to setup
888 * any hardware specific handlers as well.
889 */
4a8a4322 890static void iwl3945_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 891{
bb8c093b
CH
892 priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
893 priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
261b9c33 894 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
8ccde88a 895 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
81963d68
RC
896 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
897 iwl_rx_spectrum_measure_notif;
030f05ed 898 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 899 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
030f05ed 900 iwl_rx_pm_debug_statistics_notif;
bb8c093b 901 priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
b481de9c 902
9fbab516
BC
903 /*
904 * The same handler is used for both the REPLY to a discrete
905 * statistics request from the host as well as for the periodic
906 * statistics notifications (after received beacons) from the uCode.
b481de9c 907 */
17f36fc6 908 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_reply_statistics;
bb8c093b 909 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
b481de9c 910
cade0eb2 911 iwl_setup_rx_scan_handlers(priv);
bb8c093b 912 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
b481de9c 913
9fbab516 914 /* Set up hardware specific Rx handlers */
bb8c093b 915 iwl3945_hw_rx_handler_setup(priv);
b481de9c
ZY
916}
917
b481de9c
ZY
918/************************** RX-FUNCTIONS ****************************/
919/*
920 * Rx theory of operation
921 *
922 * The host allocates 32 DMA target addresses and passes the host address
923 * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
924 * 0 to 31
925 *
926 * Rx Queue Indexes
927 * The host/firmware share two index registers for managing the Rx buffers.
928 *
929 * The READ index maps to the first position that the firmware may be writing
930 * to -- the driver can read up to (but not including) this position and get
931 * good data.
932 * The READ index is managed by the firmware once the card is enabled.
933 *
934 * The WRITE index maps to the last position the driver has read from -- the
935 * position preceding WRITE is the last slot the firmware can place a packet.
936 *
937 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
938 * WRITE = READ.
939 *
9fbab516 940 * During initialization, the host sets up the READ queue position to the first
b481de9c
ZY
941 * INDEX position, and WRITE to the last (READ - 1 wrapped)
942 *
9fbab516 943 * When the firmware places a packet in a buffer, it will advance the READ index
b481de9c
ZY
944 * and fire the RX interrupt. The driver can then query the READ index and
945 * process as many packets as possible, moving the WRITE index forward as it
946 * resets the Rx queue buffers with new memory.
947 *
948 * The management in the driver is as follows:
949 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
950 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
01ebd063 951 * to replenish the iwl->rxq->rx_free.
bb8c093b 952 * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
b481de9c
ZY
953 * iwl->rxq is replenished and the READ INDEX is updated (updating the
954 * 'processed' and 'read' driver indexes as well)
955 * + A received packet is processed and handed to the kernel network stack,
956 * detached from the iwl->rxq. The driver 'processed' index is updated.
957 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
958 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
959 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
960 * were enough free buffers and RX_STALLED is set it is cleared.
961 *
962 *
963 * Driver sequence:
964 *
9fbab516 965 * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
bb8c093b 966 * iwl3945_rx_queue_restock
9fbab516 967 * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
b481de9c
ZY
968 * queue, updates firmware pointers, and updates
969 * the WRITE index. If insufficient rx_free buffers
bb8c093b 970 * are available, schedules iwl3945_rx_replenish
b481de9c
ZY
971 *
972 * -- enable interrupts --
6100b588 973 * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the
b481de9c
ZY
974 * READ INDEX, detaching the SKB from the pool.
975 * Moves the packet buffer from queue to rx_used.
bb8c093b 976 * Calls iwl3945_rx_queue_restock to refill any empty
b481de9c
ZY
977 * slots.
978 * ...
979 *
980 */
981
b481de9c 982/**
9fbab516 983 * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
b481de9c 984 */
4a8a4322 985static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv,
b481de9c
ZY
986 dma_addr_t dma_addr)
987{
988 return cpu_to_le32((u32)dma_addr);
989}
990
991/**
bb8c093b 992 * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
b481de9c 993 *
9fbab516 994 * If there are slots in the RX queue that need to be restocked,
b481de9c 995 * and we have free pre-allocated buffers, fill the ranks as much
9fbab516 996 * as we can, pulling from rx_free.
b481de9c
ZY
997 *
998 * This moves the 'write' index forward to catch up with 'processed', and
999 * also updates the memory address in the firmware to reference the new
1000 * target buffer.
1001 */
7bfedc59 1002static void iwl3945_rx_queue_restock(struct iwl_priv *priv)
b481de9c 1003{
cc2f362c 1004 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c 1005 struct list_head *element;
6100b588 1006 struct iwl_rx_mem_buffer *rxb;
b481de9c 1007 unsigned long flags;
7bfedc59 1008 int write;
b481de9c
ZY
1009
1010 spin_lock_irqsave(&rxq->lock, flags);
1011 write = rxq->write & ~0x7;
37d68317 1012 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
6440adb5 1013 /* Get next free Rx buffer, remove from free list */
b481de9c 1014 element = rxq->rx_free.next;
6100b588 1015 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
b481de9c 1016 list_del(element);
6440adb5
CB
1017
1018 /* Point to Rx buffer via next RBD in circular buffer */
2f301227 1019 rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->page_dma);
b481de9c
ZY
1020 rxq->queue[rxq->write] = rxb;
1021 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
1022 rxq->free_count--;
1023 }
1024 spin_unlock_irqrestore(&rxq->lock, flags);
1025 /* If the pre-allocated buffer pool is dropping low, schedule to
1026 * refill it */
1027 if (rxq->free_count <= RX_LOW_WATERMARK)
1028 queue_work(priv->workqueue, &priv->rx_replenish);
1029
1030
6440adb5
CB
1031 /* If we've added more space for the firmware to place data, tell it.
1032 * Increment device's write pointer in multiples of 8. */
d14d4440 1033 if ((rxq->write_actual != (rxq->write & ~0x7))
b481de9c
ZY
1034 || (abs(rxq->write - rxq->read) > 7)) {
1035 spin_lock_irqsave(&rxq->lock, flags);
1036 rxq->need_update = 1;
1037 spin_unlock_irqrestore(&rxq->lock, flags);
7bfedc59 1038 iwl_rx_queue_update_write_ptr(priv, rxq);
b481de9c 1039 }
b481de9c
ZY
1040}
1041
1042/**
bb8c093b 1043 * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
b481de9c
ZY
1044 *
1045 * When moving to rx_free an SKB is allocated for the slot.
1046 *
bb8c093b 1047 * Also restock the Rx queue via iwl3945_rx_queue_restock.
01ebd063 1048 * This is called as a scheduled work item (except for during initialization)
b481de9c 1049 */
d14d4440 1050static void iwl3945_rx_allocate(struct iwl_priv *priv, gfp_t priority)
b481de9c 1051{
cc2f362c 1052 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c 1053 struct list_head *element;
6100b588 1054 struct iwl_rx_mem_buffer *rxb;
2f301227 1055 struct page *page;
b481de9c 1056 unsigned long flags;
29b1b268 1057 gfp_t gfp_mask = priority;
72240498
AK
1058
1059 while (1) {
1060 spin_lock_irqsave(&rxq->lock, flags);
1061
1062 if (list_empty(&rxq->rx_used)) {
1063 spin_unlock_irqrestore(&rxq->lock, flags);
1064 return;
1065 }
72240498 1066 spin_unlock_irqrestore(&rxq->lock, flags);
6440adb5 1067
f82a924c 1068 if (rxq->free_count > RX_LOW_WATERMARK)
29b1b268 1069 gfp_mask |= __GFP_NOWARN;
2f301227
ZY
1070
1071 if (priv->hw_params.rx_page_order > 0)
29b1b268 1072 gfp_mask |= __GFP_COMP;
2f301227 1073
6440adb5 1074 /* Alloc a new receive buffer */
29b1b268 1075 page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
2f301227 1076 if (!page) {
b481de9c 1077 if (net_ratelimit())
f82a924c
RC
1078 IWL_DEBUG_INFO(priv, "Failed to allocate SKB buffer.\n");
1079 if ((rxq->free_count <= RX_LOW_WATERMARK) &&
1080 net_ratelimit())
1081 IWL_CRIT(priv, "Failed to allocate SKB buffer with %s. Only %u free buffers remaining.\n",
1082 priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
1083 rxq->free_count);
b481de9c
ZY
1084 /* We don't reschedule replenish work here -- we will
1085 * call the restock method and if it still needs
1086 * more buffers it will schedule replenish */
1087 break;
1088 }
12342c47 1089
de0bd508
RC
1090 spin_lock_irqsave(&rxq->lock, flags);
1091 if (list_empty(&rxq->rx_used)) {
1092 spin_unlock_irqrestore(&rxq->lock, flags);
2f301227 1093 __free_pages(page, priv->hw_params.rx_page_order);
de0bd508
RC
1094 return;
1095 }
1096 element = rxq->rx_used.next;
1097 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
1098 list_del(element);
1099 spin_unlock_irqrestore(&rxq->lock, flags);
1100
2f301227 1101 rxb->page = page;
6440adb5 1102 /* Get physical address of RB/SKB */
2f301227
ZY
1103 rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
1104 PAGE_SIZE << priv->hw_params.rx_page_order,
1105 PCI_DMA_FROMDEVICE);
72240498
AK
1106
1107 spin_lock_irqsave(&rxq->lock, flags);
2f301227 1108
b481de9c
ZY
1109 list_add_tail(&rxb->list, &rxq->rx_free);
1110 rxq->free_count++;
2f301227
ZY
1111 priv->alloc_rxb_page++;
1112
72240498 1113 spin_unlock_irqrestore(&rxq->lock, flags);
b481de9c 1114 }
5c0eef96
MA
1115}
1116
df833b1d
RC
1117void iwl3945_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
1118{
1119 unsigned long flags;
1120 int i;
1121 spin_lock_irqsave(&rxq->lock, flags);
1122 INIT_LIST_HEAD(&rxq->rx_free);
1123 INIT_LIST_HEAD(&rxq->rx_used);
1124 /* Fill the rx_used queue with _all_ of the Rx buffers */
1125 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
1126 /* In the reset function, these buffers may have been allocated
1127 * to an SKB, so we need to unmap and free potential storage */
2f301227
ZY
1128 if (rxq->pool[i].page != NULL) {
1129 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
1130 PAGE_SIZE << priv->hw_params.rx_page_order,
1131 PCI_DMA_FROMDEVICE);
64a76b50 1132 __iwl_free_pages(priv, rxq->pool[i].page);
2f301227 1133 rxq->pool[i].page = NULL;
df833b1d
RC
1134 }
1135 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
1136 }
1137
1138 /* Set us so that we have processed and used all buffers, but have
1139 * not restocked the Rx queue with fresh buffers */
1140 rxq->read = rxq->write = 0;
d14d4440 1141 rxq->write_actual = 0;
2f301227 1142 rxq->free_count = 0;
df833b1d
RC
1143 spin_unlock_irqrestore(&rxq->lock, flags);
1144}
df833b1d 1145
5c0eef96
MA
1146void iwl3945_rx_replenish(void *data)
1147{
4a8a4322 1148 struct iwl_priv *priv = data;
5c0eef96
MA
1149 unsigned long flags;
1150
d14d4440 1151 iwl3945_rx_allocate(priv, GFP_KERNEL);
b481de9c
ZY
1152
1153 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 1154 iwl3945_rx_queue_restock(priv);
b481de9c
ZY
1155 spin_unlock_irqrestore(&priv->lock, flags);
1156}
1157
d14d4440
AK
1158static void iwl3945_rx_replenish_now(struct iwl_priv *priv)
1159{
1160 iwl3945_rx_allocate(priv, GFP_ATOMIC);
1161
1162 iwl3945_rx_queue_restock(priv);
1163}
1164
1165
df833b1d
RC
1166/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
1167 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
1168 * This free routine walks the list of POOL entries and if SKB is set to
1169 * non NULL it is unmapped and freed
1170 */
1171static void iwl3945_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
1172{
1173 int i;
1174 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
2f301227
ZY
1175 if (rxq->pool[i].page != NULL) {
1176 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
1177 PAGE_SIZE << priv->hw_params.rx_page_order,
1178 PCI_DMA_FROMDEVICE);
64a76b50 1179 __iwl_free_pages(priv, rxq->pool[i].page);
2f301227 1180 rxq->pool[i].page = NULL;
df833b1d
RC
1181 }
1182 }
1183
f36d04ab 1184 dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
d5b25c90 1185 rxq->bd_dma);
f36d04ab
SG
1186 dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
1187 rxq->rb_stts, rxq->rb_stts_dma);
df833b1d
RC
1188 rxq->bd = NULL;
1189 rxq->rb_stts = NULL;
1190}
df833b1d
RC
1191
1192
b481de9c
ZY
1193/* Convert linear signal-to-noise ratio into dB */
1194static u8 ratio2dB[100] = {
1195/* 0 1 2 3 4 5 6 7 8 9 */
1196 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
1197 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
1198 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
1199 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
1200 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
1201 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
1202 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
1203 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
1204 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
1205 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
1206};
1207
1208/* Calculates a relative dB value from a ratio of linear
1209 * (i.e. not dB) signal levels.
1210 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
bb8c093b 1211int iwl3945_calc_db_from_ratio(int sig_ratio)
b481de9c 1212{
221c80cf
AB
1213 /* 1000:1 or higher just report as 60 dB */
1214 if (sig_ratio >= 1000)
b481de9c
ZY
1215 return 60;
1216
221c80cf 1217 /* 100:1 or higher, divide by 10 and use table,
b481de9c 1218 * add 20 dB to make up for divide by 10 */
221c80cf 1219 if (sig_ratio >= 100)
3ac7f146 1220 return 20 + (int)ratio2dB[sig_ratio/10];
b481de9c
ZY
1221
1222 /* We shouldn't see this */
1223 if (sig_ratio < 1)
1224 return 0;
1225
1226 /* Use table for ratios 1:1 - 99:1 */
1227 return (int)ratio2dB[sig_ratio];
1228}
1229
b481de9c 1230/**
9fbab516 1231 * iwl3945_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
1232 *
1233 * Uses the priv->rx_handlers callback function array to invoke
1234 * the appropriate handlers, including command responses,
1235 * frame-received notifications, and other notifications.
1236 */
4a8a4322 1237static void iwl3945_rx_handle(struct iwl_priv *priv)
b481de9c 1238{
6100b588 1239 struct iwl_rx_mem_buffer *rxb;
3d24a9f7 1240 struct iwl_rx_packet *pkt;
cc2f362c 1241 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
1242 u32 r, i;
1243 int reclaim;
1244 unsigned long flags;
5c0eef96 1245 u8 fill_rx = 0;
d68ab680 1246 u32 count = 8;
d14d4440 1247 int total_empty = 0;
b481de9c 1248
6440adb5
CB
1249 /* uCode's read index (stored in shared DRAM) indicates the last Rx
1250 * buffer that the driver may process (last buffer filled by ucode). */
8cd812bc 1251 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY
1252 i = rxq->read;
1253
d14d4440 1254 /* calculate total frames need to be restock after handling RX */
7300515d 1255 total_empty = r - rxq->write_actual;
d14d4440
AK
1256 if (total_empty < 0)
1257 total_empty += RX_QUEUE_SIZE;
1258
1259 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96 1260 fill_rx = 1;
b481de9c
ZY
1261 /* Rx interrupt, but nothing sent from uCode */
1262 if (i == r)
af472a95 1263 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c
ZY
1264
1265 while (i != r) {
f4989d9b
JB
1266 int len;
1267
b481de9c
ZY
1268 rxb = rxq->queue[i];
1269
9fbab516 1270 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
1271 * then a bug has been introduced in the queue refilling
1272 * routines -- catch it here */
1273 BUG_ON(rxb == NULL);
1274
1275 rxq->queue[i] = NULL;
1276
2f301227
ZY
1277 pci_unmap_page(priv->pci_dev, rxb->page_dma,
1278 PAGE_SIZE << priv->hw_params.rx_page_order,
1279 PCI_DMA_FROMDEVICE);
1280 pkt = rxb_addr(rxb);
b481de9c 1281
f4989d9b
JB
1282 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
1283 len += sizeof(u32); /* account for status word */
1284 trace_iwlwifi_dev_rx(priv, pkt, len);
be1a71a1 1285
b481de9c
ZY
1286 /* Reclaim a command buffer only if this packet is a response
1287 * to a (driver-originated) command.
1288 * If the packet (e.g. Rx frame) originated from uCode,
1289 * there is no command buffer to reclaim.
1290 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1291 * but apparently a few don't get set; catch them here. */
1292 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
1293 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
1294 (pkt->hdr.cmd != REPLY_TX);
1295
1296 /* Based on type of command response or notification,
1297 * handle those that need handling via function in
bb8c093b 1298 * rx_handlers table. See iwl3945_setup_rx_handlers() */
b481de9c 1299 if (priv->rx_handlers[pkt->hdr.cmd]) {
af472a95 1300 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r, i,
b481de9c 1301 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
86ddbf62 1302 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
29b1b268 1303 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
b481de9c
ZY
1304 } else {
1305 /* No handling needed */
2f301227
ZY
1306 IWL_DEBUG_RX(priv,
1307 "r %d i %d No handler needed for %s, 0x%02x\n",
b481de9c
ZY
1308 r, i, get_cmd_string(pkt->hdr.cmd),
1309 pkt->hdr.cmd);
1310 }
1311
29b1b268
ZY
1312 /*
1313 * XXX: After here, we should always check rxb->page
1314 * against NULL before touching it or its virtual
1315 * memory (pkt). Because some rx_handler might have
1316 * already taken or freed the pages.
1317 */
1318
b481de9c 1319 if (reclaim) {
2f301227
ZY
1320 /* Invoke any callbacks, transfer the buffer to caller,
1321 * and fire off the (possibly) blocking iwl_send_cmd()
b481de9c 1322 * as we reclaim the driver command queue */
29b1b268 1323 if (rxb->page)
732587ab 1324 iwl_tx_cmd_complete(priv, rxb);
b481de9c 1325 else
39aadf8c 1326 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY
1327 }
1328
7300515d
ZY
1329 /* Reuse the page if possible. For notification packets and
1330 * SKBs that fail to Rx correctly, add them back into the
1331 * rx_free list for reuse later. */
1332 spin_lock_irqsave(&rxq->lock, flags);
2f301227 1333 if (rxb->page != NULL) {
7300515d
ZY
1334 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
1335 0, PAGE_SIZE << priv->hw_params.rx_page_order,
1336 PCI_DMA_FROMDEVICE);
1337 list_add_tail(&rxb->list, &rxq->rx_free);
1338 rxq->free_count++;
1339 } else
1340 list_add_tail(&rxb->list, &rxq->rx_used);
b481de9c 1341
b481de9c 1342 spin_unlock_irqrestore(&rxq->lock, flags);
7300515d 1343
b481de9c 1344 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
1345 /* If there are a lot of unused frames,
1346 * restock the Rx queue so ucode won't assert. */
1347 if (fill_rx) {
1348 count++;
1349 if (count >= 8) {
7300515d 1350 rxq->read = i;
d14d4440 1351 iwl3945_rx_replenish_now(priv);
5c0eef96
MA
1352 count = 0;
1353 }
1354 }
b481de9c
ZY
1355 }
1356
1357 /* Backtrack one entry */
7300515d 1358 rxq->read = i;
d14d4440
AK
1359 if (fill_rx)
1360 iwl3945_rx_replenish_now(priv);
1361 else
1362 iwl3945_rx_queue_restock(priv);
b481de9c
ZY
1363}
1364
0359facc 1365/* call this function to flush any scheduled tasklet */
4a8a4322 1366static inline void iwl_synchronize_irq(struct iwl_priv *priv)
0359facc 1367{
a96a27f9 1368 /* wait to make sure we flush pending tasklet*/
0359facc
MA
1369 synchronize_irq(priv->pci_dev->irq);
1370 tasklet_kill(&priv->irq_tasklet);
1371}
1372
b481de9c
ZY
1373static const char *desc_lookup(int i)
1374{
1375 switch (i) {
1376 case 1:
1377 return "FAIL";
1378 case 2:
1379 return "BAD_PARAM";
1380 case 3:
1381 return "BAD_CHECKSUM";
1382 case 4:
1383 return "NMI_INTERRUPT";
1384 case 5:
1385 return "SYSASSERT";
1386 case 6:
1387 return "FATAL_ERROR";
1388 }
1389
1390 return "UNKNOWN";
1391}
1392
1393#define ERROR_START_OFFSET (1 * sizeof(u32))
1394#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1395
b7a79404 1396void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
b481de9c
ZY
1397{
1398 u32 i;
1399 u32 desc, time, count, base, data1;
1400 u32 blink1, blink2, ilink1, ilink2;
b481de9c
ZY
1401
1402 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1403
bb8c093b 1404 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 1405 IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
b481de9c
ZY
1406 return;
1407 }
1408
b481de9c 1409
5d49f498 1410 count = iwl_read_targ_mem(priv, base);
b481de9c
ZY
1411
1412 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
15b1687c
WT
1413 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1414 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1415 priv->status, count);
b481de9c
ZY
1416 }
1417
15b1687c 1418 IWL_ERR(priv, "Desc Time asrtPC blink2 "
b481de9c
ZY
1419 "ilink1 nmiPC Line\n");
1420 for (i = ERROR_START_OFFSET;
1421 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
1422 i += ERROR_ELEM_SIZE) {
5d49f498 1423 desc = iwl_read_targ_mem(priv, base + i);
b481de9c 1424 time =
5d49f498 1425 iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32));
b481de9c 1426 blink1 =
5d49f498 1427 iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32));
b481de9c 1428 blink2 =
5d49f498 1429 iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32));
b481de9c 1430 ilink1 =
5d49f498 1431 iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32));
b481de9c 1432 ilink2 =
5d49f498 1433 iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32));
b481de9c 1434 data1 =
5d49f498 1435 iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32));
b481de9c 1436
15b1687c 1437 IWL_ERR(priv,
87563715 1438 "%-13s (0x%X) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
15b1687c
WT
1439 desc_lookup(desc), desc, time, blink1, blink2,
1440 ilink1, ilink2, data1);
be1a71a1
JB
1441 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, 0,
1442 0, blink1, blink2, ilink1, ilink2);
b481de9c 1443 }
b481de9c
ZY
1444}
1445
f58177b9 1446#define EVENT_START_OFFSET (6 * sizeof(u32))
b481de9c
ZY
1447
1448/**
bb8c093b 1449 * iwl3945_print_event_log - Dump error event log to syslog
b481de9c 1450 *
b481de9c 1451 */
b03d7d0f
WYG
1452static int iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
1453 u32 num_events, u32 mode,
1454 int pos, char **buf, size_t bufsz)
b481de9c
ZY
1455{
1456 u32 i;
1457 u32 base; /* SRAM byte address of event log header */
1458 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1459 u32 ptr; /* SRAM byte address of log data */
1460 u32 ev, time, data; /* event log data */
e5854471 1461 unsigned long reg_flags;
b481de9c
ZY
1462
1463 if (num_events == 0)
b03d7d0f 1464 return pos;
b481de9c
ZY
1465
1466 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1467
1468 if (mode == 0)
1469 event_size = 2 * sizeof(u32);
1470 else
1471 event_size = 3 * sizeof(u32);
1472
1473 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1474
e5854471
BC
1475 /* Make sure device is powered up for SRAM reads */
1476 spin_lock_irqsave(&priv->reg_lock, reg_flags);
1477 iwl_grab_nic_access(priv);
1478
1479 /* Set starting address; reads will auto-increment */
1480 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
1481 rmb();
1482
b481de9c
ZY
1483 /* "time" is actually "data" for mode 0 (no timestamp).
1484 * place event id # at far right for easier visual parsing. */
1485 for (i = 0; i < num_events; i++) {
e5854471
BC
1486 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1487 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
15b1687c
WT
1488 if (mode == 0) {
1489 /* data, ev */
b03d7d0f
WYG
1490 if (bufsz) {
1491 pos += scnprintf(*buf + pos, bufsz - pos,
1492 "0x%08x:%04u\n",
1493 time, ev);
1494 } else {
1495 IWL_ERR(priv, "0x%08x\t%04u\n", time, ev);
1496 trace_iwlwifi_dev_ucode_event(priv, 0,
1497 time, ev);
1498 }
15b1687c 1499 } else {
e5854471 1500 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b03d7d0f
WYG
1501 if (bufsz) {
1502 pos += scnprintf(*buf + pos, bufsz - pos,
1503 "%010u:0x%08x:%04u\n",
1504 time, data, ev);
1505 } else {
1506 IWL_ERR(priv, "%010u\t0x%08x\t%04u\n",
1507 time, data, ev);
1508 trace_iwlwifi_dev_ucode_event(priv, time,
1509 data, ev);
1510 }
b481de9c
ZY
1511 }
1512 }
e5854471
BC
1513
1514 /* Allow device to power down */
1515 iwl_release_nic_access(priv);
1516 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
b03d7d0f 1517 return pos;
b481de9c
ZY
1518}
1519
c341ddb2
WYG
1520/**
1521 * iwl3945_print_last_event_logs - Dump the newest # of event log to syslog
1522 */
b03d7d0f 1523static int iwl3945_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
c341ddb2 1524 u32 num_wraps, u32 next_entry,
b03d7d0f
WYG
1525 u32 size, u32 mode,
1526 int pos, char **buf, size_t bufsz)
c341ddb2
WYG
1527{
1528 /*
1529 * display the newest DEFAULT_LOG_ENTRIES entries
1530 * i.e the entries just before the next ont that uCode would fill.
1531 */
1532 if (num_wraps) {
1533 if (next_entry < size) {
b03d7d0f
WYG
1534 pos = iwl3945_print_event_log(priv,
1535 capacity - (size - next_entry),
1536 size - next_entry, mode,
1537 pos, buf, bufsz);
1538 pos = iwl3945_print_event_log(priv, 0,
1539 next_entry, mode,
1540 pos, buf, bufsz);
c341ddb2 1541 } else
b03d7d0f
WYG
1542 pos = iwl3945_print_event_log(priv, next_entry - size,
1543 size, mode,
1544 pos, buf, bufsz);
c341ddb2
WYG
1545 } else {
1546 if (next_entry < size)
b03d7d0f
WYG
1547 pos = iwl3945_print_event_log(priv, 0,
1548 next_entry, mode,
1549 pos, buf, bufsz);
c341ddb2 1550 else
b03d7d0f
WYG
1551 pos = iwl3945_print_event_log(priv, next_entry - size,
1552 size, mode,
1553 pos, buf, bufsz);
c341ddb2 1554 }
b03d7d0f 1555 return pos;
c341ddb2
WYG
1556}
1557
c341ddb2
WYG
1558#define DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES (20)
1559
b03d7d0f
WYG
1560int iwl3945_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
1561 char **buf, bool display)
b481de9c 1562{
b481de9c
ZY
1563 u32 base; /* SRAM byte address of event log header */
1564 u32 capacity; /* event log capacity in # entries */
1565 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1566 u32 num_wraps; /* # times uCode wrapped to top of log */
1567 u32 next_entry; /* index of next entry to be written by uCode */
1568 u32 size; /* # entries that we'll print */
b03d7d0f
WYG
1569 int pos = 0;
1570 size_t bufsz = 0;
b481de9c
ZY
1571
1572 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 1573 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 1574 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
937c397e 1575 return -EINVAL;
b481de9c
ZY
1576 }
1577
b481de9c 1578 /* event log header */
5d49f498
AK
1579 capacity = iwl_read_targ_mem(priv, base);
1580 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1581 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1582 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
b481de9c 1583
7cb1b088 1584 if (capacity > priv->cfg->base_params->max_event_log_size) {
84c40692 1585 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
7cb1b088
WYG
1586 capacity, priv->cfg->base_params->max_event_log_size);
1587 capacity = priv->cfg->base_params->max_event_log_size;
84c40692
BC
1588 }
1589
7cb1b088 1590 if (next_entry > priv->cfg->base_params->max_event_log_size) {
84c40692 1591 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
7cb1b088
WYG
1592 next_entry, priv->cfg->base_params->max_event_log_size);
1593 next_entry = priv->cfg->base_params->max_event_log_size;
84c40692
BC
1594 }
1595
b481de9c
ZY
1596 size = num_wraps ? capacity : next_entry;
1597
1598 /* bail out if nothing in log */
1599 if (size == 0) {
15b1687c 1600 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
b03d7d0f 1601 return pos;
b481de9c
ZY
1602 }
1603
c341ddb2 1604#ifdef CONFIG_IWLWIFI_DEBUG
521d9bce 1605 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
c341ddb2
WYG
1606 size = (size > DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES)
1607 ? DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES : size;
1608#else
1609 size = (size > DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES)
1610 ? DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES : size;
1611#endif
1612
1613 IWL_ERR(priv, "Start IWL Event Log Dump: display last %d count\n",
1614 size);
b481de9c 1615
c341ddb2 1616#ifdef CONFIG_IWLWIFI_DEBUG
b03d7d0f
WYG
1617 if (display) {
1618 if (full_log)
1619 bufsz = capacity * 48;
1620 else
1621 bufsz = size * 48;
1622 *buf = kmalloc(bufsz, GFP_KERNEL);
1623 if (!*buf)
937c397e 1624 return -ENOMEM;
b03d7d0f 1625 }
c341ddb2
WYG
1626 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
1627 /* if uCode has wrapped back to top of log,
1628 * start at the oldest entry,
1629 * i.e the next one that uCode would fill.
1630 */
1631 if (num_wraps)
b03d7d0f
WYG
1632 pos = iwl3945_print_event_log(priv, next_entry,
1633 capacity - next_entry, mode,
1634 pos, buf, bufsz);
c341ddb2
WYG
1635
1636 /* (then/else) start at top of log */
b03d7d0f
WYG
1637 pos = iwl3945_print_event_log(priv, 0, next_entry, mode,
1638 pos, buf, bufsz);
c341ddb2 1639 } else
b03d7d0f
WYG
1640 pos = iwl3945_print_last_event_logs(priv, capacity, num_wraps,
1641 next_entry, size, mode,
1642 pos, buf, bufsz);
b7a79404 1643#else
b03d7d0f
WYG
1644 pos = iwl3945_print_last_event_logs(priv, capacity, num_wraps,
1645 next_entry, size, mode,
1646 pos, buf, bufsz);
c341ddb2 1647#endif
b03d7d0f 1648 return pos;
b7a79404
RC
1649}
1650
4a8a4322 1651static void iwl3945_irq_tasklet(struct iwl_priv *priv)
b481de9c
ZY
1652{
1653 u32 inta, handled = 0;
1654 u32 inta_fh;
1655 unsigned long flags;
d08853a3 1656#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
1657 u32 inta_mask;
1658#endif
1659
1660 spin_lock_irqsave(&priv->lock, flags);
1661
1662 /* Ack/clear/reset pending uCode interrupts.
1663 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1664 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
5d49f498
AK
1665 inta = iwl_read32(priv, CSR_INT);
1666 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY
1667
1668 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1669 * Any new interrupts that happen after this, either while we're
1670 * in this tasklet, or later, will show up in next ISR/tasklet. */
5d49f498
AK
1671 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1672 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 1673
d08853a3 1674#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1675 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
9fbab516 1676 /* just for debug */
5d49f498 1677 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 1678 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY
1679 inta, inta_mask, inta_fh);
1680 }
1681#endif
1682
2f301227
ZY
1683 spin_unlock_irqrestore(&priv->lock, flags);
1684
b481de9c
ZY
1685 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1686 * atomic, make sure that inta covers all the interrupts that
1687 * we've discovered, even if FH interrupt came in just after
1688 * reading CSR_INT. */
6f83eaa1 1689 if (inta_fh & CSR39_FH_INT_RX_MASK)
b481de9c 1690 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 1691 if (inta_fh & CSR39_FH_INT_TX_MASK)
b481de9c
ZY
1692 inta |= CSR_INT_BIT_FH_TX;
1693
1694 /* Now service all interrupt bits discovered above. */
1695 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1696 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY
1697
1698 /* Tell the device to stop sending interrupts */
ed3b932e 1699 iwl_disable_interrupts(priv);
b481de9c 1700
86ddbf62 1701 priv->isr_stats.hw++;
8ccde88a 1702 iwl_irq_handle_error(priv);
b481de9c
ZY
1703
1704 handled |= CSR_INT_BIT_HW_ERR;
1705
b481de9c
ZY
1706 return;
1707 }
1708
d08853a3 1709#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1710 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
b481de9c 1711 /* NIC fires this, but we don't use it, redundant with WAKEUP */
86ddbf62 1712 if (inta & CSR_INT_BIT_SCD) {
e1623446 1713 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1714 "the frame/frames.\n");
86ddbf62
AK
1715 priv->isr_stats.sch++;
1716 }
b481de9c
ZY
1717
1718 /* Alive notification via Rx interrupt will do the real work */
86ddbf62 1719 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 1720 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
86ddbf62
AK
1721 priv->isr_stats.alive++;
1722 }
b481de9c
ZY
1723 }
1724#endif
1725 /* Safely ignore these bits for debug checks below */
25c03d8e 1726 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1727
b481de9c
ZY
1728 /* Error detected by uCode */
1729 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT
1730 IWL_ERR(priv, "Microcode SW error detected. "
1731 "Restarting 0x%X.\n", inta);
86ddbf62 1732 priv->isr_stats.sw++;
8ccde88a 1733 iwl_irq_handle_error(priv);
b481de9c
ZY
1734 handled |= CSR_INT_BIT_SW_ERR;
1735 }
1736
1737 /* uCode wakes up after power-down sleep */
1738 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1739 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
141c43a3 1740 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
4f3602c8
SO
1741 iwl_txq_update_write_ptr(priv, &priv->txq[0]);
1742 iwl_txq_update_write_ptr(priv, &priv->txq[1]);
1743 iwl_txq_update_write_ptr(priv, &priv->txq[2]);
1744 iwl_txq_update_write_ptr(priv, &priv->txq[3]);
1745 iwl_txq_update_write_ptr(priv, &priv->txq[4]);
1746 iwl_txq_update_write_ptr(priv, &priv->txq[5]);
b481de9c 1747
86ddbf62 1748 priv->isr_stats.wakeup++;
b481de9c
ZY
1749 handled |= CSR_INT_BIT_WAKEUP;
1750 }
1751
1752 /* All uCode command responses, including Tx command responses,
1753 * Rx "responses" (frame-received notification), and other
1754 * notifications from uCode come through here*/
1755 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
bb8c093b 1756 iwl3945_rx_handle(priv);
86ddbf62 1757 priv->isr_stats.rx++;
b481de9c
ZY
1758 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1759 }
1760
1761 if (inta & CSR_INT_BIT_FH_TX) {
e1623446 1762 IWL_DEBUG_ISR(priv, "Tx interrupt\n");
86ddbf62 1763 priv->isr_stats.tx++;
b481de9c 1764
5d49f498 1765 iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
a8b50a0a
MA
1766 iwl_write_direct32(priv, FH39_TCSR_CREDIT
1767 (FH39_SRVC_CHNL), 0x0);
b481de9c
ZY
1768 handled |= CSR_INT_BIT_FH_TX;
1769 }
1770
86ddbf62 1771 if (inta & ~handled) {
15b1687c 1772 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
86ddbf62
AK
1773 priv->isr_stats.unhandled++;
1774 }
b481de9c 1775
40cefda9 1776 if (inta & ~priv->inta_mask) {
39aadf8c 1777 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1778 inta & ~priv->inta_mask);
39aadf8c 1779 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY
1780 }
1781
1782 /* Re-enable all interrupts */
0359facc
MA
1783 /* only Re-enable if disabled by irq */
1784 if (test_bit(STATUS_INT_ENABLED, &priv->status))
ed3b932e 1785 iwl_enable_interrupts(priv);
b481de9c 1786
d08853a3 1787#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1788 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
5d49f498
AK
1789 inta = iwl_read32(priv, CSR_INT);
1790 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1791 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1792 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY
1793 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1794 }
1795#endif
b481de9c
ZY
1796}
1797
14023641
AK
1798static int iwl3945_get_single_channel_for_scan(struct iwl_priv *priv,
1799 struct ieee80211_vif *vif,
1800 enum ieee80211_band band,
1801 struct iwl3945_scan_channel *scan_ch)
1802{
1803 const struct ieee80211_supported_band *sband;
1804 u16 passive_dwell = 0;
1805 u16 active_dwell = 0;
1806 int added = 0;
1807 u8 channel = 0;
1808
1809 sband = iwl_get_hw_mode(priv, band);
1810 if (!sband) {
1811 IWL_ERR(priv, "invalid band\n");
1812 return added;
1813 }
1814
1815 active_dwell = iwl_get_active_dwell_time(priv, band, 0);
1816 passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1817
1818 if (passive_dwell <= active_dwell)
1819 passive_dwell = active_dwell + 1;
1820
1821
1822 channel = iwl_get_single_channel_number(priv, band);
1823
1824 if (channel) {
1825 scan_ch->channel = channel;
1826 scan_ch->type = 0; /* passive */
1827 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1828 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1829 /* Set txpower levels to defaults */
1830 scan_ch->tpc.dsp_atten = 110;
1831 if (band == IEEE80211_BAND_5GHZ)
1832 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
1833 else
1834 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
1835 added++;
1836 } else
1837 IWL_ERR(priv, "no valid channel found\n");
1838 return added;
1839}
1840
4a8a4322 1841static int iwl3945_get_channels_for_scan(struct iwl_priv *priv,
8318d78a 1842 enum ieee80211_band band,
f9340520 1843 u8 is_active, u8 n_probes,
1dda6d28
JB
1844 struct iwl3945_scan_channel *scan_ch,
1845 struct ieee80211_vif *vif)
b481de9c 1846{
4e05c234 1847 struct ieee80211_channel *chan;
8318d78a 1848 const struct ieee80211_supported_band *sband;
d20b3c65 1849 const struct iwl_channel_info *ch_info;
b481de9c
ZY
1850 u16 passive_dwell = 0;
1851 u16 active_dwell = 0;
1852 int added, i;
1853
cbba18c6 1854 sband = iwl_get_hw_mode(priv, band);
8318d78a 1855 if (!sband)
b481de9c
ZY
1856 return 0;
1857
77fecfb8 1858 active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
1dda6d28 1859 passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
b481de9c 1860
8f4807a1
AK
1861 if (passive_dwell <= active_dwell)
1862 passive_dwell = active_dwell + 1;
1863
4e05c234
JB
1864 for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
1865 chan = priv->scan_request->channels[i];
1866
1867 if (chan->band != band)
182e2e66
JB
1868 continue;
1869
4e05c234 1870 scan_ch->channel = chan->hw_value;
b481de9c 1871
e6148917 1872 ch_info = iwl_get_channel_info(priv, band, scan_ch->channel);
b481de9c 1873 if (!is_channel_valid(ch_info)) {
e1623446 1874 IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
b481de9c
ZY
1875 scan_ch->channel);
1876 continue;
1877 }
1878
011a0330
AK
1879 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1880 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1881 /* If passive , set up for auto-switch
1882 * and use long active_dwell time.
1883 */
b481de9c 1884 if (!is_active || is_channel_passive(ch_info) ||
4e05c234 1885 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
b481de9c 1886 scan_ch->type = 0; /* passive */
011a0330
AK
1887 if (IWL_UCODE_API(priv->ucode_ver) == 1)
1888 scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
1889 } else {
b481de9c 1890 scan_ch->type = 1; /* active */
011a0330 1891 }
b481de9c 1892
011a0330
AK
1893 /* Set direct probe bits. These may be used both for active
1894 * scan channels (probes gets sent right away),
1895 * or for passive channels (probes get se sent only after
1896 * hearing clear Rx packet).*/
1897 if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
1898 if (n_probes)
0d21044e 1899 scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes);
011a0330
AK
1900 } else {
1901 /* uCode v1 does not allow setting direct probe bits on
1902 * passive channel. */
1903 if ((scan_ch->type & 1) && n_probes)
0d21044e 1904 scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes);
011a0330 1905 }
b481de9c 1906
9fbab516 1907 /* Set txpower levels to defaults */
b481de9c
ZY
1908 scan_ch->tpc.dsp_atten = 110;
1909 /* scan_pwr_info->tpc.dsp_atten; */
1910
1911 /*scan_pwr_info->tpc.tx_gain; */
8318d78a 1912 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY
1913 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
1914 else {
1915 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
1916 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
9fbab516 1917 * power level:
8a1b0245 1918 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
b481de9c
ZY
1919 */
1920 }
1921
e1623446 1922 IWL_DEBUG_SCAN(priv, "Scanning %d [%s %d]\n",
b481de9c
ZY
1923 scan_ch->channel,
1924 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
1925 (scan_ch->type & 1) ?
1926 active_dwell : passive_dwell);
1927
1928 scan_ch++;
1929 added++;
1930 }
1931
91dd6c27 1932 IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added);
b481de9c
ZY
1933 return added;
1934}
1935
4a8a4322 1936static void iwl3945_init_hw_rates(struct iwl_priv *priv,
b481de9c
ZY
1937 struct ieee80211_rate *rates)
1938{
1939 int i;
1940
8e1a53c6 1941 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
8318d78a
JB
1942 rates[i].bitrate = iwl3945_rates[i].ieee * 5;
1943 rates[i].hw_value = i; /* Rate scaling will work on indexes */
1944 rates[i].hw_value_short = i;
1945 rates[i].flags = 0;
d9829a67 1946 if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
b481de9c 1947 /*
8318d78a 1948 * If CCK != 1M then set short preamble rate flag.
b481de9c 1949 */
bb8c093b 1950 rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
8318d78a 1951 0 : IEEE80211_RATE_SHORT_PREAMBLE;
b481de9c 1952 }
b481de9c
ZY
1953 }
1954}
1955
b481de9c
ZY
1956/******************************************************************************
1957 *
1958 * uCode download functions
1959 *
1960 ******************************************************************************/
1961
4a8a4322 1962static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1963{
98c92211
TW
1964 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1965 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1966 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1967 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1968 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1969 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY
1970}
1971
1972/**
bb8c093b 1973 * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
b481de9c
ZY
1974 * looking at all data.
1975 */
4a8a4322 1976static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len)
b481de9c
ZY
1977{
1978 u32 val;
1979 u32 save_len = len;
1980 int rc = 0;
1981 u32 errcnt;
1982
e1623446 1983 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b481de9c 1984
5d49f498 1985 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 1986 IWL39_RTC_INST_LOWER_BOUND);
b481de9c
ZY
1987
1988 errcnt = 0;
1989 for (; len > 0; len -= sizeof(u32), image++) {
1990 /* read data comes through single port, auto-incr addr */
1991 /* NOTE: Use the debugless read so we don't flood kernel log
1992 * if IWL_DL_IO is set */
5d49f498 1993 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c 1994 if (val != le32_to_cpu(*image)) {
15b1687c 1995 IWL_ERR(priv, "uCode INST section is invalid at "
b481de9c
ZY
1996 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1997 save_len - len, val, le32_to_cpu(*image));
1998 rc = -EIO;
1999 errcnt++;
2000 if (errcnt >= 20)
2001 break;
2002 }
2003 }
2004
b481de9c
ZY
2005
2006 if (!errcnt)
e1623446
TW
2007 IWL_DEBUG_INFO(priv,
2008 "ucode image in INSTRUCTION memory is good\n");
b481de9c
ZY
2009
2010 return rc;
2011}
2012
2013
2014/**
bb8c093b 2015 * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
b481de9c
ZY
2016 * using sample data 100 bytes apart. If these sample points are good,
2017 * it's a pretty good bet that everything between them is good, too.
2018 */
4a8a4322 2019static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
b481de9c
ZY
2020{
2021 u32 val;
2022 int rc = 0;
2023 u32 errcnt = 0;
2024 u32 i;
2025
e1623446 2026 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b481de9c 2027
b481de9c
ZY
2028 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
2029 /* read data comes through single port, auto-incr addr */
2030 /* NOTE: Use the debugless read so we don't flood kernel log
2031 * if IWL_DL_IO is set */
5d49f498 2032 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 2033 i + IWL39_RTC_INST_LOWER_BOUND);
5d49f498 2034 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY
2035 if (val != le32_to_cpu(*image)) {
2036#if 0 /* Enable this if you want to see details */
15b1687c 2037 IWL_ERR(priv, "uCode INST section is invalid at "
b481de9c
ZY
2038 "offset 0x%x, is 0x%x, s/b 0x%x\n",
2039 i, val, *image);
2040#endif
2041 rc = -EIO;
2042 errcnt++;
2043 if (errcnt >= 3)
2044 break;
2045 }
2046 }
2047
b481de9c
ZY
2048 return rc;
2049}
2050
2051
2052/**
bb8c093b 2053 * iwl3945_verify_ucode - determine which instruction image is in SRAM,
b481de9c
ZY
2054 * and verify its contents
2055 */
4a8a4322 2056static int iwl3945_verify_ucode(struct iwl_priv *priv)
b481de9c
ZY
2057{
2058 __le32 *image;
2059 u32 len;
2060 int rc = 0;
2061
2062 /* Try bootstrap */
2063 image = (__le32 *)priv->ucode_boot.v_addr;
2064 len = priv->ucode_boot.len;
bb8c093b 2065 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c 2066 if (rc == 0) {
e1623446 2067 IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
b481de9c
ZY
2068 return 0;
2069 }
2070
2071 /* Try initialize */
2072 image = (__le32 *)priv->ucode_init.v_addr;
2073 len = priv->ucode_init.len;
bb8c093b 2074 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c 2075 if (rc == 0) {
e1623446 2076 IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
b481de9c
ZY
2077 return 0;
2078 }
2079
2080 /* Try runtime/protocol */
2081 image = (__le32 *)priv->ucode_code.v_addr;
2082 len = priv->ucode_code.len;
bb8c093b 2083 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c 2084 if (rc == 0) {
e1623446 2085 IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
b481de9c
ZY
2086 return 0;
2087 }
2088
15b1687c 2089 IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
b481de9c 2090
9fbab516
BC
2091 /* Since nothing seems to match, show first several data entries in
2092 * instruction SRAM, so maybe visual inspection will give a clue.
2093 * Selection of bootstrap image (vs. other images) is arbitrary. */
b481de9c
ZY
2094 image = (__le32 *)priv->ucode_boot.v_addr;
2095 len = priv->ucode_boot.len;
bb8c093b 2096 rc = iwl3945_verify_inst_full(priv, image, len);
b481de9c
ZY
2097
2098 return rc;
2099}
2100
4a8a4322 2101static void iwl3945_nic_start(struct iwl_priv *priv)
b481de9c
ZY
2102{
2103 /* Remove all resets to allow NIC to operate */
5d49f498 2104 iwl_write32(priv, CSR_RESET, 0);
b481de9c
ZY
2105}
2106
93b1a2f9
JB
2107#define IWL3945_UCODE_GET(item) \
2108static u32 iwl3945_ucode_get_##item(const struct iwl_ucode_header *ucode)\
2109{ \
2110 return le32_to_cpu(ucode->u.v1.item); \
2111}
2112
2113static u32 iwl3945_ucode_get_header_size(u32 api_ver)
2114{
22adba2a 2115 return 24;
93b1a2f9
JB
2116}
2117
2118static u8 *iwl3945_ucode_get_data(const struct iwl_ucode_header *ucode)
2119{
2120 return (u8 *) ucode->u.v1.data;
2121}
2122
2123IWL3945_UCODE_GET(inst_size);
2124IWL3945_UCODE_GET(data_size);
2125IWL3945_UCODE_GET(init_size);
2126IWL3945_UCODE_GET(init_data_size);
2127IWL3945_UCODE_GET(boot_size);
2128
b481de9c 2129/**
bb8c093b 2130 * iwl3945_read_ucode - Read uCode images from disk file.
b481de9c
ZY
2131 *
2132 * Copy into buffers for card to fetch via bus-mastering
2133 */
4a8a4322 2134static int iwl3945_read_ucode(struct iwl_priv *priv)
b481de9c 2135{
cc0f555d 2136 const struct iwl_ucode_header *ucode;
a0987a8d 2137 int ret = -EINVAL, index;
b481de9c
ZY
2138 const struct firmware *ucode_raw;
2139 /* firmware file name contains uCode/driver compatibility version */
a0987a8d
RC
2140 const char *name_pre = priv->cfg->fw_name_pre;
2141 const unsigned int api_max = priv->cfg->ucode_api_max;
2142 const unsigned int api_min = priv->cfg->ucode_api_min;
2143 char buf[25];
b481de9c
ZY
2144 u8 *src;
2145 size_t len;
a0987a8d 2146 u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
b481de9c
ZY
2147
2148 /* Ask kernel firmware_class module to get the boot firmware off disk.
2149 * request_firmware() is synchronous, file is in memory on return. */
a0987a8d
RC
2150 for (index = api_max; index >= api_min; index--) {
2151 sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
2152 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
2153 if (ret < 0) {
15b1687c 2154 IWL_ERR(priv, "%s firmware file req failed: %d\n",
a0987a8d
RC
2155 buf, ret);
2156 if (ret == -ENOENT)
2157 continue;
2158 else
2159 goto error;
2160 } else {
2161 if (index < api_max)
15b1687c
WT
2162 IWL_ERR(priv, "Loaded firmware %s, "
2163 "which is deprecated. "
2164 " Please use API v%u instead.\n",
a0987a8d 2165 buf, api_max);
e1623446
TW
2166 IWL_DEBUG_INFO(priv, "Got firmware '%s' file "
2167 "(%zd bytes) from disk\n",
a0987a8d
RC
2168 buf, ucode_raw->size);
2169 break;
2170 }
b481de9c
ZY
2171 }
2172
a0987a8d
RC
2173 if (ret < 0)
2174 goto error;
b481de9c
ZY
2175
2176 /* Make sure that we got at least our header! */
93b1a2f9 2177 if (ucode_raw->size < iwl3945_ucode_get_header_size(1)) {
15b1687c 2178 IWL_ERR(priv, "File size way too small!\n");
90e759d1 2179 ret = -EINVAL;
b481de9c
ZY
2180 goto err_release;
2181 }
2182
2183 /* Data from ucode file: header followed by uCode images */
cc0f555d 2184 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 2185
c02b3acd 2186 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 2187 api_ver = IWL_UCODE_API(priv->ucode_ver);
93b1a2f9
JB
2188 inst_size = iwl3945_ucode_get_inst_size(ucode);
2189 data_size = iwl3945_ucode_get_data_size(ucode);
2190 init_size = iwl3945_ucode_get_init_size(ucode);
2191 init_data_size = iwl3945_ucode_get_init_data_size(ucode);
2192 boot_size = iwl3945_ucode_get_boot_size(ucode);
2193 src = iwl3945_ucode_get_data(ucode);
b481de9c 2194
a0987a8d
RC
2195 /* api_ver should match the api version forming part of the
2196 * firmware filename ... but we don't check for that and only rely
877d0310 2197 * on the API version read from firmware header from here on forward */
a0987a8d
RC
2198
2199 if (api_ver < api_min || api_ver > api_max) {
15b1687c 2200 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC
2201 "Driver supports v%u, firmware is v%u.\n",
2202 api_max, api_ver);
2203 priv->ucode_ver = 0;
2204 ret = -EINVAL;
2205 goto err_release;
2206 }
2207 if (api_ver != api_max)
15b1687c 2208 IWL_ERR(priv, "Firmware has old API version. Expected %u, "
a0987a8d
RC
2209 "got %u. New firmware can be obtained "
2210 "from http://www.intellinuxwireless.org.\n",
2211 api_max, api_ver);
2212
978785a3
TW
2213 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
2214 IWL_UCODE_MAJOR(priv->ucode_ver),
2215 IWL_UCODE_MINOR(priv->ucode_ver),
2216 IWL_UCODE_API(priv->ucode_ver),
2217 IWL_UCODE_SERIAL(priv->ucode_ver));
2218
5ebeb5a6
RC
2219 snprintf(priv->hw->wiphy->fw_version,
2220 sizeof(priv->hw->wiphy->fw_version),
2221 "%u.%u.%u.%u",
2222 IWL_UCODE_MAJOR(priv->ucode_ver),
2223 IWL_UCODE_MINOR(priv->ucode_ver),
2224 IWL_UCODE_API(priv->ucode_ver),
2225 IWL_UCODE_SERIAL(priv->ucode_ver));
2226
e1623446 2227 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
a0987a8d 2228 priv->ucode_ver);
e1623446
TW
2229 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
2230 inst_size);
2231 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
2232 data_size);
2233 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
2234 init_size);
2235 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
2236 init_data_size);
2237 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
2238 boot_size);
b481de9c 2239
a0987a8d 2240
b481de9c 2241 /* Verify size of file vs. image size info in file's header */
93b1a2f9 2242 if (ucode_raw->size != iwl3945_ucode_get_header_size(api_ver) +
b481de9c
ZY
2243 inst_size + data_size + init_size +
2244 init_data_size + boot_size) {
2245
cc0f555d
JS
2246 IWL_DEBUG_INFO(priv,
2247 "uCode file size %zd does not match expected size\n",
2248 ucode_raw->size);
90e759d1 2249 ret = -EINVAL;
b481de9c
ZY
2250 goto err_release;
2251 }
2252
2253 /* Verify that uCode images will fit in card's SRAM */
250bdd21 2254 if (inst_size > IWL39_MAX_INST_SIZE) {
e1623446 2255 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
90e759d1
TW
2256 inst_size);
2257 ret = -EINVAL;
b481de9c
ZY
2258 goto err_release;
2259 }
2260
250bdd21 2261 if (data_size > IWL39_MAX_DATA_SIZE) {
e1623446 2262 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
90e759d1
TW
2263 data_size);
2264 ret = -EINVAL;
b481de9c
ZY
2265 goto err_release;
2266 }
250bdd21 2267 if (init_size > IWL39_MAX_INST_SIZE) {
e1623446
TW
2268 IWL_DEBUG_INFO(priv,
2269 "uCode init instr len %d too large to fit in\n",
90e759d1
TW
2270 init_size);
2271 ret = -EINVAL;
b481de9c
ZY
2272 goto err_release;
2273 }
250bdd21 2274 if (init_data_size > IWL39_MAX_DATA_SIZE) {
e1623446
TW
2275 IWL_DEBUG_INFO(priv,
2276 "uCode init data len %d too large to fit in\n",
90e759d1
TW
2277 init_data_size);
2278 ret = -EINVAL;
b481de9c
ZY
2279 goto err_release;
2280 }
250bdd21 2281 if (boot_size > IWL39_MAX_BSM_SIZE) {
e1623446
TW
2282 IWL_DEBUG_INFO(priv,
2283 "uCode boot instr len %d too large to fit in\n",
90e759d1
TW
2284 boot_size);
2285 ret = -EINVAL;
b481de9c
ZY
2286 goto err_release;
2287 }
2288
2289 /* Allocate ucode buffers for card's bus-master loading ... */
2290
2291 /* Runtime instructions and 2 copies of data:
2292 * 1) unmodified from disk
2293 * 2) backup cache for save/restore during power-downs */
2294 priv->ucode_code.len = inst_size;
98c92211 2295 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY
2296
2297 priv->ucode_data.len = data_size;
98c92211 2298 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY
2299
2300 priv->ucode_data_backup.len = data_size;
98c92211 2301 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 2302
90e759d1
TW
2303 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2304 !priv->ucode_data_backup.v_addr)
2305 goto err_pci_alloc;
b481de9c
ZY
2306
2307 /* Initialization instructions and data */
90e759d1
TW
2308 if (init_size && init_data_size) {
2309 priv->ucode_init.len = init_size;
98c92211 2310 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW
2311
2312 priv->ucode_init_data.len = init_data_size;
98c92211 2313 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW
2314
2315 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2316 goto err_pci_alloc;
2317 }
b481de9c
ZY
2318
2319 /* Bootstrap (instructions only, no data) */
90e759d1
TW
2320 if (boot_size) {
2321 priv->ucode_boot.len = boot_size;
98c92211 2322 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 2323
90e759d1
TW
2324 if (!priv->ucode_boot.v_addr)
2325 goto err_pci_alloc;
2326 }
b481de9c
ZY
2327
2328 /* Copy images into buffers for card's bus-master reads ... */
2329
2330 /* Runtime instructions (first block of data in file) */
cc0f555d 2331 len = inst_size;
e1623446
TW
2332 IWL_DEBUG_INFO(priv,
2333 "Copying (but not loading) uCode instr len %zd\n", len);
b481de9c 2334 memcpy(priv->ucode_code.v_addr, src, len);
cc0f555d
JS
2335 src += len;
2336
e1623446 2337 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY
2338 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2339
2340 /* Runtime data (2nd block)
bb8c093b 2341 * NOTE: Copy into backup buffer will be done in iwl3945_up() */
cc0f555d 2342 len = data_size;
e1623446
TW
2343 IWL_DEBUG_INFO(priv,
2344 "Copying (but not loading) uCode data len %zd\n", len);
b481de9c
ZY
2345 memcpy(priv->ucode_data.v_addr, src, len);
2346 memcpy(priv->ucode_data_backup.v_addr, src, len);
cc0f555d 2347 src += len;
b481de9c
ZY
2348
2349 /* Initialization instructions (3rd block) */
2350 if (init_size) {
cc0f555d 2351 len = init_size;
e1623446
TW
2352 IWL_DEBUG_INFO(priv,
2353 "Copying (but not loading) init instr len %zd\n", len);
b481de9c 2354 memcpy(priv->ucode_init.v_addr, src, len);
cc0f555d 2355 src += len;
b481de9c
ZY
2356 }
2357
2358 /* Initialization data (4th block) */
2359 if (init_data_size) {
cc0f555d 2360 len = init_data_size;
e1623446
TW
2361 IWL_DEBUG_INFO(priv,
2362 "Copying (but not loading) init data len %zd\n", len);
b481de9c 2363 memcpy(priv->ucode_init_data.v_addr, src, len);
cc0f555d 2364 src += len;
b481de9c
ZY
2365 }
2366
2367 /* Bootstrap instructions (5th block) */
cc0f555d 2368 len = boot_size;
e1623446
TW
2369 IWL_DEBUG_INFO(priv,
2370 "Copying (but not loading) boot instr len %zd\n", len);
b481de9c
ZY
2371 memcpy(priv->ucode_boot.v_addr, src, len);
2372
2373 /* We have our copies now, allow OS release its copies */
2374 release_firmware(ucode_raw);
2375 return 0;
2376
2377 err_pci_alloc:
15b1687c 2378 IWL_ERR(priv, "failed to allocate pci memory\n");
90e759d1 2379 ret = -ENOMEM;
bb8c093b 2380 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY
2381
2382 err_release:
2383 release_firmware(ucode_raw);
2384
2385 error:
90e759d1 2386 return ret;
b481de9c
ZY
2387}
2388
2389
2390/**
bb8c093b 2391 * iwl3945_set_ucode_ptrs - Set uCode address location
b481de9c
ZY
2392 *
2393 * Tell initialization uCode where to find runtime uCode.
2394 *
2395 * BSM registers initially contain pointers to initialization uCode.
2396 * We need to replace them to load runtime uCode inst and data,
2397 * and to save runtime data when powering down.
2398 */
4a8a4322 2399static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv)
b481de9c
ZY
2400{
2401 dma_addr_t pinst;
2402 dma_addr_t pdata;
b481de9c
ZY
2403
2404 /* bits 31:0 for 3945 */
2405 pinst = priv->ucode_code.p_addr;
2406 pdata = priv->ucode_data_backup.p_addr;
2407
b481de9c 2408 /* Tell bootstrap uCode where to find image to load */
5d49f498
AK
2409 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2410 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2411 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
b481de9c
ZY
2412 priv->ucode_data.len);
2413
a96a27f9 2414 /* Inst byte count must be last to set up, bit 31 signals uCode
b481de9c 2415 * that all new ptr/size info is in place */
5d49f498 2416 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
b481de9c
ZY
2417 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
2418
e1623446 2419 IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n");
b481de9c 2420
a8b50a0a 2421 return 0;
b481de9c
ZY
2422}
2423
2424/**
bb8c093b 2425 * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
b481de9c
ZY
2426 *
2427 * Called after REPLY_ALIVE notification received from "initialize" uCode.
2428 *
b481de9c 2429 * Tell "initialize" uCode to go ahead and load the runtime uCode.
9fbab516 2430 */
4a8a4322 2431static void iwl3945_init_alive_start(struct iwl_priv *priv)
b481de9c
ZY
2432{
2433 /* Check alive response for "valid" sign from uCode */
2434 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
2435 /* We had an error bringing up the hardware, so take it
2436 * all the way back down so we can try again */
e1623446 2437 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
b481de9c
ZY
2438 goto restart;
2439 }
2440
2441 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
2442 * This is a paranoid check, because we would not have gotten the
2443 * "initialize" alive if code weren't properly loaded. */
bb8c093b 2444 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY
2445 /* Runtime instruction load was bad;
2446 * take it all the way back down so we can try again */
e1623446 2447 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
b481de9c
ZY
2448 goto restart;
2449 }
2450
2451 /* Send pointers to protocol/runtime uCode image ... init code will
2452 * load and launch runtime uCode, which will send us another "Alive"
2453 * notification. */
e1623446 2454 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
bb8c093b 2455 if (iwl3945_set_ucode_ptrs(priv)) {
b481de9c
ZY
2456 /* Runtime instruction load won't happen;
2457 * take it all the way back down so we can try again */
e1623446 2458 IWL_DEBUG_INFO(priv, "Couldn't set up uCode pointers.\n");
b481de9c
ZY
2459 goto restart;
2460 }
2461 return;
2462
2463 restart:
2464 queue_work(priv->workqueue, &priv->restart);
2465}
2466
b481de9c 2467/**
bb8c093b 2468 * iwl3945_alive_start - called after REPLY_ALIVE notification received
b481de9c 2469 * from protocol/runtime uCode (initialization uCode's
bb8c093b 2470 * Alive gets handled by iwl3945_init_alive_start()).
b481de9c 2471 */
4a8a4322 2472static void iwl3945_alive_start(struct iwl_priv *priv)
b481de9c 2473{
b481de9c
ZY
2474 int thermal_spin = 0;
2475 u32 rfkill;
246ed355 2476 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
b481de9c 2477
e1623446 2478 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY
2479
2480 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2481 /* We had an error bringing up the hardware, so take it
2482 * all the way back down so we can try again */
e1623446 2483 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY
2484 goto restart;
2485 }
2486
2487 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2488 * This is a paranoid check, because we would not have gotten the
2489 * "runtime" alive if code weren't properly loaded. */
bb8c093b 2490 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY
2491 /* Runtime instruction load was bad;
2492 * take it all the way back down so we can try again */
e1623446 2493 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY
2494 goto restart;
2495 }
2496
5d49f498 2497 rfkill = iwl_read_prph(priv, APMG_RFKILL_REG);
e1623446 2498 IWL_DEBUG_INFO(priv, "RFKILL status: 0x%x\n", rfkill);
b481de9c
ZY
2499
2500 if (rfkill & 0x1) {
2501 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a96a27f9 2502 /* if RFKILL is not on, then wait for thermal
b481de9c 2503 * sensor in adapter to kick in */
bb8c093b 2504 while (iwl3945_hw_get_temperature(priv) == 0) {
b481de9c
ZY
2505 thermal_spin++;
2506 udelay(10);
2507 }
2508
2509 if (thermal_spin)
e1623446 2510 IWL_DEBUG_INFO(priv, "Thermal calibration took %dus\n",
b481de9c
ZY
2511 thermal_spin * 10);
2512 } else
2513 set_bit(STATUS_RF_KILL_HW, &priv->status);
2514
9fbab516 2515 /* After the ALIVE response, we can send commands to 3945 uCode */
b481de9c
ZY
2516 set_bit(STATUS_ALIVE, &priv->status);
2517
b74e31a9
WYG
2518 if (priv->cfg->ops->lib->recover_from_tx_stall) {
2519 /* Enable timer to monitor the driver queues */
2520 mod_timer(&priv->monitor_recover,
2521 jiffies +
7cb1b088
WYG
2522 msecs_to_jiffies(
2523 priv->cfg->base_params->monitor_recover_period));
b74e31a9
WYG
2524 }
2525
775a6e27 2526 if (iwl_is_rfkill(priv))
b481de9c
ZY
2527 return;
2528
36d6825b 2529 ieee80211_wake_queues(priv->hw);
b481de9c 2530
470ab2dd 2531 priv->active_rate = IWL_RATES_MASK;
b481de9c 2532
4d6ccbf5 2533 iwl_power_update_mode(priv, true);
b481de9c 2534
246ed355 2535 if (iwl_is_associated(priv, IWL_RXON_CTX_BSS)) {
bb8c093b 2536 struct iwl3945_rxon_cmd *active_rxon =
246ed355 2537 (struct iwl3945_rxon_cmd *)(&ctx->active);
b481de9c 2538
246ed355 2539 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY
2540 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2541 } else {
2542 /* Initialize our rx_config data */
d0fe478c 2543 iwl_connection_init_rx_config(priv, ctx);
b481de9c
ZY
2544 }
2545
9fbab516 2546 /* Configure Bluetooth device coexistence support */
65b52bde 2547 priv->cfg->ops->hcmd->send_bt_config(priv);
b481de9c
ZY
2548
2549 /* Configure the adapter for unassociated operation */
8289e07b 2550 iwl3945_commit_rxon(priv, ctx);
b481de9c 2551
b481de9c
ZY
2552 iwl3945_reg_txpower_periodic(priv);
2553
e932a609 2554 iwl_leds_init(priv);
fe00b5a5 2555
e1623446 2556 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 2557 set_bit(STATUS_READY, &priv->status);
5a66926a 2558 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 2559
b481de9c
ZY
2560 return;
2561
2562 restart:
2563 queue_work(priv->workqueue, &priv->restart);
2564}
2565
4a8a4322 2566static void iwl3945_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 2567
4a8a4322 2568static void __iwl3945_down(struct iwl_priv *priv)
b481de9c
ZY
2569{
2570 unsigned long flags;
d745d472 2571 int exit_pending;
b481de9c 2572
e1623446 2573 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c 2574
d745d472
SG
2575 iwl_scan_cancel_timeout(priv, 200);
2576
2577 exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 2578
b62177a0
SG
2579 /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2580 * to prevent rearm timer */
2581 if (priv->cfg->ops->lib->recover_from_tx_stall)
2582 del_timer_sync(&priv->monitor_recover);
2583
7e246191 2584 /* Station information will now be cleared in device */
dcef732c 2585 iwl_clear_ucode_stations(priv, NULL);
a194e324 2586 iwl_dealloc_bcast_stations(priv);
db125c78 2587 iwl_clear_driver_stations(priv);
b481de9c
ZY
2588
2589 /* Unblock any waiting calls */
2590 wake_up_interruptible_all(&priv->wait_command_queue);
2591
b481de9c
ZY
2592 /* Wipe out the EXIT_PENDING status bit if we are not actually
2593 * exiting the module */
2594 if (!exit_pending)
2595 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2596
2597 /* stop and reset the on-board processor */
5d49f498 2598 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY
2599
2600 /* tell the device to stop sending interrupts */
0359facc 2601 spin_lock_irqsave(&priv->lock, flags);
ed3b932e 2602 iwl_disable_interrupts(priv);
0359facc
MA
2603 spin_unlock_irqrestore(&priv->lock, flags);
2604 iwl_synchronize_irq(priv);
b481de9c
ZY
2605
2606 if (priv->mac80211_registered)
2607 ieee80211_stop_queues(priv->hw);
2608
bb8c093b 2609 /* If we have not previously called iwl3945_init() then
6da3a13e 2610 * clear all bits but the RF Kill bits and return */
775a6e27 2611 if (!iwl_is_init(priv)) {
b481de9c
ZY
2612 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2613 STATUS_RF_KILL_HW |
9788864e
RC
2614 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2615 STATUS_GEO_CONFIGURED |
ebef2008
AK
2616 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2617 STATUS_EXIT_PENDING;
b481de9c
ZY
2618 goto exit;
2619 }
2620
6da3a13e 2621 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 2622 * bit and continue taking the NIC down. */
b481de9c
ZY
2623 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2624 STATUS_RF_KILL_HW |
9788864e
RC
2625 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2626 STATUS_GEO_CONFIGURED |
b481de9c 2627 test_bit(STATUS_FW_ERROR, &priv->status) <<
ebef2008
AK
2628 STATUS_FW_ERROR |
2629 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2630 STATUS_EXIT_PENDING;
b481de9c 2631
bb8c093b
CH
2632 iwl3945_hw_txq_ctx_stop(priv);
2633 iwl3945_hw_rxq_stop(priv);
b481de9c 2634
309e731a
BC
2635 /* Power-down device's busmaster DMA clocks */
2636 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY
2637 udelay(5);
2638
4d2ccdb9 2639 /* Stop the device, and put it in low power state */
14e8e4af 2640 iwl_apm_stop(priv);
e9414b6b 2641
b481de9c 2642 exit:
3d24a9f7 2643 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c 2644
12e934dc
JB
2645 if (priv->beacon_skb)
2646 dev_kfree_skb(priv->beacon_skb);
2647 priv->beacon_skb = NULL;
b481de9c
ZY
2648
2649 /* clear out any free frames */
bb8c093b 2650 iwl3945_clear_free_frames(priv);
b481de9c
ZY
2651}
2652
4a8a4322 2653static void iwl3945_down(struct iwl_priv *priv)
b481de9c
ZY
2654{
2655 mutex_lock(&priv->mutex);
bb8c093b 2656 __iwl3945_down(priv);
b481de9c 2657 mutex_unlock(&priv->mutex);
b24d22b1 2658
bb8c093b 2659 iwl3945_cancel_deferred_work(priv);
b481de9c
ZY
2660}
2661
2662#define MAX_HW_RESTARTS 5
2663
a30e3112
JB
2664static int iwl3945_alloc_bcast_station(struct iwl_priv *priv)
2665{
2666 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2667 unsigned long flags;
2668 u8 sta_id;
2669
2670 spin_lock_irqsave(&priv->sta_lock, flags);
2671 sta_id = iwl_prep_station(priv, ctx, iwl_bcast_addr, false, NULL);
2672 if (sta_id == IWL_INVALID_STATION) {
2673 IWL_ERR(priv, "Unable to prepare broadcast station\n");
2674 spin_unlock_irqrestore(&priv->sta_lock, flags);
2675
2676 return -EINVAL;
2677 }
2678
2679 priv->stations[sta_id].used |= IWL_STA_DRIVER_ACTIVE;
2680 priv->stations[sta_id].used |= IWL_STA_BCAST;
2681 spin_unlock_irqrestore(&priv->sta_lock, flags);
2682
2683 return 0;
2684}
2685
4a8a4322 2686static int __iwl3945_up(struct iwl_priv *priv)
b481de9c
ZY
2687{
2688 int rc, i;
2689
a30e3112 2690 rc = iwl3945_alloc_bcast_station(priv);
2c810ccd
JB
2691 if (rc)
2692 return rc;
2693
b481de9c 2694 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 2695 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY
2696 return -EIO;
2697 }
2698
e903fbd4 2699 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 2700 IWL_ERR(priv, "ucode not available for device bring up\n");
e903fbd4
RC
2701 return -EIO;
2702 }
2703
e655b9f0 2704 /* If platform's RF_KILL switch is NOT set to KILL */
5d49f498 2705 if (iwl_read32(priv, CSR_GP_CNTRL) &
e655b9f0
ZY
2706 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2707 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2708 else {
2709 set_bit(STATUS_RF_KILL_HW, &priv->status);
6da3a13e
WYG
2710 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2711 return -ENODEV;
b481de9c 2712 }
80fcc9e2 2713
5d49f498 2714 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 2715
bb8c093b 2716 rc = iwl3945_hw_nic_init(priv);
b481de9c 2717 if (rc) {
15b1687c 2718 IWL_ERR(priv, "Unable to int nic\n");
b481de9c
ZY
2719 return rc;
2720 }
2721
2722 /* make sure rfkill handshake bits are cleared */
5d49f498
AK
2723 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2724 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY
2725 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2726
2727 /* clear (again), then enable host interrupts */
5d49f498 2728 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
ed3b932e 2729 iwl_enable_interrupts(priv);
b481de9c
ZY
2730
2731 /* really make sure rfkill handshake bits are cleared */
5d49f498
AK
2732 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2733 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
2734
2735 /* Copy original ucode data image from disk into backup cache.
2736 * This will be used to initialize the on-board processor's
2737 * data SRAM for a clean start when the runtime program first loads. */
2738 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 2739 priv->ucode_data.len);
b481de9c 2740
e655b9f0
ZY
2741 /* We return success when we resume from suspend and rf_kill is on. */
2742 if (test_bit(STATUS_RF_KILL_HW, &priv->status))
2743 return 0;
2744
b481de9c
ZY
2745 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2746
b481de9c
ZY
2747 /* load bootstrap state machine,
2748 * load bootstrap program into processor's memory,
2749 * prepare to load the "initialize" uCode */
75a9a926 2750 rc = priv->cfg->ops->lib->load_ucode(priv);
b481de9c
ZY
2751
2752 if (rc) {
15b1687c
WT
2753 IWL_ERR(priv,
2754 "Unable to set up bootstrap uCode: %d\n", rc);
b481de9c
ZY
2755 continue;
2756 }
2757
2758 /* start card; "initialize" will load runtime ucode */
bb8c093b 2759 iwl3945_nic_start(priv);
b481de9c 2760
e1623446 2761 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY
2762
2763 return 0;
2764 }
2765
2766 set_bit(STATUS_EXIT_PENDING, &priv->status);
bb8c093b 2767 __iwl3945_down(priv);
ebef2008 2768 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY
2769
2770 /* tried to restart and config the device for as long as our
2771 * patience could withstand */
15b1687c 2772 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY
2773 return -EIO;
2774}
2775
2776
2777/*****************************************************************************
2778 *
2779 * Workqueue callbacks
2780 *
2781 *****************************************************************************/
2782
bb8c093b 2783static void iwl3945_bg_init_alive_start(struct work_struct *data)
b481de9c 2784{
4a8a4322
AK
2785 struct iwl_priv *priv =
2786 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY
2787
2788 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2789 return;
2790
2791 mutex_lock(&priv->mutex);
bb8c093b 2792 iwl3945_init_alive_start(priv);
b481de9c
ZY
2793 mutex_unlock(&priv->mutex);
2794}
2795
bb8c093b 2796static void iwl3945_bg_alive_start(struct work_struct *data)
b481de9c 2797{
4a8a4322
AK
2798 struct iwl_priv *priv =
2799 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY
2800
2801 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2802 return;
2803
2804 mutex_lock(&priv->mutex);
bb8c093b 2805 iwl3945_alive_start(priv);
b481de9c
ZY
2806 mutex_unlock(&priv->mutex);
2807}
2808
743cdf1b
BC
2809/*
2810 * 3945 cannot interrupt driver when hardware rf kill switch toggles;
2811 * driver must poll CSR_GP_CNTRL_REG register for change. This register
2812 * *is* readable even when device has been SW_RESET into low power mode
2813 * (e.g. during RF KILL).
2814 */
2663516d
HS
2815static void iwl3945_rfkill_poll(struct work_struct *data)
2816{
2817 struct iwl_priv *priv =
ee525d13 2818 container_of(data, struct iwl_priv, _3945.rfkill_poll.work);
743cdf1b
BC
2819 bool old_rfkill = test_bit(STATUS_RF_KILL_HW, &priv->status);
2820 bool new_rfkill = !(iwl_read32(priv, CSR_GP_CNTRL)
2821 & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
2663516d 2822
743cdf1b
BC
2823 if (new_rfkill != old_rfkill) {
2824 if (new_rfkill)
2825 set_bit(STATUS_RF_KILL_HW, &priv->status);
2826 else
2827 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2663516d 2828
743cdf1b
BC
2829 wiphy_rfkill_set_hw_state(priv->hw->wiphy, new_rfkill);
2830
2831 IWL_DEBUG_RF_KILL(priv, "RF_KILL bit toggled to %s.\n",
2832 new_rfkill ? "disable radio" : "enable radio");
2833 }
2663516d 2834
743cdf1b
BC
2835 /* Keep this running, even if radio now enabled. This will be
2836 * cancelled in mac_start() if system decides to start again */
ee525d13 2837 queue_delayed_work(priv->workqueue, &priv->_3945.rfkill_poll,
2663516d
HS
2838 round_jiffies_relative(2 * HZ));
2839
2840}
2841
3eecce52 2842int iwl3945_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
b481de9c 2843{
c2d79b48 2844 struct iwl_host_cmd cmd = {
b481de9c 2845 .id = REPLY_SCAN_CMD,
bb8c093b 2846 .len = sizeof(struct iwl3945_scan_cmd),
c2acea8e 2847 .flags = CMD_SIZE_HUGE,
b481de9c 2848 };
bb8c093b 2849 struct iwl3945_scan_cmd *scan;
1ecf9fc1 2850 u8 n_probes = 0;
8318d78a 2851 enum ieee80211_band band;
1ecf9fc1 2852 bool is_active = false;
3eecce52 2853 int ret;
b481de9c 2854
3eecce52 2855 lockdep_assert_held(&priv->mutex);
b481de9c 2856
811ecc99
JB
2857 if (!priv->scan_cmd) {
2858 priv->scan_cmd = kmalloc(sizeof(struct iwl3945_scan_cmd) +
2859 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
2860 if (!priv->scan_cmd) {
4f4d4088 2861 IWL_DEBUG_SCAN(priv, "Fail to allocate scan memory\n");
3eecce52 2862 return -ENOMEM;
b481de9c
ZY
2863 }
2864 }
811ecc99 2865 scan = priv->scan_cmd;
bb8c093b 2866 memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
b481de9c
ZY
2867
2868 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
2869 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
2870
246ed355 2871 if (iwl_is_associated(priv, IWL_RXON_CTX_BSS)) {
b481de9c
ZY
2872 u16 interval = 0;
2873 u32 extra;
2874 u32 suspend_time = 100;
2875 u32 scan_suspend_time = 100;
2876 unsigned long flags;
2877
e1623446 2878 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
b481de9c
ZY
2879
2880 spin_lock_irqsave(&priv->lock, flags);
a6e492b9
JL
2881 if (priv->is_internal_short_scan)
2882 interval = 0;
2883 else
2884 interval = vif->bss_conf.beacon_int;
b481de9c
ZY
2885 spin_unlock_irqrestore(&priv->lock, flags);
2886
2887 scan->suspend_time = 0;
15e869d8 2888 scan->max_out_time = cpu_to_le32(200 * 1024);
b481de9c
ZY
2889 if (!interval)
2890 interval = suspend_time;
2891 /*
2892 * suspend time format:
2893 * 0-19: beacon interval in usec (time before exec.)
2894 * 20-23: 0
2895 * 24-31: number of beacons (suspend between channels)
2896 */
2897
2898 extra = (suspend_time / interval) << 24;
2899 scan_suspend_time = 0xFF0FFFFF &
2900 (extra | ((suspend_time % interval) * 1024));
2901
2902 scan->suspend_time = cpu_to_le32(scan_suspend_time);
e1623446 2903 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
b481de9c
ZY
2904 scan_suspend_time, interval);
2905 }
2906
4f4d4088
WYG
2907 if (priv->is_internal_short_scan) {
2908 IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
2909 } else if (priv->scan_request->n_ssids) {
1ecf9fc1
JB
2910 int i, p = 0;
2911 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
2912 for (i = 0; i < priv->scan_request->n_ssids; i++) {
2913 /* always does wildcard anyway */
2914 if (!priv->scan_request->ssids[i].ssid_len)
2915 continue;
2916 scan->direct_scan[p].id = WLAN_EID_SSID;
2917 scan->direct_scan[p].len =
2918 priv->scan_request->ssids[i].ssid_len;
2919 memcpy(scan->direct_scan[p].ssid,
2920 priv->scan_request->ssids[i].ssid,
2921 priv->scan_request->ssids[i].ssid_len);
2922 n_probes++;
2923 p++;
2924 }
2925 is_active = true;
f9340520 2926 } else
1ecf9fc1 2927 IWL_DEBUG_SCAN(priv, "Kicking off passive scan.\n");
b481de9c
ZY
2928
2929 /* We don't build a direct scan probe request; the uCode will do
2930 * that based on the direct_mask added to each channel entry */
b481de9c 2931 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
a194e324 2932 scan->tx_cmd.sta_id = priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id;
b481de9c
ZY
2933 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2934
2935 /* flags + rate selection */
2936
00700ee0
JB
2937 switch (priv->scan_band) {
2938 case IEEE80211_BAND_2GHZ:
b481de9c
ZY
2939 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
2940 scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
8318d78a 2941 band = IEEE80211_BAND_2GHZ;
00700ee0
JB
2942 break;
2943 case IEEE80211_BAND_5GHZ:
b481de9c 2944 scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
8318d78a 2945 band = IEEE80211_BAND_5GHZ;
00700ee0
JB
2946 break;
2947 default:
2948 IWL_WARN(priv, "Invalid scan band\n");
3eecce52 2949 return -EIO;
b481de9c
ZY
2950 }
2951
085fbca2
JB
2952 /*
2953 * If active scaning is requested but a certain channel
2954 * is marked passive, we can do active scanning if we
2955 * detect transmissions.
2956 */
2957 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
2958 IWL_GOOD_CRC_TH_DISABLED;
2959
4f4d4088
WYG
2960 if (!priv->is_internal_short_scan) {
2961 scan->tx_cmd.len = cpu_to_le16(
1ecf9fc1
JB
2962 iwl_fill_probe_req(priv,
2963 (struct ieee80211_mgmt *)scan->data,
3a0b9aad 2964 vif->addr,
1ecf9fc1
JB
2965 priv->scan_request->ie,
2966 priv->scan_request->ie_len,
2967 IWL_MAX_SCAN_SIZE - sizeof(*scan)));
4f4d4088 2968 } else {
3a0b9aad 2969 /* use bcast addr, will not be transmitted but must be valid */
4f4d4088
WYG
2970 scan->tx_cmd.len = cpu_to_le16(
2971 iwl_fill_probe_req(priv,
2972 (struct ieee80211_mgmt *)scan->data,
3a0b9aad 2973 iwl_bcast_addr, NULL, 0,
4f4d4088
WYG
2974 IWL_MAX_SCAN_SIZE - sizeof(*scan)));
2975 }
b481de9c
ZY
2976 /* select Rx antennas */
2977 scan->flags |= iwl3945_get_antenna_flags(priv);
2978
14023641
AK
2979 if (priv->is_internal_short_scan) {
2980 scan->channel_count =
2981 iwl3945_get_single_channel_for_scan(priv, vif, band,
2982 (void *)&scan->data[le16_to_cpu(
2983 scan->tx_cmd.len)]);
2984 } else {
2985 scan->channel_count =
2986 iwl3945_get_channels_for_scan(priv, band, is_active, n_probes,
2987 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)], vif);
2988 }
b481de9c 2989
14b54336 2990 if (scan->channel_count == 0) {
e1623446 2991 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
3eecce52 2992 return -EIO;
14b54336
RC
2993 }
2994
b481de9c 2995 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
bb8c093b 2996 scan->channel_count * sizeof(struct iwl3945_scan_channel);
b481de9c
ZY
2997 cmd.data = scan;
2998 scan->len = cpu_to_le16(cmd.len);
2999
3000 set_bit(STATUS_SCAN_HW, &priv->status);
3eecce52
JB
3001 ret = iwl_send_cmd_sync(priv, &cmd);
3002 if (ret)
3003 clear_bit(STATUS_SCAN_HW, &priv->status);
3004 return ret;
b481de9c
ZY
3005}
3006
a77029ee
JB
3007void iwl3945_post_scan(struct iwl_priv *priv)
3008{
3009 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
3010
3011 /*
3012 * Since setting the RXON may have been deferred while
3013 * performing the scan, fire one off if needed
3014 */
3015 if (memcmp(&ctx->staging, &ctx->active, sizeof(ctx->staging)))
8289e07b 3016 iwl3945_commit_rxon(priv, ctx);
a77029ee
JB
3017}
3018
bb8c093b 3019static void iwl3945_bg_restart(struct work_struct *data)
b481de9c 3020{
4a8a4322 3021 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY
3022
3023 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3024 return;
3025
19cc1087 3026 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
8bd413e6 3027 struct iwl_rxon_context *ctx;
19cc1087 3028 mutex_lock(&priv->mutex);
8bd413e6
JB
3029 for_each_context(priv, ctx)
3030 ctx->vif = NULL;
19cc1087
JB
3031 priv->is_open = 0;
3032 mutex_unlock(&priv->mutex);
3033 iwl3945_down(priv);
3034 ieee80211_restart_hw(priv->hw);
3035 } else {
3036 iwl3945_down(priv);
80676518
JB
3037
3038 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3039 return;
3040
3041 mutex_lock(&priv->mutex);
3042 __iwl3945_up(priv);
3043 mutex_unlock(&priv->mutex);
19cc1087 3044 }
b481de9c
ZY
3045}
3046
bb8c093b 3047static void iwl3945_bg_rx_replenish(struct work_struct *data)
b481de9c 3048{
4a8a4322
AK
3049 struct iwl_priv *priv =
3050 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY
3051
3052 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3053 return;
3054
3055 mutex_lock(&priv->mutex);
bb8c093b 3056 iwl3945_rx_replenish(priv);
b481de9c
ZY
3057 mutex_unlock(&priv->mutex);
3058}
3059
1dda6d28 3060void iwl3945_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif)
b481de9c 3061{
b481de9c
ZY
3062 int rc = 0;
3063 struct ieee80211_conf *conf = NULL;
246ed355 3064 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
b481de9c 3065
1dda6d28
JB
3066 if (!vif || !priv->is_open)
3067 return;
3068
3069 if (vif->type == NL80211_IFTYPE_AP) {
15b1687c 3070 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY
3071 return;
3072 }
3073
e1623446 3074 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
246ed355 3075 vif->bss_conf.aid, ctx->active.bssid_addr);
b481de9c
ZY
3076
3077 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3078 return;
3079
af0053d6 3080 iwl_scan_cancel_timeout(priv, 200);
15e869d8 3081
b481de9c
ZY
3082 conf = ieee80211_get_hw_conf(priv->hw);
3083
246ed355 3084 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
8289e07b 3085 iwl3945_commit_rxon(priv, ctx);
b481de9c 3086
47313e34 3087 rc = iwl_send_rxon_timing(priv, ctx);
b481de9c 3088 if (rc)
39aadf8c 3089 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
3090 "Attempting to continue.\n");
3091
246ed355 3092 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c 3093
246ed355 3094 ctx->staging.assoc_id = cpu_to_le16(vif->bss_conf.aid);
b481de9c 3095
e1623446 3096 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
1dda6d28 3097 vif->bss_conf.aid, vif->bss_conf.beacon_int);
b481de9c 3098
c213d745 3099 if (vif->bss_conf.use_short_preamble)
246ed355 3100 ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 3101 else
246ed355 3102 ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 3103
246ed355 3104 if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
c213d745 3105 if (vif->bss_conf.use_short_slot)
246ed355 3106 ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
b481de9c 3107 else
246ed355 3108 ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c
ZY
3109 }
3110
8289e07b 3111 iwl3945_commit_rxon(priv, ctx);
b481de9c 3112
1dda6d28 3113 switch (vif->type) {
05c914fe 3114 case NL80211_IFTYPE_STATION:
bb8c093b 3115 iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
b481de9c 3116 break;
05c914fe 3117 case NL80211_IFTYPE_ADHOC:
bb8c093b 3118 iwl3945_send_beacon_cmd(priv);
b481de9c 3119 break;
b481de9c 3120 default:
1dda6d28
JB
3121 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3122 __func__, vif->type);
b481de9c
ZY
3123 break;
3124 }
cd56d331
AK
3125}
3126
b481de9c
ZY
3127/*****************************************************************************
3128 *
3129 * mac80211 entry point functions
3130 *
3131 *****************************************************************************/
3132
5a66926a
ZY
3133#define UCODE_READY_TIMEOUT (2 * HZ)
3134
bb8c093b 3135static int iwl3945_mac_start(struct ieee80211_hw *hw)
b481de9c 3136{
4a8a4322 3137 struct iwl_priv *priv = hw->priv;
5a66926a 3138 int ret;
b481de9c 3139
e1623446 3140 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY
3141
3142 /* we should be verifying the device is ready to be opened */
3143 mutex_lock(&priv->mutex);
3144
5a66926a
ZY
3145 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
3146 * ucode filename and max sizes are card-specific. */
3147
3148 if (!priv->ucode_code.len) {
3149 ret = iwl3945_read_ucode(priv);
3150 if (ret) {
15b1687c 3151 IWL_ERR(priv, "Could not read microcode: %d\n", ret);
5a66926a
ZY
3152 mutex_unlock(&priv->mutex);
3153 goto out_release_irq;
3154 }
3155 }
b481de9c 3156
e655b9f0 3157 ret = __iwl3945_up(priv);
b481de9c
ZY
3158
3159 mutex_unlock(&priv->mutex);
5a66926a 3160
e655b9f0
ZY
3161 if (ret)
3162 goto out_release_irq;
3163
e1623446 3164 IWL_DEBUG_INFO(priv, "Start UP work.\n");
e655b9f0 3165
5a66926a
ZY
3166 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
3167 * mac80211 will not be run successfully. */
3168 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3169 test_bit(STATUS_READY, &priv->status),
3170 UCODE_READY_TIMEOUT);
3171 if (!ret) {
3172 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c
WT
3173 IWL_ERR(priv,
3174 "Wait for START_ALIVE timeout after %dms.\n",
3175 jiffies_to_msecs(UCODE_READY_TIMEOUT));
5a66926a
ZY
3176 ret = -ETIMEDOUT;
3177 goto out_release_irq;
3178 }
3179 }
3180
2663516d
HS
3181 /* ucode is running and will send rfkill notifications,
3182 * no need to poll the killswitch state anymore */
ee525d13 3183 cancel_delayed_work(&priv->_3945.rfkill_poll);
2663516d 3184
e932a609
JB
3185 iwl_led_start(priv);
3186
e655b9f0 3187 priv->is_open = 1;
e1623446 3188 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 3189 return 0;
5a66926a
ZY
3190
3191out_release_irq:
e655b9f0 3192 priv->is_open = 0;
e1623446 3193 IWL_DEBUG_MAC80211(priv, "leave - failed\n");
5a66926a 3194 return ret;
b481de9c
ZY
3195}
3196
bb8c093b 3197static void iwl3945_mac_stop(struct ieee80211_hw *hw)
b481de9c 3198{
4a8a4322 3199 struct iwl_priv *priv = hw->priv;
b481de9c 3200
e1623446 3201 IWL_DEBUG_MAC80211(priv, "enter\n");
6ef89d0a 3202
e655b9f0 3203 if (!priv->is_open) {
e1623446 3204 IWL_DEBUG_MAC80211(priv, "leave - skip\n");
e655b9f0
ZY
3205 return;
3206 }
3207
b481de9c 3208 priv->is_open = 0;
5a66926a 3209
5a66926a
ZY
3210 iwl3945_down(priv);
3211
3212 flush_workqueue(priv->workqueue);
2663516d
HS
3213
3214 /* start polling the killswitch state again */
ee525d13 3215 queue_delayed_work(priv->workqueue, &priv->_3945.rfkill_poll,
2663516d 3216 round_jiffies_relative(2 * HZ));
6ef89d0a 3217
e1623446 3218 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
3219}
3220
e039fa4a 3221static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 3222{
4a8a4322 3223 struct iwl_priv *priv = hw->priv;
b481de9c 3224
e1623446 3225 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3226
e1623446 3227 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 3228 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 3229
e039fa4a 3230 if (iwl3945_tx_skb(priv, skb))
b481de9c
ZY
3231 dev_kfree_skb_any(skb);
3232
e1623446 3233 IWL_DEBUG_MAC80211(priv, "leave\n");
637f8837 3234 return NETDEV_TX_OK;
b481de9c
ZY
3235}
3236
1dda6d28 3237void iwl3945_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif)
b481de9c 3238{
246ed355 3239 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
b481de9c
ZY
3240 int rc = 0;
3241
d986bcd1 3242 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY
3243 return;
3244
3245 /* The following should be done only at AP bring up */
246ed355 3246 if (!(iwl_is_associated(priv, IWL_RXON_CTX_BSS))) {
b481de9c
ZY
3247
3248 /* RXON - unassoc (to set timing command) */
246ed355 3249 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
8289e07b 3250 iwl3945_commit_rxon(priv, ctx);
b481de9c
ZY
3251
3252 /* RXON Timing */
47313e34 3253 rc = iwl_send_rxon_timing(priv, ctx);
b481de9c 3254 if (rc)
39aadf8c 3255 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
3256 "Attempting to continue.\n");
3257
246ed355 3258 ctx->staging.assoc_id = 0;
1dda6d28 3259
c213d745 3260 if (vif->bss_conf.use_short_preamble)
246ed355 3261 ctx->staging.flags |=
b481de9c
ZY
3262 RXON_FLG_SHORT_PREAMBLE_MSK;
3263 else
246ed355 3264 ctx->staging.flags &=
b481de9c
ZY
3265 ~RXON_FLG_SHORT_PREAMBLE_MSK;
3266
246ed355 3267 if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
c213d745 3268 if (vif->bss_conf.use_short_slot)
246ed355 3269 ctx->staging.flags |=
b481de9c
ZY
3270 RXON_FLG_SHORT_SLOT_MSK;
3271 else
246ed355 3272 ctx->staging.flags &=
b481de9c 3273 ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c
ZY
3274 }
3275 /* restore RXON assoc */
246ed355 3276 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
8289e07b 3277 iwl3945_commit_rxon(priv, ctx);
556f8db7 3278 }
bb8c093b 3279 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
3280
3281 /* FIXME - we need to add code here to detect a totally new
3282 * configuration, reset the AP, unassoc, rxon timing, assoc,
3283 * clear sta table, add BCAST sta... */
3284}
3285
bb8c093b 3286static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB
3287 struct ieee80211_vif *vif,
3288 struct ieee80211_sta *sta,
3289 struct ieee80211_key_conf *key)
b481de9c 3290{
4a8a4322 3291 struct iwl_priv *priv = hw->priv;
6e21f15c
AK
3292 int ret = 0;
3293 u8 sta_id = IWL_INVALID_STATION;
3294 u8 static_key;
b481de9c 3295
e1623446 3296 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3297
df878d8f 3298 if (iwl3945_mod_params.sw_crypto) {
e1623446 3299 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY
3300 return -EOPNOTSUPP;
3301 }
3302
246ed355 3303 static_key = !iwl_is_associated(priv, IWL_RXON_CTX_BSS);
6e21f15c
AK
3304
3305 if (!static_key) {
a194e324
JB
3306 sta_id = iwl_sta_id_or_broadcast(
3307 priv, &priv->contexts[IWL_RXON_CTX_BSS], sta);
0af8bcae
JB
3308 if (sta_id == IWL_INVALID_STATION)
3309 return -EINVAL;
b481de9c
ZY
3310 }
3311
3312 mutex_lock(&priv->mutex);
af0053d6 3313 iwl_scan_cancel_timeout(priv, 100);
15e869d8 3314
b481de9c 3315 switch (cmd) {
6e21f15c
AK
3316 case SET_KEY:
3317 if (static_key)
3318 ret = iwl3945_set_static_key(priv, key);
3319 else
3320 ret = iwl3945_set_dynamic_key(priv, key, sta_id);
3321 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY
3322 break;
3323 case DISABLE_KEY:
6e21f15c
AK
3324 if (static_key)
3325 ret = iwl3945_remove_static_key(priv);
3326 else
3327 ret = iwl3945_clear_sta_key_info(priv, sta_id);
3328 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY
3329 break;
3330 default:
42986796 3331 ret = -EINVAL;
b481de9c
ZY
3332 }
3333
72e15d71 3334 mutex_unlock(&priv->mutex);
e1623446 3335 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 3336
42986796 3337 return ret;
b481de9c
ZY
3338}
3339
fe6b23dd
RC
3340static int iwl3945_mac_sta_add(struct ieee80211_hw *hw,
3341 struct ieee80211_vif *vif,
3342 struct ieee80211_sta *sta)
3343{
3344 struct iwl_priv *priv = hw->priv;
fd1af15d 3345 struct iwl3945_sta_priv *sta_priv = (void *)sta->drv_priv;
fe6b23dd 3346 int ret;
fd1af15d 3347 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
fe6b23dd
RC
3348 u8 sta_id;
3349
3350 IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3351 sta->addr);
da5ae1cf
RC
3352 mutex_lock(&priv->mutex);
3353 IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3354 sta->addr);
3355 sta_priv->common.sta_id = IWL_INVALID_STATION;
3356
fe6b23dd 3357
a194e324 3358 ret = iwl_add_station_common(priv, &priv->contexts[IWL_RXON_CTX_BSS],
238d781d 3359 sta->addr, is_ap, sta, &sta_id);
fe6b23dd
RC
3360 if (ret) {
3361 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3362 sta->addr, ret);
3363 /* Should we return success if return code is EEXIST ? */
da5ae1cf 3364 mutex_unlock(&priv->mutex);
fe6b23dd
RC
3365 return ret;
3366 }
3367
fd1af15d
JB
3368 sta_priv->common.sta_id = sta_id;
3369
fe6b23dd 3370 /* Initialize rate scaling */
91dd6c27 3371 IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
fe6b23dd
RC
3372 sta->addr);
3373 iwl3945_rs_rate_init(priv, sta, sta_id);
da5ae1cf 3374 mutex_unlock(&priv->mutex);
fe6b23dd
RC
3375
3376 return 0;
fe6b23dd 3377}
8b8ab9d5
JB
3378
3379static void iwl3945_configure_filter(struct ieee80211_hw *hw,
3380 unsigned int changed_flags,
3381 unsigned int *total_flags,
3382 u64 multicast)
3383{
3384 struct iwl_priv *priv = hw->priv;
3385 __le32 filter_or = 0, filter_nand = 0;
246ed355 3386 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
8b8ab9d5
JB
3387
3388#define CHK(test, flag) do { \
3389 if (*total_flags & (test)) \
3390 filter_or |= (flag); \
3391 else \
3392 filter_nand |= (flag); \
3393 } while (0)
3394
3395 IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3396 changed_flags, *total_flags);
3397
3398 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3399 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
3400 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3401
3402#undef CHK
3403
3404 mutex_lock(&priv->mutex);
3405
246ed355
JB
3406 ctx->staging.filter_flags &= ~filter_nand;
3407 ctx->staging.filter_flags |= filter_or;
8b8ab9d5
JB
3408
3409 /*
3410 * Committing directly here breaks for some reason,
3411 * but we'll eventually commit the filter flags
3412 * change anyway.
3413 */
3414
3415 mutex_unlock(&priv->mutex);
3416
3417 /*
3418 * Receiving all multicast frames is always enabled by the
3419 * default flags setup in iwl_connection_init_rx_config()
3420 * since we currently do not support programming multicast
3421 * filters into the device.
3422 */
3423 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3424 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3425}
3426
3427
b481de9c
ZY
3428/*****************************************************************************
3429 *
3430 * sysfs attributes
3431 *
3432 *****************************************************************************/
3433
d08853a3 3434#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
3435
3436/*
3437 * The following adds a new attribute to the sysfs representation
3438 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
3439 * used for controlling the debug level.
3440 *
3441 * See the level definitions in iwl for details.
a562a9dd 3442 *
3d816c77
RC
3443 * The debug_level being managed using sysfs below is a per device debug
3444 * level that is used instead of the global debug level if it (the per
3445 * device debug level) is set.
b481de9c 3446 */
40b8ec0b
SO
3447static ssize_t show_debug_level(struct device *d,
3448 struct device_attribute *attr, char *buf)
b481de9c 3449{
3d816c77
RC
3450 struct iwl_priv *priv = dev_get_drvdata(d);
3451 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
b481de9c 3452}
40b8ec0b
SO
3453static ssize_t store_debug_level(struct device *d,
3454 struct device_attribute *attr,
b481de9c
ZY
3455 const char *buf, size_t count)
3456{
928841b1 3457 struct iwl_priv *priv = dev_get_drvdata(d);
40b8ec0b
SO
3458 unsigned long val;
3459 int ret;
b481de9c 3460
40b8ec0b
SO
3461 ret = strict_strtoul(buf, 0, &val);
3462 if (ret)
978785a3 3463 IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf);
20594eb0 3464 else {
3d816c77 3465 priv->debug_level = val;
20594eb0
WYG
3466 if (iwl_alloc_traffic_mem(priv))
3467 IWL_ERR(priv,
3468 "Not enough memory to generate traffic log\n");
3469 }
b481de9c
ZY
3470 return strnlen(buf, count);
3471}
3472
40b8ec0b
SO
3473static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
3474 show_debug_level, store_debug_level);
b481de9c 3475
d08853a3 3476#endif /* CONFIG_IWLWIFI_DEBUG */
b481de9c 3477
b481de9c
ZY
3478static ssize_t show_temperature(struct device *d,
3479 struct device_attribute *attr, char *buf)
3480{
928841b1 3481 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3482
775a6e27 3483 if (!iwl_is_alive(priv))
b481de9c
ZY
3484 return -EAGAIN;
3485
bb8c093b 3486 return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
b481de9c
ZY
3487}
3488
3489static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
3490
b481de9c
ZY
3491static ssize_t show_tx_power(struct device *d,
3492 struct device_attribute *attr, char *buf)
3493{
928841b1 3494 struct iwl_priv *priv = dev_get_drvdata(d);
62ea9c5b 3495 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
b481de9c
ZY
3496}
3497
3498static ssize_t store_tx_power(struct device *d,
3499 struct device_attribute *attr,
3500 const char *buf, size_t count)
3501{
928841b1 3502 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3503 char *p = (char *)buf;
3504 u32 val;
3505
3506 val = simple_strtoul(p, &p, 10);
3507 if (p == buf)
978785a3 3508 IWL_INFO(priv, ": %s is not in decimal form.\n", buf);
b481de9c 3509 else
bb8c093b 3510 iwl3945_hw_reg_set_txpower(priv, val);
b481de9c
ZY
3511
3512 return count;
3513}
3514
3515static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
3516
3517static ssize_t show_flags(struct device *d,
3518 struct device_attribute *attr, char *buf)
3519{
928841b1 3520 struct iwl_priv *priv = dev_get_drvdata(d);
246ed355 3521 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
b481de9c 3522
246ed355 3523 return sprintf(buf, "0x%04X\n", ctx->active.flags);
b481de9c
ZY
3524}
3525
3526static ssize_t store_flags(struct device *d,
3527 struct device_attribute *attr,
3528 const char *buf, size_t count)
3529{
928841b1 3530 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3531 u32 flags = simple_strtoul(buf, NULL, 0);
246ed355 3532 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
b481de9c
ZY
3533
3534 mutex_lock(&priv->mutex);
246ed355 3535 if (le32_to_cpu(ctx->staging.flags) != flags) {
b481de9c 3536 /* Cancel any currently running scans... */
af0053d6 3537 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 3538 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 3539 else {
e1623446 3540 IWL_DEBUG_INFO(priv, "Committing rxon.flags = 0x%04X\n",
b481de9c 3541 flags);
246ed355 3542 ctx->staging.flags = cpu_to_le32(flags);
8289e07b 3543 iwl3945_commit_rxon(priv, ctx);
b481de9c
ZY
3544 }
3545 }
3546 mutex_unlock(&priv->mutex);
3547
3548 return count;
3549}
3550
3551static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
3552
3553static ssize_t show_filter_flags(struct device *d,
3554 struct device_attribute *attr, char *buf)
3555{
928841b1 3556 struct iwl_priv *priv = dev_get_drvdata(d);
246ed355 3557 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
b481de9c
ZY
3558
3559 return sprintf(buf, "0x%04X\n",
246ed355 3560 le32_to_cpu(ctx->active.filter_flags));
b481de9c
ZY
3561}
3562
3563static ssize_t store_filter_flags(struct device *d,
3564 struct device_attribute *attr,
3565 const char *buf, size_t count)
3566{
928841b1 3567 struct iwl_priv *priv = dev_get_drvdata(d);
246ed355 3568 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
b481de9c
ZY
3569 u32 filter_flags = simple_strtoul(buf, NULL, 0);
3570
3571 mutex_lock(&priv->mutex);
246ed355 3572 if (le32_to_cpu(ctx->staging.filter_flags) != filter_flags) {
b481de9c 3573 /* Cancel any currently running scans... */
af0053d6 3574 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 3575 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 3576 else {
e1623446 3577 IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
b481de9c 3578 "0x%04X\n", filter_flags);
246ed355 3579 ctx->staging.filter_flags =
b481de9c 3580 cpu_to_le32(filter_flags);
8289e07b 3581 iwl3945_commit_rxon(priv, ctx);
b481de9c
ZY
3582 }
3583 }
3584 mutex_unlock(&priv->mutex);
3585
3586 return count;
3587}
3588
3589static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
3590 store_filter_flags);
3591
b481de9c
ZY
3592static ssize_t show_measurement(struct device *d,
3593 struct device_attribute *attr, char *buf)
3594{
4a8a4322 3595 struct iwl_priv *priv = dev_get_drvdata(d);
600c0e11 3596 struct iwl_spectrum_notification measure_report;
b481de9c 3597 u32 size = sizeof(measure_report), len = 0, ofs = 0;
3ac7f146 3598 u8 *data = (u8 *)&measure_report;
b481de9c
ZY
3599 unsigned long flags;
3600
3601 spin_lock_irqsave(&priv->lock, flags);
3602 if (!(priv->measurement_status & MEASUREMENT_READY)) {
3603 spin_unlock_irqrestore(&priv->lock, flags);
3604 return 0;
3605 }
3606 memcpy(&measure_report, &priv->measure_report, size);
3607 priv->measurement_status = 0;
3608 spin_unlock_irqrestore(&priv->lock, flags);
3609
3610 while (size && (PAGE_SIZE - len)) {
3611 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3612 PAGE_SIZE - len, 1);
3613 len = strlen(buf);
3614 if (PAGE_SIZE - len)
3615 buf[len++] = '\n';
3616
3617 ofs += 16;
3618 size -= min(size, 16U);
3619 }
3620
3621 return len;
3622}
3623
3624static ssize_t store_measurement(struct device *d,
3625 struct device_attribute *attr,
3626 const char *buf, size_t count)
3627{
4a8a4322 3628 struct iwl_priv *priv = dev_get_drvdata(d);
246ed355 3629 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
b481de9c 3630 struct ieee80211_measurement_params params = {
246ed355 3631 .channel = le16_to_cpu(ctx->active.channel),
e99f168c 3632 .start_time = cpu_to_le64(priv->_3945.last_tsf),
b481de9c
ZY
3633 .duration = cpu_to_le16(1),
3634 };
3635 u8 type = IWL_MEASURE_BASIC;
3636 u8 buffer[32];
3637 u8 channel;
3638
3639 if (count) {
3640 char *p = buffer;
3641 strncpy(buffer, buf, min(sizeof(buffer), count));
3642 channel = simple_strtoul(p, NULL, 0);
3643 if (channel)
3644 params.channel = channel;
3645
3646 p = buffer;
3647 while (*p && *p != ' ')
3648 p++;
3649 if (*p)
3650 type = simple_strtoul(p + 1, NULL, 0);
3651 }
3652
e1623446 3653 IWL_DEBUG_INFO(priv, "Invoking measurement of type %d on "
b481de9c 3654 "channel %d (for '%s')\n", type, params.channel, buf);
bb8c093b 3655 iwl3945_get_measurement(priv, &params, type);
b481de9c
ZY
3656
3657 return count;
3658}
3659
3660static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
3661 show_measurement, store_measurement);
b481de9c 3662
b481de9c
ZY
3663static ssize_t store_retry_rate(struct device *d,
3664 struct device_attribute *attr,
3665 const char *buf, size_t count)
3666{
4a8a4322 3667 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3668
3669 priv->retry_rate = simple_strtoul(buf, NULL, 0);
3670 if (priv->retry_rate <= 0)
3671 priv->retry_rate = 1;
3672
3673 return count;
3674}
3675
3676static ssize_t show_retry_rate(struct device *d,
3677 struct device_attribute *attr, char *buf)
3678{
4a8a4322 3679 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3680 return sprintf(buf, "%d", priv->retry_rate);
3681}
3682
3683static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
3684 store_retry_rate);
3685
d25aabb0 3686
b481de9c
ZY
3687static ssize_t show_channels(struct device *d,
3688 struct device_attribute *attr, char *buf)
3689{
8318d78a
JB
3690 /* all this shit doesn't belong into sysfs anyway */
3691 return 0;
b481de9c
ZY
3692}
3693
3694static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
3695
b481de9c
ZY
3696static ssize_t show_antenna(struct device *d,
3697 struct device_attribute *attr, char *buf)
3698{
4a8a4322 3699 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3700
775a6e27 3701 if (!iwl_is_alive(priv))
b481de9c
ZY
3702 return -EAGAIN;
3703
7e4bca5e 3704 return sprintf(buf, "%d\n", iwl3945_mod_params.antenna);
b481de9c
ZY
3705}
3706
3707static ssize_t store_antenna(struct device *d,
3708 struct device_attribute *attr,
3709 const char *buf, size_t count)
3710{
7530f85f 3711 struct iwl_priv *priv __maybe_unused = dev_get_drvdata(d);
b481de9c 3712 int ant;
b481de9c
ZY
3713
3714 if (count == 0)
3715 return 0;
3716
3717 if (sscanf(buf, "%1i", &ant) != 1) {
e1623446 3718 IWL_DEBUG_INFO(priv, "not in hex or decimal form.\n");
b481de9c
ZY
3719 return count;
3720 }
3721
3722 if ((ant >= 0) && (ant <= 2)) {
e1623446 3723 IWL_DEBUG_INFO(priv, "Setting antenna select to %d.\n", ant);
7e4bca5e 3724 iwl3945_mod_params.antenna = (enum iwl3945_antenna)ant;
b481de9c 3725 } else
e1623446 3726 IWL_DEBUG_INFO(priv, "Bad antenna select value %d.\n", ant);
b481de9c
ZY
3727
3728
3729 return count;
3730}
3731
3732static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
3733
3734static ssize_t show_status(struct device *d,
3735 struct device_attribute *attr, char *buf)
3736{
928841b1 3737 struct iwl_priv *priv = dev_get_drvdata(d);
775a6e27 3738 if (!iwl_is_alive(priv))
b481de9c
ZY
3739 return -EAGAIN;
3740 return sprintf(buf, "0x%08x\n", (int)priv->status);
3741}
3742
3743static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
3744
3745static ssize_t dump_error_log(struct device *d,
3746 struct device_attribute *attr,
3747 const char *buf, size_t count)
3748{
928841b1 3749 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3750 char *p = (char *)buf;
3751
3752 if (p[0] == '1')
928841b1 3753 iwl3945_dump_nic_error_log(priv);
b481de9c
ZY
3754
3755 return strnlen(buf, count);
3756}
3757
3758static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
3759
b481de9c
ZY
3760/*****************************************************************************
3761 *
a96a27f9 3762 * driver setup and tear down
b481de9c
ZY
3763 *
3764 *****************************************************************************/
3765
4a8a4322 3766static void iwl3945_setup_deferred_work(struct iwl_priv *priv)
b481de9c 3767{
d21050c7 3768 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY
3769
3770 init_waitqueue_head(&priv->wait_command_queue);
3771
bb8c093b
CH
3772 INIT_WORK(&priv->restart, iwl3945_bg_restart);
3773 INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
bb8c093b 3774 INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
bb8c093b
CH
3775 INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
3776 INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
ee525d13 3777 INIT_DELAYED_WORK(&priv->_3945.rfkill_poll, iwl3945_rfkill_poll);
c240879f
SG
3778
3779 iwl_setup_scan_deferred_work(priv);
bb8c093b
CH
3780
3781 iwl3945_hw_setup_deferred_work(priv);
b481de9c 3782
b74e31a9
WYG
3783 if (priv->cfg->ops->lib->recover_from_tx_stall) {
3784 init_timer(&priv->monitor_recover);
3785 priv->monitor_recover.data = (unsigned long)priv;
3786 priv->monitor_recover.function =
3787 priv->cfg->ops->lib->recover_from_tx_stall;
3788 }
3789
b481de9c 3790 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
bb8c093b 3791 iwl3945_irq_tasklet, (unsigned long)priv);
b481de9c
ZY
3792}
3793
4a8a4322 3794static void iwl3945_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 3795{
bb8c093b 3796 iwl3945_hw_cancel_deferred_work(priv);
b481de9c 3797
e47eb6ad 3798 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c 3799 cancel_delayed_work(&priv->alive_start);
b481de9c 3800 cancel_work_sync(&priv->beacon_update);
e7e16b90
SG
3801
3802 iwl_cancel_scan_deferred_work(priv);
b481de9c
ZY
3803}
3804
bb8c093b 3805static struct attribute *iwl3945_sysfs_entries[] = {
b481de9c
ZY
3806 &dev_attr_antenna.attr,
3807 &dev_attr_channels.attr,
3808 &dev_attr_dump_errors.attr,
b481de9c
ZY
3809 &dev_attr_flags.attr,
3810 &dev_attr_filter_flags.attr,
b481de9c 3811 &dev_attr_measurement.attr,
b481de9c 3812 &dev_attr_retry_rate.attr,
b481de9c
ZY
3813 &dev_attr_status.attr,
3814 &dev_attr_temperature.attr,
b481de9c 3815 &dev_attr_tx_power.attr,
d08853a3 3816#ifdef CONFIG_IWLWIFI_DEBUG
40b8ec0b
SO
3817 &dev_attr_debug_level.attr,
3818#endif
b481de9c
ZY
3819 NULL
3820};
3821
bb8c093b 3822static struct attribute_group iwl3945_attribute_group = {
b481de9c 3823 .name = NULL, /* put in device directory */
bb8c093b 3824 .attrs = iwl3945_sysfs_entries,
b481de9c
ZY
3825};
3826
bb8c093b
CH
3827static struct ieee80211_ops iwl3945_hw_ops = {
3828 .tx = iwl3945_mac_tx,
3829 .start = iwl3945_mac_start,
3830 .stop = iwl3945_mac_stop,
cbb6ab94 3831 .add_interface = iwl_mac_add_interface,
d8052319 3832 .remove_interface = iwl_mac_remove_interface,
4808368d 3833 .config = iwl_mac_config,
8b8ab9d5 3834 .configure_filter = iwl3945_configure_filter,
bb8c093b 3835 .set_key = iwl3945_mac_set_key,
488829f1 3836 .conf_tx = iwl_mac_conf_tx,
bd564261 3837 .reset_tsf = iwl_mac_reset_tsf,
5bbe233b 3838 .bss_info_changed = iwl_bss_info_changed,
fe6b23dd
RC
3839 .hw_scan = iwl_mac_hw_scan,
3840 .sta_add = iwl3945_mac_sta_add,
3841 .sta_remove = iwl_mac_sta_remove,
a85d7cca 3842 .tx_last_beacon = iwl_mac_tx_last_beacon,
b481de9c
ZY
3843};
3844
e52119c5 3845static int iwl3945_init_drv(struct iwl_priv *priv)
90a30a02
KA
3846{
3847 int ret;
e6148917 3848 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
90a30a02
KA
3849
3850 priv->retry_rate = 1;
12e934dc 3851 priv->beacon_skb = NULL;
90a30a02 3852
90a30a02
KA
3853 spin_lock_init(&priv->sta_lock);
3854 spin_lock_init(&priv->hcmd_lock);
3855
3856 INIT_LIST_HEAD(&priv->free_frames);
3857
3858 mutex_init(&priv->mutex);
d2dfe6df 3859 mutex_init(&priv->sync_cmd_mutex);
90a30a02 3860
90a30a02
KA
3861 priv->ieee_channels = NULL;
3862 priv->ieee_rates = NULL;
3863 priv->band = IEEE80211_BAND_2GHZ;
3864
3865 priv->iw_mode = NL80211_IFTYPE_STATION;
a13d276f 3866 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
90a30a02 3867
62ea9c5b 3868 priv->tx_power_user_lmt = IWL_DEFAULT_TX_POWER;
90a30a02 3869
e6148917
SO
3870 if (eeprom->version < EEPROM_3945_EEPROM_VERSION) {
3871 IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n",
3872 eeprom->version);
3873 ret = -EINVAL;
3874 goto err;
3875 }
3876 ret = iwl_init_channel_map(priv);
90a30a02
KA
3877 if (ret) {
3878 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3879 goto err;
3880 }
3881
e6148917
SO
3882 /* Set up txpower settings in driver for all channels */
3883 if (iwl3945_txpower_set_from_eeprom(priv)) {
3884 ret = -EIO;
3885 goto err_free_channel_map;
3886 }
3887
534166de 3888 ret = iwlcore_init_geos(priv);
90a30a02
KA
3889 if (ret) {
3890 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3891 goto err_free_channel_map;
3892 }
534166de
SO
3893 iwl3945_init_hw_rates(priv, priv->ieee_rates);
3894
2a4ddaab
AK
3895 return 0;
3896
3897err_free_channel_map:
3898 iwl_free_channel_map(priv);
3899err:
3900 return ret;
3901}
3902
dd7a2509
JB
3903#define IWL3945_MAX_PROBE_REQUEST 200
3904
2a4ddaab
AK
3905static int iwl3945_setup_mac(struct iwl_priv *priv)
3906{
3907 int ret;
3908 struct ieee80211_hw *hw = priv->hw;
3909
3910 hw->rate_control_algorithm = "iwl-3945-rs";
3911 hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
fd1af15d 3912 hw->vif_data_size = sizeof(struct iwl_vif_priv);
2a4ddaab
AK
3913
3914 /* Tell mac80211 our characteristics */
3915 hw->flags = IEEE80211_HW_SIGNAL_DBM |
bc45a670
RC
3916 IEEE80211_HW_SPECTRUM_MGMT;
3917
7cb1b088 3918 if (!priv->cfg->base_params->broken_powersave)
bc45a670
RC
3919 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3920 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2a4ddaab
AK
3921
3922 hw->wiphy->interface_modes =
d0fe478c 3923 priv->contexts[IWL_RXON_CTX_BSS].interface_modes;
2a4ddaab 3924
f6c8f152 3925 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
5be83de5 3926 WIPHY_FLAG_DISABLE_BEACON_HINTS;
37184244 3927
1ecf9fc1
JB
3928 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX_3945;
3929 /* we create the 802.11 header and a zero-length SSID element */
dd7a2509 3930 hw->wiphy->max_scan_ie_len = IWL3945_MAX_PROBE_REQUEST - 24 - 2;
d60cc91a 3931
2a4ddaab
AK
3932 /* Default value; 4 EDCA QOS priorities */
3933 hw->queues = 4;
3934
534166de
SO
3935 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3936 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3937 &priv->bands[IEEE80211_BAND_2GHZ];
2a4ddaab 3938
534166de
SO
3939 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3940 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3941 &priv->bands[IEEE80211_BAND_5GHZ];
90a30a02 3942
2a4ddaab
AK
3943 ret = ieee80211_register_hw(priv->hw);
3944 if (ret) {
3945 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3946 return ret;
3947 }
3948 priv->mac80211_registered = 1;
90a30a02 3949
2a4ddaab 3950 return 0;
90a30a02
KA
3951}
3952
bb8c093b 3953static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c 3954{
246ed355 3955 int err = 0, i;
4a8a4322 3956 struct iwl_priv *priv;
b481de9c 3957 struct ieee80211_hw *hw;
c0f20d91 3958 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
e6148917 3959 struct iwl3945_eeprom *eeprom;
0359facc 3960 unsigned long flags;
b481de9c 3961
cee53ddb
KA
3962 /***********************
3963 * 1. Allocating HW data
3964 * ********************/
3965
b481de9c
ZY
3966 /* mac80211 allocates memory for this device instance, including
3967 * space for this driver's private structure */
90a30a02 3968 hw = iwl_alloc_all(cfg, &iwl3945_hw_ops);
b481de9c 3969 if (hw == NULL) {
c96c31e4 3970 pr_err("Can not allocate network device\n");
b481de9c
ZY
3971 err = -ENOMEM;
3972 goto out;
3973 }
b481de9c 3974 priv = hw->priv;
90a30a02 3975 SET_IEEE80211_DEV(hw, &pdev->dev);
6440adb5 3976
13bb9483
JB
3977 priv->cmd_queue = IWL39_CMD_QUEUE_NUM;
3978
246ed355
JB
3979 /* 3945 has only one valid context */
3980 priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
3981
3982 for (i = 0; i < NUM_IWL_RXON_CTX; i++)
3983 priv->contexts[i].ctxid = i;
3984
8f2d3d2a
JB
3985 priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
3986 priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
3987 priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
8dfdb9d5 3988 priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
2995bafa 3989 priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
c10afb6e 3990 priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
d0fe478c
JB
3991 priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
3992 BIT(NL80211_IFTYPE_STATION) |
3993 BIT(NL80211_IFTYPE_ADHOC);
3994 priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
3995 priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
3996 priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
8f2d3d2a 3997
90a30a02
KA
3998 /*
3999 * Disabling hardware scan means that mac80211 will perform scans
4000 * "the hard way", rather than using device's scan.
4001 */
df878d8f 4002 if (iwl3945_mod_params.disable_hw_scan) {
72645eff 4003 IWL_ERR(priv, "sw scan support is deprecated\n");
40b8ec0b
SO
4004 iwl3945_hw_ops.hw_scan = NULL;
4005 }
4006
90a30a02 4007
e1623446 4008 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
90a30a02
KA
4009 priv->cfg = cfg;
4010 priv->pci_dev = pdev;
40cefda9 4011 priv->inta_mask = CSR_INI_SET_MASK;
cee53ddb 4012
20594eb0
WYG
4013 if (iwl_alloc_traffic_mem(priv))
4014 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 4015
cee53ddb
KA
4016 /***************************
4017 * 2. Initializing PCI bus
4018 * *************************/
1a7123cd
JL
4019 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4020 PCIE_LINK_STATE_CLKPM);
4021
b481de9c
ZY
4022 if (pci_enable_device(pdev)) {
4023 err = -ENODEV;
4024 goto out_ieee80211_free_hw;
4025 }
4026
4027 pci_set_master(pdev);
4028
284901a9 4029 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
b481de9c 4030 if (!err)
284901a9 4031 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
b481de9c 4032 if (err) {
978785a3 4033 IWL_WARN(priv, "No suitable DMA available.\n");
b481de9c
ZY
4034 goto out_pci_disable_device;
4035 }
4036
4037 pci_set_drvdata(pdev, priv);
4038 err = pci_request_regions(pdev, DRV_NAME);
4039 if (err)
4040 goto out_pci_disable_device;
6440adb5 4041
cee53ddb
KA
4042 /***********************
4043 * 3. Read REV Register
4044 * ********************/
b481de9c
ZY
4045 priv->hw_base = pci_iomap(pdev, 0, 0);
4046 if (!priv->hw_base) {
4047 err = -ENODEV;
4048 goto out_pci_release_regions;
4049 }
4050
e1623446 4051 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
b481de9c 4052 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 4053 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
b481de9c 4054
cee53ddb
KA
4055 /* We disable the RETRY_TIMEOUT register (0x41) to keep
4056 * PCI Tx retries from interfering with C3 CPU state */
4057 pci_write_config_byte(pdev, 0x41, 0x00);
b481de9c 4058
731a29b7 4059 /* these spin locks will be used in apm_ops.init and EEPROM access
a8b50a0a
MA
4060 * we should init now
4061 */
4062 spin_lock_init(&priv->reg_lock);
731a29b7 4063 spin_lock_init(&priv->lock);
a8b50a0a 4064
4843b5a7
RC
4065 /*
4066 * stop and reset the on-board processor just in case it is in a
4067 * strange state ... like being left stranded by a primary kernel
4068 * and this is now the kdump kernel trying to start up
4069 */
4070 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4071
cee53ddb
KA
4072 /***********************
4073 * 4. Read EEPROM
4074 * ********************/
90a30a02 4075
cee53ddb 4076 /* Read the EEPROM */
e6148917 4077 err = iwl_eeprom_init(priv);
cee53ddb 4078 if (err) {
15b1687c 4079 IWL_ERR(priv, "Unable to init EEPROM\n");
c8f16138 4080 goto out_iounmap;
cee53ddb
KA
4081 }
4082 /* MAC Address location in EEPROM same for 3945/4965 */
e6148917 4083 eeprom = (struct iwl3945_eeprom *)priv->eeprom;
30eabc17
JB
4084 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", eeprom->mac_address);
4085 SET_IEEE80211_PERM_ADDR(priv->hw, eeprom->mac_address);
b481de9c 4086
cee53ddb
KA
4087 /***********************
4088 * 5. Setup HW Constants
4089 * ********************/
b481de9c 4090 /* Device-specific setup */
3832ec9d 4091 if (iwl3945_hw_set_hw_params(priv)) {
15b1687c 4092 IWL_ERR(priv, "failed to set hw settings\n");
c8f16138 4093 goto out_eeprom_free;
b481de9c
ZY
4094 }
4095
cee53ddb
KA
4096 /***********************
4097 * 6. Setup priv
4098 * ********************/
cee53ddb 4099
90a30a02 4100 err = iwl3945_init_drv(priv);
b481de9c 4101 if (err) {
90a30a02 4102 IWL_ERR(priv, "initializing driver failed\n");
c8f16138 4103 goto out_unset_hw_params;
b481de9c
ZY
4104 }
4105
978785a3
TW
4106 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n",
4107 priv->cfg->name);
cee53ddb 4108
cee53ddb 4109 /***********************
09f9bf79 4110 * 7. Setup Services
cee53ddb
KA
4111 * ********************/
4112
4113 spin_lock_irqsave(&priv->lock, flags);
ed3b932e 4114 iwl_disable_interrupts(priv);
cee53ddb
KA
4115 spin_unlock_irqrestore(&priv->lock, flags);
4116
2663516d
HS
4117 pci_enable_msi(priv->pci_dev);
4118
ef850d7c
MA
4119 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
4120 IRQF_SHARED, DRV_NAME, priv);
2663516d
HS
4121 if (err) {
4122 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4123 goto out_disable_msi;
4124 }
4125
cee53ddb 4126 err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
849e0dce 4127 if (err) {
15b1687c 4128 IWL_ERR(priv, "failed to create sysfs device attributes\n");
90a30a02 4129 goto out_release_irq;
849e0dce 4130 }
849e0dce 4131
8ccde88a 4132 iwl_set_rxon_channel(priv,
246ed355
JB
4133 &priv->bands[IEEE80211_BAND_2GHZ].channels[5],
4134 &priv->contexts[IWL_RXON_CTX_BSS]);
cee53ddb
KA
4135 iwl3945_setup_deferred_work(priv);
4136 iwl3945_setup_rx_handlers(priv);
008a9e3e 4137 iwl_power_initialize(priv);
cee53ddb 4138
cee53ddb 4139 /*********************************
09f9bf79 4140 * 8. Setup and Register mac80211
cee53ddb
KA
4141 * *******************************/
4142
2a4ddaab 4143 iwl_enable_interrupts(priv);
b481de9c 4144
2a4ddaab
AK
4145 err = iwl3945_setup_mac(priv);
4146 if (err)
4147 goto out_remove_sysfs;
cee53ddb 4148
a75fbe8d
AK
4149 err = iwl_dbgfs_register(priv, DRV_NAME);
4150 if (err)
4151 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
4152
2663516d 4153 /* Start monitoring the killswitch */
ee525d13 4154 queue_delayed_work(priv->workqueue, &priv->_3945.rfkill_poll,
2663516d
HS
4155 2 * HZ);
4156
b481de9c
ZY
4157 return 0;
4158
cee53ddb 4159 out_remove_sysfs:
c8f16138
RC
4160 destroy_workqueue(priv->workqueue);
4161 priv->workqueue = NULL;
cee53ddb 4162 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 4163 out_release_irq:
2663516d 4164 free_irq(priv->pci_dev->irq, priv);
2663516d
HS
4165 out_disable_msi:
4166 pci_disable_msi(priv->pci_dev);
c8f16138
RC
4167 iwlcore_free_geos(priv);
4168 iwl_free_channel_map(priv);
4169 out_unset_hw_params:
4170 iwl3945_unset_hw_params(priv);
4171 out_eeprom_free:
4172 iwl_eeprom_free(priv);
b481de9c
ZY
4173 out_iounmap:
4174 pci_iounmap(pdev, priv->hw_base);
4175 out_pci_release_regions:
4176 pci_release_regions(pdev);
4177 out_pci_disable_device:
b481de9c 4178 pci_set_drvdata(pdev, NULL);
623d563e 4179 pci_disable_device(pdev);
b481de9c 4180 out_ieee80211_free_hw:
20594eb0 4181 iwl_free_traffic_mem(priv);
d7c76f4c 4182 ieee80211_free_hw(priv->hw);
b481de9c
ZY
4183 out:
4184 return err;
4185}
4186
c83dbf68 4187static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
b481de9c 4188{
4a8a4322 4189 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 4190 unsigned long flags;
b481de9c
ZY
4191
4192 if (!priv)
4193 return;
4194
e1623446 4195 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 4196
a75fbe8d
AK
4197 iwl_dbgfs_unregister(priv);
4198
b481de9c 4199 set_bit(STATUS_EXIT_PENDING, &priv->status);
b24d22b1 4200
d552bfb6
KA
4201 if (priv->mac80211_registered) {
4202 ieee80211_unregister_hw(priv->hw);
4203 priv->mac80211_registered = 0;
4204 } else {
4205 iwl3945_down(priv);
4206 }
b481de9c 4207
c166b25a
BC
4208 /*
4209 * Make sure device is reset to low power before unloading driver.
4210 * This may be redundant with iwl_down(), but there are paths to
4211 * run iwl_down() without calling apm_ops.stop(), and there are
4212 * paths to avoid running iwl_down() at all before leaving driver.
4213 * This (inexpensive) call *makes sure* device is reset.
4214 */
14e8e4af 4215 iwl_apm_stop(priv);
c166b25a 4216
0359facc
MA
4217 /* make sure we flush any pending irq or
4218 * tasklet for the driver
4219 */
4220 spin_lock_irqsave(&priv->lock, flags);
ed3b932e 4221 iwl_disable_interrupts(priv);
0359facc
MA
4222 spin_unlock_irqrestore(&priv->lock, flags);
4223
4224 iwl_synchronize_irq(priv);
4225
bb8c093b 4226 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 4227
ee525d13 4228 cancel_delayed_work_sync(&priv->_3945.rfkill_poll);
2663516d 4229
bb8c093b 4230 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY
4231
4232 if (priv->rxq.bd)
df833b1d 4233 iwl3945_rx_queue_free(priv, &priv->rxq);
bb8c093b 4234 iwl3945_hw_txq_ctx_free(priv);
b481de9c 4235
3832ec9d 4236 iwl3945_unset_hw_params(priv);
b481de9c 4237
6ef89d0a
MA
4238 /*netif_stop_queue(dev); */
4239 flush_workqueue(priv->workqueue);
4240
bb8c093b 4241 /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
b481de9c
ZY
4242 * priv->workqueue... so we can't take down the workqueue
4243 * until now... */
4244 destroy_workqueue(priv->workqueue);
4245 priv->workqueue = NULL;
20594eb0 4246 iwl_free_traffic_mem(priv);
b481de9c 4247
2663516d
HS
4248 free_irq(pdev->irq, priv);
4249 pci_disable_msi(pdev);
4250
b481de9c
ZY
4251 pci_iounmap(pdev, priv->hw_base);
4252 pci_release_regions(pdev);
4253 pci_disable_device(pdev);
4254 pci_set_drvdata(pdev, NULL);
4255
e6148917 4256 iwl_free_channel_map(priv);
534166de 4257 iwlcore_free_geos(priv);
811ecc99 4258 kfree(priv->scan_cmd);
12e934dc
JB
4259 if (priv->beacon_skb)
4260 dev_kfree_skb(priv->beacon_skb);
b481de9c
ZY
4261
4262 ieee80211_free_hw(priv->hw);
4263}
4264
b481de9c
ZY
4265
4266/*****************************************************************************
4267 *
4268 * driver and module entry point
4269 *
4270 *****************************************************************************/
4271
bb8c093b 4272static struct pci_driver iwl3945_driver = {
b481de9c 4273 .name = DRV_NAME,
bb8c093b
CH
4274 .id_table = iwl3945_hw_card_ids,
4275 .probe = iwl3945_pci_probe,
4276 .remove = __devexit_p(iwl3945_pci_remove),
b481de9c 4277#ifdef CONFIG_PM
6da3a13e
WYG
4278 .suspend = iwl_pci_suspend,
4279 .resume = iwl_pci_resume,
b481de9c
ZY
4280#endif
4281};
4282
bb8c093b 4283static int __init iwl3945_init(void)
b481de9c
ZY
4284{
4285
4286 int ret;
c96c31e4
JP
4287 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4288 pr_info(DRV_COPYRIGHT "\n");
897e1cf2
RC
4289
4290 ret = iwl3945_rate_control_register();
4291 if (ret) {
c96c31e4 4292 pr_err("Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC
4293 return ret;
4294 }
4295
bb8c093b 4296 ret = pci_register_driver(&iwl3945_driver);
b481de9c 4297 if (ret) {
c96c31e4 4298 pr_err("Unable to initialize PCI module\n");
897e1cf2 4299 goto error_register;
b481de9c 4300 }
b481de9c
ZY
4301
4302 return ret;
897e1cf2 4303
897e1cf2
RC
4304error_register:
4305 iwl3945_rate_control_unregister();
4306 return ret;
b481de9c
ZY
4307}
4308
bb8c093b 4309static void __exit iwl3945_exit(void)
b481de9c 4310{
bb8c093b 4311 pci_unregister_driver(&iwl3945_driver);
897e1cf2 4312 iwl3945_rate_control_unregister();
b481de9c
ZY
4313}
4314
a0987a8d 4315MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
25cb6cad 4316
4e30cb69 4317module_param_named(antenna, iwl3945_mod_params.antenna, int, S_IRUGO);
b481de9c 4318MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
4e30cb69 4319module_param_named(swcrypto, iwl3945_mod_params.sw_crypto, int, S_IRUGO);
9c74d9fb
SO
4320MODULE_PARM_DESC(swcrypto,
4321 "using software crypto (default 1 [software])\n");
a562a9dd 4322#ifdef CONFIG_IWLWIFI_DEBUG
4e30cb69 4323module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
b481de9c 4324MODULE_PARM_DESC(debug, "debug output mask");
a562a9dd 4325#endif
4e30cb69
WYG
4326module_param_named(disable_hw_scan, iwl3945_mod_params.disable_hw_scan,
4327 int, S_IRUGO);
72645eff
WYG
4328MODULE_PARM_DESC(disable_hw_scan,
4329 "disable hardware scanning (default 0) (deprecated)");
4e30cb69 4330module_param_named(fw_restart3945, iwl3945_mod_params.restart_fw, int, S_IRUGO);
af48d048
SO
4331MODULE_PARM_DESC(fw_restart3945, "restart firmware in case of error");
4332
bb8c093b
CH
4333module_exit(iwl3945_exit);
4334module_init(iwl3945_init);
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