Merge branch 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jack/linux...
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl3945-base.c
CommitLineData
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1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
b481de9c
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4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
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26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
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30#include <linux/kernel.h>
31#include <linux/module.h>
b481de9c
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32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
36#include <linux/skbuff.h>
37#include <linux/netdevice.h>
38#include <linux/wireless.h>
39#include <linux/firmware.h>
b481de9c
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40#include <linux/etherdevice.h>
41#include <linux/if_arp.h>
42
43#include <net/ieee80211_radiotap.h>
7e272fcf 44#include <net/lib80211.h>
b481de9c
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45#include <net/mac80211.h>
46
47#include <asm/div64.h>
48
a3139c59
SO
49#define DRV_NAME "iwl3945"
50
dbb6654c
WT
51#include "iwl-fh.h"
52#include "iwl-3945-fh.h"
600c0e11 53#include "iwl-commands.h"
17f841cd 54#include "iwl-sta.h"
b481de9c
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55#include "iwl-3945.h"
56#include "iwl-helpers.h"
5747d47f 57#include "iwl-core.h"
d20b3c65 58#include "iwl-dev.h"
b481de9c 59
b481de9c
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60/*
61 * module name, copyright, version, etc.
b481de9c
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62 */
63
64#define DRV_DESCRIPTION \
65"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
66
d08853a3 67#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
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68#define VD "d"
69#else
70#define VD
71#endif
72
c8b0e6e1 73#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
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74#define VS "s"
75#else
76#define VS
77#endif
78
eaa686c3 79#define IWL39_VERSION "1.2.26k" VD VS
01f8162a 80#define DRV_COPYRIGHT "Copyright(c) 2003-2009 Intel Corporation"
a7b75207 81#define DRV_AUTHOR "<ilw@linux.intel.com>"
eaa686c3 82#define DRV_VERSION IWL39_VERSION
b481de9c 83
b481de9c
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84
85MODULE_DESCRIPTION(DRV_DESCRIPTION);
86MODULE_VERSION(DRV_VERSION);
a7b75207 87MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c
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88MODULE_LICENSE("GPL");
89
df878d8f
KA
90 /* module parameters */
91struct iwl_mod_params iwl3945_mod_params = {
5905a1aa 92 .num_of_queues = IWL39_NUM_QUEUES, /* Not used */
9c74d9fb 93 .sw_crypto = 1,
af48d048 94 .restart_fw = 1,
df878d8f
KA
95 /* the rest are 0 by default */
96};
97
7e4bca5e
SO
98/**
99 * iwl3945_get_antenna_flags - Get antenna flags for RXON command
100 * @priv: eeprom and antenna fields are used to determine antenna flags
101 *
102 * priv->eeprom39 is used to determine if antenna AUX/MAIN are reversed
103 * iwl3945_mod_params.antenna specifies the antenna diversity mode:
104 *
105 * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
106 * IWL_ANTENNA_MAIN - Force MAIN antenna
107 * IWL_ANTENNA_AUX - Force AUX antenna
108 */
109__le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv)
110{
111 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
112
113 switch (iwl3945_mod_params.antenna) {
114 case IWL_ANTENNA_DIVERSITY:
115 return 0;
116
117 case IWL_ANTENNA_MAIN:
118 if (eeprom->antenna_switch_type)
119 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
120 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
121
122 case IWL_ANTENNA_AUX:
123 if (eeprom->antenna_switch_type)
124 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
125 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
126 }
127
128 /* bad antenna selector value */
129 IWL_ERR(priv, "Bad antenna selector value (0x%x)\n",
130 iwl3945_mod_params.antenna);
131
132 return 0; /* "diversity" is default if error */
133}
134
6e21f15c 135static int iwl3945_set_ccmp_dynamic_key_info(struct iwl_priv *priv,
b481de9c
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136 struct ieee80211_key_conf *keyconf,
137 u8 sta_id)
138{
139 unsigned long flags;
140 __le16 key_flags = 0;
6e21f15c
AK
141 int ret;
142
143 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
144 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
145
146 if (sta_id == priv->hw_params.bcast_sta_id)
147 key_flags |= STA_KEY_MULTICAST_MSK;
148
149 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
150 keyconf->hw_key_idx = keyconf->keyidx;
151 key_flags &= ~STA_KEY_FLG_INVALID;
b481de9c 152
b481de9c 153 spin_lock_irqsave(&priv->sta_lock, flags);
c587de0b
TW
154 priv->stations[sta_id].keyinfo.alg = keyconf->alg;
155 priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
156 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
b481de9c
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157 keyconf->keylen);
158
c587de0b 159 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
b481de9c 160 keyconf->keylen);
6e21f15c 161
c587de0b 162 if ((priv->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK)
6e21f15c 163 == STA_KEY_FLG_NO_ENC)
c587de0b 164 priv->stations[sta_id].sta.key.key_offset =
6e21f15c
AK
165 iwl_get_free_ucode_key_index(priv);
166 /* else, we are overriding an existing key => no need to allocated room
167 * in uCode. */
168
c587de0b 169 WARN(priv->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
6e21f15c
AK
170 "no space for a new key");
171
c587de0b
TW
172 priv->stations[sta_id].sta.key.key_flags = key_flags;
173 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
174 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
b481de9c 175
6e21f15c
AK
176 IWL_DEBUG_INFO(priv, "hwcrypto: modify ucode station key info\n");
177
c587de0b 178 ret = iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
6e21f15c 179
b481de9c
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180 spin_unlock_irqrestore(&priv->sta_lock, flags);
181
6e21f15c
AK
182 return ret;
183}
184
185static int iwl3945_set_tkip_dynamic_key_info(struct iwl_priv *priv,
186 struct ieee80211_key_conf *keyconf,
187 u8 sta_id)
188{
189 return -EOPNOTSUPP;
190}
191
192static int iwl3945_set_wep_dynamic_key_info(struct iwl_priv *priv,
193 struct ieee80211_key_conf *keyconf,
194 u8 sta_id)
195{
196 return -EOPNOTSUPP;
b481de9c
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197}
198
4a8a4322 199static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id)
b481de9c
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200{
201 unsigned long flags;
202
203 spin_lock_irqsave(&priv->sta_lock, flags);
c587de0b
TW
204 memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl_hw_key));
205 memset(&priv->stations[sta_id].sta.key, 0,
4c897253 206 sizeof(struct iwl4965_keyinfo));
c587de0b
TW
207 priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
208 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
209 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
b481de9c
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210 spin_unlock_irqrestore(&priv->sta_lock, flags);
211
e1623446 212 IWL_DEBUG_INFO(priv, "hwcrypto: clear ucode station key info\n");
c587de0b 213 iwl_send_add_sta(priv, &priv->stations[sta_id].sta, 0);
b481de9c
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214 return 0;
215}
216
fa11d525 217static int iwl3945_set_dynamic_key(struct iwl_priv *priv,
6e21f15c
AK
218 struct ieee80211_key_conf *keyconf, u8 sta_id)
219{
220 int ret = 0;
221
222 keyconf->hw_key_idx = HW_KEY_DYNAMIC;
223
224 switch (keyconf->alg) {
225 case ALG_CCMP:
226 ret = iwl3945_set_ccmp_dynamic_key_info(priv, keyconf, sta_id);
227 break;
228 case ALG_TKIP:
229 ret = iwl3945_set_tkip_dynamic_key_info(priv, keyconf, sta_id);
230 break;
231 case ALG_WEP:
232 ret = iwl3945_set_wep_dynamic_key_info(priv, keyconf, sta_id);
233 break;
234 default:
1e680233 235 IWL_ERR(priv, "Unknown alg: %s alg = %d\n", __func__, keyconf->alg);
6e21f15c
AK
236 ret = -EINVAL;
237 }
238
239 IWL_DEBUG_WEP(priv, "Set dynamic key: alg= %d len=%d idx=%d sta=%d ret=%d\n",
240 keyconf->alg, keyconf->keylen, keyconf->keyidx,
241 sta_id, ret);
242
243 return ret;
244}
245
246static int iwl3945_remove_static_key(struct iwl_priv *priv)
247{
248 int ret = -EOPNOTSUPP;
249
250 return ret;
251}
252
253static int iwl3945_set_static_key(struct iwl_priv *priv,
254 struct ieee80211_key_conf *key)
255{
256 if (key->alg == ALG_WEP)
257 return -EOPNOTSUPP;
258
259 IWL_ERR(priv, "Static key invalid: alg %d\n", key->alg);
260 return -EINVAL;
261}
262
4a8a4322 263static void iwl3945_clear_free_frames(struct iwl_priv *priv)
b481de9c
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264{
265 struct list_head *element;
266
e1623446 267 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
b481de9c
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268 priv->frames_count);
269
270 while (!list_empty(&priv->free_frames)) {
271 element = priv->free_frames.next;
272 list_del(element);
bb8c093b 273 kfree(list_entry(element, struct iwl3945_frame, list));
b481de9c
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274 priv->frames_count--;
275 }
276
277 if (priv->frames_count) {
39aadf8c 278 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
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279 priv->frames_count);
280 priv->frames_count = 0;
281 }
282}
283
4a8a4322 284static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv)
b481de9c 285{
bb8c093b 286 struct iwl3945_frame *frame;
b481de9c
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287 struct list_head *element;
288 if (list_empty(&priv->free_frames)) {
289 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
290 if (!frame) {
15b1687c 291 IWL_ERR(priv, "Could not allocate frame!\n");
b481de9c
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292 return NULL;
293 }
294
295 priv->frames_count++;
296 return frame;
297 }
298
299 element = priv->free_frames.next;
300 list_del(element);
bb8c093b 301 return list_entry(element, struct iwl3945_frame, list);
b481de9c
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302}
303
4a8a4322 304static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame)
b481de9c
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305{
306 memset(frame, 0, sizeof(*frame));
307 list_add(&frame->list, &priv->free_frames);
308}
309
4a8a4322 310unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv,
b481de9c 311 struct ieee80211_hdr *hdr,
73ec1cc2 312 int left)
b481de9c
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313{
314
8ccde88a 315 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB
316 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
317 (priv->iw_mode != NL80211_IFTYPE_AP)))
b481de9c
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318 return 0;
319
320 if (priv->ibss_beacon->len > left)
321 return 0;
322
323 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
324
325 return priv->ibss_beacon->len;
326}
327
4a8a4322 328static int iwl3945_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 329{
bb8c093b 330 struct iwl3945_frame *frame;
b481de9c
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331 unsigned int frame_size;
332 int rc;
333 u8 rate;
334
bb8c093b 335 frame = iwl3945_get_free_frame(priv);
b481de9c
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336
337 if (!frame) {
15b1687c 338 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
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339 "command.\n");
340 return -ENOMEM;
341 }
342
8ccde88a 343 rate = iwl_rate_get_lowest_plcp(priv);
b481de9c 344
bb8c093b 345 frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 346
518099a8 347 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
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348 &frame->u.cmd[0]);
349
bb8c093b 350 iwl3945_free_frame(priv, frame);
b481de9c
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351
352 return rc;
353}
354
4a8a4322 355static void iwl3945_unset_hw_params(struct iwl_priv *priv)
b481de9c 356{
3832ec9d 357 if (priv->shared_virt)
b481de9c 358 pci_free_consistent(priv->pci_dev,
bb8c093b 359 sizeof(struct iwl3945_shared),
3832ec9d
AK
360 priv->shared_virt,
361 priv->shared_phys);
b481de9c
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362}
363
4a8a4322 364static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv,
e039fa4a 365 struct ieee80211_tx_info *info,
c2acea8e 366 struct iwl_device_cmd *cmd,
b481de9c 367 struct sk_buff *skb_frag,
6e21f15c 368 int sta_id)
b481de9c 369{
e52119c5 370 struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
c587de0b 371 struct iwl_hw_key *keyinfo = &priv->stations[sta_id].keyinfo;
b481de9c
ZY
372
373 switch (keyinfo->alg) {
374 case ALG_CCMP:
e52119c5
WT
375 tx->sec_ctl = TX_CMD_SEC_CCM;
376 memcpy(tx->key, keyinfo->key, keyinfo->keylen);
e1623446 377 IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
b481de9c
ZY
378 break;
379
380 case ALG_TKIP:
b481de9c
ZY
381 break;
382
383 case ALG_WEP:
e52119c5 384 tx->sec_ctl = TX_CMD_SEC_WEP |
e039fa4a 385 (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
b481de9c
ZY
386
387 if (keyinfo->keylen == 13)
e52119c5 388 tx->sec_ctl |= TX_CMD_SEC_KEY128;
b481de9c 389
e52119c5 390 memcpy(&tx->key[3], keyinfo->key, keyinfo->keylen);
b481de9c 391
e1623446 392 IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
e039fa4a 393 "with key %d\n", info->control.hw_key->hw_key_idx);
b481de9c
ZY
394 break;
395
b481de9c 396 default:
978785a3 397 IWL_ERR(priv, "Unknown encode alg %d\n", keyinfo->alg);
b481de9c
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398 break;
399 }
400}
401
402/*
403 * handle build REPLY_TX command notification.
404 */
4a8a4322 405static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv,
c2acea8e 406 struct iwl_device_cmd *cmd,
e039fa4a 407 struct ieee80211_tx_info *info,
e52119c5 408 struct ieee80211_hdr *hdr, u8 std_id)
b481de9c 409{
e52119c5
WT
410 struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
411 __le32 tx_flags = tx->tx_flags;
fd7c8a40 412 __le16 fc = hdr->frame_control;
e6a9854b 413 u8 rc_flags = info->control.rates[0].flags;
b481de9c 414
e52119c5 415 tx->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e039fa4a 416 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
b481de9c 417 tx_flags |= TX_CMD_FLG_ACK_MSK;
fd7c8a40 418 if (ieee80211_is_mgmt(fc))
b481de9c 419 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
fd7c8a40 420 if (ieee80211_is_probe_resp(fc) &&
b481de9c
ZY
421 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
422 tx_flags |= TX_CMD_FLG_TSF_MSK;
423 } else {
424 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
425 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
426 }
427
e52119c5 428 tx->sta_id = std_id;
8b7b1e05 429 if (ieee80211_has_morefrags(fc))
b481de9c
ZY
430 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
431
fd7c8a40
HH
432 if (ieee80211_is_data_qos(fc)) {
433 u8 *qc = ieee80211_get_qos_ctl(hdr);
e52119c5 434 tx->tid_tspec = qc[0] & 0xf;
b481de9c 435 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 436 } else {
b481de9c 437 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 438 }
b481de9c 439
e6a9854b 440 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
b481de9c
ZY
441 tx_flags |= TX_CMD_FLG_RTS_MSK;
442 tx_flags &= ~TX_CMD_FLG_CTS_MSK;
e6a9854b 443 } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
b481de9c
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444 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
445 tx_flags |= TX_CMD_FLG_CTS_MSK;
446 }
447
448 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
449 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
450
451 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
fd7c8a40
HH
452 if (ieee80211_is_mgmt(fc)) {
453 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
e52119c5 454 tx->timeout.pm_frame_timeout = cpu_to_le16(3);
b481de9c 455 else
e52119c5 456 tx->timeout.pm_frame_timeout = cpu_to_le16(2);
ab53d8af 457 } else {
e52119c5 458 tx->timeout.pm_frame_timeout = 0;
5c8df2d5 459#ifdef CONFIG_IWLWIFI_LEDS
ab53d8af
MA
460 priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
461#endif
462 }
b481de9c 463
e52119c5
WT
464 tx->driver_txop = 0;
465 tx->tx_flags = tx_flags;
466 tx->next_frame_len = 0;
b481de9c
ZY
467}
468
b481de9c
ZY
469/*
470 * start REPLY_TX command process
471 */
4a8a4322 472static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
b481de9c
ZY
473{
474 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
e039fa4a 475 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
e52119c5 476 struct iwl3945_tx_cmd *tx;
188cf6c7 477 struct iwl_tx_queue *txq = NULL;
d20b3c65 478 struct iwl_queue *q = NULL;
c2acea8e
JB
479 struct iwl_device_cmd *out_cmd;
480 struct iwl_cmd_meta *out_meta;
b481de9c
ZY
481 dma_addr_t phys_addr;
482 dma_addr_t txcmd_phys;
e52119c5 483 int txq_id = skb_get_queue_mapping(skb);
df833b1d 484 u16 len, idx, len_org, hdr_len; /* TODO: len_org is not used */
54dbb525
TW
485 u8 id;
486 u8 unicast;
b481de9c 487 u8 sta_id;
54dbb525 488 u8 tid = 0;
b481de9c 489 u16 seq_number = 0;
fd7c8a40 490 __le16 fc;
b481de9c 491 u8 wait_write_ptr = 0;
54dbb525 492 u8 *qc = NULL;
b481de9c
ZY
493 unsigned long flags;
494 int rc;
495
496 spin_lock_irqsave(&priv->lock, flags);
775a6e27 497 if (iwl_is_rfkill(priv)) {
e1623446 498 IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
b481de9c
ZY
499 goto drop_unlock;
500 }
501
e039fa4a 502 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
15b1687c 503 IWL_ERR(priv, "ERROR: No TX rate available.\n");
b481de9c
ZY
504 goto drop_unlock;
505 }
506
507 unicast = !is_multicast_ether_addr(hdr->addr1);
508 id = 0;
509
fd7c8a40 510 fc = hdr->frame_control;
b481de9c 511
d08853a3 512#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c 513 if (ieee80211_is_auth(fc))
e1623446 514 IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
fd7c8a40 515 else if (ieee80211_is_assoc_req(fc))
e1623446 516 IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
fd7c8a40 517 else if (ieee80211_is_reassoc_req(fc))
e1623446 518 IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
b481de9c
ZY
519#endif
520
aa065263 521 /* drop all non-injected data frame if we are not associated */
914233d6 522 if (ieee80211_is_data(fc) &&
aa065263 523 !(info->flags & IEEE80211_TX_CTL_INJECTED) &&
8ccde88a 524 (!iwl_is_associated(priv) ||
05c914fe 525 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
e1623446 526 IWL_DEBUG_DROP(priv, "Dropping - !iwl_is_associated\n");
b481de9c
ZY
527 goto drop_unlock;
528 }
529
530 spin_unlock_irqrestore(&priv->lock, flags);
531
7294ec95 532 hdr_len = ieee80211_hdrlen(fc);
6440adb5
CB
533
534 /* Find (or create) index into station table for destination station */
aa065263
GS
535 if (info->flags & IEEE80211_TX_CTL_INJECTED)
536 sta_id = priv->hw_params.bcast_sta_id;
537 else
538 sta_id = iwl_get_sta_id(priv, hdr);
b481de9c 539 if (sta_id == IWL_INVALID_STATION) {
e1623446 540 IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
e174961c 541 hdr->addr1);
b481de9c
ZY
542 goto drop;
543 }
544
e1623446 545 IWL_DEBUG_RATE(priv, "station Id %d\n", sta_id);
b481de9c 546
fd7c8a40
HH
547 if (ieee80211_is_data_qos(fc)) {
548 qc = ieee80211_get_qos_ctl(hdr);
7294ec95 549 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
e6a6cf4c
RC
550 if (unlikely(tid >= MAX_TID_COUNT))
551 goto drop;
c587de0b 552 seq_number = priv->stations[sta_id].tid[tid].seq_number &
b481de9c
ZY
553 IEEE80211_SCTL_SEQ;
554 hdr->seq_ctrl = cpu_to_le16(seq_number) |
555 (hdr->seq_ctrl &
c1b4aa3f 556 cpu_to_le16(IEEE80211_SCTL_FRAG));
b481de9c
ZY
557 seq_number += 0x10;
558 }
6440adb5
CB
559
560 /* Descriptor for chosen Tx queue */
188cf6c7 561 txq = &priv->txq[txq_id];
b481de9c
ZY
562 q = &txq->q;
563
564 spin_lock_irqsave(&priv->lock, flags);
565
fc4b6853 566 idx = get_cmd_index(q, q->write_ptr, 0);
b481de9c 567
6440adb5 568 /* Set up driver data for this TFD */
dbb6654c 569 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
fc4b6853 570 txq->txb[q->write_ptr].skb[0] = skb;
6440adb5
CB
571
572 /* Init first empty entry in queue's array of Tx/cmd buffers */
188cf6c7 573 out_cmd = txq->cmd[idx];
c2acea8e 574 out_meta = &txq->meta[idx];
e52119c5 575 tx = (struct iwl3945_tx_cmd *)out_cmd->cmd.payload;
b481de9c 576 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
e52119c5 577 memset(tx, 0, sizeof(*tx));
6440adb5
CB
578
579 /*
580 * Set up the Tx-command (not MAC!) header.
581 * Store the chosen Tx queue and TFD index within the sequence field;
582 * after Tx, uCode's Tx response will return this value so driver can
583 * locate the frame within the tx queue and do post-tx processing.
584 */
b481de9c
ZY
585 out_cmd->hdr.cmd = REPLY_TX;
586 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
fc4b6853 587 INDEX_TO_SEQ(q->write_ptr)));
6440adb5
CB
588
589 /* Copy MAC header from skb into command buffer */
e52119c5 590 memcpy(tx->hdr, hdr, hdr_len);
b481de9c 591
df833b1d
RC
592
593 if (info->control.hw_key)
594 iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, sta_id);
595
596 /* TODO need this for burst mode later on */
597 iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, sta_id);
598
599 /* set is_hcca to 0; it probably will never be implemented */
600 iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
601
602 /* Total # bytes to be transmitted */
603 len = (u16)skb->len;
604 tx->len = cpu_to_le16(len);
605
20594eb0 606 iwl_dbg_log_tx_data_frame(priv, len, hdr);
22fdf3c9 607 iwl_update_stats(priv, true, fc, len);
df833b1d
RC
608 tx->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
609 tx->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
610
611 if (!ieee80211_has_morefrags(hdr->frame_control)) {
612 txq->need_update = 1;
613 if (qc)
c587de0b 614 priv->stations[sta_id].tid[tid].seq_number = seq_number;
df833b1d
RC
615 } else {
616 wait_write_ptr = 1;
617 txq->need_update = 0;
618 }
619
620 IWL_DEBUG_TX(priv, "sequence nr = 0X%x \n",
621 le16_to_cpu(out_cmd->hdr.sequence));
622 IWL_DEBUG_TX(priv, "tx_flags = 0X%x \n", le32_to_cpu(tx->tx_flags));
3d816c77
RC
623 iwl_print_hex_dump(priv, IWL_DL_TX, tx, sizeof(*tx));
624 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx->hdr,
df833b1d
RC
625 ieee80211_hdrlen(fc));
626
6440adb5
CB
627 /*
628 * Use the first empty entry in this queue's command buffer array
629 * to contain the Tx command and MAC header concatenated together
630 * (payload data will be in another buffer).
631 * Size of this varies, due to varying MAC header length.
632 * If end is not dword aligned, we'll have 2 extra bytes at the end
633 * of the MAC header (device reads on dword boundaries).
634 * We'll tell device about this padding later.
635 */
3832ec9d 636 len = sizeof(struct iwl3945_tx_cmd) +
4c897253 637 sizeof(struct iwl_cmd_header) + hdr_len;
b481de9c
ZY
638
639 len_org = len;
640 len = (len + 3) & ~3;
641
642 if (len_org != len)
643 len_org = 1;
644 else
645 len_org = 0;
646
6440adb5
CB
647 /* Physical address of this Tx command's header (not MAC header!),
648 * within command buffer array. */
df833b1d
RC
649 txcmd_phys = pci_map_single(priv->pci_dev, &out_cmd->hdr,
650 len, PCI_DMA_TODEVICE);
651 /* we do not map meta data ... so we can safely access address to
652 * provide to unmap command*/
c2acea8e
JB
653 pci_unmap_addr_set(out_meta, mapping, txcmd_phys);
654 pci_unmap_len_set(out_meta, len, len);
b481de9c 655
6440adb5
CB
656 /* Add buffer containing Tx command and MAC(!) header to TFD's
657 * first entry */
7aaa1d79
SO
658 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
659 txcmd_phys, len, 1, 0);
b481de9c 660
b481de9c 661
6440adb5
CB
662 /* Set up TFD's 2nd entry to point directly to remainder of skb,
663 * if any (802.11 null frames have no payload). */
b481de9c
ZY
664 len = skb->len - hdr_len;
665 if (len) {
666 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
667 len, PCI_DMA_TODEVICE);
7aaa1d79
SO
668 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
669 phys_addr, len,
670 0, U32_PAD(len));
b481de9c
ZY
671 }
672
b481de9c 673
6440adb5 674 /* Tell device the write index *just past* this latest filled TFD */
c54b679d 675 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
4f3602c8 676 rc = iwl_txq_update_write_ptr(priv, txq);
b481de9c
ZY
677 spin_unlock_irqrestore(&priv->lock, flags);
678
679 if (rc)
680 return rc;
681
d20b3c65 682 if ((iwl_queue_space(q) < q->high_mark)
b481de9c
ZY
683 && priv->mac80211_registered) {
684 if (wait_write_ptr) {
685 spin_lock_irqsave(&priv->lock, flags);
686 txq->need_update = 1;
4f3602c8 687 iwl_txq_update_write_ptr(priv, txq);
b481de9c
ZY
688 spin_unlock_irqrestore(&priv->lock, flags);
689 }
690
e4e72fb4 691 iwl_stop_queue(priv, skb_get_queue_mapping(skb));
b481de9c
ZY
692 }
693
694 return 0;
695
696drop_unlock:
697 spin_unlock_irqrestore(&priv->lock, flags);
698drop:
699 return -1;
700}
701
c8b0e6e1 702#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY
703
704#include "iwl-spectrum.h"
705
706#define BEACON_TIME_MASK_LOW 0x00FFFFFF
707#define BEACON_TIME_MASK_HIGH 0xFF000000
708#define TIME_UNIT 1024
709
710/*
711 * extended beacon time format
712 * time in usec will be changed into a 32-bit value in 8:24 format
713 * the high 1 byte is the beacon counts
714 * the lower 3 bytes is the time in usec within one beacon interval
715 */
716
bb8c093b 717static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
b481de9c
ZY
718{
719 u32 quot;
720 u32 rem;
721 u32 interval = beacon_interval * 1024;
722
723 if (!interval || !usec)
724 return 0;
725
726 quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
727 rem = (usec % interval) & BEACON_TIME_MASK_LOW;
728
729 return (quot << 24) + rem;
730}
731
732/* base is usually what we get from ucode with each received frame,
733 * the same as HW timer counter counting down
734 */
735
bb8c093b 736static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
b481de9c
ZY
737{
738 u32 base_low = base & BEACON_TIME_MASK_LOW;
739 u32 addon_low = addon & BEACON_TIME_MASK_LOW;
740 u32 interval = beacon_interval * TIME_UNIT;
741 u32 res = (base & BEACON_TIME_MASK_HIGH) +
742 (addon & BEACON_TIME_MASK_HIGH);
743
744 if (base_low > addon_low)
745 res += base_low - addon_low;
746 else if (base_low < addon_low) {
747 res += interval + base_low - addon_low;
748 res += (1 << 24);
749 } else
750 res += (1 << 24);
751
752 return cpu_to_le32(res);
753}
754
4a8a4322 755static int iwl3945_get_measurement(struct iwl_priv *priv,
b481de9c
ZY
756 struct ieee80211_measurement_params *params,
757 u8 type)
758{
600c0e11 759 struct iwl_spectrum_cmd spectrum;
3d24a9f7 760 struct iwl_rx_packet *res;
c2d79b48 761 struct iwl_host_cmd cmd = {
b481de9c
ZY
762 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
763 .data = (void *)&spectrum,
c2acea8e 764 .flags = CMD_WANT_SKB,
b481de9c
ZY
765 };
766 u32 add_time = le64_to_cpu(params->start_time);
767 int rc;
768 int spectrum_resp_status;
769 int duration = le16_to_cpu(params->duration);
770
8ccde88a 771 if (iwl_is_associated(priv))
b481de9c 772 add_time =
bb8c093b 773 iwl3945_usecs_to_beacons(
b481de9c
ZY
774 le64_to_cpu(params->start_time) - priv->last_tsf,
775 le16_to_cpu(priv->rxon_timing.beacon_interval));
776
777 memset(&spectrum, 0, sizeof(spectrum));
778
779 spectrum.channel_count = cpu_to_le16(1);
780 spectrum.flags =
781 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
782 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
783 cmd.len = sizeof(spectrum);
784 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
785
8ccde88a 786 if (iwl_is_associated(priv))
b481de9c 787 spectrum.start_time =
bb8c093b 788 iwl3945_add_beacon_time(priv->last_beacon_time,
b481de9c
ZY
789 add_time,
790 le16_to_cpu(priv->rxon_timing.beacon_interval));
791 else
792 spectrum.start_time = 0;
793
794 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
795 spectrum.channels[0].channel = params->channel;
796 spectrum.channels[0].type = type;
8ccde88a 797 if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
b481de9c
ZY
798 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
799 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
800
518099a8 801 rc = iwl_send_cmd_sync(priv, &cmd);
b481de9c
ZY
802 if (rc)
803 return rc;
804
c2acea8e 805 res = (struct iwl_rx_packet *)cmd.reply_skb->data;
b481de9c 806 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
15b1687c 807 IWL_ERR(priv, "Bad return from REPLY_RX_ON_ASSOC command\n");
b481de9c
ZY
808 rc = -EIO;
809 }
810
811 spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
812 switch (spectrum_resp_status) {
813 case 0: /* Command will be handled */
814 if (res->u.spectrum.id != 0xff) {
e1623446 815 IWL_DEBUG_INFO(priv, "Replaced existing measurement: %d\n",
bc434dd2 816 res->u.spectrum.id);
b481de9c
ZY
817 priv->measurement_status &= ~MEASUREMENT_READY;
818 }
819 priv->measurement_status |= MEASUREMENT_ACTIVE;
820 rc = 0;
821 break;
822
823 case 1: /* Command will not be handled */
824 rc = -EAGAIN;
825 break;
826 }
827
c2acea8e 828 dev_kfree_skb_any(cmd.reply_skb);
b481de9c
ZY
829
830 return rc;
831}
832#endif
833
4a8a4322 834static void iwl3945_rx_reply_alive(struct iwl_priv *priv,
6100b588 835 struct iwl_rx_mem_buffer *rxb)
b481de9c 836{
3d24a9f7
TW
837 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
838 struct iwl_alive_resp *palive;
b481de9c
ZY
839 struct delayed_work *pwork;
840
841 palive = &pkt->u.alive_frame;
842
e1623446 843 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY
844 "0x%01X 0x%01X\n",
845 palive->is_valid, palive->ver_type,
846 palive->ver_subtype);
847
848 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 849 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
3d24a9f7
TW
850 memcpy(&priv->card_alive_init, &pkt->u.alive_frame,
851 sizeof(struct iwl_alive_resp));
b481de9c
ZY
852 pwork = &priv->init_alive_start;
853 } else {
e1623446 854 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 855 memcpy(&priv->card_alive, &pkt->u.alive_frame,
3d24a9f7 856 sizeof(struct iwl_alive_resp));
b481de9c 857 pwork = &priv->alive_start;
bb8c093b 858 iwl3945_disable_events(priv);
b481de9c
ZY
859 }
860
861 /* We delay the ALIVE response by 5ms to
862 * give the HW RF Kill time to activate... */
863 if (palive->is_valid == UCODE_VALID_OK)
864 queue_delayed_work(priv->workqueue, pwork,
865 msecs_to_jiffies(5));
866 else
39aadf8c 867 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY
868}
869
4a8a4322 870static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv,
6100b588 871 struct iwl_rx_mem_buffer *rxb)
b481de9c 872{
c7e035a9 873#ifdef CONFIG_IWLWIFI_DEBUG
3d24a9f7 874 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
c7e035a9 875#endif
b481de9c 876
e1623446 877 IWL_DEBUG_RX(priv, "Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
b481de9c
ZY
878 return;
879}
880
bb8c093b 881static void iwl3945_bg_beacon_update(struct work_struct *work)
b481de9c 882{
4a8a4322
AK
883 struct iwl_priv *priv =
884 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY
885 struct sk_buff *beacon;
886
887 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 888 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY
889
890 if (!beacon) {
15b1687c 891 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY
892 return;
893 }
894
895 mutex_lock(&priv->mutex);
896 /* new beacon skb is allocated every time; dispose previous.*/
897 if (priv->ibss_beacon)
898 dev_kfree_skb(priv->ibss_beacon);
899
900 priv->ibss_beacon = beacon;
901 mutex_unlock(&priv->mutex);
902
bb8c093b 903 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
904}
905
4a8a4322 906static void iwl3945_rx_beacon_notif(struct iwl_priv *priv,
6100b588 907 struct iwl_rx_mem_buffer *rxb)
b481de9c 908{
d08853a3 909#ifdef CONFIG_IWLWIFI_DEBUG
3d24a9f7 910 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
bb8c093b 911 struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
b481de9c
ZY
912 u8 rate = beacon->beacon_notify_hdr.rate;
913
e1623446 914 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c
ZY
915 "tsf %d %d rate %d\n",
916 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
917 beacon->beacon_notify_hdr.failure_frame,
918 le32_to_cpu(beacon->ibss_mgr_status),
919 le32_to_cpu(beacon->high_tsf),
920 le32_to_cpu(beacon->low_tsf), rate);
921#endif
922
05c914fe 923 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY
924 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
925 queue_work(priv->workqueue, &priv->beacon_update);
926}
927
b481de9c
ZY
928/* Handle notification from uCode that card's power state is changing
929 * due to software, hardware, or critical temperature RFKILL */
4a8a4322 930static void iwl3945_rx_card_state_notif(struct iwl_priv *priv,
6100b588 931 struct iwl_rx_mem_buffer *rxb)
b481de9c 932{
3d24a9f7 933 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY
934 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
935 unsigned long status = priv->status;
936
4c423a2b 937 IWL_WARN(priv, "Card state received: HW:%s SW:%s\n",
b481de9c
ZY
938 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
939 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
940
5d49f498 941 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
942 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
943
944 if (flags & HW_CARD_DISABLED)
945 set_bit(STATUS_RF_KILL_HW, &priv->status);
946 else
947 clear_bit(STATUS_RF_KILL_HW, &priv->status);
948
949
af0053d6 950 iwl_scan_cancel(priv);
b481de9c
ZY
951
952 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB
953 test_bit(STATUS_RF_KILL_HW, &priv->status)))
954 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
955 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY
956 else
957 wake_up_interruptible(&priv->wait_command_queue);
958}
959
960/**
bb8c093b 961 * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY
962 *
963 * Setup the RX handlers for each of the reply types sent from the uCode
964 * to the host.
965 *
966 * This function chains into the hardware specific files for them to setup
967 * any hardware specific handlers as well.
968 */
4a8a4322 969static void iwl3945_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 970{
bb8c093b
CH
971 priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
972 priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
261b9c33 973 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
8ccde88a 974 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
030f05ed 975 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 976 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
030f05ed 977 iwl_rx_pm_debug_statistics_notif;
bb8c093b 978 priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
b481de9c 979
9fbab516
BC
980 /*
981 * The same handler is used for both the REPLY to a discrete
982 * statistics request from the host as well as for the periodic
983 * statistics notifications (after received beacons) from the uCode.
b481de9c 984 */
bb8c093b
CH
985 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
986 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
b481de9c 987
261b9c33 988 iwl_setup_spectrum_handlers(priv);
cade0eb2 989 iwl_setup_rx_scan_handlers(priv);
bb8c093b 990 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
b481de9c 991
9fbab516 992 /* Set up hardware specific Rx handlers */
bb8c093b 993 iwl3945_hw_rx_handler_setup(priv);
b481de9c
ZY
994}
995
b481de9c
ZY
996/************************** RX-FUNCTIONS ****************************/
997/*
998 * Rx theory of operation
999 *
1000 * The host allocates 32 DMA target addresses and passes the host address
1001 * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
1002 * 0 to 31
1003 *
1004 * Rx Queue Indexes
1005 * The host/firmware share two index registers for managing the Rx buffers.
1006 *
1007 * The READ index maps to the first position that the firmware may be writing
1008 * to -- the driver can read up to (but not including) this position and get
1009 * good data.
1010 * The READ index is managed by the firmware once the card is enabled.
1011 *
1012 * The WRITE index maps to the last position the driver has read from -- the
1013 * position preceding WRITE is the last slot the firmware can place a packet.
1014 *
1015 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
1016 * WRITE = READ.
1017 *
9fbab516 1018 * During initialization, the host sets up the READ queue position to the first
b481de9c
ZY
1019 * INDEX position, and WRITE to the last (READ - 1 wrapped)
1020 *
9fbab516 1021 * When the firmware places a packet in a buffer, it will advance the READ index
b481de9c
ZY
1022 * and fire the RX interrupt. The driver can then query the READ index and
1023 * process as many packets as possible, moving the WRITE index forward as it
1024 * resets the Rx queue buffers with new memory.
1025 *
1026 * The management in the driver is as follows:
1027 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
1028 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
01ebd063 1029 * to replenish the iwl->rxq->rx_free.
bb8c093b 1030 * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
b481de9c
ZY
1031 * iwl->rxq is replenished and the READ INDEX is updated (updating the
1032 * 'processed' and 'read' driver indexes as well)
1033 * + A received packet is processed and handed to the kernel network stack,
1034 * detached from the iwl->rxq. The driver 'processed' index is updated.
1035 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
1036 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
1037 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
1038 * were enough free buffers and RX_STALLED is set it is cleared.
1039 *
1040 *
1041 * Driver sequence:
1042 *
9fbab516 1043 * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
bb8c093b 1044 * iwl3945_rx_queue_restock
9fbab516 1045 * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
b481de9c
ZY
1046 * queue, updates firmware pointers, and updates
1047 * the WRITE index. If insufficient rx_free buffers
bb8c093b 1048 * are available, schedules iwl3945_rx_replenish
b481de9c
ZY
1049 *
1050 * -- enable interrupts --
6100b588 1051 * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the
b481de9c
ZY
1052 * READ INDEX, detaching the SKB from the pool.
1053 * Moves the packet buffer from queue to rx_used.
bb8c093b 1054 * Calls iwl3945_rx_queue_restock to refill any empty
b481de9c
ZY
1055 * slots.
1056 * ...
1057 *
1058 */
1059
b481de9c 1060/**
9fbab516 1061 * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
b481de9c 1062 */
4a8a4322 1063static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv,
b481de9c
ZY
1064 dma_addr_t dma_addr)
1065{
1066 return cpu_to_le32((u32)dma_addr);
1067}
1068
1069/**
bb8c093b 1070 * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
b481de9c 1071 *
9fbab516 1072 * If there are slots in the RX queue that need to be restocked,
b481de9c 1073 * and we have free pre-allocated buffers, fill the ranks as much
9fbab516 1074 * as we can, pulling from rx_free.
b481de9c
ZY
1075 *
1076 * This moves the 'write' index forward to catch up with 'processed', and
1077 * also updates the memory address in the firmware to reference the new
1078 * target buffer.
1079 */
4a8a4322 1080static int iwl3945_rx_queue_restock(struct iwl_priv *priv)
b481de9c 1081{
cc2f362c 1082 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c 1083 struct list_head *element;
6100b588 1084 struct iwl_rx_mem_buffer *rxb;
b481de9c
ZY
1085 unsigned long flags;
1086 int write, rc;
1087
1088 spin_lock_irqsave(&rxq->lock, flags);
1089 write = rxq->write & ~0x7;
37d68317 1090 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
6440adb5 1091 /* Get next free Rx buffer, remove from free list */
b481de9c 1092 element = rxq->rx_free.next;
6100b588 1093 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
b481de9c 1094 list_del(element);
6440adb5
CB
1095
1096 /* Point to Rx buffer via next RBD in circular buffer */
6100b588 1097 rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->real_dma_addr);
b481de9c
ZY
1098 rxq->queue[rxq->write] = rxb;
1099 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
1100 rxq->free_count--;
1101 }
1102 spin_unlock_irqrestore(&rxq->lock, flags);
1103 /* If the pre-allocated buffer pool is dropping low, schedule to
1104 * refill it */
1105 if (rxq->free_count <= RX_LOW_WATERMARK)
1106 queue_work(priv->workqueue, &priv->rx_replenish);
1107
1108
6440adb5
CB
1109 /* If we've added more space for the firmware to place data, tell it.
1110 * Increment device's write pointer in multiples of 8. */
d14d4440 1111 if ((rxq->write_actual != (rxq->write & ~0x7))
b481de9c
ZY
1112 || (abs(rxq->write - rxq->read) > 7)) {
1113 spin_lock_irqsave(&rxq->lock, flags);
1114 rxq->need_update = 1;
1115 spin_unlock_irqrestore(&rxq->lock, flags);
141c43a3 1116 rc = iwl_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY
1117 if (rc)
1118 return rc;
1119 }
1120
1121 return 0;
1122}
1123
1124/**
bb8c093b 1125 * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
b481de9c
ZY
1126 *
1127 * When moving to rx_free an SKB is allocated for the slot.
1128 *
bb8c093b 1129 * Also restock the Rx queue via iwl3945_rx_queue_restock.
01ebd063 1130 * This is called as a scheduled work item (except for during initialization)
b481de9c 1131 */
d14d4440 1132static void iwl3945_rx_allocate(struct iwl_priv *priv, gfp_t priority)
b481de9c 1133{
cc2f362c 1134 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c 1135 struct list_head *element;
6100b588 1136 struct iwl_rx_mem_buffer *rxb;
0aae511c 1137 struct sk_buff *skb;
b481de9c 1138 unsigned long flags;
72240498
AK
1139
1140 while (1) {
1141 spin_lock_irqsave(&rxq->lock, flags);
1142
1143 if (list_empty(&rxq->rx_used)) {
1144 spin_unlock_irqrestore(&rxq->lock, flags);
1145 return;
1146 }
72240498 1147 spin_unlock_irqrestore(&rxq->lock, flags);
6440adb5
CB
1148
1149 /* Alloc a new receive buffer */
0aae511c
RC
1150 skb = alloc_skb(priv->hw_params.rx_buf_size, priority);
1151 if (!skb) {
b481de9c 1152 if (net_ratelimit())
978785a3 1153 IWL_CRIT(priv, ": Can not allocate SKB buffers\n");
b481de9c
ZY
1154 /* We don't reschedule replenish work here -- we will
1155 * call the restock method and if it still needs
1156 * more buffers it will schedule replenish */
1157 break;
1158 }
12342c47 1159
0aae511c
RC
1160 spin_lock_irqsave(&rxq->lock, flags);
1161 if (list_empty(&rxq->rx_used)) {
1162 spin_unlock_irqrestore(&rxq->lock, flags);
1163 dev_kfree_skb_any(skb);
1164 return;
1165 }
1166 element = rxq->rx_used.next;
1167 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
1168 list_del(element);
1169 spin_unlock_irqrestore(&rxq->lock, flags);
1170
1171 rxb->skb = skb;
1172
12342c47
ZY
1173 /* If radiotap head is required, reserve some headroom here.
1174 * The physical head count is a variable rx_stats->phy_count.
1175 * We reserve 4 bytes here. Plus these extra bytes, the
1176 * headroom of the physical head should be enough for the
1177 * radiotap head that iwl3945 supported. See iwl3945_rt.
1178 */
1179 skb_reserve(rxb->skb, 4);
1180
6440adb5 1181 /* Get physical address of RB/SKB */
1e33dc64
WT
1182 rxb->real_dma_addr = pci_map_single(priv->pci_dev,
1183 rxb->skb->data,
1184 priv->hw_params.rx_buf_size,
1185 PCI_DMA_FROMDEVICE);
72240498
AK
1186
1187 spin_lock_irqsave(&rxq->lock, flags);
b481de9c 1188 list_add_tail(&rxb->list, &rxq->rx_free);
72240498 1189 priv->alloc_rxb_skb++;
b481de9c 1190 rxq->free_count++;
72240498 1191 spin_unlock_irqrestore(&rxq->lock, flags);
b481de9c 1192 }
5c0eef96
MA
1193}
1194
df833b1d
RC
1195void iwl3945_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
1196{
1197 unsigned long flags;
1198 int i;
1199 spin_lock_irqsave(&rxq->lock, flags);
1200 INIT_LIST_HEAD(&rxq->rx_free);
1201 INIT_LIST_HEAD(&rxq->rx_used);
1202 /* Fill the rx_used queue with _all_ of the Rx buffers */
1203 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
1204 /* In the reset function, these buffers may have been allocated
1205 * to an SKB, so we need to unmap and free potential storage */
1206 if (rxq->pool[i].skb != NULL) {
1207 pci_unmap_single(priv->pci_dev,
1208 rxq->pool[i].real_dma_addr,
1209 priv->hw_params.rx_buf_size,
1210 PCI_DMA_FROMDEVICE);
1211 priv->alloc_rxb_skb--;
1212 dev_kfree_skb(rxq->pool[i].skb);
1213 rxq->pool[i].skb = NULL;
1214 }
1215 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
1216 }
1217
1218 /* Set us so that we have processed and used all buffers, but have
1219 * not restocked the Rx queue with fresh buffers */
1220 rxq->read = rxq->write = 0;
1221 rxq->free_count = 0;
d14d4440 1222 rxq->write_actual = 0;
df833b1d
RC
1223 spin_unlock_irqrestore(&rxq->lock, flags);
1224}
df833b1d 1225
5c0eef96
MA
1226void iwl3945_rx_replenish(void *data)
1227{
4a8a4322 1228 struct iwl_priv *priv = data;
5c0eef96
MA
1229 unsigned long flags;
1230
d14d4440 1231 iwl3945_rx_allocate(priv, GFP_KERNEL);
b481de9c
ZY
1232
1233 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 1234 iwl3945_rx_queue_restock(priv);
b481de9c
ZY
1235 spin_unlock_irqrestore(&priv->lock, flags);
1236}
1237
d14d4440
AK
1238static void iwl3945_rx_replenish_now(struct iwl_priv *priv)
1239{
1240 iwl3945_rx_allocate(priv, GFP_ATOMIC);
1241
1242 iwl3945_rx_queue_restock(priv);
1243}
1244
1245
df833b1d
RC
1246/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
1247 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
1248 * This free routine walks the list of POOL entries and if SKB is set to
1249 * non NULL it is unmapped and freed
1250 */
1251static void iwl3945_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
1252{
1253 int i;
1254 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
1255 if (rxq->pool[i].skb != NULL) {
1256 pci_unmap_single(priv->pci_dev,
1257 rxq->pool[i].real_dma_addr,
1258 priv->hw_params.rx_buf_size,
1259 PCI_DMA_FROMDEVICE);
1260 dev_kfree_skb(rxq->pool[i].skb);
1261 }
1262 }
1263
1264 pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
1265 rxq->dma_addr);
1266 pci_free_consistent(priv->pci_dev, sizeof(struct iwl_rb_status),
1267 rxq->rb_stts, rxq->rb_stts_dma);
1268 rxq->bd = NULL;
1269 rxq->rb_stts = NULL;
1270}
df833b1d
RC
1271
1272
b481de9c
ZY
1273/* Convert linear signal-to-noise ratio into dB */
1274static u8 ratio2dB[100] = {
1275/* 0 1 2 3 4 5 6 7 8 9 */
1276 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
1277 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
1278 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
1279 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
1280 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
1281 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
1282 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
1283 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
1284 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
1285 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
1286};
1287
1288/* Calculates a relative dB value from a ratio of linear
1289 * (i.e. not dB) signal levels.
1290 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
bb8c093b 1291int iwl3945_calc_db_from_ratio(int sig_ratio)
b481de9c 1292{
221c80cf
AB
1293 /* 1000:1 or higher just report as 60 dB */
1294 if (sig_ratio >= 1000)
b481de9c
ZY
1295 return 60;
1296
221c80cf 1297 /* 100:1 or higher, divide by 10 and use table,
b481de9c 1298 * add 20 dB to make up for divide by 10 */
221c80cf 1299 if (sig_ratio >= 100)
3ac7f146 1300 return 20 + (int)ratio2dB[sig_ratio/10];
b481de9c
ZY
1301
1302 /* We shouldn't see this */
1303 if (sig_ratio < 1)
1304 return 0;
1305
1306 /* Use table for ratios 1:1 - 99:1 */
1307 return (int)ratio2dB[sig_ratio];
1308}
1309
1310#define PERFECT_RSSI (-20) /* dBm */
1311#define WORST_RSSI (-95) /* dBm */
1312#define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
1313
1314/* Calculate an indication of rx signal quality (a percentage, not dBm!).
1315 * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
1316 * about formulas used below. */
bb8c093b 1317int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
b481de9c
ZY
1318{
1319 int sig_qual;
1320 int degradation = PERFECT_RSSI - rssi_dbm;
1321
1322 /* If we get a noise measurement, use signal-to-noise ratio (SNR)
1323 * as indicator; formula is (signal dbm - noise dbm).
1324 * SNR at or above 40 is a great signal (100%).
1325 * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
1326 * Weakest usable signal is usually 10 - 15 dB SNR. */
1327 if (noise_dbm) {
1328 if (rssi_dbm - noise_dbm >= 40)
1329 return 100;
1330 else if (rssi_dbm < noise_dbm)
1331 return 0;
1332 sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
1333
1334 /* Else use just the signal level.
1335 * This formula is a least squares fit of data points collected and
1336 * compared with a reference system that had a percentage (%) display
1337 * for signal quality. */
1338 } else
1339 sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
1340 (15 * RSSI_RANGE + 62 * degradation)) /
1341 (RSSI_RANGE * RSSI_RANGE);
1342
1343 if (sig_qual > 100)
1344 sig_qual = 100;
1345 else if (sig_qual < 1)
1346 sig_qual = 0;
1347
1348 return sig_qual;
1349}
1350
1351/**
9fbab516 1352 * iwl3945_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
1353 *
1354 * Uses the priv->rx_handlers callback function array to invoke
1355 * the appropriate handlers, including command responses,
1356 * frame-received notifications, and other notifications.
1357 */
4a8a4322 1358static void iwl3945_rx_handle(struct iwl_priv *priv)
b481de9c 1359{
6100b588 1360 struct iwl_rx_mem_buffer *rxb;
3d24a9f7 1361 struct iwl_rx_packet *pkt;
cc2f362c 1362 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
1363 u32 r, i;
1364 int reclaim;
1365 unsigned long flags;
5c0eef96 1366 u8 fill_rx = 0;
d68ab680 1367 u32 count = 8;
d14d4440 1368 int total_empty = 0;
b481de9c 1369
6440adb5
CB
1370 /* uCode's read index (stored in shared DRAM) indicates the last Rx
1371 * buffer that the driver may process (last buffer filled by ucode). */
8cd812bc 1372 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY
1373 i = rxq->read;
1374
d14d4440
AK
1375 /* calculate total frames need to be restock after handling RX */
1376 total_empty = r - priv->rxq.write_actual;
1377 if (total_empty < 0)
1378 total_empty += RX_QUEUE_SIZE;
1379
1380 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96 1381 fill_rx = 1;
b481de9c
ZY
1382 /* Rx interrupt, but nothing sent from uCode */
1383 if (i == r)
af472a95 1384 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c
ZY
1385
1386 while (i != r) {
1387 rxb = rxq->queue[i];
1388
9fbab516 1389 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
1390 * then a bug has been introduced in the queue refilling
1391 * routines -- catch it here */
1392 BUG_ON(rxb == NULL);
1393
1394 rxq->queue[i] = NULL;
1395
df833b1d
RC
1396 pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
1397 priv->hw_params.rx_buf_size,
1398 PCI_DMA_FROMDEVICE);
3d24a9f7 1399 pkt = (struct iwl_rx_packet *)rxb->skb->data;
b481de9c
ZY
1400
1401 /* Reclaim a command buffer only if this packet is a response
1402 * to a (driver-originated) command.
1403 * If the packet (e.g. Rx frame) originated from uCode,
1404 * there is no command buffer to reclaim.
1405 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1406 * but apparently a few don't get set; catch them here. */
1407 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
1408 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
1409 (pkt->hdr.cmd != REPLY_TX);
1410
1411 /* Based on type of command response or notification,
1412 * handle those that need handling via function in
bb8c093b 1413 * rx_handlers table. See iwl3945_setup_rx_handlers() */
b481de9c 1414 if (priv->rx_handlers[pkt->hdr.cmd]) {
af472a95 1415 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r, i,
b481de9c
ZY
1416 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
1417 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
86ddbf62 1418 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
b481de9c
ZY
1419 } else {
1420 /* No handling needed */
af472a95 1421 IWL_DEBUG_RX(priv, "r %d i %d No handler needed for %s, 0x%02x\n",
b481de9c
ZY
1422 r, i, get_cmd_string(pkt->hdr.cmd),
1423 pkt->hdr.cmd);
1424 }
1425
1426 if (reclaim) {
9fbab516 1427 /* Invoke any callbacks, transfer the skb to caller, and
518099a8 1428 * fire off the (possibly) blocking iwl_send_cmd()
b481de9c
ZY
1429 * as we reclaim the driver command queue */
1430 if (rxb && rxb->skb)
732587ab 1431 iwl_tx_cmd_complete(priv, rxb);
b481de9c 1432 else
39aadf8c 1433 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY
1434 }
1435
1436 /* For now we just don't re-use anything. We can tweak this
1437 * later to try and re-use notification packets and SKBs that
1438 * fail to Rx correctly */
1439 if (rxb->skb != NULL) {
1440 priv->alloc_rxb_skb--;
1441 dev_kfree_skb_any(rxb->skb);
1442 rxb->skb = NULL;
1443 }
1444
b481de9c
ZY
1445 spin_lock_irqsave(&rxq->lock, flags);
1446 list_add_tail(&rxb->list, &priv->rxq.rx_used);
1447 spin_unlock_irqrestore(&rxq->lock, flags);
1448 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
1449 /* If there are a lot of unused frames,
1450 * restock the Rx queue so ucode won't assert. */
1451 if (fill_rx) {
1452 count++;
1453 if (count >= 8) {
1454 priv->rxq.read = i;
d14d4440 1455 iwl3945_rx_replenish_now(priv);
5c0eef96
MA
1456 count = 0;
1457 }
1458 }
b481de9c
ZY
1459 }
1460
1461 /* Backtrack one entry */
1462 priv->rxq.read = i;
d14d4440
AK
1463 if (fill_rx)
1464 iwl3945_rx_replenish_now(priv);
1465 else
1466 iwl3945_rx_queue_restock(priv);
b481de9c
ZY
1467}
1468
0359facc 1469/* call this function to flush any scheduled tasklet */
4a8a4322 1470static inline void iwl_synchronize_irq(struct iwl_priv *priv)
0359facc 1471{
a96a27f9 1472 /* wait to make sure we flush pending tasklet*/
0359facc
MA
1473 synchronize_irq(priv->pci_dev->irq);
1474 tasklet_kill(&priv->irq_tasklet);
1475}
1476
b481de9c
ZY
1477static const char *desc_lookup(int i)
1478{
1479 switch (i) {
1480 case 1:
1481 return "FAIL";
1482 case 2:
1483 return "BAD_PARAM";
1484 case 3:
1485 return "BAD_CHECKSUM";
1486 case 4:
1487 return "NMI_INTERRUPT";
1488 case 5:
1489 return "SYSASSERT";
1490 case 6:
1491 return "FATAL_ERROR";
1492 }
1493
1494 return "UNKNOWN";
1495}
1496
1497#define ERROR_START_OFFSET (1 * sizeof(u32))
1498#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1499
4a8a4322 1500static void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
b481de9c
ZY
1501{
1502 u32 i;
1503 u32 desc, time, count, base, data1;
1504 u32 blink1, blink2, ilink1, ilink2;
b481de9c
ZY
1505
1506 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1507
bb8c093b 1508 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 1509 IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
b481de9c
ZY
1510 return;
1511 }
1512
b481de9c 1513
5d49f498 1514 count = iwl_read_targ_mem(priv, base);
b481de9c
ZY
1515
1516 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
15b1687c
WT
1517 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1518 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1519 priv->status, count);
b481de9c
ZY
1520 }
1521
15b1687c 1522 IWL_ERR(priv, "Desc Time asrtPC blink2 "
b481de9c
ZY
1523 "ilink1 nmiPC Line\n");
1524 for (i = ERROR_START_OFFSET;
1525 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
1526 i += ERROR_ELEM_SIZE) {
5d49f498 1527 desc = iwl_read_targ_mem(priv, base + i);
b481de9c 1528 time =
5d49f498 1529 iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32));
b481de9c 1530 blink1 =
5d49f498 1531 iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32));
b481de9c 1532 blink2 =
5d49f498 1533 iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32));
b481de9c 1534 ilink1 =
5d49f498 1535 iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32));
b481de9c 1536 ilink2 =
5d49f498 1537 iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32));
b481de9c 1538 data1 =
5d49f498 1539 iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32));
b481de9c 1540
15b1687c
WT
1541 IWL_ERR(priv,
1542 "%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
1543 desc_lookup(desc), desc, time, blink1, blink2,
1544 ilink1, ilink2, data1);
b481de9c
ZY
1545 }
1546
b481de9c
ZY
1547}
1548
f58177b9 1549#define EVENT_START_OFFSET (6 * sizeof(u32))
b481de9c
ZY
1550
1551/**
bb8c093b 1552 * iwl3945_print_event_log - Dump error event log to syslog
b481de9c 1553 *
b481de9c 1554 */
4a8a4322 1555static void iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
b481de9c
ZY
1556 u32 num_events, u32 mode)
1557{
1558 u32 i;
1559 u32 base; /* SRAM byte address of event log header */
1560 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1561 u32 ptr; /* SRAM byte address of log data */
1562 u32 ev, time, data; /* event log data */
1563
1564 if (num_events == 0)
1565 return;
1566
1567 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1568
1569 if (mode == 0)
1570 event_size = 2 * sizeof(u32);
1571 else
1572 event_size = 3 * sizeof(u32);
1573
1574 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1575
1576 /* "time" is actually "data" for mode 0 (no timestamp).
1577 * place event id # at far right for easier visual parsing. */
1578 for (i = 0; i < num_events; i++) {
5d49f498 1579 ev = iwl_read_targ_mem(priv, ptr);
b481de9c 1580 ptr += sizeof(u32);
5d49f498 1581 time = iwl_read_targ_mem(priv, ptr);
b481de9c 1582 ptr += sizeof(u32);
15b1687c
WT
1583 if (mode == 0) {
1584 /* data, ev */
1585 IWL_ERR(priv, "0x%08x\t%04u\n", time, ev);
1586 } else {
5d49f498 1587 data = iwl_read_targ_mem(priv, ptr);
b481de9c 1588 ptr += sizeof(u32);
15b1687c 1589 IWL_ERR(priv, "%010u\t0x%08x\t%04u\n", time, data, ev);
b481de9c
ZY
1590 }
1591 }
1592}
1593
4a8a4322 1594static void iwl3945_dump_nic_event_log(struct iwl_priv *priv)
b481de9c 1595{
b481de9c
ZY
1596 u32 base; /* SRAM byte address of event log header */
1597 u32 capacity; /* event log capacity in # entries */
1598 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1599 u32 num_wraps; /* # times uCode wrapped to top of log */
1600 u32 next_entry; /* index of next entry to be written by uCode */
1601 u32 size; /* # entries that we'll print */
1602
1603 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 1604 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 1605 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
b481de9c
ZY
1606 return;
1607 }
1608
b481de9c 1609 /* event log header */
5d49f498
AK
1610 capacity = iwl_read_targ_mem(priv, base);
1611 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1612 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1613 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
b481de9c
ZY
1614
1615 size = num_wraps ? capacity : next_entry;
1616
1617 /* bail out if nothing in log */
1618 if (size == 0) {
15b1687c 1619 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
b481de9c
ZY
1620 return;
1621 }
1622
15b1687c 1623 IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
b481de9c
ZY
1624 size, num_wraps);
1625
1626 /* if uCode has wrapped back to top of log, start at the oldest entry,
1627 * i.e the next one that uCode would fill. */
1628 if (num_wraps)
bb8c093b 1629 iwl3945_print_event_log(priv, next_entry,
b481de9c
ZY
1630 capacity - next_entry, mode);
1631
1632 /* (then/else) start at top of log */
bb8c093b 1633 iwl3945_print_event_log(priv, 0, next_entry, mode);
b481de9c 1634
b481de9c
ZY
1635}
1636
4a8a4322 1637static void iwl3945_irq_tasklet(struct iwl_priv *priv)
b481de9c
ZY
1638{
1639 u32 inta, handled = 0;
1640 u32 inta_fh;
1641 unsigned long flags;
d08853a3 1642#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
1643 u32 inta_mask;
1644#endif
1645
1646 spin_lock_irqsave(&priv->lock, flags);
1647
1648 /* Ack/clear/reset pending uCode interrupts.
1649 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1650 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
5d49f498
AK
1651 inta = iwl_read32(priv, CSR_INT);
1652 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY
1653
1654 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1655 * Any new interrupts that happen after this, either while we're
1656 * in this tasklet, or later, will show up in next ISR/tasklet. */
5d49f498
AK
1657 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1658 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 1659
d08853a3 1660#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1661 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
9fbab516 1662 /* just for debug */
5d49f498 1663 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 1664 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY
1665 inta, inta_mask, inta_fh);
1666 }
1667#endif
1668
1669 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1670 * atomic, make sure that inta covers all the interrupts that
1671 * we've discovered, even if FH interrupt came in just after
1672 * reading CSR_INT. */
6f83eaa1 1673 if (inta_fh & CSR39_FH_INT_RX_MASK)
b481de9c 1674 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 1675 if (inta_fh & CSR39_FH_INT_TX_MASK)
b481de9c
ZY
1676 inta |= CSR_INT_BIT_FH_TX;
1677
1678 /* Now service all interrupt bits discovered above. */
1679 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1680 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY
1681
1682 /* Tell the device to stop sending interrupts */
ed3b932e 1683 iwl_disable_interrupts(priv);
b481de9c 1684
86ddbf62 1685 priv->isr_stats.hw++;
8ccde88a 1686 iwl_irq_handle_error(priv);
b481de9c
ZY
1687
1688 handled |= CSR_INT_BIT_HW_ERR;
1689
1690 spin_unlock_irqrestore(&priv->lock, flags);
1691
1692 return;
1693 }
1694
d08853a3 1695#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1696 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
b481de9c 1697 /* NIC fires this, but we don't use it, redundant with WAKEUP */
86ddbf62 1698 if (inta & CSR_INT_BIT_SCD) {
e1623446 1699 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1700 "the frame/frames.\n");
86ddbf62
AK
1701 priv->isr_stats.sch++;
1702 }
b481de9c
ZY
1703
1704 /* Alive notification via Rx interrupt will do the real work */
86ddbf62 1705 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 1706 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
86ddbf62
AK
1707 priv->isr_stats.alive++;
1708 }
b481de9c
ZY
1709 }
1710#endif
1711 /* Safely ignore these bits for debug checks below */
25c03d8e 1712 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1713
b481de9c
ZY
1714 /* Error detected by uCode */
1715 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT
1716 IWL_ERR(priv, "Microcode SW error detected. "
1717 "Restarting 0x%X.\n", inta);
86ddbf62
AK
1718 priv->isr_stats.sw++;
1719 priv->isr_stats.sw_err = inta;
8ccde88a 1720 iwl_irq_handle_error(priv);
b481de9c
ZY
1721 handled |= CSR_INT_BIT_SW_ERR;
1722 }
1723
1724 /* uCode wakes up after power-down sleep */
1725 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1726 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
141c43a3 1727 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
4f3602c8
SO
1728 iwl_txq_update_write_ptr(priv, &priv->txq[0]);
1729 iwl_txq_update_write_ptr(priv, &priv->txq[1]);
1730 iwl_txq_update_write_ptr(priv, &priv->txq[2]);
1731 iwl_txq_update_write_ptr(priv, &priv->txq[3]);
1732 iwl_txq_update_write_ptr(priv, &priv->txq[4]);
1733 iwl_txq_update_write_ptr(priv, &priv->txq[5]);
b481de9c 1734
86ddbf62 1735 priv->isr_stats.wakeup++;
b481de9c
ZY
1736 handled |= CSR_INT_BIT_WAKEUP;
1737 }
1738
1739 /* All uCode command responses, including Tx command responses,
1740 * Rx "responses" (frame-received notification), and other
1741 * notifications from uCode come through here*/
1742 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
bb8c093b 1743 iwl3945_rx_handle(priv);
86ddbf62 1744 priv->isr_stats.rx++;
b481de9c
ZY
1745 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1746 }
1747
1748 if (inta & CSR_INT_BIT_FH_TX) {
e1623446 1749 IWL_DEBUG_ISR(priv, "Tx interrupt\n");
86ddbf62 1750 priv->isr_stats.tx++;
b481de9c 1751
5d49f498 1752 iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
a8b50a0a
MA
1753 iwl_write_direct32(priv, FH39_TCSR_CREDIT
1754 (FH39_SRVC_CHNL), 0x0);
b481de9c
ZY
1755 handled |= CSR_INT_BIT_FH_TX;
1756 }
1757
86ddbf62 1758 if (inta & ~handled) {
15b1687c 1759 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
86ddbf62
AK
1760 priv->isr_stats.unhandled++;
1761 }
b481de9c 1762
40cefda9 1763 if (inta & ~priv->inta_mask) {
39aadf8c 1764 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1765 inta & ~priv->inta_mask);
39aadf8c 1766 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY
1767 }
1768
1769 /* Re-enable all interrupts */
0359facc
MA
1770 /* only Re-enable if disabled by irq */
1771 if (test_bit(STATUS_INT_ENABLED, &priv->status))
ed3b932e 1772 iwl_enable_interrupts(priv);
b481de9c 1773
d08853a3 1774#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1775 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
5d49f498
AK
1776 inta = iwl_read32(priv, CSR_INT);
1777 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1778 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1779 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY
1780 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1781 }
1782#endif
1783 spin_unlock_irqrestore(&priv->lock, flags);
1784}
1785
4a8a4322 1786static int iwl3945_get_channels_for_scan(struct iwl_priv *priv,
8318d78a 1787 enum ieee80211_band band,
f9340520 1788 u8 is_active, u8 n_probes,
bb8c093b 1789 struct iwl3945_scan_channel *scan_ch)
b481de9c 1790{
4e05c234 1791 struct ieee80211_channel *chan;
8318d78a 1792 const struct ieee80211_supported_band *sband;
d20b3c65 1793 const struct iwl_channel_info *ch_info;
b481de9c
ZY
1794 u16 passive_dwell = 0;
1795 u16 active_dwell = 0;
1796 int added, i;
1797
cbba18c6 1798 sband = iwl_get_hw_mode(priv, band);
8318d78a 1799 if (!sband)
b481de9c
ZY
1800 return 0;
1801
77fecfb8
SO
1802 active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
1803 passive_dwell = iwl_get_passive_dwell_time(priv, band);
b481de9c 1804
8f4807a1
AK
1805 if (passive_dwell <= active_dwell)
1806 passive_dwell = active_dwell + 1;
1807
4e05c234
JB
1808 for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
1809 chan = priv->scan_request->channels[i];
1810
1811 if (chan->band != band)
182e2e66
JB
1812 continue;
1813
4e05c234 1814 scan_ch->channel = chan->hw_value;
b481de9c 1815
e6148917 1816 ch_info = iwl_get_channel_info(priv, band, scan_ch->channel);
b481de9c 1817 if (!is_channel_valid(ch_info)) {
e1623446 1818 IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
b481de9c
ZY
1819 scan_ch->channel);
1820 continue;
1821 }
1822
011a0330
AK
1823 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1824 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1825 /* If passive , set up for auto-switch
1826 * and use long active_dwell time.
1827 */
b481de9c 1828 if (!is_active || is_channel_passive(ch_info) ||
4e05c234 1829 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
b481de9c 1830 scan_ch->type = 0; /* passive */
011a0330
AK
1831 if (IWL_UCODE_API(priv->ucode_ver) == 1)
1832 scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
1833 } else {
b481de9c 1834 scan_ch->type = 1; /* active */
011a0330 1835 }
b481de9c 1836
011a0330
AK
1837 /* Set direct probe bits. These may be used both for active
1838 * scan channels (probes gets sent right away),
1839 * or for passive channels (probes get se sent only after
1840 * hearing clear Rx packet).*/
1841 if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
1842 if (n_probes)
0d21044e 1843 scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes);
011a0330
AK
1844 } else {
1845 /* uCode v1 does not allow setting direct probe bits on
1846 * passive channel. */
1847 if ((scan_ch->type & 1) && n_probes)
0d21044e 1848 scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes);
011a0330 1849 }
b481de9c 1850
9fbab516 1851 /* Set txpower levels to defaults */
b481de9c
ZY
1852 scan_ch->tpc.dsp_atten = 110;
1853 /* scan_pwr_info->tpc.dsp_atten; */
1854
1855 /*scan_pwr_info->tpc.tx_gain; */
8318d78a 1856 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY
1857 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
1858 else {
1859 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
1860 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
9fbab516 1861 * power level:
8a1b0245 1862 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
b481de9c
ZY
1863 */
1864 }
1865
e1623446 1866 IWL_DEBUG_SCAN(priv, "Scanning %d [%s %d]\n",
b481de9c
ZY
1867 scan_ch->channel,
1868 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
1869 (scan_ch->type & 1) ?
1870 active_dwell : passive_dwell);
1871
1872 scan_ch++;
1873 added++;
1874 }
1875
e1623446 1876 IWL_DEBUG_SCAN(priv, "total channels to scan %d \n", added);
b481de9c
ZY
1877 return added;
1878}
1879
4a8a4322 1880static void iwl3945_init_hw_rates(struct iwl_priv *priv,
b481de9c
ZY
1881 struct ieee80211_rate *rates)
1882{
1883 int i;
1884
1885 for (i = 0; i < IWL_RATE_COUNT; i++) {
8318d78a
JB
1886 rates[i].bitrate = iwl3945_rates[i].ieee * 5;
1887 rates[i].hw_value = i; /* Rate scaling will work on indexes */
1888 rates[i].hw_value_short = i;
1889 rates[i].flags = 0;
d9829a67 1890 if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
b481de9c 1891 /*
8318d78a 1892 * If CCK != 1M then set short preamble rate flag.
b481de9c 1893 */
bb8c093b 1894 rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
8318d78a 1895 0 : IEEE80211_RATE_SHORT_PREAMBLE;
b481de9c 1896 }
b481de9c
ZY
1897 }
1898}
1899
b481de9c
ZY
1900/******************************************************************************
1901 *
1902 * uCode download functions
1903 *
1904 ******************************************************************************/
1905
4a8a4322 1906static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1907{
98c92211
TW
1908 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1909 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1910 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1911 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1912 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1913 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY
1914}
1915
1916/**
bb8c093b 1917 * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
b481de9c
ZY
1918 * looking at all data.
1919 */
4a8a4322 1920static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len)
b481de9c
ZY
1921{
1922 u32 val;
1923 u32 save_len = len;
1924 int rc = 0;
1925 u32 errcnt;
1926
e1623446 1927 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b481de9c 1928
5d49f498 1929 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 1930 IWL39_RTC_INST_LOWER_BOUND);
b481de9c
ZY
1931
1932 errcnt = 0;
1933 for (; len > 0; len -= sizeof(u32), image++) {
1934 /* read data comes through single port, auto-incr addr */
1935 /* NOTE: Use the debugless read so we don't flood kernel log
1936 * if IWL_DL_IO is set */
5d49f498 1937 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c 1938 if (val != le32_to_cpu(*image)) {
15b1687c 1939 IWL_ERR(priv, "uCode INST section is invalid at "
b481de9c
ZY
1940 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1941 save_len - len, val, le32_to_cpu(*image));
1942 rc = -EIO;
1943 errcnt++;
1944 if (errcnt >= 20)
1945 break;
1946 }
1947 }
1948
b481de9c
ZY
1949
1950 if (!errcnt)
e1623446
TW
1951 IWL_DEBUG_INFO(priv,
1952 "ucode image in INSTRUCTION memory is good\n");
b481de9c
ZY
1953
1954 return rc;
1955}
1956
1957
1958/**
bb8c093b 1959 * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
b481de9c
ZY
1960 * using sample data 100 bytes apart. If these sample points are good,
1961 * it's a pretty good bet that everything between them is good, too.
1962 */
4a8a4322 1963static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
b481de9c
ZY
1964{
1965 u32 val;
1966 int rc = 0;
1967 u32 errcnt = 0;
1968 u32 i;
1969
e1623446 1970 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b481de9c 1971
b481de9c
ZY
1972 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
1973 /* read data comes through single port, auto-incr addr */
1974 /* NOTE: Use the debugless read so we don't flood kernel log
1975 * if IWL_DL_IO is set */
5d49f498 1976 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 1977 i + IWL39_RTC_INST_LOWER_BOUND);
5d49f498 1978 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY
1979 if (val != le32_to_cpu(*image)) {
1980#if 0 /* Enable this if you want to see details */
15b1687c 1981 IWL_ERR(priv, "uCode INST section is invalid at "
b481de9c
ZY
1982 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1983 i, val, *image);
1984#endif
1985 rc = -EIO;
1986 errcnt++;
1987 if (errcnt >= 3)
1988 break;
1989 }
1990 }
1991
b481de9c
ZY
1992 return rc;
1993}
1994
1995
1996/**
bb8c093b 1997 * iwl3945_verify_ucode - determine which instruction image is in SRAM,
b481de9c
ZY
1998 * and verify its contents
1999 */
4a8a4322 2000static int iwl3945_verify_ucode(struct iwl_priv *priv)
b481de9c
ZY
2001{
2002 __le32 *image;
2003 u32 len;
2004 int rc = 0;
2005
2006 /* Try bootstrap */
2007 image = (__le32 *)priv->ucode_boot.v_addr;
2008 len = priv->ucode_boot.len;
bb8c093b 2009 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c 2010 if (rc == 0) {
e1623446 2011 IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
b481de9c
ZY
2012 return 0;
2013 }
2014
2015 /* Try initialize */
2016 image = (__le32 *)priv->ucode_init.v_addr;
2017 len = priv->ucode_init.len;
bb8c093b 2018 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c 2019 if (rc == 0) {
e1623446 2020 IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
b481de9c
ZY
2021 return 0;
2022 }
2023
2024 /* Try runtime/protocol */
2025 image = (__le32 *)priv->ucode_code.v_addr;
2026 len = priv->ucode_code.len;
bb8c093b 2027 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c 2028 if (rc == 0) {
e1623446 2029 IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
b481de9c
ZY
2030 return 0;
2031 }
2032
15b1687c 2033 IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
b481de9c 2034
9fbab516
BC
2035 /* Since nothing seems to match, show first several data entries in
2036 * instruction SRAM, so maybe visual inspection will give a clue.
2037 * Selection of bootstrap image (vs. other images) is arbitrary. */
b481de9c
ZY
2038 image = (__le32 *)priv->ucode_boot.v_addr;
2039 len = priv->ucode_boot.len;
bb8c093b 2040 rc = iwl3945_verify_inst_full(priv, image, len);
b481de9c
ZY
2041
2042 return rc;
2043}
2044
4a8a4322 2045static void iwl3945_nic_start(struct iwl_priv *priv)
b481de9c
ZY
2046{
2047 /* Remove all resets to allow NIC to operate */
5d49f498 2048 iwl_write32(priv, CSR_RESET, 0);
b481de9c
ZY
2049}
2050
2051/**
bb8c093b 2052 * iwl3945_read_ucode - Read uCode images from disk file.
b481de9c
ZY
2053 *
2054 * Copy into buffers for card to fetch via bus-mastering
2055 */
4a8a4322 2056static int iwl3945_read_ucode(struct iwl_priv *priv)
b481de9c 2057{
cc0f555d 2058 const struct iwl_ucode_header *ucode;
a0987a8d 2059 int ret = -EINVAL, index;
b481de9c
ZY
2060 const struct firmware *ucode_raw;
2061 /* firmware file name contains uCode/driver compatibility version */
a0987a8d
RC
2062 const char *name_pre = priv->cfg->fw_name_pre;
2063 const unsigned int api_max = priv->cfg->ucode_api_max;
2064 const unsigned int api_min = priv->cfg->ucode_api_min;
2065 char buf[25];
b481de9c
ZY
2066 u8 *src;
2067 size_t len;
a0987a8d 2068 u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
b481de9c
ZY
2069
2070 /* Ask kernel firmware_class module to get the boot firmware off disk.
2071 * request_firmware() is synchronous, file is in memory on return. */
a0987a8d
RC
2072 for (index = api_max; index >= api_min; index--) {
2073 sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
2074 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
2075 if (ret < 0) {
15b1687c 2076 IWL_ERR(priv, "%s firmware file req failed: %d\n",
a0987a8d
RC
2077 buf, ret);
2078 if (ret == -ENOENT)
2079 continue;
2080 else
2081 goto error;
2082 } else {
2083 if (index < api_max)
15b1687c
WT
2084 IWL_ERR(priv, "Loaded firmware %s, "
2085 "which is deprecated. "
2086 " Please use API v%u instead.\n",
a0987a8d 2087 buf, api_max);
e1623446
TW
2088 IWL_DEBUG_INFO(priv, "Got firmware '%s' file "
2089 "(%zd bytes) from disk\n",
a0987a8d
RC
2090 buf, ucode_raw->size);
2091 break;
2092 }
b481de9c
ZY
2093 }
2094
a0987a8d
RC
2095 if (ret < 0)
2096 goto error;
b481de9c
ZY
2097
2098 /* Make sure that we got at least our header! */
cc0f555d 2099 if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
15b1687c 2100 IWL_ERR(priv, "File size way too small!\n");
90e759d1 2101 ret = -EINVAL;
b481de9c
ZY
2102 goto err_release;
2103 }
2104
2105 /* Data from ucode file: header followed by uCode images */
cc0f555d 2106 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 2107
c02b3acd 2108 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 2109 api_ver = IWL_UCODE_API(priv->ucode_ver);
cc0f555d
JS
2110 inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
2111 data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
2112 init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
2113 init_data_size =
2114 priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
2115 boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
2116 src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
b481de9c 2117
a0987a8d
RC
2118 /* api_ver should match the api version forming part of the
2119 * firmware filename ... but we don't check for that and only rely
877d0310 2120 * on the API version read from firmware header from here on forward */
a0987a8d
RC
2121
2122 if (api_ver < api_min || api_ver > api_max) {
15b1687c 2123 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC
2124 "Driver supports v%u, firmware is v%u.\n",
2125 api_max, api_ver);
2126 priv->ucode_ver = 0;
2127 ret = -EINVAL;
2128 goto err_release;
2129 }
2130 if (api_ver != api_max)
15b1687c 2131 IWL_ERR(priv, "Firmware has old API version. Expected %u, "
a0987a8d
RC
2132 "got %u. New firmware can be obtained "
2133 "from http://www.intellinuxwireless.org.\n",
2134 api_max, api_ver);
2135
978785a3
TW
2136 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
2137 IWL_UCODE_MAJOR(priv->ucode_ver),
2138 IWL_UCODE_MINOR(priv->ucode_ver),
2139 IWL_UCODE_API(priv->ucode_ver),
2140 IWL_UCODE_SERIAL(priv->ucode_ver));
2141
e1623446 2142 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
a0987a8d 2143 priv->ucode_ver);
e1623446
TW
2144 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
2145 inst_size);
2146 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
2147 data_size);
2148 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
2149 init_size);
2150 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
2151 init_data_size);
2152 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
2153 boot_size);
b481de9c 2154
a0987a8d 2155
b481de9c 2156 /* Verify size of file vs. image size info in file's header */
cc0f555d 2157 if (ucode_raw->size != priv->cfg->ops->ucode->get_header_size(api_ver) +
b481de9c
ZY
2158 inst_size + data_size + init_size +
2159 init_data_size + boot_size) {
2160
cc0f555d
JS
2161 IWL_DEBUG_INFO(priv,
2162 "uCode file size %zd does not match expected size\n",
2163 ucode_raw->size);
90e759d1 2164 ret = -EINVAL;
b481de9c
ZY
2165 goto err_release;
2166 }
2167
2168 /* Verify that uCode images will fit in card's SRAM */
250bdd21 2169 if (inst_size > IWL39_MAX_INST_SIZE) {
e1623446 2170 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
90e759d1
TW
2171 inst_size);
2172 ret = -EINVAL;
b481de9c
ZY
2173 goto err_release;
2174 }
2175
250bdd21 2176 if (data_size > IWL39_MAX_DATA_SIZE) {
e1623446 2177 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
90e759d1
TW
2178 data_size);
2179 ret = -EINVAL;
b481de9c
ZY
2180 goto err_release;
2181 }
250bdd21 2182 if (init_size > IWL39_MAX_INST_SIZE) {
e1623446
TW
2183 IWL_DEBUG_INFO(priv,
2184 "uCode init instr len %d too large to fit in\n",
90e759d1
TW
2185 init_size);
2186 ret = -EINVAL;
b481de9c
ZY
2187 goto err_release;
2188 }
250bdd21 2189 if (init_data_size > IWL39_MAX_DATA_SIZE) {
e1623446
TW
2190 IWL_DEBUG_INFO(priv,
2191 "uCode init data len %d too large to fit in\n",
90e759d1
TW
2192 init_data_size);
2193 ret = -EINVAL;
b481de9c
ZY
2194 goto err_release;
2195 }
250bdd21 2196 if (boot_size > IWL39_MAX_BSM_SIZE) {
e1623446
TW
2197 IWL_DEBUG_INFO(priv,
2198 "uCode boot instr len %d too large to fit in\n",
90e759d1
TW
2199 boot_size);
2200 ret = -EINVAL;
b481de9c
ZY
2201 goto err_release;
2202 }
2203
2204 /* Allocate ucode buffers for card's bus-master loading ... */
2205
2206 /* Runtime instructions and 2 copies of data:
2207 * 1) unmodified from disk
2208 * 2) backup cache for save/restore during power-downs */
2209 priv->ucode_code.len = inst_size;
98c92211 2210 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY
2211
2212 priv->ucode_data.len = data_size;
98c92211 2213 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY
2214
2215 priv->ucode_data_backup.len = data_size;
98c92211 2216 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 2217
90e759d1
TW
2218 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2219 !priv->ucode_data_backup.v_addr)
2220 goto err_pci_alloc;
b481de9c
ZY
2221
2222 /* Initialization instructions and data */
90e759d1
TW
2223 if (init_size && init_data_size) {
2224 priv->ucode_init.len = init_size;
98c92211 2225 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW
2226
2227 priv->ucode_init_data.len = init_data_size;
98c92211 2228 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW
2229
2230 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2231 goto err_pci_alloc;
2232 }
b481de9c
ZY
2233
2234 /* Bootstrap (instructions only, no data) */
90e759d1
TW
2235 if (boot_size) {
2236 priv->ucode_boot.len = boot_size;
98c92211 2237 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 2238
90e759d1
TW
2239 if (!priv->ucode_boot.v_addr)
2240 goto err_pci_alloc;
2241 }
b481de9c
ZY
2242
2243 /* Copy images into buffers for card's bus-master reads ... */
2244
2245 /* Runtime instructions (first block of data in file) */
cc0f555d 2246 len = inst_size;
e1623446
TW
2247 IWL_DEBUG_INFO(priv,
2248 "Copying (but not loading) uCode instr len %zd\n", len);
b481de9c 2249 memcpy(priv->ucode_code.v_addr, src, len);
cc0f555d
JS
2250 src += len;
2251
e1623446 2252 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY
2253 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2254
2255 /* Runtime data (2nd block)
bb8c093b 2256 * NOTE: Copy into backup buffer will be done in iwl3945_up() */
cc0f555d 2257 len = data_size;
e1623446
TW
2258 IWL_DEBUG_INFO(priv,
2259 "Copying (but not loading) uCode data len %zd\n", len);
b481de9c
ZY
2260 memcpy(priv->ucode_data.v_addr, src, len);
2261 memcpy(priv->ucode_data_backup.v_addr, src, len);
cc0f555d 2262 src += len;
b481de9c
ZY
2263
2264 /* Initialization instructions (3rd block) */
2265 if (init_size) {
cc0f555d 2266 len = init_size;
e1623446
TW
2267 IWL_DEBUG_INFO(priv,
2268 "Copying (but not loading) init instr len %zd\n", len);
b481de9c 2269 memcpy(priv->ucode_init.v_addr, src, len);
cc0f555d 2270 src += len;
b481de9c
ZY
2271 }
2272
2273 /* Initialization data (4th block) */
2274 if (init_data_size) {
cc0f555d 2275 len = init_data_size;
e1623446
TW
2276 IWL_DEBUG_INFO(priv,
2277 "Copying (but not loading) init data len %zd\n", len);
b481de9c 2278 memcpy(priv->ucode_init_data.v_addr, src, len);
cc0f555d 2279 src += len;
b481de9c
ZY
2280 }
2281
2282 /* Bootstrap instructions (5th block) */
cc0f555d 2283 len = boot_size;
e1623446
TW
2284 IWL_DEBUG_INFO(priv,
2285 "Copying (but not loading) boot instr len %zd\n", len);
b481de9c
ZY
2286 memcpy(priv->ucode_boot.v_addr, src, len);
2287
2288 /* We have our copies now, allow OS release its copies */
2289 release_firmware(ucode_raw);
2290 return 0;
2291
2292 err_pci_alloc:
15b1687c 2293 IWL_ERR(priv, "failed to allocate pci memory\n");
90e759d1 2294 ret = -ENOMEM;
bb8c093b 2295 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY
2296
2297 err_release:
2298 release_firmware(ucode_raw);
2299
2300 error:
90e759d1 2301 return ret;
b481de9c
ZY
2302}
2303
2304
2305/**
bb8c093b 2306 * iwl3945_set_ucode_ptrs - Set uCode address location
b481de9c
ZY
2307 *
2308 * Tell initialization uCode where to find runtime uCode.
2309 *
2310 * BSM registers initially contain pointers to initialization uCode.
2311 * We need to replace them to load runtime uCode inst and data,
2312 * and to save runtime data when powering down.
2313 */
4a8a4322 2314static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv)
b481de9c
ZY
2315{
2316 dma_addr_t pinst;
2317 dma_addr_t pdata;
b481de9c
ZY
2318
2319 /* bits 31:0 for 3945 */
2320 pinst = priv->ucode_code.p_addr;
2321 pdata = priv->ucode_data_backup.p_addr;
2322
b481de9c 2323 /* Tell bootstrap uCode where to find image to load */
5d49f498
AK
2324 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2325 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2326 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
b481de9c
ZY
2327 priv->ucode_data.len);
2328
a96a27f9 2329 /* Inst byte count must be last to set up, bit 31 signals uCode
b481de9c 2330 * that all new ptr/size info is in place */
5d49f498 2331 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
b481de9c
ZY
2332 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
2333
e1623446 2334 IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n");
b481de9c 2335
a8b50a0a 2336 return 0;
b481de9c
ZY
2337}
2338
2339/**
bb8c093b 2340 * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
b481de9c
ZY
2341 *
2342 * Called after REPLY_ALIVE notification received from "initialize" uCode.
2343 *
b481de9c 2344 * Tell "initialize" uCode to go ahead and load the runtime uCode.
9fbab516 2345 */
4a8a4322 2346static void iwl3945_init_alive_start(struct iwl_priv *priv)
b481de9c
ZY
2347{
2348 /* Check alive response for "valid" sign from uCode */
2349 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
2350 /* We had an error bringing up the hardware, so take it
2351 * all the way back down so we can try again */
e1623446 2352 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
b481de9c
ZY
2353 goto restart;
2354 }
2355
2356 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
2357 * This is a paranoid check, because we would not have gotten the
2358 * "initialize" alive if code weren't properly loaded. */
bb8c093b 2359 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY
2360 /* Runtime instruction load was bad;
2361 * take it all the way back down so we can try again */
e1623446 2362 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
b481de9c
ZY
2363 goto restart;
2364 }
2365
2366 /* Send pointers to protocol/runtime uCode image ... init code will
2367 * load and launch runtime uCode, which will send us another "Alive"
2368 * notification. */
e1623446 2369 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
bb8c093b 2370 if (iwl3945_set_ucode_ptrs(priv)) {
b481de9c
ZY
2371 /* Runtime instruction load won't happen;
2372 * take it all the way back down so we can try again */
e1623446 2373 IWL_DEBUG_INFO(priv, "Couldn't set up uCode pointers.\n");
b481de9c
ZY
2374 goto restart;
2375 }
2376 return;
2377
2378 restart:
2379 queue_work(priv->workqueue, &priv->restart);
2380}
2381
b481de9c 2382/**
bb8c093b 2383 * iwl3945_alive_start - called after REPLY_ALIVE notification received
b481de9c 2384 * from protocol/runtime uCode (initialization uCode's
bb8c093b 2385 * Alive gets handled by iwl3945_init_alive_start()).
b481de9c 2386 */
4a8a4322 2387static void iwl3945_alive_start(struct iwl_priv *priv)
b481de9c 2388{
b481de9c
ZY
2389 int thermal_spin = 0;
2390 u32 rfkill;
2391
e1623446 2392 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY
2393
2394 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2395 /* We had an error bringing up the hardware, so take it
2396 * all the way back down so we can try again */
e1623446 2397 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY
2398 goto restart;
2399 }
2400
2401 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2402 * This is a paranoid check, because we would not have gotten the
2403 * "runtime" alive if code weren't properly loaded. */
bb8c093b 2404 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY
2405 /* Runtime instruction load was bad;
2406 * take it all the way back down so we can try again */
e1623446 2407 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY
2408 goto restart;
2409 }
2410
c587de0b 2411 iwl_clear_stations_table(priv);
b481de9c 2412
5d49f498 2413 rfkill = iwl_read_prph(priv, APMG_RFKILL_REG);
e1623446 2414 IWL_DEBUG_INFO(priv, "RFKILL status: 0x%x\n", rfkill);
b481de9c
ZY
2415
2416 if (rfkill & 0x1) {
2417 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a96a27f9 2418 /* if RFKILL is not on, then wait for thermal
b481de9c 2419 * sensor in adapter to kick in */
bb8c093b 2420 while (iwl3945_hw_get_temperature(priv) == 0) {
b481de9c
ZY
2421 thermal_spin++;
2422 udelay(10);
2423 }
2424
2425 if (thermal_spin)
e1623446 2426 IWL_DEBUG_INFO(priv, "Thermal calibration took %dus\n",
b481de9c
ZY
2427 thermal_spin * 10);
2428 } else
2429 set_bit(STATUS_RF_KILL_HW, &priv->status);
2430
9fbab516 2431 /* After the ALIVE response, we can send commands to 3945 uCode */
b481de9c
ZY
2432 set_bit(STATUS_ALIVE, &priv->status);
2433
775a6e27 2434 if (iwl_is_rfkill(priv))
b481de9c
ZY
2435 return;
2436
36d6825b 2437 ieee80211_wake_queues(priv->hw);
b481de9c
ZY
2438
2439 priv->active_rate = priv->rates_mask;
2440 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
2441
d25aabb0 2442 iwl_power_update_mode(priv, false);
b481de9c 2443
8ccde88a 2444 if (iwl_is_associated(priv)) {
bb8c093b 2445 struct iwl3945_rxon_cmd *active_rxon =
8ccde88a 2446 (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
b481de9c 2447
8a9b9926 2448 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY
2449 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2450 } else {
2451 /* Initialize our rx_config data */
8ccde88a 2452 iwl_connection_init_rx_config(priv, priv->iw_mode);
b481de9c
ZY
2453 }
2454
9fbab516 2455 /* Configure Bluetooth device coexistence support */
17f841cd 2456 iwl_send_bt_config(priv);
b481de9c
ZY
2457
2458 /* Configure the adapter for unassociated operation */
e0158e61 2459 iwlcore_commit_rxon(priv);
b481de9c 2460
b481de9c
ZY
2461 iwl3945_reg_txpower_periodic(priv);
2462
fe00b5a5
RC
2463 iwl3945_led_register(priv);
2464
e1623446 2465 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 2466 set_bit(STATUS_READY, &priv->status);
5a66926a 2467 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 2468
9bdf5eca
MA
2469 /* reassociate for ADHOC mode */
2470 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
2471 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
2472 priv->vif);
2473 if (beacon)
9944b938 2474 iwl_mac_beacon_update(priv->hw, beacon);
9bdf5eca
MA
2475 }
2476
f45c2714 2477 if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
727882d6 2478 iwl_set_mode(priv, priv->iw_mode);
f45c2714 2479
b481de9c
ZY
2480 return;
2481
2482 restart:
2483 queue_work(priv->workqueue, &priv->restart);
2484}
2485
4a8a4322 2486static void iwl3945_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 2487
4a8a4322 2488static void __iwl3945_down(struct iwl_priv *priv)
b481de9c
ZY
2489{
2490 unsigned long flags;
2491 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2492 struct ieee80211_conf *conf = NULL;
2493
e1623446 2494 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c
ZY
2495
2496 conf = ieee80211_get_hw_conf(priv->hw);
2497
2498 if (!exit_pending)
2499 set_bit(STATUS_EXIT_PENDING, &priv->status);
2500
ab53d8af 2501 iwl3945_led_unregister(priv);
c587de0b 2502 iwl_clear_stations_table(priv);
b481de9c
ZY
2503
2504 /* Unblock any waiting calls */
2505 wake_up_interruptible_all(&priv->wait_command_queue);
2506
b481de9c
ZY
2507 /* Wipe out the EXIT_PENDING status bit if we are not actually
2508 * exiting the module */
2509 if (!exit_pending)
2510 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2511
2512 /* stop and reset the on-board processor */
5d49f498 2513 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY
2514
2515 /* tell the device to stop sending interrupts */
0359facc 2516 spin_lock_irqsave(&priv->lock, flags);
ed3b932e 2517 iwl_disable_interrupts(priv);
0359facc
MA
2518 spin_unlock_irqrestore(&priv->lock, flags);
2519 iwl_synchronize_irq(priv);
b481de9c
ZY
2520
2521 if (priv->mac80211_registered)
2522 ieee80211_stop_queues(priv->hw);
2523
bb8c093b 2524 /* If we have not previously called iwl3945_init() then
6da3a13e 2525 * clear all bits but the RF Kill bits and return */
775a6e27 2526 if (!iwl_is_init(priv)) {
b481de9c
ZY
2527 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2528 STATUS_RF_KILL_HW |
9788864e
RC
2529 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2530 STATUS_GEO_CONFIGURED |
ebef2008
AK
2531 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2532 STATUS_EXIT_PENDING;
b481de9c
ZY
2533 goto exit;
2534 }
2535
6da3a13e 2536 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 2537 * bit and continue taking the NIC down. */
b481de9c
ZY
2538 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2539 STATUS_RF_KILL_HW |
9788864e
RC
2540 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2541 STATUS_GEO_CONFIGURED |
b481de9c 2542 test_bit(STATUS_FW_ERROR, &priv->status) <<
ebef2008
AK
2543 STATUS_FW_ERROR |
2544 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2545 STATUS_EXIT_PENDING;
b481de9c 2546
e9414b6b 2547 priv->cfg->ops->lib->apm_ops.reset(priv);
b481de9c 2548 spin_lock_irqsave(&priv->lock, flags);
5d49f498 2549 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY
2550 spin_unlock_irqrestore(&priv->lock, flags);
2551
bb8c093b
CH
2552 iwl3945_hw_txq_ctx_stop(priv);
2553 iwl3945_hw_rxq_stop(priv);
b481de9c 2554
a8b50a0a
MA
2555 iwl_write_prph(priv, APMG_CLK_DIS_REG,
2556 APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY
2557
2558 udelay(5);
2559
6da3a13e 2560 if (exit_pending)
e9414b6b
AM
2561 priv->cfg->ops->lib->apm_ops.stop(priv);
2562 else
2563 priv->cfg->ops->lib->apm_ops.reset(priv);
2564
b481de9c 2565 exit:
3d24a9f7 2566 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY
2567
2568 if (priv->ibss_beacon)
2569 dev_kfree_skb(priv->ibss_beacon);
2570 priv->ibss_beacon = NULL;
2571
2572 /* clear out any free frames */
bb8c093b 2573 iwl3945_clear_free_frames(priv);
b481de9c
ZY
2574}
2575
4a8a4322 2576static void iwl3945_down(struct iwl_priv *priv)
b481de9c
ZY
2577{
2578 mutex_lock(&priv->mutex);
bb8c093b 2579 __iwl3945_down(priv);
b481de9c 2580 mutex_unlock(&priv->mutex);
b24d22b1 2581
bb8c093b 2582 iwl3945_cancel_deferred_work(priv);
b481de9c
ZY
2583}
2584
2585#define MAX_HW_RESTARTS 5
2586
4a8a4322 2587static int __iwl3945_up(struct iwl_priv *priv)
b481de9c
ZY
2588{
2589 int rc, i;
2590
2591 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 2592 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY
2593 return -EIO;
2594 }
2595
e903fbd4 2596 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 2597 IWL_ERR(priv, "ucode not available for device bring up\n");
e903fbd4
RC
2598 return -EIO;
2599 }
2600
e655b9f0 2601 /* If platform's RF_KILL switch is NOT set to KILL */
5d49f498 2602 if (iwl_read32(priv, CSR_GP_CNTRL) &
e655b9f0
ZY
2603 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2604 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2605 else {
2606 set_bit(STATUS_RF_KILL_HW, &priv->status);
6da3a13e
WYG
2607 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2608 return -ENODEV;
b481de9c 2609 }
80fcc9e2 2610
5d49f498 2611 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 2612
bb8c093b 2613 rc = iwl3945_hw_nic_init(priv);
b481de9c 2614 if (rc) {
15b1687c 2615 IWL_ERR(priv, "Unable to int nic\n");
b481de9c
ZY
2616 return rc;
2617 }
2618
2619 /* make sure rfkill handshake bits are cleared */
5d49f498
AK
2620 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2621 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY
2622 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2623
2624 /* clear (again), then enable host interrupts */
5d49f498 2625 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
ed3b932e 2626 iwl_enable_interrupts(priv);
b481de9c
ZY
2627
2628 /* really make sure rfkill handshake bits are cleared */
5d49f498
AK
2629 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2630 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
2631
2632 /* Copy original ucode data image from disk into backup cache.
2633 * This will be used to initialize the on-board processor's
2634 * data SRAM for a clean start when the runtime program first loads. */
2635 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 2636 priv->ucode_data.len);
b481de9c 2637
e655b9f0
ZY
2638 /* We return success when we resume from suspend and rf_kill is on. */
2639 if (test_bit(STATUS_RF_KILL_HW, &priv->status))
2640 return 0;
2641
b481de9c
ZY
2642 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2643
c587de0b 2644 iwl_clear_stations_table(priv);
b481de9c
ZY
2645
2646 /* load bootstrap state machine,
2647 * load bootstrap program into processor's memory,
2648 * prepare to load the "initialize" uCode */
0164b9b4 2649 priv->cfg->ops->lib->load_ucode(priv);
b481de9c
ZY
2650
2651 if (rc) {
15b1687c
WT
2652 IWL_ERR(priv,
2653 "Unable to set up bootstrap uCode: %d\n", rc);
b481de9c
ZY
2654 continue;
2655 }
2656
2657 /* start card; "initialize" will load runtime ucode */
bb8c093b 2658 iwl3945_nic_start(priv);
b481de9c 2659
e1623446 2660 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY
2661
2662 return 0;
2663 }
2664
2665 set_bit(STATUS_EXIT_PENDING, &priv->status);
bb8c093b 2666 __iwl3945_down(priv);
ebef2008 2667 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY
2668
2669 /* tried to restart and config the device for as long as our
2670 * patience could withstand */
15b1687c 2671 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY
2672 return -EIO;
2673}
2674
2675
2676/*****************************************************************************
2677 *
2678 * Workqueue callbacks
2679 *
2680 *****************************************************************************/
2681
bb8c093b 2682static void iwl3945_bg_init_alive_start(struct work_struct *data)
b481de9c 2683{
4a8a4322
AK
2684 struct iwl_priv *priv =
2685 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY
2686
2687 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2688 return;
2689
2690 mutex_lock(&priv->mutex);
bb8c093b 2691 iwl3945_init_alive_start(priv);
b481de9c
ZY
2692 mutex_unlock(&priv->mutex);
2693}
2694
bb8c093b 2695static void iwl3945_bg_alive_start(struct work_struct *data)
b481de9c 2696{
4a8a4322
AK
2697 struct iwl_priv *priv =
2698 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY
2699
2700 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2701 return;
2702
2703 mutex_lock(&priv->mutex);
bb8c093b 2704 iwl3945_alive_start(priv);
b481de9c
ZY
2705 mutex_unlock(&priv->mutex);
2706}
2707
2663516d
HS
2708static void iwl3945_rfkill_poll(struct work_struct *data)
2709{
2710 struct iwl_priv *priv =
2711 container_of(data, struct iwl_priv, rfkill_poll.work);
2663516d
HS
2712
2713 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2714 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2715 else
2716 set_bit(STATUS_RF_KILL_HW, &priv->status);
2717
a60e77e5
JB
2718 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
2719 test_bit(STATUS_RF_KILL_HW, &priv->status));
2663516d
HS
2720
2721 queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
2722 round_jiffies_relative(2 * HZ));
2723
2724}
2725
b481de9c 2726#define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
bb8c093b 2727static void iwl3945_bg_request_scan(struct work_struct *data)
b481de9c 2728{
4a8a4322
AK
2729 struct iwl_priv *priv =
2730 container_of(data, struct iwl_priv, request_scan);
c2d79b48 2731 struct iwl_host_cmd cmd = {
b481de9c 2732 .id = REPLY_SCAN_CMD,
bb8c093b 2733 .len = sizeof(struct iwl3945_scan_cmd),
c2acea8e 2734 .flags = CMD_SIZE_HUGE,
b481de9c
ZY
2735 };
2736 int rc = 0;
bb8c093b 2737 struct iwl3945_scan_cmd *scan;
b481de9c 2738 struct ieee80211_conf *conf = NULL;
1ecf9fc1 2739 u8 n_probes = 0;
8318d78a 2740 enum ieee80211_band band;
1ecf9fc1 2741 bool is_active = false;
b481de9c
ZY
2742
2743 conf = ieee80211_get_hw_conf(priv->hw);
2744
2745 mutex_lock(&priv->mutex);
2746
fbc9f97b
RC
2747 cancel_delayed_work(&priv->scan_check);
2748
775a6e27 2749 if (!iwl_is_ready(priv)) {
39aadf8c 2750 IWL_WARN(priv, "request scan called when driver not ready.\n");
b481de9c
ZY
2751 goto done;
2752 }
2753
a96a27f9 2754 /* Make sure the scan wasn't canceled before this queued work
b481de9c
ZY
2755 * was given the chance to run... */
2756 if (!test_bit(STATUS_SCANNING, &priv->status))
2757 goto done;
2758
2759 /* This should never be called or scheduled if there is currently
2760 * a scan active in the hardware. */
2761 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
e1623446
TW
2762 IWL_DEBUG_INFO(priv, "Multiple concurrent scan requests "
2763 "Ignoring second request.\n");
b481de9c
ZY
2764 rc = -EIO;
2765 goto done;
2766 }
2767
2768 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
e1623446 2769 IWL_DEBUG_SCAN(priv, "Aborting scan due to device shutdown\n");
b481de9c
ZY
2770 goto done;
2771 }
2772
2773 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
e1623446
TW
2774 IWL_DEBUG_HC(priv,
2775 "Scan request while abort pending. Queuing.\n");
b481de9c
ZY
2776 goto done;
2777 }
2778
775a6e27 2779 if (iwl_is_rfkill(priv)) {
e1623446 2780 IWL_DEBUG_HC(priv, "Aborting scan due to RF Kill activation\n");
b481de9c
ZY
2781 goto done;
2782 }
2783
2784 if (!test_bit(STATUS_READY, &priv->status)) {
e1623446
TW
2785 IWL_DEBUG_HC(priv,
2786 "Scan request while uninitialized. Queuing.\n");
b481de9c
ZY
2787 goto done;
2788 }
2789
2790 if (!priv->scan_bands) {
e1623446 2791 IWL_DEBUG_HC(priv, "Aborting scan due to no requested bands\n");
b481de9c
ZY
2792 goto done;
2793 }
2794
805cee5b
WT
2795 if (!priv->scan) {
2796 priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
b481de9c 2797 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
805cee5b 2798 if (!priv->scan) {
b481de9c
ZY
2799 rc = -ENOMEM;
2800 goto done;
2801 }
2802 }
805cee5b 2803 scan = priv->scan;
bb8c093b 2804 memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
b481de9c
ZY
2805
2806 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
2807 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
2808
8ccde88a 2809 if (iwl_is_associated(priv)) {
b481de9c
ZY
2810 u16 interval = 0;
2811 u32 extra;
2812 u32 suspend_time = 100;
2813 u32 scan_suspend_time = 100;
2814 unsigned long flags;
2815
e1623446 2816 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
b481de9c
ZY
2817
2818 spin_lock_irqsave(&priv->lock, flags);
2819 interval = priv->beacon_int;
2820 spin_unlock_irqrestore(&priv->lock, flags);
2821
2822 scan->suspend_time = 0;
15e869d8 2823 scan->max_out_time = cpu_to_le32(200 * 1024);
b481de9c
ZY
2824 if (!interval)
2825 interval = suspend_time;
2826 /*
2827 * suspend time format:
2828 * 0-19: beacon interval in usec (time before exec.)
2829 * 20-23: 0
2830 * 24-31: number of beacons (suspend between channels)
2831 */
2832
2833 extra = (suspend_time / interval) << 24;
2834 scan_suspend_time = 0xFF0FFFFF &
2835 (extra | ((suspend_time % interval) * 1024));
2836
2837 scan->suspend_time = cpu_to_le32(scan_suspend_time);
e1623446 2838 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
b481de9c
ZY
2839 scan_suspend_time, interval);
2840 }
2841
1ecf9fc1
JB
2842 if (priv->scan_request->n_ssids) {
2843 int i, p = 0;
2844 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
2845 for (i = 0; i < priv->scan_request->n_ssids; i++) {
2846 /* always does wildcard anyway */
2847 if (!priv->scan_request->ssids[i].ssid_len)
2848 continue;
2849 scan->direct_scan[p].id = WLAN_EID_SSID;
2850 scan->direct_scan[p].len =
2851 priv->scan_request->ssids[i].ssid_len;
2852 memcpy(scan->direct_scan[p].ssid,
2853 priv->scan_request->ssids[i].ssid,
2854 priv->scan_request->ssids[i].ssid_len);
2855 n_probes++;
2856 p++;
2857 }
2858 is_active = true;
f9340520 2859 } else
1ecf9fc1 2860 IWL_DEBUG_SCAN(priv, "Kicking off passive scan.\n");
b481de9c
ZY
2861
2862 /* We don't build a direct scan probe request; the uCode will do
2863 * that based on the direct_mask added to each channel entry */
b481de9c 2864 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
3832ec9d 2865 scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY
2866 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2867
2868 /* flags + rate selection */
2869
66b5004d 2870 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
b481de9c
ZY
2871 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
2872 scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
2873 scan->good_CRC_th = 0;
8318d78a 2874 band = IEEE80211_BAND_2GHZ;
66b5004d 2875 } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
b481de9c 2876 scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
b097ad29
JB
2877 /*
2878 * If active scaning is requested but a certain channel
2879 * is marked passive, we can do active scanning if we
2880 * detect transmissions.
2881 */
2882 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH : 0;
8318d78a 2883 band = IEEE80211_BAND_5GHZ;
66b5004d 2884 } else {
39aadf8c 2885 IWL_WARN(priv, "Invalid scan band count\n");
b481de9c
ZY
2886 goto done;
2887 }
2888
77fecfb8 2889 scan->tx_cmd.len = cpu_to_le16(
1ecf9fc1
JB
2890 iwl_fill_probe_req(priv,
2891 (struct ieee80211_mgmt *)scan->data,
2892 priv->scan_request->ie,
2893 priv->scan_request->ie_len,
2894 IWL_MAX_SCAN_SIZE - sizeof(*scan)));
77fecfb8 2895
b481de9c
ZY
2896 /* select Rx antennas */
2897 scan->flags |= iwl3945_get_antenna_flags(priv);
2898
279b05d4 2899 if (iwl_is_monitor_mode(priv))
b481de9c
ZY
2900 scan->filter_flags = RXON_FILTER_PROMISC_MSK;
2901
f9340520 2902 scan->channel_count =
1ecf9fc1 2903 iwl3945_get_channels_for_scan(priv, band, is_active, n_probes,
f9340520 2904 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
b481de9c 2905
14b54336 2906 if (scan->channel_count == 0) {
e1623446 2907 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
14b54336
RC
2908 goto done;
2909 }
2910
b481de9c 2911 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
bb8c093b 2912 scan->channel_count * sizeof(struct iwl3945_scan_channel);
b481de9c
ZY
2913 cmd.data = scan;
2914 scan->len = cpu_to_le16(cmd.len);
2915
2916 set_bit(STATUS_SCAN_HW, &priv->status);
518099a8 2917 rc = iwl_send_cmd_sync(priv, &cmd);
b481de9c
ZY
2918 if (rc)
2919 goto done;
2920
2921 queue_delayed_work(priv->workqueue, &priv->scan_check,
2922 IWL_SCAN_CHECK_WATCHDOG);
2923
2924 mutex_unlock(&priv->mutex);
2925 return;
2926
2927 done:
2420ebc1
MA
2928 /* can not perform scan make sure we clear scanning
2929 * bits from status so next scan request can be performed.
2930 * if we dont clear scanning status bit here all next scan
2931 * will fail
2932 */
2933 clear_bit(STATUS_SCAN_HW, &priv->status);
2934 clear_bit(STATUS_SCANNING, &priv->status);
2935
01ebd063 2936 /* inform mac80211 scan aborted */
b481de9c
ZY
2937 queue_work(priv->workqueue, &priv->scan_completed);
2938 mutex_unlock(&priv->mutex);
2939}
2940
bb8c093b 2941static void iwl3945_bg_up(struct work_struct *data)
b481de9c 2942{
4a8a4322 2943 struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
b481de9c
ZY
2944
2945 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2946 return;
2947
2948 mutex_lock(&priv->mutex);
bb8c093b 2949 __iwl3945_up(priv);
b481de9c
ZY
2950 mutex_unlock(&priv->mutex);
2951}
2952
bb8c093b 2953static void iwl3945_bg_restart(struct work_struct *data)
b481de9c 2954{
4a8a4322 2955 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY
2956
2957 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2958 return;
2959
19cc1087
JB
2960 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2961 mutex_lock(&priv->mutex);
2962 priv->vif = NULL;
2963 priv->is_open = 0;
2964 mutex_unlock(&priv->mutex);
2965 iwl3945_down(priv);
2966 ieee80211_restart_hw(priv->hw);
2967 } else {
2968 iwl3945_down(priv);
2969 queue_work(priv->workqueue, &priv->up);
2970 }
b481de9c
ZY
2971}
2972
bb8c093b 2973static void iwl3945_bg_rx_replenish(struct work_struct *data)
b481de9c 2974{
4a8a4322
AK
2975 struct iwl_priv *priv =
2976 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY
2977
2978 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2979 return;
2980
2981 mutex_lock(&priv->mutex);
bb8c093b 2982 iwl3945_rx_replenish(priv);
b481de9c
ZY
2983 mutex_unlock(&priv->mutex);
2984}
2985
7878a5a4
MA
2986#define IWL_DELAY_NEXT_SCAN (HZ*2)
2987
5bbe233b 2988void iwl3945_post_associate(struct iwl_priv *priv)
b481de9c 2989{
b481de9c
ZY
2990 int rc = 0;
2991 struct ieee80211_conf *conf = NULL;
2992
05c914fe 2993 if (priv->iw_mode == NL80211_IFTYPE_AP) {
15b1687c 2994 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY
2995 return;
2996 }
2997
2998
e1623446 2999 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
8ccde88a 3000 priv->assoc_id, priv->active_rxon.bssid_addr);
b481de9c
ZY
3001
3002 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3003 return;
3004
322a9811 3005 if (!priv->vif || !priv->is_open)
6ef89d0a 3006 return;
322a9811 3007
af0053d6 3008 iwl_scan_cancel_timeout(priv, 200);
15e869d8 3009
b481de9c
ZY
3010 conf = ieee80211_get_hw_conf(priv->hw);
3011
8ccde88a 3012 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 3013 iwlcore_commit_rxon(priv);
b481de9c 3014
28afaf91 3015 memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
2c2f3b33 3016 iwl_setup_rxon_timing(priv);
518099a8 3017 rc = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY
3018 sizeof(priv->rxon_timing), &priv->rxon_timing);
3019 if (rc)
39aadf8c 3020 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
3021 "Attempting to continue.\n");
3022
8ccde88a 3023 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c 3024
8ccde88a 3025 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
b481de9c 3026
e1623446 3027 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
b481de9c
ZY
3028 priv->assoc_id, priv->beacon_int);
3029
3030 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
8ccde88a 3031 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 3032 else
8ccde88a 3033 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 3034
8ccde88a 3035 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
b481de9c 3036 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
8ccde88a 3037 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
b481de9c 3038 else
8ccde88a 3039 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c 3040
05c914fe 3041 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
8ccde88a 3042 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c
ZY
3043
3044 }
3045
e0158e61 3046 iwlcore_commit_rxon(priv);
b481de9c
ZY
3047
3048 switch (priv->iw_mode) {
05c914fe 3049 case NL80211_IFTYPE_STATION:
bb8c093b 3050 iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
b481de9c
ZY
3051 break;
3052
05c914fe 3053 case NL80211_IFTYPE_ADHOC:
b481de9c 3054
ce546fd2 3055 priv->assoc_id = 1;
c587de0b 3056 iwl_add_station(priv, priv->bssid, 0, CMD_SYNC, NULL);
b481de9c 3057 iwl3945_sync_sta(priv, IWL_STA_ID,
8318d78a 3058 (priv->band == IEEE80211_BAND_5GHZ) ?
b481de9c
ZY
3059 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
3060 CMD_ASYNC);
bb8c093b
CH
3061 iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
3062 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
3063
3064 break;
3065
3066 default:
15b1687c 3067 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3ac7f146 3068 __func__, priv->iw_mode);
b481de9c
ZY
3069 break;
3070 }
3071
14d2aac5 3072 iwl_activate_qos(priv, 0);
292ae174 3073
7878a5a4
MA
3074 /* we have just associated, don't start scan too early */
3075 priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
cd56d331
AK
3076}
3077
b481de9c
ZY
3078/*****************************************************************************
3079 *
3080 * mac80211 entry point functions
3081 *
3082 *****************************************************************************/
3083
5a66926a
ZY
3084#define UCODE_READY_TIMEOUT (2 * HZ)
3085
bb8c093b 3086static int iwl3945_mac_start(struct ieee80211_hw *hw)
b481de9c 3087{
4a8a4322 3088 struct iwl_priv *priv = hw->priv;
5a66926a 3089 int ret;
b481de9c 3090
e1623446 3091 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY
3092
3093 /* we should be verifying the device is ready to be opened */
3094 mutex_lock(&priv->mutex);
3095
5a66926a
ZY
3096 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
3097 * ucode filename and max sizes are card-specific. */
3098
3099 if (!priv->ucode_code.len) {
3100 ret = iwl3945_read_ucode(priv);
3101 if (ret) {
15b1687c 3102 IWL_ERR(priv, "Could not read microcode: %d\n", ret);
5a66926a
ZY
3103 mutex_unlock(&priv->mutex);
3104 goto out_release_irq;
3105 }
3106 }
b481de9c 3107
e655b9f0 3108 ret = __iwl3945_up(priv);
b481de9c
ZY
3109
3110 mutex_unlock(&priv->mutex);
5a66926a 3111
e655b9f0
ZY
3112 if (ret)
3113 goto out_release_irq;
3114
e1623446 3115 IWL_DEBUG_INFO(priv, "Start UP work.\n");
e655b9f0 3116
5a66926a
ZY
3117 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
3118 * mac80211 will not be run successfully. */
3119 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3120 test_bit(STATUS_READY, &priv->status),
3121 UCODE_READY_TIMEOUT);
3122 if (!ret) {
3123 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c
WT
3124 IWL_ERR(priv,
3125 "Wait for START_ALIVE timeout after %dms.\n",
3126 jiffies_to_msecs(UCODE_READY_TIMEOUT));
5a66926a
ZY
3127 ret = -ETIMEDOUT;
3128 goto out_release_irq;
3129 }
3130 }
3131
2663516d
HS
3132 /* ucode is running and will send rfkill notifications,
3133 * no need to poll the killswitch state anymore */
3134 cancel_delayed_work(&priv->rfkill_poll);
3135
e655b9f0 3136 priv->is_open = 1;
e1623446 3137 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 3138 return 0;
5a66926a
ZY
3139
3140out_release_irq:
e655b9f0 3141 priv->is_open = 0;
e1623446 3142 IWL_DEBUG_MAC80211(priv, "leave - failed\n");
5a66926a 3143 return ret;
b481de9c
ZY
3144}
3145
bb8c093b 3146static void iwl3945_mac_stop(struct ieee80211_hw *hw)
b481de9c 3147{
4a8a4322 3148 struct iwl_priv *priv = hw->priv;
b481de9c 3149
e1623446 3150 IWL_DEBUG_MAC80211(priv, "enter\n");
6ef89d0a 3151
e655b9f0 3152 if (!priv->is_open) {
e1623446 3153 IWL_DEBUG_MAC80211(priv, "leave - skip\n");
e655b9f0
ZY
3154 return;
3155 }
3156
b481de9c 3157 priv->is_open = 0;
5a66926a 3158
775a6e27 3159 if (iwl_is_ready_rf(priv)) {
e655b9f0
ZY
3160 /* stop mac, cancel any scan request and clear
3161 * RXON_FILTER_ASSOC_MSK BIT
3162 */
5a66926a 3163 mutex_lock(&priv->mutex);
af0053d6 3164 iwl_scan_cancel_timeout(priv, 100);
fde3571f 3165 mutex_unlock(&priv->mutex);
fde3571f
MA
3166 }
3167
5a66926a
ZY
3168 iwl3945_down(priv);
3169
3170 flush_workqueue(priv->workqueue);
2663516d
HS
3171
3172 /* start polling the killswitch state again */
3173 queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
3174 round_jiffies_relative(2 * HZ));
6ef89d0a 3175
e1623446 3176 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
3177}
3178
e039fa4a 3179static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 3180{
4a8a4322 3181 struct iwl_priv *priv = hw->priv;
b481de9c 3182
e1623446 3183 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3184
e1623446 3185 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 3186 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 3187
e039fa4a 3188 if (iwl3945_tx_skb(priv, skb))
b481de9c
ZY
3189 dev_kfree_skb_any(skb);
3190
e1623446 3191 IWL_DEBUG_MAC80211(priv, "leave\n");
637f8837 3192 return NETDEV_TX_OK;
b481de9c
ZY
3193}
3194
60690a6a 3195void iwl3945_config_ap(struct iwl_priv *priv)
b481de9c
ZY
3196{
3197 int rc = 0;
3198
d986bcd1 3199 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY
3200 return;
3201
3202 /* The following should be done only at AP bring up */
8ccde88a 3203 if (!(iwl_is_associated(priv))) {
b481de9c
ZY
3204
3205 /* RXON - unassoc (to set timing command) */
8ccde88a 3206 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 3207 iwlcore_commit_rxon(priv);
b481de9c
ZY
3208
3209 /* RXON Timing */
28afaf91 3210 memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
2c2f3b33 3211 iwl_setup_rxon_timing(priv);
518099a8
SO
3212 rc = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
3213 sizeof(priv->rxon_timing),
3214 &priv->rxon_timing);
b481de9c 3215 if (rc)
39aadf8c 3216 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
3217 "Attempting to continue.\n");
3218
3219 /* FIXME: what should be the assoc_id for AP? */
8ccde88a 3220 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
b481de9c 3221 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
8ccde88a 3222 priv->staging_rxon.flags |=
b481de9c
ZY
3223 RXON_FLG_SHORT_PREAMBLE_MSK;
3224 else
8ccde88a 3225 priv->staging_rxon.flags &=
b481de9c
ZY
3226 ~RXON_FLG_SHORT_PREAMBLE_MSK;
3227
8ccde88a 3228 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
b481de9c
ZY
3229 if (priv->assoc_capability &
3230 WLAN_CAPABILITY_SHORT_SLOT_TIME)
8ccde88a 3231 priv->staging_rxon.flags |=
b481de9c
ZY
3232 RXON_FLG_SHORT_SLOT_MSK;
3233 else
8ccde88a 3234 priv->staging_rxon.flags &=
b481de9c
ZY
3235 ~RXON_FLG_SHORT_SLOT_MSK;
3236
05c914fe 3237 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
8ccde88a 3238 priv->staging_rxon.flags &=
b481de9c
ZY
3239 ~RXON_FLG_SHORT_SLOT_MSK;
3240 }
3241 /* restore RXON assoc */
8ccde88a 3242 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
e0158e61 3243 iwlcore_commit_rxon(priv);
c587de0b 3244 iwl_add_station(priv, iwl_bcast_addr, 0, CMD_SYNC, NULL);
556f8db7 3245 }
bb8c093b 3246 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
3247
3248 /* FIXME - we need to add code here to detect a totally new
3249 * configuration, reset the AP, unassoc, rxon timing, assoc,
3250 * clear sta table, add BCAST sta... */
3251}
3252
bb8c093b 3253static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB
3254 struct ieee80211_vif *vif,
3255 struct ieee80211_sta *sta,
3256 struct ieee80211_key_conf *key)
b481de9c 3257{
4a8a4322 3258 struct iwl_priv *priv = hw->priv;
dc822b5d 3259 const u8 *addr;
6e21f15c
AK
3260 int ret = 0;
3261 u8 sta_id = IWL_INVALID_STATION;
3262 u8 static_key;
b481de9c 3263
e1623446 3264 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3265
df878d8f 3266 if (iwl3945_mod_params.sw_crypto) {
e1623446 3267 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY
3268 return -EOPNOTSUPP;
3269 }
3270
42986796 3271 addr = sta ? sta->addr : iwl_bcast_addr;
6e21f15c
AK
3272 static_key = !iwl_is_associated(priv);
3273
3274 if (!static_key) {
c587de0b 3275 sta_id = iwl_find_station(priv, addr);
6e21f15c 3276 if (sta_id == IWL_INVALID_STATION) {
12514396 3277 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
6e21f15c
AK
3278 addr);
3279 return -EINVAL;
3280 }
b481de9c
ZY
3281 }
3282
3283 mutex_lock(&priv->mutex);
af0053d6 3284 iwl_scan_cancel_timeout(priv, 100);
6e21f15c 3285 mutex_unlock(&priv->mutex);
15e869d8 3286
b481de9c 3287 switch (cmd) {
6e21f15c
AK
3288 case SET_KEY:
3289 if (static_key)
3290 ret = iwl3945_set_static_key(priv, key);
3291 else
3292 ret = iwl3945_set_dynamic_key(priv, key, sta_id);
3293 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY
3294 break;
3295 case DISABLE_KEY:
6e21f15c
AK
3296 if (static_key)
3297 ret = iwl3945_remove_static_key(priv);
3298 else
3299 ret = iwl3945_clear_sta_key_info(priv, sta_id);
3300 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY
3301 break;
3302 default:
42986796 3303 ret = -EINVAL;
b481de9c
ZY
3304 }
3305
e1623446 3306 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 3307
42986796 3308 return ret;
b481de9c
ZY
3309}
3310
b481de9c
ZY
3311/*****************************************************************************
3312 *
3313 * sysfs attributes
3314 *
3315 *****************************************************************************/
3316
d08853a3 3317#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
3318
3319/*
3320 * The following adds a new attribute to the sysfs representation
3321 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
3322 * used for controlling the debug level.
3323 *
3324 * See the level definitions in iwl for details.
a562a9dd 3325 *
3d816c77
RC
3326 * The debug_level being managed using sysfs below is a per device debug
3327 * level that is used instead of the global debug level if it (the per
3328 * device debug level) is set.
b481de9c 3329 */
40b8ec0b
SO
3330static ssize_t show_debug_level(struct device *d,
3331 struct device_attribute *attr, char *buf)
b481de9c 3332{
3d816c77
RC
3333 struct iwl_priv *priv = dev_get_drvdata(d);
3334 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
b481de9c 3335}
40b8ec0b
SO
3336static ssize_t store_debug_level(struct device *d,
3337 struct device_attribute *attr,
b481de9c
ZY
3338 const char *buf, size_t count)
3339{
928841b1 3340 struct iwl_priv *priv = dev_get_drvdata(d);
40b8ec0b
SO
3341 unsigned long val;
3342 int ret;
b481de9c 3343
40b8ec0b
SO
3344 ret = strict_strtoul(buf, 0, &val);
3345 if (ret)
978785a3 3346 IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf);
20594eb0 3347 else {
3d816c77 3348 priv->debug_level = val;
20594eb0
WYG
3349 if (iwl_alloc_traffic_mem(priv))
3350 IWL_ERR(priv,
3351 "Not enough memory to generate traffic log\n");
3352 }
b481de9c
ZY
3353 return strnlen(buf, count);
3354}
3355
40b8ec0b
SO
3356static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
3357 show_debug_level, store_debug_level);
b481de9c 3358
d08853a3 3359#endif /* CONFIG_IWLWIFI_DEBUG */
b481de9c 3360
b481de9c
ZY
3361static ssize_t show_temperature(struct device *d,
3362 struct device_attribute *attr, char *buf)
3363{
928841b1 3364 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3365
775a6e27 3366 if (!iwl_is_alive(priv))
b481de9c
ZY
3367 return -EAGAIN;
3368
bb8c093b 3369 return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
b481de9c
ZY
3370}
3371
3372static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
3373
b481de9c
ZY
3374static ssize_t show_tx_power(struct device *d,
3375 struct device_attribute *attr, char *buf)
3376{
928841b1 3377 struct iwl_priv *priv = dev_get_drvdata(d);
62ea9c5b 3378 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
b481de9c
ZY
3379}
3380
3381static ssize_t store_tx_power(struct device *d,
3382 struct device_attribute *attr,
3383 const char *buf, size_t count)
3384{
928841b1 3385 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3386 char *p = (char *)buf;
3387 u32 val;
3388
3389 val = simple_strtoul(p, &p, 10);
3390 if (p == buf)
978785a3 3391 IWL_INFO(priv, ": %s is not in decimal form.\n", buf);
b481de9c 3392 else
bb8c093b 3393 iwl3945_hw_reg_set_txpower(priv, val);
b481de9c
ZY
3394
3395 return count;
3396}
3397
3398static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
3399
3400static ssize_t show_flags(struct device *d,
3401 struct device_attribute *attr, char *buf)
3402{
928841b1 3403 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3404
8ccde88a 3405 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
b481de9c
ZY
3406}
3407
3408static ssize_t store_flags(struct device *d,
3409 struct device_attribute *attr,
3410 const char *buf, size_t count)
3411{
928841b1 3412 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3413 u32 flags = simple_strtoul(buf, NULL, 0);
3414
3415 mutex_lock(&priv->mutex);
8ccde88a 3416 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
b481de9c 3417 /* Cancel any currently running scans... */
af0053d6 3418 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 3419 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 3420 else {
e1623446 3421 IWL_DEBUG_INFO(priv, "Committing rxon.flags = 0x%04X\n",
b481de9c 3422 flags);
8ccde88a 3423 priv->staging_rxon.flags = cpu_to_le32(flags);
e0158e61 3424 iwlcore_commit_rxon(priv);
b481de9c
ZY
3425 }
3426 }
3427 mutex_unlock(&priv->mutex);
3428
3429 return count;
3430}
3431
3432static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
3433
3434static ssize_t show_filter_flags(struct device *d,
3435 struct device_attribute *attr, char *buf)
3436{
928841b1 3437 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3438
3439 return sprintf(buf, "0x%04X\n",
8ccde88a 3440 le32_to_cpu(priv->active_rxon.filter_flags));
b481de9c
ZY
3441}
3442
3443static ssize_t store_filter_flags(struct device *d,
3444 struct device_attribute *attr,
3445 const char *buf, size_t count)
3446{
928841b1 3447 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3448 u32 filter_flags = simple_strtoul(buf, NULL, 0);
3449
3450 mutex_lock(&priv->mutex);
8ccde88a 3451 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
b481de9c 3452 /* Cancel any currently running scans... */
af0053d6 3453 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 3454 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 3455 else {
e1623446 3456 IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
b481de9c 3457 "0x%04X\n", filter_flags);
8ccde88a 3458 priv->staging_rxon.filter_flags =
b481de9c 3459 cpu_to_le32(filter_flags);
e0158e61 3460 iwlcore_commit_rxon(priv);
b481de9c
ZY
3461 }
3462 }
3463 mutex_unlock(&priv->mutex);
3464
3465 return count;
3466}
3467
3468static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
3469 store_filter_flags);
3470
c8b0e6e1 3471#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY
3472
3473static ssize_t show_measurement(struct device *d,
3474 struct device_attribute *attr, char *buf)
3475{
4a8a4322 3476 struct iwl_priv *priv = dev_get_drvdata(d);
600c0e11 3477 struct iwl_spectrum_notification measure_report;
b481de9c 3478 u32 size = sizeof(measure_report), len = 0, ofs = 0;
3ac7f146 3479 u8 *data = (u8 *)&measure_report;
b481de9c
ZY
3480 unsigned long flags;
3481
3482 spin_lock_irqsave(&priv->lock, flags);
3483 if (!(priv->measurement_status & MEASUREMENT_READY)) {
3484 spin_unlock_irqrestore(&priv->lock, flags);
3485 return 0;
3486 }
3487 memcpy(&measure_report, &priv->measure_report, size);
3488 priv->measurement_status = 0;
3489 spin_unlock_irqrestore(&priv->lock, flags);
3490
3491 while (size && (PAGE_SIZE - len)) {
3492 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3493 PAGE_SIZE - len, 1);
3494 len = strlen(buf);
3495 if (PAGE_SIZE - len)
3496 buf[len++] = '\n';
3497
3498 ofs += 16;
3499 size -= min(size, 16U);
3500 }
3501
3502 return len;
3503}
3504
3505static ssize_t store_measurement(struct device *d,
3506 struct device_attribute *attr,
3507 const char *buf, size_t count)
3508{
4a8a4322 3509 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3510 struct ieee80211_measurement_params params = {
8ccde88a 3511 .channel = le16_to_cpu(priv->active_rxon.channel),
b481de9c
ZY
3512 .start_time = cpu_to_le64(priv->last_tsf),
3513 .duration = cpu_to_le16(1),
3514 };
3515 u8 type = IWL_MEASURE_BASIC;
3516 u8 buffer[32];
3517 u8 channel;
3518
3519 if (count) {
3520 char *p = buffer;
3521 strncpy(buffer, buf, min(sizeof(buffer), count));
3522 channel = simple_strtoul(p, NULL, 0);
3523 if (channel)
3524 params.channel = channel;
3525
3526 p = buffer;
3527 while (*p && *p != ' ')
3528 p++;
3529 if (*p)
3530 type = simple_strtoul(p + 1, NULL, 0);
3531 }
3532
e1623446 3533 IWL_DEBUG_INFO(priv, "Invoking measurement of type %d on "
b481de9c 3534 "channel %d (for '%s')\n", type, params.channel, buf);
bb8c093b 3535 iwl3945_get_measurement(priv, &params, type);
b481de9c
ZY
3536
3537 return count;
3538}
3539
3540static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
3541 show_measurement, store_measurement);
c8b0e6e1 3542#endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
b481de9c 3543
b481de9c
ZY
3544static ssize_t store_retry_rate(struct device *d,
3545 struct device_attribute *attr,
3546 const char *buf, size_t count)
3547{
4a8a4322 3548 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3549
3550 priv->retry_rate = simple_strtoul(buf, NULL, 0);
3551 if (priv->retry_rate <= 0)
3552 priv->retry_rate = 1;
3553
3554 return count;
3555}
3556
3557static ssize_t show_retry_rate(struct device *d,
3558 struct device_attribute *attr, char *buf)
3559{
4a8a4322 3560 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3561 return sprintf(buf, "%d", priv->retry_rate);
3562}
3563
3564static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
3565 store_retry_rate);
3566
d25aabb0 3567
b481de9c
ZY
3568static ssize_t show_channels(struct device *d,
3569 struct device_attribute *attr, char *buf)
3570{
8318d78a
JB
3571 /* all this shit doesn't belong into sysfs anyway */
3572 return 0;
b481de9c
ZY
3573}
3574
3575static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
3576
3577static ssize_t show_statistics(struct device *d,
3578 struct device_attribute *attr, char *buf)
3579{
4a8a4322 3580 struct iwl_priv *priv = dev_get_drvdata(d);
bb8c093b 3581 u32 size = sizeof(struct iwl3945_notif_statistics);
b481de9c 3582 u32 len = 0, ofs = 0;
f2c7e521 3583 u8 *data = (u8 *)&priv->statistics_39;
b481de9c
ZY
3584 int rc = 0;
3585
775a6e27 3586 if (!iwl_is_alive(priv))
b481de9c
ZY
3587 return -EAGAIN;
3588
3589 mutex_lock(&priv->mutex);
17f841cd 3590 rc = iwl_send_statistics_request(priv, 0);
b481de9c
ZY
3591 mutex_unlock(&priv->mutex);
3592
3593 if (rc) {
3594 len = sprintf(buf,
3595 "Error sending statistics request: 0x%08X\n", rc);
3596 return len;
3597 }
3598
3599 while (size && (PAGE_SIZE - len)) {
3600 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3601 PAGE_SIZE - len, 1);
3602 len = strlen(buf);
3603 if (PAGE_SIZE - len)
3604 buf[len++] = '\n';
3605
3606 ofs += 16;
3607 size -= min(size, 16U);
3608 }
3609
3610 return len;
3611}
3612
3613static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
3614
3615static ssize_t show_antenna(struct device *d,
3616 struct device_attribute *attr, char *buf)
3617{
4a8a4322 3618 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3619
775a6e27 3620 if (!iwl_is_alive(priv))
b481de9c
ZY
3621 return -EAGAIN;
3622
7e4bca5e 3623 return sprintf(buf, "%d\n", iwl3945_mod_params.antenna);
b481de9c
ZY
3624}
3625
3626static ssize_t store_antenna(struct device *d,
3627 struct device_attribute *attr,
3628 const char *buf, size_t count)
3629{
7530f85f 3630 struct iwl_priv *priv __maybe_unused = dev_get_drvdata(d);
b481de9c 3631 int ant;
b481de9c
ZY
3632
3633 if (count == 0)
3634 return 0;
3635
3636 if (sscanf(buf, "%1i", &ant) != 1) {
e1623446 3637 IWL_DEBUG_INFO(priv, "not in hex or decimal form.\n");
b481de9c
ZY
3638 return count;
3639 }
3640
3641 if ((ant >= 0) && (ant <= 2)) {
e1623446 3642 IWL_DEBUG_INFO(priv, "Setting antenna select to %d.\n", ant);
7e4bca5e 3643 iwl3945_mod_params.antenna = (enum iwl3945_antenna)ant;
b481de9c 3644 } else
e1623446 3645 IWL_DEBUG_INFO(priv, "Bad antenna select value %d.\n", ant);
b481de9c
ZY
3646
3647
3648 return count;
3649}
3650
3651static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
3652
3653static ssize_t show_status(struct device *d,
3654 struct device_attribute *attr, char *buf)
3655{
928841b1 3656 struct iwl_priv *priv = dev_get_drvdata(d);
775a6e27 3657 if (!iwl_is_alive(priv))
b481de9c
ZY
3658 return -EAGAIN;
3659 return sprintf(buf, "0x%08x\n", (int)priv->status);
3660}
3661
3662static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
3663
3664static ssize_t dump_error_log(struct device *d,
3665 struct device_attribute *attr,
3666 const char *buf, size_t count)
3667{
928841b1 3668 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3669 char *p = (char *)buf;
3670
3671 if (p[0] == '1')
928841b1 3672 iwl3945_dump_nic_error_log(priv);
b481de9c
ZY
3673
3674 return strnlen(buf, count);
3675}
3676
3677static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
3678
3679static ssize_t dump_event_log(struct device *d,
3680 struct device_attribute *attr,
3681 const char *buf, size_t count)
3682{
928841b1 3683 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3684 char *p = (char *)buf;
3685
3686 if (p[0] == '1')
928841b1 3687 iwl3945_dump_nic_event_log(priv);
b481de9c
ZY
3688
3689 return strnlen(buf, count);
3690}
3691
3692static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
3693
3694/*****************************************************************************
3695 *
a96a27f9 3696 * driver setup and tear down
b481de9c
ZY
3697 *
3698 *****************************************************************************/
3699
4a8a4322 3700static void iwl3945_setup_deferred_work(struct iwl_priv *priv)
b481de9c 3701{
d21050c7 3702 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY
3703
3704 init_waitqueue_head(&priv->wait_command_queue);
3705
bb8c093b
CH
3706 INIT_WORK(&priv->up, iwl3945_bg_up);
3707 INIT_WORK(&priv->restart, iwl3945_bg_restart);
3708 INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
bb8c093b 3709 INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
bb8c093b
CH
3710 INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
3711 INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
2663516d 3712 INIT_DELAYED_WORK(&priv->rfkill_poll, iwl3945_rfkill_poll);
77fecfb8
SO
3713 INIT_WORK(&priv->scan_completed, iwl_bg_scan_completed);
3714 INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
3715 INIT_WORK(&priv->abort_scan, iwl_bg_abort_scan);
3716 INIT_DELAYED_WORK(&priv->scan_check, iwl_bg_scan_check);
bb8c093b
CH
3717
3718 iwl3945_hw_setup_deferred_work(priv);
b481de9c
ZY
3719
3720 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
bb8c093b 3721 iwl3945_irq_tasklet, (unsigned long)priv);
b481de9c
ZY
3722}
3723
4a8a4322 3724static void iwl3945_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 3725{
bb8c093b 3726 iwl3945_hw_cancel_deferred_work(priv);
b481de9c 3727
e47eb6ad 3728 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY
3729 cancel_delayed_work(&priv->scan_check);
3730 cancel_delayed_work(&priv->alive_start);
b481de9c
ZY
3731 cancel_work_sync(&priv->beacon_update);
3732}
3733
bb8c093b 3734static struct attribute *iwl3945_sysfs_entries[] = {
b481de9c
ZY
3735 &dev_attr_antenna.attr,
3736 &dev_attr_channels.attr,
3737 &dev_attr_dump_errors.attr,
3738 &dev_attr_dump_events.attr,
3739 &dev_attr_flags.attr,
3740 &dev_attr_filter_flags.attr,
c8b0e6e1 3741#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY
3742 &dev_attr_measurement.attr,
3743#endif
b481de9c 3744 &dev_attr_retry_rate.attr,
b481de9c
ZY
3745 &dev_attr_statistics.attr,
3746 &dev_attr_status.attr,
3747 &dev_attr_temperature.attr,
b481de9c 3748 &dev_attr_tx_power.attr,
d08853a3 3749#ifdef CONFIG_IWLWIFI_DEBUG
40b8ec0b
SO
3750 &dev_attr_debug_level.attr,
3751#endif
b481de9c
ZY
3752 NULL
3753};
3754
bb8c093b 3755static struct attribute_group iwl3945_attribute_group = {
b481de9c 3756 .name = NULL, /* put in device directory */
bb8c093b 3757 .attrs = iwl3945_sysfs_entries,
b481de9c
ZY
3758};
3759
bb8c093b
CH
3760static struct ieee80211_ops iwl3945_hw_ops = {
3761 .tx = iwl3945_mac_tx,
3762 .start = iwl3945_mac_start,
3763 .stop = iwl3945_mac_stop,
cbb6ab94 3764 .add_interface = iwl_mac_add_interface,
d8052319 3765 .remove_interface = iwl_mac_remove_interface,
4808368d 3766 .config = iwl_mac_config,
8ccde88a 3767 .configure_filter = iwl_configure_filter,
bb8c093b 3768 .set_key = iwl3945_mac_set_key,
aa89f31e 3769 .get_tx_stats = iwl_mac_get_tx_stats,
488829f1 3770 .conf_tx = iwl_mac_conf_tx,
bd564261 3771 .reset_tsf = iwl_mac_reset_tsf,
5bbe233b 3772 .bss_info_changed = iwl_bss_info_changed,
e9dde6f6 3773 .hw_scan = iwl_mac_hw_scan
b481de9c
ZY
3774};
3775
e52119c5 3776static int iwl3945_init_drv(struct iwl_priv *priv)
90a30a02
KA
3777{
3778 int ret;
e6148917 3779 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
90a30a02
KA
3780
3781 priv->retry_rate = 1;
3782 priv->ibss_beacon = NULL;
3783
3784 spin_lock_init(&priv->lock);
90a30a02
KA
3785 spin_lock_init(&priv->sta_lock);
3786 spin_lock_init(&priv->hcmd_lock);
3787
3788 INIT_LIST_HEAD(&priv->free_frames);
3789
3790 mutex_init(&priv->mutex);
3791
3792 /* Clear the driver's (not device's) station table */
c587de0b 3793 iwl_clear_stations_table(priv);
90a30a02
KA
3794
3795 priv->data_retry_limit = -1;
3796 priv->ieee_channels = NULL;
3797 priv->ieee_rates = NULL;
3798 priv->band = IEEE80211_BAND_2GHZ;
3799
3800 priv->iw_mode = NL80211_IFTYPE_STATION;
3801
3802 iwl_reset_qos(priv);
3803
3804 priv->qos_data.qos_active = 0;
3805 priv->qos_data.qos_cap.val = 0;
3806
3807 priv->rates_mask = IWL_RATES_MASK;
62ea9c5b 3808 priv->tx_power_user_lmt = IWL_DEFAULT_TX_POWER;
90a30a02 3809
e6148917
SO
3810 if (eeprom->version < EEPROM_3945_EEPROM_VERSION) {
3811 IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n",
3812 eeprom->version);
3813 ret = -EINVAL;
3814 goto err;
3815 }
3816 ret = iwl_init_channel_map(priv);
90a30a02
KA
3817 if (ret) {
3818 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3819 goto err;
3820 }
3821
e6148917
SO
3822 /* Set up txpower settings in driver for all channels */
3823 if (iwl3945_txpower_set_from_eeprom(priv)) {
3824 ret = -EIO;
3825 goto err_free_channel_map;
3826 }
3827
534166de 3828 ret = iwlcore_init_geos(priv);
90a30a02
KA
3829 if (ret) {
3830 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3831 goto err_free_channel_map;
3832 }
534166de
SO
3833 iwl3945_init_hw_rates(priv, priv->ieee_rates);
3834
2a4ddaab
AK
3835 return 0;
3836
3837err_free_channel_map:
3838 iwl_free_channel_map(priv);
3839err:
3840 return ret;
3841}
3842
3843static int iwl3945_setup_mac(struct iwl_priv *priv)
3844{
3845 int ret;
3846 struct ieee80211_hw *hw = priv->hw;
3847
3848 hw->rate_control_algorithm = "iwl-3945-rs";
3849 hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
3850
3851 /* Tell mac80211 our characteristics */
3852 hw->flags = IEEE80211_HW_SIGNAL_DBM |
b1c6019b 3853 IEEE80211_HW_NOISE_DBM |
e312c24c
JB
3854 IEEE80211_HW_SPECTRUM_MGMT |
3855 IEEE80211_HW_SUPPORTS_PS |
3856 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2a4ddaab
AK
3857
3858 hw->wiphy->interface_modes =
3859 BIT(NL80211_IFTYPE_STATION) |
3860 BIT(NL80211_IFTYPE_ADHOC);
3861
3862 hw->wiphy->custom_regulatory = true;
3863
37184244
LR
3864 /* Firmware does not support this */
3865 hw->wiphy->disable_beacon_hints = true;
3866
1ecf9fc1
JB
3867 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX_3945;
3868 /* we create the 802.11 header and a zero-length SSID element */
3869 hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
d60cc91a 3870
2a4ddaab
AK
3871 /* Default value; 4 EDCA QOS priorities */
3872 hw->queues = 4;
3873
534166de
SO
3874 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3875 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3876 &priv->bands[IEEE80211_BAND_2GHZ];
2a4ddaab 3877
534166de
SO
3878 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3879 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3880 &priv->bands[IEEE80211_BAND_5GHZ];
90a30a02 3881
2a4ddaab
AK
3882 ret = ieee80211_register_hw(priv->hw);
3883 if (ret) {
3884 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3885 return ret;
3886 }
3887 priv->mac80211_registered = 1;
90a30a02 3888
2a4ddaab 3889 return 0;
90a30a02
KA
3890}
3891
bb8c093b 3892static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY
3893{
3894 int err = 0;
4a8a4322 3895 struct iwl_priv *priv;
b481de9c 3896 struct ieee80211_hw *hw;
c0f20d91 3897 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
e6148917 3898 struct iwl3945_eeprom *eeprom;
0359facc 3899 unsigned long flags;
b481de9c 3900
cee53ddb
KA
3901 /***********************
3902 * 1. Allocating HW data
3903 * ********************/
3904
b481de9c
ZY
3905 /* mac80211 allocates memory for this device instance, including
3906 * space for this driver's private structure */
90a30a02 3907 hw = iwl_alloc_all(cfg, &iwl3945_hw_ops);
b481de9c 3908 if (hw == NULL) {
a3139c59 3909 printk(KERN_ERR DRV_NAME "Can not allocate network device\n");
b481de9c
ZY
3910 err = -ENOMEM;
3911 goto out;
3912 }
b481de9c 3913 priv = hw->priv;
90a30a02 3914 SET_IEEE80211_DEV(hw, &pdev->dev);
6440adb5 3915
90a30a02
KA
3916 /*
3917 * Disabling hardware scan means that mac80211 will perform scans
3918 * "the hard way", rather than using device's scan.
3919 */
df878d8f 3920 if (iwl3945_mod_params.disable_hw_scan) {
e1623446 3921 IWL_DEBUG_INFO(priv, "Disabling hw_scan\n");
40b8ec0b
SO
3922 iwl3945_hw_ops.hw_scan = NULL;
3923 }
3924
90a30a02 3925
e1623446 3926 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
90a30a02
KA
3927 priv->cfg = cfg;
3928 priv->pci_dev = pdev;
40cefda9 3929 priv->inta_mask = CSR_INI_SET_MASK;
cee53ddb 3930
d08853a3 3931#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
3932 atomic_set(&priv->restrict_refcnt, 0);
3933#endif
20594eb0
WYG
3934 if (iwl_alloc_traffic_mem(priv))
3935 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 3936
cee53ddb
KA
3937 /***************************
3938 * 2. Initializing PCI bus
3939 * *************************/
b481de9c
ZY
3940 if (pci_enable_device(pdev)) {
3941 err = -ENODEV;
3942 goto out_ieee80211_free_hw;
3943 }
3944
3945 pci_set_master(pdev);
3946
284901a9 3947 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
b481de9c 3948 if (!err)
284901a9 3949 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
b481de9c 3950 if (err) {
978785a3 3951 IWL_WARN(priv, "No suitable DMA available.\n");
b481de9c
ZY
3952 goto out_pci_disable_device;
3953 }
3954
3955 pci_set_drvdata(pdev, priv);
3956 err = pci_request_regions(pdev, DRV_NAME);
3957 if (err)
3958 goto out_pci_disable_device;
6440adb5 3959
cee53ddb
KA
3960 /***********************
3961 * 3. Read REV Register
3962 * ********************/
b481de9c
ZY
3963 priv->hw_base = pci_iomap(pdev, 0, 0);
3964 if (!priv->hw_base) {
3965 err = -ENODEV;
3966 goto out_pci_release_regions;
3967 }
3968
e1623446 3969 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
b481de9c 3970 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 3971 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
b481de9c 3972
cee53ddb
KA
3973 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3974 * PCI Tx retries from interfering with C3 CPU state */
3975 pci_write_config_byte(pdev, 0x41, 0x00);
b481de9c 3976
a8b50a0a
MA
3977 /* this spin lock will be used in apm_ops.init and EEPROM access
3978 * we should init now
3979 */
3980 spin_lock_init(&priv->reg_lock);
3981
90a30a02
KA
3982 /* amp init */
3983 err = priv->cfg->ops->lib->apm_ops.init(priv);
cee53ddb 3984 if (err < 0) {
d5df2a16 3985 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
90a30a02 3986 goto out_iounmap;
cee53ddb 3987 }
b481de9c 3988
cee53ddb
KA
3989 /***********************
3990 * 4. Read EEPROM
3991 * ********************/
90a30a02 3992
cee53ddb 3993 /* Read the EEPROM */
e6148917 3994 err = iwl_eeprom_init(priv);
cee53ddb 3995 if (err) {
15b1687c 3996 IWL_ERR(priv, "Unable to init EEPROM\n");
c8f16138 3997 goto out_iounmap;
cee53ddb
KA
3998 }
3999 /* MAC Address location in EEPROM same for 3945/4965 */
e6148917
SO
4000 eeprom = (struct iwl3945_eeprom *)priv->eeprom;
4001 memcpy(priv->mac_addr, eeprom->mac_address, ETH_ALEN);
e1623446 4002 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
cee53ddb 4003 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
b481de9c 4004
cee53ddb
KA
4005 /***********************
4006 * 5. Setup HW Constants
4007 * ********************/
b481de9c 4008 /* Device-specific setup */
3832ec9d 4009 if (iwl3945_hw_set_hw_params(priv)) {
15b1687c 4010 IWL_ERR(priv, "failed to set hw settings\n");
c8f16138 4011 goto out_eeprom_free;
b481de9c
ZY
4012 }
4013
cee53ddb
KA
4014 /***********************
4015 * 6. Setup priv
4016 * ********************/
cee53ddb 4017
90a30a02 4018 err = iwl3945_init_drv(priv);
b481de9c 4019 if (err) {
90a30a02 4020 IWL_ERR(priv, "initializing driver failed\n");
c8f16138 4021 goto out_unset_hw_params;
b481de9c
ZY
4022 }
4023
978785a3
TW
4024 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n",
4025 priv->cfg->name);
cee53ddb 4026
cee53ddb 4027 /***********************
09f9bf79 4028 * 7. Setup Services
cee53ddb
KA
4029 * ********************/
4030
4031 spin_lock_irqsave(&priv->lock, flags);
ed3b932e 4032 iwl_disable_interrupts(priv);
cee53ddb
KA
4033 spin_unlock_irqrestore(&priv->lock, flags);
4034
2663516d
HS
4035 pci_enable_msi(priv->pci_dev);
4036
ef850d7c
MA
4037 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
4038 IRQF_SHARED, DRV_NAME, priv);
2663516d
HS
4039 if (err) {
4040 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4041 goto out_disable_msi;
4042 }
4043
cee53ddb 4044 err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
849e0dce 4045 if (err) {
15b1687c 4046 IWL_ERR(priv, "failed to create sysfs device attributes\n");
90a30a02 4047 goto out_release_irq;
849e0dce 4048 }
849e0dce 4049
8ccde88a
SO
4050 iwl_set_rxon_channel(priv,
4051 &priv->bands[IEEE80211_BAND_2GHZ].channels[5]);
cee53ddb
KA
4052 iwl3945_setup_deferred_work(priv);
4053 iwl3945_setup_rx_handlers(priv);
4054
cee53ddb 4055 /*********************************
09f9bf79 4056 * 8. Setup and Register mac80211
cee53ddb
KA
4057 * *******************************/
4058
2a4ddaab 4059 iwl_enable_interrupts(priv);
b481de9c 4060
2a4ddaab
AK
4061 err = iwl3945_setup_mac(priv);
4062 if (err)
4063 goto out_remove_sysfs;
cee53ddb 4064
a75fbe8d
AK
4065 err = iwl_dbgfs_register(priv, DRV_NAME);
4066 if (err)
4067 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
4068
2663516d
HS
4069 /* Start monitoring the killswitch */
4070 queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
4071 2 * HZ);
4072
b481de9c
ZY
4073 return 0;
4074
cee53ddb 4075 out_remove_sysfs:
c8f16138
RC
4076 destroy_workqueue(priv->workqueue);
4077 priv->workqueue = NULL;
cee53ddb 4078 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 4079 out_release_irq:
2663516d 4080 free_irq(priv->pci_dev->irq, priv);
2663516d
HS
4081 out_disable_msi:
4082 pci_disable_msi(priv->pci_dev);
c8f16138
RC
4083 iwlcore_free_geos(priv);
4084 iwl_free_channel_map(priv);
4085 out_unset_hw_params:
4086 iwl3945_unset_hw_params(priv);
4087 out_eeprom_free:
4088 iwl_eeprom_free(priv);
b481de9c
ZY
4089 out_iounmap:
4090 pci_iounmap(pdev, priv->hw_base);
4091 out_pci_release_regions:
4092 pci_release_regions(pdev);
4093 out_pci_disable_device:
b481de9c 4094 pci_set_drvdata(pdev, NULL);
623d563e 4095 pci_disable_device(pdev);
b481de9c
ZY
4096 out_ieee80211_free_hw:
4097 ieee80211_free_hw(priv->hw);
20594eb0 4098 iwl_free_traffic_mem(priv);
b481de9c
ZY
4099 out:
4100 return err;
4101}
4102
c83dbf68 4103static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
b481de9c 4104{
4a8a4322 4105 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 4106 unsigned long flags;
b481de9c
ZY
4107
4108 if (!priv)
4109 return;
4110
e1623446 4111 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 4112
a75fbe8d
AK
4113 iwl_dbgfs_unregister(priv);
4114
b481de9c 4115 set_bit(STATUS_EXIT_PENDING, &priv->status);
b24d22b1 4116
d552bfb6
KA
4117 if (priv->mac80211_registered) {
4118 ieee80211_unregister_hw(priv->hw);
4119 priv->mac80211_registered = 0;
4120 } else {
4121 iwl3945_down(priv);
4122 }
b481de9c 4123
0359facc
MA
4124 /* make sure we flush any pending irq or
4125 * tasklet for the driver
4126 */
4127 spin_lock_irqsave(&priv->lock, flags);
ed3b932e 4128 iwl_disable_interrupts(priv);
0359facc
MA
4129 spin_unlock_irqrestore(&priv->lock, flags);
4130
4131 iwl_synchronize_irq(priv);
4132
bb8c093b 4133 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 4134
71d449b5 4135 cancel_delayed_work_sync(&priv->rfkill_poll);
2663516d 4136
bb8c093b 4137 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY
4138
4139 if (priv->rxq.bd)
df833b1d 4140 iwl3945_rx_queue_free(priv, &priv->rxq);
bb8c093b 4141 iwl3945_hw_txq_ctx_free(priv);
b481de9c 4142
3832ec9d 4143 iwl3945_unset_hw_params(priv);
c587de0b 4144 iwl_clear_stations_table(priv);
b481de9c 4145
6ef89d0a
MA
4146 /*netif_stop_queue(dev); */
4147 flush_workqueue(priv->workqueue);
4148
bb8c093b 4149 /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
b481de9c
ZY
4150 * priv->workqueue... so we can't take down the workqueue
4151 * until now... */
4152 destroy_workqueue(priv->workqueue);
4153 priv->workqueue = NULL;
20594eb0 4154 iwl_free_traffic_mem(priv);
b481de9c 4155
2663516d
HS
4156 free_irq(pdev->irq, priv);
4157 pci_disable_msi(pdev);
4158
b481de9c
ZY
4159 pci_iounmap(pdev, priv->hw_base);
4160 pci_release_regions(pdev);
4161 pci_disable_device(pdev);
4162 pci_set_drvdata(pdev, NULL);
4163
e6148917 4164 iwl_free_channel_map(priv);
534166de 4165 iwlcore_free_geos(priv);
805cee5b 4166 kfree(priv->scan);
b481de9c
ZY
4167 if (priv->ibss_beacon)
4168 dev_kfree_skb(priv->ibss_beacon);
4169
4170 ieee80211_free_hw(priv->hw);
4171}
4172
b481de9c
ZY
4173
4174/*****************************************************************************
4175 *
4176 * driver and module entry point
4177 *
4178 *****************************************************************************/
4179
bb8c093b 4180static struct pci_driver iwl3945_driver = {
b481de9c 4181 .name = DRV_NAME,
bb8c093b
CH
4182 .id_table = iwl3945_hw_card_ids,
4183 .probe = iwl3945_pci_probe,
4184 .remove = __devexit_p(iwl3945_pci_remove),
b481de9c 4185#ifdef CONFIG_PM
6da3a13e
WYG
4186 .suspend = iwl_pci_suspend,
4187 .resume = iwl_pci_resume,
b481de9c
ZY
4188#endif
4189};
4190
bb8c093b 4191static int __init iwl3945_init(void)
b481de9c
ZY
4192{
4193
4194 int ret;
4195 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
4196 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2
RC
4197
4198 ret = iwl3945_rate_control_register();
4199 if (ret) {
a3139c59
SO
4200 printk(KERN_ERR DRV_NAME
4201 "Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC
4202 return ret;
4203 }
4204
bb8c093b 4205 ret = pci_register_driver(&iwl3945_driver);
b481de9c 4206 if (ret) {
a3139c59 4207 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
897e1cf2 4208 goto error_register;
b481de9c 4209 }
b481de9c
ZY
4210
4211 return ret;
897e1cf2 4212
897e1cf2
RC
4213error_register:
4214 iwl3945_rate_control_unregister();
4215 return ret;
b481de9c
ZY
4216}
4217
bb8c093b 4218static void __exit iwl3945_exit(void)
b481de9c 4219{
bb8c093b 4220 pci_unregister_driver(&iwl3945_driver);
897e1cf2 4221 iwl3945_rate_control_unregister();
b481de9c
ZY
4222}
4223
a0987a8d 4224MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
25cb6cad 4225
df878d8f 4226module_param_named(antenna, iwl3945_mod_params.antenna, int, 0444);
b481de9c 4227MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
9c74d9fb
SO
4228module_param_named(swcrypto, iwl3945_mod_params.sw_crypto, int, 0444);
4229MODULE_PARM_DESC(swcrypto,
4230 "using software crypto (default 1 [software])\n");
a562a9dd
RC
4231#ifdef CONFIG_IWLWIFI_DEBUG
4232module_param_named(debug, iwl_debug_level, uint, 0644);
b481de9c 4233MODULE_PARM_DESC(debug, "debug output mask");
a562a9dd 4234#endif
df878d8f 4235module_param_named(disable_hw_scan, iwl3945_mod_params.disable_hw_scan, int, 0444);
b481de9c 4236MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
af48d048
SO
4237module_param_named(fw_restart3945, iwl3945_mod_params.restart_fw, int, 0444);
4238MODULE_PARM_DESC(fw_restart3945, "restart firmware in case of error");
4239
bb8c093b
CH
4240module_exit(iwl3945_exit);
4241module_init(iwl3945_init);
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