iwlwifi: re-introduce per device debugging
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl3945-base.c
CommitLineData
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1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
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4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
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26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
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30#include <linux/kernel.h>
31#include <linux/module.h>
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32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
36#include <linux/skbuff.h>
37#include <linux/netdevice.h>
38#include <linux/wireless.h>
39#include <linux/firmware.h>
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40#include <linux/etherdevice.h>
41#include <linux/if_arp.h>
42
43#include <net/ieee80211_radiotap.h>
7e272fcf 44#include <net/lib80211.h>
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45#include <net/mac80211.h>
46
47#include <asm/div64.h>
48
a3139c59
SO
49#define DRV_NAME "iwl3945"
50
dbb6654c
WT
51#include "iwl-fh.h"
52#include "iwl-3945-fh.h"
600c0e11 53#include "iwl-commands.h"
17f841cd 54#include "iwl-sta.h"
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55#include "iwl-3945.h"
56#include "iwl-helpers.h"
5747d47f 57#include "iwl-core.h"
d20b3c65 58#include "iwl-dev.h"
b481de9c 59
b481de9c
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60/*
61 * module name, copyright, version, etc.
b481de9c
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62 */
63
64#define DRV_DESCRIPTION \
65"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
66
d08853a3 67#ifdef CONFIG_IWLWIFI_DEBUG
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68#define VD "d"
69#else
70#define VD
71#endif
72
c8b0e6e1 73#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
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74#define VS "s"
75#else
76#define VS
77#endif
78
eaa686c3 79#define IWL39_VERSION "1.2.26k" VD VS
01f8162a 80#define DRV_COPYRIGHT "Copyright(c) 2003-2009 Intel Corporation"
a7b75207 81#define DRV_AUTHOR "<ilw@linux.intel.com>"
eaa686c3 82#define DRV_VERSION IWL39_VERSION
b481de9c 83
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84
85MODULE_DESCRIPTION(DRV_DESCRIPTION);
86MODULE_VERSION(DRV_VERSION);
a7b75207 87MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
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88MODULE_LICENSE("GPL");
89
df878d8f
KA
90 /* module parameters */
91struct iwl_mod_params iwl3945_mod_params = {
5905a1aa 92 .num_of_queues = IWL39_NUM_QUEUES, /* Not used */
9c74d9fb 93 .sw_crypto = 1,
af48d048 94 .restart_fw = 1,
df878d8f
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95 /* the rest are 0 by default */
96};
97
7e4bca5e
SO
98/**
99 * iwl3945_get_antenna_flags - Get antenna flags for RXON command
100 * @priv: eeprom and antenna fields are used to determine antenna flags
101 *
102 * priv->eeprom39 is used to determine if antenna AUX/MAIN are reversed
103 * iwl3945_mod_params.antenna specifies the antenna diversity mode:
104 *
105 * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
106 * IWL_ANTENNA_MAIN - Force MAIN antenna
107 * IWL_ANTENNA_AUX - Force AUX antenna
108 */
109__le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv)
110{
111 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
112
113 switch (iwl3945_mod_params.antenna) {
114 case IWL_ANTENNA_DIVERSITY:
115 return 0;
116
117 case IWL_ANTENNA_MAIN:
118 if (eeprom->antenna_switch_type)
119 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
120 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
121
122 case IWL_ANTENNA_AUX:
123 if (eeprom->antenna_switch_type)
124 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
125 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
126 }
127
128 /* bad antenna selector value */
129 IWL_ERR(priv, "Bad antenna selector value (0x%x)\n",
130 iwl3945_mod_params.antenna);
131
132 return 0; /* "diversity" is default if error */
133}
134
6e21f15c 135static int iwl3945_set_ccmp_dynamic_key_info(struct iwl_priv *priv,
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136 struct ieee80211_key_conf *keyconf,
137 u8 sta_id)
138{
139 unsigned long flags;
140 __le16 key_flags = 0;
6e21f15c
AK
141 int ret;
142
143 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
144 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
145
146 if (sta_id == priv->hw_params.bcast_sta_id)
147 key_flags |= STA_KEY_MULTICAST_MSK;
148
149 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
150 keyconf->hw_key_idx = keyconf->keyidx;
151 key_flags &= ~STA_KEY_FLG_INVALID;
b481de9c 152
b481de9c 153 spin_lock_irqsave(&priv->sta_lock, flags);
c587de0b
TW
154 priv->stations[sta_id].keyinfo.alg = keyconf->alg;
155 priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
156 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
b481de9c
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157 keyconf->keylen);
158
c587de0b 159 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
b481de9c 160 keyconf->keylen);
6e21f15c 161
c587de0b 162 if ((priv->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK)
6e21f15c 163 == STA_KEY_FLG_NO_ENC)
c587de0b 164 priv->stations[sta_id].sta.key.key_offset =
6e21f15c
AK
165 iwl_get_free_ucode_key_index(priv);
166 /* else, we are overriding an existing key => no need to allocated room
167 * in uCode. */
168
c587de0b 169 WARN(priv->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
6e21f15c
AK
170 "no space for a new key");
171
c587de0b
TW
172 priv->stations[sta_id].sta.key.key_flags = key_flags;
173 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
174 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
b481de9c 175
6e21f15c
AK
176 IWL_DEBUG_INFO(priv, "hwcrypto: modify ucode station key info\n");
177
c587de0b 178 ret = iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
6e21f15c 179
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180 spin_unlock_irqrestore(&priv->sta_lock, flags);
181
6e21f15c
AK
182 return ret;
183}
184
185static int iwl3945_set_tkip_dynamic_key_info(struct iwl_priv *priv,
186 struct ieee80211_key_conf *keyconf,
187 u8 sta_id)
188{
189 return -EOPNOTSUPP;
190}
191
192static int iwl3945_set_wep_dynamic_key_info(struct iwl_priv *priv,
193 struct ieee80211_key_conf *keyconf,
194 u8 sta_id)
195{
196 return -EOPNOTSUPP;
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197}
198
4a8a4322 199static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id)
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200{
201 unsigned long flags;
202
203 spin_lock_irqsave(&priv->sta_lock, flags);
c587de0b
TW
204 memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl_hw_key));
205 memset(&priv->stations[sta_id].sta.key, 0,
4c897253 206 sizeof(struct iwl4965_keyinfo));
c587de0b
TW
207 priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
208 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
209 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
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210 spin_unlock_irqrestore(&priv->sta_lock, flags);
211
e1623446 212 IWL_DEBUG_INFO(priv, "hwcrypto: clear ucode station key info\n");
c587de0b 213 iwl_send_add_sta(priv, &priv->stations[sta_id].sta, 0);
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214 return 0;
215}
216
fa11d525 217static int iwl3945_set_dynamic_key(struct iwl_priv *priv,
6e21f15c
AK
218 struct ieee80211_key_conf *keyconf, u8 sta_id)
219{
220 int ret = 0;
221
222 keyconf->hw_key_idx = HW_KEY_DYNAMIC;
223
224 switch (keyconf->alg) {
225 case ALG_CCMP:
226 ret = iwl3945_set_ccmp_dynamic_key_info(priv, keyconf, sta_id);
227 break;
228 case ALG_TKIP:
229 ret = iwl3945_set_tkip_dynamic_key_info(priv, keyconf, sta_id);
230 break;
231 case ALG_WEP:
232 ret = iwl3945_set_wep_dynamic_key_info(priv, keyconf, sta_id);
233 break;
234 default:
1e680233 235 IWL_ERR(priv, "Unknown alg: %s alg = %d\n", __func__, keyconf->alg);
6e21f15c
AK
236 ret = -EINVAL;
237 }
238
239 IWL_DEBUG_WEP(priv, "Set dynamic key: alg= %d len=%d idx=%d sta=%d ret=%d\n",
240 keyconf->alg, keyconf->keylen, keyconf->keyidx,
241 sta_id, ret);
242
243 return ret;
244}
245
246static int iwl3945_remove_static_key(struct iwl_priv *priv)
247{
248 int ret = -EOPNOTSUPP;
249
250 return ret;
251}
252
253static int iwl3945_set_static_key(struct iwl_priv *priv,
254 struct ieee80211_key_conf *key)
255{
256 if (key->alg == ALG_WEP)
257 return -EOPNOTSUPP;
258
259 IWL_ERR(priv, "Static key invalid: alg %d\n", key->alg);
260 return -EINVAL;
261}
262
4a8a4322 263static void iwl3945_clear_free_frames(struct iwl_priv *priv)
b481de9c
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264{
265 struct list_head *element;
266
e1623446 267 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
b481de9c
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268 priv->frames_count);
269
270 while (!list_empty(&priv->free_frames)) {
271 element = priv->free_frames.next;
272 list_del(element);
bb8c093b 273 kfree(list_entry(element, struct iwl3945_frame, list));
b481de9c
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274 priv->frames_count--;
275 }
276
277 if (priv->frames_count) {
39aadf8c 278 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
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279 priv->frames_count);
280 priv->frames_count = 0;
281 }
282}
283
4a8a4322 284static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv)
b481de9c 285{
bb8c093b 286 struct iwl3945_frame *frame;
b481de9c
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287 struct list_head *element;
288 if (list_empty(&priv->free_frames)) {
289 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
290 if (!frame) {
15b1687c 291 IWL_ERR(priv, "Could not allocate frame!\n");
b481de9c
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292 return NULL;
293 }
294
295 priv->frames_count++;
296 return frame;
297 }
298
299 element = priv->free_frames.next;
300 list_del(element);
bb8c093b 301 return list_entry(element, struct iwl3945_frame, list);
b481de9c
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302}
303
4a8a4322 304static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame)
b481de9c
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305{
306 memset(frame, 0, sizeof(*frame));
307 list_add(&frame->list, &priv->free_frames);
308}
309
4a8a4322 310unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv,
b481de9c 311 struct ieee80211_hdr *hdr,
73ec1cc2 312 int left)
b481de9c
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313{
314
8ccde88a 315 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB
316 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
317 (priv->iw_mode != NL80211_IFTYPE_AP)))
b481de9c
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318 return 0;
319
320 if (priv->ibss_beacon->len > left)
321 return 0;
322
323 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
324
325 return priv->ibss_beacon->len;
326}
327
4a8a4322 328static int iwl3945_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 329{
bb8c093b 330 struct iwl3945_frame *frame;
b481de9c
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331 unsigned int frame_size;
332 int rc;
333 u8 rate;
334
bb8c093b 335 frame = iwl3945_get_free_frame(priv);
b481de9c
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336
337 if (!frame) {
15b1687c 338 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
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339 "command.\n");
340 return -ENOMEM;
341 }
342
8ccde88a 343 rate = iwl_rate_get_lowest_plcp(priv);
b481de9c 344
bb8c093b 345 frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 346
518099a8 347 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
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348 &frame->u.cmd[0]);
349
bb8c093b 350 iwl3945_free_frame(priv, frame);
b481de9c
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351
352 return rc;
353}
354
4a8a4322 355static void iwl3945_unset_hw_params(struct iwl_priv *priv)
b481de9c 356{
3832ec9d 357 if (priv->shared_virt)
b481de9c 358 pci_free_consistent(priv->pci_dev,
bb8c093b 359 sizeof(struct iwl3945_shared),
3832ec9d
AK
360 priv->shared_virt,
361 priv->shared_phys);
b481de9c
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362}
363
4a8a4322 364static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv,
e039fa4a 365 struct ieee80211_tx_info *info,
c2acea8e 366 struct iwl_device_cmd *cmd,
b481de9c 367 struct sk_buff *skb_frag,
6e21f15c 368 int sta_id)
b481de9c 369{
e52119c5 370 struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
c587de0b 371 struct iwl_hw_key *keyinfo = &priv->stations[sta_id].keyinfo;
b481de9c
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372
373 switch (keyinfo->alg) {
374 case ALG_CCMP:
e52119c5
WT
375 tx->sec_ctl = TX_CMD_SEC_CCM;
376 memcpy(tx->key, keyinfo->key, keyinfo->keylen);
e1623446 377 IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
b481de9c
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378 break;
379
380 case ALG_TKIP:
b481de9c
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381 break;
382
383 case ALG_WEP:
e52119c5 384 tx->sec_ctl = TX_CMD_SEC_WEP |
e039fa4a 385 (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
b481de9c
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386
387 if (keyinfo->keylen == 13)
e52119c5 388 tx->sec_ctl |= TX_CMD_SEC_KEY128;
b481de9c 389
e52119c5 390 memcpy(&tx->key[3], keyinfo->key, keyinfo->keylen);
b481de9c 391
e1623446 392 IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
e039fa4a 393 "with key %d\n", info->control.hw_key->hw_key_idx);
b481de9c
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394 break;
395
b481de9c 396 default:
978785a3 397 IWL_ERR(priv, "Unknown encode alg %d\n", keyinfo->alg);
b481de9c
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398 break;
399 }
400}
401
402/*
403 * handle build REPLY_TX command notification.
404 */
4a8a4322 405static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv,
c2acea8e 406 struct iwl_device_cmd *cmd,
e039fa4a 407 struct ieee80211_tx_info *info,
e52119c5 408 struct ieee80211_hdr *hdr, u8 std_id)
b481de9c 409{
e52119c5
WT
410 struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
411 __le32 tx_flags = tx->tx_flags;
fd7c8a40 412 __le16 fc = hdr->frame_control;
e6a9854b 413 u8 rc_flags = info->control.rates[0].flags;
b481de9c 414
e52119c5 415 tx->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e039fa4a 416 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
b481de9c 417 tx_flags |= TX_CMD_FLG_ACK_MSK;
fd7c8a40 418 if (ieee80211_is_mgmt(fc))
b481de9c 419 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
fd7c8a40 420 if (ieee80211_is_probe_resp(fc) &&
b481de9c
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421 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
422 tx_flags |= TX_CMD_FLG_TSF_MSK;
423 } else {
424 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
425 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
426 }
427
e52119c5 428 tx->sta_id = std_id;
8b7b1e05 429 if (ieee80211_has_morefrags(fc))
b481de9c
ZY
430 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
431
fd7c8a40
HH
432 if (ieee80211_is_data_qos(fc)) {
433 u8 *qc = ieee80211_get_qos_ctl(hdr);
e52119c5 434 tx->tid_tspec = qc[0] & 0xf;
b481de9c 435 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 436 } else {
b481de9c 437 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 438 }
b481de9c 439
e6a9854b 440 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
b481de9c
ZY
441 tx_flags |= TX_CMD_FLG_RTS_MSK;
442 tx_flags &= ~TX_CMD_FLG_CTS_MSK;
e6a9854b 443 } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
b481de9c
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444 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
445 tx_flags |= TX_CMD_FLG_CTS_MSK;
446 }
447
448 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
449 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
450
451 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
fd7c8a40
HH
452 if (ieee80211_is_mgmt(fc)) {
453 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
e52119c5 454 tx->timeout.pm_frame_timeout = cpu_to_le16(3);
b481de9c 455 else
e52119c5 456 tx->timeout.pm_frame_timeout = cpu_to_le16(2);
ab53d8af 457 } else {
e52119c5 458 tx->timeout.pm_frame_timeout = 0;
5c8df2d5 459#ifdef CONFIG_IWLWIFI_LEDS
ab53d8af
MA
460 priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
461#endif
462 }
b481de9c 463
e52119c5
WT
464 tx->driver_txop = 0;
465 tx->tx_flags = tx_flags;
466 tx->next_frame_len = 0;
b481de9c
ZY
467}
468
b481de9c
ZY
469/*
470 * start REPLY_TX command process
471 */
4a8a4322 472static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
b481de9c
ZY
473{
474 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
e039fa4a 475 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
e52119c5 476 struct iwl3945_tx_cmd *tx;
188cf6c7 477 struct iwl_tx_queue *txq = NULL;
d20b3c65 478 struct iwl_queue *q = NULL;
c2acea8e
JB
479 struct iwl_device_cmd *out_cmd;
480 struct iwl_cmd_meta *out_meta;
b481de9c
ZY
481 dma_addr_t phys_addr;
482 dma_addr_t txcmd_phys;
e52119c5 483 int txq_id = skb_get_queue_mapping(skb);
df833b1d 484 u16 len, idx, len_org, hdr_len; /* TODO: len_org is not used */
54dbb525
TW
485 u8 id;
486 u8 unicast;
b481de9c 487 u8 sta_id;
54dbb525 488 u8 tid = 0;
b481de9c 489 u16 seq_number = 0;
fd7c8a40 490 __le16 fc;
b481de9c 491 u8 wait_write_ptr = 0;
54dbb525 492 u8 *qc = NULL;
b481de9c
ZY
493 unsigned long flags;
494 int rc;
495
496 spin_lock_irqsave(&priv->lock, flags);
775a6e27 497 if (iwl_is_rfkill(priv)) {
e1623446 498 IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
b481de9c
ZY
499 goto drop_unlock;
500 }
501
e039fa4a 502 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
15b1687c 503 IWL_ERR(priv, "ERROR: No TX rate available.\n");
b481de9c
ZY
504 goto drop_unlock;
505 }
506
507 unicast = !is_multicast_ether_addr(hdr->addr1);
508 id = 0;
509
fd7c8a40 510 fc = hdr->frame_control;
b481de9c 511
d08853a3 512#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c 513 if (ieee80211_is_auth(fc))
e1623446 514 IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
fd7c8a40 515 else if (ieee80211_is_assoc_req(fc))
e1623446 516 IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
fd7c8a40 517 else if (ieee80211_is_reassoc_req(fc))
e1623446 518 IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
b481de9c
ZY
519#endif
520
7878a5a4 521 /* drop all data frame if we are not associated */
914233d6 522 if (ieee80211_is_data(fc) &&
279b05d4 523 (!iwl_is_monitor_mode(priv)) && /* packet injection */
8ccde88a 524 (!iwl_is_associated(priv) ||
05c914fe 525 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
e1623446 526 IWL_DEBUG_DROP(priv, "Dropping - !iwl_is_associated\n");
b481de9c
ZY
527 goto drop_unlock;
528 }
529
530 spin_unlock_irqrestore(&priv->lock, flags);
531
7294ec95 532 hdr_len = ieee80211_hdrlen(fc);
6440adb5
CB
533
534 /* Find (or create) index into station table for destination station */
f5d30266 535 sta_id = iwl_get_sta_id(priv, hdr);
b481de9c 536 if (sta_id == IWL_INVALID_STATION) {
e1623446 537 IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
e174961c 538 hdr->addr1);
b481de9c
ZY
539 goto drop;
540 }
541
e1623446 542 IWL_DEBUG_RATE(priv, "station Id %d\n", sta_id);
b481de9c 543
fd7c8a40
HH
544 if (ieee80211_is_data_qos(fc)) {
545 qc = ieee80211_get_qos_ctl(hdr);
7294ec95 546 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
c587de0b 547 seq_number = priv->stations[sta_id].tid[tid].seq_number &
b481de9c
ZY
548 IEEE80211_SCTL_SEQ;
549 hdr->seq_ctrl = cpu_to_le16(seq_number) |
550 (hdr->seq_ctrl &
c1b4aa3f 551 cpu_to_le16(IEEE80211_SCTL_FRAG));
b481de9c
ZY
552 seq_number += 0x10;
553 }
6440adb5
CB
554
555 /* Descriptor for chosen Tx queue */
188cf6c7 556 txq = &priv->txq[txq_id];
b481de9c
ZY
557 q = &txq->q;
558
559 spin_lock_irqsave(&priv->lock, flags);
560
fc4b6853 561 idx = get_cmd_index(q, q->write_ptr, 0);
b481de9c 562
6440adb5 563 /* Set up driver data for this TFD */
dbb6654c 564 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
fc4b6853 565 txq->txb[q->write_ptr].skb[0] = skb;
6440adb5
CB
566
567 /* Init first empty entry in queue's array of Tx/cmd buffers */
188cf6c7 568 out_cmd = txq->cmd[idx];
c2acea8e 569 out_meta = &txq->meta[idx];
e52119c5 570 tx = (struct iwl3945_tx_cmd *)out_cmd->cmd.payload;
b481de9c 571 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
e52119c5 572 memset(tx, 0, sizeof(*tx));
6440adb5
CB
573
574 /*
575 * Set up the Tx-command (not MAC!) header.
576 * Store the chosen Tx queue and TFD index within the sequence field;
577 * after Tx, uCode's Tx response will return this value so driver can
578 * locate the frame within the tx queue and do post-tx processing.
579 */
b481de9c
ZY
580 out_cmd->hdr.cmd = REPLY_TX;
581 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
fc4b6853 582 INDEX_TO_SEQ(q->write_ptr)));
6440adb5
CB
583
584 /* Copy MAC header from skb into command buffer */
e52119c5 585 memcpy(tx->hdr, hdr, hdr_len);
b481de9c 586
df833b1d
RC
587
588 if (info->control.hw_key)
589 iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, sta_id);
590
591 /* TODO need this for burst mode later on */
592 iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, sta_id);
593
594 /* set is_hcca to 0; it probably will never be implemented */
595 iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
596
597 /* Total # bytes to be transmitted */
598 len = (u16)skb->len;
599 tx->len = cpu_to_le16(len);
600
601
602 tx->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
603 tx->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
604
605 if (!ieee80211_has_morefrags(hdr->frame_control)) {
606 txq->need_update = 1;
607 if (qc)
c587de0b 608 priv->stations[sta_id].tid[tid].seq_number = seq_number;
df833b1d
RC
609 } else {
610 wait_write_ptr = 1;
611 txq->need_update = 0;
612 }
613
614 IWL_DEBUG_TX(priv, "sequence nr = 0X%x \n",
615 le16_to_cpu(out_cmd->hdr.sequence));
616 IWL_DEBUG_TX(priv, "tx_flags = 0X%x \n", le32_to_cpu(tx->tx_flags));
3d816c77
RC
617 iwl_print_hex_dump(priv, IWL_DL_TX, tx, sizeof(*tx));
618 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx->hdr,
df833b1d
RC
619 ieee80211_hdrlen(fc));
620
6440adb5
CB
621 /*
622 * Use the first empty entry in this queue's command buffer array
623 * to contain the Tx command and MAC header concatenated together
624 * (payload data will be in another buffer).
625 * Size of this varies, due to varying MAC header length.
626 * If end is not dword aligned, we'll have 2 extra bytes at the end
627 * of the MAC header (device reads on dword boundaries).
628 * We'll tell device about this padding later.
629 */
3832ec9d 630 len = sizeof(struct iwl3945_tx_cmd) +
4c897253 631 sizeof(struct iwl_cmd_header) + hdr_len;
b481de9c
ZY
632
633 len_org = len;
634 len = (len + 3) & ~3;
635
636 if (len_org != len)
637 len_org = 1;
638 else
639 len_org = 0;
640
6440adb5
CB
641 /* Physical address of this Tx command's header (not MAC header!),
642 * within command buffer array. */
df833b1d
RC
643 txcmd_phys = pci_map_single(priv->pci_dev, &out_cmd->hdr,
644 len, PCI_DMA_TODEVICE);
645 /* we do not map meta data ... so we can safely access address to
646 * provide to unmap command*/
c2acea8e
JB
647 pci_unmap_addr_set(out_meta, mapping, txcmd_phys);
648 pci_unmap_len_set(out_meta, len, len);
b481de9c 649
6440adb5
CB
650 /* Add buffer containing Tx command and MAC(!) header to TFD's
651 * first entry */
7aaa1d79
SO
652 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
653 txcmd_phys, len, 1, 0);
b481de9c 654
b481de9c 655
6440adb5
CB
656 /* Set up TFD's 2nd entry to point directly to remainder of skb,
657 * if any (802.11 null frames have no payload). */
b481de9c
ZY
658 len = skb->len - hdr_len;
659 if (len) {
660 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
661 len, PCI_DMA_TODEVICE);
7aaa1d79
SO
662 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
663 phys_addr, len,
664 0, U32_PAD(len));
b481de9c
ZY
665 }
666
b481de9c 667
6440adb5 668 /* Tell device the write index *just past* this latest filled TFD */
c54b679d 669 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
4f3602c8 670 rc = iwl_txq_update_write_ptr(priv, txq);
b481de9c
ZY
671 spin_unlock_irqrestore(&priv->lock, flags);
672
673 if (rc)
674 return rc;
675
d20b3c65 676 if ((iwl_queue_space(q) < q->high_mark)
b481de9c
ZY
677 && priv->mac80211_registered) {
678 if (wait_write_ptr) {
679 spin_lock_irqsave(&priv->lock, flags);
680 txq->need_update = 1;
4f3602c8 681 iwl_txq_update_write_ptr(priv, txq);
b481de9c
ZY
682 spin_unlock_irqrestore(&priv->lock, flags);
683 }
684
e4e72fb4 685 iwl_stop_queue(priv, skb_get_queue_mapping(skb));
b481de9c
ZY
686 }
687
688 return 0;
689
690drop_unlock:
691 spin_unlock_irqrestore(&priv->lock, flags);
692drop:
693 return -1;
694}
695
c8b0e6e1 696#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY
697
698#include "iwl-spectrum.h"
699
700#define BEACON_TIME_MASK_LOW 0x00FFFFFF
701#define BEACON_TIME_MASK_HIGH 0xFF000000
702#define TIME_UNIT 1024
703
704/*
705 * extended beacon time format
706 * time in usec will be changed into a 32-bit value in 8:24 format
707 * the high 1 byte is the beacon counts
708 * the lower 3 bytes is the time in usec within one beacon interval
709 */
710
bb8c093b 711static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
b481de9c
ZY
712{
713 u32 quot;
714 u32 rem;
715 u32 interval = beacon_interval * 1024;
716
717 if (!interval || !usec)
718 return 0;
719
720 quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
721 rem = (usec % interval) & BEACON_TIME_MASK_LOW;
722
723 return (quot << 24) + rem;
724}
725
726/* base is usually what we get from ucode with each received frame,
727 * the same as HW timer counter counting down
728 */
729
bb8c093b 730static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
b481de9c
ZY
731{
732 u32 base_low = base & BEACON_TIME_MASK_LOW;
733 u32 addon_low = addon & BEACON_TIME_MASK_LOW;
734 u32 interval = beacon_interval * TIME_UNIT;
735 u32 res = (base & BEACON_TIME_MASK_HIGH) +
736 (addon & BEACON_TIME_MASK_HIGH);
737
738 if (base_low > addon_low)
739 res += base_low - addon_low;
740 else if (base_low < addon_low) {
741 res += interval + base_low - addon_low;
742 res += (1 << 24);
743 } else
744 res += (1 << 24);
745
746 return cpu_to_le32(res);
747}
748
4a8a4322 749static int iwl3945_get_measurement(struct iwl_priv *priv,
b481de9c
ZY
750 struct ieee80211_measurement_params *params,
751 u8 type)
752{
600c0e11 753 struct iwl_spectrum_cmd spectrum;
3d24a9f7 754 struct iwl_rx_packet *res;
c2d79b48 755 struct iwl_host_cmd cmd = {
b481de9c
ZY
756 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
757 .data = (void *)&spectrum,
c2acea8e 758 .flags = CMD_WANT_SKB,
b481de9c
ZY
759 };
760 u32 add_time = le64_to_cpu(params->start_time);
761 int rc;
762 int spectrum_resp_status;
763 int duration = le16_to_cpu(params->duration);
764
8ccde88a 765 if (iwl_is_associated(priv))
b481de9c 766 add_time =
bb8c093b 767 iwl3945_usecs_to_beacons(
b481de9c
ZY
768 le64_to_cpu(params->start_time) - priv->last_tsf,
769 le16_to_cpu(priv->rxon_timing.beacon_interval));
770
771 memset(&spectrum, 0, sizeof(spectrum));
772
773 spectrum.channel_count = cpu_to_le16(1);
774 spectrum.flags =
775 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
776 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
777 cmd.len = sizeof(spectrum);
778 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
779
8ccde88a 780 if (iwl_is_associated(priv))
b481de9c 781 spectrum.start_time =
bb8c093b 782 iwl3945_add_beacon_time(priv->last_beacon_time,
b481de9c
ZY
783 add_time,
784 le16_to_cpu(priv->rxon_timing.beacon_interval));
785 else
786 spectrum.start_time = 0;
787
788 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
789 spectrum.channels[0].channel = params->channel;
790 spectrum.channels[0].type = type;
8ccde88a 791 if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
b481de9c
ZY
792 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
793 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
794
518099a8 795 rc = iwl_send_cmd_sync(priv, &cmd);
b481de9c
ZY
796 if (rc)
797 return rc;
798
c2acea8e 799 res = (struct iwl_rx_packet *)cmd.reply_skb->data;
b481de9c 800 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
15b1687c 801 IWL_ERR(priv, "Bad return from REPLY_RX_ON_ASSOC command\n");
b481de9c
ZY
802 rc = -EIO;
803 }
804
805 spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
806 switch (spectrum_resp_status) {
807 case 0: /* Command will be handled */
808 if (res->u.spectrum.id != 0xff) {
e1623446 809 IWL_DEBUG_INFO(priv, "Replaced existing measurement: %d\n",
bc434dd2 810 res->u.spectrum.id);
b481de9c
ZY
811 priv->measurement_status &= ~MEASUREMENT_READY;
812 }
813 priv->measurement_status |= MEASUREMENT_ACTIVE;
814 rc = 0;
815 break;
816
817 case 1: /* Command will not be handled */
818 rc = -EAGAIN;
819 break;
820 }
821
c2acea8e 822 dev_kfree_skb_any(cmd.reply_skb);
b481de9c
ZY
823
824 return rc;
825}
826#endif
827
4a8a4322 828static void iwl3945_rx_reply_alive(struct iwl_priv *priv,
6100b588 829 struct iwl_rx_mem_buffer *rxb)
b481de9c 830{
3d24a9f7
TW
831 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
832 struct iwl_alive_resp *palive;
b481de9c
ZY
833 struct delayed_work *pwork;
834
835 palive = &pkt->u.alive_frame;
836
e1623446 837 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY
838 "0x%01X 0x%01X\n",
839 palive->is_valid, palive->ver_type,
840 palive->ver_subtype);
841
842 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 843 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
3d24a9f7
TW
844 memcpy(&priv->card_alive_init, &pkt->u.alive_frame,
845 sizeof(struct iwl_alive_resp));
b481de9c
ZY
846 pwork = &priv->init_alive_start;
847 } else {
e1623446 848 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 849 memcpy(&priv->card_alive, &pkt->u.alive_frame,
3d24a9f7 850 sizeof(struct iwl_alive_resp));
b481de9c 851 pwork = &priv->alive_start;
bb8c093b 852 iwl3945_disable_events(priv);
b481de9c
ZY
853 }
854
855 /* We delay the ALIVE response by 5ms to
856 * give the HW RF Kill time to activate... */
857 if (palive->is_valid == UCODE_VALID_OK)
858 queue_delayed_work(priv->workqueue, pwork,
859 msecs_to_jiffies(5));
860 else
39aadf8c 861 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY
862}
863
4a8a4322 864static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv,
6100b588 865 struct iwl_rx_mem_buffer *rxb)
b481de9c 866{
c7e035a9 867#ifdef CONFIG_IWLWIFI_DEBUG
3d24a9f7 868 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
c7e035a9 869#endif
b481de9c 870
e1623446 871 IWL_DEBUG_RX(priv, "Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
b481de9c
ZY
872 return;
873}
874
bb8c093b 875static void iwl3945_bg_beacon_update(struct work_struct *work)
b481de9c 876{
4a8a4322
AK
877 struct iwl_priv *priv =
878 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY
879 struct sk_buff *beacon;
880
881 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 882 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY
883
884 if (!beacon) {
15b1687c 885 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY
886 return;
887 }
888
889 mutex_lock(&priv->mutex);
890 /* new beacon skb is allocated every time; dispose previous.*/
891 if (priv->ibss_beacon)
892 dev_kfree_skb(priv->ibss_beacon);
893
894 priv->ibss_beacon = beacon;
895 mutex_unlock(&priv->mutex);
896
bb8c093b 897 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
898}
899
4a8a4322 900static void iwl3945_rx_beacon_notif(struct iwl_priv *priv,
6100b588 901 struct iwl_rx_mem_buffer *rxb)
b481de9c 902{
d08853a3 903#ifdef CONFIG_IWLWIFI_DEBUG
3d24a9f7 904 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
bb8c093b 905 struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
b481de9c
ZY
906 u8 rate = beacon->beacon_notify_hdr.rate;
907
e1623446 908 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c
ZY
909 "tsf %d %d rate %d\n",
910 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
911 beacon->beacon_notify_hdr.failure_frame,
912 le32_to_cpu(beacon->ibss_mgr_status),
913 le32_to_cpu(beacon->high_tsf),
914 le32_to_cpu(beacon->low_tsf), rate);
915#endif
916
05c914fe 917 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY
918 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
919 queue_work(priv->workqueue, &priv->beacon_update);
920}
921
b481de9c
ZY
922/* Handle notification from uCode that card's power state is changing
923 * due to software, hardware, or critical temperature RFKILL */
4a8a4322 924static void iwl3945_rx_card_state_notif(struct iwl_priv *priv,
6100b588 925 struct iwl_rx_mem_buffer *rxb)
b481de9c 926{
3d24a9f7 927 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY
928 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
929 unsigned long status = priv->status;
930
4c423a2b 931 IWL_WARN(priv, "Card state received: HW:%s SW:%s\n",
b481de9c
ZY
932 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
933 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
934
5d49f498 935 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
936 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
937
938 if (flags & HW_CARD_DISABLED)
939 set_bit(STATUS_RF_KILL_HW, &priv->status);
940 else
941 clear_bit(STATUS_RF_KILL_HW, &priv->status);
942
943
af0053d6 944 iwl_scan_cancel(priv);
b481de9c
ZY
945
946 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB
947 test_bit(STATUS_RF_KILL_HW, &priv->status)))
948 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
949 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY
950 else
951 wake_up_interruptible(&priv->wait_command_queue);
952}
953
954/**
bb8c093b 955 * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY
956 *
957 * Setup the RX handlers for each of the reply types sent from the uCode
958 * to the host.
959 *
960 * This function chains into the hardware specific files for them to setup
961 * any hardware specific handlers as well.
962 */
4a8a4322 963static void iwl3945_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 964{
bb8c093b
CH
965 priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
966 priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
261b9c33 967 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
8ccde88a 968 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
030f05ed 969 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 970 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
030f05ed 971 iwl_rx_pm_debug_statistics_notif;
bb8c093b 972 priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
b481de9c 973
9fbab516
BC
974 /*
975 * The same handler is used for both the REPLY to a discrete
976 * statistics request from the host as well as for the periodic
977 * statistics notifications (after received beacons) from the uCode.
b481de9c 978 */
bb8c093b
CH
979 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
980 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
b481de9c 981
261b9c33 982 iwl_setup_spectrum_handlers(priv);
cade0eb2 983 iwl_setup_rx_scan_handlers(priv);
bb8c093b 984 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
b481de9c 985
9fbab516 986 /* Set up hardware specific Rx handlers */
bb8c093b 987 iwl3945_hw_rx_handler_setup(priv);
b481de9c
ZY
988}
989
b481de9c
ZY
990/************************** RX-FUNCTIONS ****************************/
991/*
992 * Rx theory of operation
993 *
994 * The host allocates 32 DMA target addresses and passes the host address
995 * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
996 * 0 to 31
997 *
998 * Rx Queue Indexes
999 * The host/firmware share two index registers for managing the Rx buffers.
1000 *
1001 * The READ index maps to the first position that the firmware may be writing
1002 * to -- the driver can read up to (but not including) this position and get
1003 * good data.
1004 * The READ index is managed by the firmware once the card is enabled.
1005 *
1006 * The WRITE index maps to the last position the driver has read from -- the
1007 * position preceding WRITE is the last slot the firmware can place a packet.
1008 *
1009 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
1010 * WRITE = READ.
1011 *
9fbab516 1012 * During initialization, the host sets up the READ queue position to the first
b481de9c
ZY
1013 * INDEX position, and WRITE to the last (READ - 1 wrapped)
1014 *
9fbab516 1015 * When the firmware places a packet in a buffer, it will advance the READ index
b481de9c
ZY
1016 * and fire the RX interrupt. The driver can then query the READ index and
1017 * process as many packets as possible, moving the WRITE index forward as it
1018 * resets the Rx queue buffers with new memory.
1019 *
1020 * The management in the driver is as follows:
1021 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
1022 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
01ebd063 1023 * to replenish the iwl->rxq->rx_free.
bb8c093b 1024 * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
b481de9c
ZY
1025 * iwl->rxq is replenished and the READ INDEX is updated (updating the
1026 * 'processed' and 'read' driver indexes as well)
1027 * + A received packet is processed and handed to the kernel network stack,
1028 * detached from the iwl->rxq. The driver 'processed' index is updated.
1029 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
1030 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
1031 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
1032 * were enough free buffers and RX_STALLED is set it is cleared.
1033 *
1034 *
1035 * Driver sequence:
1036 *
9fbab516 1037 * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
bb8c093b 1038 * iwl3945_rx_queue_restock
9fbab516 1039 * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
b481de9c
ZY
1040 * queue, updates firmware pointers, and updates
1041 * the WRITE index. If insufficient rx_free buffers
bb8c093b 1042 * are available, schedules iwl3945_rx_replenish
b481de9c
ZY
1043 *
1044 * -- enable interrupts --
6100b588 1045 * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the
b481de9c
ZY
1046 * READ INDEX, detaching the SKB from the pool.
1047 * Moves the packet buffer from queue to rx_used.
bb8c093b 1048 * Calls iwl3945_rx_queue_restock to refill any empty
b481de9c
ZY
1049 * slots.
1050 * ...
1051 *
1052 */
1053
b481de9c 1054/**
9fbab516 1055 * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
b481de9c 1056 */
4a8a4322 1057static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv,
b481de9c
ZY
1058 dma_addr_t dma_addr)
1059{
1060 return cpu_to_le32((u32)dma_addr);
1061}
1062
1063/**
bb8c093b 1064 * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
b481de9c 1065 *
9fbab516 1066 * If there are slots in the RX queue that need to be restocked,
b481de9c 1067 * and we have free pre-allocated buffers, fill the ranks as much
9fbab516 1068 * as we can, pulling from rx_free.
b481de9c
ZY
1069 *
1070 * This moves the 'write' index forward to catch up with 'processed', and
1071 * also updates the memory address in the firmware to reference the new
1072 * target buffer.
1073 */
4a8a4322 1074static int iwl3945_rx_queue_restock(struct iwl_priv *priv)
b481de9c 1075{
cc2f362c 1076 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c 1077 struct list_head *element;
6100b588 1078 struct iwl_rx_mem_buffer *rxb;
b481de9c
ZY
1079 unsigned long flags;
1080 int write, rc;
1081
1082 spin_lock_irqsave(&rxq->lock, flags);
1083 write = rxq->write & ~0x7;
37d68317 1084 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
6440adb5 1085 /* Get next free Rx buffer, remove from free list */
b481de9c 1086 element = rxq->rx_free.next;
6100b588 1087 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
b481de9c 1088 list_del(element);
6440adb5
CB
1089
1090 /* Point to Rx buffer via next RBD in circular buffer */
6100b588 1091 rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->real_dma_addr);
b481de9c
ZY
1092 rxq->queue[rxq->write] = rxb;
1093 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
1094 rxq->free_count--;
1095 }
1096 spin_unlock_irqrestore(&rxq->lock, flags);
1097 /* If the pre-allocated buffer pool is dropping low, schedule to
1098 * refill it */
1099 if (rxq->free_count <= RX_LOW_WATERMARK)
1100 queue_work(priv->workqueue, &priv->rx_replenish);
1101
1102
6440adb5
CB
1103 /* If we've added more space for the firmware to place data, tell it.
1104 * Increment device's write pointer in multiples of 8. */
d14d4440 1105 if ((rxq->write_actual != (rxq->write & ~0x7))
b481de9c
ZY
1106 || (abs(rxq->write - rxq->read) > 7)) {
1107 spin_lock_irqsave(&rxq->lock, flags);
1108 rxq->need_update = 1;
1109 spin_unlock_irqrestore(&rxq->lock, flags);
141c43a3 1110 rc = iwl_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY
1111 if (rc)
1112 return rc;
1113 }
1114
1115 return 0;
1116}
1117
1118/**
bb8c093b 1119 * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
b481de9c
ZY
1120 *
1121 * When moving to rx_free an SKB is allocated for the slot.
1122 *
bb8c093b 1123 * Also restock the Rx queue via iwl3945_rx_queue_restock.
01ebd063 1124 * This is called as a scheduled work item (except for during initialization)
b481de9c 1125 */
d14d4440 1126static void iwl3945_rx_allocate(struct iwl_priv *priv, gfp_t priority)
b481de9c 1127{
cc2f362c 1128 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c 1129 struct list_head *element;
6100b588 1130 struct iwl_rx_mem_buffer *rxb;
b481de9c 1131 unsigned long flags;
72240498
AK
1132
1133 while (1) {
1134 spin_lock_irqsave(&rxq->lock, flags);
1135
1136 if (list_empty(&rxq->rx_used)) {
1137 spin_unlock_irqrestore(&rxq->lock, flags);
1138 return;
1139 }
1140
b481de9c 1141 element = rxq->rx_used.next;
6100b588 1142 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
72240498
AK
1143 list_del(element);
1144 spin_unlock_irqrestore(&rxq->lock, flags);
6440adb5
CB
1145
1146 /* Alloc a new receive buffer */
b481de9c 1147 rxb->skb =
1e33dc64 1148 alloc_skb(priv->hw_params.rx_buf_size,
d14d4440 1149 priority);
b481de9c
ZY
1150 if (!rxb->skb) {
1151 if (net_ratelimit())
978785a3 1152 IWL_CRIT(priv, ": Can not allocate SKB buffers\n");
b481de9c
ZY
1153 /* We don't reschedule replenish work here -- we will
1154 * call the restock method and if it still needs
1155 * more buffers it will schedule replenish */
1156 break;
1157 }
12342c47
ZY
1158
1159 /* If radiotap head is required, reserve some headroom here.
1160 * The physical head count is a variable rx_stats->phy_count.
1161 * We reserve 4 bytes here. Plus these extra bytes, the
1162 * headroom of the physical head should be enough for the
1163 * radiotap head that iwl3945 supported. See iwl3945_rt.
1164 */
1165 skb_reserve(rxb->skb, 4);
1166
6440adb5 1167 /* Get physical address of RB/SKB */
1e33dc64
WT
1168 rxb->real_dma_addr = pci_map_single(priv->pci_dev,
1169 rxb->skb->data,
1170 priv->hw_params.rx_buf_size,
1171 PCI_DMA_FROMDEVICE);
72240498
AK
1172
1173 spin_lock_irqsave(&rxq->lock, flags);
b481de9c 1174 list_add_tail(&rxb->list, &rxq->rx_free);
72240498 1175 priv->alloc_rxb_skb++;
b481de9c 1176 rxq->free_count++;
72240498 1177 spin_unlock_irqrestore(&rxq->lock, flags);
b481de9c 1178 }
5c0eef96
MA
1179}
1180
df833b1d
RC
1181void iwl3945_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
1182{
1183 unsigned long flags;
1184 int i;
1185 spin_lock_irqsave(&rxq->lock, flags);
1186 INIT_LIST_HEAD(&rxq->rx_free);
1187 INIT_LIST_HEAD(&rxq->rx_used);
1188 /* Fill the rx_used queue with _all_ of the Rx buffers */
1189 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
1190 /* In the reset function, these buffers may have been allocated
1191 * to an SKB, so we need to unmap and free potential storage */
1192 if (rxq->pool[i].skb != NULL) {
1193 pci_unmap_single(priv->pci_dev,
1194 rxq->pool[i].real_dma_addr,
1195 priv->hw_params.rx_buf_size,
1196 PCI_DMA_FROMDEVICE);
1197 priv->alloc_rxb_skb--;
1198 dev_kfree_skb(rxq->pool[i].skb);
1199 rxq->pool[i].skb = NULL;
1200 }
1201 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
1202 }
1203
1204 /* Set us so that we have processed and used all buffers, but have
1205 * not restocked the Rx queue with fresh buffers */
1206 rxq->read = rxq->write = 0;
1207 rxq->free_count = 0;
d14d4440 1208 rxq->write_actual = 0;
df833b1d
RC
1209 spin_unlock_irqrestore(&rxq->lock, flags);
1210}
df833b1d 1211
5c0eef96
MA
1212void iwl3945_rx_replenish(void *data)
1213{
4a8a4322 1214 struct iwl_priv *priv = data;
5c0eef96
MA
1215 unsigned long flags;
1216
d14d4440 1217 iwl3945_rx_allocate(priv, GFP_KERNEL);
b481de9c
ZY
1218
1219 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 1220 iwl3945_rx_queue_restock(priv);
b481de9c
ZY
1221 spin_unlock_irqrestore(&priv->lock, flags);
1222}
1223
d14d4440
AK
1224static void iwl3945_rx_replenish_now(struct iwl_priv *priv)
1225{
1226 iwl3945_rx_allocate(priv, GFP_ATOMIC);
1227
1228 iwl3945_rx_queue_restock(priv);
1229}
1230
1231
df833b1d
RC
1232/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
1233 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
1234 * This free routine walks the list of POOL entries and if SKB is set to
1235 * non NULL it is unmapped and freed
1236 */
1237static void iwl3945_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
1238{
1239 int i;
1240 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
1241 if (rxq->pool[i].skb != NULL) {
1242 pci_unmap_single(priv->pci_dev,
1243 rxq->pool[i].real_dma_addr,
1244 priv->hw_params.rx_buf_size,
1245 PCI_DMA_FROMDEVICE);
1246 dev_kfree_skb(rxq->pool[i].skb);
1247 }
1248 }
1249
1250 pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
1251 rxq->dma_addr);
1252 pci_free_consistent(priv->pci_dev, sizeof(struct iwl_rb_status),
1253 rxq->rb_stts, rxq->rb_stts_dma);
1254 rxq->bd = NULL;
1255 rxq->rb_stts = NULL;
1256}
df833b1d
RC
1257
1258
b481de9c
ZY
1259/* Convert linear signal-to-noise ratio into dB */
1260static u8 ratio2dB[100] = {
1261/* 0 1 2 3 4 5 6 7 8 9 */
1262 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
1263 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
1264 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
1265 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
1266 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
1267 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
1268 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
1269 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
1270 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
1271 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
1272};
1273
1274/* Calculates a relative dB value from a ratio of linear
1275 * (i.e. not dB) signal levels.
1276 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
bb8c093b 1277int iwl3945_calc_db_from_ratio(int sig_ratio)
b481de9c 1278{
221c80cf
AB
1279 /* 1000:1 or higher just report as 60 dB */
1280 if (sig_ratio >= 1000)
b481de9c
ZY
1281 return 60;
1282
221c80cf 1283 /* 100:1 or higher, divide by 10 and use table,
b481de9c 1284 * add 20 dB to make up for divide by 10 */
221c80cf 1285 if (sig_ratio >= 100)
3ac7f146 1286 return 20 + (int)ratio2dB[sig_ratio/10];
b481de9c
ZY
1287
1288 /* We shouldn't see this */
1289 if (sig_ratio < 1)
1290 return 0;
1291
1292 /* Use table for ratios 1:1 - 99:1 */
1293 return (int)ratio2dB[sig_ratio];
1294}
1295
1296#define PERFECT_RSSI (-20) /* dBm */
1297#define WORST_RSSI (-95) /* dBm */
1298#define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
1299
1300/* Calculate an indication of rx signal quality (a percentage, not dBm!).
1301 * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
1302 * about formulas used below. */
bb8c093b 1303int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
b481de9c
ZY
1304{
1305 int sig_qual;
1306 int degradation = PERFECT_RSSI - rssi_dbm;
1307
1308 /* If we get a noise measurement, use signal-to-noise ratio (SNR)
1309 * as indicator; formula is (signal dbm - noise dbm).
1310 * SNR at or above 40 is a great signal (100%).
1311 * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
1312 * Weakest usable signal is usually 10 - 15 dB SNR. */
1313 if (noise_dbm) {
1314 if (rssi_dbm - noise_dbm >= 40)
1315 return 100;
1316 else if (rssi_dbm < noise_dbm)
1317 return 0;
1318 sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
1319
1320 /* Else use just the signal level.
1321 * This formula is a least squares fit of data points collected and
1322 * compared with a reference system that had a percentage (%) display
1323 * for signal quality. */
1324 } else
1325 sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
1326 (15 * RSSI_RANGE + 62 * degradation)) /
1327 (RSSI_RANGE * RSSI_RANGE);
1328
1329 if (sig_qual > 100)
1330 sig_qual = 100;
1331 else if (sig_qual < 1)
1332 sig_qual = 0;
1333
1334 return sig_qual;
1335}
1336
1337/**
9fbab516 1338 * iwl3945_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
1339 *
1340 * Uses the priv->rx_handlers callback function array to invoke
1341 * the appropriate handlers, including command responses,
1342 * frame-received notifications, and other notifications.
1343 */
4a8a4322 1344static void iwl3945_rx_handle(struct iwl_priv *priv)
b481de9c 1345{
6100b588 1346 struct iwl_rx_mem_buffer *rxb;
3d24a9f7 1347 struct iwl_rx_packet *pkt;
cc2f362c 1348 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
1349 u32 r, i;
1350 int reclaim;
1351 unsigned long flags;
5c0eef96 1352 u8 fill_rx = 0;
d68ab680 1353 u32 count = 8;
d14d4440 1354 int total_empty = 0;
b481de9c 1355
6440adb5
CB
1356 /* uCode's read index (stored in shared DRAM) indicates the last Rx
1357 * buffer that the driver may process (last buffer filled by ucode). */
8cd812bc 1358 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY
1359 i = rxq->read;
1360
d14d4440
AK
1361 /* calculate total frames need to be restock after handling RX */
1362 total_empty = r - priv->rxq.write_actual;
1363 if (total_empty < 0)
1364 total_empty += RX_QUEUE_SIZE;
1365
1366 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96 1367 fill_rx = 1;
b481de9c
ZY
1368 /* Rx interrupt, but nothing sent from uCode */
1369 if (i == r)
e1623446 1370 IWL_DEBUG(priv, IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
b481de9c
ZY
1371
1372 while (i != r) {
1373 rxb = rxq->queue[i];
1374
9fbab516 1375 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
1376 * then a bug has been introduced in the queue refilling
1377 * routines -- catch it here */
1378 BUG_ON(rxb == NULL);
1379
1380 rxq->queue[i] = NULL;
1381
df833b1d
RC
1382 pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
1383 priv->hw_params.rx_buf_size,
1384 PCI_DMA_FROMDEVICE);
3d24a9f7 1385 pkt = (struct iwl_rx_packet *)rxb->skb->data;
b481de9c
ZY
1386
1387 /* Reclaim a command buffer only if this packet is a response
1388 * to a (driver-originated) command.
1389 * If the packet (e.g. Rx frame) originated from uCode,
1390 * there is no command buffer to reclaim.
1391 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1392 * but apparently a few don't get set; catch them here. */
1393 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
1394 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
1395 (pkt->hdr.cmd != REPLY_TX);
1396
1397 /* Based on type of command response or notification,
1398 * handle those that need handling via function in
bb8c093b 1399 * rx_handlers table. See iwl3945_setup_rx_handlers() */
b481de9c 1400 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 1401 IWL_DEBUG(priv, IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR,
b481de9c
ZY
1402 "r = %d, i = %d, %s, 0x%02x\n", r, i,
1403 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
1404 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
86ddbf62 1405 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
b481de9c
ZY
1406 } else {
1407 /* No handling needed */
e1623446 1408 IWL_DEBUG(priv, IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR,
b481de9c
ZY
1409 "r %d i %d No handler needed for %s, 0x%02x\n",
1410 r, i, get_cmd_string(pkt->hdr.cmd),
1411 pkt->hdr.cmd);
1412 }
1413
1414 if (reclaim) {
9fbab516 1415 /* Invoke any callbacks, transfer the skb to caller, and
518099a8 1416 * fire off the (possibly) blocking iwl_send_cmd()
b481de9c
ZY
1417 * as we reclaim the driver command queue */
1418 if (rxb && rxb->skb)
732587ab 1419 iwl_tx_cmd_complete(priv, rxb);
b481de9c 1420 else
39aadf8c 1421 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY
1422 }
1423
1424 /* For now we just don't re-use anything. We can tweak this
1425 * later to try and re-use notification packets and SKBs that
1426 * fail to Rx correctly */
1427 if (rxb->skb != NULL) {
1428 priv->alloc_rxb_skb--;
1429 dev_kfree_skb_any(rxb->skb);
1430 rxb->skb = NULL;
1431 }
1432
b481de9c
ZY
1433 spin_lock_irqsave(&rxq->lock, flags);
1434 list_add_tail(&rxb->list, &priv->rxq.rx_used);
1435 spin_unlock_irqrestore(&rxq->lock, flags);
1436 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
1437 /* If there are a lot of unused frames,
1438 * restock the Rx queue so ucode won't assert. */
1439 if (fill_rx) {
1440 count++;
1441 if (count >= 8) {
1442 priv->rxq.read = i;
d14d4440 1443 iwl3945_rx_replenish_now(priv);
5c0eef96
MA
1444 count = 0;
1445 }
1446 }
b481de9c
ZY
1447 }
1448
1449 /* Backtrack one entry */
1450 priv->rxq.read = i;
d14d4440
AK
1451 if (fill_rx)
1452 iwl3945_rx_replenish_now(priv);
1453 else
1454 iwl3945_rx_queue_restock(priv);
b481de9c
ZY
1455}
1456
0359facc 1457/* call this function to flush any scheduled tasklet */
4a8a4322 1458static inline void iwl_synchronize_irq(struct iwl_priv *priv)
0359facc 1459{
a96a27f9 1460 /* wait to make sure we flush pending tasklet*/
0359facc
MA
1461 synchronize_irq(priv->pci_dev->irq);
1462 tasklet_kill(&priv->irq_tasklet);
1463}
1464
b481de9c
ZY
1465static const char *desc_lookup(int i)
1466{
1467 switch (i) {
1468 case 1:
1469 return "FAIL";
1470 case 2:
1471 return "BAD_PARAM";
1472 case 3:
1473 return "BAD_CHECKSUM";
1474 case 4:
1475 return "NMI_INTERRUPT";
1476 case 5:
1477 return "SYSASSERT";
1478 case 6:
1479 return "FATAL_ERROR";
1480 }
1481
1482 return "UNKNOWN";
1483}
1484
1485#define ERROR_START_OFFSET (1 * sizeof(u32))
1486#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1487
4a8a4322 1488static void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
b481de9c
ZY
1489{
1490 u32 i;
1491 u32 desc, time, count, base, data1;
1492 u32 blink1, blink2, ilink1, ilink2;
b481de9c
ZY
1493
1494 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1495
bb8c093b 1496 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 1497 IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
b481de9c
ZY
1498 return;
1499 }
1500
b481de9c 1501
5d49f498 1502 count = iwl_read_targ_mem(priv, base);
b481de9c
ZY
1503
1504 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
15b1687c
WT
1505 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1506 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1507 priv->status, count);
b481de9c
ZY
1508 }
1509
15b1687c 1510 IWL_ERR(priv, "Desc Time asrtPC blink2 "
b481de9c
ZY
1511 "ilink1 nmiPC Line\n");
1512 for (i = ERROR_START_OFFSET;
1513 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
1514 i += ERROR_ELEM_SIZE) {
5d49f498 1515 desc = iwl_read_targ_mem(priv, base + i);
b481de9c 1516 time =
5d49f498 1517 iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32));
b481de9c 1518 blink1 =
5d49f498 1519 iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32));
b481de9c 1520 blink2 =
5d49f498 1521 iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32));
b481de9c 1522 ilink1 =
5d49f498 1523 iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32));
b481de9c 1524 ilink2 =
5d49f498 1525 iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32));
b481de9c 1526 data1 =
5d49f498 1527 iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32));
b481de9c 1528
15b1687c
WT
1529 IWL_ERR(priv,
1530 "%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
1531 desc_lookup(desc), desc, time, blink1, blink2,
1532 ilink1, ilink2, data1);
b481de9c
ZY
1533 }
1534
b481de9c
ZY
1535}
1536
f58177b9 1537#define EVENT_START_OFFSET (6 * sizeof(u32))
b481de9c
ZY
1538
1539/**
bb8c093b 1540 * iwl3945_print_event_log - Dump error event log to syslog
b481de9c 1541 *
b481de9c 1542 */
4a8a4322 1543static void iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
b481de9c
ZY
1544 u32 num_events, u32 mode)
1545{
1546 u32 i;
1547 u32 base; /* SRAM byte address of event log header */
1548 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1549 u32 ptr; /* SRAM byte address of log data */
1550 u32 ev, time, data; /* event log data */
1551
1552 if (num_events == 0)
1553 return;
1554
1555 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1556
1557 if (mode == 0)
1558 event_size = 2 * sizeof(u32);
1559 else
1560 event_size = 3 * sizeof(u32);
1561
1562 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1563
1564 /* "time" is actually "data" for mode 0 (no timestamp).
1565 * place event id # at far right for easier visual parsing. */
1566 for (i = 0; i < num_events; i++) {
5d49f498 1567 ev = iwl_read_targ_mem(priv, ptr);
b481de9c 1568 ptr += sizeof(u32);
5d49f498 1569 time = iwl_read_targ_mem(priv, ptr);
b481de9c 1570 ptr += sizeof(u32);
15b1687c
WT
1571 if (mode == 0) {
1572 /* data, ev */
1573 IWL_ERR(priv, "0x%08x\t%04u\n", time, ev);
1574 } else {
5d49f498 1575 data = iwl_read_targ_mem(priv, ptr);
b481de9c 1576 ptr += sizeof(u32);
15b1687c 1577 IWL_ERR(priv, "%010u\t0x%08x\t%04u\n", time, data, ev);
b481de9c
ZY
1578 }
1579 }
1580}
1581
4a8a4322 1582static void iwl3945_dump_nic_event_log(struct iwl_priv *priv)
b481de9c 1583{
b481de9c
ZY
1584 u32 base; /* SRAM byte address of event log header */
1585 u32 capacity; /* event log capacity in # entries */
1586 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1587 u32 num_wraps; /* # times uCode wrapped to top of log */
1588 u32 next_entry; /* index of next entry to be written by uCode */
1589 u32 size; /* # entries that we'll print */
1590
1591 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 1592 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 1593 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
b481de9c
ZY
1594 return;
1595 }
1596
b481de9c 1597 /* event log header */
5d49f498
AK
1598 capacity = iwl_read_targ_mem(priv, base);
1599 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1600 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1601 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
b481de9c
ZY
1602
1603 size = num_wraps ? capacity : next_entry;
1604
1605 /* bail out if nothing in log */
1606 if (size == 0) {
15b1687c 1607 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
b481de9c
ZY
1608 return;
1609 }
1610
15b1687c 1611 IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
b481de9c
ZY
1612 size, num_wraps);
1613
1614 /* if uCode has wrapped back to top of log, start at the oldest entry,
1615 * i.e the next one that uCode would fill. */
1616 if (num_wraps)
bb8c093b 1617 iwl3945_print_event_log(priv, next_entry,
b481de9c
ZY
1618 capacity - next_entry, mode);
1619
1620 /* (then/else) start at top of log */
bb8c093b 1621 iwl3945_print_event_log(priv, 0, next_entry, mode);
b481de9c 1622
b481de9c
ZY
1623}
1624
4a8a4322 1625static void iwl3945_irq_tasklet(struct iwl_priv *priv)
b481de9c
ZY
1626{
1627 u32 inta, handled = 0;
1628 u32 inta_fh;
1629 unsigned long flags;
d08853a3 1630#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
1631 u32 inta_mask;
1632#endif
1633
1634 spin_lock_irqsave(&priv->lock, flags);
1635
1636 /* Ack/clear/reset pending uCode interrupts.
1637 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1638 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
5d49f498
AK
1639 inta = iwl_read32(priv, CSR_INT);
1640 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY
1641
1642 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1643 * Any new interrupts that happen after this, either while we're
1644 * in this tasklet, or later, will show up in next ISR/tasklet. */
5d49f498
AK
1645 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1646 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 1647
d08853a3 1648#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1649 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
9fbab516 1650 /* just for debug */
5d49f498 1651 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 1652 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY
1653 inta, inta_mask, inta_fh);
1654 }
1655#endif
1656
1657 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1658 * atomic, make sure that inta covers all the interrupts that
1659 * we've discovered, even if FH interrupt came in just after
1660 * reading CSR_INT. */
6f83eaa1 1661 if (inta_fh & CSR39_FH_INT_RX_MASK)
b481de9c 1662 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 1663 if (inta_fh & CSR39_FH_INT_TX_MASK)
b481de9c
ZY
1664 inta |= CSR_INT_BIT_FH_TX;
1665
1666 /* Now service all interrupt bits discovered above. */
1667 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1668 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY
1669
1670 /* Tell the device to stop sending interrupts */
ed3b932e 1671 iwl_disable_interrupts(priv);
b481de9c 1672
86ddbf62 1673 priv->isr_stats.hw++;
8ccde88a 1674 iwl_irq_handle_error(priv);
b481de9c
ZY
1675
1676 handled |= CSR_INT_BIT_HW_ERR;
1677
1678 spin_unlock_irqrestore(&priv->lock, flags);
1679
1680 return;
1681 }
1682
d08853a3 1683#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1684 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
b481de9c 1685 /* NIC fires this, but we don't use it, redundant with WAKEUP */
86ddbf62 1686 if (inta & CSR_INT_BIT_SCD) {
e1623446 1687 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1688 "the frame/frames.\n");
86ddbf62
AK
1689 priv->isr_stats.sch++;
1690 }
b481de9c
ZY
1691
1692 /* Alive notification via Rx interrupt will do the real work */
86ddbf62 1693 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 1694 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
86ddbf62
AK
1695 priv->isr_stats.alive++;
1696 }
b481de9c
ZY
1697 }
1698#endif
1699 /* Safely ignore these bits for debug checks below */
25c03d8e 1700 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1701
b481de9c
ZY
1702 /* Error detected by uCode */
1703 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT
1704 IWL_ERR(priv, "Microcode SW error detected. "
1705 "Restarting 0x%X.\n", inta);
86ddbf62
AK
1706 priv->isr_stats.sw++;
1707 priv->isr_stats.sw_err = inta;
8ccde88a 1708 iwl_irq_handle_error(priv);
b481de9c
ZY
1709 handled |= CSR_INT_BIT_SW_ERR;
1710 }
1711
1712 /* uCode wakes up after power-down sleep */
1713 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1714 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
141c43a3 1715 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
4f3602c8
SO
1716 iwl_txq_update_write_ptr(priv, &priv->txq[0]);
1717 iwl_txq_update_write_ptr(priv, &priv->txq[1]);
1718 iwl_txq_update_write_ptr(priv, &priv->txq[2]);
1719 iwl_txq_update_write_ptr(priv, &priv->txq[3]);
1720 iwl_txq_update_write_ptr(priv, &priv->txq[4]);
1721 iwl_txq_update_write_ptr(priv, &priv->txq[5]);
b481de9c 1722
86ddbf62 1723 priv->isr_stats.wakeup++;
b481de9c
ZY
1724 handled |= CSR_INT_BIT_WAKEUP;
1725 }
1726
1727 /* All uCode command responses, including Tx command responses,
1728 * Rx "responses" (frame-received notification), and other
1729 * notifications from uCode come through here*/
1730 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
bb8c093b 1731 iwl3945_rx_handle(priv);
86ddbf62 1732 priv->isr_stats.rx++;
b481de9c
ZY
1733 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1734 }
1735
1736 if (inta & CSR_INT_BIT_FH_TX) {
e1623446 1737 IWL_DEBUG_ISR(priv, "Tx interrupt\n");
86ddbf62 1738 priv->isr_stats.tx++;
b481de9c 1739
5d49f498 1740 iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
a8b50a0a
MA
1741 iwl_write_direct32(priv, FH39_TCSR_CREDIT
1742 (FH39_SRVC_CHNL), 0x0);
b481de9c
ZY
1743 handled |= CSR_INT_BIT_FH_TX;
1744 }
1745
86ddbf62 1746 if (inta & ~handled) {
15b1687c 1747 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
86ddbf62
AK
1748 priv->isr_stats.unhandled++;
1749 }
b481de9c 1750
40cefda9 1751 if (inta & ~priv->inta_mask) {
39aadf8c 1752 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1753 inta & ~priv->inta_mask);
39aadf8c 1754 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY
1755 }
1756
1757 /* Re-enable all interrupts */
0359facc
MA
1758 /* only Re-enable if disabled by irq */
1759 if (test_bit(STATUS_INT_ENABLED, &priv->status))
ed3b932e 1760 iwl_enable_interrupts(priv);
b481de9c 1761
d08853a3 1762#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1763 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
5d49f498
AK
1764 inta = iwl_read32(priv, CSR_INT);
1765 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1766 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1767 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY
1768 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1769 }
1770#endif
1771 spin_unlock_irqrestore(&priv->lock, flags);
1772}
1773
4a8a4322 1774static int iwl3945_get_channels_for_scan(struct iwl_priv *priv,
8318d78a 1775 enum ieee80211_band band,
f9340520 1776 u8 is_active, u8 n_probes,
bb8c093b 1777 struct iwl3945_scan_channel *scan_ch)
b481de9c 1778{
4e05c234 1779 struct ieee80211_channel *chan;
8318d78a 1780 const struct ieee80211_supported_band *sband;
d20b3c65 1781 const struct iwl_channel_info *ch_info;
b481de9c
ZY
1782 u16 passive_dwell = 0;
1783 u16 active_dwell = 0;
1784 int added, i;
1785
cbba18c6 1786 sband = iwl_get_hw_mode(priv, band);
8318d78a 1787 if (!sband)
b481de9c
ZY
1788 return 0;
1789
77fecfb8
SO
1790 active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
1791 passive_dwell = iwl_get_passive_dwell_time(priv, band);
b481de9c 1792
8f4807a1
AK
1793 if (passive_dwell <= active_dwell)
1794 passive_dwell = active_dwell + 1;
1795
4e05c234
JB
1796 for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
1797 chan = priv->scan_request->channels[i];
1798
1799 if (chan->band != band)
182e2e66
JB
1800 continue;
1801
4e05c234 1802 scan_ch->channel = chan->hw_value;
b481de9c 1803
e6148917 1804 ch_info = iwl_get_channel_info(priv, band, scan_ch->channel);
b481de9c 1805 if (!is_channel_valid(ch_info)) {
e1623446 1806 IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
b481de9c
ZY
1807 scan_ch->channel);
1808 continue;
1809 }
1810
011a0330
AK
1811 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1812 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1813 /* If passive , set up for auto-switch
1814 * and use long active_dwell time.
1815 */
b481de9c 1816 if (!is_active || is_channel_passive(ch_info) ||
4e05c234 1817 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
b481de9c 1818 scan_ch->type = 0; /* passive */
011a0330
AK
1819 if (IWL_UCODE_API(priv->ucode_ver) == 1)
1820 scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
1821 } else {
b481de9c 1822 scan_ch->type = 1; /* active */
011a0330 1823 }
b481de9c 1824
011a0330
AK
1825 /* Set direct probe bits. These may be used both for active
1826 * scan channels (probes gets sent right away),
1827 * or for passive channels (probes get se sent only after
1828 * hearing clear Rx packet).*/
1829 if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
1830 if (n_probes)
0d21044e 1831 scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes);
011a0330
AK
1832 } else {
1833 /* uCode v1 does not allow setting direct probe bits on
1834 * passive channel. */
1835 if ((scan_ch->type & 1) && n_probes)
0d21044e 1836 scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes);
011a0330 1837 }
b481de9c 1838
9fbab516 1839 /* Set txpower levels to defaults */
b481de9c
ZY
1840 scan_ch->tpc.dsp_atten = 110;
1841 /* scan_pwr_info->tpc.dsp_atten; */
1842
1843 /*scan_pwr_info->tpc.tx_gain; */
8318d78a 1844 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY
1845 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
1846 else {
1847 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
1848 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
9fbab516 1849 * power level:
8a1b0245 1850 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
b481de9c
ZY
1851 */
1852 }
1853
e1623446 1854 IWL_DEBUG_SCAN(priv, "Scanning %d [%s %d]\n",
b481de9c
ZY
1855 scan_ch->channel,
1856 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
1857 (scan_ch->type & 1) ?
1858 active_dwell : passive_dwell);
1859
1860 scan_ch++;
1861 added++;
1862 }
1863
e1623446 1864 IWL_DEBUG_SCAN(priv, "total channels to scan %d \n", added);
b481de9c
ZY
1865 return added;
1866}
1867
4a8a4322 1868static void iwl3945_init_hw_rates(struct iwl_priv *priv,
b481de9c
ZY
1869 struct ieee80211_rate *rates)
1870{
1871 int i;
1872
1873 for (i = 0; i < IWL_RATE_COUNT; i++) {
8318d78a
JB
1874 rates[i].bitrate = iwl3945_rates[i].ieee * 5;
1875 rates[i].hw_value = i; /* Rate scaling will work on indexes */
1876 rates[i].hw_value_short = i;
1877 rates[i].flags = 0;
d9829a67 1878 if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
b481de9c 1879 /*
8318d78a 1880 * If CCK != 1M then set short preamble rate flag.
b481de9c 1881 */
bb8c093b 1882 rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
8318d78a 1883 0 : IEEE80211_RATE_SHORT_PREAMBLE;
b481de9c 1884 }
b481de9c
ZY
1885 }
1886}
1887
b481de9c
ZY
1888/******************************************************************************
1889 *
1890 * uCode download functions
1891 *
1892 ******************************************************************************/
1893
4a8a4322 1894static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1895{
98c92211
TW
1896 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1897 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1898 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1899 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1900 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1901 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY
1902}
1903
1904/**
bb8c093b 1905 * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
b481de9c
ZY
1906 * looking at all data.
1907 */
4a8a4322 1908static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len)
b481de9c
ZY
1909{
1910 u32 val;
1911 u32 save_len = len;
1912 int rc = 0;
1913 u32 errcnt;
1914
e1623446 1915 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b481de9c 1916
5d49f498 1917 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 1918 IWL39_RTC_INST_LOWER_BOUND);
b481de9c
ZY
1919
1920 errcnt = 0;
1921 for (; len > 0; len -= sizeof(u32), image++) {
1922 /* read data comes through single port, auto-incr addr */
1923 /* NOTE: Use the debugless read so we don't flood kernel log
1924 * if IWL_DL_IO is set */
5d49f498 1925 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c 1926 if (val != le32_to_cpu(*image)) {
15b1687c 1927 IWL_ERR(priv, "uCode INST section is invalid at "
b481de9c
ZY
1928 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1929 save_len - len, val, le32_to_cpu(*image));
1930 rc = -EIO;
1931 errcnt++;
1932 if (errcnt >= 20)
1933 break;
1934 }
1935 }
1936
b481de9c
ZY
1937
1938 if (!errcnt)
e1623446
TW
1939 IWL_DEBUG_INFO(priv,
1940 "ucode image in INSTRUCTION memory is good\n");
b481de9c
ZY
1941
1942 return rc;
1943}
1944
1945
1946/**
bb8c093b 1947 * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
b481de9c
ZY
1948 * using sample data 100 bytes apart. If these sample points are good,
1949 * it's a pretty good bet that everything between them is good, too.
1950 */
4a8a4322 1951static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
b481de9c
ZY
1952{
1953 u32 val;
1954 int rc = 0;
1955 u32 errcnt = 0;
1956 u32 i;
1957
e1623446 1958 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b481de9c 1959
b481de9c
ZY
1960 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
1961 /* read data comes through single port, auto-incr addr */
1962 /* NOTE: Use the debugless read so we don't flood kernel log
1963 * if IWL_DL_IO is set */
5d49f498 1964 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 1965 i + IWL39_RTC_INST_LOWER_BOUND);
5d49f498 1966 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY
1967 if (val != le32_to_cpu(*image)) {
1968#if 0 /* Enable this if you want to see details */
15b1687c 1969 IWL_ERR(priv, "uCode INST section is invalid at "
b481de9c
ZY
1970 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1971 i, val, *image);
1972#endif
1973 rc = -EIO;
1974 errcnt++;
1975 if (errcnt >= 3)
1976 break;
1977 }
1978 }
1979
b481de9c
ZY
1980 return rc;
1981}
1982
1983
1984/**
bb8c093b 1985 * iwl3945_verify_ucode - determine which instruction image is in SRAM,
b481de9c
ZY
1986 * and verify its contents
1987 */
4a8a4322 1988static int iwl3945_verify_ucode(struct iwl_priv *priv)
b481de9c
ZY
1989{
1990 __le32 *image;
1991 u32 len;
1992 int rc = 0;
1993
1994 /* Try bootstrap */
1995 image = (__le32 *)priv->ucode_boot.v_addr;
1996 len = priv->ucode_boot.len;
bb8c093b 1997 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c 1998 if (rc == 0) {
e1623446 1999 IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
b481de9c
ZY
2000 return 0;
2001 }
2002
2003 /* Try initialize */
2004 image = (__le32 *)priv->ucode_init.v_addr;
2005 len = priv->ucode_init.len;
bb8c093b 2006 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c 2007 if (rc == 0) {
e1623446 2008 IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
b481de9c
ZY
2009 return 0;
2010 }
2011
2012 /* Try runtime/protocol */
2013 image = (__le32 *)priv->ucode_code.v_addr;
2014 len = priv->ucode_code.len;
bb8c093b 2015 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c 2016 if (rc == 0) {
e1623446 2017 IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
b481de9c
ZY
2018 return 0;
2019 }
2020
15b1687c 2021 IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
b481de9c 2022
9fbab516
BC
2023 /* Since nothing seems to match, show first several data entries in
2024 * instruction SRAM, so maybe visual inspection will give a clue.
2025 * Selection of bootstrap image (vs. other images) is arbitrary. */
b481de9c
ZY
2026 image = (__le32 *)priv->ucode_boot.v_addr;
2027 len = priv->ucode_boot.len;
bb8c093b 2028 rc = iwl3945_verify_inst_full(priv, image, len);
b481de9c
ZY
2029
2030 return rc;
2031}
2032
4a8a4322 2033static void iwl3945_nic_start(struct iwl_priv *priv)
b481de9c
ZY
2034{
2035 /* Remove all resets to allow NIC to operate */
5d49f498 2036 iwl_write32(priv, CSR_RESET, 0);
b481de9c
ZY
2037}
2038
2039/**
bb8c093b 2040 * iwl3945_read_ucode - Read uCode images from disk file.
b481de9c
ZY
2041 *
2042 * Copy into buffers for card to fetch via bus-mastering
2043 */
4a8a4322 2044static int iwl3945_read_ucode(struct iwl_priv *priv)
b481de9c 2045{
cc0f555d 2046 const struct iwl_ucode_header *ucode;
a0987a8d 2047 int ret = -EINVAL, index;
b481de9c
ZY
2048 const struct firmware *ucode_raw;
2049 /* firmware file name contains uCode/driver compatibility version */
a0987a8d
RC
2050 const char *name_pre = priv->cfg->fw_name_pre;
2051 const unsigned int api_max = priv->cfg->ucode_api_max;
2052 const unsigned int api_min = priv->cfg->ucode_api_min;
2053 char buf[25];
b481de9c
ZY
2054 u8 *src;
2055 size_t len;
a0987a8d 2056 u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
b481de9c
ZY
2057
2058 /* Ask kernel firmware_class module to get the boot firmware off disk.
2059 * request_firmware() is synchronous, file is in memory on return. */
a0987a8d
RC
2060 for (index = api_max; index >= api_min; index--) {
2061 sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
2062 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
2063 if (ret < 0) {
15b1687c 2064 IWL_ERR(priv, "%s firmware file req failed: %d\n",
a0987a8d
RC
2065 buf, ret);
2066 if (ret == -ENOENT)
2067 continue;
2068 else
2069 goto error;
2070 } else {
2071 if (index < api_max)
15b1687c
WT
2072 IWL_ERR(priv, "Loaded firmware %s, "
2073 "which is deprecated. "
2074 " Please use API v%u instead.\n",
a0987a8d 2075 buf, api_max);
e1623446
TW
2076 IWL_DEBUG_INFO(priv, "Got firmware '%s' file "
2077 "(%zd bytes) from disk\n",
a0987a8d
RC
2078 buf, ucode_raw->size);
2079 break;
2080 }
b481de9c
ZY
2081 }
2082
a0987a8d
RC
2083 if (ret < 0)
2084 goto error;
b481de9c
ZY
2085
2086 /* Make sure that we got at least our header! */
cc0f555d 2087 if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
15b1687c 2088 IWL_ERR(priv, "File size way too small!\n");
90e759d1 2089 ret = -EINVAL;
b481de9c
ZY
2090 goto err_release;
2091 }
2092
2093 /* Data from ucode file: header followed by uCode images */
cc0f555d 2094 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 2095
c02b3acd 2096 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 2097 api_ver = IWL_UCODE_API(priv->ucode_ver);
cc0f555d
JS
2098 inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
2099 data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
2100 init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
2101 init_data_size =
2102 priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
2103 boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
2104 src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
b481de9c 2105
a0987a8d
RC
2106 /* api_ver should match the api version forming part of the
2107 * firmware filename ... but we don't check for that and only rely
877d0310 2108 * on the API version read from firmware header from here on forward */
a0987a8d
RC
2109
2110 if (api_ver < api_min || api_ver > api_max) {
15b1687c 2111 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC
2112 "Driver supports v%u, firmware is v%u.\n",
2113 api_max, api_ver);
2114 priv->ucode_ver = 0;
2115 ret = -EINVAL;
2116 goto err_release;
2117 }
2118 if (api_ver != api_max)
15b1687c 2119 IWL_ERR(priv, "Firmware has old API version. Expected %u, "
a0987a8d
RC
2120 "got %u. New firmware can be obtained "
2121 "from http://www.intellinuxwireless.org.\n",
2122 api_max, api_ver);
2123
978785a3
TW
2124 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
2125 IWL_UCODE_MAJOR(priv->ucode_ver),
2126 IWL_UCODE_MINOR(priv->ucode_ver),
2127 IWL_UCODE_API(priv->ucode_ver),
2128 IWL_UCODE_SERIAL(priv->ucode_ver));
2129
e1623446 2130 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
a0987a8d 2131 priv->ucode_ver);
e1623446
TW
2132 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
2133 inst_size);
2134 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
2135 data_size);
2136 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
2137 init_size);
2138 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
2139 init_data_size);
2140 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
2141 boot_size);
b481de9c 2142
a0987a8d 2143
b481de9c 2144 /* Verify size of file vs. image size info in file's header */
cc0f555d 2145 if (ucode_raw->size != priv->cfg->ops->ucode->get_header_size(api_ver) +
b481de9c
ZY
2146 inst_size + data_size + init_size +
2147 init_data_size + boot_size) {
2148
cc0f555d
JS
2149 IWL_DEBUG_INFO(priv,
2150 "uCode file size %zd does not match expected size\n",
2151 ucode_raw->size);
90e759d1 2152 ret = -EINVAL;
b481de9c
ZY
2153 goto err_release;
2154 }
2155
2156 /* Verify that uCode images will fit in card's SRAM */
250bdd21 2157 if (inst_size > IWL39_MAX_INST_SIZE) {
e1623446 2158 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
90e759d1
TW
2159 inst_size);
2160 ret = -EINVAL;
b481de9c
ZY
2161 goto err_release;
2162 }
2163
250bdd21 2164 if (data_size > IWL39_MAX_DATA_SIZE) {
e1623446 2165 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
90e759d1
TW
2166 data_size);
2167 ret = -EINVAL;
b481de9c
ZY
2168 goto err_release;
2169 }
250bdd21 2170 if (init_size > IWL39_MAX_INST_SIZE) {
e1623446
TW
2171 IWL_DEBUG_INFO(priv,
2172 "uCode init instr len %d too large to fit in\n",
90e759d1
TW
2173 init_size);
2174 ret = -EINVAL;
b481de9c
ZY
2175 goto err_release;
2176 }
250bdd21 2177 if (init_data_size > IWL39_MAX_DATA_SIZE) {
e1623446
TW
2178 IWL_DEBUG_INFO(priv,
2179 "uCode init data len %d too large to fit in\n",
90e759d1
TW
2180 init_data_size);
2181 ret = -EINVAL;
b481de9c
ZY
2182 goto err_release;
2183 }
250bdd21 2184 if (boot_size > IWL39_MAX_BSM_SIZE) {
e1623446
TW
2185 IWL_DEBUG_INFO(priv,
2186 "uCode boot instr len %d too large to fit in\n",
90e759d1
TW
2187 boot_size);
2188 ret = -EINVAL;
b481de9c
ZY
2189 goto err_release;
2190 }
2191
2192 /* Allocate ucode buffers for card's bus-master loading ... */
2193
2194 /* Runtime instructions and 2 copies of data:
2195 * 1) unmodified from disk
2196 * 2) backup cache for save/restore during power-downs */
2197 priv->ucode_code.len = inst_size;
98c92211 2198 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY
2199
2200 priv->ucode_data.len = data_size;
98c92211 2201 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY
2202
2203 priv->ucode_data_backup.len = data_size;
98c92211 2204 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 2205
90e759d1
TW
2206 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2207 !priv->ucode_data_backup.v_addr)
2208 goto err_pci_alloc;
b481de9c
ZY
2209
2210 /* Initialization instructions and data */
90e759d1
TW
2211 if (init_size && init_data_size) {
2212 priv->ucode_init.len = init_size;
98c92211 2213 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW
2214
2215 priv->ucode_init_data.len = init_data_size;
98c92211 2216 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW
2217
2218 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2219 goto err_pci_alloc;
2220 }
b481de9c
ZY
2221
2222 /* Bootstrap (instructions only, no data) */
90e759d1
TW
2223 if (boot_size) {
2224 priv->ucode_boot.len = boot_size;
98c92211 2225 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 2226
90e759d1
TW
2227 if (!priv->ucode_boot.v_addr)
2228 goto err_pci_alloc;
2229 }
b481de9c
ZY
2230
2231 /* Copy images into buffers for card's bus-master reads ... */
2232
2233 /* Runtime instructions (first block of data in file) */
cc0f555d 2234 len = inst_size;
e1623446
TW
2235 IWL_DEBUG_INFO(priv,
2236 "Copying (but not loading) uCode instr len %zd\n", len);
b481de9c 2237 memcpy(priv->ucode_code.v_addr, src, len);
cc0f555d
JS
2238 src += len;
2239
e1623446 2240 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY
2241 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2242
2243 /* Runtime data (2nd block)
bb8c093b 2244 * NOTE: Copy into backup buffer will be done in iwl3945_up() */
cc0f555d 2245 len = data_size;
e1623446
TW
2246 IWL_DEBUG_INFO(priv,
2247 "Copying (but not loading) uCode data len %zd\n", len);
b481de9c
ZY
2248 memcpy(priv->ucode_data.v_addr, src, len);
2249 memcpy(priv->ucode_data_backup.v_addr, src, len);
cc0f555d 2250 src += len;
b481de9c
ZY
2251
2252 /* Initialization instructions (3rd block) */
2253 if (init_size) {
cc0f555d 2254 len = init_size;
e1623446
TW
2255 IWL_DEBUG_INFO(priv,
2256 "Copying (but not loading) init instr len %zd\n", len);
b481de9c 2257 memcpy(priv->ucode_init.v_addr, src, len);
cc0f555d 2258 src += len;
b481de9c
ZY
2259 }
2260
2261 /* Initialization data (4th block) */
2262 if (init_data_size) {
cc0f555d 2263 len = init_data_size;
e1623446
TW
2264 IWL_DEBUG_INFO(priv,
2265 "Copying (but not loading) init data len %zd\n", len);
b481de9c 2266 memcpy(priv->ucode_init_data.v_addr, src, len);
cc0f555d 2267 src += len;
b481de9c
ZY
2268 }
2269
2270 /* Bootstrap instructions (5th block) */
cc0f555d 2271 len = boot_size;
e1623446
TW
2272 IWL_DEBUG_INFO(priv,
2273 "Copying (but not loading) boot instr len %zd\n", len);
b481de9c
ZY
2274 memcpy(priv->ucode_boot.v_addr, src, len);
2275
2276 /* We have our copies now, allow OS release its copies */
2277 release_firmware(ucode_raw);
2278 return 0;
2279
2280 err_pci_alloc:
15b1687c 2281 IWL_ERR(priv, "failed to allocate pci memory\n");
90e759d1 2282 ret = -ENOMEM;
bb8c093b 2283 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY
2284
2285 err_release:
2286 release_firmware(ucode_raw);
2287
2288 error:
90e759d1 2289 return ret;
b481de9c
ZY
2290}
2291
2292
2293/**
bb8c093b 2294 * iwl3945_set_ucode_ptrs - Set uCode address location
b481de9c
ZY
2295 *
2296 * Tell initialization uCode where to find runtime uCode.
2297 *
2298 * BSM registers initially contain pointers to initialization uCode.
2299 * We need to replace them to load runtime uCode inst and data,
2300 * and to save runtime data when powering down.
2301 */
4a8a4322 2302static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv)
b481de9c
ZY
2303{
2304 dma_addr_t pinst;
2305 dma_addr_t pdata;
b481de9c
ZY
2306
2307 /* bits 31:0 for 3945 */
2308 pinst = priv->ucode_code.p_addr;
2309 pdata = priv->ucode_data_backup.p_addr;
2310
b481de9c 2311 /* Tell bootstrap uCode where to find image to load */
5d49f498
AK
2312 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2313 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2314 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
b481de9c
ZY
2315 priv->ucode_data.len);
2316
a96a27f9 2317 /* Inst byte count must be last to set up, bit 31 signals uCode
b481de9c 2318 * that all new ptr/size info is in place */
5d49f498 2319 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
b481de9c
ZY
2320 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
2321
e1623446 2322 IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n");
b481de9c 2323
a8b50a0a 2324 return 0;
b481de9c
ZY
2325}
2326
2327/**
bb8c093b 2328 * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
b481de9c
ZY
2329 *
2330 * Called after REPLY_ALIVE notification received from "initialize" uCode.
2331 *
b481de9c 2332 * Tell "initialize" uCode to go ahead and load the runtime uCode.
9fbab516 2333 */
4a8a4322 2334static void iwl3945_init_alive_start(struct iwl_priv *priv)
b481de9c
ZY
2335{
2336 /* Check alive response for "valid" sign from uCode */
2337 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
2338 /* We had an error bringing up the hardware, so take it
2339 * all the way back down so we can try again */
e1623446 2340 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
b481de9c
ZY
2341 goto restart;
2342 }
2343
2344 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
2345 * This is a paranoid check, because we would not have gotten the
2346 * "initialize" alive if code weren't properly loaded. */
bb8c093b 2347 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY
2348 /* Runtime instruction load was bad;
2349 * take it all the way back down so we can try again */
e1623446 2350 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
b481de9c
ZY
2351 goto restart;
2352 }
2353
2354 /* Send pointers to protocol/runtime uCode image ... init code will
2355 * load and launch runtime uCode, which will send us another "Alive"
2356 * notification. */
e1623446 2357 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
bb8c093b 2358 if (iwl3945_set_ucode_ptrs(priv)) {
b481de9c
ZY
2359 /* Runtime instruction load won't happen;
2360 * take it all the way back down so we can try again */
e1623446 2361 IWL_DEBUG_INFO(priv, "Couldn't set up uCode pointers.\n");
b481de9c
ZY
2362 goto restart;
2363 }
2364 return;
2365
2366 restart:
2367 queue_work(priv->workqueue, &priv->restart);
2368}
2369
b481de9c 2370/**
bb8c093b 2371 * iwl3945_alive_start - called after REPLY_ALIVE notification received
b481de9c 2372 * from protocol/runtime uCode (initialization uCode's
bb8c093b 2373 * Alive gets handled by iwl3945_init_alive_start()).
b481de9c 2374 */
4a8a4322 2375static void iwl3945_alive_start(struct iwl_priv *priv)
b481de9c 2376{
b481de9c
ZY
2377 int thermal_spin = 0;
2378 u32 rfkill;
2379
e1623446 2380 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY
2381
2382 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2383 /* We had an error bringing up the hardware, so take it
2384 * all the way back down so we can try again */
e1623446 2385 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY
2386 goto restart;
2387 }
2388
2389 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2390 * This is a paranoid check, because we would not have gotten the
2391 * "runtime" alive if code weren't properly loaded. */
bb8c093b 2392 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY
2393 /* Runtime instruction load was bad;
2394 * take it all the way back down so we can try again */
e1623446 2395 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY
2396 goto restart;
2397 }
2398
c587de0b 2399 iwl_clear_stations_table(priv);
b481de9c 2400
5d49f498 2401 rfkill = iwl_read_prph(priv, APMG_RFKILL_REG);
e1623446 2402 IWL_DEBUG_INFO(priv, "RFKILL status: 0x%x\n", rfkill);
b481de9c
ZY
2403
2404 if (rfkill & 0x1) {
2405 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a96a27f9 2406 /* if RFKILL is not on, then wait for thermal
b481de9c 2407 * sensor in adapter to kick in */
bb8c093b 2408 while (iwl3945_hw_get_temperature(priv) == 0) {
b481de9c
ZY
2409 thermal_spin++;
2410 udelay(10);
2411 }
2412
2413 if (thermal_spin)
e1623446 2414 IWL_DEBUG_INFO(priv, "Thermal calibration took %dus\n",
b481de9c
ZY
2415 thermal_spin * 10);
2416 } else
2417 set_bit(STATUS_RF_KILL_HW, &priv->status);
2418
9fbab516 2419 /* After the ALIVE response, we can send commands to 3945 uCode */
b481de9c
ZY
2420 set_bit(STATUS_ALIVE, &priv->status);
2421
775a6e27 2422 if (iwl_is_rfkill(priv))
b481de9c
ZY
2423 return;
2424
36d6825b 2425 ieee80211_wake_queues(priv->hw);
b481de9c
ZY
2426
2427 priv->active_rate = priv->rates_mask;
2428 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
2429
d25aabb0 2430 iwl_power_update_mode(priv, false);
b481de9c 2431
8ccde88a 2432 if (iwl_is_associated(priv)) {
bb8c093b 2433 struct iwl3945_rxon_cmd *active_rxon =
8ccde88a 2434 (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
b481de9c 2435
8a9b9926 2436 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY
2437 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2438 } else {
2439 /* Initialize our rx_config data */
8ccde88a 2440 iwl_connection_init_rx_config(priv, priv->iw_mode);
b481de9c
ZY
2441 }
2442
9fbab516 2443 /* Configure Bluetooth device coexistence support */
17f841cd 2444 iwl_send_bt_config(priv);
b481de9c
ZY
2445
2446 /* Configure the adapter for unassociated operation */
e0158e61 2447 iwlcore_commit_rxon(priv);
b481de9c 2448
b481de9c
ZY
2449 iwl3945_reg_txpower_periodic(priv);
2450
fe00b5a5
RC
2451 iwl3945_led_register(priv);
2452
e1623446 2453 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 2454 set_bit(STATUS_READY, &priv->status);
5a66926a 2455 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 2456
9bdf5eca
MA
2457 /* reassociate for ADHOC mode */
2458 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
2459 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
2460 priv->vif);
2461 if (beacon)
9944b938 2462 iwl_mac_beacon_update(priv->hw, beacon);
9bdf5eca
MA
2463 }
2464
f45c2714 2465 if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
727882d6 2466 iwl_set_mode(priv, priv->iw_mode);
f45c2714 2467
b481de9c
ZY
2468 return;
2469
2470 restart:
2471 queue_work(priv->workqueue, &priv->restart);
2472}
2473
4a8a4322 2474static void iwl3945_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 2475
4a8a4322 2476static void __iwl3945_down(struct iwl_priv *priv)
b481de9c
ZY
2477{
2478 unsigned long flags;
2479 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2480 struct ieee80211_conf *conf = NULL;
2481
e1623446 2482 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c
ZY
2483
2484 conf = ieee80211_get_hw_conf(priv->hw);
2485
2486 if (!exit_pending)
2487 set_bit(STATUS_EXIT_PENDING, &priv->status);
2488
ab53d8af 2489 iwl3945_led_unregister(priv);
c587de0b 2490 iwl_clear_stations_table(priv);
b481de9c
ZY
2491
2492 /* Unblock any waiting calls */
2493 wake_up_interruptible_all(&priv->wait_command_queue);
2494
b481de9c
ZY
2495 /* Wipe out the EXIT_PENDING status bit if we are not actually
2496 * exiting the module */
2497 if (!exit_pending)
2498 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2499
2500 /* stop and reset the on-board processor */
5d49f498 2501 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY
2502
2503 /* tell the device to stop sending interrupts */
0359facc 2504 spin_lock_irqsave(&priv->lock, flags);
ed3b932e 2505 iwl_disable_interrupts(priv);
0359facc
MA
2506 spin_unlock_irqrestore(&priv->lock, flags);
2507 iwl_synchronize_irq(priv);
b481de9c
ZY
2508
2509 if (priv->mac80211_registered)
2510 ieee80211_stop_queues(priv->hw);
2511
bb8c093b 2512 /* If we have not previously called iwl3945_init() then
6da3a13e 2513 * clear all bits but the RF Kill bits and return */
775a6e27 2514 if (!iwl_is_init(priv)) {
b481de9c
ZY
2515 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2516 STATUS_RF_KILL_HW |
9788864e
RC
2517 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2518 STATUS_GEO_CONFIGURED |
ebef2008
AK
2519 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2520 STATUS_EXIT_PENDING;
b481de9c
ZY
2521 goto exit;
2522 }
2523
6da3a13e 2524 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 2525 * bit and continue taking the NIC down. */
b481de9c
ZY
2526 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2527 STATUS_RF_KILL_HW |
9788864e
RC
2528 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2529 STATUS_GEO_CONFIGURED |
b481de9c 2530 test_bit(STATUS_FW_ERROR, &priv->status) <<
ebef2008
AK
2531 STATUS_FW_ERROR |
2532 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2533 STATUS_EXIT_PENDING;
b481de9c 2534
e9414b6b 2535 priv->cfg->ops->lib->apm_ops.reset(priv);
b481de9c 2536 spin_lock_irqsave(&priv->lock, flags);
5d49f498 2537 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY
2538 spin_unlock_irqrestore(&priv->lock, flags);
2539
bb8c093b
CH
2540 iwl3945_hw_txq_ctx_stop(priv);
2541 iwl3945_hw_rxq_stop(priv);
b481de9c 2542
a8b50a0a
MA
2543 iwl_write_prph(priv, APMG_CLK_DIS_REG,
2544 APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY
2545
2546 udelay(5);
2547
6da3a13e 2548 if (exit_pending)
e9414b6b
AM
2549 priv->cfg->ops->lib->apm_ops.stop(priv);
2550 else
2551 priv->cfg->ops->lib->apm_ops.reset(priv);
2552
b481de9c 2553 exit:
3d24a9f7 2554 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY
2555
2556 if (priv->ibss_beacon)
2557 dev_kfree_skb(priv->ibss_beacon);
2558 priv->ibss_beacon = NULL;
2559
2560 /* clear out any free frames */
bb8c093b 2561 iwl3945_clear_free_frames(priv);
b481de9c
ZY
2562}
2563
4a8a4322 2564static void iwl3945_down(struct iwl_priv *priv)
b481de9c
ZY
2565{
2566 mutex_lock(&priv->mutex);
bb8c093b 2567 __iwl3945_down(priv);
b481de9c 2568 mutex_unlock(&priv->mutex);
b24d22b1 2569
bb8c093b 2570 iwl3945_cancel_deferred_work(priv);
b481de9c
ZY
2571}
2572
2573#define MAX_HW_RESTARTS 5
2574
4a8a4322 2575static int __iwl3945_up(struct iwl_priv *priv)
b481de9c
ZY
2576{
2577 int rc, i;
2578
2579 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 2580 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY
2581 return -EIO;
2582 }
2583
e903fbd4 2584 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 2585 IWL_ERR(priv, "ucode not available for device bring up\n");
e903fbd4
RC
2586 return -EIO;
2587 }
2588
e655b9f0 2589 /* If platform's RF_KILL switch is NOT set to KILL */
5d49f498 2590 if (iwl_read32(priv, CSR_GP_CNTRL) &
e655b9f0
ZY
2591 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2592 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2593 else {
2594 set_bit(STATUS_RF_KILL_HW, &priv->status);
6da3a13e
WYG
2595 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2596 return -ENODEV;
b481de9c 2597 }
80fcc9e2 2598
5d49f498 2599 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 2600
bb8c093b 2601 rc = iwl3945_hw_nic_init(priv);
b481de9c 2602 if (rc) {
15b1687c 2603 IWL_ERR(priv, "Unable to int nic\n");
b481de9c
ZY
2604 return rc;
2605 }
2606
2607 /* make sure rfkill handshake bits are cleared */
5d49f498
AK
2608 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2609 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY
2610 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2611
2612 /* clear (again), then enable host interrupts */
5d49f498 2613 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
ed3b932e 2614 iwl_enable_interrupts(priv);
b481de9c
ZY
2615
2616 /* really make sure rfkill handshake bits are cleared */
5d49f498
AK
2617 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2618 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
2619
2620 /* Copy original ucode data image from disk into backup cache.
2621 * This will be used to initialize the on-board processor's
2622 * data SRAM for a clean start when the runtime program first loads. */
2623 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 2624 priv->ucode_data.len);
b481de9c 2625
e655b9f0
ZY
2626 /* We return success when we resume from suspend and rf_kill is on. */
2627 if (test_bit(STATUS_RF_KILL_HW, &priv->status))
2628 return 0;
2629
b481de9c
ZY
2630 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2631
c587de0b 2632 iwl_clear_stations_table(priv);
b481de9c
ZY
2633
2634 /* load bootstrap state machine,
2635 * load bootstrap program into processor's memory,
2636 * prepare to load the "initialize" uCode */
0164b9b4 2637 priv->cfg->ops->lib->load_ucode(priv);
b481de9c
ZY
2638
2639 if (rc) {
15b1687c
WT
2640 IWL_ERR(priv,
2641 "Unable to set up bootstrap uCode: %d\n", rc);
b481de9c
ZY
2642 continue;
2643 }
2644
2645 /* start card; "initialize" will load runtime ucode */
bb8c093b 2646 iwl3945_nic_start(priv);
b481de9c 2647
e1623446 2648 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY
2649
2650 return 0;
2651 }
2652
2653 set_bit(STATUS_EXIT_PENDING, &priv->status);
bb8c093b 2654 __iwl3945_down(priv);
ebef2008 2655 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY
2656
2657 /* tried to restart and config the device for as long as our
2658 * patience could withstand */
15b1687c 2659 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY
2660 return -EIO;
2661}
2662
2663
2664/*****************************************************************************
2665 *
2666 * Workqueue callbacks
2667 *
2668 *****************************************************************************/
2669
bb8c093b 2670static void iwl3945_bg_init_alive_start(struct work_struct *data)
b481de9c 2671{
4a8a4322
AK
2672 struct iwl_priv *priv =
2673 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY
2674
2675 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2676 return;
2677
2678 mutex_lock(&priv->mutex);
bb8c093b 2679 iwl3945_init_alive_start(priv);
b481de9c
ZY
2680 mutex_unlock(&priv->mutex);
2681}
2682
bb8c093b 2683static void iwl3945_bg_alive_start(struct work_struct *data)
b481de9c 2684{
4a8a4322
AK
2685 struct iwl_priv *priv =
2686 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY
2687
2688 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2689 return;
2690
2691 mutex_lock(&priv->mutex);
bb8c093b 2692 iwl3945_alive_start(priv);
b481de9c
ZY
2693 mutex_unlock(&priv->mutex);
2694}
2695
2663516d
HS
2696static void iwl3945_rfkill_poll(struct work_struct *data)
2697{
2698 struct iwl_priv *priv =
2699 container_of(data, struct iwl_priv, rfkill_poll.work);
2663516d
HS
2700
2701 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2702 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2703 else
2704 set_bit(STATUS_RF_KILL_HW, &priv->status);
2705
a60e77e5
JB
2706 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
2707 test_bit(STATUS_RF_KILL_HW, &priv->status));
2663516d
HS
2708
2709 queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
2710 round_jiffies_relative(2 * HZ));
2711
2712}
2713
b481de9c 2714#define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
bb8c093b 2715static void iwl3945_bg_request_scan(struct work_struct *data)
b481de9c 2716{
4a8a4322
AK
2717 struct iwl_priv *priv =
2718 container_of(data, struct iwl_priv, request_scan);
c2d79b48 2719 struct iwl_host_cmd cmd = {
b481de9c 2720 .id = REPLY_SCAN_CMD,
bb8c093b 2721 .len = sizeof(struct iwl3945_scan_cmd),
c2acea8e 2722 .flags = CMD_SIZE_HUGE,
b481de9c
ZY
2723 };
2724 int rc = 0;
bb8c093b 2725 struct iwl3945_scan_cmd *scan;
b481de9c 2726 struct ieee80211_conf *conf = NULL;
1ecf9fc1 2727 u8 n_probes = 0;
8318d78a 2728 enum ieee80211_band band;
1ecf9fc1 2729 bool is_active = false;
b481de9c
ZY
2730
2731 conf = ieee80211_get_hw_conf(priv->hw);
2732
2733 mutex_lock(&priv->mutex);
2734
fbc9f97b
RC
2735 cancel_delayed_work(&priv->scan_check);
2736
775a6e27 2737 if (!iwl_is_ready(priv)) {
39aadf8c 2738 IWL_WARN(priv, "request scan called when driver not ready.\n");
b481de9c
ZY
2739 goto done;
2740 }
2741
a96a27f9 2742 /* Make sure the scan wasn't canceled before this queued work
b481de9c
ZY
2743 * was given the chance to run... */
2744 if (!test_bit(STATUS_SCANNING, &priv->status))
2745 goto done;
2746
2747 /* This should never be called or scheduled if there is currently
2748 * a scan active in the hardware. */
2749 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
e1623446
TW
2750 IWL_DEBUG_INFO(priv, "Multiple concurrent scan requests "
2751 "Ignoring second request.\n");
b481de9c
ZY
2752 rc = -EIO;
2753 goto done;
2754 }
2755
2756 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
e1623446 2757 IWL_DEBUG_SCAN(priv, "Aborting scan due to device shutdown\n");
b481de9c
ZY
2758 goto done;
2759 }
2760
2761 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
e1623446
TW
2762 IWL_DEBUG_HC(priv,
2763 "Scan request while abort pending. Queuing.\n");
b481de9c
ZY
2764 goto done;
2765 }
2766
775a6e27 2767 if (iwl_is_rfkill(priv)) {
e1623446 2768 IWL_DEBUG_HC(priv, "Aborting scan due to RF Kill activation\n");
b481de9c
ZY
2769 goto done;
2770 }
2771
2772 if (!test_bit(STATUS_READY, &priv->status)) {
e1623446
TW
2773 IWL_DEBUG_HC(priv,
2774 "Scan request while uninitialized. Queuing.\n");
b481de9c
ZY
2775 goto done;
2776 }
2777
2778 if (!priv->scan_bands) {
e1623446 2779 IWL_DEBUG_HC(priv, "Aborting scan due to no requested bands\n");
b481de9c
ZY
2780 goto done;
2781 }
2782
805cee5b
WT
2783 if (!priv->scan) {
2784 priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
b481de9c 2785 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
805cee5b 2786 if (!priv->scan) {
b481de9c
ZY
2787 rc = -ENOMEM;
2788 goto done;
2789 }
2790 }
805cee5b 2791 scan = priv->scan;
bb8c093b 2792 memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
b481de9c
ZY
2793
2794 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
2795 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
2796
8ccde88a 2797 if (iwl_is_associated(priv)) {
b481de9c
ZY
2798 u16 interval = 0;
2799 u32 extra;
2800 u32 suspend_time = 100;
2801 u32 scan_suspend_time = 100;
2802 unsigned long flags;
2803
e1623446 2804 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
b481de9c
ZY
2805
2806 spin_lock_irqsave(&priv->lock, flags);
2807 interval = priv->beacon_int;
2808 spin_unlock_irqrestore(&priv->lock, flags);
2809
2810 scan->suspend_time = 0;
15e869d8 2811 scan->max_out_time = cpu_to_le32(200 * 1024);
b481de9c
ZY
2812 if (!interval)
2813 interval = suspend_time;
2814 /*
2815 * suspend time format:
2816 * 0-19: beacon interval in usec (time before exec.)
2817 * 20-23: 0
2818 * 24-31: number of beacons (suspend between channels)
2819 */
2820
2821 extra = (suspend_time / interval) << 24;
2822 scan_suspend_time = 0xFF0FFFFF &
2823 (extra | ((suspend_time % interval) * 1024));
2824
2825 scan->suspend_time = cpu_to_le32(scan_suspend_time);
e1623446 2826 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
b481de9c
ZY
2827 scan_suspend_time, interval);
2828 }
2829
1ecf9fc1
JB
2830 if (priv->scan_request->n_ssids) {
2831 int i, p = 0;
2832 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
2833 for (i = 0; i < priv->scan_request->n_ssids; i++) {
2834 /* always does wildcard anyway */
2835 if (!priv->scan_request->ssids[i].ssid_len)
2836 continue;
2837 scan->direct_scan[p].id = WLAN_EID_SSID;
2838 scan->direct_scan[p].len =
2839 priv->scan_request->ssids[i].ssid_len;
2840 memcpy(scan->direct_scan[p].ssid,
2841 priv->scan_request->ssids[i].ssid,
2842 priv->scan_request->ssids[i].ssid_len);
2843 n_probes++;
2844 p++;
2845 }
2846 is_active = true;
f9340520 2847 } else
1ecf9fc1 2848 IWL_DEBUG_SCAN(priv, "Kicking off passive scan.\n");
b481de9c
ZY
2849
2850 /* We don't build a direct scan probe request; the uCode will do
2851 * that based on the direct_mask added to each channel entry */
b481de9c 2852 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
3832ec9d 2853 scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY
2854 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2855
2856 /* flags + rate selection */
2857
66b5004d 2858 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
b481de9c
ZY
2859 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
2860 scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
2861 scan->good_CRC_th = 0;
8318d78a 2862 band = IEEE80211_BAND_2GHZ;
66b5004d 2863 } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
b481de9c 2864 scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
b097ad29
JB
2865 /*
2866 * If active scaning is requested but a certain channel
2867 * is marked passive, we can do active scanning if we
2868 * detect transmissions.
2869 */
2870 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH : 0;
8318d78a 2871 band = IEEE80211_BAND_5GHZ;
66b5004d 2872 } else {
39aadf8c 2873 IWL_WARN(priv, "Invalid scan band count\n");
b481de9c
ZY
2874 goto done;
2875 }
2876
77fecfb8 2877 scan->tx_cmd.len = cpu_to_le16(
1ecf9fc1
JB
2878 iwl_fill_probe_req(priv,
2879 (struct ieee80211_mgmt *)scan->data,
2880 priv->scan_request->ie,
2881 priv->scan_request->ie_len,
2882 IWL_MAX_SCAN_SIZE - sizeof(*scan)));
77fecfb8 2883
b481de9c
ZY
2884 /* select Rx antennas */
2885 scan->flags |= iwl3945_get_antenna_flags(priv);
2886
279b05d4 2887 if (iwl_is_monitor_mode(priv))
b481de9c
ZY
2888 scan->filter_flags = RXON_FILTER_PROMISC_MSK;
2889
f9340520 2890 scan->channel_count =
1ecf9fc1 2891 iwl3945_get_channels_for_scan(priv, band, is_active, n_probes,
f9340520 2892 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
b481de9c 2893
14b54336 2894 if (scan->channel_count == 0) {
e1623446 2895 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
14b54336
RC
2896 goto done;
2897 }
2898
b481de9c 2899 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
bb8c093b 2900 scan->channel_count * sizeof(struct iwl3945_scan_channel);
b481de9c
ZY
2901 cmd.data = scan;
2902 scan->len = cpu_to_le16(cmd.len);
2903
2904 set_bit(STATUS_SCAN_HW, &priv->status);
518099a8 2905 rc = iwl_send_cmd_sync(priv, &cmd);
b481de9c
ZY
2906 if (rc)
2907 goto done;
2908
2909 queue_delayed_work(priv->workqueue, &priv->scan_check,
2910 IWL_SCAN_CHECK_WATCHDOG);
2911
2912 mutex_unlock(&priv->mutex);
2913 return;
2914
2915 done:
2420ebc1
MA
2916 /* can not perform scan make sure we clear scanning
2917 * bits from status so next scan request can be performed.
2918 * if we dont clear scanning status bit here all next scan
2919 * will fail
2920 */
2921 clear_bit(STATUS_SCAN_HW, &priv->status);
2922 clear_bit(STATUS_SCANNING, &priv->status);
2923
01ebd063 2924 /* inform mac80211 scan aborted */
b481de9c
ZY
2925 queue_work(priv->workqueue, &priv->scan_completed);
2926 mutex_unlock(&priv->mutex);
2927}
2928
bb8c093b 2929static void iwl3945_bg_up(struct work_struct *data)
b481de9c 2930{
4a8a4322 2931 struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
b481de9c
ZY
2932
2933 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2934 return;
2935
2936 mutex_lock(&priv->mutex);
bb8c093b 2937 __iwl3945_up(priv);
b481de9c
ZY
2938 mutex_unlock(&priv->mutex);
2939}
2940
bb8c093b 2941static void iwl3945_bg_restart(struct work_struct *data)
b481de9c 2942{
4a8a4322 2943 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY
2944
2945 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2946 return;
2947
19cc1087
JB
2948 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2949 mutex_lock(&priv->mutex);
2950 priv->vif = NULL;
2951 priv->is_open = 0;
2952 mutex_unlock(&priv->mutex);
2953 iwl3945_down(priv);
2954 ieee80211_restart_hw(priv->hw);
2955 } else {
2956 iwl3945_down(priv);
2957 queue_work(priv->workqueue, &priv->up);
2958 }
b481de9c
ZY
2959}
2960
bb8c093b 2961static void iwl3945_bg_rx_replenish(struct work_struct *data)
b481de9c 2962{
4a8a4322
AK
2963 struct iwl_priv *priv =
2964 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY
2965
2966 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2967 return;
2968
2969 mutex_lock(&priv->mutex);
bb8c093b 2970 iwl3945_rx_replenish(priv);
b481de9c
ZY
2971 mutex_unlock(&priv->mutex);
2972}
2973
7878a5a4
MA
2974#define IWL_DELAY_NEXT_SCAN (HZ*2)
2975
5bbe233b 2976void iwl3945_post_associate(struct iwl_priv *priv)
b481de9c 2977{
b481de9c
ZY
2978 int rc = 0;
2979 struct ieee80211_conf *conf = NULL;
2980
05c914fe 2981 if (priv->iw_mode == NL80211_IFTYPE_AP) {
15b1687c 2982 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY
2983 return;
2984 }
2985
2986
e1623446 2987 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
8ccde88a 2988 priv->assoc_id, priv->active_rxon.bssid_addr);
b481de9c
ZY
2989
2990 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2991 return;
2992
322a9811 2993 if (!priv->vif || !priv->is_open)
6ef89d0a 2994 return;
322a9811 2995
af0053d6 2996 iwl_scan_cancel_timeout(priv, 200);
15e869d8 2997
b481de9c
ZY
2998 conf = ieee80211_get_hw_conf(priv->hw);
2999
8ccde88a 3000 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 3001 iwlcore_commit_rxon(priv);
b481de9c 3002
28afaf91 3003 memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
2c2f3b33 3004 iwl_setup_rxon_timing(priv);
518099a8 3005 rc = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY
3006 sizeof(priv->rxon_timing), &priv->rxon_timing);
3007 if (rc)
39aadf8c 3008 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
3009 "Attempting to continue.\n");
3010
8ccde88a 3011 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c 3012
8ccde88a 3013 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
b481de9c 3014
e1623446 3015 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
b481de9c
ZY
3016 priv->assoc_id, priv->beacon_int);
3017
3018 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
8ccde88a 3019 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 3020 else
8ccde88a 3021 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 3022
8ccde88a 3023 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
b481de9c 3024 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
8ccde88a 3025 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
b481de9c 3026 else
8ccde88a 3027 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c 3028
05c914fe 3029 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
8ccde88a 3030 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c
ZY
3031
3032 }
3033
e0158e61 3034 iwlcore_commit_rxon(priv);
b481de9c
ZY
3035
3036 switch (priv->iw_mode) {
05c914fe 3037 case NL80211_IFTYPE_STATION:
bb8c093b 3038 iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
b481de9c
ZY
3039 break;
3040
05c914fe 3041 case NL80211_IFTYPE_ADHOC:
b481de9c 3042
ce546fd2 3043 priv->assoc_id = 1;
c587de0b 3044 iwl_add_station(priv, priv->bssid, 0, CMD_SYNC, NULL);
b481de9c 3045 iwl3945_sync_sta(priv, IWL_STA_ID,
8318d78a 3046 (priv->band == IEEE80211_BAND_5GHZ) ?
b481de9c
ZY
3047 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
3048 CMD_ASYNC);
bb8c093b
CH
3049 iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
3050 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
3051
3052 break;
3053
3054 default:
15b1687c 3055 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3ac7f146 3056 __func__, priv->iw_mode);
b481de9c
ZY
3057 break;
3058 }
3059
14d2aac5 3060 iwl_activate_qos(priv, 0);
292ae174 3061
7878a5a4
MA
3062 /* we have just associated, don't start scan too early */
3063 priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
cd56d331
AK
3064}
3065
b481de9c
ZY
3066/*****************************************************************************
3067 *
3068 * mac80211 entry point functions
3069 *
3070 *****************************************************************************/
3071
5a66926a
ZY
3072#define UCODE_READY_TIMEOUT (2 * HZ)
3073
bb8c093b 3074static int iwl3945_mac_start(struct ieee80211_hw *hw)
b481de9c 3075{
4a8a4322 3076 struct iwl_priv *priv = hw->priv;
5a66926a 3077 int ret;
b481de9c 3078
e1623446 3079 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY
3080
3081 /* we should be verifying the device is ready to be opened */
3082 mutex_lock(&priv->mutex);
3083
5a66926a
ZY
3084 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
3085 * ucode filename and max sizes are card-specific. */
3086
3087 if (!priv->ucode_code.len) {
3088 ret = iwl3945_read_ucode(priv);
3089 if (ret) {
15b1687c 3090 IWL_ERR(priv, "Could not read microcode: %d\n", ret);
5a66926a
ZY
3091 mutex_unlock(&priv->mutex);
3092 goto out_release_irq;
3093 }
3094 }
b481de9c 3095
e655b9f0 3096 ret = __iwl3945_up(priv);
b481de9c
ZY
3097
3098 mutex_unlock(&priv->mutex);
5a66926a 3099
e655b9f0
ZY
3100 if (ret)
3101 goto out_release_irq;
3102
e1623446 3103 IWL_DEBUG_INFO(priv, "Start UP work.\n");
e655b9f0 3104
5a66926a
ZY
3105 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
3106 * mac80211 will not be run successfully. */
3107 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3108 test_bit(STATUS_READY, &priv->status),
3109 UCODE_READY_TIMEOUT);
3110 if (!ret) {
3111 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c
WT
3112 IWL_ERR(priv,
3113 "Wait for START_ALIVE timeout after %dms.\n",
3114 jiffies_to_msecs(UCODE_READY_TIMEOUT));
5a66926a
ZY
3115 ret = -ETIMEDOUT;
3116 goto out_release_irq;
3117 }
3118 }
3119
2663516d
HS
3120 /* ucode is running and will send rfkill notifications,
3121 * no need to poll the killswitch state anymore */
3122 cancel_delayed_work(&priv->rfkill_poll);
3123
e655b9f0 3124 priv->is_open = 1;
e1623446 3125 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 3126 return 0;
5a66926a
ZY
3127
3128out_release_irq:
e655b9f0 3129 priv->is_open = 0;
e1623446 3130 IWL_DEBUG_MAC80211(priv, "leave - failed\n");
5a66926a 3131 return ret;
b481de9c
ZY
3132}
3133
bb8c093b 3134static void iwl3945_mac_stop(struct ieee80211_hw *hw)
b481de9c 3135{
4a8a4322 3136 struct iwl_priv *priv = hw->priv;
b481de9c 3137
e1623446 3138 IWL_DEBUG_MAC80211(priv, "enter\n");
6ef89d0a 3139
e655b9f0 3140 if (!priv->is_open) {
e1623446 3141 IWL_DEBUG_MAC80211(priv, "leave - skip\n");
e655b9f0
ZY
3142 return;
3143 }
3144
b481de9c 3145 priv->is_open = 0;
5a66926a 3146
775a6e27 3147 if (iwl_is_ready_rf(priv)) {
e655b9f0
ZY
3148 /* stop mac, cancel any scan request and clear
3149 * RXON_FILTER_ASSOC_MSK BIT
3150 */
5a66926a 3151 mutex_lock(&priv->mutex);
af0053d6 3152 iwl_scan_cancel_timeout(priv, 100);
fde3571f 3153 mutex_unlock(&priv->mutex);
fde3571f
MA
3154 }
3155
5a66926a
ZY
3156 iwl3945_down(priv);
3157
3158 flush_workqueue(priv->workqueue);
2663516d
HS
3159
3160 /* start polling the killswitch state again */
3161 queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
3162 round_jiffies_relative(2 * HZ));
6ef89d0a 3163
e1623446 3164 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
3165}
3166
e039fa4a 3167static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 3168{
4a8a4322 3169 struct iwl_priv *priv = hw->priv;
b481de9c 3170
e1623446 3171 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3172
e1623446 3173 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 3174 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 3175
e039fa4a 3176 if (iwl3945_tx_skb(priv, skb))
b481de9c
ZY
3177 dev_kfree_skb_any(skb);
3178
e1623446 3179 IWL_DEBUG_MAC80211(priv, "leave\n");
637f8837 3180 return NETDEV_TX_OK;
b481de9c
ZY
3181}
3182
60690a6a 3183void iwl3945_config_ap(struct iwl_priv *priv)
b481de9c
ZY
3184{
3185 int rc = 0;
3186
d986bcd1 3187 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY
3188 return;
3189
3190 /* The following should be done only at AP bring up */
8ccde88a 3191 if (!(iwl_is_associated(priv))) {
b481de9c
ZY
3192
3193 /* RXON - unassoc (to set timing command) */
8ccde88a 3194 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 3195 iwlcore_commit_rxon(priv);
b481de9c
ZY
3196
3197 /* RXON Timing */
28afaf91 3198 memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
2c2f3b33 3199 iwl_setup_rxon_timing(priv);
518099a8
SO
3200 rc = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
3201 sizeof(priv->rxon_timing),
3202 &priv->rxon_timing);
b481de9c 3203 if (rc)
39aadf8c 3204 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
3205 "Attempting to continue.\n");
3206
3207 /* FIXME: what should be the assoc_id for AP? */
8ccde88a 3208 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
b481de9c 3209 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
8ccde88a 3210 priv->staging_rxon.flags |=
b481de9c
ZY
3211 RXON_FLG_SHORT_PREAMBLE_MSK;
3212 else
8ccde88a 3213 priv->staging_rxon.flags &=
b481de9c
ZY
3214 ~RXON_FLG_SHORT_PREAMBLE_MSK;
3215
8ccde88a 3216 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
b481de9c
ZY
3217 if (priv->assoc_capability &
3218 WLAN_CAPABILITY_SHORT_SLOT_TIME)
8ccde88a 3219 priv->staging_rxon.flags |=
b481de9c
ZY
3220 RXON_FLG_SHORT_SLOT_MSK;
3221 else
8ccde88a 3222 priv->staging_rxon.flags &=
b481de9c
ZY
3223 ~RXON_FLG_SHORT_SLOT_MSK;
3224
05c914fe 3225 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
8ccde88a 3226 priv->staging_rxon.flags &=
b481de9c
ZY
3227 ~RXON_FLG_SHORT_SLOT_MSK;
3228 }
3229 /* restore RXON assoc */
8ccde88a 3230 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
e0158e61 3231 iwlcore_commit_rxon(priv);
c587de0b 3232 iwl_add_station(priv, iwl_bcast_addr, 0, CMD_SYNC, NULL);
556f8db7 3233 }
bb8c093b 3234 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
3235
3236 /* FIXME - we need to add code here to detect a totally new
3237 * configuration, reset the AP, unassoc, rxon timing, assoc,
3238 * clear sta table, add BCAST sta... */
3239}
3240
bb8c093b 3241static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB
3242 struct ieee80211_vif *vif,
3243 struct ieee80211_sta *sta,
3244 struct ieee80211_key_conf *key)
b481de9c 3245{
4a8a4322 3246 struct iwl_priv *priv = hw->priv;
dc822b5d 3247 const u8 *addr;
6e21f15c
AK
3248 int ret = 0;
3249 u8 sta_id = IWL_INVALID_STATION;
3250 u8 static_key;
b481de9c 3251
e1623446 3252 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3253
df878d8f 3254 if (iwl3945_mod_params.sw_crypto) {
e1623446 3255 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY
3256 return -EOPNOTSUPP;
3257 }
3258
42986796 3259 addr = sta ? sta->addr : iwl_bcast_addr;
6e21f15c
AK
3260 static_key = !iwl_is_associated(priv);
3261
3262 if (!static_key) {
c587de0b 3263 sta_id = iwl_find_station(priv, addr);
6e21f15c 3264 if (sta_id == IWL_INVALID_STATION) {
12514396 3265 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
6e21f15c
AK
3266 addr);
3267 return -EINVAL;
3268 }
b481de9c
ZY
3269 }
3270
3271 mutex_lock(&priv->mutex);
af0053d6 3272 iwl_scan_cancel_timeout(priv, 100);
6e21f15c 3273 mutex_unlock(&priv->mutex);
15e869d8 3274
b481de9c 3275 switch (cmd) {
6e21f15c
AK
3276 case SET_KEY:
3277 if (static_key)
3278 ret = iwl3945_set_static_key(priv, key);
3279 else
3280 ret = iwl3945_set_dynamic_key(priv, key, sta_id);
3281 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY
3282 break;
3283 case DISABLE_KEY:
6e21f15c
AK
3284 if (static_key)
3285 ret = iwl3945_remove_static_key(priv);
3286 else
3287 ret = iwl3945_clear_sta_key_info(priv, sta_id);
3288 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY
3289 break;
3290 default:
42986796 3291 ret = -EINVAL;
b481de9c
ZY
3292 }
3293
e1623446 3294 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 3295
42986796 3296 return ret;
b481de9c
ZY
3297}
3298
b481de9c
ZY
3299/*****************************************************************************
3300 *
3301 * sysfs attributes
3302 *
3303 *****************************************************************************/
3304
d08853a3 3305#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
3306
3307/*
3308 * The following adds a new attribute to the sysfs representation
3309 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
3310 * used for controlling the debug level.
3311 *
3312 * See the level definitions in iwl for details.
a562a9dd 3313 *
3d816c77
RC
3314 * The debug_level being managed using sysfs below is a per device debug
3315 * level that is used instead of the global debug level if it (the per
3316 * device debug level) is set.
b481de9c 3317 */
40b8ec0b
SO
3318static ssize_t show_debug_level(struct device *d,
3319 struct device_attribute *attr, char *buf)
b481de9c 3320{
3d816c77
RC
3321 struct iwl_priv *priv = dev_get_drvdata(d);
3322 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
b481de9c 3323}
40b8ec0b
SO
3324static ssize_t store_debug_level(struct device *d,
3325 struct device_attribute *attr,
b481de9c
ZY
3326 const char *buf, size_t count)
3327{
928841b1 3328 struct iwl_priv *priv = dev_get_drvdata(d);
40b8ec0b
SO
3329 unsigned long val;
3330 int ret;
b481de9c 3331
40b8ec0b
SO
3332 ret = strict_strtoul(buf, 0, &val);
3333 if (ret)
978785a3 3334 IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf);
b481de9c 3335 else
3d816c77 3336 priv->debug_level = val;
b481de9c
ZY
3337
3338 return strnlen(buf, count);
3339}
3340
40b8ec0b
SO
3341static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
3342 show_debug_level, store_debug_level);
b481de9c 3343
d08853a3 3344#endif /* CONFIG_IWLWIFI_DEBUG */
b481de9c 3345
b481de9c
ZY
3346static ssize_t show_temperature(struct device *d,
3347 struct device_attribute *attr, char *buf)
3348{
928841b1 3349 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3350
775a6e27 3351 if (!iwl_is_alive(priv))
b481de9c
ZY
3352 return -EAGAIN;
3353
bb8c093b 3354 return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
b481de9c
ZY
3355}
3356
3357static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
3358
b481de9c
ZY
3359static ssize_t show_tx_power(struct device *d,
3360 struct device_attribute *attr, char *buf)
3361{
928841b1 3362 struct iwl_priv *priv = dev_get_drvdata(d);
62ea9c5b 3363 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
b481de9c
ZY
3364}
3365
3366static ssize_t store_tx_power(struct device *d,
3367 struct device_attribute *attr,
3368 const char *buf, size_t count)
3369{
928841b1 3370 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3371 char *p = (char *)buf;
3372 u32 val;
3373
3374 val = simple_strtoul(p, &p, 10);
3375 if (p == buf)
978785a3 3376 IWL_INFO(priv, ": %s is not in decimal form.\n", buf);
b481de9c 3377 else
bb8c093b 3378 iwl3945_hw_reg_set_txpower(priv, val);
b481de9c
ZY
3379
3380 return count;
3381}
3382
3383static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
3384
3385static ssize_t show_flags(struct device *d,
3386 struct device_attribute *attr, char *buf)
3387{
928841b1 3388 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3389
8ccde88a 3390 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
b481de9c
ZY
3391}
3392
3393static ssize_t store_flags(struct device *d,
3394 struct device_attribute *attr,
3395 const char *buf, size_t count)
3396{
928841b1 3397 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3398 u32 flags = simple_strtoul(buf, NULL, 0);
3399
3400 mutex_lock(&priv->mutex);
8ccde88a 3401 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
b481de9c 3402 /* Cancel any currently running scans... */
af0053d6 3403 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 3404 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 3405 else {
e1623446 3406 IWL_DEBUG_INFO(priv, "Committing rxon.flags = 0x%04X\n",
b481de9c 3407 flags);
8ccde88a 3408 priv->staging_rxon.flags = cpu_to_le32(flags);
e0158e61 3409 iwlcore_commit_rxon(priv);
b481de9c
ZY
3410 }
3411 }
3412 mutex_unlock(&priv->mutex);
3413
3414 return count;
3415}
3416
3417static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
3418
3419static ssize_t show_filter_flags(struct device *d,
3420 struct device_attribute *attr, char *buf)
3421{
928841b1 3422 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3423
3424 return sprintf(buf, "0x%04X\n",
8ccde88a 3425 le32_to_cpu(priv->active_rxon.filter_flags));
b481de9c
ZY
3426}
3427
3428static ssize_t store_filter_flags(struct device *d,
3429 struct device_attribute *attr,
3430 const char *buf, size_t count)
3431{
928841b1 3432 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3433 u32 filter_flags = simple_strtoul(buf, NULL, 0);
3434
3435 mutex_lock(&priv->mutex);
8ccde88a 3436 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
b481de9c 3437 /* Cancel any currently running scans... */
af0053d6 3438 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 3439 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 3440 else {
e1623446 3441 IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
b481de9c 3442 "0x%04X\n", filter_flags);
8ccde88a 3443 priv->staging_rxon.filter_flags =
b481de9c 3444 cpu_to_le32(filter_flags);
e0158e61 3445 iwlcore_commit_rxon(priv);
b481de9c
ZY
3446 }
3447 }
3448 mutex_unlock(&priv->mutex);
3449
3450 return count;
3451}
3452
3453static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
3454 store_filter_flags);
3455
c8b0e6e1 3456#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY
3457
3458static ssize_t show_measurement(struct device *d,
3459 struct device_attribute *attr, char *buf)
3460{
4a8a4322 3461 struct iwl_priv *priv = dev_get_drvdata(d);
600c0e11 3462 struct iwl_spectrum_notification measure_report;
b481de9c 3463 u32 size = sizeof(measure_report), len = 0, ofs = 0;
3ac7f146 3464 u8 *data = (u8 *)&measure_report;
b481de9c
ZY
3465 unsigned long flags;
3466
3467 spin_lock_irqsave(&priv->lock, flags);
3468 if (!(priv->measurement_status & MEASUREMENT_READY)) {
3469 spin_unlock_irqrestore(&priv->lock, flags);
3470 return 0;
3471 }
3472 memcpy(&measure_report, &priv->measure_report, size);
3473 priv->measurement_status = 0;
3474 spin_unlock_irqrestore(&priv->lock, flags);
3475
3476 while (size && (PAGE_SIZE - len)) {
3477 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3478 PAGE_SIZE - len, 1);
3479 len = strlen(buf);
3480 if (PAGE_SIZE - len)
3481 buf[len++] = '\n';
3482
3483 ofs += 16;
3484 size -= min(size, 16U);
3485 }
3486
3487 return len;
3488}
3489
3490static ssize_t store_measurement(struct device *d,
3491 struct device_attribute *attr,
3492 const char *buf, size_t count)
3493{
4a8a4322 3494 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3495 struct ieee80211_measurement_params params = {
8ccde88a 3496 .channel = le16_to_cpu(priv->active_rxon.channel),
b481de9c
ZY
3497 .start_time = cpu_to_le64(priv->last_tsf),
3498 .duration = cpu_to_le16(1),
3499 };
3500 u8 type = IWL_MEASURE_BASIC;
3501 u8 buffer[32];
3502 u8 channel;
3503
3504 if (count) {
3505 char *p = buffer;
3506 strncpy(buffer, buf, min(sizeof(buffer), count));
3507 channel = simple_strtoul(p, NULL, 0);
3508 if (channel)
3509 params.channel = channel;
3510
3511 p = buffer;
3512 while (*p && *p != ' ')
3513 p++;
3514 if (*p)
3515 type = simple_strtoul(p + 1, NULL, 0);
3516 }
3517
e1623446 3518 IWL_DEBUG_INFO(priv, "Invoking measurement of type %d on "
b481de9c 3519 "channel %d (for '%s')\n", type, params.channel, buf);
bb8c093b 3520 iwl3945_get_measurement(priv, &params, type);
b481de9c
ZY
3521
3522 return count;
3523}
3524
3525static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
3526 show_measurement, store_measurement);
c8b0e6e1 3527#endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
b481de9c 3528
b481de9c
ZY
3529static ssize_t store_retry_rate(struct device *d,
3530 struct device_attribute *attr,
3531 const char *buf, size_t count)
3532{
4a8a4322 3533 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3534
3535 priv->retry_rate = simple_strtoul(buf, NULL, 0);
3536 if (priv->retry_rate <= 0)
3537 priv->retry_rate = 1;
3538
3539 return count;
3540}
3541
3542static ssize_t show_retry_rate(struct device *d,
3543 struct device_attribute *attr, char *buf)
3544{
4a8a4322 3545 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3546 return sprintf(buf, "%d", priv->retry_rate);
3547}
3548
3549static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
3550 store_retry_rate);
3551
d25aabb0 3552
b481de9c
ZY
3553static ssize_t store_power_level(struct device *d,
3554 struct device_attribute *attr,
3555 const char *buf, size_t count)
3556{
4a8a4322 3557 struct iwl_priv *priv = dev_get_drvdata(d);
d25aabb0
WT
3558 int ret;
3559 unsigned long mode;
3560
b481de9c 3561
b481de9c
ZY
3562 mutex_lock(&priv->mutex);
3563
d25aabb0
WT
3564 ret = strict_strtoul(buf, 10, &mode);
3565 if (ret)
3566 goto out;
b481de9c 3567
d25aabb0
WT
3568 ret = iwl_power_set_user_mode(priv, mode);
3569 if (ret) {
3570 IWL_DEBUG_MAC80211(priv, "failed setting power mode.\n");
3571 goto out;
b481de9c 3572 }
d25aabb0 3573 ret = count;
b481de9c
ZY
3574
3575 out:
3576 mutex_unlock(&priv->mutex);
d25aabb0 3577 return ret;
b481de9c
ZY
3578}
3579
d25aabb0
WT
3580static ssize_t show_power_level(struct device *d,
3581 struct device_attribute *attr, char *buf)
3582{
3583 struct iwl_priv *priv = dev_get_drvdata(d);
d25aabb0
WT
3584 int level = priv->power_data.power_mode;
3585 char *p = buf;
3586
872ed190 3587 p += sprintf(p, "%d\n", level);
d25aabb0
WT
3588 return p - buf + 1;
3589}
3590
3591static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR,
3592 show_power_level, store_power_level);
3593
b481de9c
ZY
3594#define MAX_WX_STRING 80
3595
3596/* Values are in microsecond */
3597static const s32 timeout_duration[] = {
3598 350000,
3599 250000,
3600 75000,
3601 37000,
3602 25000,
3603};
3604static const s32 period_duration[] = {
3605 400000,
3606 700000,
3607 1000000,
3608 1000000,
3609 1000000
3610};
3611
b481de9c
ZY
3612static ssize_t show_channels(struct device *d,
3613 struct device_attribute *attr, char *buf)
3614{
8318d78a
JB
3615 /* all this shit doesn't belong into sysfs anyway */
3616 return 0;
b481de9c
ZY
3617}
3618
3619static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
3620
3621static ssize_t show_statistics(struct device *d,
3622 struct device_attribute *attr, char *buf)
3623{
4a8a4322 3624 struct iwl_priv *priv = dev_get_drvdata(d);
bb8c093b 3625 u32 size = sizeof(struct iwl3945_notif_statistics);
b481de9c 3626 u32 len = 0, ofs = 0;
f2c7e521 3627 u8 *data = (u8 *)&priv->statistics_39;
b481de9c
ZY
3628 int rc = 0;
3629
775a6e27 3630 if (!iwl_is_alive(priv))
b481de9c
ZY
3631 return -EAGAIN;
3632
3633 mutex_lock(&priv->mutex);
17f841cd 3634 rc = iwl_send_statistics_request(priv, 0);
b481de9c
ZY
3635 mutex_unlock(&priv->mutex);
3636
3637 if (rc) {
3638 len = sprintf(buf,
3639 "Error sending statistics request: 0x%08X\n", rc);
3640 return len;
3641 }
3642
3643 while (size && (PAGE_SIZE - len)) {
3644 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3645 PAGE_SIZE - len, 1);
3646 len = strlen(buf);
3647 if (PAGE_SIZE - len)
3648 buf[len++] = '\n';
3649
3650 ofs += 16;
3651 size -= min(size, 16U);
3652 }
3653
3654 return len;
3655}
3656
3657static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
3658
3659static ssize_t show_antenna(struct device *d,
3660 struct device_attribute *attr, char *buf)
3661{
4a8a4322 3662 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3663
775a6e27 3664 if (!iwl_is_alive(priv))
b481de9c
ZY
3665 return -EAGAIN;
3666
7e4bca5e 3667 return sprintf(buf, "%d\n", iwl3945_mod_params.antenna);
b481de9c
ZY
3668}
3669
3670static ssize_t store_antenna(struct device *d,
3671 struct device_attribute *attr,
3672 const char *buf, size_t count)
3673{
7530f85f 3674 struct iwl_priv *priv __maybe_unused = dev_get_drvdata(d);
b481de9c 3675 int ant;
b481de9c
ZY
3676
3677 if (count == 0)
3678 return 0;
3679
3680 if (sscanf(buf, "%1i", &ant) != 1) {
e1623446 3681 IWL_DEBUG_INFO(priv, "not in hex or decimal form.\n");
b481de9c
ZY
3682 return count;
3683 }
3684
3685 if ((ant >= 0) && (ant <= 2)) {
e1623446 3686 IWL_DEBUG_INFO(priv, "Setting antenna select to %d.\n", ant);
7e4bca5e 3687 iwl3945_mod_params.antenna = (enum iwl3945_antenna)ant;
b481de9c 3688 } else
e1623446 3689 IWL_DEBUG_INFO(priv, "Bad antenna select value %d.\n", ant);
b481de9c
ZY
3690
3691
3692 return count;
3693}
3694
3695static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
3696
3697static ssize_t show_status(struct device *d,
3698 struct device_attribute *attr, char *buf)
3699{
928841b1 3700 struct iwl_priv *priv = dev_get_drvdata(d);
775a6e27 3701 if (!iwl_is_alive(priv))
b481de9c
ZY
3702 return -EAGAIN;
3703 return sprintf(buf, "0x%08x\n", (int)priv->status);
3704}
3705
3706static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
3707
3708static ssize_t dump_error_log(struct device *d,
3709 struct device_attribute *attr,
3710 const char *buf, size_t count)
3711{
928841b1 3712 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3713 char *p = (char *)buf;
3714
3715 if (p[0] == '1')
928841b1 3716 iwl3945_dump_nic_error_log(priv);
b481de9c
ZY
3717
3718 return strnlen(buf, count);
3719}
3720
3721static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
3722
3723static ssize_t dump_event_log(struct device *d,
3724 struct device_attribute *attr,
3725 const char *buf, size_t count)
3726{
928841b1 3727 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3728 char *p = (char *)buf;
3729
3730 if (p[0] == '1')
928841b1 3731 iwl3945_dump_nic_event_log(priv);
b481de9c
ZY
3732
3733 return strnlen(buf, count);
3734}
3735
3736static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
3737
3738/*****************************************************************************
3739 *
a96a27f9 3740 * driver setup and tear down
b481de9c
ZY
3741 *
3742 *****************************************************************************/
3743
4a8a4322 3744static void iwl3945_setup_deferred_work(struct iwl_priv *priv)
b481de9c 3745{
d21050c7 3746 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY
3747
3748 init_waitqueue_head(&priv->wait_command_queue);
3749
bb8c093b
CH
3750 INIT_WORK(&priv->up, iwl3945_bg_up);
3751 INIT_WORK(&priv->restart, iwl3945_bg_restart);
3752 INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
bb8c093b 3753 INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
bb8c093b
CH
3754 INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
3755 INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
2663516d 3756 INIT_DELAYED_WORK(&priv->rfkill_poll, iwl3945_rfkill_poll);
77fecfb8
SO
3757 INIT_WORK(&priv->scan_completed, iwl_bg_scan_completed);
3758 INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
3759 INIT_WORK(&priv->abort_scan, iwl_bg_abort_scan);
3760 INIT_DELAYED_WORK(&priv->scan_check, iwl_bg_scan_check);
bb8c093b
CH
3761
3762 iwl3945_hw_setup_deferred_work(priv);
b481de9c
ZY
3763
3764 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
bb8c093b 3765 iwl3945_irq_tasklet, (unsigned long)priv);
b481de9c
ZY
3766}
3767
4a8a4322 3768static void iwl3945_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 3769{
bb8c093b 3770 iwl3945_hw_cancel_deferred_work(priv);
b481de9c 3771
e47eb6ad 3772 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY
3773 cancel_delayed_work(&priv->scan_check);
3774 cancel_delayed_work(&priv->alive_start);
b481de9c
ZY
3775 cancel_work_sync(&priv->beacon_update);
3776}
3777
bb8c093b 3778static struct attribute *iwl3945_sysfs_entries[] = {
b481de9c
ZY
3779 &dev_attr_antenna.attr,
3780 &dev_attr_channels.attr,
3781 &dev_attr_dump_errors.attr,
3782 &dev_attr_dump_events.attr,
3783 &dev_attr_flags.attr,
3784 &dev_attr_filter_flags.attr,
c8b0e6e1 3785#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY
3786 &dev_attr_measurement.attr,
3787#endif
3788 &dev_attr_power_level.attr,
b481de9c 3789 &dev_attr_retry_rate.attr,
b481de9c
ZY
3790 &dev_attr_statistics.attr,
3791 &dev_attr_status.attr,
3792 &dev_attr_temperature.attr,
b481de9c 3793 &dev_attr_tx_power.attr,
d08853a3 3794#ifdef CONFIG_IWLWIFI_DEBUG
40b8ec0b
SO
3795 &dev_attr_debug_level.attr,
3796#endif
b481de9c
ZY
3797 NULL
3798};
3799
bb8c093b 3800static struct attribute_group iwl3945_attribute_group = {
b481de9c 3801 .name = NULL, /* put in device directory */
bb8c093b 3802 .attrs = iwl3945_sysfs_entries,
b481de9c
ZY
3803};
3804
bb8c093b
CH
3805static struct ieee80211_ops iwl3945_hw_ops = {
3806 .tx = iwl3945_mac_tx,
3807 .start = iwl3945_mac_start,
3808 .stop = iwl3945_mac_stop,
cbb6ab94 3809 .add_interface = iwl_mac_add_interface,
d8052319 3810 .remove_interface = iwl_mac_remove_interface,
4808368d 3811 .config = iwl_mac_config,
8ccde88a 3812 .configure_filter = iwl_configure_filter,
bb8c093b 3813 .set_key = iwl3945_mac_set_key,
aa89f31e 3814 .get_tx_stats = iwl_mac_get_tx_stats,
488829f1 3815 .conf_tx = iwl_mac_conf_tx,
bd564261 3816 .reset_tsf = iwl_mac_reset_tsf,
5bbe233b 3817 .bss_info_changed = iwl_bss_info_changed,
e9dde6f6 3818 .hw_scan = iwl_mac_hw_scan
b481de9c
ZY
3819};
3820
e52119c5 3821static int iwl3945_init_drv(struct iwl_priv *priv)
90a30a02
KA
3822{
3823 int ret;
e6148917 3824 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
90a30a02
KA
3825
3826 priv->retry_rate = 1;
3827 priv->ibss_beacon = NULL;
3828
3829 spin_lock_init(&priv->lock);
90a30a02
KA
3830 spin_lock_init(&priv->sta_lock);
3831 spin_lock_init(&priv->hcmd_lock);
3832
3833 INIT_LIST_HEAD(&priv->free_frames);
3834
3835 mutex_init(&priv->mutex);
3836
3837 /* Clear the driver's (not device's) station table */
c587de0b 3838 iwl_clear_stations_table(priv);
90a30a02
KA
3839
3840 priv->data_retry_limit = -1;
3841 priv->ieee_channels = NULL;
3842 priv->ieee_rates = NULL;
3843 priv->band = IEEE80211_BAND_2GHZ;
3844
3845 priv->iw_mode = NL80211_IFTYPE_STATION;
3846
3847 iwl_reset_qos(priv);
3848
3849 priv->qos_data.qos_active = 0;
3850 priv->qos_data.qos_cap.val = 0;
3851
3852 priv->rates_mask = IWL_RATES_MASK;
d25aabb0
WT
3853 /* If power management is turned on, default to CAM mode */
3854 priv->power_mode = IWL_POWER_MODE_CAM;
62ea9c5b 3855 priv->tx_power_user_lmt = IWL_DEFAULT_TX_POWER;
90a30a02 3856
e6148917
SO
3857 if (eeprom->version < EEPROM_3945_EEPROM_VERSION) {
3858 IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n",
3859 eeprom->version);
3860 ret = -EINVAL;
3861 goto err;
3862 }
3863 ret = iwl_init_channel_map(priv);
90a30a02
KA
3864 if (ret) {
3865 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3866 goto err;
3867 }
3868
e6148917
SO
3869 /* Set up txpower settings in driver for all channels */
3870 if (iwl3945_txpower_set_from_eeprom(priv)) {
3871 ret = -EIO;
3872 goto err_free_channel_map;
3873 }
3874
534166de 3875 ret = iwlcore_init_geos(priv);
90a30a02
KA
3876 if (ret) {
3877 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3878 goto err_free_channel_map;
3879 }
534166de
SO
3880 iwl3945_init_hw_rates(priv, priv->ieee_rates);
3881
2a4ddaab
AK
3882 return 0;
3883
3884err_free_channel_map:
3885 iwl_free_channel_map(priv);
3886err:
3887 return ret;
3888}
3889
3890static int iwl3945_setup_mac(struct iwl_priv *priv)
3891{
3892 int ret;
3893 struct ieee80211_hw *hw = priv->hw;
3894
3895 hw->rate_control_algorithm = "iwl-3945-rs";
3896 hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
3897
3898 /* Tell mac80211 our characteristics */
3899 hw->flags = IEEE80211_HW_SIGNAL_DBM |
b1c6019b
MA
3900 IEEE80211_HW_NOISE_DBM |
3901 IEEE80211_HW_SPECTRUM_MGMT;
2a4ddaab
AK
3902
3903 hw->wiphy->interface_modes =
3904 BIT(NL80211_IFTYPE_STATION) |
3905 BIT(NL80211_IFTYPE_ADHOC);
3906
3907 hw->wiphy->custom_regulatory = true;
3908
37184244
LR
3909 /* Firmware does not support this */
3910 hw->wiphy->disable_beacon_hints = true;
3911
1ecf9fc1
JB
3912 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX_3945;
3913 /* we create the 802.11 header and a zero-length SSID element */
3914 hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
d60cc91a 3915
2a4ddaab
AK
3916 /* Default value; 4 EDCA QOS priorities */
3917 hw->queues = 4;
3918
534166de
SO
3919 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3920 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3921 &priv->bands[IEEE80211_BAND_2GHZ];
2a4ddaab 3922
534166de
SO
3923 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3924 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3925 &priv->bands[IEEE80211_BAND_5GHZ];
90a30a02 3926
2a4ddaab
AK
3927 ret = ieee80211_register_hw(priv->hw);
3928 if (ret) {
3929 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3930 return ret;
3931 }
3932 priv->mac80211_registered = 1;
90a30a02 3933
2a4ddaab 3934 return 0;
90a30a02
KA
3935}
3936
bb8c093b 3937static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY
3938{
3939 int err = 0;
4a8a4322 3940 struct iwl_priv *priv;
b481de9c 3941 struct ieee80211_hw *hw;
c0f20d91 3942 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
e6148917 3943 struct iwl3945_eeprom *eeprom;
0359facc 3944 unsigned long flags;
b481de9c 3945
cee53ddb
KA
3946 /***********************
3947 * 1. Allocating HW data
3948 * ********************/
3949
b481de9c
ZY
3950 /* mac80211 allocates memory for this device instance, including
3951 * space for this driver's private structure */
90a30a02 3952 hw = iwl_alloc_all(cfg, &iwl3945_hw_ops);
b481de9c 3953 if (hw == NULL) {
a3139c59 3954 printk(KERN_ERR DRV_NAME "Can not allocate network device\n");
b481de9c
ZY
3955 err = -ENOMEM;
3956 goto out;
3957 }
b481de9c 3958 priv = hw->priv;
90a30a02 3959 SET_IEEE80211_DEV(hw, &pdev->dev);
6440adb5 3960
90a30a02
KA
3961 /*
3962 * Disabling hardware scan means that mac80211 will perform scans
3963 * "the hard way", rather than using device's scan.
3964 */
df878d8f 3965 if (iwl3945_mod_params.disable_hw_scan) {
e1623446 3966 IWL_DEBUG_INFO(priv, "Disabling hw_scan\n");
40b8ec0b
SO
3967 iwl3945_hw_ops.hw_scan = NULL;
3968 }
3969
90a30a02 3970
e1623446 3971 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
90a30a02
KA
3972 priv->cfg = cfg;
3973 priv->pci_dev = pdev;
40cefda9 3974 priv->inta_mask = CSR_INI_SET_MASK;
cee53ddb 3975
d08853a3 3976#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
3977 atomic_set(&priv->restrict_refcnt, 0);
3978#endif
b481de9c 3979
cee53ddb
KA
3980 /***************************
3981 * 2. Initializing PCI bus
3982 * *************************/
b481de9c
ZY
3983 if (pci_enable_device(pdev)) {
3984 err = -ENODEV;
3985 goto out_ieee80211_free_hw;
3986 }
3987
3988 pci_set_master(pdev);
3989
284901a9 3990 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
b481de9c 3991 if (!err)
284901a9 3992 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
b481de9c 3993 if (err) {
978785a3 3994 IWL_WARN(priv, "No suitable DMA available.\n");
b481de9c
ZY
3995 goto out_pci_disable_device;
3996 }
3997
3998 pci_set_drvdata(pdev, priv);
3999 err = pci_request_regions(pdev, DRV_NAME);
4000 if (err)
4001 goto out_pci_disable_device;
6440adb5 4002
cee53ddb
KA
4003 /***********************
4004 * 3. Read REV Register
4005 * ********************/
b481de9c
ZY
4006 priv->hw_base = pci_iomap(pdev, 0, 0);
4007 if (!priv->hw_base) {
4008 err = -ENODEV;
4009 goto out_pci_release_regions;
4010 }
4011
e1623446 4012 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
b481de9c 4013 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 4014 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
b481de9c 4015
cee53ddb
KA
4016 /* We disable the RETRY_TIMEOUT register (0x41) to keep
4017 * PCI Tx retries from interfering with C3 CPU state */
4018 pci_write_config_byte(pdev, 0x41, 0x00);
b481de9c 4019
a8b50a0a
MA
4020 /* this spin lock will be used in apm_ops.init and EEPROM access
4021 * we should init now
4022 */
4023 spin_lock_init(&priv->reg_lock);
4024
90a30a02
KA
4025 /* amp init */
4026 err = priv->cfg->ops->lib->apm_ops.init(priv);
cee53ddb 4027 if (err < 0) {
d5df2a16 4028 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
90a30a02 4029 goto out_iounmap;
cee53ddb 4030 }
b481de9c 4031
cee53ddb
KA
4032 /***********************
4033 * 4. Read EEPROM
4034 * ********************/
90a30a02 4035
cee53ddb 4036 /* Read the EEPROM */
e6148917 4037 err = iwl_eeprom_init(priv);
cee53ddb 4038 if (err) {
15b1687c 4039 IWL_ERR(priv, "Unable to init EEPROM\n");
c8f16138 4040 goto out_iounmap;
cee53ddb
KA
4041 }
4042 /* MAC Address location in EEPROM same for 3945/4965 */
e6148917
SO
4043 eeprom = (struct iwl3945_eeprom *)priv->eeprom;
4044 memcpy(priv->mac_addr, eeprom->mac_address, ETH_ALEN);
e1623446 4045 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
cee53ddb 4046 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
b481de9c 4047
cee53ddb
KA
4048 /***********************
4049 * 5. Setup HW Constants
4050 * ********************/
b481de9c 4051 /* Device-specific setup */
3832ec9d 4052 if (iwl3945_hw_set_hw_params(priv)) {
15b1687c 4053 IWL_ERR(priv, "failed to set hw settings\n");
c8f16138 4054 goto out_eeprom_free;
b481de9c
ZY
4055 }
4056
cee53ddb
KA
4057 /***********************
4058 * 6. Setup priv
4059 * ********************/
cee53ddb 4060
90a30a02 4061 err = iwl3945_init_drv(priv);
b481de9c 4062 if (err) {
90a30a02 4063 IWL_ERR(priv, "initializing driver failed\n");
c8f16138 4064 goto out_unset_hw_params;
b481de9c
ZY
4065 }
4066
978785a3
TW
4067 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n",
4068 priv->cfg->name);
cee53ddb 4069
cee53ddb 4070 /***********************
09f9bf79 4071 * 7. Setup Services
cee53ddb
KA
4072 * ********************/
4073
4074 spin_lock_irqsave(&priv->lock, flags);
ed3b932e 4075 iwl_disable_interrupts(priv);
cee53ddb
KA
4076 spin_unlock_irqrestore(&priv->lock, flags);
4077
2663516d
HS
4078 pci_enable_msi(priv->pci_dev);
4079
ef850d7c
MA
4080 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
4081 IRQF_SHARED, DRV_NAME, priv);
2663516d
HS
4082 if (err) {
4083 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4084 goto out_disable_msi;
4085 }
4086
cee53ddb 4087 err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
849e0dce 4088 if (err) {
15b1687c 4089 IWL_ERR(priv, "failed to create sysfs device attributes\n");
90a30a02 4090 goto out_release_irq;
849e0dce 4091 }
849e0dce 4092
8ccde88a
SO
4093 iwl_set_rxon_channel(priv,
4094 &priv->bands[IEEE80211_BAND_2GHZ].channels[5]);
cee53ddb
KA
4095 iwl3945_setup_deferred_work(priv);
4096 iwl3945_setup_rx_handlers(priv);
4097
cee53ddb 4098 /*********************************
09f9bf79 4099 * 8. Setup and Register mac80211
cee53ddb
KA
4100 * *******************************/
4101
2a4ddaab 4102 iwl_enable_interrupts(priv);
b481de9c 4103
2a4ddaab
AK
4104 err = iwl3945_setup_mac(priv);
4105 if (err)
4106 goto out_remove_sysfs;
cee53ddb 4107
a75fbe8d
AK
4108 err = iwl_dbgfs_register(priv, DRV_NAME);
4109 if (err)
4110 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
4111
2663516d
HS
4112 /* Start monitoring the killswitch */
4113 queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
4114 2 * HZ);
4115
b481de9c
ZY
4116 return 0;
4117
cee53ddb 4118 out_remove_sysfs:
c8f16138
RC
4119 destroy_workqueue(priv->workqueue);
4120 priv->workqueue = NULL;
cee53ddb 4121 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 4122 out_release_irq:
2663516d 4123 free_irq(priv->pci_dev->irq, priv);
2663516d
HS
4124 out_disable_msi:
4125 pci_disable_msi(priv->pci_dev);
c8f16138
RC
4126 iwlcore_free_geos(priv);
4127 iwl_free_channel_map(priv);
4128 out_unset_hw_params:
4129 iwl3945_unset_hw_params(priv);
4130 out_eeprom_free:
4131 iwl_eeprom_free(priv);
b481de9c
ZY
4132 out_iounmap:
4133 pci_iounmap(pdev, priv->hw_base);
4134 out_pci_release_regions:
4135 pci_release_regions(pdev);
4136 out_pci_disable_device:
b481de9c 4137 pci_set_drvdata(pdev, NULL);
623d563e 4138 pci_disable_device(pdev);
b481de9c
ZY
4139 out_ieee80211_free_hw:
4140 ieee80211_free_hw(priv->hw);
4141 out:
4142 return err;
4143}
4144
c83dbf68 4145static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
b481de9c 4146{
4a8a4322 4147 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 4148 unsigned long flags;
b481de9c
ZY
4149
4150 if (!priv)
4151 return;
4152
e1623446 4153 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 4154
a75fbe8d
AK
4155 iwl_dbgfs_unregister(priv);
4156
b481de9c 4157 set_bit(STATUS_EXIT_PENDING, &priv->status);
b24d22b1 4158
d552bfb6
KA
4159 if (priv->mac80211_registered) {
4160 ieee80211_unregister_hw(priv->hw);
4161 priv->mac80211_registered = 0;
4162 } else {
4163 iwl3945_down(priv);
4164 }
b481de9c 4165
0359facc
MA
4166 /* make sure we flush any pending irq or
4167 * tasklet for the driver
4168 */
4169 spin_lock_irqsave(&priv->lock, flags);
ed3b932e 4170 iwl_disable_interrupts(priv);
0359facc
MA
4171 spin_unlock_irqrestore(&priv->lock, flags);
4172
4173 iwl_synchronize_irq(priv);
4174
bb8c093b 4175 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 4176
71d449b5 4177 cancel_delayed_work_sync(&priv->rfkill_poll);
2663516d 4178
bb8c093b 4179 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY
4180
4181 if (priv->rxq.bd)
df833b1d 4182 iwl3945_rx_queue_free(priv, &priv->rxq);
bb8c093b 4183 iwl3945_hw_txq_ctx_free(priv);
b481de9c 4184
3832ec9d 4185 iwl3945_unset_hw_params(priv);
c587de0b 4186 iwl_clear_stations_table(priv);
b481de9c 4187
6ef89d0a
MA
4188 /*netif_stop_queue(dev); */
4189 flush_workqueue(priv->workqueue);
4190
bb8c093b 4191 /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
b481de9c
ZY
4192 * priv->workqueue... so we can't take down the workqueue
4193 * until now... */
4194 destroy_workqueue(priv->workqueue);
4195 priv->workqueue = NULL;
4196
2663516d
HS
4197 free_irq(pdev->irq, priv);
4198 pci_disable_msi(pdev);
4199
b481de9c
ZY
4200 pci_iounmap(pdev, priv->hw_base);
4201 pci_release_regions(pdev);
4202 pci_disable_device(pdev);
4203 pci_set_drvdata(pdev, NULL);
4204
e6148917 4205 iwl_free_channel_map(priv);
534166de 4206 iwlcore_free_geos(priv);
805cee5b 4207 kfree(priv->scan);
b481de9c
ZY
4208 if (priv->ibss_beacon)
4209 dev_kfree_skb(priv->ibss_beacon);
4210
4211 ieee80211_free_hw(priv->hw);
4212}
4213
b481de9c
ZY
4214
4215/*****************************************************************************
4216 *
4217 * driver and module entry point
4218 *
4219 *****************************************************************************/
4220
bb8c093b 4221static struct pci_driver iwl3945_driver = {
b481de9c 4222 .name = DRV_NAME,
bb8c093b
CH
4223 .id_table = iwl3945_hw_card_ids,
4224 .probe = iwl3945_pci_probe,
4225 .remove = __devexit_p(iwl3945_pci_remove),
b481de9c 4226#ifdef CONFIG_PM
6da3a13e
WYG
4227 .suspend = iwl_pci_suspend,
4228 .resume = iwl_pci_resume,
b481de9c
ZY
4229#endif
4230};
4231
bb8c093b 4232static int __init iwl3945_init(void)
b481de9c
ZY
4233{
4234
4235 int ret;
4236 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
4237 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2
RC
4238
4239 ret = iwl3945_rate_control_register();
4240 if (ret) {
a3139c59
SO
4241 printk(KERN_ERR DRV_NAME
4242 "Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC
4243 return ret;
4244 }
4245
bb8c093b 4246 ret = pci_register_driver(&iwl3945_driver);
b481de9c 4247 if (ret) {
a3139c59 4248 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
897e1cf2 4249 goto error_register;
b481de9c 4250 }
b481de9c
ZY
4251
4252 return ret;
897e1cf2 4253
897e1cf2
RC
4254error_register:
4255 iwl3945_rate_control_unregister();
4256 return ret;
b481de9c
ZY
4257}
4258
bb8c093b 4259static void __exit iwl3945_exit(void)
b481de9c 4260{
bb8c093b 4261 pci_unregister_driver(&iwl3945_driver);
897e1cf2 4262 iwl3945_rate_control_unregister();
b481de9c
ZY
4263}
4264
a0987a8d 4265MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
25cb6cad 4266
df878d8f 4267module_param_named(antenna, iwl3945_mod_params.antenna, int, 0444);
b481de9c 4268MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
9c74d9fb
SO
4269module_param_named(swcrypto, iwl3945_mod_params.sw_crypto, int, 0444);
4270MODULE_PARM_DESC(swcrypto,
4271 "using software crypto (default 1 [software])\n");
a562a9dd
RC
4272#ifdef CONFIG_IWLWIFI_DEBUG
4273module_param_named(debug, iwl_debug_level, uint, 0644);
b481de9c 4274MODULE_PARM_DESC(debug, "debug output mask");
a562a9dd 4275#endif
df878d8f 4276module_param_named(disable_hw_scan, iwl3945_mod_params.disable_hw_scan, int, 0444);
b481de9c 4277MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
af48d048
SO
4278module_param_named(fw_restart3945, iwl3945_mod_params.restart_fw, int, 0444);
4279MODULE_PARM_DESC(fw_restart3945, "restart firmware in case of error");
4280
bb8c093b
CH
4281module_exit(iwl3945_exit);
4282module_init(iwl3945_init);
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