Commit | Line | Data |
---|---|---|
b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
01f8162a | 3 | * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
b481de9c ZY |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
b481de9c ZY |
32 | #include <linux/init.h> |
33 | #include <linux/pci.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/delay.h> | |
36 | #include <linux/skbuff.h> | |
37 | #include <linux/netdevice.h> | |
38 | #include <linux/wireless.h> | |
39 | #include <linux/firmware.h> | |
b481de9c ZY |
40 | #include <linux/etherdevice.h> |
41 | #include <linux/if_arp.h> | |
42 | ||
43 | #include <net/ieee80211_radiotap.h> | |
7e272fcf | 44 | #include <net/lib80211.h> |
b481de9c ZY |
45 | #include <net/mac80211.h> |
46 | ||
47 | #include <asm/div64.h> | |
48 | ||
a3139c59 SO |
49 | #define DRV_NAME "iwl3945" |
50 | ||
dbb6654c WT |
51 | #include "iwl-fh.h" |
52 | #include "iwl-3945-fh.h" | |
600c0e11 | 53 | #include "iwl-commands.h" |
17f841cd | 54 | #include "iwl-sta.h" |
b481de9c ZY |
55 | #include "iwl-3945.h" |
56 | #include "iwl-helpers.h" | |
5747d47f | 57 | #include "iwl-core.h" |
d20b3c65 | 58 | #include "iwl-dev.h" |
b481de9c | 59 | |
b481de9c ZY |
60 | /* |
61 | * module name, copyright, version, etc. | |
b481de9c ZY |
62 | */ |
63 | ||
64 | #define DRV_DESCRIPTION \ | |
65 | "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux" | |
66 | ||
d08853a3 | 67 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
68 | #define VD "d" |
69 | #else | |
70 | #define VD | |
71 | #endif | |
72 | ||
c8b0e6e1 | 73 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
74 | #define VS "s" |
75 | #else | |
76 | #define VS | |
77 | #endif | |
78 | ||
eaa686c3 | 79 | #define IWL39_VERSION "1.2.26k" VD VS |
01f8162a | 80 | #define DRV_COPYRIGHT "Copyright(c) 2003-2009 Intel Corporation" |
a7b75207 | 81 | #define DRV_AUTHOR "<ilw@linux.intel.com>" |
eaa686c3 | 82 | #define DRV_VERSION IWL39_VERSION |
b481de9c | 83 | |
b481de9c ZY |
84 | |
85 | MODULE_DESCRIPTION(DRV_DESCRIPTION); | |
86 | MODULE_VERSION(DRV_VERSION); | |
a7b75207 | 87 | MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); |
b481de9c ZY |
88 | MODULE_LICENSE("GPL"); |
89 | ||
df878d8f KA |
90 | /* module parameters */ |
91 | struct iwl_mod_params iwl3945_mod_params = { | |
92 | .num_of_queues = IWL39_MAX_NUM_QUEUES, | |
9c74d9fb | 93 | .sw_crypto = 1, |
af48d048 | 94 | .restart_fw = 1, |
df878d8f KA |
95 | /* the rest are 0 by default */ |
96 | }; | |
97 | ||
7e4bca5e SO |
98 | /** |
99 | * iwl3945_get_antenna_flags - Get antenna flags for RXON command | |
100 | * @priv: eeprom and antenna fields are used to determine antenna flags | |
101 | * | |
102 | * priv->eeprom39 is used to determine if antenna AUX/MAIN are reversed | |
103 | * iwl3945_mod_params.antenna specifies the antenna diversity mode: | |
104 | * | |
105 | * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself | |
106 | * IWL_ANTENNA_MAIN - Force MAIN antenna | |
107 | * IWL_ANTENNA_AUX - Force AUX antenna | |
108 | */ | |
109 | __le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv) | |
110 | { | |
111 | struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom; | |
112 | ||
113 | switch (iwl3945_mod_params.antenna) { | |
114 | case IWL_ANTENNA_DIVERSITY: | |
115 | return 0; | |
116 | ||
117 | case IWL_ANTENNA_MAIN: | |
118 | if (eeprom->antenna_switch_type) | |
119 | return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK; | |
120 | return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK; | |
121 | ||
122 | case IWL_ANTENNA_AUX: | |
123 | if (eeprom->antenna_switch_type) | |
124 | return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK; | |
125 | return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK; | |
126 | } | |
127 | ||
128 | /* bad antenna selector value */ | |
129 | IWL_ERR(priv, "Bad antenna selector value (0x%x)\n", | |
130 | iwl3945_mod_params.antenna); | |
131 | ||
132 | return 0; /* "diversity" is default if error */ | |
133 | } | |
134 | ||
6e21f15c | 135 | static int iwl3945_set_ccmp_dynamic_key_info(struct iwl_priv *priv, |
b481de9c ZY |
136 | struct ieee80211_key_conf *keyconf, |
137 | u8 sta_id) | |
138 | { | |
139 | unsigned long flags; | |
140 | __le16 key_flags = 0; | |
6e21f15c AK |
141 | int ret; |
142 | ||
143 | key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK); | |
144 | key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS); | |
145 | ||
146 | if (sta_id == priv->hw_params.bcast_sta_id) | |
147 | key_flags |= STA_KEY_MULTICAST_MSK; | |
148 | ||
149 | keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
150 | keyconf->hw_key_idx = keyconf->keyidx; | |
151 | key_flags &= ~STA_KEY_FLG_INVALID; | |
b481de9c | 152 | |
b481de9c | 153 | spin_lock_irqsave(&priv->sta_lock, flags); |
c587de0b TW |
154 | priv->stations[sta_id].keyinfo.alg = keyconf->alg; |
155 | priv->stations[sta_id].keyinfo.keylen = keyconf->keylen; | |
156 | memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key, | |
b481de9c ZY |
157 | keyconf->keylen); |
158 | ||
c587de0b | 159 | memcpy(priv->stations[sta_id].sta.key.key, keyconf->key, |
b481de9c | 160 | keyconf->keylen); |
6e21f15c | 161 | |
c587de0b | 162 | if ((priv->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK) |
6e21f15c | 163 | == STA_KEY_FLG_NO_ENC) |
c587de0b | 164 | priv->stations[sta_id].sta.key.key_offset = |
6e21f15c AK |
165 | iwl_get_free_ucode_key_index(priv); |
166 | /* else, we are overriding an existing key => no need to allocated room | |
167 | * in uCode. */ | |
168 | ||
c587de0b | 169 | WARN(priv->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET, |
6e21f15c AK |
170 | "no space for a new key"); |
171 | ||
c587de0b TW |
172 | priv->stations[sta_id].sta.key.key_flags = key_flags; |
173 | priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; | |
174 | priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
b481de9c | 175 | |
6e21f15c AK |
176 | IWL_DEBUG_INFO(priv, "hwcrypto: modify ucode station key info\n"); |
177 | ||
c587de0b | 178 | ret = iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC); |
6e21f15c | 179 | |
b481de9c ZY |
180 | spin_unlock_irqrestore(&priv->sta_lock, flags); |
181 | ||
6e21f15c AK |
182 | return ret; |
183 | } | |
184 | ||
185 | static int iwl3945_set_tkip_dynamic_key_info(struct iwl_priv *priv, | |
186 | struct ieee80211_key_conf *keyconf, | |
187 | u8 sta_id) | |
188 | { | |
189 | return -EOPNOTSUPP; | |
190 | } | |
191 | ||
192 | static int iwl3945_set_wep_dynamic_key_info(struct iwl_priv *priv, | |
193 | struct ieee80211_key_conf *keyconf, | |
194 | u8 sta_id) | |
195 | { | |
196 | return -EOPNOTSUPP; | |
b481de9c ZY |
197 | } |
198 | ||
4a8a4322 | 199 | static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id) |
b481de9c ZY |
200 | { |
201 | unsigned long flags; | |
202 | ||
203 | spin_lock_irqsave(&priv->sta_lock, flags); | |
c587de0b TW |
204 | memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl_hw_key)); |
205 | memset(&priv->stations[sta_id].sta.key, 0, | |
4c897253 | 206 | sizeof(struct iwl4965_keyinfo)); |
c587de0b TW |
207 | priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC; |
208 | priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; | |
209 | priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
b481de9c ZY |
210 | spin_unlock_irqrestore(&priv->sta_lock, flags); |
211 | ||
e1623446 | 212 | IWL_DEBUG_INFO(priv, "hwcrypto: clear ucode station key info\n"); |
c587de0b | 213 | iwl_send_add_sta(priv, &priv->stations[sta_id].sta, 0); |
b481de9c ZY |
214 | return 0; |
215 | } | |
216 | ||
fa11d525 | 217 | static int iwl3945_set_dynamic_key(struct iwl_priv *priv, |
6e21f15c AK |
218 | struct ieee80211_key_conf *keyconf, u8 sta_id) |
219 | { | |
220 | int ret = 0; | |
221 | ||
222 | keyconf->hw_key_idx = HW_KEY_DYNAMIC; | |
223 | ||
224 | switch (keyconf->alg) { | |
225 | case ALG_CCMP: | |
226 | ret = iwl3945_set_ccmp_dynamic_key_info(priv, keyconf, sta_id); | |
227 | break; | |
228 | case ALG_TKIP: | |
229 | ret = iwl3945_set_tkip_dynamic_key_info(priv, keyconf, sta_id); | |
230 | break; | |
231 | case ALG_WEP: | |
232 | ret = iwl3945_set_wep_dynamic_key_info(priv, keyconf, sta_id); | |
233 | break; | |
234 | default: | |
1e680233 | 235 | IWL_ERR(priv, "Unknown alg: %s alg = %d\n", __func__, keyconf->alg); |
6e21f15c AK |
236 | ret = -EINVAL; |
237 | } | |
238 | ||
239 | IWL_DEBUG_WEP(priv, "Set dynamic key: alg= %d len=%d idx=%d sta=%d ret=%d\n", | |
240 | keyconf->alg, keyconf->keylen, keyconf->keyidx, | |
241 | sta_id, ret); | |
242 | ||
243 | return ret; | |
244 | } | |
245 | ||
246 | static int iwl3945_remove_static_key(struct iwl_priv *priv) | |
247 | { | |
248 | int ret = -EOPNOTSUPP; | |
249 | ||
250 | return ret; | |
251 | } | |
252 | ||
253 | static int iwl3945_set_static_key(struct iwl_priv *priv, | |
254 | struct ieee80211_key_conf *key) | |
255 | { | |
256 | if (key->alg == ALG_WEP) | |
257 | return -EOPNOTSUPP; | |
258 | ||
259 | IWL_ERR(priv, "Static key invalid: alg %d\n", key->alg); | |
260 | return -EINVAL; | |
261 | } | |
262 | ||
4a8a4322 | 263 | static void iwl3945_clear_free_frames(struct iwl_priv *priv) |
b481de9c ZY |
264 | { |
265 | struct list_head *element; | |
266 | ||
e1623446 | 267 | IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n", |
b481de9c ZY |
268 | priv->frames_count); |
269 | ||
270 | while (!list_empty(&priv->free_frames)) { | |
271 | element = priv->free_frames.next; | |
272 | list_del(element); | |
bb8c093b | 273 | kfree(list_entry(element, struct iwl3945_frame, list)); |
b481de9c ZY |
274 | priv->frames_count--; |
275 | } | |
276 | ||
277 | if (priv->frames_count) { | |
39aadf8c | 278 | IWL_WARN(priv, "%d frames still in use. Did we lose one?\n", |
b481de9c ZY |
279 | priv->frames_count); |
280 | priv->frames_count = 0; | |
281 | } | |
282 | } | |
283 | ||
4a8a4322 | 284 | static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv) |
b481de9c | 285 | { |
bb8c093b | 286 | struct iwl3945_frame *frame; |
b481de9c ZY |
287 | struct list_head *element; |
288 | if (list_empty(&priv->free_frames)) { | |
289 | frame = kzalloc(sizeof(*frame), GFP_KERNEL); | |
290 | if (!frame) { | |
15b1687c | 291 | IWL_ERR(priv, "Could not allocate frame!\n"); |
b481de9c ZY |
292 | return NULL; |
293 | } | |
294 | ||
295 | priv->frames_count++; | |
296 | return frame; | |
297 | } | |
298 | ||
299 | element = priv->free_frames.next; | |
300 | list_del(element); | |
bb8c093b | 301 | return list_entry(element, struct iwl3945_frame, list); |
b481de9c ZY |
302 | } |
303 | ||
4a8a4322 | 304 | static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame) |
b481de9c ZY |
305 | { |
306 | memset(frame, 0, sizeof(*frame)); | |
307 | list_add(&frame->list, &priv->free_frames); | |
308 | } | |
309 | ||
4a8a4322 | 310 | unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv, |
b481de9c | 311 | struct ieee80211_hdr *hdr, |
73ec1cc2 | 312 | int left) |
b481de9c ZY |
313 | { |
314 | ||
8ccde88a | 315 | if (!iwl_is_associated(priv) || !priv->ibss_beacon || |
05c914fe JB |
316 | ((priv->iw_mode != NL80211_IFTYPE_ADHOC) && |
317 | (priv->iw_mode != NL80211_IFTYPE_AP))) | |
b481de9c ZY |
318 | return 0; |
319 | ||
320 | if (priv->ibss_beacon->len > left) | |
321 | return 0; | |
322 | ||
323 | memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len); | |
324 | ||
325 | return priv->ibss_beacon->len; | |
326 | } | |
327 | ||
4a8a4322 | 328 | static int iwl3945_send_beacon_cmd(struct iwl_priv *priv) |
b481de9c | 329 | { |
bb8c093b | 330 | struct iwl3945_frame *frame; |
b481de9c ZY |
331 | unsigned int frame_size; |
332 | int rc; | |
333 | u8 rate; | |
334 | ||
bb8c093b | 335 | frame = iwl3945_get_free_frame(priv); |
b481de9c ZY |
336 | |
337 | if (!frame) { | |
15b1687c | 338 | IWL_ERR(priv, "Could not obtain free frame buffer for beacon " |
b481de9c ZY |
339 | "command.\n"); |
340 | return -ENOMEM; | |
341 | } | |
342 | ||
8ccde88a | 343 | rate = iwl_rate_get_lowest_plcp(priv); |
b481de9c | 344 | |
bb8c093b | 345 | frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate); |
b481de9c | 346 | |
518099a8 | 347 | rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size, |
b481de9c ZY |
348 | &frame->u.cmd[0]); |
349 | ||
bb8c093b | 350 | iwl3945_free_frame(priv, frame); |
b481de9c ZY |
351 | |
352 | return rc; | |
353 | } | |
354 | ||
4a8a4322 | 355 | static void iwl3945_unset_hw_params(struct iwl_priv *priv) |
b481de9c | 356 | { |
3832ec9d | 357 | if (priv->shared_virt) |
b481de9c | 358 | pci_free_consistent(priv->pci_dev, |
bb8c093b | 359 | sizeof(struct iwl3945_shared), |
3832ec9d AK |
360 | priv->shared_virt, |
361 | priv->shared_phys); | |
b481de9c ZY |
362 | } |
363 | ||
b481de9c | 364 | #define MAX_UCODE_BEACON_INTERVAL 1024 |
c1b4aa3f | 365 | #define INTEL_CONN_LISTEN_INTERVAL cpu_to_le16(0xA) |
b481de9c | 366 | |
bb8c093b | 367 | static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val) |
b481de9c ZY |
368 | { |
369 | u16 new_val = 0; | |
370 | u16 beacon_factor = 0; | |
371 | ||
372 | beacon_factor = | |
373 | (beacon_val + MAX_UCODE_BEACON_INTERVAL) | |
374 | / MAX_UCODE_BEACON_INTERVAL; | |
375 | new_val = beacon_val / beacon_factor; | |
376 | ||
377 | return cpu_to_le16(new_val); | |
378 | } | |
379 | ||
4a8a4322 | 380 | static void iwl3945_setup_rxon_timing(struct iwl_priv *priv) |
b481de9c ZY |
381 | { |
382 | u64 interval_tm_unit; | |
383 | u64 tsf, result; | |
384 | unsigned long flags; | |
385 | struct ieee80211_conf *conf = NULL; | |
386 | u16 beacon_int = 0; | |
387 | ||
388 | conf = ieee80211_get_hw_conf(priv->hw); | |
389 | ||
390 | spin_lock_irqsave(&priv->lock, flags); | |
28afaf91 | 391 | priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp); |
b481de9c ZY |
392 | priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL; |
393 | ||
28afaf91 | 394 | tsf = priv->timestamp; |
b481de9c ZY |
395 | |
396 | beacon_int = priv->beacon_int; | |
397 | spin_unlock_irqrestore(&priv->lock, flags); | |
398 | ||
05c914fe | 399 | if (priv->iw_mode == NL80211_IFTYPE_STATION) { |
b481de9c ZY |
400 | if (beacon_int == 0) { |
401 | priv->rxon_timing.beacon_interval = cpu_to_le16(100); | |
402 | priv->rxon_timing.beacon_init_val = cpu_to_le32(102400); | |
403 | } else { | |
404 | priv->rxon_timing.beacon_interval = | |
405 | cpu_to_le16(beacon_int); | |
406 | priv->rxon_timing.beacon_interval = | |
bb8c093b | 407 | iwl3945_adjust_beacon_interval( |
b481de9c ZY |
408 | le16_to_cpu(priv->rxon_timing.beacon_interval)); |
409 | } | |
410 | ||
411 | priv->rxon_timing.atim_window = 0; | |
412 | } else { | |
413 | priv->rxon_timing.beacon_interval = | |
57c4d7b4 JB |
414 | iwl3945_adjust_beacon_interval( |
415 | priv->vif->bss_conf.beacon_int); | |
b481de9c ZY |
416 | /* TODO: we need to get atim_window from upper stack |
417 | * for now we set to 0 */ | |
418 | priv->rxon_timing.atim_window = 0; | |
419 | } | |
420 | ||
421 | interval_tm_unit = | |
422 | (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024); | |
423 | result = do_div(tsf, interval_tm_unit); | |
424 | priv->rxon_timing.beacon_init_val = | |
425 | cpu_to_le32((u32) ((u64) interval_tm_unit - result)); | |
426 | ||
e1623446 TW |
427 | IWL_DEBUG_ASSOC(priv, |
428 | "beacon interval %d beacon timer %d beacon tim %d\n", | |
b481de9c ZY |
429 | le16_to_cpu(priv->rxon_timing.beacon_interval), |
430 | le32_to_cpu(priv->rxon_timing.beacon_init_val), | |
431 | le16_to_cpu(priv->rxon_timing.atim_window)); | |
432 | } | |
433 | ||
4a8a4322 | 434 | static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv, |
e039fa4a | 435 | struct ieee80211_tx_info *info, |
c2d79b48 | 436 | struct iwl_cmd *cmd, |
b481de9c | 437 | struct sk_buff *skb_frag, |
6e21f15c | 438 | int sta_id) |
b481de9c | 439 | { |
e52119c5 | 440 | struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload; |
c587de0b | 441 | struct iwl_hw_key *keyinfo = &priv->stations[sta_id].keyinfo; |
b481de9c ZY |
442 | |
443 | switch (keyinfo->alg) { | |
444 | case ALG_CCMP: | |
e52119c5 WT |
445 | tx->sec_ctl = TX_CMD_SEC_CCM; |
446 | memcpy(tx->key, keyinfo->key, keyinfo->keylen); | |
e1623446 | 447 | IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n"); |
b481de9c ZY |
448 | break; |
449 | ||
450 | case ALG_TKIP: | |
b481de9c ZY |
451 | break; |
452 | ||
453 | case ALG_WEP: | |
e52119c5 | 454 | tx->sec_ctl = TX_CMD_SEC_WEP | |
e039fa4a | 455 | (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT; |
b481de9c ZY |
456 | |
457 | if (keyinfo->keylen == 13) | |
e52119c5 | 458 | tx->sec_ctl |= TX_CMD_SEC_KEY128; |
b481de9c | 459 | |
e52119c5 | 460 | memcpy(&tx->key[3], keyinfo->key, keyinfo->keylen); |
b481de9c | 461 | |
e1623446 | 462 | IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption " |
e039fa4a | 463 | "with key %d\n", info->control.hw_key->hw_key_idx); |
b481de9c ZY |
464 | break; |
465 | ||
b481de9c | 466 | default: |
978785a3 | 467 | IWL_ERR(priv, "Unknown encode alg %d\n", keyinfo->alg); |
b481de9c ZY |
468 | break; |
469 | } | |
470 | } | |
471 | ||
472 | /* | |
473 | * handle build REPLY_TX command notification. | |
474 | */ | |
4a8a4322 | 475 | static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv, |
c2d79b48 | 476 | struct iwl_cmd *cmd, |
e039fa4a | 477 | struct ieee80211_tx_info *info, |
e52119c5 | 478 | struct ieee80211_hdr *hdr, u8 std_id) |
b481de9c | 479 | { |
e52119c5 WT |
480 | struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload; |
481 | __le32 tx_flags = tx->tx_flags; | |
fd7c8a40 | 482 | __le16 fc = hdr->frame_control; |
e6a9854b | 483 | u8 rc_flags = info->control.rates[0].flags; |
b481de9c | 484 | |
e52119c5 | 485 | tx->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; |
e039fa4a | 486 | if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { |
b481de9c | 487 | tx_flags |= TX_CMD_FLG_ACK_MSK; |
fd7c8a40 | 488 | if (ieee80211_is_mgmt(fc)) |
b481de9c | 489 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; |
fd7c8a40 | 490 | if (ieee80211_is_probe_resp(fc) && |
b481de9c ZY |
491 | !(le16_to_cpu(hdr->seq_ctrl) & 0xf)) |
492 | tx_flags |= TX_CMD_FLG_TSF_MSK; | |
493 | } else { | |
494 | tx_flags &= (~TX_CMD_FLG_ACK_MSK); | |
495 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
496 | } | |
497 | ||
e52119c5 | 498 | tx->sta_id = std_id; |
8b7b1e05 | 499 | if (ieee80211_has_morefrags(fc)) |
b481de9c ZY |
500 | tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK; |
501 | ||
fd7c8a40 HH |
502 | if (ieee80211_is_data_qos(fc)) { |
503 | u8 *qc = ieee80211_get_qos_ctl(hdr); | |
e52119c5 | 504 | tx->tid_tspec = qc[0] & 0xf; |
b481de9c | 505 | tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK; |
54dbb525 | 506 | } else { |
b481de9c | 507 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; |
54dbb525 | 508 | } |
b481de9c | 509 | |
e6a9854b | 510 | if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) { |
b481de9c ZY |
511 | tx_flags |= TX_CMD_FLG_RTS_MSK; |
512 | tx_flags &= ~TX_CMD_FLG_CTS_MSK; | |
e6a9854b | 513 | } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { |
b481de9c ZY |
514 | tx_flags &= ~TX_CMD_FLG_RTS_MSK; |
515 | tx_flags |= TX_CMD_FLG_CTS_MSK; | |
516 | } | |
517 | ||
518 | if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK)) | |
519 | tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK; | |
520 | ||
521 | tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK); | |
fd7c8a40 HH |
522 | if (ieee80211_is_mgmt(fc)) { |
523 | if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc)) | |
e52119c5 | 524 | tx->timeout.pm_frame_timeout = cpu_to_le16(3); |
b481de9c | 525 | else |
e52119c5 | 526 | tx->timeout.pm_frame_timeout = cpu_to_le16(2); |
ab53d8af | 527 | } else { |
e52119c5 | 528 | tx->timeout.pm_frame_timeout = 0; |
5c8df2d5 | 529 | #ifdef CONFIG_IWLWIFI_LEDS |
ab53d8af MA |
530 | priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len); |
531 | #endif | |
532 | } | |
b481de9c | 533 | |
e52119c5 WT |
534 | tx->driver_txop = 0; |
535 | tx->tx_flags = tx_flags; | |
536 | tx->next_frame_len = 0; | |
b481de9c ZY |
537 | } |
538 | ||
b481de9c ZY |
539 | /* |
540 | * start REPLY_TX command process | |
541 | */ | |
4a8a4322 | 542 | static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb) |
b481de9c ZY |
543 | { |
544 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
e039fa4a | 545 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
e52119c5 | 546 | struct iwl3945_tx_cmd *tx; |
188cf6c7 | 547 | struct iwl_tx_queue *txq = NULL; |
d20b3c65 | 548 | struct iwl_queue *q = NULL; |
e52119c5 | 549 | struct iwl_cmd *out_cmd = NULL; |
b481de9c ZY |
550 | dma_addr_t phys_addr; |
551 | dma_addr_t txcmd_phys; | |
e52119c5 | 552 | int txq_id = skb_get_queue_mapping(skb); |
df833b1d | 553 | u16 len, idx, len_org, hdr_len; /* TODO: len_org is not used */ |
54dbb525 TW |
554 | u8 id; |
555 | u8 unicast; | |
b481de9c | 556 | u8 sta_id; |
54dbb525 | 557 | u8 tid = 0; |
b481de9c | 558 | u16 seq_number = 0; |
fd7c8a40 | 559 | __le16 fc; |
b481de9c | 560 | u8 wait_write_ptr = 0; |
54dbb525 | 561 | u8 *qc = NULL; |
b481de9c ZY |
562 | unsigned long flags; |
563 | int rc; | |
564 | ||
565 | spin_lock_irqsave(&priv->lock, flags); | |
775a6e27 | 566 | if (iwl_is_rfkill(priv)) { |
e1623446 | 567 | IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n"); |
b481de9c ZY |
568 | goto drop_unlock; |
569 | } | |
570 | ||
e039fa4a | 571 | if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) { |
15b1687c | 572 | IWL_ERR(priv, "ERROR: No TX rate available.\n"); |
b481de9c ZY |
573 | goto drop_unlock; |
574 | } | |
575 | ||
576 | unicast = !is_multicast_ether_addr(hdr->addr1); | |
577 | id = 0; | |
578 | ||
fd7c8a40 | 579 | fc = hdr->frame_control; |
b481de9c | 580 | |
d08853a3 | 581 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c | 582 | if (ieee80211_is_auth(fc)) |
e1623446 | 583 | IWL_DEBUG_TX(priv, "Sending AUTH frame\n"); |
fd7c8a40 | 584 | else if (ieee80211_is_assoc_req(fc)) |
e1623446 | 585 | IWL_DEBUG_TX(priv, "Sending ASSOC frame\n"); |
fd7c8a40 | 586 | else if (ieee80211_is_reassoc_req(fc)) |
e1623446 | 587 | IWL_DEBUG_TX(priv, "Sending REASSOC frame\n"); |
b481de9c ZY |
588 | #endif |
589 | ||
7878a5a4 | 590 | /* drop all data frame if we are not associated */ |
914233d6 | 591 | if (ieee80211_is_data(fc) && |
279b05d4 | 592 | (!iwl_is_monitor_mode(priv)) && /* packet injection */ |
8ccde88a | 593 | (!iwl_is_associated(priv) || |
05c914fe | 594 | ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) { |
e1623446 | 595 | IWL_DEBUG_DROP(priv, "Dropping - !iwl_is_associated\n"); |
b481de9c ZY |
596 | goto drop_unlock; |
597 | } | |
598 | ||
599 | spin_unlock_irqrestore(&priv->lock, flags); | |
600 | ||
7294ec95 | 601 | hdr_len = ieee80211_hdrlen(fc); |
6440adb5 CB |
602 | |
603 | /* Find (or create) index into station table for destination station */ | |
f5d30266 | 604 | sta_id = iwl_get_sta_id(priv, hdr); |
b481de9c | 605 | if (sta_id == IWL_INVALID_STATION) { |
e1623446 | 606 | IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n", |
e174961c | 607 | hdr->addr1); |
b481de9c ZY |
608 | goto drop; |
609 | } | |
610 | ||
e1623446 | 611 | IWL_DEBUG_RATE(priv, "station Id %d\n", sta_id); |
b481de9c | 612 | |
fd7c8a40 HH |
613 | if (ieee80211_is_data_qos(fc)) { |
614 | qc = ieee80211_get_qos_ctl(hdr); | |
7294ec95 | 615 | tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; |
c587de0b | 616 | seq_number = priv->stations[sta_id].tid[tid].seq_number & |
b481de9c ZY |
617 | IEEE80211_SCTL_SEQ; |
618 | hdr->seq_ctrl = cpu_to_le16(seq_number) | | |
619 | (hdr->seq_ctrl & | |
c1b4aa3f | 620 | cpu_to_le16(IEEE80211_SCTL_FRAG)); |
b481de9c ZY |
621 | seq_number += 0x10; |
622 | } | |
6440adb5 CB |
623 | |
624 | /* Descriptor for chosen Tx queue */ | |
188cf6c7 | 625 | txq = &priv->txq[txq_id]; |
b481de9c ZY |
626 | q = &txq->q; |
627 | ||
628 | spin_lock_irqsave(&priv->lock, flags); | |
629 | ||
fc4b6853 | 630 | idx = get_cmd_index(q, q->write_ptr, 0); |
b481de9c | 631 | |
6440adb5 | 632 | /* Set up driver data for this TFD */ |
dbb6654c | 633 | memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info)); |
fc4b6853 | 634 | txq->txb[q->write_ptr].skb[0] = skb; |
6440adb5 CB |
635 | |
636 | /* Init first empty entry in queue's array of Tx/cmd buffers */ | |
188cf6c7 | 637 | out_cmd = txq->cmd[idx]; |
e52119c5 | 638 | tx = (struct iwl3945_tx_cmd *)out_cmd->cmd.payload; |
b481de9c | 639 | memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr)); |
e52119c5 | 640 | memset(tx, 0, sizeof(*tx)); |
6440adb5 CB |
641 | |
642 | /* | |
643 | * Set up the Tx-command (not MAC!) header. | |
644 | * Store the chosen Tx queue and TFD index within the sequence field; | |
645 | * after Tx, uCode's Tx response will return this value so driver can | |
646 | * locate the frame within the tx queue and do post-tx processing. | |
647 | */ | |
b481de9c ZY |
648 | out_cmd->hdr.cmd = REPLY_TX; |
649 | out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
fc4b6853 | 650 | INDEX_TO_SEQ(q->write_ptr))); |
6440adb5 CB |
651 | |
652 | /* Copy MAC header from skb into command buffer */ | |
e52119c5 | 653 | memcpy(tx->hdr, hdr, hdr_len); |
b481de9c | 654 | |
df833b1d RC |
655 | |
656 | if (info->control.hw_key) | |
657 | iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, sta_id); | |
658 | ||
659 | /* TODO need this for burst mode later on */ | |
660 | iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, sta_id); | |
661 | ||
662 | /* set is_hcca to 0; it probably will never be implemented */ | |
663 | iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0); | |
664 | ||
665 | /* Total # bytes to be transmitted */ | |
666 | len = (u16)skb->len; | |
667 | tx->len = cpu_to_le16(len); | |
668 | ||
669 | ||
670 | tx->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK; | |
671 | tx->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK; | |
672 | ||
673 | if (!ieee80211_has_morefrags(hdr->frame_control)) { | |
674 | txq->need_update = 1; | |
675 | if (qc) | |
c587de0b | 676 | priv->stations[sta_id].tid[tid].seq_number = seq_number; |
df833b1d RC |
677 | } else { |
678 | wait_write_ptr = 1; | |
679 | txq->need_update = 0; | |
680 | } | |
681 | ||
682 | IWL_DEBUG_TX(priv, "sequence nr = 0X%x \n", | |
683 | le16_to_cpu(out_cmd->hdr.sequence)); | |
684 | IWL_DEBUG_TX(priv, "tx_flags = 0X%x \n", le32_to_cpu(tx->tx_flags)); | |
685 | iwl_print_hex_dump(priv, IWL_DL_TX, tx, sizeof(*tx)); | |
686 | iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx->hdr, | |
687 | ieee80211_hdrlen(fc)); | |
688 | ||
6440adb5 CB |
689 | /* |
690 | * Use the first empty entry in this queue's command buffer array | |
691 | * to contain the Tx command and MAC header concatenated together | |
692 | * (payload data will be in another buffer). | |
693 | * Size of this varies, due to varying MAC header length. | |
694 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
695 | * of the MAC header (device reads on dword boundaries). | |
696 | * We'll tell device about this padding later. | |
697 | */ | |
3832ec9d | 698 | len = sizeof(struct iwl3945_tx_cmd) + |
4c897253 | 699 | sizeof(struct iwl_cmd_header) + hdr_len; |
b481de9c ZY |
700 | |
701 | len_org = len; | |
702 | len = (len + 3) & ~3; | |
703 | ||
704 | if (len_org != len) | |
705 | len_org = 1; | |
706 | else | |
707 | len_org = 0; | |
708 | ||
6440adb5 CB |
709 | /* Physical address of this Tx command's header (not MAC header!), |
710 | * within command buffer array. */ | |
df833b1d RC |
711 | txcmd_phys = pci_map_single(priv->pci_dev, &out_cmd->hdr, |
712 | len, PCI_DMA_TODEVICE); | |
713 | /* we do not map meta data ... so we can safely access address to | |
714 | * provide to unmap command*/ | |
188cf6c7 | 715 | pci_unmap_addr_set(&out_cmd->meta, mapping, txcmd_phys); |
df833b1d | 716 | pci_unmap_len_set(&out_cmd->meta, len, len); |
b481de9c | 717 | |
6440adb5 CB |
718 | /* Add buffer containing Tx command and MAC(!) header to TFD's |
719 | * first entry */ | |
7aaa1d79 SO |
720 | priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, |
721 | txcmd_phys, len, 1, 0); | |
b481de9c | 722 | |
b481de9c | 723 | |
6440adb5 CB |
724 | /* Set up TFD's 2nd entry to point directly to remainder of skb, |
725 | * if any (802.11 null frames have no payload). */ | |
b481de9c ZY |
726 | len = skb->len - hdr_len; |
727 | if (len) { | |
728 | phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len, | |
729 | len, PCI_DMA_TODEVICE); | |
7aaa1d79 SO |
730 | priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, |
731 | phys_addr, len, | |
732 | 0, U32_PAD(len)); | |
b481de9c ZY |
733 | } |
734 | ||
b481de9c | 735 | |
6440adb5 | 736 | /* Tell device the write index *just past* this latest filled TFD */ |
c54b679d | 737 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); |
4f3602c8 | 738 | rc = iwl_txq_update_write_ptr(priv, txq); |
b481de9c ZY |
739 | spin_unlock_irqrestore(&priv->lock, flags); |
740 | ||
741 | if (rc) | |
742 | return rc; | |
743 | ||
d20b3c65 | 744 | if ((iwl_queue_space(q) < q->high_mark) |
b481de9c ZY |
745 | && priv->mac80211_registered) { |
746 | if (wait_write_ptr) { | |
747 | spin_lock_irqsave(&priv->lock, flags); | |
748 | txq->need_update = 1; | |
4f3602c8 | 749 | iwl_txq_update_write_ptr(priv, txq); |
b481de9c ZY |
750 | spin_unlock_irqrestore(&priv->lock, flags); |
751 | } | |
752 | ||
e4e72fb4 | 753 | iwl_stop_queue(priv, skb_get_queue_mapping(skb)); |
b481de9c ZY |
754 | } |
755 | ||
756 | return 0; | |
757 | ||
758 | drop_unlock: | |
759 | spin_unlock_irqrestore(&priv->lock, flags); | |
760 | drop: | |
761 | return -1; | |
762 | } | |
763 | ||
c8b0e6e1 | 764 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
765 | |
766 | #include "iwl-spectrum.h" | |
767 | ||
768 | #define BEACON_TIME_MASK_LOW 0x00FFFFFF | |
769 | #define BEACON_TIME_MASK_HIGH 0xFF000000 | |
770 | #define TIME_UNIT 1024 | |
771 | ||
772 | /* | |
773 | * extended beacon time format | |
774 | * time in usec will be changed into a 32-bit value in 8:24 format | |
775 | * the high 1 byte is the beacon counts | |
776 | * the lower 3 bytes is the time in usec within one beacon interval | |
777 | */ | |
778 | ||
bb8c093b | 779 | static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval) |
b481de9c ZY |
780 | { |
781 | u32 quot; | |
782 | u32 rem; | |
783 | u32 interval = beacon_interval * 1024; | |
784 | ||
785 | if (!interval || !usec) | |
786 | return 0; | |
787 | ||
788 | quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24); | |
789 | rem = (usec % interval) & BEACON_TIME_MASK_LOW; | |
790 | ||
791 | return (quot << 24) + rem; | |
792 | } | |
793 | ||
794 | /* base is usually what we get from ucode with each received frame, | |
795 | * the same as HW timer counter counting down | |
796 | */ | |
797 | ||
bb8c093b | 798 | static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval) |
b481de9c ZY |
799 | { |
800 | u32 base_low = base & BEACON_TIME_MASK_LOW; | |
801 | u32 addon_low = addon & BEACON_TIME_MASK_LOW; | |
802 | u32 interval = beacon_interval * TIME_UNIT; | |
803 | u32 res = (base & BEACON_TIME_MASK_HIGH) + | |
804 | (addon & BEACON_TIME_MASK_HIGH); | |
805 | ||
806 | if (base_low > addon_low) | |
807 | res += base_low - addon_low; | |
808 | else if (base_low < addon_low) { | |
809 | res += interval + base_low - addon_low; | |
810 | res += (1 << 24); | |
811 | } else | |
812 | res += (1 << 24); | |
813 | ||
814 | return cpu_to_le32(res); | |
815 | } | |
816 | ||
4a8a4322 | 817 | static int iwl3945_get_measurement(struct iwl_priv *priv, |
b481de9c ZY |
818 | struct ieee80211_measurement_params *params, |
819 | u8 type) | |
820 | { | |
600c0e11 | 821 | struct iwl_spectrum_cmd spectrum; |
3d24a9f7 | 822 | struct iwl_rx_packet *res; |
c2d79b48 | 823 | struct iwl_host_cmd cmd = { |
b481de9c ZY |
824 | .id = REPLY_SPECTRUM_MEASUREMENT_CMD, |
825 | .data = (void *)&spectrum, | |
826 | .meta.flags = CMD_WANT_SKB, | |
827 | }; | |
828 | u32 add_time = le64_to_cpu(params->start_time); | |
829 | int rc; | |
830 | int spectrum_resp_status; | |
831 | int duration = le16_to_cpu(params->duration); | |
832 | ||
8ccde88a | 833 | if (iwl_is_associated(priv)) |
b481de9c | 834 | add_time = |
bb8c093b | 835 | iwl3945_usecs_to_beacons( |
b481de9c ZY |
836 | le64_to_cpu(params->start_time) - priv->last_tsf, |
837 | le16_to_cpu(priv->rxon_timing.beacon_interval)); | |
838 | ||
839 | memset(&spectrum, 0, sizeof(spectrum)); | |
840 | ||
841 | spectrum.channel_count = cpu_to_le16(1); | |
842 | spectrum.flags = | |
843 | RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK; | |
844 | spectrum.filter_flags = MEASUREMENT_FILTER_FLAG; | |
845 | cmd.len = sizeof(spectrum); | |
846 | spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len)); | |
847 | ||
8ccde88a | 848 | if (iwl_is_associated(priv)) |
b481de9c | 849 | spectrum.start_time = |
bb8c093b | 850 | iwl3945_add_beacon_time(priv->last_beacon_time, |
b481de9c ZY |
851 | add_time, |
852 | le16_to_cpu(priv->rxon_timing.beacon_interval)); | |
853 | else | |
854 | spectrum.start_time = 0; | |
855 | ||
856 | spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT); | |
857 | spectrum.channels[0].channel = params->channel; | |
858 | spectrum.channels[0].type = type; | |
8ccde88a | 859 | if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK) |
b481de9c ZY |
860 | spectrum.flags |= RXON_FLG_BAND_24G_MSK | |
861 | RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK; | |
862 | ||
518099a8 | 863 | rc = iwl_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
864 | if (rc) |
865 | return rc; | |
866 | ||
3d24a9f7 | 867 | res = (struct iwl_rx_packet *)cmd.meta.u.skb->data; |
b481de9c | 868 | if (res->hdr.flags & IWL_CMD_FAILED_MSK) { |
15b1687c | 869 | IWL_ERR(priv, "Bad return from REPLY_RX_ON_ASSOC command\n"); |
b481de9c ZY |
870 | rc = -EIO; |
871 | } | |
872 | ||
873 | spectrum_resp_status = le16_to_cpu(res->u.spectrum.status); | |
874 | switch (spectrum_resp_status) { | |
875 | case 0: /* Command will be handled */ | |
876 | if (res->u.spectrum.id != 0xff) { | |
e1623446 | 877 | IWL_DEBUG_INFO(priv, "Replaced existing measurement: %d\n", |
bc434dd2 | 878 | res->u.spectrum.id); |
b481de9c ZY |
879 | priv->measurement_status &= ~MEASUREMENT_READY; |
880 | } | |
881 | priv->measurement_status |= MEASUREMENT_ACTIVE; | |
882 | rc = 0; | |
883 | break; | |
884 | ||
885 | case 1: /* Command will not be handled */ | |
886 | rc = -EAGAIN; | |
887 | break; | |
888 | } | |
889 | ||
890 | dev_kfree_skb_any(cmd.meta.u.skb); | |
891 | ||
892 | return rc; | |
893 | } | |
894 | #endif | |
895 | ||
4a8a4322 | 896 | static void iwl3945_rx_reply_alive(struct iwl_priv *priv, |
6100b588 | 897 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 898 | { |
3d24a9f7 TW |
899 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
900 | struct iwl_alive_resp *palive; | |
b481de9c ZY |
901 | struct delayed_work *pwork; |
902 | ||
903 | palive = &pkt->u.alive_frame; | |
904 | ||
e1623446 | 905 | IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision " |
b481de9c ZY |
906 | "0x%01X 0x%01X\n", |
907 | palive->is_valid, palive->ver_type, | |
908 | palive->ver_subtype); | |
909 | ||
910 | if (palive->ver_subtype == INITIALIZE_SUBTYPE) { | |
e1623446 | 911 | IWL_DEBUG_INFO(priv, "Initialization Alive received.\n"); |
3d24a9f7 TW |
912 | memcpy(&priv->card_alive_init, &pkt->u.alive_frame, |
913 | sizeof(struct iwl_alive_resp)); | |
b481de9c ZY |
914 | pwork = &priv->init_alive_start; |
915 | } else { | |
e1623446 | 916 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c | 917 | memcpy(&priv->card_alive, &pkt->u.alive_frame, |
3d24a9f7 | 918 | sizeof(struct iwl_alive_resp)); |
b481de9c | 919 | pwork = &priv->alive_start; |
bb8c093b | 920 | iwl3945_disable_events(priv); |
b481de9c ZY |
921 | } |
922 | ||
923 | /* We delay the ALIVE response by 5ms to | |
924 | * give the HW RF Kill time to activate... */ | |
925 | if (palive->is_valid == UCODE_VALID_OK) | |
926 | queue_delayed_work(priv->workqueue, pwork, | |
927 | msecs_to_jiffies(5)); | |
928 | else | |
39aadf8c | 929 | IWL_WARN(priv, "uCode did not respond OK.\n"); |
b481de9c ZY |
930 | } |
931 | ||
4a8a4322 | 932 | static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv, |
6100b588 | 933 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 934 | { |
c7e035a9 | 935 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d24a9f7 | 936 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
c7e035a9 | 937 | #endif |
b481de9c | 938 | |
e1623446 | 939 | IWL_DEBUG_RX(priv, "Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status); |
b481de9c ZY |
940 | return; |
941 | } | |
942 | ||
bb8c093b | 943 | static void iwl3945_bg_beacon_update(struct work_struct *work) |
b481de9c | 944 | { |
4a8a4322 AK |
945 | struct iwl_priv *priv = |
946 | container_of(work, struct iwl_priv, beacon_update); | |
b481de9c ZY |
947 | struct sk_buff *beacon; |
948 | ||
949 | /* Pull updated AP beacon from mac80211. will fail if not in AP mode */ | |
e039fa4a | 950 | beacon = ieee80211_beacon_get(priv->hw, priv->vif); |
b481de9c ZY |
951 | |
952 | if (!beacon) { | |
15b1687c | 953 | IWL_ERR(priv, "update beacon failed\n"); |
b481de9c ZY |
954 | return; |
955 | } | |
956 | ||
957 | mutex_lock(&priv->mutex); | |
958 | /* new beacon skb is allocated every time; dispose previous.*/ | |
959 | if (priv->ibss_beacon) | |
960 | dev_kfree_skb(priv->ibss_beacon); | |
961 | ||
962 | priv->ibss_beacon = beacon; | |
963 | mutex_unlock(&priv->mutex); | |
964 | ||
bb8c093b | 965 | iwl3945_send_beacon_cmd(priv); |
b481de9c ZY |
966 | } |
967 | ||
4a8a4322 | 968 | static void iwl3945_rx_beacon_notif(struct iwl_priv *priv, |
6100b588 | 969 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 970 | { |
d08853a3 | 971 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d24a9f7 | 972 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
bb8c093b | 973 | struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status); |
b481de9c ZY |
974 | u8 rate = beacon->beacon_notify_hdr.rate; |
975 | ||
e1623446 | 976 | IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d " |
b481de9c ZY |
977 | "tsf %d %d rate %d\n", |
978 | le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK, | |
979 | beacon->beacon_notify_hdr.failure_frame, | |
980 | le32_to_cpu(beacon->ibss_mgr_status), | |
981 | le32_to_cpu(beacon->high_tsf), | |
982 | le32_to_cpu(beacon->low_tsf), rate); | |
983 | #endif | |
984 | ||
05c914fe | 985 | if ((priv->iw_mode == NL80211_IFTYPE_AP) && |
b481de9c ZY |
986 | (!test_bit(STATUS_EXIT_PENDING, &priv->status))) |
987 | queue_work(priv->workqueue, &priv->beacon_update); | |
988 | } | |
989 | ||
b481de9c ZY |
990 | /* Handle notification from uCode that card's power state is changing |
991 | * due to software, hardware, or critical temperature RFKILL */ | |
4a8a4322 | 992 | static void iwl3945_rx_card_state_notif(struct iwl_priv *priv, |
6100b588 | 993 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 994 | { |
3d24a9f7 | 995 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
996 | u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); |
997 | unsigned long status = priv->status; | |
998 | ||
e1623446 | 999 | IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n", |
b481de9c ZY |
1000 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", |
1001 | (flags & SW_CARD_DISABLED) ? "Kill" : "On"); | |
1002 | ||
5d49f498 | 1003 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c ZY |
1004 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
1005 | ||
1006 | if (flags & HW_CARD_DISABLED) | |
1007 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
1008 | else | |
1009 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
1010 | ||
1011 | ||
af0053d6 | 1012 | iwl_scan_cancel(priv); |
b481de9c ZY |
1013 | |
1014 | if ((test_bit(STATUS_RF_KILL_HW, &status) != | |
a60e77e5 JB |
1015 | test_bit(STATUS_RF_KILL_HW, &priv->status))) |
1016 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, | |
1017 | test_bit(STATUS_RF_KILL_HW, &priv->status)); | |
b481de9c ZY |
1018 | else |
1019 | wake_up_interruptible(&priv->wait_command_queue); | |
1020 | } | |
1021 | ||
1022 | /** | |
bb8c093b | 1023 | * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks |
b481de9c ZY |
1024 | * |
1025 | * Setup the RX handlers for each of the reply types sent from the uCode | |
1026 | * to the host. | |
1027 | * | |
1028 | * This function chains into the hardware specific files for them to setup | |
1029 | * any hardware specific handlers as well. | |
1030 | */ | |
4a8a4322 | 1031 | static void iwl3945_setup_rx_handlers(struct iwl_priv *priv) |
b481de9c | 1032 | { |
bb8c093b CH |
1033 | priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive; |
1034 | priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta; | |
261b9c33 | 1035 | priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error; |
8ccde88a | 1036 | priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa; |
030f05ed | 1037 | priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif; |
b481de9c | 1038 | priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] = |
030f05ed | 1039 | iwl_rx_pm_debug_statistics_notif; |
bb8c093b | 1040 | priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif; |
b481de9c | 1041 | |
9fbab516 BC |
1042 | /* |
1043 | * The same handler is used for both the REPLY to a discrete | |
1044 | * statistics request from the host as well as for the periodic | |
1045 | * statistics notifications (after received beacons) from the uCode. | |
b481de9c | 1046 | */ |
bb8c093b CH |
1047 | priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics; |
1048 | priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics; | |
b481de9c | 1049 | |
261b9c33 | 1050 | iwl_setup_spectrum_handlers(priv); |
cade0eb2 | 1051 | iwl_setup_rx_scan_handlers(priv); |
bb8c093b | 1052 | priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif; |
b481de9c | 1053 | |
9fbab516 | 1054 | /* Set up hardware specific Rx handlers */ |
bb8c093b | 1055 | iwl3945_hw_rx_handler_setup(priv); |
b481de9c ZY |
1056 | } |
1057 | ||
b481de9c ZY |
1058 | /************************** RX-FUNCTIONS ****************************/ |
1059 | /* | |
1060 | * Rx theory of operation | |
1061 | * | |
1062 | * The host allocates 32 DMA target addresses and passes the host address | |
1063 | * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is | |
1064 | * 0 to 31 | |
1065 | * | |
1066 | * Rx Queue Indexes | |
1067 | * The host/firmware share two index registers for managing the Rx buffers. | |
1068 | * | |
1069 | * The READ index maps to the first position that the firmware may be writing | |
1070 | * to -- the driver can read up to (but not including) this position and get | |
1071 | * good data. | |
1072 | * The READ index is managed by the firmware once the card is enabled. | |
1073 | * | |
1074 | * The WRITE index maps to the last position the driver has read from -- the | |
1075 | * position preceding WRITE is the last slot the firmware can place a packet. | |
1076 | * | |
1077 | * The queue is empty (no good data) if WRITE = READ - 1, and is full if | |
1078 | * WRITE = READ. | |
1079 | * | |
9fbab516 | 1080 | * During initialization, the host sets up the READ queue position to the first |
b481de9c ZY |
1081 | * INDEX position, and WRITE to the last (READ - 1 wrapped) |
1082 | * | |
9fbab516 | 1083 | * When the firmware places a packet in a buffer, it will advance the READ index |
b481de9c ZY |
1084 | * and fire the RX interrupt. The driver can then query the READ index and |
1085 | * process as many packets as possible, moving the WRITE index forward as it | |
1086 | * resets the Rx queue buffers with new memory. | |
1087 | * | |
1088 | * The management in the driver is as follows: | |
1089 | * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When | |
1090 | * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled | |
01ebd063 | 1091 | * to replenish the iwl->rxq->rx_free. |
bb8c093b | 1092 | * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the |
b481de9c ZY |
1093 | * iwl->rxq is replenished and the READ INDEX is updated (updating the |
1094 | * 'processed' and 'read' driver indexes as well) | |
1095 | * + A received packet is processed and handed to the kernel network stack, | |
1096 | * detached from the iwl->rxq. The driver 'processed' index is updated. | |
1097 | * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free | |
1098 | * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ | |
1099 | * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there | |
1100 | * were enough free buffers and RX_STALLED is set it is cleared. | |
1101 | * | |
1102 | * | |
1103 | * Driver sequence: | |
1104 | * | |
9fbab516 | 1105 | * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls |
bb8c093b | 1106 | * iwl3945_rx_queue_restock |
9fbab516 | 1107 | * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx |
b481de9c ZY |
1108 | * queue, updates firmware pointers, and updates |
1109 | * the WRITE index. If insufficient rx_free buffers | |
bb8c093b | 1110 | * are available, schedules iwl3945_rx_replenish |
b481de9c ZY |
1111 | * |
1112 | * -- enable interrupts -- | |
6100b588 | 1113 | * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the |
b481de9c ZY |
1114 | * READ INDEX, detaching the SKB from the pool. |
1115 | * Moves the packet buffer from queue to rx_used. | |
bb8c093b | 1116 | * Calls iwl3945_rx_queue_restock to refill any empty |
b481de9c ZY |
1117 | * slots. |
1118 | * ... | |
1119 | * | |
1120 | */ | |
1121 | ||
b481de9c | 1122 | /** |
9fbab516 | 1123 | * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr |
b481de9c | 1124 | */ |
4a8a4322 | 1125 | static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv, |
b481de9c ZY |
1126 | dma_addr_t dma_addr) |
1127 | { | |
1128 | return cpu_to_le32((u32)dma_addr); | |
1129 | } | |
1130 | ||
1131 | /** | |
bb8c093b | 1132 | * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool |
b481de9c | 1133 | * |
9fbab516 | 1134 | * If there are slots in the RX queue that need to be restocked, |
b481de9c | 1135 | * and we have free pre-allocated buffers, fill the ranks as much |
9fbab516 | 1136 | * as we can, pulling from rx_free. |
b481de9c ZY |
1137 | * |
1138 | * This moves the 'write' index forward to catch up with 'processed', and | |
1139 | * also updates the memory address in the firmware to reference the new | |
1140 | * target buffer. | |
1141 | */ | |
4a8a4322 | 1142 | static int iwl3945_rx_queue_restock(struct iwl_priv *priv) |
b481de9c | 1143 | { |
cc2f362c | 1144 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c | 1145 | struct list_head *element; |
6100b588 | 1146 | struct iwl_rx_mem_buffer *rxb; |
b481de9c ZY |
1147 | unsigned long flags; |
1148 | int write, rc; | |
1149 | ||
1150 | spin_lock_irqsave(&rxq->lock, flags); | |
1151 | write = rxq->write & ~0x7; | |
37d68317 | 1152 | while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) { |
6440adb5 | 1153 | /* Get next free Rx buffer, remove from free list */ |
b481de9c | 1154 | element = rxq->rx_free.next; |
6100b588 | 1155 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); |
b481de9c | 1156 | list_del(element); |
6440adb5 CB |
1157 | |
1158 | /* Point to Rx buffer via next RBD in circular buffer */ | |
6100b588 | 1159 | rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->real_dma_addr); |
b481de9c ZY |
1160 | rxq->queue[rxq->write] = rxb; |
1161 | rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; | |
1162 | rxq->free_count--; | |
1163 | } | |
1164 | spin_unlock_irqrestore(&rxq->lock, flags); | |
1165 | /* If the pre-allocated buffer pool is dropping low, schedule to | |
1166 | * refill it */ | |
1167 | if (rxq->free_count <= RX_LOW_WATERMARK) | |
1168 | queue_work(priv->workqueue, &priv->rx_replenish); | |
1169 | ||
1170 | ||
6440adb5 CB |
1171 | /* If we've added more space for the firmware to place data, tell it. |
1172 | * Increment device's write pointer in multiples of 8. */ | |
d14d4440 | 1173 | if ((rxq->write_actual != (rxq->write & ~0x7)) |
b481de9c ZY |
1174 | || (abs(rxq->write - rxq->read) > 7)) { |
1175 | spin_lock_irqsave(&rxq->lock, flags); | |
1176 | rxq->need_update = 1; | |
1177 | spin_unlock_irqrestore(&rxq->lock, flags); | |
141c43a3 | 1178 | rc = iwl_rx_queue_update_write_ptr(priv, rxq); |
b481de9c ZY |
1179 | if (rc) |
1180 | return rc; | |
1181 | } | |
1182 | ||
1183 | return 0; | |
1184 | } | |
1185 | ||
1186 | /** | |
bb8c093b | 1187 | * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free |
b481de9c ZY |
1188 | * |
1189 | * When moving to rx_free an SKB is allocated for the slot. | |
1190 | * | |
bb8c093b | 1191 | * Also restock the Rx queue via iwl3945_rx_queue_restock. |
01ebd063 | 1192 | * This is called as a scheduled work item (except for during initialization) |
b481de9c | 1193 | */ |
d14d4440 | 1194 | static void iwl3945_rx_allocate(struct iwl_priv *priv, gfp_t priority) |
b481de9c | 1195 | { |
cc2f362c | 1196 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c | 1197 | struct list_head *element; |
6100b588 | 1198 | struct iwl_rx_mem_buffer *rxb; |
b481de9c | 1199 | unsigned long flags; |
72240498 AK |
1200 | |
1201 | while (1) { | |
1202 | spin_lock_irqsave(&rxq->lock, flags); | |
1203 | ||
1204 | if (list_empty(&rxq->rx_used)) { | |
1205 | spin_unlock_irqrestore(&rxq->lock, flags); | |
1206 | return; | |
1207 | } | |
1208 | ||
b481de9c | 1209 | element = rxq->rx_used.next; |
6100b588 | 1210 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); |
72240498 AK |
1211 | list_del(element); |
1212 | spin_unlock_irqrestore(&rxq->lock, flags); | |
6440adb5 CB |
1213 | |
1214 | /* Alloc a new receive buffer */ | |
b481de9c | 1215 | rxb->skb = |
1e33dc64 | 1216 | alloc_skb(priv->hw_params.rx_buf_size, |
d14d4440 | 1217 | priority); |
b481de9c ZY |
1218 | if (!rxb->skb) { |
1219 | if (net_ratelimit()) | |
978785a3 | 1220 | IWL_CRIT(priv, ": Can not allocate SKB buffers\n"); |
b481de9c ZY |
1221 | /* We don't reschedule replenish work here -- we will |
1222 | * call the restock method and if it still needs | |
1223 | * more buffers it will schedule replenish */ | |
1224 | break; | |
1225 | } | |
12342c47 ZY |
1226 | |
1227 | /* If radiotap head is required, reserve some headroom here. | |
1228 | * The physical head count is a variable rx_stats->phy_count. | |
1229 | * We reserve 4 bytes here. Plus these extra bytes, the | |
1230 | * headroom of the physical head should be enough for the | |
1231 | * radiotap head that iwl3945 supported. See iwl3945_rt. | |
1232 | */ | |
1233 | skb_reserve(rxb->skb, 4); | |
1234 | ||
6440adb5 | 1235 | /* Get physical address of RB/SKB */ |
1e33dc64 WT |
1236 | rxb->real_dma_addr = pci_map_single(priv->pci_dev, |
1237 | rxb->skb->data, | |
1238 | priv->hw_params.rx_buf_size, | |
1239 | PCI_DMA_FROMDEVICE); | |
72240498 AK |
1240 | |
1241 | spin_lock_irqsave(&rxq->lock, flags); | |
b481de9c | 1242 | list_add_tail(&rxb->list, &rxq->rx_free); |
72240498 | 1243 | priv->alloc_rxb_skb++; |
b481de9c | 1244 | rxq->free_count++; |
72240498 | 1245 | spin_unlock_irqrestore(&rxq->lock, flags); |
b481de9c | 1246 | } |
5c0eef96 MA |
1247 | } |
1248 | ||
df833b1d RC |
1249 | void iwl3945_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq) |
1250 | { | |
1251 | unsigned long flags; | |
1252 | int i; | |
1253 | spin_lock_irqsave(&rxq->lock, flags); | |
1254 | INIT_LIST_HEAD(&rxq->rx_free); | |
1255 | INIT_LIST_HEAD(&rxq->rx_used); | |
1256 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
1257 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { | |
1258 | /* In the reset function, these buffers may have been allocated | |
1259 | * to an SKB, so we need to unmap and free potential storage */ | |
1260 | if (rxq->pool[i].skb != NULL) { | |
1261 | pci_unmap_single(priv->pci_dev, | |
1262 | rxq->pool[i].real_dma_addr, | |
1263 | priv->hw_params.rx_buf_size, | |
1264 | PCI_DMA_FROMDEVICE); | |
1265 | priv->alloc_rxb_skb--; | |
1266 | dev_kfree_skb(rxq->pool[i].skb); | |
1267 | rxq->pool[i].skb = NULL; | |
1268 | } | |
1269 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
1270 | } | |
1271 | ||
1272 | /* Set us so that we have processed and used all buffers, but have | |
1273 | * not restocked the Rx queue with fresh buffers */ | |
1274 | rxq->read = rxq->write = 0; | |
1275 | rxq->free_count = 0; | |
d14d4440 | 1276 | rxq->write_actual = 0; |
df833b1d RC |
1277 | spin_unlock_irqrestore(&rxq->lock, flags); |
1278 | } | |
df833b1d | 1279 | |
5c0eef96 MA |
1280 | void iwl3945_rx_replenish(void *data) |
1281 | { | |
4a8a4322 | 1282 | struct iwl_priv *priv = data; |
5c0eef96 MA |
1283 | unsigned long flags; |
1284 | ||
d14d4440 | 1285 | iwl3945_rx_allocate(priv, GFP_KERNEL); |
b481de9c ZY |
1286 | |
1287 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 1288 | iwl3945_rx_queue_restock(priv); |
b481de9c ZY |
1289 | spin_unlock_irqrestore(&priv->lock, flags); |
1290 | } | |
1291 | ||
d14d4440 AK |
1292 | static void iwl3945_rx_replenish_now(struct iwl_priv *priv) |
1293 | { | |
1294 | iwl3945_rx_allocate(priv, GFP_ATOMIC); | |
1295 | ||
1296 | iwl3945_rx_queue_restock(priv); | |
1297 | } | |
1298 | ||
1299 | ||
df833b1d RC |
1300 | /* Assumes that the skb field of the buffers in 'pool' is kept accurate. |
1301 | * If an SKB has been detached, the POOL needs to have its SKB set to NULL | |
1302 | * This free routine walks the list of POOL entries and if SKB is set to | |
1303 | * non NULL it is unmapped and freed | |
1304 | */ | |
1305 | static void iwl3945_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq) | |
1306 | { | |
1307 | int i; | |
1308 | for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) { | |
1309 | if (rxq->pool[i].skb != NULL) { | |
1310 | pci_unmap_single(priv->pci_dev, | |
1311 | rxq->pool[i].real_dma_addr, | |
1312 | priv->hw_params.rx_buf_size, | |
1313 | PCI_DMA_FROMDEVICE); | |
1314 | dev_kfree_skb(rxq->pool[i].skb); | |
1315 | } | |
1316 | } | |
1317 | ||
1318 | pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd, | |
1319 | rxq->dma_addr); | |
1320 | pci_free_consistent(priv->pci_dev, sizeof(struct iwl_rb_status), | |
1321 | rxq->rb_stts, rxq->rb_stts_dma); | |
1322 | rxq->bd = NULL; | |
1323 | rxq->rb_stts = NULL; | |
1324 | } | |
df833b1d RC |
1325 | |
1326 | ||
b481de9c ZY |
1327 | /* Convert linear signal-to-noise ratio into dB */ |
1328 | static u8 ratio2dB[100] = { | |
1329 | /* 0 1 2 3 4 5 6 7 8 9 */ | |
1330 | 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */ | |
1331 | 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */ | |
1332 | 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */ | |
1333 | 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */ | |
1334 | 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */ | |
1335 | 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */ | |
1336 | 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */ | |
1337 | 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */ | |
1338 | 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */ | |
1339 | 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */ | |
1340 | }; | |
1341 | ||
1342 | /* Calculates a relative dB value from a ratio of linear | |
1343 | * (i.e. not dB) signal levels. | |
1344 | * Conversion assumes that levels are voltages (20*log), not powers (10*log). */ | |
bb8c093b | 1345 | int iwl3945_calc_db_from_ratio(int sig_ratio) |
b481de9c | 1346 | { |
221c80cf AB |
1347 | /* 1000:1 or higher just report as 60 dB */ |
1348 | if (sig_ratio >= 1000) | |
b481de9c ZY |
1349 | return 60; |
1350 | ||
221c80cf | 1351 | /* 100:1 or higher, divide by 10 and use table, |
b481de9c | 1352 | * add 20 dB to make up for divide by 10 */ |
221c80cf | 1353 | if (sig_ratio >= 100) |
3ac7f146 | 1354 | return 20 + (int)ratio2dB[sig_ratio/10]; |
b481de9c ZY |
1355 | |
1356 | /* We shouldn't see this */ | |
1357 | if (sig_ratio < 1) | |
1358 | return 0; | |
1359 | ||
1360 | /* Use table for ratios 1:1 - 99:1 */ | |
1361 | return (int)ratio2dB[sig_ratio]; | |
1362 | } | |
1363 | ||
1364 | #define PERFECT_RSSI (-20) /* dBm */ | |
1365 | #define WORST_RSSI (-95) /* dBm */ | |
1366 | #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI) | |
1367 | ||
1368 | /* Calculate an indication of rx signal quality (a percentage, not dBm!). | |
1369 | * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info | |
1370 | * about formulas used below. */ | |
bb8c093b | 1371 | int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm) |
b481de9c ZY |
1372 | { |
1373 | int sig_qual; | |
1374 | int degradation = PERFECT_RSSI - rssi_dbm; | |
1375 | ||
1376 | /* If we get a noise measurement, use signal-to-noise ratio (SNR) | |
1377 | * as indicator; formula is (signal dbm - noise dbm). | |
1378 | * SNR at or above 40 is a great signal (100%). | |
1379 | * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator. | |
1380 | * Weakest usable signal is usually 10 - 15 dB SNR. */ | |
1381 | if (noise_dbm) { | |
1382 | if (rssi_dbm - noise_dbm >= 40) | |
1383 | return 100; | |
1384 | else if (rssi_dbm < noise_dbm) | |
1385 | return 0; | |
1386 | sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2; | |
1387 | ||
1388 | /* Else use just the signal level. | |
1389 | * This formula is a least squares fit of data points collected and | |
1390 | * compared with a reference system that had a percentage (%) display | |
1391 | * for signal quality. */ | |
1392 | } else | |
1393 | sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation * | |
1394 | (15 * RSSI_RANGE + 62 * degradation)) / | |
1395 | (RSSI_RANGE * RSSI_RANGE); | |
1396 | ||
1397 | if (sig_qual > 100) | |
1398 | sig_qual = 100; | |
1399 | else if (sig_qual < 1) | |
1400 | sig_qual = 0; | |
1401 | ||
1402 | return sig_qual; | |
1403 | } | |
1404 | ||
1405 | /** | |
9fbab516 | 1406 | * iwl3945_rx_handle - Main entry function for receiving responses from uCode |
b481de9c ZY |
1407 | * |
1408 | * Uses the priv->rx_handlers callback function array to invoke | |
1409 | * the appropriate handlers, including command responses, | |
1410 | * frame-received notifications, and other notifications. | |
1411 | */ | |
4a8a4322 | 1412 | static void iwl3945_rx_handle(struct iwl_priv *priv) |
b481de9c | 1413 | { |
6100b588 | 1414 | struct iwl_rx_mem_buffer *rxb; |
3d24a9f7 | 1415 | struct iwl_rx_packet *pkt; |
cc2f362c | 1416 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c ZY |
1417 | u32 r, i; |
1418 | int reclaim; | |
1419 | unsigned long flags; | |
5c0eef96 | 1420 | u8 fill_rx = 0; |
d68ab680 | 1421 | u32 count = 8; |
d14d4440 | 1422 | int total_empty = 0; |
b481de9c | 1423 | |
6440adb5 CB |
1424 | /* uCode's read index (stored in shared DRAM) indicates the last Rx |
1425 | * buffer that the driver may process (last buffer filled by ucode). */ | |
8cd812bc | 1426 | r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; |
b481de9c ZY |
1427 | i = rxq->read; |
1428 | ||
d14d4440 AK |
1429 | /* calculate total frames need to be restock after handling RX */ |
1430 | total_empty = r - priv->rxq.write_actual; | |
1431 | if (total_empty < 0) | |
1432 | total_empty += RX_QUEUE_SIZE; | |
1433 | ||
1434 | if (total_empty > (RX_QUEUE_SIZE / 2)) | |
5c0eef96 | 1435 | fill_rx = 1; |
b481de9c ZY |
1436 | /* Rx interrupt, but nothing sent from uCode */ |
1437 | if (i == r) | |
e1623446 | 1438 | IWL_DEBUG(priv, IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i); |
b481de9c ZY |
1439 | |
1440 | while (i != r) { | |
1441 | rxb = rxq->queue[i]; | |
1442 | ||
9fbab516 | 1443 | /* If an RXB doesn't have a Rx queue slot associated with it, |
b481de9c ZY |
1444 | * then a bug has been introduced in the queue refilling |
1445 | * routines -- catch it here */ | |
1446 | BUG_ON(rxb == NULL); | |
1447 | ||
1448 | rxq->queue[i] = NULL; | |
1449 | ||
df833b1d RC |
1450 | pci_unmap_single(priv->pci_dev, rxb->real_dma_addr, |
1451 | priv->hw_params.rx_buf_size, | |
1452 | PCI_DMA_FROMDEVICE); | |
3d24a9f7 | 1453 | pkt = (struct iwl_rx_packet *)rxb->skb->data; |
b481de9c ZY |
1454 | |
1455 | /* Reclaim a command buffer only if this packet is a response | |
1456 | * to a (driver-originated) command. | |
1457 | * If the packet (e.g. Rx frame) originated from uCode, | |
1458 | * there is no command buffer to reclaim. | |
1459 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
1460 | * but apparently a few don't get set; catch them here. */ | |
1461 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
1462 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && | |
1463 | (pkt->hdr.cmd != REPLY_TX); | |
1464 | ||
1465 | /* Based on type of command response or notification, | |
1466 | * handle those that need handling via function in | |
bb8c093b | 1467 | * rx_handlers table. See iwl3945_setup_rx_handlers() */ |
b481de9c | 1468 | if (priv->rx_handlers[pkt->hdr.cmd]) { |
e1623446 | 1469 | IWL_DEBUG(priv, IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR, |
b481de9c ZY |
1470 | "r = %d, i = %d, %s, 0x%02x\n", r, i, |
1471 | get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); | |
1472 | priv->rx_handlers[pkt->hdr.cmd] (priv, rxb); | |
86ddbf62 | 1473 | priv->isr_stats.rx_handlers[pkt->hdr.cmd]++; |
b481de9c ZY |
1474 | } else { |
1475 | /* No handling needed */ | |
e1623446 | 1476 | IWL_DEBUG(priv, IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR, |
b481de9c ZY |
1477 | "r %d i %d No handler needed for %s, 0x%02x\n", |
1478 | r, i, get_cmd_string(pkt->hdr.cmd), | |
1479 | pkt->hdr.cmd); | |
1480 | } | |
1481 | ||
1482 | if (reclaim) { | |
9fbab516 | 1483 | /* Invoke any callbacks, transfer the skb to caller, and |
518099a8 | 1484 | * fire off the (possibly) blocking iwl_send_cmd() |
b481de9c ZY |
1485 | * as we reclaim the driver command queue */ |
1486 | if (rxb && rxb->skb) | |
732587ab | 1487 | iwl_tx_cmd_complete(priv, rxb); |
b481de9c | 1488 | else |
39aadf8c | 1489 | IWL_WARN(priv, "Claim null rxb?\n"); |
b481de9c ZY |
1490 | } |
1491 | ||
1492 | /* For now we just don't re-use anything. We can tweak this | |
1493 | * later to try and re-use notification packets and SKBs that | |
1494 | * fail to Rx correctly */ | |
1495 | if (rxb->skb != NULL) { | |
1496 | priv->alloc_rxb_skb--; | |
1497 | dev_kfree_skb_any(rxb->skb); | |
1498 | rxb->skb = NULL; | |
1499 | } | |
1500 | ||
b481de9c ZY |
1501 | spin_lock_irqsave(&rxq->lock, flags); |
1502 | list_add_tail(&rxb->list, &priv->rxq.rx_used); | |
1503 | spin_unlock_irqrestore(&rxq->lock, flags); | |
1504 | i = (i + 1) & RX_QUEUE_MASK; | |
5c0eef96 MA |
1505 | /* If there are a lot of unused frames, |
1506 | * restock the Rx queue so ucode won't assert. */ | |
1507 | if (fill_rx) { | |
1508 | count++; | |
1509 | if (count >= 8) { | |
1510 | priv->rxq.read = i; | |
d14d4440 | 1511 | iwl3945_rx_replenish_now(priv); |
5c0eef96 MA |
1512 | count = 0; |
1513 | } | |
1514 | } | |
b481de9c ZY |
1515 | } |
1516 | ||
1517 | /* Backtrack one entry */ | |
1518 | priv->rxq.read = i; | |
d14d4440 AK |
1519 | if (fill_rx) |
1520 | iwl3945_rx_replenish_now(priv); | |
1521 | else | |
1522 | iwl3945_rx_queue_restock(priv); | |
b481de9c ZY |
1523 | } |
1524 | ||
0359facc | 1525 | /* call this function to flush any scheduled tasklet */ |
4a8a4322 | 1526 | static inline void iwl_synchronize_irq(struct iwl_priv *priv) |
0359facc | 1527 | { |
a96a27f9 | 1528 | /* wait to make sure we flush pending tasklet*/ |
0359facc MA |
1529 | synchronize_irq(priv->pci_dev->irq); |
1530 | tasklet_kill(&priv->irq_tasklet); | |
1531 | } | |
1532 | ||
b481de9c ZY |
1533 | static const char *desc_lookup(int i) |
1534 | { | |
1535 | switch (i) { | |
1536 | case 1: | |
1537 | return "FAIL"; | |
1538 | case 2: | |
1539 | return "BAD_PARAM"; | |
1540 | case 3: | |
1541 | return "BAD_CHECKSUM"; | |
1542 | case 4: | |
1543 | return "NMI_INTERRUPT"; | |
1544 | case 5: | |
1545 | return "SYSASSERT"; | |
1546 | case 6: | |
1547 | return "FATAL_ERROR"; | |
1548 | } | |
1549 | ||
1550 | return "UNKNOWN"; | |
1551 | } | |
1552 | ||
1553 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | |
1554 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | |
1555 | ||
4a8a4322 | 1556 | static void iwl3945_dump_nic_error_log(struct iwl_priv *priv) |
b481de9c ZY |
1557 | { |
1558 | u32 i; | |
1559 | u32 desc, time, count, base, data1; | |
1560 | u32 blink1, blink2, ilink1, ilink2; | |
b481de9c ZY |
1561 | |
1562 | base = le32_to_cpu(priv->card_alive.error_event_table_ptr); | |
1563 | ||
bb8c093b | 1564 | if (!iwl3945_hw_valid_rtc_data_addr(base)) { |
15b1687c | 1565 | IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base); |
b481de9c ZY |
1566 | return; |
1567 | } | |
1568 | ||
b481de9c | 1569 | |
5d49f498 | 1570 | count = iwl_read_targ_mem(priv, base); |
b481de9c ZY |
1571 | |
1572 | if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { | |
15b1687c WT |
1573 | IWL_ERR(priv, "Start IWL Error Log Dump:\n"); |
1574 | IWL_ERR(priv, "Status: 0x%08lX, count: %d\n", | |
1575 | priv->status, count); | |
b481de9c ZY |
1576 | } |
1577 | ||
15b1687c | 1578 | IWL_ERR(priv, "Desc Time asrtPC blink2 " |
b481de9c ZY |
1579 | "ilink1 nmiPC Line\n"); |
1580 | for (i = ERROR_START_OFFSET; | |
1581 | i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET; | |
1582 | i += ERROR_ELEM_SIZE) { | |
5d49f498 | 1583 | desc = iwl_read_targ_mem(priv, base + i); |
b481de9c | 1584 | time = |
5d49f498 | 1585 | iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32)); |
b481de9c | 1586 | blink1 = |
5d49f498 | 1587 | iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32)); |
b481de9c | 1588 | blink2 = |
5d49f498 | 1589 | iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32)); |
b481de9c | 1590 | ilink1 = |
5d49f498 | 1591 | iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32)); |
b481de9c | 1592 | ilink2 = |
5d49f498 | 1593 | iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32)); |
b481de9c | 1594 | data1 = |
5d49f498 | 1595 | iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32)); |
b481de9c | 1596 | |
15b1687c WT |
1597 | IWL_ERR(priv, |
1598 | "%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n", | |
1599 | desc_lookup(desc), desc, time, blink1, blink2, | |
1600 | ilink1, ilink2, data1); | |
b481de9c ZY |
1601 | } |
1602 | ||
b481de9c ZY |
1603 | } |
1604 | ||
f58177b9 | 1605 | #define EVENT_START_OFFSET (6 * sizeof(u32)) |
b481de9c ZY |
1606 | |
1607 | /** | |
bb8c093b | 1608 | * iwl3945_print_event_log - Dump error event log to syslog |
b481de9c | 1609 | * |
b481de9c | 1610 | */ |
4a8a4322 | 1611 | static void iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx, |
b481de9c ZY |
1612 | u32 num_events, u32 mode) |
1613 | { | |
1614 | u32 i; | |
1615 | u32 base; /* SRAM byte address of event log header */ | |
1616 | u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */ | |
1617 | u32 ptr; /* SRAM byte address of log data */ | |
1618 | u32 ev, time, data; /* event log data */ | |
1619 | ||
1620 | if (num_events == 0) | |
1621 | return; | |
1622 | ||
1623 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
1624 | ||
1625 | if (mode == 0) | |
1626 | event_size = 2 * sizeof(u32); | |
1627 | else | |
1628 | event_size = 3 * sizeof(u32); | |
1629 | ||
1630 | ptr = base + EVENT_START_OFFSET + (start_idx * event_size); | |
1631 | ||
1632 | /* "time" is actually "data" for mode 0 (no timestamp). | |
1633 | * place event id # at far right for easier visual parsing. */ | |
1634 | for (i = 0; i < num_events; i++) { | |
5d49f498 | 1635 | ev = iwl_read_targ_mem(priv, ptr); |
b481de9c | 1636 | ptr += sizeof(u32); |
5d49f498 | 1637 | time = iwl_read_targ_mem(priv, ptr); |
b481de9c | 1638 | ptr += sizeof(u32); |
15b1687c WT |
1639 | if (mode == 0) { |
1640 | /* data, ev */ | |
1641 | IWL_ERR(priv, "0x%08x\t%04u\n", time, ev); | |
1642 | } else { | |
5d49f498 | 1643 | data = iwl_read_targ_mem(priv, ptr); |
b481de9c | 1644 | ptr += sizeof(u32); |
15b1687c | 1645 | IWL_ERR(priv, "%010u\t0x%08x\t%04u\n", time, data, ev); |
b481de9c ZY |
1646 | } |
1647 | } | |
1648 | } | |
1649 | ||
4a8a4322 | 1650 | static void iwl3945_dump_nic_event_log(struct iwl_priv *priv) |
b481de9c | 1651 | { |
b481de9c ZY |
1652 | u32 base; /* SRAM byte address of event log header */ |
1653 | u32 capacity; /* event log capacity in # entries */ | |
1654 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
1655 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
1656 | u32 next_entry; /* index of next entry to be written by uCode */ | |
1657 | u32 size; /* # entries that we'll print */ | |
1658 | ||
1659 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
bb8c093b | 1660 | if (!iwl3945_hw_valid_rtc_data_addr(base)) { |
15b1687c | 1661 | IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base); |
b481de9c ZY |
1662 | return; |
1663 | } | |
1664 | ||
b481de9c | 1665 | /* event log header */ |
5d49f498 AK |
1666 | capacity = iwl_read_targ_mem(priv, base); |
1667 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
1668 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
1669 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
b481de9c ZY |
1670 | |
1671 | size = num_wraps ? capacity : next_entry; | |
1672 | ||
1673 | /* bail out if nothing in log */ | |
1674 | if (size == 0) { | |
15b1687c | 1675 | IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n"); |
b481de9c ZY |
1676 | return; |
1677 | } | |
1678 | ||
15b1687c | 1679 | IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n", |
b481de9c ZY |
1680 | size, num_wraps); |
1681 | ||
1682 | /* if uCode has wrapped back to top of log, start at the oldest entry, | |
1683 | * i.e the next one that uCode would fill. */ | |
1684 | if (num_wraps) | |
bb8c093b | 1685 | iwl3945_print_event_log(priv, next_entry, |
b481de9c ZY |
1686 | capacity - next_entry, mode); |
1687 | ||
1688 | /* (then/else) start at top of log */ | |
bb8c093b | 1689 | iwl3945_print_event_log(priv, 0, next_entry, mode); |
b481de9c | 1690 | |
b481de9c ZY |
1691 | } |
1692 | ||
4a8a4322 | 1693 | static void iwl3945_irq_tasklet(struct iwl_priv *priv) |
b481de9c ZY |
1694 | { |
1695 | u32 inta, handled = 0; | |
1696 | u32 inta_fh; | |
1697 | unsigned long flags; | |
d08853a3 | 1698 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
1699 | u32 inta_mask; |
1700 | #endif | |
1701 | ||
1702 | spin_lock_irqsave(&priv->lock, flags); | |
1703 | ||
1704 | /* Ack/clear/reset pending uCode interrupts. | |
1705 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
1706 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ | |
5d49f498 AK |
1707 | inta = iwl_read32(priv, CSR_INT); |
1708 | iwl_write32(priv, CSR_INT, inta); | |
b481de9c ZY |
1709 | |
1710 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. | |
1711 | * Any new interrupts that happen after this, either while we're | |
1712 | * in this tasklet, or later, will show up in next ISR/tasklet. */ | |
5d49f498 AK |
1713 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); |
1714 | iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh); | |
b481de9c | 1715 | |
d08853a3 | 1716 | #ifdef CONFIG_IWLWIFI_DEBUG |
40b8ec0b | 1717 | if (priv->debug_level & IWL_DL_ISR) { |
9fbab516 | 1718 | /* just for debug */ |
5d49f498 | 1719 | inta_mask = iwl_read32(priv, CSR_INT_MASK); |
e1623446 | 1720 | IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", |
b481de9c ZY |
1721 | inta, inta_mask, inta_fh); |
1722 | } | |
1723 | #endif | |
1724 | ||
1725 | /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not | |
1726 | * atomic, make sure that inta covers all the interrupts that | |
1727 | * we've discovered, even if FH interrupt came in just after | |
1728 | * reading CSR_INT. */ | |
6f83eaa1 | 1729 | if (inta_fh & CSR39_FH_INT_RX_MASK) |
b481de9c | 1730 | inta |= CSR_INT_BIT_FH_RX; |
6f83eaa1 | 1731 | if (inta_fh & CSR39_FH_INT_TX_MASK) |
b481de9c ZY |
1732 | inta |= CSR_INT_BIT_FH_TX; |
1733 | ||
1734 | /* Now service all interrupt bits discovered above. */ | |
1735 | if (inta & CSR_INT_BIT_HW_ERR) { | |
15b1687c | 1736 | IWL_ERR(priv, "Microcode HW error detected. Restarting.\n"); |
b481de9c ZY |
1737 | |
1738 | /* Tell the device to stop sending interrupts */ | |
ed3b932e | 1739 | iwl_disable_interrupts(priv); |
b481de9c | 1740 | |
86ddbf62 | 1741 | priv->isr_stats.hw++; |
8ccde88a | 1742 | iwl_irq_handle_error(priv); |
b481de9c ZY |
1743 | |
1744 | handled |= CSR_INT_BIT_HW_ERR; | |
1745 | ||
1746 | spin_unlock_irqrestore(&priv->lock, flags); | |
1747 | ||
1748 | return; | |
1749 | } | |
1750 | ||
d08853a3 | 1751 | #ifdef CONFIG_IWLWIFI_DEBUG |
40b8ec0b | 1752 | if (priv->debug_level & (IWL_DL_ISR)) { |
b481de9c | 1753 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
86ddbf62 | 1754 | if (inta & CSR_INT_BIT_SCD) { |
e1623446 | 1755 | IWL_DEBUG_ISR(priv, "Scheduler finished to transmit " |
25c03d8e | 1756 | "the frame/frames.\n"); |
86ddbf62 AK |
1757 | priv->isr_stats.sch++; |
1758 | } | |
b481de9c ZY |
1759 | |
1760 | /* Alive notification via Rx interrupt will do the real work */ | |
86ddbf62 | 1761 | if (inta & CSR_INT_BIT_ALIVE) { |
e1623446 | 1762 | IWL_DEBUG_ISR(priv, "Alive interrupt\n"); |
86ddbf62 AK |
1763 | priv->isr_stats.alive++; |
1764 | } | |
b481de9c ZY |
1765 | } |
1766 | #endif | |
1767 | /* Safely ignore these bits for debug checks below */ | |
25c03d8e | 1768 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); |
b481de9c | 1769 | |
b481de9c ZY |
1770 | /* Error detected by uCode */ |
1771 | if (inta & CSR_INT_BIT_SW_ERR) { | |
15b1687c WT |
1772 | IWL_ERR(priv, "Microcode SW error detected. " |
1773 | "Restarting 0x%X.\n", inta); | |
86ddbf62 AK |
1774 | priv->isr_stats.sw++; |
1775 | priv->isr_stats.sw_err = inta; | |
8ccde88a | 1776 | iwl_irq_handle_error(priv); |
b481de9c ZY |
1777 | handled |= CSR_INT_BIT_SW_ERR; |
1778 | } | |
1779 | ||
1780 | /* uCode wakes up after power-down sleep */ | |
1781 | if (inta & CSR_INT_BIT_WAKEUP) { | |
e1623446 | 1782 | IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); |
141c43a3 | 1783 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); |
4f3602c8 SO |
1784 | iwl_txq_update_write_ptr(priv, &priv->txq[0]); |
1785 | iwl_txq_update_write_ptr(priv, &priv->txq[1]); | |
1786 | iwl_txq_update_write_ptr(priv, &priv->txq[2]); | |
1787 | iwl_txq_update_write_ptr(priv, &priv->txq[3]); | |
1788 | iwl_txq_update_write_ptr(priv, &priv->txq[4]); | |
1789 | iwl_txq_update_write_ptr(priv, &priv->txq[5]); | |
b481de9c | 1790 | |
86ddbf62 | 1791 | priv->isr_stats.wakeup++; |
b481de9c ZY |
1792 | handled |= CSR_INT_BIT_WAKEUP; |
1793 | } | |
1794 | ||
1795 | /* All uCode command responses, including Tx command responses, | |
1796 | * Rx "responses" (frame-received notification), and other | |
1797 | * notifications from uCode come through here*/ | |
1798 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | |
bb8c093b | 1799 | iwl3945_rx_handle(priv); |
86ddbf62 | 1800 | priv->isr_stats.rx++; |
b481de9c ZY |
1801 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); |
1802 | } | |
1803 | ||
1804 | if (inta & CSR_INT_BIT_FH_TX) { | |
e1623446 | 1805 | IWL_DEBUG_ISR(priv, "Tx interrupt\n"); |
86ddbf62 | 1806 | priv->isr_stats.tx++; |
b481de9c | 1807 | |
5d49f498 | 1808 | iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6)); |
a8b50a0a MA |
1809 | iwl_write_direct32(priv, FH39_TCSR_CREDIT |
1810 | (FH39_SRVC_CHNL), 0x0); | |
b481de9c ZY |
1811 | handled |= CSR_INT_BIT_FH_TX; |
1812 | } | |
1813 | ||
86ddbf62 | 1814 | if (inta & ~handled) { |
15b1687c | 1815 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); |
86ddbf62 AK |
1816 | priv->isr_stats.unhandled++; |
1817 | } | |
b481de9c | 1818 | |
40cefda9 | 1819 | if (inta & ~priv->inta_mask) { |
39aadf8c | 1820 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", |
40cefda9 | 1821 | inta & ~priv->inta_mask); |
39aadf8c | 1822 | IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh); |
b481de9c ZY |
1823 | } |
1824 | ||
1825 | /* Re-enable all interrupts */ | |
0359facc MA |
1826 | /* only Re-enable if disabled by irq */ |
1827 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
ed3b932e | 1828 | iwl_enable_interrupts(priv); |
b481de9c | 1829 | |
d08853a3 | 1830 | #ifdef CONFIG_IWLWIFI_DEBUG |
40b8ec0b | 1831 | if (priv->debug_level & (IWL_DL_ISR)) { |
5d49f498 AK |
1832 | inta = iwl_read32(priv, CSR_INT); |
1833 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
1834 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | |
e1623446 | 1835 | IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " |
b481de9c ZY |
1836 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); |
1837 | } | |
1838 | #endif | |
1839 | spin_unlock_irqrestore(&priv->lock, flags); | |
1840 | } | |
1841 | ||
4a8a4322 | 1842 | static int iwl3945_get_channels_for_scan(struct iwl_priv *priv, |
8318d78a | 1843 | enum ieee80211_band band, |
f9340520 | 1844 | u8 is_active, u8 n_probes, |
bb8c093b | 1845 | struct iwl3945_scan_channel *scan_ch) |
b481de9c | 1846 | { |
4e05c234 | 1847 | struct ieee80211_channel *chan; |
8318d78a | 1848 | const struct ieee80211_supported_band *sband; |
d20b3c65 | 1849 | const struct iwl_channel_info *ch_info; |
b481de9c ZY |
1850 | u16 passive_dwell = 0; |
1851 | u16 active_dwell = 0; | |
1852 | int added, i; | |
1853 | ||
cbba18c6 | 1854 | sband = iwl_get_hw_mode(priv, band); |
8318d78a | 1855 | if (!sband) |
b481de9c ZY |
1856 | return 0; |
1857 | ||
77fecfb8 SO |
1858 | active_dwell = iwl_get_active_dwell_time(priv, band, n_probes); |
1859 | passive_dwell = iwl_get_passive_dwell_time(priv, band); | |
b481de9c | 1860 | |
8f4807a1 AK |
1861 | if (passive_dwell <= active_dwell) |
1862 | passive_dwell = active_dwell + 1; | |
1863 | ||
4e05c234 JB |
1864 | for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) { |
1865 | chan = priv->scan_request->channels[i]; | |
1866 | ||
1867 | if (chan->band != band) | |
182e2e66 JB |
1868 | continue; |
1869 | ||
4e05c234 | 1870 | scan_ch->channel = chan->hw_value; |
b481de9c | 1871 | |
e6148917 | 1872 | ch_info = iwl_get_channel_info(priv, band, scan_ch->channel); |
b481de9c | 1873 | if (!is_channel_valid(ch_info)) { |
e1623446 | 1874 | IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n", |
b481de9c ZY |
1875 | scan_ch->channel); |
1876 | continue; | |
1877 | } | |
1878 | ||
011a0330 AK |
1879 | scan_ch->active_dwell = cpu_to_le16(active_dwell); |
1880 | scan_ch->passive_dwell = cpu_to_le16(passive_dwell); | |
1881 | /* If passive , set up for auto-switch | |
1882 | * and use long active_dwell time. | |
1883 | */ | |
b481de9c | 1884 | if (!is_active || is_channel_passive(ch_info) || |
4e05c234 | 1885 | (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) { |
b481de9c | 1886 | scan_ch->type = 0; /* passive */ |
011a0330 AK |
1887 | if (IWL_UCODE_API(priv->ucode_ver) == 1) |
1888 | scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1); | |
1889 | } else { | |
b481de9c | 1890 | scan_ch->type = 1; /* active */ |
011a0330 | 1891 | } |
b481de9c | 1892 | |
011a0330 AK |
1893 | /* Set direct probe bits. These may be used both for active |
1894 | * scan channels (probes gets sent right away), | |
1895 | * or for passive channels (probes get se sent only after | |
1896 | * hearing clear Rx packet).*/ | |
1897 | if (IWL_UCODE_API(priv->ucode_ver) >= 2) { | |
1898 | if (n_probes) | |
0d21044e | 1899 | scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes); |
011a0330 AK |
1900 | } else { |
1901 | /* uCode v1 does not allow setting direct probe bits on | |
1902 | * passive channel. */ | |
1903 | if ((scan_ch->type & 1) && n_probes) | |
0d21044e | 1904 | scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes); |
011a0330 | 1905 | } |
b481de9c | 1906 | |
9fbab516 | 1907 | /* Set txpower levels to defaults */ |
b481de9c ZY |
1908 | scan_ch->tpc.dsp_atten = 110; |
1909 | /* scan_pwr_info->tpc.dsp_atten; */ | |
1910 | ||
1911 | /*scan_pwr_info->tpc.tx_gain; */ | |
8318d78a | 1912 | if (band == IEEE80211_BAND_5GHZ) |
b481de9c ZY |
1913 | scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3; |
1914 | else { | |
1915 | scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3)); | |
1916 | /* NOTE: if we were doing 6Mb OFDM for scans we'd use | |
9fbab516 | 1917 | * power level: |
8a1b0245 | 1918 | * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3; |
b481de9c ZY |
1919 | */ |
1920 | } | |
1921 | ||
e1623446 | 1922 | IWL_DEBUG_SCAN(priv, "Scanning %d [%s %d]\n", |
b481de9c ZY |
1923 | scan_ch->channel, |
1924 | (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE", | |
1925 | (scan_ch->type & 1) ? | |
1926 | active_dwell : passive_dwell); | |
1927 | ||
1928 | scan_ch++; | |
1929 | added++; | |
1930 | } | |
1931 | ||
e1623446 | 1932 | IWL_DEBUG_SCAN(priv, "total channels to scan %d \n", added); |
b481de9c ZY |
1933 | return added; |
1934 | } | |
1935 | ||
4a8a4322 | 1936 | static void iwl3945_init_hw_rates(struct iwl_priv *priv, |
b481de9c ZY |
1937 | struct ieee80211_rate *rates) |
1938 | { | |
1939 | int i; | |
1940 | ||
1941 | for (i = 0; i < IWL_RATE_COUNT; i++) { | |
8318d78a JB |
1942 | rates[i].bitrate = iwl3945_rates[i].ieee * 5; |
1943 | rates[i].hw_value = i; /* Rate scaling will work on indexes */ | |
1944 | rates[i].hw_value_short = i; | |
1945 | rates[i].flags = 0; | |
d9829a67 | 1946 | if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) { |
b481de9c | 1947 | /* |
8318d78a | 1948 | * If CCK != 1M then set short preamble rate flag. |
b481de9c | 1949 | */ |
bb8c093b | 1950 | rates[i].flags |= (iwl3945_rates[i].plcp == 10) ? |
8318d78a | 1951 | 0 : IEEE80211_RATE_SHORT_PREAMBLE; |
b481de9c | 1952 | } |
b481de9c ZY |
1953 | } |
1954 | } | |
1955 | ||
b481de9c ZY |
1956 | /****************************************************************************** |
1957 | * | |
1958 | * uCode download functions | |
1959 | * | |
1960 | ******************************************************************************/ | |
1961 | ||
4a8a4322 | 1962 | static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv) |
b481de9c | 1963 | { |
98c92211 TW |
1964 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code); |
1965 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data); | |
1966 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup); | |
1967 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init); | |
1968 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data); | |
1969 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot); | |
b481de9c ZY |
1970 | } |
1971 | ||
1972 | /** | |
bb8c093b | 1973 | * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host, |
b481de9c ZY |
1974 | * looking at all data. |
1975 | */ | |
4a8a4322 | 1976 | static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len) |
b481de9c ZY |
1977 | { |
1978 | u32 val; | |
1979 | u32 save_len = len; | |
1980 | int rc = 0; | |
1981 | u32 errcnt; | |
1982 | ||
e1623446 | 1983 | IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len); |
b481de9c | 1984 | |
5d49f498 | 1985 | iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, |
250bdd21 | 1986 | IWL39_RTC_INST_LOWER_BOUND); |
b481de9c ZY |
1987 | |
1988 | errcnt = 0; | |
1989 | for (; len > 0; len -= sizeof(u32), image++) { | |
1990 | /* read data comes through single port, auto-incr addr */ | |
1991 | /* NOTE: Use the debugless read so we don't flood kernel log | |
1992 | * if IWL_DL_IO is set */ | |
5d49f498 | 1993 | val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b481de9c | 1994 | if (val != le32_to_cpu(*image)) { |
15b1687c | 1995 | IWL_ERR(priv, "uCode INST section is invalid at " |
b481de9c ZY |
1996 | "offset 0x%x, is 0x%x, s/b 0x%x\n", |
1997 | save_len - len, val, le32_to_cpu(*image)); | |
1998 | rc = -EIO; | |
1999 | errcnt++; | |
2000 | if (errcnt >= 20) | |
2001 | break; | |
2002 | } | |
2003 | } | |
2004 | ||
b481de9c ZY |
2005 | |
2006 | if (!errcnt) | |
e1623446 TW |
2007 | IWL_DEBUG_INFO(priv, |
2008 | "ucode image in INSTRUCTION memory is good\n"); | |
b481de9c ZY |
2009 | |
2010 | return rc; | |
2011 | } | |
2012 | ||
2013 | ||
2014 | /** | |
bb8c093b | 2015 | * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host, |
b481de9c ZY |
2016 | * using sample data 100 bytes apart. If these sample points are good, |
2017 | * it's a pretty good bet that everything between them is good, too. | |
2018 | */ | |
4a8a4322 | 2019 | static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len) |
b481de9c ZY |
2020 | { |
2021 | u32 val; | |
2022 | int rc = 0; | |
2023 | u32 errcnt = 0; | |
2024 | u32 i; | |
2025 | ||
e1623446 | 2026 | IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len); |
b481de9c | 2027 | |
b481de9c ZY |
2028 | for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) { |
2029 | /* read data comes through single port, auto-incr addr */ | |
2030 | /* NOTE: Use the debugless read so we don't flood kernel log | |
2031 | * if IWL_DL_IO is set */ | |
5d49f498 | 2032 | iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, |
250bdd21 | 2033 | i + IWL39_RTC_INST_LOWER_BOUND); |
5d49f498 | 2034 | val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b481de9c ZY |
2035 | if (val != le32_to_cpu(*image)) { |
2036 | #if 0 /* Enable this if you want to see details */ | |
15b1687c | 2037 | IWL_ERR(priv, "uCode INST section is invalid at " |
b481de9c ZY |
2038 | "offset 0x%x, is 0x%x, s/b 0x%x\n", |
2039 | i, val, *image); | |
2040 | #endif | |
2041 | rc = -EIO; | |
2042 | errcnt++; | |
2043 | if (errcnt >= 3) | |
2044 | break; | |
2045 | } | |
2046 | } | |
2047 | ||
b481de9c ZY |
2048 | return rc; |
2049 | } | |
2050 | ||
2051 | ||
2052 | /** | |
bb8c093b | 2053 | * iwl3945_verify_ucode - determine which instruction image is in SRAM, |
b481de9c ZY |
2054 | * and verify its contents |
2055 | */ | |
4a8a4322 | 2056 | static int iwl3945_verify_ucode(struct iwl_priv *priv) |
b481de9c ZY |
2057 | { |
2058 | __le32 *image; | |
2059 | u32 len; | |
2060 | int rc = 0; | |
2061 | ||
2062 | /* Try bootstrap */ | |
2063 | image = (__le32 *)priv->ucode_boot.v_addr; | |
2064 | len = priv->ucode_boot.len; | |
bb8c093b | 2065 | rc = iwl3945_verify_inst_sparse(priv, image, len); |
b481de9c | 2066 | if (rc == 0) { |
e1623446 | 2067 | IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n"); |
b481de9c ZY |
2068 | return 0; |
2069 | } | |
2070 | ||
2071 | /* Try initialize */ | |
2072 | image = (__le32 *)priv->ucode_init.v_addr; | |
2073 | len = priv->ucode_init.len; | |
bb8c093b | 2074 | rc = iwl3945_verify_inst_sparse(priv, image, len); |
b481de9c | 2075 | if (rc == 0) { |
e1623446 | 2076 | IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n"); |
b481de9c ZY |
2077 | return 0; |
2078 | } | |
2079 | ||
2080 | /* Try runtime/protocol */ | |
2081 | image = (__le32 *)priv->ucode_code.v_addr; | |
2082 | len = priv->ucode_code.len; | |
bb8c093b | 2083 | rc = iwl3945_verify_inst_sparse(priv, image, len); |
b481de9c | 2084 | if (rc == 0) { |
e1623446 | 2085 | IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n"); |
b481de9c ZY |
2086 | return 0; |
2087 | } | |
2088 | ||
15b1687c | 2089 | IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n"); |
b481de9c | 2090 | |
9fbab516 BC |
2091 | /* Since nothing seems to match, show first several data entries in |
2092 | * instruction SRAM, so maybe visual inspection will give a clue. | |
2093 | * Selection of bootstrap image (vs. other images) is arbitrary. */ | |
b481de9c ZY |
2094 | image = (__le32 *)priv->ucode_boot.v_addr; |
2095 | len = priv->ucode_boot.len; | |
bb8c093b | 2096 | rc = iwl3945_verify_inst_full(priv, image, len); |
b481de9c ZY |
2097 | |
2098 | return rc; | |
2099 | } | |
2100 | ||
4a8a4322 | 2101 | static void iwl3945_nic_start(struct iwl_priv *priv) |
b481de9c ZY |
2102 | { |
2103 | /* Remove all resets to allow NIC to operate */ | |
5d49f498 | 2104 | iwl_write32(priv, CSR_RESET, 0); |
b481de9c ZY |
2105 | } |
2106 | ||
2107 | /** | |
bb8c093b | 2108 | * iwl3945_read_ucode - Read uCode images from disk file. |
b481de9c ZY |
2109 | * |
2110 | * Copy into buffers for card to fetch via bus-mastering | |
2111 | */ | |
4a8a4322 | 2112 | static int iwl3945_read_ucode(struct iwl_priv *priv) |
b481de9c | 2113 | { |
a78fe754 | 2114 | struct iwl_ucode *ucode; |
a0987a8d | 2115 | int ret = -EINVAL, index; |
b481de9c ZY |
2116 | const struct firmware *ucode_raw; |
2117 | /* firmware file name contains uCode/driver compatibility version */ | |
a0987a8d RC |
2118 | const char *name_pre = priv->cfg->fw_name_pre; |
2119 | const unsigned int api_max = priv->cfg->ucode_api_max; | |
2120 | const unsigned int api_min = priv->cfg->ucode_api_min; | |
2121 | char buf[25]; | |
b481de9c ZY |
2122 | u8 *src; |
2123 | size_t len; | |
a0987a8d | 2124 | u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size; |
b481de9c ZY |
2125 | |
2126 | /* Ask kernel firmware_class module to get the boot firmware off disk. | |
2127 | * request_firmware() is synchronous, file is in memory on return. */ | |
a0987a8d RC |
2128 | for (index = api_max; index >= api_min; index--) { |
2129 | sprintf(buf, "%s%u%s", name_pre, index, ".ucode"); | |
2130 | ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev); | |
2131 | if (ret < 0) { | |
15b1687c | 2132 | IWL_ERR(priv, "%s firmware file req failed: %d\n", |
a0987a8d RC |
2133 | buf, ret); |
2134 | if (ret == -ENOENT) | |
2135 | continue; | |
2136 | else | |
2137 | goto error; | |
2138 | } else { | |
2139 | if (index < api_max) | |
15b1687c WT |
2140 | IWL_ERR(priv, "Loaded firmware %s, " |
2141 | "which is deprecated. " | |
2142 | " Please use API v%u instead.\n", | |
a0987a8d | 2143 | buf, api_max); |
e1623446 TW |
2144 | IWL_DEBUG_INFO(priv, "Got firmware '%s' file " |
2145 | "(%zd bytes) from disk\n", | |
a0987a8d RC |
2146 | buf, ucode_raw->size); |
2147 | break; | |
2148 | } | |
b481de9c ZY |
2149 | } |
2150 | ||
a0987a8d RC |
2151 | if (ret < 0) |
2152 | goto error; | |
b481de9c ZY |
2153 | |
2154 | /* Make sure that we got at least our header! */ | |
2155 | if (ucode_raw->size < sizeof(*ucode)) { | |
15b1687c | 2156 | IWL_ERR(priv, "File size way too small!\n"); |
90e759d1 | 2157 | ret = -EINVAL; |
b481de9c ZY |
2158 | goto err_release; |
2159 | } | |
2160 | ||
2161 | /* Data from ucode file: header followed by uCode images */ | |
2162 | ucode = (void *)ucode_raw->data; | |
2163 | ||
c02b3acd | 2164 | priv->ucode_ver = le32_to_cpu(ucode->ver); |
a0987a8d | 2165 | api_ver = IWL_UCODE_API(priv->ucode_ver); |
b481de9c ZY |
2166 | inst_size = le32_to_cpu(ucode->inst_size); |
2167 | data_size = le32_to_cpu(ucode->data_size); | |
2168 | init_size = le32_to_cpu(ucode->init_size); | |
2169 | init_data_size = le32_to_cpu(ucode->init_data_size); | |
2170 | boot_size = le32_to_cpu(ucode->boot_size); | |
2171 | ||
a0987a8d RC |
2172 | /* api_ver should match the api version forming part of the |
2173 | * firmware filename ... but we don't check for that and only rely | |
877d0310 | 2174 | * on the API version read from firmware header from here on forward */ |
a0987a8d RC |
2175 | |
2176 | if (api_ver < api_min || api_ver > api_max) { | |
15b1687c | 2177 | IWL_ERR(priv, "Driver unable to support your firmware API. " |
a0987a8d RC |
2178 | "Driver supports v%u, firmware is v%u.\n", |
2179 | api_max, api_ver); | |
2180 | priv->ucode_ver = 0; | |
2181 | ret = -EINVAL; | |
2182 | goto err_release; | |
2183 | } | |
2184 | if (api_ver != api_max) | |
15b1687c | 2185 | IWL_ERR(priv, "Firmware has old API version. Expected %u, " |
a0987a8d RC |
2186 | "got %u. New firmware can be obtained " |
2187 | "from http://www.intellinuxwireless.org.\n", | |
2188 | api_max, api_ver); | |
2189 | ||
978785a3 TW |
2190 | IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n", |
2191 | IWL_UCODE_MAJOR(priv->ucode_ver), | |
2192 | IWL_UCODE_MINOR(priv->ucode_ver), | |
2193 | IWL_UCODE_API(priv->ucode_ver), | |
2194 | IWL_UCODE_SERIAL(priv->ucode_ver)); | |
2195 | ||
e1623446 | 2196 | IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n", |
a0987a8d | 2197 | priv->ucode_ver); |
e1623446 TW |
2198 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n", |
2199 | inst_size); | |
2200 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n", | |
2201 | data_size); | |
2202 | IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n", | |
2203 | init_size); | |
2204 | IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n", | |
2205 | init_data_size); | |
2206 | IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n", | |
2207 | boot_size); | |
b481de9c | 2208 | |
a0987a8d | 2209 | |
b481de9c ZY |
2210 | /* Verify size of file vs. image size info in file's header */ |
2211 | if (ucode_raw->size < sizeof(*ucode) + | |
2212 | inst_size + data_size + init_size + | |
2213 | init_data_size + boot_size) { | |
2214 | ||
e1623446 TW |
2215 | IWL_DEBUG_INFO(priv, "uCode file size %zd too small\n", |
2216 | ucode_raw->size); | |
90e759d1 | 2217 | ret = -EINVAL; |
b481de9c ZY |
2218 | goto err_release; |
2219 | } | |
2220 | ||
2221 | /* Verify that uCode images will fit in card's SRAM */ | |
250bdd21 | 2222 | if (inst_size > IWL39_MAX_INST_SIZE) { |
e1623446 | 2223 | IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n", |
90e759d1 TW |
2224 | inst_size); |
2225 | ret = -EINVAL; | |
b481de9c ZY |
2226 | goto err_release; |
2227 | } | |
2228 | ||
250bdd21 | 2229 | if (data_size > IWL39_MAX_DATA_SIZE) { |
e1623446 | 2230 | IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n", |
90e759d1 TW |
2231 | data_size); |
2232 | ret = -EINVAL; | |
b481de9c ZY |
2233 | goto err_release; |
2234 | } | |
250bdd21 | 2235 | if (init_size > IWL39_MAX_INST_SIZE) { |
e1623446 TW |
2236 | IWL_DEBUG_INFO(priv, |
2237 | "uCode init instr len %d too large to fit in\n", | |
90e759d1 TW |
2238 | init_size); |
2239 | ret = -EINVAL; | |
b481de9c ZY |
2240 | goto err_release; |
2241 | } | |
250bdd21 | 2242 | if (init_data_size > IWL39_MAX_DATA_SIZE) { |
e1623446 TW |
2243 | IWL_DEBUG_INFO(priv, |
2244 | "uCode init data len %d too large to fit in\n", | |
90e759d1 TW |
2245 | init_data_size); |
2246 | ret = -EINVAL; | |
b481de9c ZY |
2247 | goto err_release; |
2248 | } | |
250bdd21 | 2249 | if (boot_size > IWL39_MAX_BSM_SIZE) { |
e1623446 TW |
2250 | IWL_DEBUG_INFO(priv, |
2251 | "uCode boot instr len %d too large to fit in\n", | |
90e759d1 TW |
2252 | boot_size); |
2253 | ret = -EINVAL; | |
b481de9c ZY |
2254 | goto err_release; |
2255 | } | |
2256 | ||
2257 | /* Allocate ucode buffers for card's bus-master loading ... */ | |
2258 | ||
2259 | /* Runtime instructions and 2 copies of data: | |
2260 | * 1) unmodified from disk | |
2261 | * 2) backup cache for save/restore during power-downs */ | |
2262 | priv->ucode_code.len = inst_size; | |
98c92211 | 2263 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code); |
b481de9c ZY |
2264 | |
2265 | priv->ucode_data.len = data_size; | |
98c92211 | 2266 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data); |
b481de9c ZY |
2267 | |
2268 | priv->ucode_data_backup.len = data_size; | |
98c92211 | 2269 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup); |
b481de9c | 2270 | |
90e759d1 TW |
2271 | if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr || |
2272 | !priv->ucode_data_backup.v_addr) | |
2273 | goto err_pci_alloc; | |
b481de9c ZY |
2274 | |
2275 | /* Initialization instructions and data */ | |
90e759d1 TW |
2276 | if (init_size && init_data_size) { |
2277 | priv->ucode_init.len = init_size; | |
98c92211 | 2278 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init); |
90e759d1 TW |
2279 | |
2280 | priv->ucode_init_data.len = init_data_size; | |
98c92211 | 2281 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data); |
90e759d1 TW |
2282 | |
2283 | if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr) | |
2284 | goto err_pci_alloc; | |
2285 | } | |
b481de9c ZY |
2286 | |
2287 | /* Bootstrap (instructions only, no data) */ | |
90e759d1 TW |
2288 | if (boot_size) { |
2289 | priv->ucode_boot.len = boot_size; | |
98c92211 | 2290 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot); |
b481de9c | 2291 | |
90e759d1 TW |
2292 | if (!priv->ucode_boot.v_addr) |
2293 | goto err_pci_alloc; | |
2294 | } | |
b481de9c ZY |
2295 | |
2296 | /* Copy images into buffers for card's bus-master reads ... */ | |
2297 | ||
2298 | /* Runtime instructions (first block of data in file) */ | |
2299 | src = &ucode->data[0]; | |
2300 | len = priv->ucode_code.len; | |
e1623446 TW |
2301 | IWL_DEBUG_INFO(priv, |
2302 | "Copying (but not loading) uCode instr len %zd\n", len); | |
b481de9c | 2303 | memcpy(priv->ucode_code.v_addr, src, len); |
e1623446 | 2304 | IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n", |
b481de9c ZY |
2305 | priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr); |
2306 | ||
2307 | /* Runtime data (2nd block) | |
bb8c093b | 2308 | * NOTE: Copy into backup buffer will be done in iwl3945_up() */ |
b481de9c ZY |
2309 | src = &ucode->data[inst_size]; |
2310 | len = priv->ucode_data.len; | |
e1623446 TW |
2311 | IWL_DEBUG_INFO(priv, |
2312 | "Copying (but not loading) uCode data len %zd\n", len); | |
b481de9c ZY |
2313 | memcpy(priv->ucode_data.v_addr, src, len); |
2314 | memcpy(priv->ucode_data_backup.v_addr, src, len); | |
2315 | ||
2316 | /* Initialization instructions (3rd block) */ | |
2317 | if (init_size) { | |
2318 | src = &ucode->data[inst_size + data_size]; | |
2319 | len = priv->ucode_init.len; | |
e1623446 TW |
2320 | IWL_DEBUG_INFO(priv, |
2321 | "Copying (but not loading) init instr len %zd\n", len); | |
b481de9c ZY |
2322 | memcpy(priv->ucode_init.v_addr, src, len); |
2323 | } | |
2324 | ||
2325 | /* Initialization data (4th block) */ | |
2326 | if (init_data_size) { | |
2327 | src = &ucode->data[inst_size + data_size + init_size]; | |
2328 | len = priv->ucode_init_data.len; | |
e1623446 TW |
2329 | IWL_DEBUG_INFO(priv, |
2330 | "Copying (but not loading) init data len %zd\n", len); | |
b481de9c ZY |
2331 | memcpy(priv->ucode_init_data.v_addr, src, len); |
2332 | } | |
2333 | ||
2334 | /* Bootstrap instructions (5th block) */ | |
2335 | src = &ucode->data[inst_size + data_size + init_size + init_data_size]; | |
2336 | len = priv->ucode_boot.len; | |
e1623446 TW |
2337 | IWL_DEBUG_INFO(priv, |
2338 | "Copying (but not loading) boot instr len %zd\n", len); | |
b481de9c ZY |
2339 | memcpy(priv->ucode_boot.v_addr, src, len); |
2340 | ||
2341 | /* We have our copies now, allow OS release its copies */ | |
2342 | release_firmware(ucode_raw); | |
2343 | return 0; | |
2344 | ||
2345 | err_pci_alloc: | |
15b1687c | 2346 | IWL_ERR(priv, "failed to allocate pci memory\n"); |
90e759d1 | 2347 | ret = -ENOMEM; |
bb8c093b | 2348 | iwl3945_dealloc_ucode_pci(priv); |
b481de9c ZY |
2349 | |
2350 | err_release: | |
2351 | release_firmware(ucode_raw); | |
2352 | ||
2353 | error: | |
90e759d1 | 2354 | return ret; |
b481de9c ZY |
2355 | } |
2356 | ||
2357 | ||
2358 | /** | |
bb8c093b | 2359 | * iwl3945_set_ucode_ptrs - Set uCode address location |
b481de9c ZY |
2360 | * |
2361 | * Tell initialization uCode where to find runtime uCode. | |
2362 | * | |
2363 | * BSM registers initially contain pointers to initialization uCode. | |
2364 | * We need to replace them to load runtime uCode inst and data, | |
2365 | * and to save runtime data when powering down. | |
2366 | */ | |
4a8a4322 | 2367 | static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv) |
b481de9c ZY |
2368 | { |
2369 | dma_addr_t pinst; | |
2370 | dma_addr_t pdata; | |
b481de9c ZY |
2371 | |
2372 | /* bits 31:0 for 3945 */ | |
2373 | pinst = priv->ucode_code.p_addr; | |
2374 | pdata = priv->ucode_data_backup.p_addr; | |
2375 | ||
b481de9c | 2376 | /* Tell bootstrap uCode where to find image to load */ |
5d49f498 AK |
2377 | iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); |
2378 | iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); | |
2379 | iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, | |
b481de9c ZY |
2380 | priv->ucode_data.len); |
2381 | ||
a96a27f9 | 2382 | /* Inst byte count must be last to set up, bit 31 signals uCode |
b481de9c | 2383 | * that all new ptr/size info is in place */ |
5d49f498 | 2384 | iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, |
b481de9c ZY |
2385 | priv->ucode_code.len | BSM_DRAM_INST_LOAD); |
2386 | ||
e1623446 | 2387 | IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n"); |
b481de9c | 2388 | |
a8b50a0a | 2389 | return 0; |
b481de9c ZY |
2390 | } |
2391 | ||
2392 | /** | |
bb8c093b | 2393 | * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received |
b481de9c ZY |
2394 | * |
2395 | * Called after REPLY_ALIVE notification received from "initialize" uCode. | |
2396 | * | |
b481de9c | 2397 | * Tell "initialize" uCode to go ahead and load the runtime uCode. |
9fbab516 | 2398 | */ |
4a8a4322 | 2399 | static void iwl3945_init_alive_start(struct iwl_priv *priv) |
b481de9c ZY |
2400 | { |
2401 | /* Check alive response for "valid" sign from uCode */ | |
2402 | if (priv->card_alive_init.is_valid != UCODE_VALID_OK) { | |
2403 | /* We had an error bringing up the hardware, so take it | |
2404 | * all the way back down so we can try again */ | |
e1623446 | 2405 | IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n"); |
b481de9c ZY |
2406 | goto restart; |
2407 | } | |
2408 | ||
2409 | /* Bootstrap uCode has loaded initialize uCode ... verify inst image. | |
2410 | * This is a paranoid check, because we would not have gotten the | |
2411 | * "initialize" alive if code weren't properly loaded. */ | |
bb8c093b | 2412 | if (iwl3945_verify_ucode(priv)) { |
b481de9c ZY |
2413 | /* Runtime instruction load was bad; |
2414 | * take it all the way back down so we can try again */ | |
e1623446 | 2415 | IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n"); |
b481de9c ZY |
2416 | goto restart; |
2417 | } | |
2418 | ||
2419 | /* Send pointers to protocol/runtime uCode image ... init code will | |
2420 | * load and launch runtime uCode, which will send us another "Alive" | |
2421 | * notification. */ | |
e1623446 | 2422 | IWL_DEBUG_INFO(priv, "Initialization Alive received.\n"); |
bb8c093b | 2423 | if (iwl3945_set_ucode_ptrs(priv)) { |
b481de9c ZY |
2424 | /* Runtime instruction load won't happen; |
2425 | * take it all the way back down so we can try again */ | |
e1623446 | 2426 | IWL_DEBUG_INFO(priv, "Couldn't set up uCode pointers.\n"); |
b481de9c ZY |
2427 | goto restart; |
2428 | } | |
2429 | return; | |
2430 | ||
2431 | restart: | |
2432 | queue_work(priv->workqueue, &priv->restart); | |
2433 | } | |
2434 | ||
b481de9c | 2435 | /** |
bb8c093b | 2436 | * iwl3945_alive_start - called after REPLY_ALIVE notification received |
b481de9c | 2437 | * from protocol/runtime uCode (initialization uCode's |
bb8c093b | 2438 | * Alive gets handled by iwl3945_init_alive_start()). |
b481de9c | 2439 | */ |
4a8a4322 | 2440 | static void iwl3945_alive_start(struct iwl_priv *priv) |
b481de9c | 2441 | { |
b481de9c ZY |
2442 | int thermal_spin = 0; |
2443 | u32 rfkill; | |
2444 | ||
e1623446 | 2445 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c ZY |
2446 | |
2447 | if (priv->card_alive.is_valid != UCODE_VALID_OK) { | |
2448 | /* We had an error bringing up the hardware, so take it | |
2449 | * all the way back down so we can try again */ | |
e1623446 | 2450 | IWL_DEBUG_INFO(priv, "Alive failed.\n"); |
b481de9c ZY |
2451 | goto restart; |
2452 | } | |
2453 | ||
2454 | /* Initialize uCode has loaded Runtime uCode ... verify inst image. | |
2455 | * This is a paranoid check, because we would not have gotten the | |
2456 | * "runtime" alive if code weren't properly loaded. */ | |
bb8c093b | 2457 | if (iwl3945_verify_ucode(priv)) { |
b481de9c ZY |
2458 | /* Runtime instruction load was bad; |
2459 | * take it all the way back down so we can try again */ | |
e1623446 | 2460 | IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n"); |
b481de9c ZY |
2461 | goto restart; |
2462 | } | |
2463 | ||
c587de0b | 2464 | iwl_clear_stations_table(priv); |
b481de9c | 2465 | |
5d49f498 | 2466 | rfkill = iwl_read_prph(priv, APMG_RFKILL_REG); |
e1623446 | 2467 | IWL_DEBUG_INFO(priv, "RFKILL status: 0x%x\n", rfkill); |
b481de9c ZY |
2468 | |
2469 | if (rfkill & 0x1) { | |
2470 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
a96a27f9 | 2471 | /* if RFKILL is not on, then wait for thermal |
b481de9c | 2472 | * sensor in adapter to kick in */ |
bb8c093b | 2473 | while (iwl3945_hw_get_temperature(priv) == 0) { |
b481de9c ZY |
2474 | thermal_spin++; |
2475 | udelay(10); | |
2476 | } | |
2477 | ||
2478 | if (thermal_spin) | |
e1623446 | 2479 | IWL_DEBUG_INFO(priv, "Thermal calibration took %dus\n", |
b481de9c ZY |
2480 | thermal_spin * 10); |
2481 | } else | |
2482 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
2483 | ||
9fbab516 | 2484 | /* After the ALIVE response, we can send commands to 3945 uCode */ |
b481de9c ZY |
2485 | set_bit(STATUS_ALIVE, &priv->status); |
2486 | ||
775a6e27 | 2487 | if (iwl_is_rfkill(priv)) |
b481de9c ZY |
2488 | return; |
2489 | ||
36d6825b | 2490 | ieee80211_wake_queues(priv->hw); |
b481de9c ZY |
2491 | |
2492 | priv->active_rate = priv->rates_mask; | |
2493 | priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK; | |
2494 | ||
d25aabb0 | 2495 | iwl_power_update_mode(priv, false); |
b481de9c | 2496 | |
8ccde88a | 2497 | if (iwl_is_associated(priv)) { |
bb8c093b | 2498 | struct iwl3945_rxon_cmd *active_rxon = |
8ccde88a | 2499 | (struct iwl3945_rxon_cmd *)(&priv->active_rxon); |
b481de9c | 2500 | |
8a9b9926 | 2501 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; |
b481de9c ZY |
2502 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
2503 | } else { | |
2504 | /* Initialize our rx_config data */ | |
8ccde88a | 2505 | iwl_connection_init_rx_config(priv, priv->iw_mode); |
b481de9c ZY |
2506 | } |
2507 | ||
9fbab516 | 2508 | /* Configure Bluetooth device coexistence support */ |
17f841cd | 2509 | iwl_send_bt_config(priv); |
b481de9c ZY |
2510 | |
2511 | /* Configure the adapter for unassociated operation */ | |
e0158e61 | 2512 | iwlcore_commit_rxon(priv); |
b481de9c | 2513 | |
b481de9c ZY |
2514 | iwl3945_reg_txpower_periodic(priv); |
2515 | ||
fe00b5a5 RC |
2516 | iwl3945_led_register(priv); |
2517 | ||
e1623446 | 2518 | IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n"); |
a9f46786 | 2519 | set_bit(STATUS_READY, &priv->status); |
5a66926a | 2520 | wake_up_interruptible(&priv->wait_command_queue); |
b481de9c | 2521 | |
9bdf5eca MA |
2522 | /* reassociate for ADHOC mode */ |
2523 | if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) { | |
2524 | struct sk_buff *beacon = ieee80211_beacon_get(priv->hw, | |
2525 | priv->vif); | |
2526 | if (beacon) | |
9944b938 | 2527 | iwl_mac_beacon_update(priv->hw, beacon); |
9bdf5eca MA |
2528 | } |
2529 | ||
f45c2714 | 2530 | if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status)) |
727882d6 | 2531 | iwl_set_mode(priv, priv->iw_mode); |
f45c2714 | 2532 | |
b481de9c ZY |
2533 | return; |
2534 | ||
2535 | restart: | |
2536 | queue_work(priv->workqueue, &priv->restart); | |
2537 | } | |
2538 | ||
4a8a4322 | 2539 | static void iwl3945_cancel_deferred_work(struct iwl_priv *priv); |
b481de9c | 2540 | |
4a8a4322 | 2541 | static void __iwl3945_down(struct iwl_priv *priv) |
b481de9c ZY |
2542 | { |
2543 | unsigned long flags; | |
2544 | int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status); | |
2545 | struct ieee80211_conf *conf = NULL; | |
2546 | ||
e1623446 | 2547 | IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n"); |
b481de9c ZY |
2548 | |
2549 | conf = ieee80211_get_hw_conf(priv->hw); | |
2550 | ||
2551 | if (!exit_pending) | |
2552 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
2553 | ||
ab53d8af | 2554 | iwl3945_led_unregister(priv); |
c587de0b | 2555 | iwl_clear_stations_table(priv); |
b481de9c ZY |
2556 | |
2557 | /* Unblock any waiting calls */ | |
2558 | wake_up_interruptible_all(&priv->wait_command_queue); | |
2559 | ||
b481de9c ZY |
2560 | /* Wipe out the EXIT_PENDING status bit if we are not actually |
2561 | * exiting the module */ | |
2562 | if (!exit_pending) | |
2563 | clear_bit(STATUS_EXIT_PENDING, &priv->status); | |
2564 | ||
2565 | /* stop and reset the on-board processor */ | |
5d49f498 | 2566 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
b481de9c ZY |
2567 | |
2568 | /* tell the device to stop sending interrupts */ | |
0359facc | 2569 | spin_lock_irqsave(&priv->lock, flags); |
ed3b932e | 2570 | iwl_disable_interrupts(priv); |
0359facc MA |
2571 | spin_unlock_irqrestore(&priv->lock, flags); |
2572 | iwl_synchronize_irq(priv); | |
b481de9c ZY |
2573 | |
2574 | if (priv->mac80211_registered) | |
2575 | ieee80211_stop_queues(priv->hw); | |
2576 | ||
bb8c093b | 2577 | /* If we have not previously called iwl3945_init() then |
6da3a13e | 2578 | * clear all bits but the RF Kill bits and return */ |
775a6e27 | 2579 | if (!iwl_is_init(priv)) { |
b481de9c ZY |
2580 | priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) << |
2581 | STATUS_RF_KILL_HW | | |
9788864e RC |
2582 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
2583 | STATUS_GEO_CONFIGURED | | |
ebef2008 AK |
2584 | test_bit(STATUS_EXIT_PENDING, &priv->status) << |
2585 | STATUS_EXIT_PENDING; | |
b481de9c ZY |
2586 | goto exit; |
2587 | } | |
2588 | ||
6da3a13e | 2589 | /* ...otherwise clear out all the status bits but the RF Kill |
a60e77e5 | 2590 | * bit and continue taking the NIC down. */ |
b481de9c ZY |
2591 | priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) << |
2592 | STATUS_RF_KILL_HW | | |
9788864e RC |
2593 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
2594 | STATUS_GEO_CONFIGURED | | |
b481de9c | 2595 | test_bit(STATUS_FW_ERROR, &priv->status) << |
ebef2008 AK |
2596 | STATUS_FW_ERROR | |
2597 | test_bit(STATUS_EXIT_PENDING, &priv->status) << | |
2598 | STATUS_EXIT_PENDING; | |
b481de9c | 2599 | |
e9414b6b | 2600 | priv->cfg->ops->lib->apm_ops.reset(priv); |
b481de9c | 2601 | spin_lock_irqsave(&priv->lock, flags); |
5d49f498 | 2602 | iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
b481de9c ZY |
2603 | spin_unlock_irqrestore(&priv->lock, flags); |
2604 | ||
bb8c093b CH |
2605 | iwl3945_hw_txq_ctx_stop(priv); |
2606 | iwl3945_hw_rxq_stop(priv); | |
b481de9c | 2607 | |
a8b50a0a MA |
2608 | iwl_write_prph(priv, APMG_CLK_DIS_REG, |
2609 | APMG_CLK_VAL_DMA_CLK_RQT); | |
b481de9c ZY |
2610 | |
2611 | udelay(5); | |
2612 | ||
6da3a13e | 2613 | if (exit_pending) |
e9414b6b AM |
2614 | priv->cfg->ops->lib->apm_ops.stop(priv); |
2615 | else | |
2616 | priv->cfg->ops->lib->apm_ops.reset(priv); | |
2617 | ||
b481de9c | 2618 | exit: |
3d24a9f7 | 2619 | memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp)); |
b481de9c ZY |
2620 | |
2621 | if (priv->ibss_beacon) | |
2622 | dev_kfree_skb(priv->ibss_beacon); | |
2623 | priv->ibss_beacon = NULL; | |
2624 | ||
2625 | /* clear out any free frames */ | |
bb8c093b | 2626 | iwl3945_clear_free_frames(priv); |
b481de9c ZY |
2627 | } |
2628 | ||
4a8a4322 | 2629 | static void iwl3945_down(struct iwl_priv *priv) |
b481de9c ZY |
2630 | { |
2631 | mutex_lock(&priv->mutex); | |
bb8c093b | 2632 | __iwl3945_down(priv); |
b481de9c | 2633 | mutex_unlock(&priv->mutex); |
b24d22b1 | 2634 | |
bb8c093b | 2635 | iwl3945_cancel_deferred_work(priv); |
b481de9c ZY |
2636 | } |
2637 | ||
2638 | #define MAX_HW_RESTARTS 5 | |
2639 | ||
4a8a4322 | 2640 | static int __iwl3945_up(struct iwl_priv *priv) |
b481de9c ZY |
2641 | { |
2642 | int rc, i; | |
2643 | ||
2644 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
39aadf8c | 2645 | IWL_WARN(priv, "Exit pending; will not bring the NIC up\n"); |
b481de9c ZY |
2646 | return -EIO; |
2647 | } | |
2648 | ||
e903fbd4 | 2649 | if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) { |
15b1687c | 2650 | IWL_ERR(priv, "ucode not available for device bring up\n"); |
e903fbd4 RC |
2651 | return -EIO; |
2652 | } | |
2653 | ||
e655b9f0 | 2654 | /* If platform's RF_KILL switch is NOT set to KILL */ |
5d49f498 | 2655 | if (iwl_read32(priv, CSR_GP_CNTRL) & |
e655b9f0 ZY |
2656 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
2657 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
2658 | else { | |
2659 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
6da3a13e WYG |
2660 | IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n"); |
2661 | return -ENODEV; | |
b481de9c | 2662 | } |
80fcc9e2 | 2663 | |
5d49f498 | 2664 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
b481de9c | 2665 | |
bb8c093b | 2666 | rc = iwl3945_hw_nic_init(priv); |
b481de9c | 2667 | if (rc) { |
15b1687c | 2668 | IWL_ERR(priv, "Unable to int nic\n"); |
b481de9c ZY |
2669 | return rc; |
2670 | } | |
2671 | ||
2672 | /* make sure rfkill handshake bits are cleared */ | |
5d49f498 AK |
2673 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2674 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
b481de9c ZY |
2675 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
2676 | ||
2677 | /* clear (again), then enable host interrupts */ | |
5d49f498 | 2678 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
ed3b932e | 2679 | iwl_enable_interrupts(priv); |
b481de9c ZY |
2680 | |
2681 | /* really make sure rfkill handshake bits are cleared */ | |
5d49f498 AK |
2682 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2683 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
b481de9c ZY |
2684 | |
2685 | /* Copy original ucode data image from disk into backup cache. | |
2686 | * This will be used to initialize the on-board processor's | |
2687 | * data SRAM for a clean start when the runtime program first loads. */ | |
2688 | memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr, | |
5a66926a | 2689 | priv->ucode_data.len); |
b481de9c | 2690 | |
e655b9f0 ZY |
2691 | /* We return success when we resume from suspend and rf_kill is on. */ |
2692 | if (test_bit(STATUS_RF_KILL_HW, &priv->status)) | |
2693 | return 0; | |
2694 | ||
b481de9c ZY |
2695 | for (i = 0; i < MAX_HW_RESTARTS; i++) { |
2696 | ||
c587de0b | 2697 | iwl_clear_stations_table(priv); |
b481de9c ZY |
2698 | |
2699 | /* load bootstrap state machine, | |
2700 | * load bootstrap program into processor's memory, | |
2701 | * prepare to load the "initialize" uCode */ | |
0164b9b4 | 2702 | priv->cfg->ops->lib->load_ucode(priv); |
b481de9c ZY |
2703 | |
2704 | if (rc) { | |
15b1687c WT |
2705 | IWL_ERR(priv, |
2706 | "Unable to set up bootstrap uCode: %d\n", rc); | |
b481de9c ZY |
2707 | continue; |
2708 | } | |
2709 | ||
2710 | /* start card; "initialize" will load runtime ucode */ | |
bb8c093b | 2711 | iwl3945_nic_start(priv); |
b481de9c | 2712 | |
e1623446 | 2713 | IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n"); |
b481de9c ZY |
2714 | |
2715 | return 0; | |
2716 | } | |
2717 | ||
2718 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
bb8c093b | 2719 | __iwl3945_down(priv); |
ebef2008 | 2720 | clear_bit(STATUS_EXIT_PENDING, &priv->status); |
b481de9c ZY |
2721 | |
2722 | /* tried to restart and config the device for as long as our | |
2723 | * patience could withstand */ | |
15b1687c | 2724 | IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i); |
b481de9c ZY |
2725 | return -EIO; |
2726 | } | |
2727 | ||
2728 | ||
2729 | /***************************************************************************** | |
2730 | * | |
2731 | * Workqueue callbacks | |
2732 | * | |
2733 | *****************************************************************************/ | |
2734 | ||
bb8c093b | 2735 | static void iwl3945_bg_init_alive_start(struct work_struct *data) |
b481de9c | 2736 | { |
4a8a4322 AK |
2737 | struct iwl_priv *priv = |
2738 | container_of(data, struct iwl_priv, init_alive_start.work); | |
b481de9c ZY |
2739 | |
2740 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2741 | return; | |
2742 | ||
2743 | mutex_lock(&priv->mutex); | |
bb8c093b | 2744 | iwl3945_init_alive_start(priv); |
b481de9c ZY |
2745 | mutex_unlock(&priv->mutex); |
2746 | } | |
2747 | ||
bb8c093b | 2748 | static void iwl3945_bg_alive_start(struct work_struct *data) |
b481de9c | 2749 | { |
4a8a4322 AK |
2750 | struct iwl_priv *priv = |
2751 | container_of(data, struct iwl_priv, alive_start.work); | |
b481de9c ZY |
2752 | |
2753 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2754 | return; | |
2755 | ||
2756 | mutex_lock(&priv->mutex); | |
bb8c093b | 2757 | iwl3945_alive_start(priv); |
b481de9c ZY |
2758 | mutex_unlock(&priv->mutex); |
2759 | } | |
2760 | ||
2663516d HS |
2761 | static void iwl3945_rfkill_poll(struct work_struct *data) |
2762 | { | |
2763 | struct iwl_priv *priv = | |
2764 | container_of(data, struct iwl_priv, rfkill_poll.work); | |
2663516d HS |
2765 | |
2766 | if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) | |
2767 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
2768 | else | |
2769 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
2770 | ||
a60e77e5 JB |
2771 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, |
2772 | test_bit(STATUS_RF_KILL_HW, &priv->status)); | |
2663516d HS |
2773 | |
2774 | queue_delayed_work(priv->workqueue, &priv->rfkill_poll, | |
2775 | round_jiffies_relative(2 * HZ)); | |
2776 | ||
2777 | } | |
2778 | ||
b481de9c | 2779 | #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ) |
bb8c093b | 2780 | static void iwl3945_bg_request_scan(struct work_struct *data) |
b481de9c | 2781 | { |
4a8a4322 AK |
2782 | struct iwl_priv *priv = |
2783 | container_of(data, struct iwl_priv, request_scan); | |
c2d79b48 | 2784 | struct iwl_host_cmd cmd = { |
b481de9c | 2785 | .id = REPLY_SCAN_CMD, |
bb8c093b | 2786 | .len = sizeof(struct iwl3945_scan_cmd), |
b481de9c ZY |
2787 | .meta.flags = CMD_SIZE_HUGE, |
2788 | }; | |
2789 | int rc = 0; | |
bb8c093b | 2790 | struct iwl3945_scan_cmd *scan; |
b481de9c | 2791 | struct ieee80211_conf *conf = NULL; |
1ecf9fc1 | 2792 | u8 n_probes = 0; |
8318d78a | 2793 | enum ieee80211_band band; |
1ecf9fc1 | 2794 | bool is_active = false; |
b481de9c ZY |
2795 | |
2796 | conf = ieee80211_get_hw_conf(priv->hw); | |
2797 | ||
2798 | mutex_lock(&priv->mutex); | |
2799 | ||
fbc9f97b RC |
2800 | cancel_delayed_work(&priv->scan_check); |
2801 | ||
775a6e27 | 2802 | if (!iwl_is_ready(priv)) { |
39aadf8c | 2803 | IWL_WARN(priv, "request scan called when driver not ready.\n"); |
b481de9c ZY |
2804 | goto done; |
2805 | } | |
2806 | ||
a96a27f9 | 2807 | /* Make sure the scan wasn't canceled before this queued work |
b481de9c ZY |
2808 | * was given the chance to run... */ |
2809 | if (!test_bit(STATUS_SCANNING, &priv->status)) | |
2810 | goto done; | |
2811 | ||
2812 | /* This should never be called or scheduled if there is currently | |
2813 | * a scan active in the hardware. */ | |
2814 | if (test_bit(STATUS_SCAN_HW, &priv->status)) { | |
e1623446 TW |
2815 | IWL_DEBUG_INFO(priv, "Multiple concurrent scan requests " |
2816 | "Ignoring second request.\n"); | |
b481de9c ZY |
2817 | rc = -EIO; |
2818 | goto done; | |
2819 | } | |
2820 | ||
2821 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
e1623446 | 2822 | IWL_DEBUG_SCAN(priv, "Aborting scan due to device shutdown\n"); |
b481de9c ZY |
2823 | goto done; |
2824 | } | |
2825 | ||
2826 | if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
e1623446 TW |
2827 | IWL_DEBUG_HC(priv, |
2828 | "Scan request while abort pending. Queuing.\n"); | |
b481de9c ZY |
2829 | goto done; |
2830 | } | |
2831 | ||
775a6e27 | 2832 | if (iwl_is_rfkill(priv)) { |
e1623446 | 2833 | IWL_DEBUG_HC(priv, "Aborting scan due to RF Kill activation\n"); |
b481de9c ZY |
2834 | goto done; |
2835 | } | |
2836 | ||
2837 | if (!test_bit(STATUS_READY, &priv->status)) { | |
e1623446 TW |
2838 | IWL_DEBUG_HC(priv, |
2839 | "Scan request while uninitialized. Queuing.\n"); | |
b481de9c ZY |
2840 | goto done; |
2841 | } | |
2842 | ||
2843 | if (!priv->scan_bands) { | |
e1623446 | 2844 | IWL_DEBUG_HC(priv, "Aborting scan due to no requested bands\n"); |
b481de9c ZY |
2845 | goto done; |
2846 | } | |
2847 | ||
805cee5b WT |
2848 | if (!priv->scan) { |
2849 | priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) + | |
b481de9c | 2850 | IWL_MAX_SCAN_SIZE, GFP_KERNEL); |
805cee5b | 2851 | if (!priv->scan) { |
b481de9c ZY |
2852 | rc = -ENOMEM; |
2853 | goto done; | |
2854 | } | |
2855 | } | |
805cee5b | 2856 | scan = priv->scan; |
bb8c093b | 2857 | memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE); |
b481de9c ZY |
2858 | |
2859 | scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH; | |
2860 | scan->quiet_time = IWL_ACTIVE_QUIET_TIME; | |
2861 | ||
8ccde88a | 2862 | if (iwl_is_associated(priv)) { |
b481de9c ZY |
2863 | u16 interval = 0; |
2864 | u32 extra; | |
2865 | u32 suspend_time = 100; | |
2866 | u32 scan_suspend_time = 100; | |
2867 | unsigned long flags; | |
2868 | ||
e1623446 | 2869 | IWL_DEBUG_INFO(priv, "Scanning while associated...\n"); |
b481de9c ZY |
2870 | |
2871 | spin_lock_irqsave(&priv->lock, flags); | |
2872 | interval = priv->beacon_int; | |
2873 | spin_unlock_irqrestore(&priv->lock, flags); | |
2874 | ||
2875 | scan->suspend_time = 0; | |
15e869d8 | 2876 | scan->max_out_time = cpu_to_le32(200 * 1024); |
b481de9c ZY |
2877 | if (!interval) |
2878 | interval = suspend_time; | |
2879 | /* | |
2880 | * suspend time format: | |
2881 | * 0-19: beacon interval in usec (time before exec.) | |
2882 | * 20-23: 0 | |
2883 | * 24-31: number of beacons (suspend between channels) | |
2884 | */ | |
2885 | ||
2886 | extra = (suspend_time / interval) << 24; | |
2887 | scan_suspend_time = 0xFF0FFFFF & | |
2888 | (extra | ((suspend_time % interval) * 1024)); | |
2889 | ||
2890 | scan->suspend_time = cpu_to_le32(scan_suspend_time); | |
e1623446 | 2891 | IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n", |
b481de9c ZY |
2892 | scan_suspend_time, interval); |
2893 | } | |
2894 | ||
1ecf9fc1 JB |
2895 | if (priv->scan_request->n_ssids) { |
2896 | int i, p = 0; | |
2897 | IWL_DEBUG_SCAN(priv, "Kicking off active scan\n"); | |
2898 | for (i = 0; i < priv->scan_request->n_ssids; i++) { | |
2899 | /* always does wildcard anyway */ | |
2900 | if (!priv->scan_request->ssids[i].ssid_len) | |
2901 | continue; | |
2902 | scan->direct_scan[p].id = WLAN_EID_SSID; | |
2903 | scan->direct_scan[p].len = | |
2904 | priv->scan_request->ssids[i].ssid_len; | |
2905 | memcpy(scan->direct_scan[p].ssid, | |
2906 | priv->scan_request->ssids[i].ssid, | |
2907 | priv->scan_request->ssids[i].ssid_len); | |
2908 | n_probes++; | |
2909 | p++; | |
2910 | } | |
2911 | is_active = true; | |
f9340520 | 2912 | } else |
1ecf9fc1 | 2913 | IWL_DEBUG_SCAN(priv, "Kicking off passive scan.\n"); |
b481de9c ZY |
2914 | |
2915 | /* We don't build a direct scan probe request; the uCode will do | |
2916 | * that based on the direct_mask added to each channel entry */ | |
b481de9c | 2917 | scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK; |
3832ec9d | 2918 | scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id; |
b481de9c ZY |
2919 | scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; |
2920 | ||
2921 | /* flags + rate selection */ | |
2922 | ||
66b5004d | 2923 | if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) { |
b481de9c ZY |
2924 | scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK; |
2925 | scan->tx_cmd.rate = IWL_RATE_1M_PLCP; | |
2926 | scan->good_CRC_th = 0; | |
8318d78a | 2927 | band = IEEE80211_BAND_2GHZ; |
66b5004d | 2928 | } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) { |
b481de9c | 2929 | scan->tx_cmd.rate = IWL_RATE_6M_PLCP; |
b097ad29 JB |
2930 | /* |
2931 | * If active scaning is requested but a certain channel | |
2932 | * is marked passive, we can do active scanning if we | |
2933 | * detect transmissions. | |
2934 | */ | |
2935 | scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH : 0; | |
8318d78a | 2936 | band = IEEE80211_BAND_5GHZ; |
66b5004d | 2937 | } else { |
39aadf8c | 2938 | IWL_WARN(priv, "Invalid scan band count\n"); |
b481de9c ZY |
2939 | goto done; |
2940 | } | |
2941 | ||
77fecfb8 | 2942 | scan->tx_cmd.len = cpu_to_le16( |
1ecf9fc1 JB |
2943 | iwl_fill_probe_req(priv, |
2944 | (struct ieee80211_mgmt *)scan->data, | |
2945 | priv->scan_request->ie, | |
2946 | priv->scan_request->ie_len, | |
2947 | IWL_MAX_SCAN_SIZE - sizeof(*scan))); | |
77fecfb8 | 2948 | |
b481de9c ZY |
2949 | /* select Rx antennas */ |
2950 | scan->flags |= iwl3945_get_antenna_flags(priv); | |
2951 | ||
279b05d4 | 2952 | if (iwl_is_monitor_mode(priv)) |
b481de9c ZY |
2953 | scan->filter_flags = RXON_FILTER_PROMISC_MSK; |
2954 | ||
f9340520 | 2955 | scan->channel_count = |
1ecf9fc1 | 2956 | iwl3945_get_channels_for_scan(priv, band, is_active, n_probes, |
f9340520 | 2957 | (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]); |
b481de9c | 2958 | |
14b54336 | 2959 | if (scan->channel_count == 0) { |
e1623446 | 2960 | IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count); |
14b54336 RC |
2961 | goto done; |
2962 | } | |
2963 | ||
b481de9c | 2964 | cmd.len += le16_to_cpu(scan->tx_cmd.len) + |
bb8c093b | 2965 | scan->channel_count * sizeof(struct iwl3945_scan_channel); |
b481de9c ZY |
2966 | cmd.data = scan; |
2967 | scan->len = cpu_to_le16(cmd.len); | |
2968 | ||
2969 | set_bit(STATUS_SCAN_HW, &priv->status); | |
518099a8 | 2970 | rc = iwl_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
2971 | if (rc) |
2972 | goto done; | |
2973 | ||
2974 | queue_delayed_work(priv->workqueue, &priv->scan_check, | |
2975 | IWL_SCAN_CHECK_WATCHDOG); | |
2976 | ||
2977 | mutex_unlock(&priv->mutex); | |
2978 | return; | |
2979 | ||
2980 | done: | |
2420ebc1 MA |
2981 | /* can not perform scan make sure we clear scanning |
2982 | * bits from status so next scan request can be performed. | |
2983 | * if we dont clear scanning status bit here all next scan | |
2984 | * will fail | |
2985 | */ | |
2986 | clear_bit(STATUS_SCAN_HW, &priv->status); | |
2987 | clear_bit(STATUS_SCANNING, &priv->status); | |
2988 | ||
01ebd063 | 2989 | /* inform mac80211 scan aborted */ |
b481de9c ZY |
2990 | queue_work(priv->workqueue, &priv->scan_completed); |
2991 | mutex_unlock(&priv->mutex); | |
2992 | } | |
2993 | ||
bb8c093b | 2994 | static void iwl3945_bg_up(struct work_struct *data) |
b481de9c | 2995 | { |
4a8a4322 | 2996 | struct iwl_priv *priv = container_of(data, struct iwl_priv, up); |
b481de9c ZY |
2997 | |
2998 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2999 | return; | |
3000 | ||
3001 | mutex_lock(&priv->mutex); | |
bb8c093b | 3002 | __iwl3945_up(priv); |
b481de9c ZY |
3003 | mutex_unlock(&priv->mutex); |
3004 | } | |
3005 | ||
bb8c093b | 3006 | static void iwl3945_bg_restart(struct work_struct *data) |
b481de9c | 3007 | { |
4a8a4322 | 3008 | struct iwl_priv *priv = container_of(data, struct iwl_priv, restart); |
b481de9c ZY |
3009 | |
3010 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
3011 | return; | |
3012 | ||
19cc1087 JB |
3013 | if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) { |
3014 | mutex_lock(&priv->mutex); | |
3015 | priv->vif = NULL; | |
3016 | priv->is_open = 0; | |
3017 | mutex_unlock(&priv->mutex); | |
3018 | iwl3945_down(priv); | |
3019 | ieee80211_restart_hw(priv->hw); | |
3020 | } else { | |
3021 | iwl3945_down(priv); | |
3022 | queue_work(priv->workqueue, &priv->up); | |
3023 | } | |
b481de9c ZY |
3024 | } |
3025 | ||
bb8c093b | 3026 | static void iwl3945_bg_rx_replenish(struct work_struct *data) |
b481de9c | 3027 | { |
4a8a4322 AK |
3028 | struct iwl_priv *priv = |
3029 | container_of(data, struct iwl_priv, rx_replenish); | |
b481de9c ZY |
3030 | |
3031 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
3032 | return; | |
3033 | ||
3034 | mutex_lock(&priv->mutex); | |
bb8c093b | 3035 | iwl3945_rx_replenish(priv); |
b481de9c ZY |
3036 | mutex_unlock(&priv->mutex); |
3037 | } | |
3038 | ||
7878a5a4 MA |
3039 | #define IWL_DELAY_NEXT_SCAN (HZ*2) |
3040 | ||
5bbe233b | 3041 | void iwl3945_post_associate(struct iwl_priv *priv) |
b481de9c | 3042 | { |
b481de9c ZY |
3043 | int rc = 0; |
3044 | struct ieee80211_conf *conf = NULL; | |
3045 | ||
05c914fe | 3046 | if (priv->iw_mode == NL80211_IFTYPE_AP) { |
15b1687c | 3047 | IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__); |
b481de9c ZY |
3048 | return; |
3049 | } | |
3050 | ||
3051 | ||
e1623446 | 3052 | IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n", |
8ccde88a | 3053 | priv->assoc_id, priv->active_rxon.bssid_addr); |
b481de9c ZY |
3054 | |
3055 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
3056 | return; | |
3057 | ||
322a9811 | 3058 | if (!priv->vif || !priv->is_open) |
6ef89d0a | 3059 | return; |
322a9811 | 3060 | |
af0053d6 | 3061 | iwl_scan_cancel_timeout(priv, 200); |
15e869d8 | 3062 | |
b481de9c ZY |
3063 | conf = ieee80211_get_hw_conf(priv->hw); |
3064 | ||
8ccde88a | 3065 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
e0158e61 | 3066 | iwlcore_commit_rxon(priv); |
b481de9c | 3067 | |
28afaf91 | 3068 | memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd)); |
bb8c093b | 3069 | iwl3945_setup_rxon_timing(priv); |
518099a8 | 3070 | rc = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
b481de9c ZY |
3071 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
3072 | if (rc) | |
39aadf8c | 3073 | IWL_WARN(priv, "REPLY_RXON_TIMING failed - " |
b481de9c ZY |
3074 | "Attempting to continue.\n"); |
3075 | ||
8ccde88a | 3076 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; |
b481de9c | 3077 | |
8ccde88a | 3078 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); |
b481de9c | 3079 | |
e1623446 | 3080 | IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n", |
b481de9c ZY |
3081 | priv->assoc_id, priv->beacon_int); |
3082 | ||
3083 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) | |
8ccde88a | 3084 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; |
b481de9c | 3085 | else |
8ccde88a | 3086 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; |
b481de9c | 3087 | |
8ccde88a | 3088 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { |
b481de9c | 3089 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME) |
8ccde88a | 3090 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; |
b481de9c | 3091 | else |
8ccde88a | 3092 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
b481de9c | 3093 | |
05c914fe | 3094 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
8ccde88a | 3095 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
b481de9c ZY |
3096 | |
3097 | } | |
3098 | ||
e0158e61 | 3099 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
3100 | |
3101 | switch (priv->iw_mode) { | |
05c914fe | 3102 | case NL80211_IFTYPE_STATION: |
bb8c093b | 3103 | iwl3945_rate_scale_init(priv->hw, IWL_AP_ID); |
b481de9c ZY |
3104 | break; |
3105 | ||
05c914fe | 3106 | case NL80211_IFTYPE_ADHOC: |
b481de9c | 3107 | |
ce546fd2 | 3108 | priv->assoc_id = 1; |
c587de0b | 3109 | iwl_add_station(priv, priv->bssid, 0, CMD_SYNC, NULL); |
b481de9c | 3110 | iwl3945_sync_sta(priv, IWL_STA_ID, |
8318d78a | 3111 | (priv->band == IEEE80211_BAND_5GHZ) ? |
b481de9c ZY |
3112 | IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP, |
3113 | CMD_ASYNC); | |
bb8c093b CH |
3114 | iwl3945_rate_scale_init(priv->hw, IWL_STA_ID); |
3115 | iwl3945_send_beacon_cmd(priv); | |
b481de9c ZY |
3116 | |
3117 | break; | |
3118 | ||
3119 | default: | |
15b1687c | 3120 | IWL_ERR(priv, "%s Should not be called in %d mode\n", |
3ac7f146 | 3121 | __func__, priv->iw_mode); |
b481de9c ZY |
3122 | break; |
3123 | } | |
3124 | ||
14d2aac5 | 3125 | iwl_activate_qos(priv, 0); |
292ae174 | 3126 | |
7878a5a4 MA |
3127 | /* we have just associated, don't start scan too early */ |
3128 | priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN; | |
cd56d331 AK |
3129 | } |
3130 | ||
b481de9c ZY |
3131 | /***************************************************************************** |
3132 | * | |
3133 | * mac80211 entry point functions | |
3134 | * | |
3135 | *****************************************************************************/ | |
3136 | ||
5a66926a ZY |
3137 | #define UCODE_READY_TIMEOUT (2 * HZ) |
3138 | ||
bb8c093b | 3139 | static int iwl3945_mac_start(struct ieee80211_hw *hw) |
b481de9c | 3140 | { |
4a8a4322 | 3141 | struct iwl_priv *priv = hw->priv; |
5a66926a | 3142 | int ret; |
b481de9c | 3143 | |
e1623446 | 3144 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c ZY |
3145 | |
3146 | /* we should be verifying the device is ready to be opened */ | |
3147 | mutex_lock(&priv->mutex); | |
3148 | ||
5a66926a ZY |
3149 | /* fetch ucode file from disk, alloc and copy to bus-master buffers ... |
3150 | * ucode filename and max sizes are card-specific. */ | |
3151 | ||
3152 | if (!priv->ucode_code.len) { | |
3153 | ret = iwl3945_read_ucode(priv); | |
3154 | if (ret) { | |
15b1687c | 3155 | IWL_ERR(priv, "Could not read microcode: %d\n", ret); |
5a66926a ZY |
3156 | mutex_unlock(&priv->mutex); |
3157 | goto out_release_irq; | |
3158 | } | |
3159 | } | |
b481de9c | 3160 | |
e655b9f0 | 3161 | ret = __iwl3945_up(priv); |
b481de9c ZY |
3162 | |
3163 | mutex_unlock(&priv->mutex); | |
5a66926a | 3164 | |
e655b9f0 ZY |
3165 | if (ret) |
3166 | goto out_release_irq; | |
3167 | ||
e1623446 | 3168 | IWL_DEBUG_INFO(priv, "Start UP work.\n"); |
e655b9f0 | 3169 | |
5a66926a ZY |
3170 | /* Wait for START_ALIVE from ucode. Otherwise callbacks from |
3171 | * mac80211 will not be run successfully. */ | |
3172 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, | |
3173 | test_bit(STATUS_READY, &priv->status), | |
3174 | UCODE_READY_TIMEOUT); | |
3175 | if (!ret) { | |
3176 | if (!test_bit(STATUS_READY, &priv->status)) { | |
15b1687c WT |
3177 | IWL_ERR(priv, |
3178 | "Wait for START_ALIVE timeout after %dms.\n", | |
3179 | jiffies_to_msecs(UCODE_READY_TIMEOUT)); | |
5a66926a ZY |
3180 | ret = -ETIMEDOUT; |
3181 | goto out_release_irq; | |
3182 | } | |
3183 | } | |
3184 | ||
2663516d HS |
3185 | /* ucode is running and will send rfkill notifications, |
3186 | * no need to poll the killswitch state anymore */ | |
3187 | cancel_delayed_work(&priv->rfkill_poll); | |
3188 | ||
e655b9f0 | 3189 | priv->is_open = 1; |
e1623446 | 3190 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c | 3191 | return 0; |
5a66926a ZY |
3192 | |
3193 | out_release_irq: | |
e655b9f0 | 3194 | priv->is_open = 0; |
e1623446 | 3195 | IWL_DEBUG_MAC80211(priv, "leave - failed\n"); |
5a66926a | 3196 | return ret; |
b481de9c ZY |
3197 | } |
3198 | ||
bb8c093b | 3199 | static void iwl3945_mac_stop(struct ieee80211_hw *hw) |
b481de9c | 3200 | { |
4a8a4322 | 3201 | struct iwl_priv *priv = hw->priv; |
b481de9c | 3202 | |
e1623446 | 3203 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
6ef89d0a | 3204 | |
e655b9f0 | 3205 | if (!priv->is_open) { |
e1623446 | 3206 | IWL_DEBUG_MAC80211(priv, "leave - skip\n"); |
e655b9f0 ZY |
3207 | return; |
3208 | } | |
3209 | ||
b481de9c | 3210 | priv->is_open = 0; |
5a66926a | 3211 | |
775a6e27 | 3212 | if (iwl_is_ready_rf(priv)) { |
e655b9f0 ZY |
3213 | /* stop mac, cancel any scan request and clear |
3214 | * RXON_FILTER_ASSOC_MSK BIT | |
3215 | */ | |
5a66926a | 3216 | mutex_lock(&priv->mutex); |
af0053d6 | 3217 | iwl_scan_cancel_timeout(priv, 100); |
fde3571f | 3218 | mutex_unlock(&priv->mutex); |
fde3571f MA |
3219 | } |
3220 | ||
5a66926a ZY |
3221 | iwl3945_down(priv); |
3222 | ||
3223 | flush_workqueue(priv->workqueue); | |
2663516d HS |
3224 | |
3225 | /* start polling the killswitch state again */ | |
3226 | queue_delayed_work(priv->workqueue, &priv->rfkill_poll, | |
3227 | round_jiffies_relative(2 * HZ)); | |
6ef89d0a | 3228 | |
e1623446 | 3229 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c ZY |
3230 | } |
3231 | ||
e039fa4a | 3232 | static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) |
b481de9c | 3233 | { |
4a8a4322 | 3234 | struct iwl_priv *priv = hw->priv; |
b481de9c | 3235 | |
e1623446 | 3236 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c | 3237 | |
e1623446 | 3238 | IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, |
e039fa4a | 3239 | ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate); |
b481de9c | 3240 | |
e039fa4a | 3241 | if (iwl3945_tx_skb(priv, skb)) |
b481de9c ZY |
3242 | dev_kfree_skb_any(skb); |
3243 | ||
e1623446 | 3244 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
637f8837 | 3245 | return NETDEV_TX_OK; |
b481de9c ZY |
3246 | } |
3247 | ||
60690a6a | 3248 | void iwl3945_config_ap(struct iwl_priv *priv) |
b481de9c ZY |
3249 | { |
3250 | int rc = 0; | |
3251 | ||
d986bcd1 | 3252 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
b481de9c ZY |
3253 | return; |
3254 | ||
3255 | /* The following should be done only at AP bring up */ | |
8ccde88a | 3256 | if (!(iwl_is_associated(priv))) { |
b481de9c ZY |
3257 | |
3258 | /* RXON - unassoc (to set timing command) */ | |
8ccde88a | 3259 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
e0158e61 | 3260 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
3261 | |
3262 | /* RXON Timing */ | |
28afaf91 | 3263 | memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd)); |
bb8c093b | 3264 | iwl3945_setup_rxon_timing(priv); |
518099a8 SO |
3265 | rc = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
3266 | sizeof(priv->rxon_timing), | |
3267 | &priv->rxon_timing); | |
b481de9c | 3268 | if (rc) |
39aadf8c | 3269 | IWL_WARN(priv, "REPLY_RXON_TIMING failed - " |
b481de9c ZY |
3270 | "Attempting to continue.\n"); |
3271 | ||
3272 | /* FIXME: what should be the assoc_id for AP? */ | |
8ccde88a | 3273 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); |
b481de9c | 3274 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) |
8ccde88a | 3275 | priv->staging_rxon.flags |= |
b481de9c ZY |
3276 | RXON_FLG_SHORT_PREAMBLE_MSK; |
3277 | else | |
8ccde88a | 3278 | priv->staging_rxon.flags &= |
b481de9c ZY |
3279 | ~RXON_FLG_SHORT_PREAMBLE_MSK; |
3280 | ||
8ccde88a | 3281 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { |
b481de9c ZY |
3282 | if (priv->assoc_capability & |
3283 | WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
8ccde88a | 3284 | priv->staging_rxon.flags |= |
b481de9c ZY |
3285 | RXON_FLG_SHORT_SLOT_MSK; |
3286 | else | |
8ccde88a | 3287 | priv->staging_rxon.flags &= |
b481de9c ZY |
3288 | ~RXON_FLG_SHORT_SLOT_MSK; |
3289 | ||
05c914fe | 3290 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
8ccde88a | 3291 | priv->staging_rxon.flags &= |
b481de9c ZY |
3292 | ~RXON_FLG_SHORT_SLOT_MSK; |
3293 | } | |
3294 | /* restore RXON assoc */ | |
8ccde88a | 3295 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; |
e0158e61 | 3296 | iwlcore_commit_rxon(priv); |
c587de0b | 3297 | iwl_add_station(priv, iwl_bcast_addr, 0, CMD_SYNC, NULL); |
556f8db7 | 3298 | } |
bb8c093b | 3299 | iwl3945_send_beacon_cmd(priv); |
b481de9c ZY |
3300 | |
3301 | /* FIXME - we need to add code here to detect a totally new | |
3302 | * configuration, reset the AP, unassoc, rxon timing, assoc, | |
3303 | * clear sta table, add BCAST sta... */ | |
3304 | } | |
3305 | ||
bb8c093b | 3306 | static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
dc822b5d JB |
3307 | struct ieee80211_vif *vif, |
3308 | struct ieee80211_sta *sta, | |
3309 | struct ieee80211_key_conf *key) | |
b481de9c | 3310 | { |
4a8a4322 | 3311 | struct iwl_priv *priv = hw->priv; |
dc822b5d | 3312 | const u8 *addr; |
6e21f15c AK |
3313 | int ret = 0; |
3314 | u8 sta_id = IWL_INVALID_STATION; | |
3315 | u8 static_key; | |
b481de9c | 3316 | |
e1623446 | 3317 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c | 3318 | |
df878d8f | 3319 | if (iwl3945_mod_params.sw_crypto) { |
e1623446 | 3320 | IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n"); |
b481de9c ZY |
3321 | return -EOPNOTSUPP; |
3322 | } | |
3323 | ||
42986796 | 3324 | addr = sta ? sta->addr : iwl_bcast_addr; |
6e21f15c AK |
3325 | static_key = !iwl_is_associated(priv); |
3326 | ||
3327 | if (!static_key) { | |
c587de0b | 3328 | sta_id = iwl_find_station(priv, addr); |
6e21f15c | 3329 | if (sta_id == IWL_INVALID_STATION) { |
12514396 | 3330 | IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n", |
6e21f15c AK |
3331 | addr); |
3332 | return -EINVAL; | |
3333 | } | |
b481de9c ZY |
3334 | } |
3335 | ||
3336 | mutex_lock(&priv->mutex); | |
af0053d6 | 3337 | iwl_scan_cancel_timeout(priv, 100); |
6e21f15c | 3338 | mutex_unlock(&priv->mutex); |
15e869d8 | 3339 | |
b481de9c | 3340 | switch (cmd) { |
6e21f15c AK |
3341 | case SET_KEY: |
3342 | if (static_key) | |
3343 | ret = iwl3945_set_static_key(priv, key); | |
3344 | else | |
3345 | ret = iwl3945_set_dynamic_key(priv, key, sta_id); | |
3346 | IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n"); | |
b481de9c ZY |
3347 | break; |
3348 | case DISABLE_KEY: | |
6e21f15c AK |
3349 | if (static_key) |
3350 | ret = iwl3945_remove_static_key(priv); | |
3351 | else | |
3352 | ret = iwl3945_clear_sta_key_info(priv, sta_id); | |
3353 | IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n"); | |
b481de9c ZY |
3354 | break; |
3355 | default: | |
42986796 | 3356 | ret = -EINVAL; |
b481de9c ZY |
3357 | } |
3358 | ||
e1623446 | 3359 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c | 3360 | |
42986796 | 3361 | return ret; |
b481de9c ZY |
3362 | } |
3363 | ||
b481de9c ZY |
3364 | /***************************************************************************** |
3365 | * | |
3366 | * sysfs attributes | |
3367 | * | |
3368 | *****************************************************************************/ | |
3369 | ||
d08853a3 | 3370 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
3371 | |
3372 | /* | |
3373 | * The following adds a new attribute to the sysfs representation | |
3374 | * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/) | |
3375 | * used for controlling the debug level. | |
3376 | * | |
3377 | * See the level definitions in iwl for details. | |
3378 | */ | |
40b8ec0b SO |
3379 | static ssize_t show_debug_level(struct device *d, |
3380 | struct device_attribute *attr, char *buf) | |
b481de9c | 3381 | { |
928841b1 | 3382 | struct iwl_priv *priv = dev_get_drvdata(d); |
40b8ec0b SO |
3383 | |
3384 | return sprintf(buf, "0x%08X\n", priv->debug_level); | |
b481de9c | 3385 | } |
40b8ec0b SO |
3386 | static ssize_t store_debug_level(struct device *d, |
3387 | struct device_attribute *attr, | |
b481de9c ZY |
3388 | const char *buf, size_t count) |
3389 | { | |
928841b1 | 3390 | struct iwl_priv *priv = dev_get_drvdata(d); |
40b8ec0b SO |
3391 | unsigned long val; |
3392 | int ret; | |
b481de9c | 3393 | |
40b8ec0b SO |
3394 | ret = strict_strtoul(buf, 0, &val); |
3395 | if (ret) | |
978785a3 | 3396 | IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf); |
b481de9c | 3397 | else |
40b8ec0b | 3398 | priv->debug_level = val; |
b481de9c ZY |
3399 | |
3400 | return strnlen(buf, count); | |
3401 | } | |
3402 | ||
40b8ec0b SO |
3403 | static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, |
3404 | show_debug_level, store_debug_level); | |
b481de9c | 3405 | |
d08853a3 | 3406 | #endif /* CONFIG_IWLWIFI_DEBUG */ |
b481de9c | 3407 | |
b481de9c ZY |
3408 | static ssize_t show_temperature(struct device *d, |
3409 | struct device_attribute *attr, char *buf) | |
3410 | { | |
928841b1 | 3411 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 3412 | |
775a6e27 | 3413 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
3414 | return -EAGAIN; |
3415 | ||
bb8c093b | 3416 | return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv)); |
b481de9c ZY |
3417 | } |
3418 | ||
3419 | static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL); | |
3420 | ||
b481de9c ZY |
3421 | static ssize_t show_tx_power(struct device *d, |
3422 | struct device_attribute *attr, char *buf) | |
3423 | { | |
928841b1 | 3424 | struct iwl_priv *priv = dev_get_drvdata(d); |
62ea9c5b | 3425 | return sprintf(buf, "%d\n", priv->tx_power_user_lmt); |
b481de9c ZY |
3426 | } |
3427 | ||
3428 | static ssize_t store_tx_power(struct device *d, | |
3429 | struct device_attribute *attr, | |
3430 | const char *buf, size_t count) | |
3431 | { | |
928841b1 | 3432 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3433 | char *p = (char *)buf; |
3434 | u32 val; | |
3435 | ||
3436 | val = simple_strtoul(p, &p, 10); | |
3437 | if (p == buf) | |
978785a3 | 3438 | IWL_INFO(priv, ": %s is not in decimal form.\n", buf); |
b481de9c | 3439 | else |
bb8c093b | 3440 | iwl3945_hw_reg_set_txpower(priv, val); |
b481de9c ZY |
3441 | |
3442 | return count; | |
3443 | } | |
3444 | ||
3445 | static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power); | |
3446 | ||
3447 | static ssize_t show_flags(struct device *d, | |
3448 | struct device_attribute *attr, char *buf) | |
3449 | { | |
928841b1 | 3450 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 3451 | |
8ccde88a | 3452 | return sprintf(buf, "0x%04X\n", priv->active_rxon.flags); |
b481de9c ZY |
3453 | } |
3454 | ||
3455 | static ssize_t store_flags(struct device *d, | |
3456 | struct device_attribute *attr, | |
3457 | const char *buf, size_t count) | |
3458 | { | |
928841b1 | 3459 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3460 | u32 flags = simple_strtoul(buf, NULL, 0); |
3461 | ||
3462 | mutex_lock(&priv->mutex); | |
8ccde88a | 3463 | if (le32_to_cpu(priv->staging_rxon.flags) != flags) { |
b481de9c | 3464 | /* Cancel any currently running scans... */ |
af0053d6 | 3465 | if (iwl_scan_cancel_timeout(priv, 100)) |
39aadf8c | 3466 | IWL_WARN(priv, "Could not cancel scan.\n"); |
b481de9c | 3467 | else { |
e1623446 | 3468 | IWL_DEBUG_INFO(priv, "Committing rxon.flags = 0x%04X\n", |
b481de9c | 3469 | flags); |
8ccde88a | 3470 | priv->staging_rxon.flags = cpu_to_le32(flags); |
e0158e61 | 3471 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
3472 | } |
3473 | } | |
3474 | mutex_unlock(&priv->mutex); | |
3475 | ||
3476 | return count; | |
3477 | } | |
3478 | ||
3479 | static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags); | |
3480 | ||
3481 | static ssize_t show_filter_flags(struct device *d, | |
3482 | struct device_attribute *attr, char *buf) | |
3483 | { | |
928841b1 | 3484 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3485 | |
3486 | return sprintf(buf, "0x%04X\n", | |
8ccde88a | 3487 | le32_to_cpu(priv->active_rxon.filter_flags)); |
b481de9c ZY |
3488 | } |
3489 | ||
3490 | static ssize_t store_filter_flags(struct device *d, | |
3491 | struct device_attribute *attr, | |
3492 | const char *buf, size_t count) | |
3493 | { | |
928841b1 | 3494 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3495 | u32 filter_flags = simple_strtoul(buf, NULL, 0); |
3496 | ||
3497 | mutex_lock(&priv->mutex); | |
8ccde88a | 3498 | if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) { |
b481de9c | 3499 | /* Cancel any currently running scans... */ |
af0053d6 | 3500 | if (iwl_scan_cancel_timeout(priv, 100)) |
39aadf8c | 3501 | IWL_WARN(priv, "Could not cancel scan.\n"); |
b481de9c | 3502 | else { |
e1623446 | 3503 | IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = " |
b481de9c | 3504 | "0x%04X\n", filter_flags); |
8ccde88a | 3505 | priv->staging_rxon.filter_flags = |
b481de9c | 3506 | cpu_to_le32(filter_flags); |
e0158e61 | 3507 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
3508 | } |
3509 | } | |
3510 | mutex_unlock(&priv->mutex); | |
3511 | ||
3512 | return count; | |
3513 | } | |
3514 | ||
3515 | static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags, | |
3516 | store_filter_flags); | |
3517 | ||
c8b0e6e1 | 3518 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
3519 | |
3520 | static ssize_t show_measurement(struct device *d, | |
3521 | struct device_attribute *attr, char *buf) | |
3522 | { | |
4a8a4322 | 3523 | struct iwl_priv *priv = dev_get_drvdata(d); |
600c0e11 | 3524 | struct iwl_spectrum_notification measure_report; |
b481de9c | 3525 | u32 size = sizeof(measure_report), len = 0, ofs = 0; |
3ac7f146 | 3526 | u8 *data = (u8 *)&measure_report; |
b481de9c ZY |
3527 | unsigned long flags; |
3528 | ||
3529 | spin_lock_irqsave(&priv->lock, flags); | |
3530 | if (!(priv->measurement_status & MEASUREMENT_READY)) { | |
3531 | spin_unlock_irqrestore(&priv->lock, flags); | |
3532 | return 0; | |
3533 | } | |
3534 | memcpy(&measure_report, &priv->measure_report, size); | |
3535 | priv->measurement_status = 0; | |
3536 | spin_unlock_irqrestore(&priv->lock, flags); | |
3537 | ||
3538 | while (size && (PAGE_SIZE - len)) { | |
3539 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
3540 | PAGE_SIZE - len, 1); | |
3541 | len = strlen(buf); | |
3542 | if (PAGE_SIZE - len) | |
3543 | buf[len++] = '\n'; | |
3544 | ||
3545 | ofs += 16; | |
3546 | size -= min(size, 16U); | |
3547 | } | |
3548 | ||
3549 | return len; | |
3550 | } | |
3551 | ||
3552 | static ssize_t store_measurement(struct device *d, | |
3553 | struct device_attribute *attr, | |
3554 | const char *buf, size_t count) | |
3555 | { | |
4a8a4322 | 3556 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 3557 | struct ieee80211_measurement_params params = { |
8ccde88a | 3558 | .channel = le16_to_cpu(priv->active_rxon.channel), |
b481de9c ZY |
3559 | .start_time = cpu_to_le64(priv->last_tsf), |
3560 | .duration = cpu_to_le16(1), | |
3561 | }; | |
3562 | u8 type = IWL_MEASURE_BASIC; | |
3563 | u8 buffer[32]; | |
3564 | u8 channel; | |
3565 | ||
3566 | if (count) { | |
3567 | char *p = buffer; | |
3568 | strncpy(buffer, buf, min(sizeof(buffer), count)); | |
3569 | channel = simple_strtoul(p, NULL, 0); | |
3570 | if (channel) | |
3571 | params.channel = channel; | |
3572 | ||
3573 | p = buffer; | |
3574 | while (*p && *p != ' ') | |
3575 | p++; | |
3576 | if (*p) | |
3577 | type = simple_strtoul(p + 1, NULL, 0); | |
3578 | } | |
3579 | ||
e1623446 | 3580 | IWL_DEBUG_INFO(priv, "Invoking measurement of type %d on " |
b481de9c | 3581 | "channel %d (for '%s')\n", type, params.channel, buf); |
bb8c093b | 3582 | iwl3945_get_measurement(priv, ¶ms, type); |
b481de9c ZY |
3583 | |
3584 | return count; | |
3585 | } | |
3586 | ||
3587 | static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR, | |
3588 | show_measurement, store_measurement); | |
c8b0e6e1 | 3589 | #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */ |
b481de9c | 3590 | |
b481de9c ZY |
3591 | static ssize_t store_retry_rate(struct device *d, |
3592 | struct device_attribute *attr, | |
3593 | const char *buf, size_t count) | |
3594 | { | |
4a8a4322 | 3595 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3596 | |
3597 | priv->retry_rate = simple_strtoul(buf, NULL, 0); | |
3598 | if (priv->retry_rate <= 0) | |
3599 | priv->retry_rate = 1; | |
3600 | ||
3601 | return count; | |
3602 | } | |
3603 | ||
3604 | static ssize_t show_retry_rate(struct device *d, | |
3605 | struct device_attribute *attr, char *buf) | |
3606 | { | |
4a8a4322 | 3607 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3608 | return sprintf(buf, "%d", priv->retry_rate); |
3609 | } | |
3610 | ||
3611 | static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate, | |
3612 | store_retry_rate); | |
3613 | ||
d25aabb0 | 3614 | |
b481de9c ZY |
3615 | static ssize_t store_power_level(struct device *d, |
3616 | struct device_attribute *attr, | |
3617 | const char *buf, size_t count) | |
3618 | { | |
4a8a4322 | 3619 | struct iwl_priv *priv = dev_get_drvdata(d); |
d25aabb0 WT |
3620 | int ret; |
3621 | unsigned long mode; | |
3622 | ||
b481de9c | 3623 | |
b481de9c ZY |
3624 | mutex_lock(&priv->mutex); |
3625 | ||
d25aabb0 WT |
3626 | ret = strict_strtoul(buf, 10, &mode); |
3627 | if (ret) | |
3628 | goto out; | |
b481de9c | 3629 | |
d25aabb0 WT |
3630 | ret = iwl_power_set_user_mode(priv, mode); |
3631 | if (ret) { | |
3632 | IWL_DEBUG_MAC80211(priv, "failed setting power mode.\n"); | |
3633 | goto out; | |
b481de9c | 3634 | } |
d25aabb0 | 3635 | ret = count; |
b481de9c ZY |
3636 | |
3637 | out: | |
3638 | mutex_unlock(&priv->mutex); | |
d25aabb0 | 3639 | return ret; |
b481de9c ZY |
3640 | } |
3641 | ||
d25aabb0 WT |
3642 | static ssize_t show_power_level(struct device *d, |
3643 | struct device_attribute *attr, char *buf) | |
3644 | { | |
3645 | struct iwl_priv *priv = dev_get_drvdata(d); | |
3646 | int mode = priv->power_data.user_power_setting; | |
d25aabb0 WT |
3647 | int level = priv->power_data.power_mode; |
3648 | char *p = buf; | |
3649 | ||
7af2c460 JB |
3650 | p += sprintf(p, "INDEX:%d\t", level); |
3651 | p += sprintf(p, "USER:%d\n", mode); | |
d25aabb0 WT |
3652 | return p - buf + 1; |
3653 | } | |
3654 | ||
3655 | static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, | |
3656 | show_power_level, store_power_level); | |
3657 | ||
b481de9c ZY |
3658 | #define MAX_WX_STRING 80 |
3659 | ||
3660 | /* Values are in microsecond */ | |
3661 | static const s32 timeout_duration[] = { | |
3662 | 350000, | |
3663 | 250000, | |
3664 | 75000, | |
3665 | 37000, | |
3666 | 25000, | |
3667 | }; | |
3668 | static const s32 period_duration[] = { | |
3669 | 400000, | |
3670 | 700000, | |
3671 | 1000000, | |
3672 | 1000000, | |
3673 | 1000000 | |
3674 | }; | |
3675 | ||
b481de9c ZY |
3676 | static ssize_t show_channels(struct device *d, |
3677 | struct device_attribute *attr, char *buf) | |
3678 | { | |
8318d78a JB |
3679 | /* all this shit doesn't belong into sysfs anyway */ |
3680 | return 0; | |
b481de9c ZY |
3681 | } |
3682 | ||
3683 | static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL); | |
3684 | ||
3685 | static ssize_t show_statistics(struct device *d, | |
3686 | struct device_attribute *attr, char *buf) | |
3687 | { | |
4a8a4322 | 3688 | struct iwl_priv *priv = dev_get_drvdata(d); |
bb8c093b | 3689 | u32 size = sizeof(struct iwl3945_notif_statistics); |
b481de9c | 3690 | u32 len = 0, ofs = 0; |
f2c7e521 | 3691 | u8 *data = (u8 *)&priv->statistics_39; |
b481de9c ZY |
3692 | int rc = 0; |
3693 | ||
775a6e27 | 3694 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
3695 | return -EAGAIN; |
3696 | ||
3697 | mutex_lock(&priv->mutex); | |
17f841cd | 3698 | rc = iwl_send_statistics_request(priv, 0); |
b481de9c ZY |
3699 | mutex_unlock(&priv->mutex); |
3700 | ||
3701 | if (rc) { | |
3702 | len = sprintf(buf, | |
3703 | "Error sending statistics request: 0x%08X\n", rc); | |
3704 | return len; | |
3705 | } | |
3706 | ||
3707 | while (size && (PAGE_SIZE - len)) { | |
3708 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
3709 | PAGE_SIZE - len, 1); | |
3710 | len = strlen(buf); | |
3711 | if (PAGE_SIZE - len) | |
3712 | buf[len++] = '\n'; | |
3713 | ||
3714 | ofs += 16; | |
3715 | size -= min(size, 16U); | |
3716 | } | |
3717 | ||
3718 | return len; | |
3719 | } | |
3720 | ||
3721 | static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL); | |
3722 | ||
3723 | static ssize_t show_antenna(struct device *d, | |
3724 | struct device_attribute *attr, char *buf) | |
3725 | { | |
4a8a4322 | 3726 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 3727 | |
775a6e27 | 3728 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
3729 | return -EAGAIN; |
3730 | ||
7e4bca5e | 3731 | return sprintf(buf, "%d\n", iwl3945_mod_params.antenna); |
b481de9c ZY |
3732 | } |
3733 | ||
3734 | static ssize_t store_antenna(struct device *d, | |
3735 | struct device_attribute *attr, | |
3736 | const char *buf, size_t count) | |
3737 | { | |
7530f85f | 3738 | struct iwl_priv *priv __maybe_unused = dev_get_drvdata(d); |
b481de9c | 3739 | int ant; |
b481de9c ZY |
3740 | |
3741 | if (count == 0) | |
3742 | return 0; | |
3743 | ||
3744 | if (sscanf(buf, "%1i", &ant) != 1) { | |
e1623446 | 3745 | IWL_DEBUG_INFO(priv, "not in hex or decimal form.\n"); |
b481de9c ZY |
3746 | return count; |
3747 | } | |
3748 | ||
3749 | if ((ant >= 0) && (ant <= 2)) { | |
e1623446 | 3750 | IWL_DEBUG_INFO(priv, "Setting antenna select to %d.\n", ant); |
7e4bca5e | 3751 | iwl3945_mod_params.antenna = (enum iwl3945_antenna)ant; |
b481de9c | 3752 | } else |
e1623446 | 3753 | IWL_DEBUG_INFO(priv, "Bad antenna select value %d.\n", ant); |
b481de9c ZY |
3754 | |
3755 | ||
3756 | return count; | |
3757 | } | |
3758 | ||
3759 | static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna); | |
3760 | ||
3761 | static ssize_t show_status(struct device *d, | |
3762 | struct device_attribute *attr, char *buf) | |
3763 | { | |
928841b1 | 3764 | struct iwl_priv *priv = dev_get_drvdata(d); |
775a6e27 | 3765 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
3766 | return -EAGAIN; |
3767 | return sprintf(buf, "0x%08x\n", (int)priv->status); | |
3768 | } | |
3769 | ||
3770 | static DEVICE_ATTR(status, S_IRUGO, show_status, NULL); | |
3771 | ||
3772 | static ssize_t dump_error_log(struct device *d, | |
3773 | struct device_attribute *attr, | |
3774 | const char *buf, size_t count) | |
3775 | { | |
928841b1 | 3776 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3777 | char *p = (char *)buf; |
3778 | ||
3779 | if (p[0] == '1') | |
928841b1 | 3780 | iwl3945_dump_nic_error_log(priv); |
b481de9c ZY |
3781 | |
3782 | return strnlen(buf, count); | |
3783 | } | |
3784 | ||
3785 | static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log); | |
3786 | ||
3787 | static ssize_t dump_event_log(struct device *d, | |
3788 | struct device_attribute *attr, | |
3789 | const char *buf, size_t count) | |
3790 | { | |
928841b1 | 3791 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3792 | char *p = (char *)buf; |
3793 | ||
3794 | if (p[0] == '1') | |
928841b1 | 3795 | iwl3945_dump_nic_event_log(priv); |
b481de9c ZY |
3796 | |
3797 | return strnlen(buf, count); | |
3798 | } | |
3799 | ||
3800 | static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log); | |
3801 | ||
3802 | /***************************************************************************** | |
3803 | * | |
a96a27f9 | 3804 | * driver setup and tear down |
b481de9c ZY |
3805 | * |
3806 | *****************************************************************************/ | |
3807 | ||
4a8a4322 | 3808 | static void iwl3945_setup_deferred_work(struct iwl_priv *priv) |
b481de9c | 3809 | { |
d21050c7 | 3810 | priv->workqueue = create_singlethread_workqueue(DRV_NAME); |
b481de9c ZY |
3811 | |
3812 | init_waitqueue_head(&priv->wait_command_queue); | |
3813 | ||
bb8c093b CH |
3814 | INIT_WORK(&priv->up, iwl3945_bg_up); |
3815 | INIT_WORK(&priv->restart, iwl3945_bg_restart); | |
3816 | INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish); | |
bb8c093b | 3817 | INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update); |
bb8c093b CH |
3818 | INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start); |
3819 | INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start); | |
2663516d | 3820 | INIT_DELAYED_WORK(&priv->rfkill_poll, iwl3945_rfkill_poll); |
77fecfb8 SO |
3821 | INIT_WORK(&priv->scan_completed, iwl_bg_scan_completed); |
3822 | INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan); | |
3823 | INIT_WORK(&priv->abort_scan, iwl_bg_abort_scan); | |
3824 | INIT_DELAYED_WORK(&priv->scan_check, iwl_bg_scan_check); | |
bb8c093b CH |
3825 | |
3826 | iwl3945_hw_setup_deferred_work(priv); | |
b481de9c ZY |
3827 | |
3828 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | |
bb8c093b | 3829 | iwl3945_irq_tasklet, (unsigned long)priv); |
b481de9c ZY |
3830 | } |
3831 | ||
4a8a4322 | 3832 | static void iwl3945_cancel_deferred_work(struct iwl_priv *priv) |
b481de9c | 3833 | { |
bb8c093b | 3834 | iwl3945_hw_cancel_deferred_work(priv); |
b481de9c | 3835 | |
e47eb6ad | 3836 | cancel_delayed_work_sync(&priv->init_alive_start); |
b481de9c ZY |
3837 | cancel_delayed_work(&priv->scan_check); |
3838 | cancel_delayed_work(&priv->alive_start); | |
b481de9c ZY |
3839 | cancel_work_sync(&priv->beacon_update); |
3840 | } | |
3841 | ||
bb8c093b | 3842 | static struct attribute *iwl3945_sysfs_entries[] = { |
b481de9c ZY |
3843 | &dev_attr_antenna.attr, |
3844 | &dev_attr_channels.attr, | |
3845 | &dev_attr_dump_errors.attr, | |
3846 | &dev_attr_dump_events.attr, | |
3847 | &dev_attr_flags.attr, | |
3848 | &dev_attr_filter_flags.attr, | |
c8b0e6e1 | 3849 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
3850 | &dev_attr_measurement.attr, |
3851 | #endif | |
3852 | &dev_attr_power_level.attr, | |
b481de9c | 3853 | &dev_attr_retry_rate.attr, |
b481de9c ZY |
3854 | &dev_attr_statistics.attr, |
3855 | &dev_attr_status.attr, | |
3856 | &dev_attr_temperature.attr, | |
b481de9c | 3857 | &dev_attr_tx_power.attr, |
d08853a3 | 3858 | #ifdef CONFIG_IWLWIFI_DEBUG |
40b8ec0b SO |
3859 | &dev_attr_debug_level.attr, |
3860 | #endif | |
b481de9c ZY |
3861 | NULL |
3862 | }; | |
3863 | ||
bb8c093b | 3864 | static struct attribute_group iwl3945_attribute_group = { |
b481de9c | 3865 | .name = NULL, /* put in device directory */ |
bb8c093b | 3866 | .attrs = iwl3945_sysfs_entries, |
b481de9c ZY |
3867 | }; |
3868 | ||
bb8c093b CH |
3869 | static struct ieee80211_ops iwl3945_hw_ops = { |
3870 | .tx = iwl3945_mac_tx, | |
3871 | .start = iwl3945_mac_start, | |
3872 | .stop = iwl3945_mac_stop, | |
cbb6ab94 | 3873 | .add_interface = iwl_mac_add_interface, |
d8052319 | 3874 | .remove_interface = iwl_mac_remove_interface, |
4808368d | 3875 | .config = iwl_mac_config, |
8ccde88a | 3876 | .configure_filter = iwl_configure_filter, |
bb8c093b | 3877 | .set_key = iwl3945_mac_set_key, |
aa89f31e | 3878 | .get_tx_stats = iwl_mac_get_tx_stats, |
488829f1 | 3879 | .conf_tx = iwl_mac_conf_tx, |
bd564261 | 3880 | .reset_tsf = iwl_mac_reset_tsf, |
5bbe233b | 3881 | .bss_info_changed = iwl_bss_info_changed, |
e9dde6f6 | 3882 | .hw_scan = iwl_mac_hw_scan |
b481de9c ZY |
3883 | }; |
3884 | ||
e52119c5 | 3885 | static int iwl3945_init_drv(struct iwl_priv *priv) |
90a30a02 KA |
3886 | { |
3887 | int ret; | |
e6148917 | 3888 | struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom; |
90a30a02 KA |
3889 | |
3890 | priv->retry_rate = 1; | |
3891 | priv->ibss_beacon = NULL; | |
3892 | ||
3893 | spin_lock_init(&priv->lock); | |
90a30a02 KA |
3894 | spin_lock_init(&priv->sta_lock); |
3895 | spin_lock_init(&priv->hcmd_lock); | |
3896 | ||
3897 | INIT_LIST_HEAD(&priv->free_frames); | |
3898 | ||
3899 | mutex_init(&priv->mutex); | |
3900 | ||
3901 | /* Clear the driver's (not device's) station table */ | |
c587de0b | 3902 | iwl_clear_stations_table(priv); |
90a30a02 KA |
3903 | |
3904 | priv->data_retry_limit = -1; | |
3905 | priv->ieee_channels = NULL; | |
3906 | priv->ieee_rates = NULL; | |
3907 | priv->band = IEEE80211_BAND_2GHZ; | |
3908 | ||
3909 | priv->iw_mode = NL80211_IFTYPE_STATION; | |
3910 | ||
3911 | iwl_reset_qos(priv); | |
3912 | ||
3913 | priv->qos_data.qos_active = 0; | |
3914 | priv->qos_data.qos_cap.val = 0; | |
3915 | ||
3916 | priv->rates_mask = IWL_RATES_MASK; | |
d25aabb0 WT |
3917 | /* If power management is turned on, default to CAM mode */ |
3918 | priv->power_mode = IWL_POWER_MODE_CAM; | |
62ea9c5b | 3919 | priv->tx_power_user_lmt = IWL_DEFAULT_TX_POWER; |
90a30a02 | 3920 | |
e6148917 SO |
3921 | if (eeprom->version < EEPROM_3945_EEPROM_VERSION) { |
3922 | IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n", | |
3923 | eeprom->version); | |
3924 | ret = -EINVAL; | |
3925 | goto err; | |
3926 | } | |
3927 | ret = iwl_init_channel_map(priv); | |
90a30a02 KA |
3928 | if (ret) { |
3929 | IWL_ERR(priv, "initializing regulatory failed: %d\n", ret); | |
3930 | goto err; | |
3931 | } | |
3932 | ||
e6148917 SO |
3933 | /* Set up txpower settings in driver for all channels */ |
3934 | if (iwl3945_txpower_set_from_eeprom(priv)) { | |
3935 | ret = -EIO; | |
3936 | goto err_free_channel_map; | |
3937 | } | |
3938 | ||
534166de | 3939 | ret = iwlcore_init_geos(priv); |
90a30a02 KA |
3940 | if (ret) { |
3941 | IWL_ERR(priv, "initializing geos failed: %d\n", ret); | |
3942 | goto err_free_channel_map; | |
3943 | } | |
534166de SO |
3944 | iwl3945_init_hw_rates(priv, priv->ieee_rates); |
3945 | ||
2a4ddaab AK |
3946 | return 0; |
3947 | ||
3948 | err_free_channel_map: | |
3949 | iwl_free_channel_map(priv); | |
3950 | err: | |
3951 | return ret; | |
3952 | } | |
3953 | ||
3954 | static int iwl3945_setup_mac(struct iwl_priv *priv) | |
3955 | { | |
3956 | int ret; | |
3957 | struct ieee80211_hw *hw = priv->hw; | |
3958 | ||
3959 | hw->rate_control_algorithm = "iwl-3945-rs"; | |
3960 | hw->sta_data_size = sizeof(struct iwl3945_sta_priv); | |
3961 | ||
3962 | /* Tell mac80211 our characteristics */ | |
3963 | hw->flags = IEEE80211_HW_SIGNAL_DBM | | |
b1c6019b MA |
3964 | IEEE80211_HW_NOISE_DBM | |
3965 | IEEE80211_HW_SPECTRUM_MGMT; | |
2a4ddaab AK |
3966 | |
3967 | hw->wiphy->interface_modes = | |
3968 | BIT(NL80211_IFTYPE_STATION) | | |
3969 | BIT(NL80211_IFTYPE_ADHOC); | |
3970 | ||
3971 | hw->wiphy->custom_regulatory = true; | |
3972 | ||
1ecf9fc1 JB |
3973 | hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX_3945; |
3974 | /* we create the 802.11 header and a zero-length SSID element */ | |
3975 | hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2; | |
d60cc91a | 3976 | |
2a4ddaab AK |
3977 | /* Default value; 4 EDCA QOS priorities */ |
3978 | hw->queues = 4; | |
3979 | ||
534166de SO |
3980 | if (priv->bands[IEEE80211_BAND_2GHZ].n_channels) |
3981 | priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = | |
3982 | &priv->bands[IEEE80211_BAND_2GHZ]; | |
2a4ddaab | 3983 | |
534166de SO |
3984 | if (priv->bands[IEEE80211_BAND_5GHZ].n_channels) |
3985 | priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
3986 | &priv->bands[IEEE80211_BAND_5GHZ]; | |
90a30a02 | 3987 | |
2a4ddaab AK |
3988 | ret = ieee80211_register_hw(priv->hw); |
3989 | if (ret) { | |
3990 | IWL_ERR(priv, "Failed to register hw (error %d)\n", ret); | |
3991 | return ret; | |
3992 | } | |
3993 | priv->mac80211_registered = 1; | |
90a30a02 | 3994 | |
2a4ddaab | 3995 | return 0; |
90a30a02 KA |
3996 | } |
3997 | ||
bb8c093b | 3998 | static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
b481de9c ZY |
3999 | { |
4000 | int err = 0; | |
4a8a4322 | 4001 | struct iwl_priv *priv; |
b481de9c | 4002 | struct ieee80211_hw *hw; |
c0f20d91 | 4003 | struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data); |
e6148917 | 4004 | struct iwl3945_eeprom *eeprom; |
0359facc | 4005 | unsigned long flags; |
b481de9c | 4006 | |
cee53ddb KA |
4007 | /*********************** |
4008 | * 1. Allocating HW data | |
4009 | * ********************/ | |
4010 | ||
b481de9c ZY |
4011 | /* mac80211 allocates memory for this device instance, including |
4012 | * space for this driver's private structure */ | |
90a30a02 | 4013 | hw = iwl_alloc_all(cfg, &iwl3945_hw_ops); |
b481de9c | 4014 | if (hw == NULL) { |
a3139c59 | 4015 | printk(KERN_ERR DRV_NAME "Can not allocate network device\n"); |
b481de9c ZY |
4016 | err = -ENOMEM; |
4017 | goto out; | |
4018 | } | |
b481de9c | 4019 | priv = hw->priv; |
90a30a02 | 4020 | SET_IEEE80211_DEV(hw, &pdev->dev); |
6440adb5 | 4021 | |
df878d8f KA |
4022 | if ((iwl3945_mod_params.num_of_queues > IWL39_MAX_NUM_QUEUES) || |
4023 | (iwl3945_mod_params.num_of_queues < IWL_MIN_NUM_QUEUES)) { | |
15b1687c WT |
4024 | IWL_ERR(priv, |
4025 | "invalid queues_num, should be between %d and %d\n", | |
4026 | IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES); | |
a3139c59 | 4027 | err = -EINVAL; |
c8f16138 | 4028 | goto out_ieee80211_free_hw; |
a3139c59 SO |
4029 | } |
4030 | ||
90a30a02 KA |
4031 | /* |
4032 | * Disabling hardware scan means that mac80211 will perform scans | |
4033 | * "the hard way", rather than using device's scan. | |
4034 | */ | |
df878d8f | 4035 | if (iwl3945_mod_params.disable_hw_scan) { |
e1623446 | 4036 | IWL_DEBUG_INFO(priv, "Disabling hw_scan\n"); |
40b8ec0b SO |
4037 | iwl3945_hw_ops.hw_scan = NULL; |
4038 | } | |
4039 | ||
90a30a02 | 4040 | |
e1623446 | 4041 | IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n"); |
90a30a02 KA |
4042 | priv->cfg = cfg; |
4043 | priv->pci_dev = pdev; | |
40cefda9 | 4044 | priv->inta_mask = CSR_INI_SET_MASK; |
cee53ddb | 4045 | |
d08853a3 | 4046 | #ifdef CONFIG_IWLWIFI_DEBUG |
df878d8f | 4047 | priv->debug_level = iwl3945_mod_params.debug; |
b481de9c ZY |
4048 | atomic_set(&priv->restrict_refcnt, 0); |
4049 | #endif | |
b481de9c | 4050 | |
cee53ddb KA |
4051 | /*************************** |
4052 | * 2. Initializing PCI bus | |
4053 | * *************************/ | |
b481de9c ZY |
4054 | if (pci_enable_device(pdev)) { |
4055 | err = -ENODEV; | |
4056 | goto out_ieee80211_free_hw; | |
4057 | } | |
4058 | ||
4059 | pci_set_master(pdev); | |
4060 | ||
284901a9 | 4061 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
b481de9c | 4062 | if (!err) |
284901a9 | 4063 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
b481de9c | 4064 | if (err) { |
978785a3 | 4065 | IWL_WARN(priv, "No suitable DMA available.\n"); |
b481de9c ZY |
4066 | goto out_pci_disable_device; |
4067 | } | |
4068 | ||
4069 | pci_set_drvdata(pdev, priv); | |
4070 | err = pci_request_regions(pdev, DRV_NAME); | |
4071 | if (err) | |
4072 | goto out_pci_disable_device; | |
6440adb5 | 4073 | |
cee53ddb KA |
4074 | /*********************** |
4075 | * 3. Read REV Register | |
4076 | * ********************/ | |
b481de9c ZY |
4077 | priv->hw_base = pci_iomap(pdev, 0, 0); |
4078 | if (!priv->hw_base) { | |
4079 | err = -ENODEV; | |
4080 | goto out_pci_release_regions; | |
4081 | } | |
4082 | ||
e1623446 | 4083 | IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n", |
b481de9c | 4084 | (unsigned long long) pci_resource_len(pdev, 0)); |
e1623446 | 4085 | IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base); |
b481de9c | 4086 | |
cee53ddb KA |
4087 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
4088 | * PCI Tx retries from interfering with C3 CPU state */ | |
4089 | pci_write_config_byte(pdev, 0x41, 0x00); | |
b481de9c | 4090 | |
a8b50a0a MA |
4091 | /* this spin lock will be used in apm_ops.init and EEPROM access |
4092 | * we should init now | |
4093 | */ | |
4094 | spin_lock_init(&priv->reg_lock); | |
4095 | ||
90a30a02 KA |
4096 | /* amp init */ |
4097 | err = priv->cfg->ops->lib->apm_ops.init(priv); | |
cee53ddb | 4098 | if (err < 0) { |
d5df2a16 | 4099 | IWL_DEBUG_INFO(priv, "Failed to init the card\n"); |
90a30a02 | 4100 | goto out_iounmap; |
cee53ddb | 4101 | } |
b481de9c | 4102 | |
cee53ddb KA |
4103 | /*********************** |
4104 | * 4. Read EEPROM | |
4105 | * ********************/ | |
90a30a02 | 4106 | |
cee53ddb | 4107 | /* Read the EEPROM */ |
e6148917 | 4108 | err = iwl_eeprom_init(priv); |
cee53ddb | 4109 | if (err) { |
15b1687c | 4110 | IWL_ERR(priv, "Unable to init EEPROM\n"); |
c8f16138 | 4111 | goto out_iounmap; |
cee53ddb KA |
4112 | } |
4113 | /* MAC Address location in EEPROM same for 3945/4965 */ | |
e6148917 SO |
4114 | eeprom = (struct iwl3945_eeprom *)priv->eeprom; |
4115 | memcpy(priv->mac_addr, eeprom->mac_address, ETH_ALEN); | |
e1623446 | 4116 | IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr); |
cee53ddb | 4117 | SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr); |
b481de9c | 4118 | |
cee53ddb KA |
4119 | /*********************** |
4120 | * 5. Setup HW Constants | |
4121 | * ********************/ | |
b481de9c | 4122 | /* Device-specific setup */ |
3832ec9d | 4123 | if (iwl3945_hw_set_hw_params(priv)) { |
15b1687c | 4124 | IWL_ERR(priv, "failed to set hw settings\n"); |
c8f16138 | 4125 | goto out_eeprom_free; |
b481de9c ZY |
4126 | } |
4127 | ||
cee53ddb KA |
4128 | /*********************** |
4129 | * 6. Setup priv | |
4130 | * ********************/ | |
cee53ddb | 4131 | |
90a30a02 | 4132 | err = iwl3945_init_drv(priv); |
b481de9c | 4133 | if (err) { |
90a30a02 | 4134 | IWL_ERR(priv, "initializing driver failed\n"); |
c8f16138 | 4135 | goto out_unset_hw_params; |
b481de9c ZY |
4136 | } |
4137 | ||
978785a3 TW |
4138 | IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n", |
4139 | priv->cfg->name); | |
cee53ddb | 4140 | |
cee53ddb | 4141 | /*********************** |
09f9bf79 | 4142 | * 7. Setup Services |
cee53ddb KA |
4143 | * ********************/ |
4144 | ||
4145 | spin_lock_irqsave(&priv->lock, flags); | |
ed3b932e | 4146 | iwl_disable_interrupts(priv); |
cee53ddb KA |
4147 | spin_unlock_irqrestore(&priv->lock, flags); |
4148 | ||
2663516d HS |
4149 | pci_enable_msi(priv->pci_dev); |
4150 | ||
ef850d7c MA |
4151 | err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr, |
4152 | IRQF_SHARED, DRV_NAME, priv); | |
2663516d HS |
4153 | if (err) { |
4154 | IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq); | |
4155 | goto out_disable_msi; | |
4156 | } | |
4157 | ||
cee53ddb | 4158 | err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group); |
849e0dce | 4159 | if (err) { |
15b1687c | 4160 | IWL_ERR(priv, "failed to create sysfs device attributes\n"); |
90a30a02 | 4161 | goto out_release_irq; |
849e0dce | 4162 | } |
849e0dce | 4163 | |
8ccde88a SO |
4164 | iwl_set_rxon_channel(priv, |
4165 | &priv->bands[IEEE80211_BAND_2GHZ].channels[5]); | |
cee53ddb KA |
4166 | iwl3945_setup_deferred_work(priv); |
4167 | iwl3945_setup_rx_handlers(priv); | |
4168 | ||
cee53ddb | 4169 | /********************************* |
09f9bf79 | 4170 | * 8. Setup and Register mac80211 |
cee53ddb KA |
4171 | * *******************************/ |
4172 | ||
2a4ddaab | 4173 | iwl_enable_interrupts(priv); |
b481de9c | 4174 | |
2a4ddaab AK |
4175 | err = iwl3945_setup_mac(priv); |
4176 | if (err) | |
4177 | goto out_remove_sysfs; | |
cee53ddb | 4178 | |
a75fbe8d AK |
4179 | err = iwl_dbgfs_register(priv, DRV_NAME); |
4180 | if (err) | |
4181 | IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err); | |
4182 | ||
2663516d HS |
4183 | /* Start monitoring the killswitch */ |
4184 | queue_delayed_work(priv->workqueue, &priv->rfkill_poll, | |
4185 | 2 * HZ); | |
4186 | ||
b481de9c ZY |
4187 | return 0; |
4188 | ||
cee53ddb | 4189 | out_remove_sysfs: |
c8f16138 RC |
4190 | destroy_workqueue(priv->workqueue); |
4191 | priv->workqueue = NULL; | |
cee53ddb | 4192 | sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group); |
b481de9c | 4193 | out_release_irq: |
2663516d | 4194 | free_irq(priv->pci_dev->irq, priv); |
2663516d HS |
4195 | out_disable_msi: |
4196 | pci_disable_msi(priv->pci_dev); | |
c8f16138 RC |
4197 | iwlcore_free_geos(priv); |
4198 | iwl_free_channel_map(priv); | |
4199 | out_unset_hw_params: | |
4200 | iwl3945_unset_hw_params(priv); | |
4201 | out_eeprom_free: | |
4202 | iwl_eeprom_free(priv); | |
b481de9c ZY |
4203 | out_iounmap: |
4204 | pci_iounmap(pdev, priv->hw_base); | |
4205 | out_pci_release_regions: | |
4206 | pci_release_regions(pdev); | |
4207 | out_pci_disable_device: | |
b481de9c | 4208 | pci_set_drvdata(pdev, NULL); |
623d563e | 4209 | pci_disable_device(pdev); |
b481de9c ZY |
4210 | out_ieee80211_free_hw: |
4211 | ieee80211_free_hw(priv->hw); | |
4212 | out: | |
4213 | return err; | |
4214 | } | |
4215 | ||
c83dbf68 | 4216 | static void __devexit iwl3945_pci_remove(struct pci_dev *pdev) |
b481de9c | 4217 | { |
4a8a4322 | 4218 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
0359facc | 4219 | unsigned long flags; |
b481de9c ZY |
4220 | |
4221 | if (!priv) | |
4222 | return; | |
4223 | ||
e1623446 | 4224 | IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n"); |
b481de9c | 4225 | |
a75fbe8d AK |
4226 | iwl_dbgfs_unregister(priv); |
4227 | ||
b481de9c | 4228 | set_bit(STATUS_EXIT_PENDING, &priv->status); |
b24d22b1 | 4229 | |
d552bfb6 KA |
4230 | if (priv->mac80211_registered) { |
4231 | ieee80211_unregister_hw(priv->hw); | |
4232 | priv->mac80211_registered = 0; | |
4233 | } else { | |
4234 | iwl3945_down(priv); | |
4235 | } | |
b481de9c | 4236 | |
0359facc MA |
4237 | /* make sure we flush any pending irq or |
4238 | * tasklet for the driver | |
4239 | */ | |
4240 | spin_lock_irqsave(&priv->lock, flags); | |
ed3b932e | 4241 | iwl_disable_interrupts(priv); |
0359facc MA |
4242 | spin_unlock_irqrestore(&priv->lock, flags); |
4243 | ||
4244 | iwl_synchronize_irq(priv); | |
4245 | ||
bb8c093b | 4246 | sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group); |
b481de9c | 4247 | |
71d449b5 | 4248 | cancel_delayed_work_sync(&priv->rfkill_poll); |
2663516d | 4249 | |
bb8c093b | 4250 | iwl3945_dealloc_ucode_pci(priv); |
b481de9c ZY |
4251 | |
4252 | if (priv->rxq.bd) | |
df833b1d | 4253 | iwl3945_rx_queue_free(priv, &priv->rxq); |
bb8c093b | 4254 | iwl3945_hw_txq_ctx_free(priv); |
b481de9c | 4255 | |
3832ec9d | 4256 | iwl3945_unset_hw_params(priv); |
c587de0b | 4257 | iwl_clear_stations_table(priv); |
b481de9c | 4258 | |
6ef89d0a MA |
4259 | /*netif_stop_queue(dev); */ |
4260 | flush_workqueue(priv->workqueue); | |
4261 | ||
bb8c093b | 4262 | /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes |
b481de9c ZY |
4263 | * priv->workqueue... so we can't take down the workqueue |
4264 | * until now... */ | |
4265 | destroy_workqueue(priv->workqueue); | |
4266 | priv->workqueue = NULL; | |
4267 | ||
2663516d HS |
4268 | free_irq(pdev->irq, priv); |
4269 | pci_disable_msi(pdev); | |
4270 | ||
b481de9c ZY |
4271 | pci_iounmap(pdev, priv->hw_base); |
4272 | pci_release_regions(pdev); | |
4273 | pci_disable_device(pdev); | |
4274 | pci_set_drvdata(pdev, NULL); | |
4275 | ||
e6148917 | 4276 | iwl_free_channel_map(priv); |
534166de | 4277 | iwlcore_free_geos(priv); |
805cee5b | 4278 | kfree(priv->scan); |
b481de9c ZY |
4279 | if (priv->ibss_beacon) |
4280 | dev_kfree_skb(priv->ibss_beacon); | |
4281 | ||
4282 | ieee80211_free_hw(priv->hw); | |
4283 | } | |
4284 | ||
b481de9c ZY |
4285 | |
4286 | /***************************************************************************** | |
4287 | * | |
4288 | * driver and module entry point | |
4289 | * | |
4290 | *****************************************************************************/ | |
4291 | ||
bb8c093b | 4292 | static struct pci_driver iwl3945_driver = { |
b481de9c | 4293 | .name = DRV_NAME, |
bb8c093b CH |
4294 | .id_table = iwl3945_hw_card_ids, |
4295 | .probe = iwl3945_pci_probe, | |
4296 | .remove = __devexit_p(iwl3945_pci_remove), | |
b481de9c | 4297 | #ifdef CONFIG_PM |
6da3a13e WYG |
4298 | .suspend = iwl_pci_suspend, |
4299 | .resume = iwl_pci_resume, | |
b481de9c ZY |
4300 | #endif |
4301 | }; | |
4302 | ||
bb8c093b | 4303 | static int __init iwl3945_init(void) |
b481de9c ZY |
4304 | { |
4305 | ||
4306 | int ret; | |
4307 | printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n"); | |
4308 | printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n"); | |
897e1cf2 RC |
4309 | |
4310 | ret = iwl3945_rate_control_register(); | |
4311 | if (ret) { | |
a3139c59 SO |
4312 | printk(KERN_ERR DRV_NAME |
4313 | "Unable to register rate control algorithm: %d\n", ret); | |
897e1cf2 RC |
4314 | return ret; |
4315 | } | |
4316 | ||
bb8c093b | 4317 | ret = pci_register_driver(&iwl3945_driver); |
b481de9c | 4318 | if (ret) { |
a3139c59 | 4319 | printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n"); |
897e1cf2 | 4320 | goto error_register; |
b481de9c | 4321 | } |
b481de9c ZY |
4322 | |
4323 | return ret; | |
897e1cf2 | 4324 | |
897e1cf2 RC |
4325 | error_register: |
4326 | iwl3945_rate_control_unregister(); | |
4327 | return ret; | |
b481de9c ZY |
4328 | } |
4329 | ||
bb8c093b | 4330 | static void __exit iwl3945_exit(void) |
b481de9c | 4331 | { |
bb8c093b | 4332 | pci_unregister_driver(&iwl3945_driver); |
897e1cf2 | 4333 | iwl3945_rate_control_unregister(); |
b481de9c ZY |
4334 | } |
4335 | ||
a0987a8d | 4336 | MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX)); |
25cb6cad | 4337 | |
df878d8f | 4338 | module_param_named(antenna, iwl3945_mod_params.antenna, int, 0444); |
b481de9c | 4339 | MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])"); |
9c74d9fb SO |
4340 | module_param_named(swcrypto, iwl3945_mod_params.sw_crypto, int, 0444); |
4341 | MODULE_PARM_DESC(swcrypto, | |
4342 | "using software crypto (default 1 [software])\n"); | |
df878d8f | 4343 | module_param_named(debug, iwl3945_mod_params.debug, uint, 0444); |
b481de9c | 4344 | MODULE_PARM_DESC(debug, "debug output mask"); |
df878d8f | 4345 | module_param_named(disable_hw_scan, iwl3945_mod_params.disable_hw_scan, int, 0444); |
b481de9c ZY |
4346 | MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)"); |
4347 | ||
df878d8f | 4348 | module_param_named(queues_num, iwl3945_mod_params.num_of_queues, int, 0444); |
b481de9c ZY |
4349 | MODULE_PARM_DESC(queues_num, "number of hw queues."); |
4350 | ||
af48d048 SO |
4351 | module_param_named(fw_restart3945, iwl3945_mod_params.restart_fw, int, 0444); |
4352 | MODULE_PARM_DESC(fw_restart3945, "restart firmware in case of error"); | |
4353 | ||
bb8c093b CH |
4354 | module_exit(iwl3945_exit); |
4355 | module_init(iwl3945_init); |