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iwlwifi: fix iwl4965 temperature callback calibration issue
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl3945-base.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
b481de9c
ZY		 30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/version.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/dma-mapping.h>
36#include <linux/delay.h>
37#include <linux/skbuff.h>
38#include <linux/netdevice.h>
39#include <linux/wireless.h>
40#include <linux/firmware.h>
b481de9c
ZY		 41#include <linux/etherdevice.h>
42#include <linux/if_arp.h>
43
44#include <net/ieee80211_radiotap.h>
45#include <net/mac80211.h>
46
47#include <asm/div64.h>
48
82b9a121 49#include "iwl-3945-core.h"
b481de9c
ZY		 50#include "iwl-3945.h"
51#include "iwl-helpers.h"
52
c8b0e6e1 53#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 54u32 iwl3945_debug_level;
b481de9c
ZY		 55#endif
56
bb8c093b
CH		 57static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
58 struct iwl3945_tx_queue *txq);
416e1438 59
b481de9c
ZY		 60/******************************************************************************
61 *
62 * module boiler plate
63 *
64 ******************************************************************************/
65
66/* module parameters */
6440adb5
CB		 67static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */
68static int iwl3945_param_debug; /* def: 0 = minimal debug log messages */
69static int iwl3945_param_disable; /* def: 0 = enable radio */
9fbab516 70static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */
6440adb5
CB		 71int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */
72static int iwl3945_param_qos_enable = 1; /* def: 1 = use quality of service */
dfe7d458 73int iwl3945_param_queues_num = IWL39_MAX_NUM_QUEUES; /* def: 8 Tx queues */
b481de9c
ZY		 74
75/*
76 * module name, copyright, version, etc.
77 * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
78 */
79
80#define DRV_DESCRIPTION \
81"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
82
c8b0e6e1 83#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 84#define VD "d"
85#else
86#define VD
87#endif
88
c8b0e6e1 89#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 90#define VS "s"
91#else
92#define VS
93#endif
94
b9e0b449 95#define IWLWIFI_VERSION "1.2.26k" VD VS
eb7ae89c 96#define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation"
b481de9c
ZY		 97#define DRV_VERSION IWLWIFI_VERSION
98
b481de9c
ZY		 99
100MODULE_DESCRIPTION(DRV_DESCRIPTION);
101MODULE_VERSION(DRV_VERSION);
102MODULE_AUTHOR(DRV_COPYRIGHT);
103MODULE_LICENSE("GPL");
104
8318d78a
JB		 105static const struct ieee80211_supported_band *iwl3945_get_band(
106 struct iwl3945_priv *priv, enum ieee80211_band band)
b481de9c 107{
8318d78a 108 return priv->hw->wiphy->bands[band];
b481de9c
ZY		 109}
110
bb8c093b 111static int iwl3945_is_empty_essid(const char *essid, int essid_len)
b481de9c
ZY		 112{
113 /* Single white space is for Linksys APs */
114 if (essid_len == 1 && essid[0] == ' ')
115 return 1;
116
117 /* Otherwise, if the entire essid is 0, we assume it is hidden */
118 while (essid_len) {
119 essid_len--;
120 if (essid[essid_len] != '\0')
121 return 0;
122 }
123
124 return 1;
125}
126
bb8c093b 127static const char *iwl3945_escape_essid(const char *essid, u8 essid_len)
b481de9c
ZY		 128{
129 static char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
130 const char *s = essid;
131 char *d = escaped;
132
bb8c093b 133 if (iwl3945_is_empty_essid(essid, essid_len)) {
b481de9c
ZY		 134 memcpy(escaped, "<hidden>", sizeof("<hidden>"));
135 return escaped;
136 }
137
138 essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE);
139 while (essid_len--) {
140 if (*s == '\0') {
141 *d++ = '\\';
142 *d++ = '0';
143 s++;
144 } else
145 *d++ = *s++;
146 }
147 *d = '\0';
148 return escaped;
149}
150
b481de9c
ZY		 151/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
152 * DMA services
153 *
154 * Theory of operation
155 *
6440adb5
CB		 156 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
157 * of buffer descriptors, each of which points to one or more data buffers for
158 * the device to read from or fill. Driver and device exchange status of each
159 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
160 * entries in each circular buffer, to protect against confusing empty and full
161 * queue states.
162 *
163 * The device reads or writes the data in the queues via the device's several
164 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
b481de9c
ZY		 165 *
166 * For Tx queue, there are low mark and high mark limits. If, after queuing
167 * the packet for Tx, free space become < low mark, Tx queue stopped. When
168 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
169 * Tx queue resumed.
170 *
6440adb5
CB		 171 * The 3945 operates with six queues: One receive queue, one transmit queue
172 * (#4) for sending commands to the device firmware, and four transmit queues
173 * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
b481de9c
ZY		 174 ***************************************************/
175
c54b679d 176int iwl3945_queue_space(const struct iwl3945_queue *q)
b481de9c 177{
fc4b6853 178 int s = q->read_ptr - q->write_ptr;
b481de9c 179
fc4b6853 180 if (q->read_ptr > q->write_ptr)
b481de9c
ZY		 181 s -= q->n_bd;
182
183 if (s <= 0)
184 s += q->n_window;
185 /* keep some reserve to not confuse empty and full situations */
186 s -= 2;
187 if (s < 0)
188 s = 0;
189 return s;
190}
191
c54b679d 192int iwl3945_x2_queue_used(const struct iwl3945_queue *q, int i)
b481de9c 193{
fc4b6853
TW		 194 return q->write_ptr > q->read_ptr ?
195 (i >= q->read_ptr && i < q->write_ptr) :
196 !(i < q->read_ptr && i >= q->write_ptr);
b481de9c
ZY		 197}
198
c54b679d 199
bb8c093b 200static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge)
b481de9c 201{
6440adb5 202 /* This is for scan command, the big buffer at end of command array */
b481de9c 203 if (is_huge)
6440adb5 204 return q->n_window; /* must be power of 2 */
b481de9c 205
6440adb5 206 /* Otherwise, use normal size buffers */
b481de9c
ZY		 207 return index & (q->n_window - 1);
208}
209
6440adb5
CB		 210/**
211 * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
212 */
bb8c093b 213static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q,
b481de9c
ZY		 214 int count, int slots_num, u32 id)
215{
216 q->n_bd = count;
217 q->n_window = slots_num;
218 q->id = id;
219
c54b679d
TW		 220 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
221 * and iwl_queue_dec_wrap are broken. */
b481de9c
ZY		 222 BUG_ON(!is_power_of_2(count));
223
224 /* slots_num must be power-of-two size, otherwise
225 * get_cmd_index is broken. */
226 BUG_ON(!is_power_of_2(slots_num));
227
228 q->low_mark = q->n_window / 4;
229 if (q->low_mark < 4)
230 q->low_mark = 4;
231
232 q->high_mark = q->n_window / 8;
233 if (q->high_mark < 2)
234 q->high_mark = 2;
235
fc4b6853 236 q->write_ptr = q->read_ptr = 0;
b481de9c
ZY		 237
238 return 0;
239}
240
6440adb5
CB		 241/**
242 * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
243 */
bb8c093b
CH		 244static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
245 struct iwl3945_tx_queue *txq, u32 id)
b481de9c
ZY		 246{
247 struct pci_dev *dev = priv->pci_dev;
248
6440adb5
CB		 249 /* Driver private data, only for Tx (not command) queues,
250 * not shared with device. */
b481de9c
ZY		 251 if (id != IWL_CMD_QUEUE_NUM) {
252 txq->txb = kmalloc(sizeof(txq->txb[0]) *
253 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
254 if (!txq->txb) {
01ebd063 255 IWL_ERROR("kmalloc for auxiliary BD "
b481de9c
ZY		 256 "structures failed\n");
257 goto error;
258 }
259 } else
260 txq->txb = NULL;
261
6440adb5
CB		 262 /* Circular buffer of transmit frame descriptors (TFDs),
263 * shared with device */
b481de9c
ZY		 264 txq->bd = pci_alloc_consistent(dev,
265 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
266 &txq->q.dma_addr);
267
268 if (!txq->bd) {
269 IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
270 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
271 goto error;
272 }
273 txq->q.id = id;
274
275 return 0;
276
277 error:
278 if (txq->txb) {
279 kfree(txq->txb);
280 txq->txb = NULL;
281 }
282
283 return -ENOMEM;
284}
285
6440adb5
CB		 286/**
287 * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
288 */
bb8c093b
CH		 289int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
290 struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
b481de9c
ZY		 291{
292 struct pci_dev *dev = priv->pci_dev;
293 int len;
294 int rc = 0;
295
6440adb5
CB		 296 /*
297 * Alloc buffer array for commands (Tx or other types of commands).
298 * For the command queue (#4), allocate command space + one big
299 * command for scan, since scan command is very huge; the system will
300 * not have two scans at the same time, so only one is needed.
301 * For data Tx queues (all other queues), no super-size command
302 * space is needed.
303 */
bb8c093b 304 len = sizeof(struct iwl3945_cmd) * slots_num;
b481de9c
ZY		 305 if (txq_id == IWL_CMD_QUEUE_NUM)
306 len += IWL_MAX_SCAN_SIZE;
307 txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
308 if (!txq->cmd)
309 return -ENOMEM;
310
6440adb5 311 /* Alloc driver data array and TFD circular buffer */
bb8c093b 312 rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
b481de9c
ZY		 313 if (rc) {
314 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
315
316 return -ENOMEM;
317 }
318 txq->need_update = 0;
319
320 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
c54b679d 321 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
b481de9c 322 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
6440adb5
CB		 323
324 /* Initialize queue high/low-water, head/tail indexes */
bb8c093b 325 iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
b481de9c 326
6440adb5 327 /* Tell device where to find queue, enable DMA channel. */
bb8c093b 328 iwl3945_hw_tx_queue_init(priv, txq);
b481de9c
ZY		 329
330 return 0;
331}
332
333/**
bb8c093b 334 * iwl3945_tx_queue_free - Deallocate DMA queue.
b481de9c
ZY		 335 * @txq: Transmit queue to deallocate.
336 *
337 * Empty queue by removing and destroying all BD's.
6440adb5
CB		 338 * Free all buffers.
339 * 0-fill, but do not free "txq" descriptor structure.
b481de9c 340 */
bb8c093b 341void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c 342{
bb8c093b 343 struct iwl3945_queue *q = &txq->q;
b481de9c
ZY		 344 struct pci_dev *dev = priv->pci_dev;
345 int len;
346
347 if (q->n_bd == 0)
348 return;
349
350 /* first, empty all BD's */
fc4b6853 351 for (; q->write_ptr != q->read_ptr;
c54b679d 352 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
bb8c093b 353 iwl3945_hw_txq_free_tfd(priv, txq);
b481de9c 354
bb8c093b 355 len = sizeof(struct iwl3945_cmd) * q->n_window;
b481de9c
ZY		 356 if (q->id == IWL_CMD_QUEUE_NUM)
357 len += IWL_MAX_SCAN_SIZE;
358
6440adb5 359 /* De-alloc array of command/tx buffers */
b481de9c
ZY		 360 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
361
6440adb5 362 /* De-alloc circular buffer of TFDs */
b481de9c 363 if (txq->q.n_bd)
bb8c093b 364 pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
b481de9c
ZY		 365 txq->q.n_bd, txq->bd, txq->q.dma_addr);
366
6440adb5 367 /* De-alloc array of per-TFD driver data */
b481de9c
ZY		 368 if (txq->txb) {
369 kfree(txq->txb);
370 txq->txb = NULL;
371 }
372
6440adb5 373 /* 0-fill queue descriptor structure */
b481de9c
ZY		 374 memset(txq, 0, sizeof(*txq));
375}
376
bb8c093b 377const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
b481de9c
ZY		 378
379/*************** STATION TABLE MANAGEMENT ****
9fbab516 380 * mac80211 should be examined to determine if sta_info is duplicating
b481de9c
ZY		 381 * the functionality provided here
382 */
383
384/**************************************************************/
01ebd063 385#if 0 /* temporary disable till we add real remove station */
6440adb5
CB		 386/**
387 * iwl3945_remove_station - Remove driver's knowledge of station.
388 *
389 * NOTE: This does not remove station from device's station table.
390 */
bb8c093b 391static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
b481de9c
ZY		 392{
393 int index = IWL_INVALID_STATION;
394 int i;
395 unsigned long flags;
396
397 spin_lock_irqsave(&priv->sta_lock, flags);
398
399 if (is_ap)
400 index = IWL_AP_ID;
401 else if (is_broadcast_ether_addr(addr))
402 index = priv->hw_setting.bcast_sta_id;
403 else
404 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
405 if (priv->stations[i].used &&
406 !compare_ether_addr(priv->stations[i].sta.sta.addr,
407 addr)) {
408 index = i;
409 break;
410 }
411
412 if (unlikely(index == IWL_INVALID_STATION))
413 goto out;
414
415 if (priv->stations[index].used) {
416 priv->stations[index].used = 0;
417 priv->num_stations--;
418 }
419
420 BUG_ON(priv->num_stations < 0);
421
422out:
423 spin_unlock_irqrestore(&priv->sta_lock, flags);
424 return 0;
425}
556f8db7 426#endif
6440adb5
CB		 427
428/**
429 * iwl3945_clear_stations_table - Clear the driver's station table
430 *
431 * NOTE: This does not clear or otherwise alter the device's station table.
432 */
bb8c093b 433static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
b481de9c
ZY		 434{
435 unsigned long flags;
436
437 spin_lock_irqsave(&priv->sta_lock, flags);
438
439 priv->num_stations = 0;
440 memset(priv->stations, 0, sizeof(priv->stations));
441
442 spin_unlock_irqrestore(&priv->sta_lock, flags);
443}
444
6440adb5
CB		 445/**
446 * iwl3945_add_station - Add station to station tables in driver and device
447 */
bb8c093b 448u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
b481de9c
ZY		 449{
450 int i;
451 int index = IWL_INVALID_STATION;
bb8c093b 452 struct iwl3945_station_entry *station;
b481de9c 453 unsigned long flags_spin;
0795af57 454 DECLARE_MAC_BUF(mac);
c14c521e 455 u8 rate;
b481de9c
ZY		 456
457 spin_lock_irqsave(&priv->sta_lock, flags_spin);
458 if (is_ap)
459 index = IWL_AP_ID;
460 else if (is_broadcast_ether_addr(addr))
461 index = priv->hw_setting.bcast_sta_id;
462 else
463 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
464 if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
465 addr)) {
466 index = i;
467 break;
468 }
469
470 if (!priv->stations[i].used &&
471 index == IWL_INVALID_STATION)
472 index = i;
473 }
474
01ebd063 475 /* These two conditions has the same outcome but keep them separate
b481de9c
ZY		 476 since they have different meaning */
477 if (unlikely(index == IWL_INVALID_STATION)) {
478 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
479 return index;
480 }
481
482 if (priv->stations[index].used &&
483 !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
484 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
485 return index;
486 }
487
0795af57 488 IWL_DEBUG_ASSOC("Add STA ID %d: %s\n", index, print_mac(mac, addr));
b481de9c
ZY		 489 station = &priv->stations[index];
490 station->used = 1;
491 priv->num_stations++;
492
6440adb5 493 /* Set up the REPLY_ADD_STA command to send to device */
bb8c093b 494 memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
b481de9c
ZY		 495 memcpy(station->sta.sta.addr, addr, ETH_ALEN);
496 station->sta.mode = 0;
497 station->sta.sta.sta_id = index;
498 station->sta.station_flags = 0;
499
8318d78a 500 if (priv->band == IEEE80211_BAND_5GHZ)
69946333
TW		 501 rate = IWL_RATE_6M_PLCP;
502 else
503 rate = IWL_RATE_1M_PLCP;
c14c521e
ZY		 504
505 /* Turn on both antennas for the station... */
506 station->sta.rate_n_flags =
bb8c093b 507 iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
c14c521e
ZY		 508 station->current_rate.rate_n_flags =
509 le16_to_cpu(station->sta.rate_n_flags);
510
b481de9c 511 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
6440adb5
CB		 512
513 /* Add station to device's station table */
bb8c093b 514 iwl3945_send_add_station(priv, &station->sta, flags);
b481de9c
ZY		 515 return index;
516
517}
518
519/*************** DRIVER STATUS FUNCTIONS *****/
520
bb8c093b 521static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
b481de9c
ZY		 522{
523 /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
524 * set but EXIT_PENDING is not */
525 return test_bit(STATUS_READY, &priv->status) &&
526 test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
527 !test_bit(STATUS_EXIT_PENDING, &priv->status);
528}
529
bb8c093b 530static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
b481de9c
ZY		 531{
532 return test_bit(STATUS_ALIVE, &priv->status);
533}
534
bb8c093b 535static inline int iwl3945_is_init(struct iwl3945_priv *priv)
b481de9c
ZY		 536{
537 return test_bit(STATUS_INIT, &priv->status);
538}
539
bb8c093b 540static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
b481de9c
ZY		 541{
542 return test_bit(STATUS_RF_KILL_HW, &priv->status) ||
543 test_bit(STATUS_RF_KILL_SW, &priv->status);
544}
545
bb8c093b 546static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
b481de9c
ZY		 547{
548
bb8c093b 549 if (iwl3945_is_rfkill(priv))
b481de9c
ZY		 550 return 0;
551
bb8c093b 552 return iwl3945_is_ready(priv);
b481de9c
ZY		 553}
554
555/*************** HOST COMMAND QUEUE FUNCTIONS *****/
556
557#define IWL_CMD(x) case x : return #x
558
559static const char *get_cmd_string(u8 cmd)
560{
561 switch (cmd) {
562 IWL_CMD(REPLY_ALIVE);
563 IWL_CMD(REPLY_ERROR);
564 IWL_CMD(REPLY_RXON);
565 IWL_CMD(REPLY_RXON_ASSOC);
566 IWL_CMD(REPLY_QOS_PARAM);
567 IWL_CMD(REPLY_RXON_TIMING);
568 IWL_CMD(REPLY_ADD_STA);
569 IWL_CMD(REPLY_REMOVE_STA);
570 IWL_CMD(REPLY_REMOVE_ALL_STA);
571 IWL_CMD(REPLY_3945_RX);
572 IWL_CMD(REPLY_TX);
573 IWL_CMD(REPLY_RATE_SCALE);
574 IWL_CMD(REPLY_LEDS_CMD);
575 IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
576 IWL_CMD(RADAR_NOTIFICATION);
577 IWL_CMD(REPLY_QUIET_CMD);
578 IWL_CMD(REPLY_CHANNEL_SWITCH);
579 IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
580 IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
581 IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
582 IWL_CMD(POWER_TABLE_CMD);
583 IWL_CMD(PM_SLEEP_NOTIFICATION);
584 IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
585 IWL_CMD(REPLY_SCAN_CMD);
586 IWL_CMD(REPLY_SCAN_ABORT_CMD);
587 IWL_CMD(SCAN_START_NOTIFICATION);
588 IWL_CMD(SCAN_RESULTS_NOTIFICATION);
589 IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
590 IWL_CMD(BEACON_NOTIFICATION);
591 IWL_CMD(REPLY_TX_BEACON);
592 IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
593 IWL_CMD(QUIET_NOTIFICATION);
594 IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
595 IWL_CMD(MEASURE_ABORT_NOTIFICATION);
596 IWL_CMD(REPLY_BT_CONFIG);
597 IWL_CMD(REPLY_STATISTICS_CMD);
598 IWL_CMD(STATISTICS_NOTIFICATION);
599 IWL_CMD(REPLY_CARD_STATE_CMD);
600 IWL_CMD(CARD_STATE_NOTIFICATION);
601 IWL_CMD(MISSED_BEACONS_NOTIFICATION);
602 default:
603 return "UNKNOWN";
604
605 }
606}
607
608#define HOST_COMPLETE_TIMEOUT (HZ / 2)
609
610/**
bb8c093b 611 * iwl3945_enqueue_hcmd - enqueue a uCode command
b481de9c
ZY		 612 * @priv: device private data point
613 * @cmd: a point to the ucode command structure
614 *
615 * The function returns < 0 values to indicate the operation is
616 * failed. On success, it turns the index (> 0) of command in the
617 * command queue.
618 */
bb8c093b 619static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c 620{
bb8c093b
CH		 621 struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
622 struct iwl3945_queue *q = &txq->q;
623 struct iwl3945_tfd_frame *tfd;
b481de9c 624 u32 *control_flags;
bb8c093b 625 struct iwl3945_cmd *out_cmd;
b481de9c
ZY		 626 u32 idx;
627 u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
628 dma_addr_t phys_addr;
629 int pad;
630 u16 count;
631 int ret;
632 unsigned long flags;
633
634 /* If any of the command structures end up being larger than
635 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
636 * we will need to increase the size of the TFD entries */
637 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
638 !(cmd->meta.flags & CMD_SIZE_HUGE));
639
c342a1b9
GG		 640
641 if (iwl3945_is_rfkill(priv)) {
642 IWL_DEBUG_INFO("Not sending command - RF KILL");
643 return -EIO;
644 }
645
bb8c093b 646 if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
b481de9c
ZY		 647 IWL_ERROR("No space for Tx\n");
648 return -ENOSPC;
649 }
650
651 spin_lock_irqsave(&priv->hcmd_lock, flags);
652
fc4b6853 653 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY		 654 memset(tfd, 0, sizeof(*tfd));
655
656 control_flags = (u32 *) tfd;
657
fc4b6853 658 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
b481de9c
ZY		 659 out_cmd = &txq->cmd[idx];
660
661 out_cmd->hdr.cmd = cmd->id;
662 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
663 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
664
665 /* At this point, the out_cmd now has all of the incoming cmd
666 * information */
667
668 out_cmd->hdr.flags = 0;
669 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
fc4b6853 670 INDEX_TO_SEQ(q->write_ptr));
b481de9c
ZY		 671 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
672 out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
673
674 phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
bb8c093b
CH		 675 offsetof(struct iwl3945_cmd, hdr);
676 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
b481de9c
ZY		 677
678 pad = U32_PAD(cmd->len);
679 count = TFD_CTL_COUNT_GET(*control_flags);
680 *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
681
682 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
683 "%d bytes at %d[%d]:%d\n",
684 get_cmd_string(out_cmd->hdr.cmd),
685 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
fc4b6853 686 fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
b481de9c
ZY		 687
688 txq->need_update = 1;
6440adb5
CB		 689
690 /* Increment and update queue's write index */
c54b679d 691 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
bb8c093b 692 ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 693
694 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
695 return ret ? ret : idx;
696}
697
bb8c093b 698static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c
ZY		 699{
700 int ret;
701
702 BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
703
704 /* An asynchronous command can not expect an SKB to be set. */
705 BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
706
707 /* An asynchronous command MUST have a callback. */
708 BUG_ON(!cmd->meta.u.callback);
709
710 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
711 return -EBUSY;
712
bb8c093b 713 ret = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c 714 if (ret < 0) {
bb8c093b 715 IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
b481de9c
ZY		 716 get_cmd_string(cmd->id), ret);
717 return ret;
718 }
719 return 0;
720}
721
bb8c093b 722static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c
ZY		 723{
724 int cmd_idx;
725 int ret;
b481de9c
ZY		 726
727 BUG_ON(cmd->meta.flags & CMD_ASYNC);
728
729 /* A synchronous command can not have a callback set. */
730 BUG_ON(cmd->meta.u.callback != NULL);
731
e5472978 732 if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) {
b481de9c
ZY		 733 IWL_ERROR("Error sending %s: Already sending a host command\n",
734 get_cmd_string(cmd->id));
e5472978
TW		 735 ret = -EBUSY;
736 goto out;
b481de9c
ZY		 737 }
738
739 set_bit(STATUS_HCMD_ACTIVE, &priv->status);
740
741 if (cmd->meta.flags & CMD_WANT_SKB)
742 cmd->meta.source = &cmd->meta;
743
bb8c093b 744 cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c
ZY		 745 if (cmd_idx < 0) {
746 ret = cmd_idx;
bb8c093b 747 IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
b481de9c
ZY		 748 get_cmd_string(cmd->id), ret);
749 goto out;
750 }
751
752 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
753 !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
754 HOST_COMPLETE_TIMEOUT);
755 if (!ret) {
756 if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
757 IWL_ERROR("Error sending %s: time out after %dms.\n",
758 get_cmd_string(cmd->id),
759 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
760
761 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
762 ret = -ETIMEDOUT;
763 goto cancel;
764 }
765 }
766
767 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
768 IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
769 get_cmd_string(cmd->id));
770 ret = -ECANCELED;
771 goto fail;
772 }
773 if (test_bit(STATUS_FW_ERROR, &priv->status)) {
774 IWL_DEBUG_INFO("Command %s failed: FW Error\n",
775 get_cmd_string(cmd->id));
776 ret = -EIO;
777 goto fail;
778 }
779 if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
780 IWL_ERROR("Error: Response NULL in '%s'\n",
781 get_cmd_string(cmd->id));
782 ret = -EIO;
783 goto out;
784 }
785
786 ret = 0;
787 goto out;
788
789cancel:
790 if (cmd->meta.flags & CMD_WANT_SKB) {
bb8c093b 791 struct iwl3945_cmd *qcmd;
b481de9c
ZY		 792
793 /* Cancel the CMD_WANT_SKB flag for the cmd in the
794 * TX cmd queue. Otherwise in case the cmd comes
795 * in later, it will possibly set an invalid
796 * address (cmd->meta.source). */
797 qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
798 qcmd->meta.flags &= ~CMD_WANT_SKB;
799 }
800fail:
801 if (cmd->meta.u.skb) {
802 dev_kfree_skb_any(cmd->meta.u.skb);
803 cmd->meta.u.skb = NULL;
804 }
805out:
e5472978 806 clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status);
b481de9c
ZY		 807 return ret;
808}
809
bb8c093b 810int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c 811{
b481de9c 812 if (cmd->meta.flags & CMD_ASYNC)
bb8c093b 813 return iwl3945_send_cmd_async(priv, cmd);
b481de9c 814
bb8c093b 815 return iwl3945_send_cmd_sync(priv, cmd);
b481de9c
ZY		 816}
817
bb8c093b 818int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
b481de9c 819{
bb8c093b 820 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 821 .id = id,
822 .len = len,
823 .data = data,
824 };
825
bb8c093b 826 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 827}
828
bb8c093b 829static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
b481de9c 830{
bb8c093b 831 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 832 .id = id,
833 .len = sizeof(val),
834 .data = &val,
835 };
836
bb8c093b 837 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 838}
839
bb8c093b 840int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
b481de9c 841{
bb8c093b 842 return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
b481de9c
ZY		 843}
844
b481de9c 845/**
bb8c093b 846 * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
8318d78a
JB		 847 * @band: 2.4 or 5 GHz band
848 * @channel: Any channel valid for the requested band
b481de9c 849
8318d78a 850 * In addition to setting the staging RXON, priv->band is also set.
b481de9c
ZY		 851 *
852 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
8318d78a 853 * in the staging RXON flag structure based on the band
b481de9c 854 */
8318d78a
JB		 855static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv,
856 enum ieee80211_band band,
857 u16 channel)
b481de9c 858{
8318d78a 859 if (!iwl3945_get_channel_info(priv, band, channel)) {
b481de9c 860 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
8318d78a 861 channel, band);
b481de9c
ZY		 862 return -EINVAL;
863 }
864
865 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
8318d78a 866 (priv->band == band))
b481de9c
ZY		 867 return 0;
868
869 priv->staging_rxon.channel = cpu_to_le16(channel);
8318d78a 870 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 871 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
872 else
873 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
874
8318d78a 875 priv->band = band;
b481de9c 876
8318d78a 877 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
b481de9c
ZY		 878
879 return 0;
880}
881
882/**
bb8c093b 883 * iwl3945_check_rxon_cmd - validate RXON structure is valid
b481de9c
ZY		 884 *
885 * NOTE: This is really only useful during development and can eventually
886 * be #ifdef'd out once the driver is stable and folks aren't actively
887 * making changes
888 */
bb8c093b 889static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon)
b481de9c
ZY		 890{
891 int error = 0;
892 int counter = 1;
893
894 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
895 error |= le32_to_cpu(rxon->flags &
896 (RXON_FLG_TGJ_NARROW_BAND_MSK |
897 RXON_FLG_RADAR_DETECT_MSK));
898 if (error)
899 IWL_WARNING("check 24G fields %d | %d\n",
900 counter++, error);
901 } else {
902 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
903 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
904 if (error)
905 IWL_WARNING("check 52 fields %d | %d\n",
906 counter++, error);
907 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
908 if (error)
909 IWL_WARNING("check 52 CCK %d | %d\n",
910 counter++, error);
911 }
912 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
913 if (error)
914 IWL_WARNING("check mac addr %d | %d\n", counter++, error);
915
916 /* make sure basic rates 6Mbps and 1Mbps are supported */
917 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
918 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
919 if (error)
920 IWL_WARNING("check basic rate %d | %d\n", counter++, error);
921
922 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
923 if (error)
924 IWL_WARNING("check assoc id %d | %d\n", counter++, error);
925
926 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
927 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
928 if (error)
929 IWL_WARNING("check CCK and short slot %d | %d\n",
930 counter++, error);
931
932 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
933 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
934 if (error)
935 IWL_WARNING("check CCK & auto detect %d | %d\n",
936 counter++, error);
937
938 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
939 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
940 if (error)
941 IWL_WARNING("check TGG and auto detect %d | %d\n",
942 counter++, error);
943
944 if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
945 error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
946 RXON_FLG_ANT_A_MSK)) == 0);
947 if (error)
948 IWL_WARNING("check antenna %d %d\n", counter++, error);
949
950 if (error)
951 IWL_WARNING("Tuning to channel %d\n",
952 le16_to_cpu(rxon->channel));
953
954 if (error) {
bb8c093b 955 IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
b481de9c
ZY		 956 return -1;
957 }
958 return 0;
959}
960
961/**
9fbab516 962 * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
01ebd063 963 * @priv: staging_rxon is compared to active_rxon
b481de9c 964 *
9fbab516
BC		 965 * If the RXON structure is changing enough to require a new tune,
966 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
967 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
b481de9c 968 */
bb8c093b 969static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
b481de9c
ZY		 970{
971
972 /* These items are only settable from the full RXON command */
5d1e2325 973 if (!(iwl3945_is_associated(priv)) ||
b481de9c
ZY		 974 compare_ether_addr(priv->staging_rxon.bssid_addr,
975 priv->active_rxon.bssid_addr) ||
976 compare_ether_addr(priv->staging_rxon.node_addr,
977 priv->active_rxon.node_addr) ||
978 compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
979 priv->active_rxon.wlap_bssid_addr) ||
980 (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
981 (priv->staging_rxon.channel != priv->active_rxon.channel) ||
982 (priv->staging_rxon.air_propagation !=
983 priv->active_rxon.air_propagation) ||
984 (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
985 return 1;
986
987 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
988 * be updated with the RXON_ASSOC command -- however only some
989 * flag transitions are allowed using RXON_ASSOC */
990
991 /* Check if we are not switching bands */
992 if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
993 (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
994 return 1;
995
996 /* Check if we are switching association toggle */
997 if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
998 (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
999 return 1;
1000
1001 return 0;
1002}
1003
bb8c093b 1004static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
b481de9c
ZY		 1005{
1006 int rc = 0;
bb8c093b
CH		 1007 struct iwl3945_rx_packet *res = NULL;
1008 struct iwl3945_rxon_assoc_cmd rxon_assoc;
1009 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 1010 .id = REPLY_RXON_ASSOC,
1011 .len = sizeof(rxon_assoc),
1012 .meta.flags = CMD_WANT_SKB,
1013 .data = &rxon_assoc,
1014 };
bb8c093b
CH		 1015 const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
1016 const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
b481de9c
ZY		 1017
1018 if ((rxon1->flags == rxon2->flags) &&
1019 (rxon1->filter_flags == rxon2->filter_flags) &&
1020 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1021 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1022 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
1023 return 0;
1024 }
1025
1026 rxon_assoc.flags = priv->staging_rxon.flags;
1027 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1028 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1029 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1030 rxon_assoc.reserved = 0;
1031
bb8c093b 1032 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 1033 if (rc)
1034 return rc;
1035
bb8c093b 1036 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1037 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1038 IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
1039 rc = -EIO;
1040 }
1041
1042 priv->alloc_rxb_skb--;
1043 dev_kfree_skb_any(cmd.meta.u.skb);
1044
1045 return rc;
1046}
1047
1048/**
bb8c093b 1049 * iwl3945_commit_rxon - commit staging_rxon to hardware
b481de9c 1050 *
01ebd063 1051 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
ZY		 1052 * the active_rxon structure is updated with the new data. This
1053 * function correctly transitions out of the RXON_ASSOC_MSK state if
1054 * a HW tune is required based on the RXON structure changes.
1055 */
bb8c093b 1056static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
b481de9c
ZY		 1057{
1058 /* cast away the const for active_rxon in this function */
bb8c093b 1059 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
b481de9c 1060 int rc = 0;
0795af57 1061 DECLARE_MAC_BUF(mac);
b481de9c 1062
bb8c093b 1063 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 1064 return -1;
1065
1066 /* always get timestamp with Rx frame */
1067 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
1068
1069 /* select antenna */
1070 priv->staging_rxon.flags &=
1071 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1072 priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
1073
bb8c093b 1074 rc = iwl3945_check_rxon_cmd(&priv->staging_rxon);
b481de9c
ZY		 1075 if (rc) {
1076 IWL_ERROR("Invalid RXON configuration. Not committing.\n");
1077 return -EINVAL;
1078 }
1079
1080 /* If we don't need to send a full RXON, we can use
bb8c093b 1081 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 1082 * and other flags for the current radio configuration. */
bb8c093b
CH		 1083 if (!iwl3945_full_rxon_required(priv)) {
1084 rc = iwl3945_send_rxon_assoc(priv);
b481de9c
ZY		 1085 if (rc) {
1086 IWL_ERROR("Error setting RXON_ASSOC "
1087 "configuration (%d).\n", rc);
1088 return rc;
1089 }
1090
1091 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1092
1093 return 0;
1094 }
1095
1096 /* If we are currently associated and the new config requires
1097 * an RXON_ASSOC and the new config wants the associated mask enabled,
1098 * we must clear the associated from the active configuration
1099 * before we apply the new config */
bb8c093b 1100 if (iwl3945_is_associated(priv) &&
b481de9c
ZY		 1101 (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
1102 IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
1103 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1104
bb8c093b
CH		 1105 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
1106 sizeof(struct iwl3945_rxon_cmd),
b481de9c
ZY		 1107 &priv->active_rxon);
1108
1109 /* If the mask clearing failed then we set
1110 * active_rxon back to what it was previously */
1111 if (rc) {
1112 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1113 IWL_ERROR("Error clearing ASSOC_MSK on current "
1114 "configuration (%d).\n", rc);
1115 return rc;
1116 }
b481de9c
ZY		 1117 }
1118
1119 IWL_DEBUG_INFO("Sending RXON\n"
1120 "* with%s RXON_FILTER_ASSOC_MSK\n"
1121 "* channel = %d\n"
0795af57 1122 "* bssid = %s\n",
b481de9c
ZY		 1123 ((priv->staging_rxon.filter_flags &
1124 RXON_FILTER_ASSOC_MSK) ? "" : "out"),
1125 le16_to_cpu(priv->staging_rxon.channel),
0795af57 1126 print_mac(mac, priv->staging_rxon.bssid_addr));
b481de9c
ZY		 1127
1128 /* Apply the new configuration */
bb8c093b
CH		 1129 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
1130 sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
b481de9c
ZY		 1131 if (rc) {
1132 IWL_ERROR("Error setting new configuration (%d).\n", rc);
1133 return rc;
1134 }
1135
1136 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1137
bb8c093b 1138 iwl3945_clear_stations_table(priv);
556f8db7 1139
b481de9c
ZY		 1140 /* If we issue a new RXON command which required a tune then we must
1141 * send a new TXPOWER command or we won't be able to Tx any frames */
bb8c093b 1142 rc = iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 1143 if (rc) {
1144 IWL_ERROR("Error setting Tx power (%d).\n", rc);
1145 return rc;
1146 }
1147
1148 /* Add the broadcast address so we can send broadcast frames */
bb8c093b 1149 if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
b481de9c
ZY		 1150 IWL_INVALID_STATION) {
1151 IWL_ERROR("Error adding BROADCAST address for transmit.\n");
1152 return -EIO;
1153 }
1154
1155 /* If we have set the ASSOC_MSK and we are in BSS mode then
1156 * add the IWL_AP_ID to the station rate table */
bb8c093b 1157 if (iwl3945_is_associated(priv) &&
b481de9c 1158 (priv->iw_mode == IEEE80211_IF_TYPE_STA))
bb8c093b 1159 if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
b481de9c
ZY		 1160 == IWL_INVALID_STATION) {
1161 IWL_ERROR("Error adding AP address for transmit.\n");
1162 return -EIO;
1163 }
1164
8318d78a 1165 /* Init the hardware's rate fallback order based on the band */
b481de9c
ZY		 1166 rc = iwl3945_init_hw_rate_table(priv);
1167 if (rc) {
1168 IWL_ERROR("Error setting HW rate table: %02X\n", rc);
1169 return -EIO;
1170 }
1171
1172 return 0;
1173}
1174
bb8c093b 1175static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
b481de9c 1176{
bb8c093b 1177 struct iwl3945_bt_cmd bt_cmd = {
b481de9c
ZY		 1178 .flags = 3,
1179 .lead_time = 0xAA,
1180 .max_kill = 1,
1181 .kill_ack_mask = 0,
1182 .kill_cts_mask = 0,
1183 };
1184
bb8c093b
CH		 1185 return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1186 sizeof(struct iwl3945_bt_cmd), &bt_cmd);
b481de9c
ZY		 1187}
1188
bb8c093b 1189static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
b481de9c
ZY		 1190{
1191 int rc = 0;
bb8c093b
CH		 1192 struct iwl3945_rx_packet *res;
1193 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 1194 .id = REPLY_SCAN_ABORT_CMD,
1195 .meta.flags = CMD_WANT_SKB,
1196 };
1197
1198 /* If there isn't a scan actively going on in the hardware
1199 * then we are in between scan bands and not actually
1200 * actively scanning, so don't send the abort command */
1201 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
1202 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1203 return 0;
1204 }
1205
bb8c093b 1206 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 1207 if (rc) {
1208 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1209 return rc;
1210 }
1211
bb8c093b 1212 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1213 if (res->u.status != CAN_ABORT_STATUS) {
1214 /* The scan abort will return 1 for success or
1215 * 2 for "failure". A failure condition can be
1216 * due to simply not being in an active scan which
1217 * can occur if we send the scan abort before we
1218 * the microcode has notified us that a scan is
1219 * completed. */
1220 IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
1221 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1222 clear_bit(STATUS_SCAN_HW, &priv->status);
1223 }
1224
1225 dev_kfree_skb_any(cmd.meta.u.skb);
1226
1227 return rc;
1228}
1229
bb8c093b
CH		 1230static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
1231 struct iwl3945_cmd *cmd,
b481de9c
ZY		 1232 struct sk_buff *skb)
1233{
1234 return 1;
1235}
1236
1237/*
1238 * CARD_STATE_CMD
1239 *
9fbab516 1240 * Use: Sets the device's internal card state to enable, disable, or halt
b481de9c
ZY		 1241 *
1242 * When in the 'enable' state the card operates as normal.
1243 * When in the 'disable' state, the card enters into a low power mode.
1244 * When in the 'halt' state, the card is shut down and must be fully
1245 * restarted to come back on.
1246 */
bb8c093b 1247static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
b481de9c 1248{
bb8c093b 1249 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 1250 .id = REPLY_CARD_STATE_CMD,
1251 .len = sizeof(u32),
1252 .data = &flags,
1253 .meta.flags = meta_flag,
1254 };
1255
1256 if (meta_flag & CMD_ASYNC)
bb8c093b 1257 cmd.meta.u.callback = iwl3945_card_state_sync_callback;
b481de9c 1258
bb8c093b 1259 return iwl3945_send_cmd(priv, &cmd);
b481de9c
ZY		 1260}
1261
bb8c093b
CH		 1262static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
1263 struct iwl3945_cmd *cmd, struct sk_buff *skb)
b481de9c 1264{
bb8c093b 1265 struct iwl3945_rx_packet *res = NULL;
b481de9c
ZY		 1266
1267 if (!skb) {
1268 IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
1269 return 1;
1270 }
1271
bb8c093b 1272 res = (struct iwl3945_rx_packet *)skb->data;
b481de9c
ZY		 1273 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1274 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1275 res->hdr.flags);
1276 return 1;
1277 }
1278
1279 switch (res->u.add_sta.status) {
1280 case ADD_STA_SUCCESS_MSK:
1281 break;
1282 default:
1283 break;
1284 }
1285
1286 /* We didn't cache the SKB; let the caller free it */
1287 return 1;
1288}
1289
bb8c093b
CH		 1290int iwl3945_send_add_station(struct iwl3945_priv *priv,
1291 struct iwl3945_addsta_cmd *sta, u8 flags)
b481de9c 1292{
bb8c093b 1293 struct iwl3945_rx_packet *res = NULL;
b481de9c 1294 int rc = 0;
bb8c093b 1295 struct iwl3945_host_cmd cmd = {
b481de9c 1296 .id = REPLY_ADD_STA,
bb8c093b 1297 .len = sizeof(struct iwl3945_addsta_cmd),
b481de9c
ZY		 1298 .meta.flags = flags,
1299 .data = sta,
1300 };
1301
1302 if (flags & CMD_ASYNC)
bb8c093b 1303 cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
b481de9c
ZY		 1304 else
1305 cmd.meta.flags |= CMD_WANT_SKB;
1306
bb8c093b 1307 rc = iwl3945_send_cmd(priv, &cmd);
b481de9c
ZY		 1308
1309 if (rc || (flags & CMD_ASYNC))
1310 return rc;
1311
bb8c093b 1312 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1313 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1314 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1315 res->hdr.flags);
1316 rc = -EIO;
1317 }
1318
1319 if (rc == 0) {
1320 switch (res->u.add_sta.status) {
1321 case ADD_STA_SUCCESS_MSK:
1322 IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
1323 break;
1324 default:
1325 rc = -EIO;
1326 IWL_WARNING("REPLY_ADD_STA failed\n");
1327 break;
1328 }
1329 }
1330
1331 priv->alloc_rxb_skb--;
1332 dev_kfree_skb_any(cmd.meta.u.skb);
1333
1334 return rc;
1335}
1336
bb8c093b 1337static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
b481de9c
ZY		 1338 struct ieee80211_key_conf *keyconf,
1339 u8 sta_id)
1340{
1341 unsigned long flags;
1342 __le16 key_flags = 0;
1343
1344 switch (keyconf->alg) {
1345 case ALG_CCMP:
1346 key_flags |= STA_KEY_FLG_CCMP;
1347 key_flags |= cpu_to_le16(
1348 keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
1349 key_flags &= ~STA_KEY_FLG_INVALID;
1350 break;
1351 case ALG_TKIP:
1352 case ALG_WEP:
b481de9c
ZY		 1353 default:
1354 return -EINVAL;
1355 }
1356 spin_lock_irqsave(&priv->sta_lock, flags);
1357 priv->stations[sta_id].keyinfo.alg = keyconf->alg;
1358 priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
1359 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
1360 keyconf->keylen);
1361
1362 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
1363 keyconf->keylen);
1364 priv->stations[sta_id].sta.key.key_flags = key_flags;
1365 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1366 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1367
1368 spin_unlock_irqrestore(&priv->sta_lock, flags);
1369
1370 IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
bb8c093b 1371 iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY		 1372 return 0;
1373}
1374
bb8c093b 1375static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
b481de9c
ZY		 1376{
1377 unsigned long flags;
1378
1379 spin_lock_irqsave(&priv->sta_lock, flags);
bb8c093b
CH		 1380 memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
1381 memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl3945_keyinfo));
b481de9c
ZY		 1382 priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
1383 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1384 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1385 spin_unlock_irqrestore(&priv->sta_lock, flags);
1386
1387 IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
bb8c093b 1388 iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY		 1389 return 0;
1390}
1391
bb8c093b 1392static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
b481de9c
ZY		 1393{
1394 struct list_head *element;
1395
1396 IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
1397 priv->frames_count);
1398
1399 while (!list_empty(&priv->free_frames)) {
1400 element = priv->free_frames.next;
1401 list_del(element);
bb8c093b 1402 kfree(list_entry(element, struct iwl3945_frame, list));
b481de9c
ZY		 1403 priv->frames_count--;
1404 }
1405
1406 if (priv->frames_count) {
1407 IWL_WARNING("%d frames still in use. Did we lose one?\n",
1408 priv->frames_count);
1409 priv->frames_count = 0;
1410 }
1411}
1412
bb8c093b 1413static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
b481de9c 1414{
bb8c093b 1415 struct iwl3945_frame *frame;
b481de9c
ZY		 1416 struct list_head *element;
1417 if (list_empty(&priv->free_frames)) {
1418 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
1419 if (!frame) {
1420 IWL_ERROR("Could not allocate frame!\n");
1421 return NULL;
1422 }
1423
1424 priv->frames_count++;
1425 return frame;
1426 }
1427
1428 element = priv->free_frames.next;
1429 list_del(element);
bb8c093b 1430 return list_entry(element, struct iwl3945_frame, list);
b481de9c
ZY		 1431}
1432
bb8c093b 1433static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
b481de9c
ZY		 1434{
1435 memset(frame, 0, sizeof(*frame));
1436 list_add(&frame->list, &priv->free_frames);
1437}
1438
bb8c093b 1439unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
b481de9c
ZY		 1440 struct ieee80211_hdr *hdr,
1441 const u8 *dest, int left)
1442{
1443
bb8c093b 1444 if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
b481de9c
ZY		 1445 ((priv->iw_mode != IEEE80211_IF_TYPE_IBSS) &&
1446 (priv->iw_mode != IEEE80211_IF_TYPE_AP)))
1447 return 0;
1448
1449 if (priv->ibss_beacon->len > left)
1450 return 0;
1451
1452 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
1453
1454 return priv->ibss_beacon->len;
1455}
1456
bb8c093b 1457static u8 iwl3945_rate_get_lowest_plcp(int rate_mask)
b481de9c
ZY		 1458{
1459 u8 i;
1460
1461 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
bb8c093b 1462 i = iwl3945_rates[i].next_ieee) {
b481de9c 1463 if (rate_mask & (1 << i))
bb8c093b 1464 return iwl3945_rates[i].plcp;
b481de9c
ZY		 1465 }
1466
1467 return IWL_RATE_INVALID;
1468}
1469
bb8c093b 1470static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
b481de9c 1471{
bb8c093b 1472 struct iwl3945_frame *frame;
b481de9c
ZY		 1473 unsigned int frame_size;
1474 int rc;
1475 u8 rate;
1476
bb8c093b 1477 frame = iwl3945_get_free_frame(priv);
b481de9c
ZY		 1478
1479 if (!frame) {
1480 IWL_ERROR("Could not obtain free frame buffer for beacon "
1481 "command.\n");
1482 return -ENOMEM;
1483 }
1484
1485 if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) {
bb8c093b 1486 rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic &
b481de9c
ZY		 1487 0xFF0);
1488 if (rate == IWL_INVALID_RATE)
1489 rate = IWL_RATE_6M_PLCP;
1490 } else {
bb8c093b 1491 rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic & 0xF);
b481de9c
ZY		 1492 if (rate == IWL_INVALID_RATE)
1493 rate = IWL_RATE_1M_PLCP;
1494 }
1495
bb8c093b 1496 frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 1497
bb8c093b 1498 rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY		 1499 &frame->u.cmd[0]);
1500
bb8c093b 1501 iwl3945_free_frame(priv, frame);
b481de9c
ZY		 1502
1503 return rc;
1504}
1505
1506/******************************************************************************
1507 *
1508 * EEPROM related functions
1509 *
1510 ******************************************************************************/
1511
bb8c093b 1512static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
b481de9c
ZY		 1513{
1514 memcpy(mac, priv->eeprom.mac_address, 6);
1515}
1516
74a3a250
RC		 1517/*
1518 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
1519 * embedded controller) as EEPROM reader; each read is a series of pulses
1520 * to/from the EEPROM chip, not a single event, so even reads could conflict
1521 * if they weren't arbitrated by some ownership mechanism. Here, the driver
1522 * simply claims ownership, which should be safe when this function is called
1523 * (i.e. before loading uCode!).
1524 */
1525static inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv)
1526{
1527 _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
1528 return 0;
1529}
1530
b481de9c 1531/**
bb8c093b 1532 * iwl3945_eeprom_init - read EEPROM contents
b481de9c 1533 *
6440adb5 1534 * Load the EEPROM contents from adapter into priv->eeprom
b481de9c
ZY		 1535 *
1536 * NOTE: This routine uses the non-debug IO access functions.
1537 */
bb8c093b 1538int iwl3945_eeprom_init(struct iwl3945_priv *priv)
b481de9c 1539{
58ff6d4d 1540 u16 *e = (u16 *)&priv->eeprom;
bb8c093b 1541 u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
b481de9c
ZY		 1542 u32 r;
1543 int sz = sizeof(priv->eeprom);
1544 int rc;
1545 int i;
1546 u16 addr;
1547
1548 /* The EEPROM structure has several padding buffers within it
1549 * and when adding new EEPROM maps is subject to programmer errors
1550 * which may be very difficult to identify without explicitly
1551 * checking the resulting size of the eeprom map. */
1552 BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
1553
1554 if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
1555 IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp);
1556 return -ENOENT;
1557 }
1558
6440adb5 1559 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
bb8c093b 1560 rc = iwl3945_eeprom_acquire_semaphore(priv);
b481de9c 1561 if (rc < 0) {
91e17473 1562 IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
b481de9c
ZY		 1563 return -ENOENT;
1564 }
1565
1566 /* eeprom is an array of 16bit values */
1567 for (addr = 0; addr < sz; addr += sizeof(u16)) {
bb8c093b
CH		 1568 _iwl3945_write32(priv, CSR_EEPROM_REG, addr << 1);
1569 _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
b481de9c
ZY		 1570
1571 for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
1572 i += IWL_EEPROM_ACCESS_DELAY) {
bb8c093b 1573 r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
b481de9c
ZY		 1574 if (r & CSR_EEPROM_REG_READ_VALID_MSK)
1575 break;
1576 udelay(IWL_EEPROM_ACCESS_DELAY);
1577 }
1578
1579 if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) {
1580 IWL_ERROR("Time out reading EEPROM[%d]", addr);
1581 return -ETIMEDOUT;
1582 }
58ff6d4d 1583 e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
b481de9c
ZY		 1584 }
1585
1586 return 0;
1587}
1588
bb8c093b 1589static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
b481de9c
ZY		 1590{
1591 if (priv->hw_setting.shared_virt)
1592 pci_free_consistent(priv->pci_dev,
bb8c093b 1593 sizeof(struct iwl3945_shared),
b481de9c
ZY		 1594 priv->hw_setting.shared_virt,
1595 priv->hw_setting.shared_phys);
1596}
1597
1598/**
bb8c093b 1599 * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
b481de9c
ZY		 1600 *
1601 * return : set the bit for each supported rate insert in ie
1602 */
bb8c093b 1603static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
c7c46676 1604 u16 basic_rate, int *left)
b481de9c
ZY		 1605{
1606 u16 ret_rates = 0, bit;
1607 int i;
c7c46676
TW		 1608 u8 *cnt = ie;
1609 u8 *rates = ie + 1;
b481de9c
ZY		 1610
1611 for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
1612 if (bit & supported_rate) {
1613 ret_rates |= bit;
bb8c093b 1614 rates[*cnt] = iwl3945_rates[i].ieee |
c7c46676
TW		 1615 ((bit & basic_rate) ? 0x80 : 0x00);
1616 (*cnt)++;
1617 (*left)--;
1618 if ((*left <= 0) ||
1619 (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
b481de9c
ZY		 1620 break;
1621 }
1622 }
1623
1624 return ret_rates;
1625}
1626
1627/**
bb8c093b 1628 * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
b481de9c 1629 */
bb8c093b 1630static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
b481de9c
ZY		 1631 struct ieee80211_mgmt *frame,
1632 int left, int is_direct)
1633{
1634 int len = 0;
1635 u8 *pos = NULL;
c7c46676 1636 u16 active_rates, ret_rates, cck_rates;
b481de9c
ZY		 1637
1638 /* Make sure there is enough space for the probe request,
1639 * two mandatory IEs and the data */
1640 left -= 24;
1641 if (left < 0)
1642 return 0;
1643 len += 24;
1644
1645 frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
bb8c093b 1646 memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
b481de9c 1647 memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
bb8c093b 1648 memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
b481de9c
ZY		 1649 frame->seq_ctrl = 0;
1650
1651 /* fill in our indirect SSID IE */
1652 /* ...next IE... */
1653
1654 left -= 2;
1655 if (left < 0)
1656 return 0;
1657 len += 2;
1658 pos = &(frame->u.probe_req.variable[0]);
1659 *pos++ = WLAN_EID_SSID;
1660 *pos++ = 0;
1661
1662 /* fill in our direct SSID IE... */
1663 if (is_direct) {
1664 /* ...next IE... */
1665 left -= 2 + priv->essid_len;
1666 if (left < 0)
1667 return 0;
1668 /* ... fill it in... */
1669 *pos++ = WLAN_EID_SSID;
1670 *pos++ = priv->essid_len;
1671 memcpy(pos, priv->essid, priv->essid_len);
1672 pos += priv->essid_len;
1673 len += 2 + priv->essid_len;
1674 }
1675
1676 /* fill in supported rate */
1677 /* ...next IE... */
1678 left -= 2;
1679 if (left < 0)
1680 return 0;
c7c46676 1681
b481de9c
ZY		 1682 /* ... fill it in... */
1683 *pos++ = WLAN_EID_SUPP_RATES;
1684 *pos = 0;
c7c46676
TW		 1685
1686 priv->active_rate = priv->rates_mask;
1687 active_rates = priv->active_rate;
b481de9c
ZY		 1688 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1689
c7c46676 1690 cck_rates = IWL_CCK_RATES_MASK & active_rates;
bb8c093b 1691 ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
c7c46676
TW		 1692 priv->active_rate_basic, &left);
1693 active_rates &= ~ret_rates;
1694
bb8c093b 1695 ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676
TW		 1696 priv->active_rate_basic, &left);
1697 active_rates &= ~ret_rates;
1698
b481de9c
ZY		 1699 len += 2 + *pos;
1700 pos += (*pos) + 1;
c7c46676 1701 if (active_rates == 0)
b481de9c
ZY		 1702 goto fill_end;
1703
1704 /* fill in supported extended rate */
1705 /* ...next IE... */
1706 left -= 2;
1707 if (left < 0)
1708 return 0;
1709 /* ... fill it in... */
1710 *pos++ = WLAN_EID_EXT_SUPP_RATES;
1711 *pos = 0;
bb8c093b 1712 iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676 1713 priv->active_rate_basic, &left);
b481de9c
ZY		 1714 if (*pos > 0)
1715 len += 2 + *pos;
1716
1717 fill_end:
1718 return (u16)len;
1719}
1720
1721/*
1722 * QoS support
1723*/
bb8c093b
CH		 1724static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
1725 struct iwl3945_qosparam_cmd *qos)
b481de9c
ZY		 1726{
1727
bb8c093b
CH		 1728 return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
1729 sizeof(struct iwl3945_qosparam_cmd), qos);
b481de9c
ZY		 1730}
1731
bb8c093b 1732static void iwl3945_reset_qos(struct iwl3945_priv *priv)
b481de9c
ZY		 1733{
1734 u16 cw_min = 15;
1735 u16 cw_max = 1023;
1736 u8 aifs = 2;
1737 u8 is_legacy = 0;
1738 unsigned long flags;
1739 int i;
1740
1741 spin_lock_irqsave(&priv->lock, flags);
1742 priv->qos_data.qos_active = 0;
1743
1744 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
1745 if (priv->qos_data.qos_enable)
1746 priv->qos_data.qos_active = 1;
1747 if (!(priv->active_rate & 0xfff0)) {
1748 cw_min = 31;
1749 is_legacy = 1;
1750 }
1751 } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
1752 if (priv->qos_data.qos_enable)
1753 priv->qos_data.qos_active = 1;
1754 } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
1755 cw_min = 31;
1756 is_legacy = 1;
1757 }
1758
1759 if (priv->qos_data.qos_active)
1760 aifs = 3;
1761
1762 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
1763 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
1764 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
1765 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
1766 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
1767
1768 if (priv->qos_data.qos_active) {
1769 i = 1;
1770 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
1771 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
1772 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
1773 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
1774 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1775
1776 i = 2;
1777 priv->qos_data.def_qos_parm.ac[i].cw_min =
1778 cpu_to_le16((cw_min + 1) / 2 - 1);
1779 priv->qos_data.def_qos_parm.ac[i].cw_max =
1780 cpu_to_le16(cw_max);
1781 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1782 if (is_legacy)
1783 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1784 cpu_to_le16(6016);
1785 else
1786 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1787 cpu_to_le16(3008);
1788 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1789
1790 i = 3;
1791 priv->qos_data.def_qos_parm.ac[i].cw_min =
1792 cpu_to_le16((cw_min + 1) / 4 - 1);
1793 priv->qos_data.def_qos_parm.ac[i].cw_max =
1794 cpu_to_le16((cw_max + 1) / 2 - 1);
1795 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1796 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1797 if (is_legacy)
1798 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1799 cpu_to_le16(3264);
1800 else
1801 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1802 cpu_to_le16(1504);
1803 } else {
1804 for (i = 1; i < 4; i++) {
1805 priv->qos_data.def_qos_parm.ac[i].cw_min =
1806 cpu_to_le16(cw_min);
1807 priv->qos_data.def_qos_parm.ac[i].cw_max =
1808 cpu_to_le16(cw_max);
1809 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
1810 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
1811 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1812 }
1813 }
1814 IWL_DEBUG_QOS("set QoS to default \n");
1815
1816 spin_unlock_irqrestore(&priv->lock, flags);
1817}
1818
bb8c093b 1819static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
b481de9c
ZY		 1820{
1821 unsigned long flags;
1822
b481de9c
ZY		 1823 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1824 return;
1825
1826 if (!priv->qos_data.qos_enable)
1827 return;
1828
1829 spin_lock_irqsave(&priv->lock, flags);
1830 priv->qos_data.def_qos_parm.qos_flags = 0;
1831
1832 if (priv->qos_data.qos_cap.q_AP.queue_request &&
1833 !priv->qos_data.qos_cap.q_AP.txop_request)
1834 priv->qos_data.def_qos_parm.qos_flags |=
1835 QOS_PARAM_FLG_TXOP_TYPE_MSK;
1836
1837 if (priv->qos_data.qos_active)
1838 priv->qos_data.def_qos_parm.qos_flags |=
1839 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
1840
1841 spin_unlock_irqrestore(&priv->lock, flags);
1842
bb8c093b 1843 if (force || iwl3945_is_associated(priv)) {
b481de9c
ZY		 1844 IWL_DEBUG_QOS("send QoS cmd with Qos active %d \n",
1845 priv->qos_data.qos_active);
1846
bb8c093b 1847 iwl3945_send_qos_params_command(priv,
b481de9c
ZY		 1848 &(priv->qos_data.def_qos_parm));
1849 }
1850}
1851
b481de9c
ZY		 1852/*
1853 * Power management (not Tx power!) functions
1854 */
1855#define MSEC_TO_USEC 1024
1856
1857#define NOSLP __constant_cpu_to_le32(0)
1858#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK
1859#define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
1860#define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
1861 __constant_cpu_to_le32(X1), \
1862 __constant_cpu_to_le32(X2), \
1863 __constant_cpu_to_le32(X3), \
1864 __constant_cpu_to_le32(X4)}
1865
1866
1867/* default power management (not Tx power) table values */
1868/* for tim 0-10 */
bb8c093b 1869static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = {
b481de9c
ZY		 1870 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1871 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
1872 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
1873 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
1874 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
1875 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
1876};
1877
1878/* for tim > 10 */
bb8c093b 1879static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = {
b481de9c
ZY		 1880 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1881 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
1882 SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
1883 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
1884 SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
1885 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
1886 SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
1887 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
1888 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
1889 SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
1890};
1891
bb8c093b 1892int iwl3945_power_init_handle(struct iwl3945_priv *priv)
b481de9c
ZY		 1893{
1894 int rc = 0, i;
bb8c093b
CH		 1895 struct iwl3945_power_mgr *pow_data;
1896 int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC;
b481de9c
ZY		 1897 u16 pci_pm;
1898
1899 IWL_DEBUG_POWER("Initialize power \n");
1900
1901 pow_data = &(priv->power_data);
1902
1903 memset(pow_data, 0, sizeof(*pow_data));
1904
1905 pow_data->active_index = IWL_POWER_RANGE_0;
1906 pow_data->dtim_val = 0xffff;
1907
1908 memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
1909 memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
1910
1911 rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
1912 if (rc != 0)
1913 return 0;
1914 else {
bb8c093b 1915 struct iwl3945_powertable_cmd *cmd;
b481de9c
ZY		 1916
1917 IWL_DEBUG_POWER("adjust power command flags\n");
1918
1919 for (i = 0; i < IWL_POWER_AC; i++) {
1920 cmd = &pow_data->pwr_range_0[i].cmd;
1921
1922 if (pci_pm & 0x1)
1923 cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
1924 else
1925 cmd->flags |= IWL_POWER_PCI_PM_MSK;
1926 }
1927 }
1928 return rc;
1929}
1930
bb8c093b
CH		 1931static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
1932 struct iwl3945_powertable_cmd *cmd, u32 mode)
b481de9c
ZY		 1933{
1934 int rc = 0, i;
1935 u8 skip;
1936 u32 max_sleep = 0;
bb8c093b 1937 struct iwl3945_power_vec_entry *range;
b481de9c 1938 u8 period = 0;
bb8c093b 1939 struct iwl3945_power_mgr *pow_data;
b481de9c
ZY		 1940
1941 if (mode > IWL_POWER_INDEX_5) {
1942 IWL_DEBUG_POWER("Error invalid power mode \n");
1943 return -1;
1944 }
1945 pow_data = &(priv->power_data);
1946
1947 if (pow_data->active_index == IWL_POWER_RANGE_0)
1948 range = &pow_data->pwr_range_0[0];
1949 else
1950 range = &pow_data->pwr_range_1[1];
1951
bb8c093b 1952 memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
b481de9c
ZY		 1953
1954#ifdef IWL_MAC80211_DISABLE
1955 if (priv->assoc_network != NULL) {
1956 unsigned long flags;
1957
1958 period = priv->assoc_network->tim.tim_period;
1959 }
1960#endif /*IWL_MAC80211_DISABLE */
1961 skip = range[mode].no_dtim;
1962
1963 if (period == 0) {
1964 period = 1;
1965 skip = 0;
1966 }
1967
1968 if (skip == 0) {
1969 max_sleep = period;
1970 cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
1971 } else {
1972 __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
1973 max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
1974 cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
1975 }
1976
1977 for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
1978 if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
1979 cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
1980 }
1981
1982 IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
1983 IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
1984 IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
1985 IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
1986 le32_to_cpu(cmd->sleep_interval[0]),
1987 le32_to_cpu(cmd->sleep_interval[1]),
1988 le32_to_cpu(cmd->sleep_interval[2]),
1989 le32_to_cpu(cmd->sleep_interval[3]),
1990 le32_to_cpu(cmd->sleep_interval[4]));
1991
1992 return rc;
1993}
1994
bb8c093b 1995static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
b481de9c 1996{
9a62f73b 1997 u32 uninitialized_var(final_mode);
b481de9c 1998 int rc;
bb8c093b 1999 struct iwl3945_powertable_cmd cmd;
b481de9c
ZY		 2000
2001 /* If on battery, set to 3,
01ebd063 2002 * if plugged into AC power, set to CAM ("continuously aware mode"),
b481de9c
ZY		 2003 * else user level */
2004 switch (mode) {
2005 case IWL_POWER_BATTERY:
2006 final_mode = IWL_POWER_INDEX_3;
2007 break;
2008 case IWL_POWER_AC:
2009 final_mode = IWL_POWER_MODE_CAM;
2010 break;
2011 default:
2012 final_mode = mode;
2013 break;
2014 }
2015
bb8c093b 2016 iwl3945_update_power_cmd(priv, &cmd, final_mode);
b481de9c 2017
bb8c093b 2018 rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
b481de9c
ZY		 2019
2020 if (final_mode == IWL_POWER_MODE_CAM)
2021 clear_bit(STATUS_POWER_PMI, &priv->status);
2022 else
2023 set_bit(STATUS_POWER_PMI, &priv->status);
2024
2025 return rc;
2026}
2027
bb8c093b 2028int iwl3945_is_network_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
b481de9c
ZY		 2029{
2030 /* Filter incoming packets to determine if they are targeted toward
2031 * this network, discarding packets coming from ourselves */
2032 switch (priv->iw_mode) {
2033 case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */
2034 /* packets from our adapter are dropped (echo) */
2035 if (!compare_ether_addr(header->addr2, priv->mac_addr))
2036 return 0;
2037 /* {broad,multi}cast packets to our IBSS go through */
2038 if (is_multicast_ether_addr(header->addr1))
2039 return !compare_ether_addr(header->addr3, priv->bssid);
2040 /* packets to our adapter go through */
2041 return !compare_ether_addr(header->addr1, priv->mac_addr);
2042 case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */
2043 /* packets from our adapter are dropped (echo) */
2044 if (!compare_ether_addr(header->addr3, priv->mac_addr))
2045 return 0;
2046 /* {broad,multi}cast packets to our BSS go through */
2047 if (is_multicast_ether_addr(header->addr1))
2048 return !compare_ether_addr(header->addr2, priv->bssid);
2049 /* packets to our adapter go through */
2050 return !compare_ether_addr(header->addr1, priv->mac_addr);
69dc5d9d
TW		 2051 default:
2052 return 1;
b481de9c
ZY		 2053 }
2054
2055 return 1;
2056}
2057
b481de9c 2058/**
bb8c093b 2059 * iwl3945_scan_cancel - Cancel any currently executing HW scan
b481de9c
ZY		 2060 *
2061 * NOTE: priv->mutex is not required before calling this function
2062 */
bb8c093b 2063static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
b481de9c
ZY		 2064{
2065 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
2066 clear_bit(STATUS_SCANNING, &priv->status);
2067 return 0;
2068 }
2069
2070 if (test_bit(STATUS_SCANNING, &priv->status)) {
2071 if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2072 IWL_DEBUG_SCAN("Queuing scan abort.\n");
2073 set_bit(STATUS_SCAN_ABORTING, &priv->status);
2074 queue_work(priv->workqueue, &priv->abort_scan);
2075
2076 } else
2077 IWL_DEBUG_SCAN("Scan abort already in progress.\n");
2078
2079 return test_bit(STATUS_SCANNING, &priv->status);
2080 }
2081
2082 return 0;
2083}
2084
2085/**
bb8c093b 2086 * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
b481de9c
ZY		 2087 * @ms: amount of time to wait (in milliseconds) for scan to abort
2088 *
2089 * NOTE: priv->mutex must be held before calling this function
2090 */
bb8c093b 2091static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
b481de9c
ZY		 2092{
2093 unsigned long now = jiffies;
2094 int ret;
2095
bb8c093b 2096 ret = iwl3945_scan_cancel(priv);
b481de9c
ZY		 2097 if (ret && ms) {
2098 mutex_unlock(&priv->mutex);
2099 while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
2100 test_bit(STATUS_SCANNING, &priv->status))
2101 msleep(1);
2102 mutex_lock(&priv->mutex);
2103
2104 return test_bit(STATUS_SCANNING, &priv->status);
2105 }
2106
2107 return ret;
2108}
2109
bb8c093b 2110static void iwl3945_sequence_reset(struct iwl3945_priv *priv)
b481de9c
ZY		 2111{
2112 /* Reset ieee stats */
2113
2114 /* We don't reset the net_device_stats (ieee->stats) on
2115 * re-association */
2116
2117 priv->last_seq_num = -1;
2118 priv->last_frag_num = -1;
2119 priv->last_packet_time = 0;
2120
bb8c093b 2121 iwl3945_scan_cancel(priv);
b481de9c
ZY		 2122}
2123
2124#define MAX_UCODE_BEACON_INTERVAL 1024
2125#define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
2126
bb8c093b 2127static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
b481de9c
ZY		 2128{
2129 u16 new_val = 0;
2130 u16 beacon_factor = 0;
2131
2132 beacon_factor =
2133 (beacon_val + MAX_UCODE_BEACON_INTERVAL)
2134 / MAX_UCODE_BEACON_INTERVAL;
2135 new_val = beacon_val / beacon_factor;
2136
2137 return cpu_to_le16(new_val);
2138}
2139
bb8c093b 2140static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
b481de9c
ZY		 2141{
2142 u64 interval_tm_unit;
2143 u64 tsf, result;
2144 unsigned long flags;
2145 struct ieee80211_conf *conf = NULL;
2146 u16 beacon_int = 0;
2147
2148 conf = ieee80211_get_hw_conf(priv->hw);
2149
2150 spin_lock_irqsave(&priv->lock, flags);
2151 priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
2152 priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
2153
2154 priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
2155
2156 tsf = priv->timestamp1;
2157 tsf = ((tsf << 32) | priv->timestamp0);
2158
2159 beacon_int = priv->beacon_int;
2160 spin_unlock_irqrestore(&priv->lock, flags);
2161
2162 if (priv->iw_mode == IEEE80211_IF_TYPE_STA) {
2163 if (beacon_int == 0) {
2164 priv->rxon_timing.beacon_interval = cpu_to_le16(100);
2165 priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
2166 } else {
2167 priv->rxon_timing.beacon_interval =
2168 cpu_to_le16(beacon_int);
2169 priv->rxon_timing.beacon_interval =
bb8c093b 2170 iwl3945_adjust_beacon_interval(
b481de9c
ZY		 2171 le16_to_cpu(priv->rxon_timing.beacon_interval));
2172 }
2173
2174 priv->rxon_timing.atim_window = 0;
2175 } else {
2176 priv->rxon_timing.beacon_interval =
bb8c093b 2177 iwl3945_adjust_beacon_interval(conf->beacon_int);
b481de9c
ZY		 2178 /* TODO: we need to get atim_window from upper stack
2179 * for now we set to 0 */
2180 priv->rxon_timing.atim_window = 0;
2181 }
2182
2183 interval_tm_unit =
2184 (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
2185 result = do_div(tsf, interval_tm_unit);
2186 priv->rxon_timing.beacon_init_val =
2187 cpu_to_le32((u32) ((u64) interval_tm_unit - result));
2188
2189 IWL_DEBUG_ASSOC
2190 ("beacon interval %d beacon timer %d beacon tim %d\n",
2191 le16_to_cpu(priv->rxon_timing.beacon_interval),
2192 le32_to_cpu(priv->rxon_timing.beacon_init_val),
2193 le16_to_cpu(priv->rxon_timing.atim_window));
2194}
2195
bb8c093b 2196static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
b481de9c
ZY		 2197{
2198 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
2199 IWL_ERROR("APs don't scan.\n");
2200 return 0;
2201 }
2202
bb8c093b 2203 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 2204 IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
2205 return -EIO;
2206 }
2207
2208 if (test_bit(STATUS_SCANNING, &priv->status)) {
2209 IWL_DEBUG_SCAN("Scan already in progress.\n");
2210 return -EAGAIN;
2211 }
2212
2213 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2214 IWL_DEBUG_SCAN("Scan request while abort pending. "
2215 "Queuing.\n");
2216 return -EAGAIN;
2217 }
2218
2219 IWL_DEBUG_INFO("Starting scan...\n");
66b5004d
RR		 2220 if (priv->cfg->sku & IWL_SKU_G)
2221 priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ);
2222 if (priv->cfg->sku & IWL_SKU_A)
2223 priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ);
b481de9c
ZY		 2224 set_bit(STATUS_SCANNING, &priv->status);
2225 priv->scan_start = jiffies;
2226 priv->scan_pass_start = priv->scan_start;
2227
2228 queue_work(priv->workqueue, &priv->request_scan);
2229
2230 return 0;
2231}
2232
bb8c093b 2233static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
b481de9c 2234{
bb8c093b 2235 struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
b481de9c
ZY		 2236
2237 if (hw_decrypt)
2238 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
2239 else
2240 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
2241
2242 return 0;
2243}
2244
8318d78a
JB		 2245static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv,
2246 enum ieee80211_band band)
b481de9c 2247{
8318d78a 2248 if (band == IEEE80211_BAND_5GHZ) {
b481de9c
ZY		 2249 priv->staging_rxon.flags &=
2250 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
2251 | RXON_FLG_CCK_MSK);
2252 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2253 } else {
bb8c093b 2254 /* Copied from iwl3945_bg_post_associate() */
b481de9c
ZY		 2255 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2256 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2257 else
2258 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2259
2260 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
2261 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2262
2263 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
2264 priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
2265 priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
2266 }
2267}
2268
2269/*
01ebd063 2270 * initialize rxon structure with default values from eeprom
b481de9c 2271 */
bb8c093b 2272static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv)
b481de9c 2273{
bb8c093b 2274 const struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 2275
2276 memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
2277
2278 switch (priv->iw_mode) {
2279 case IEEE80211_IF_TYPE_AP:
2280 priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
2281 break;
2282
2283 case IEEE80211_IF_TYPE_STA:
2284 priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
2285 priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
2286 break;
2287
2288 case IEEE80211_IF_TYPE_IBSS:
2289 priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
2290 priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
2291 priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
2292 RXON_FILTER_ACCEPT_GRP_MSK;
2293 break;
2294
2295 case IEEE80211_IF_TYPE_MNTR:
2296 priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
2297 priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
2298 RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
2299 break;
69dc5d9d
TW		 2300 default:
2301 IWL_ERROR("Unsupported interface type %d\n", priv->iw_mode);
2302 break;
b481de9c
ZY		 2303 }
2304
2305#if 0
2306 /* TODO: Figure out when short_preamble would be set and cache from
2307 * that */
2308 if (!hw_to_local(priv->hw)->short_preamble)
2309 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2310 else
2311 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2312#endif
2313
8318d78a 2314 ch_info = iwl3945_get_channel_info(priv, priv->band,
25b3f57c 2315 le16_to_cpu(priv->active_rxon.channel));
b481de9c
ZY		 2316
2317 if (!ch_info)
2318 ch_info = &priv->channel_info[0];
2319
2320 /*
2321 * in some case A channels are all non IBSS
2322 * in this case force B/G channel
2323 */
2324 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
2325 !(is_channel_ibss(ch_info)))
2326 ch_info = &priv->channel_info[0];
2327
2328 priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
2329 if (is_channel_a_band(ch_info))
8318d78a 2330 priv->band = IEEE80211_BAND_5GHZ;
b481de9c 2331 else
8318d78a 2332 priv->band = IEEE80211_BAND_2GHZ;
b481de9c 2333
8318d78a 2334 iwl3945_set_flags_for_phymode(priv, priv->band);
b481de9c
ZY		 2335
2336 priv->staging_rxon.ofdm_basic_rates =
2337 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2338 priv->staging_rxon.cck_basic_rates =
2339 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2340}
2341
bb8c093b 2342static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
b481de9c 2343{
b481de9c 2344 if (mode == IEEE80211_IF_TYPE_IBSS) {
bb8c093b 2345 const struct iwl3945_channel_info *ch_info;
b481de9c 2346
bb8c093b 2347 ch_info = iwl3945_get_channel_info(priv,
8318d78a 2348 priv->band,
b481de9c
ZY		 2349 le16_to_cpu(priv->staging_rxon.channel));
2350
2351 if (!ch_info || !is_channel_ibss(ch_info)) {
2352 IWL_ERROR("channel %d not IBSS channel\n",
2353 le16_to_cpu(priv->staging_rxon.channel));
2354 return -EINVAL;
2355 }
2356 }
2357
b481de9c
ZY		 2358 priv->iw_mode = mode;
2359
bb8c093b 2360 iwl3945_connection_init_rx_config(priv);
b481de9c
ZY		 2361 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2362
bb8c093b 2363 iwl3945_clear_stations_table(priv);
b481de9c 2364
fde3571f
MA		 2365 /* dont commit rxon if rf-kill is on*/
2366 if (!iwl3945_is_ready_rf(priv))
2367 return -EAGAIN;
2368
2369 cancel_delayed_work(&priv->scan_check);
2370 if (iwl3945_scan_cancel_timeout(priv, 100)) {
2371 IWL_WARNING("Aborted scan still in progress after 100ms\n");
2372 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
2373 return -EAGAIN;
2374 }
2375
bb8c093b 2376 iwl3945_commit_rxon(priv);
b481de9c
ZY		 2377
2378 return 0;
2379}
2380
bb8c093b 2381static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
e039fa4a 2382 struct ieee80211_tx_info *info,
bb8c093b 2383 struct iwl3945_cmd *cmd,
b481de9c
ZY		 2384 struct sk_buff *skb_frag,
2385 int last_frag)
2386{
1c014420 2387 struct iwl3945_hw_key *keyinfo =
e039fa4a 2388 &priv->stations[info->control.hw_key->hw_key_idx].keyinfo;
b481de9c
ZY		 2389
2390 switch (keyinfo->alg) {
2391 case ALG_CCMP:
2392 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
2393 memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
2394 IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
2395 break;
2396
2397 case ALG_TKIP:
2398#if 0
2399 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
2400
2401 if (last_frag)
2402 memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
2403 8);
2404 else
2405 memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
2406#endif
2407 break;
2408
2409 case ALG_WEP:
2410 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
e039fa4a 2411 (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
b481de9c
ZY		 2412
2413 if (keyinfo->keylen == 13)
2414 cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
2415
2416 memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
2417
2418 IWL_DEBUG_TX("Configuring packet for WEP encryption "
e039fa4a 2419 "with key %d\n", info->control.hw_key->hw_key_idx);
b481de9c
ZY		 2420 break;
2421
b481de9c
ZY		 2422 default:
2423 printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
2424 break;
2425 }
2426}
2427
2428/*
2429 * handle build REPLY_TX command notification.
2430 */
bb8c093b
CH		 2431static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
2432 struct iwl3945_cmd *cmd,
e039fa4a 2433 struct ieee80211_tx_info *info,
b481de9c
ZY		 2434 struct ieee80211_hdr *hdr,
2435 int is_unicast, u8 std_id)
2436{
fd7c8a40 2437 __le16 fc = hdr->frame_control;
b481de9c
ZY		 2438 __le32 tx_flags = cmd->cmd.tx.tx_flags;
2439
2440 cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e039fa4a 2441 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
b481de9c 2442 tx_flags |= TX_CMD_FLG_ACK_MSK;
fd7c8a40 2443 if (ieee80211_is_mgmt(fc))
b481de9c 2444 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
fd7c8a40 2445 if (ieee80211_is_probe_resp(fc) &&
b481de9c
ZY		 2446 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
2447 tx_flags |= TX_CMD_FLG_TSF_MSK;
2448 } else {
2449 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
2450 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2451 }
2452
2453 cmd->cmd.tx.sta_id = std_id;
8b7b1e05 2454 if (ieee80211_has_morefrags(fc))
b481de9c
ZY		 2455 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
2456
fd7c8a40
HH		 2457 if (ieee80211_is_data_qos(fc)) {
2458 u8 *qc = ieee80211_get_qos_ctl(hdr);
54dbb525 2459 cmd->cmd.tx.tid_tspec = qc[0] & 0xf;
b481de9c 2460 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 2461 } else {
b481de9c 2462 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 2463 }
b481de9c 2464
e039fa4a 2465 if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) {
b481de9c
ZY		 2466 tx_flags |= TX_CMD_FLG_RTS_MSK;
2467 tx_flags &= ~TX_CMD_FLG_CTS_MSK;
e039fa4a 2468 } else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) {
b481de9c
ZY		 2469 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2470 tx_flags |= TX_CMD_FLG_CTS_MSK;
2471 }
2472
2473 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
2474 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
2475
2476 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
fd7c8a40
HH		 2477 if (ieee80211_is_mgmt(fc)) {
2478 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
bc434dd2 2479 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
b481de9c 2480 else
bc434dd2 2481 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
ab53d8af 2482 } else {
b481de9c 2483 cmd->cmd.tx.timeout.pm_frame_timeout = 0;
ab53d8af
MA		 2484#ifdef CONFIG_IWL3945_LEDS
2485 priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
2486#endif
2487 }
b481de9c
ZY		 2488
2489 cmd->cmd.tx.driver_txop = 0;
2490 cmd->cmd.tx.tx_flags = tx_flags;
2491 cmd->cmd.tx.next_frame_len = 0;
2492}
2493
6440adb5
CB		 2494/**
2495 * iwl3945_get_sta_id - Find station's index within station table
2496 */
bb8c093b 2497static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
b481de9c
ZY		 2498{
2499 int sta_id;
2500 u16 fc = le16_to_cpu(hdr->frame_control);
2501
6440adb5 2502 /* If this frame is broadcast or management, use broadcast station id */
b481de9c
ZY		 2503 if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
2504 is_multicast_ether_addr(hdr->addr1))
2505 return priv->hw_setting.bcast_sta_id;
2506
2507 switch (priv->iw_mode) {
2508
6440adb5
CB		 2509 /* If we are a client station in a BSS network, use the special
2510 * AP station entry (that's the only station we communicate with) */
b481de9c
ZY		 2511 case IEEE80211_IF_TYPE_STA:
2512 return IWL_AP_ID;
2513
2514 /* If we are an AP, then find the station, or use BCAST */
2515 case IEEE80211_IF_TYPE_AP:
bb8c093b 2516 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY		 2517 if (sta_id != IWL_INVALID_STATION)
2518 return sta_id;
2519 return priv->hw_setting.bcast_sta_id;
2520
6440adb5
CB		 2521 /* If this frame is going out to an IBSS network, find the station,
2522 * or create a new station table entry */
0795af57
JP		 2523 case IEEE80211_IF_TYPE_IBSS: {
2524 DECLARE_MAC_BUF(mac);
2525
6440adb5 2526 /* Create new station table entry */
bb8c093b 2527 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY		 2528 if (sta_id != IWL_INVALID_STATION)
2529 return sta_id;
2530
bb8c093b 2531 sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
b481de9c
ZY		 2532
2533 if (sta_id != IWL_INVALID_STATION)
2534 return sta_id;
2535
0795af57 2536 IWL_DEBUG_DROP("Station %s not in station map. "
b481de9c 2537 "Defaulting to broadcast...\n",
0795af57 2538 print_mac(mac, hdr->addr1));
bb8c093b 2539 iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
b481de9c 2540 return priv->hw_setting.bcast_sta_id;
0795af57 2541 }
914233d6
SG		 2542 /* If we are in monitor mode, use BCAST. This is required for
2543 * packet injection. */
2544 case IEEE80211_IF_TYPE_MNTR:
2545 return priv->hw_setting.bcast_sta_id;
2546
b481de9c 2547 default:
01ebd063 2548 IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode);
b481de9c
ZY		 2549 return priv->hw_setting.bcast_sta_id;
2550 }
2551}
2552
2553/*
2554 * start REPLY_TX command process
2555 */
e039fa4a 2556static int iwl3945_tx_skb(struct iwl3945_priv *priv, struct sk_buff *skb)
b481de9c
ZY		 2557{
2558 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
e039fa4a 2559 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bb8c093b 2560 struct iwl3945_tfd_frame *tfd;
b481de9c 2561 u32 *control_flags;
e2530083 2562 int txq_id = skb_get_queue_mapping(skb);
bb8c093b
CH		 2563 struct iwl3945_tx_queue *txq = NULL;
2564 struct iwl3945_queue *q = NULL;
b481de9c
ZY		 2565 dma_addr_t phys_addr;
2566 dma_addr_t txcmd_phys;
bb8c093b 2567 struct iwl3945_cmd *out_cmd = NULL;
54dbb525
TW		 2568 u16 len, idx, len_org, hdr_len;
2569 u8 id;
2570 u8 unicast;
b481de9c 2571 u8 sta_id;
54dbb525 2572 u8 tid = 0;
b481de9c 2573 u16 seq_number = 0;
fd7c8a40 2574 __le16 fc;
b481de9c 2575 u8 wait_write_ptr = 0;
54dbb525 2576 u8 *qc = NULL;
b481de9c
ZY		 2577 unsigned long flags;
2578 int rc;
2579
2580 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2581 if (iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 2582 IWL_DEBUG_DROP("Dropping - RF KILL\n");
2583 goto drop_unlock;
2584 }
2585
e039fa4a 2586 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
b481de9c
ZY		 2587 IWL_ERROR("ERROR: No TX rate available.\n");
2588 goto drop_unlock;
2589 }
2590
2591 unicast = !is_multicast_ether_addr(hdr->addr1);
2592 id = 0;
2593
fd7c8a40 2594 fc = hdr->frame_control;
b481de9c 2595
c8b0e6e1 2596#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 2597 if (ieee80211_is_auth(fc))
2598 IWL_DEBUG_TX("Sending AUTH frame\n");
fd7c8a40 2599 else if (ieee80211_is_assoc_req(fc))
b481de9c 2600 IWL_DEBUG_TX("Sending ASSOC frame\n");
fd7c8a40 2601 else if (ieee80211_is_reassoc_req(fc))
b481de9c
ZY		 2602 IWL_DEBUG_TX("Sending REASSOC frame\n");
2603#endif
2604
7878a5a4 2605 /* drop all data frame if we are not associated */
914233d6
SG		 2606 if (ieee80211_is_data(fc) &&
2607 (priv->iw_mode != IEEE80211_IF_TYPE_MNTR) && /* packet injection */
2608 (!iwl3945_is_associated(priv) ||
2609 ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && !priv->assoc_id))) {
bb8c093b 2610 IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
b481de9c
ZY		 2611 goto drop_unlock;
2612 }
2613
2614 spin_unlock_irqrestore(&priv->lock, flags);
2615
fd7c8a40 2616 hdr_len = ieee80211_get_hdrlen(le16_to_cpu(fc));
6440adb5
CB		 2617
2618 /* Find (or create) index into station table for destination station */
bb8c093b 2619 sta_id = iwl3945_get_sta_id(priv, hdr);
b481de9c 2620 if (sta_id == IWL_INVALID_STATION) {
0795af57
JP		 2621 DECLARE_MAC_BUF(mac);
2622
2623 IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
2624 print_mac(mac, hdr->addr1));
b481de9c
ZY		 2625 goto drop;
2626 }
2627
2628 IWL_DEBUG_RATE("station Id %d\n", sta_id);
2629
fd7c8a40
HH		 2630 if (ieee80211_is_data_qos(fc)) {
2631 qc = ieee80211_get_qos_ctl(hdr);
54dbb525 2632 tid = qc[0] & 0xf;
b481de9c
ZY		 2633 seq_number = priv->stations[sta_id].tid[tid].seq_number &
2634 IEEE80211_SCTL_SEQ;
2635 hdr->seq_ctrl = cpu_to_le16(seq_number) |
2636 (hdr->seq_ctrl &
2637 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
2638 seq_number += 0x10;
2639 }
6440adb5
CB		 2640
2641 /* Descriptor for chosen Tx queue */
b481de9c
ZY		 2642 txq = &priv->txq[txq_id];
2643 q = &txq->q;
2644
2645 spin_lock_irqsave(&priv->lock, flags);
2646
6440adb5 2647 /* Set up first empty TFD within this queue's circular TFD buffer */
fc4b6853 2648 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY		 2649 memset(tfd, 0, sizeof(*tfd));
2650 control_flags = (u32 *) tfd;
fc4b6853 2651 idx = get_cmd_index(q, q->write_ptr, 0);
b481de9c 2652
6440adb5 2653 /* Set up driver data for this TFD */
bb8c093b 2654 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
fc4b6853 2655 txq->txb[q->write_ptr].skb[0] = skb;
6440adb5
CB		 2656
2657 /* Init first empty entry in queue's array of Tx/cmd buffers */
b481de9c
ZY		 2658 out_cmd = &txq->cmd[idx];
2659 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
2660 memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
6440adb5
CB		 2661
2662 /*
2663 * Set up the Tx-command (not MAC!) header.
2664 * Store the chosen Tx queue and TFD index within the sequence field;
2665 * after Tx, uCode's Tx response will return this value so driver can
2666 * locate the frame within the tx queue and do post-tx processing.
2667 */
b481de9c
ZY		 2668 out_cmd->hdr.cmd = REPLY_TX;
2669 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
fc4b6853 2670 INDEX_TO_SEQ(q->write_ptr)));
6440adb5
CB		 2671
2672 /* Copy MAC header from skb into command buffer */
b481de9c
ZY		 2673 memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
2674
6440adb5
CB		 2675 /*
2676 * Use the first empty entry in this queue's command buffer array
2677 * to contain the Tx command and MAC header concatenated together
2678 * (payload data will be in another buffer).
2679 * Size of this varies, due to varying MAC header length.
2680 * If end is not dword aligned, we'll have 2 extra bytes at the end
2681 * of the MAC header (device reads on dword boundaries).
2682 * We'll tell device about this padding later.
2683 */
b481de9c 2684 len = priv->hw_setting.tx_cmd_len +
bb8c093b 2685 sizeof(struct iwl3945_cmd_header) + hdr_len;
b481de9c
ZY		 2686
2687 len_org = len;
2688 len = (len + 3) & ~3;
2689
2690 if (len_org != len)
2691 len_org = 1;
2692 else
2693 len_org = 0;
2694
6440adb5
CB		 2695 /* Physical address of this Tx command's header (not MAC header!),
2696 * within command buffer array. */
bb8c093b
CH		 2697 txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
2698 offsetof(struct iwl3945_cmd, hdr);
b481de9c 2699
6440adb5
CB		 2700 /* Add buffer containing Tx command and MAC(!) header to TFD's
2701 * first entry */
bb8c093b 2702 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
b481de9c 2703
e039fa4a
JB		 2704 if (!(info->flags & IEEE80211_TX_CTL_DO_NOT_ENCRYPT))
2705 iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0);
b481de9c 2706
6440adb5
CB		 2707 /* Set up TFD's 2nd entry to point directly to remainder of skb,
2708 * if any (802.11 null frames have no payload). */
b481de9c
ZY		 2709 len = skb->len - hdr_len;
2710 if (len) {
2711 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
2712 len, PCI_DMA_TODEVICE);
bb8c093b 2713 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
b481de9c
ZY		 2714 }
2715
b481de9c 2716 if (!len)
6440adb5 2717 /* If there is no payload, then we use only one Tx buffer */
b481de9c
ZY		 2718 *control_flags = TFD_CTL_COUNT_SET(1);
2719 else
6440adb5
CB		 2720 /* Else use 2 buffers.
2721 * Tell 3945 about any padding after MAC header */
b481de9c
ZY		 2722 *control_flags = TFD_CTL_COUNT_SET(2) |
2723 TFD_CTL_PAD_SET(U32_PAD(len));
2724
6440adb5 2725 /* Total # bytes to be transmitted */
b481de9c
ZY		 2726 len = (u16)skb->len;
2727 out_cmd->cmd.tx.len = cpu_to_le16(len);
2728
2729 /* TODO need this for burst mode later on */
e039fa4a 2730 iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, unicast, sta_id);
b481de9c
ZY		 2731
2732 /* set is_hcca to 0; it probably will never be implemented */
e039fa4a 2733 iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
b481de9c
ZY		 2734
2735 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
2736 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
2737
8b7b1e05 2738 if (!ieee80211_has_morefrags(hdr->frame_control)) {
b481de9c
ZY		 2739 txq->need_update = 1;
2740 if (qc) {
b481de9c
ZY		 2741 priv->stations[sta_id].tid[tid].seq_number = seq_number;
2742 }
2743 } else {
2744 wait_write_ptr = 1;
2745 txq->need_update = 0;
2746 }
2747
bb8c093b 2748 iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
b481de9c
ZY		 2749 sizeof(out_cmd->cmd.tx));
2750
bb8c093b 2751 iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
fd7c8a40 2752 ieee80211_get_hdrlen(le16_to_cpu(fc)));
b481de9c 2753
6440adb5 2754 /* Tell device the write index *just past* this latest filled TFD */
c54b679d 2755 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
bb8c093b 2756 rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 2757 spin_unlock_irqrestore(&priv->lock, flags);
2758
2759 if (rc)
2760 return rc;
2761
bb8c093b 2762 if ((iwl3945_queue_space(q) < q->high_mark)
b481de9c
ZY		 2763 && priv->mac80211_registered) {
2764 if (wait_write_ptr) {
2765 spin_lock_irqsave(&priv->lock, flags);
2766 txq->need_update = 1;
bb8c093b 2767 iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 2768 spin_unlock_irqrestore(&priv->lock, flags);
2769 }
2770
e2530083 2771 ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
b481de9c
ZY		 2772 }
2773
2774 return 0;
2775
2776drop_unlock:
2777 spin_unlock_irqrestore(&priv->lock, flags);
2778drop:
2779 return -1;
2780}
2781
bb8c093b 2782static void iwl3945_set_rate(struct iwl3945_priv *priv)
b481de9c 2783{
8318d78a 2784 const struct ieee80211_supported_band *sband = NULL;
b481de9c
ZY		 2785 struct ieee80211_rate *rate;
2786 int i;
2787
8318d78a
JB		 2788 sband = iwl3945_get_band(priv, priv->band);
2789 if (!sband) {
c4ba9621
SA		 2790 IWL_ERROR("Failed to set rate: unable to get hw mode\n");
2791 return;
2792 }
b481de9c
ZY		 2793
2794 priv->active_rate = 0;
2795 priv->active_rate_basic = 0;
2796
8318d78a
JB		 2797 IWL_DEBUG_RATE("Setting rates for %s GHz\n",
2798 sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
2799
2800 for (i = 0; i < sband->n_bitrates; i++) {
2801 rate = &sband->bitrates[i];
2802 if ((rate->hw_value < IWL_RATE_COUNT) &&
2803 !(rate->flags & IEEE80211_CHAN_DISABLED)) {
2804 IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
2805 rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
2806 priv->active_rate |= (1 << rate->hw_value);
2807 }
b481de9c
ZY		 2808 }
2809
2810 IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
2811 priv->active_rate, priv->active_rate_basic);
2812
2813 /*
2814 * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
2815 * otherwise set it to the default of all CCK rates and 6, 12, 24 for
2816 * OFDM
2817 */
2818 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
2819 priv->staging_rxon.cck_basic_rates =
2820 ((priv->active_rate_basic &
2821 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
2822 else
2823 priv->staging_rxon.cck_basic_rates =
2824 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2825
2826 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
2827 priv->staging_rxon.ofdm_basic_rates =
2828 ((priv->active_rate_basic &
2829 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
2830 IWL_FIRST_OFDM_RATE) & 0xFF;
2831 else
2832 priv->staging_rxon.ofdm_basic_rates =
2833 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2834}
2835
bb8c093b 2836static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
b481de9c
ZY		 2837{
2838 unsigned long flags;
2839
2840 if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
2841 return;
2842
2843 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
2844 disable_radio ? "OFF" : "ON");
2845
2846 if (disable_radio) {
bb8c093b 2847 iwl3945_scan_cancel(priv);
b481de9c
ZY		 2848 /* FIXME: This is a workaround for AP */
2849 if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
2850 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2851 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 2852 CSR_UCODE_SW_BIT_RFKILL);
2853 spin_unlock_irqrestore(&priv->lock, flags);
bb8c093b 2854 iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
b481de9c
ZY		 2855 set_bit(STATUS_RF_KILL_SW, &priv->status);
2856 }
2857 return;
2858 }
2859
2860 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2861 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 2862
2863 clear_bit(STATUS_RF_KILL_SW, &priv->status);
2864 spin_unlock_irqrestore(&priv->lock, flags);
2865
2866 /* wake up ucode */
2867 msleep(10);
2868
2869 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH		 2870 iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
2871 if (!iwl3945_grab_nic_access(priv))
2872 iwl3945_release_nic_access(priv);
b481de9c
ZY		 2873 spin_unlock_irqrestore(&priv->lock, flags);
2874
2875 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
2876 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
2877 "disabled by HW switch\n");
2878 return;
2879 }
2880
808e72a0
ZY		 2881 if (priv->is_open)
2882 queue_work(priv->workqueue, &priv->restart);
b481de9c
ZY		 2883 return;
2884}
2885
bb8c093b 2886void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
b481de9c
ZY		 2887 u32 decrypt_res, struct ieee80211_rx_status *stats)
2888{
2889 u16 fc =
2890 le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
2891
2892 if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
2893 return;
2894
2895 if (!(fc & IEEE80211_FCTL_PROTECTED))
2896 return;
2897
2898 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
2899 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2900 case RX_RES_STATUS_SEC_TYPE_TKIP:
2901 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2902 RX_RES_STATUS_BAD_ICV_MIC)
2903 stats->flag |= RX_FLAG_MMIC_ERROR;
2904 case RX_RES_STATUS_SEC_TYPE_WEP:
2905 case RX_RES_STATUS_SEC_TYPE_CCMP:
2906 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2907 RX_RES_STATUS_DECRYPT_OK) {
2908 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
2909 stats->flag |= RX_FLAG_DECRYPTED;
2910 }
2911 break;
2912
2913 default:
2914 break;
2915 }
2916}
2917
b481de9c
ZY		 2918#define IWL_PACKET_RETRY_TIME HZ
2919
bb8c093b 2920int iwl3945_is_duplicate_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
b481de9c
ZY		 2921{
2922 u16 sc = le16_to_cpu(header->seq_ctrl);
2923 u16 seq = (sc & IEEE80211_SCTL_SEQ) >> 4;
2924 u16 frag = sc & IEEE80211_SCTL_FRAG;
2925 u16 *last_seq, *last_frag;
2926 unsigned long *last_time;
2927
2928 switch (priv->iw_mode) {
2929 case IEEE80211_IF_TYPE_IBSS:{
2930 struct list_head *p;
bb8c093b 2931 struct iwl3945_ibss_seq *entry = NULL;
b481de9c
ZY		 2932 u8 *mac = header->addr2;
2933 int index = mac[5] & (IWL_IBSS_MAC_HASH_SIZE - 1);
2934
2935 __list_for_each(p, &priv->ibss_mac_hash[index]) {
bb8c093b 2936 entry = list_entry(p, struct iwl3945_ibss_seq, list);
b481de9c
ZY		 2937 if (!compare_ether_addr(entry->mac, mac))
2938 break;
2939 }
2940 if (p == &priv->ibss_mac_hash[index]) {
2941 entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
2942 if (!entry) {
bc434dd2 2943 IWL_ERROR("Cannot malloc new mac entry\n");
b481de9c
ZY		 2944 return 0;
2945 }
2946 memcpy(entry->mac, mac, ETH_ALEN);
2947 entry->seq_num = seq;
2948 entry->frag_num = frag;
2949 entry->packet_time = jiffies;
bc434dd2 2950 list_add(&entry->list, &priv->ibss_mac_hash[index]);
b481de9c
ZY		 2951 return 0;
2952 }
2953 last_seq = &entry->seq_num;
2954 last_frag = &entry->frag_num;
2955 last_time = &entry->packet_time;
2956 break;
2957 }
2958 case IEEE80211_IF_TYPE_STA:
2959 last_seq = &priv->last_seq_num;
2960 last_frag = &priv->last_frag_num;
2961 last_time = &priv->last_packet_time;
2962 break;
2963 default:
2964 return 0;
2965 }
2966 if ((*last_seq == seq) &&
2967 time_after(*last_time + IWL_PACKET_RETRY_TIME, jiffies)) {
2968 if (*last_frag == frag)
2969 goto drop;
2970 if (*last_frag + 1 != frag)
2971 /* out-of-order fragment */
2972 goto drop;
2973 } else
2974 *last_seq = seq;
2975
2976 *last_frag = frag;
2977 *last_time = jiffies;
2978 return 0;
2979
2980 drop:
2981 return 1;
2982}
2983
c8b0e6e1 2984#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 2985
2986#include "iwl-spectrum.h"
2987
2988#define BEACON_TIME_MASK_LOW 0x00FFFFFF
2989#define BEACON_TIME_MASK_HIGH 0xFF000000
2990#define TIME_UNIT 1024
2991
2992/*
2993 * extended beacon time format
2994 * time in usec will be changed into a 32-bit value in 8:24 format
2995 * the high 1 byte is the beacon counts
2996 * the lower 3 bytes is the time in usec within one beacon interval
2997 */
2998
bb8c093b 2999static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
b481de9c
ZY		 3000{
3001 u32 quot;
3002 u32 rem;
3003 u32 interval = beacon_interval * 1024;
3004
3005 if (!interval || !usec)
3006 return 0;
3007
3008 quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
3009 rem = (usec % interval) & BEACON_TIME_MASK_LOW;
3010
3011 return (quot << 24) + rem;
3012}
3013
3014/* base is usually what we get from ucode with each received frame,
3015 * the same as HW timer counter counting down
3016 */
3017
bb8c093b 3018static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
b481de9c
ZY		 3019{
3020 u32 base_low = base & BEACON_TIME_MASK_LOW;
3021 u32 addon_low = addon & BEACON_TIME_MASK_LOW;
3022 u32 interval = beacon_interval * TIME_UNIT;
3023 u32 res = (base & BEACON_TIME_MASK_HIGH) +
3024 (addon & BEACON_TIME_MASK_HIGH);
3025
3026 if (base_low > addon_low)
3027 res += base_low - addon_low;
3028 else if (base_low < addon_low) {
3029 res += interval + base_low - addon_low;
3030 res += (1 << 24);
3031 } else
3032 res += (1 << 24);
3033
3034 return cpu_to_le32(res);
3035}
3036
bb8c093b 3037static int iwl3945_get_measurement(struct iwl3945_priv *priv,
b481de9c
ZY		 3038 struct ieee80211_measurement_params *params,
3039 u8 type)
3040{
bb8c093b
CH		 3041 struct iwl3945_spectrum_cmd spectrum;
3042 struct iwl3945_rx_packet *res;
3043 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 3044 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
3045 .data = (void *)&spectrum,
3046 .meta.flags = CMD_WANT_SKB,
3047 };
3048 u32 add_time = le64_to_cpu(params->start_time);
3049 int rc;
3050 int spectrum_resp_status;
3051 int duration = le16_to_cpu(params->duration);
3052
bb8c093b 3053 if (iwl3945_is_associated(priv))
b481de9c 3054 add_time =
bb8c093b 3055 iwl3945_usecs_to_beacons(
b481de9c
ZY		 3056 le64_to_cpu(params->start_time) - priv->last_tsf,
3057 le16_to_cpu(priv->rxon_timing.beacon_interval));
3058
3059 memset(&spectrum, 0, sizeof(spectrum));
3060
3061 spectrum.channel_count = cpu_to_le16(1);
3062 spectrum.flags =
3063 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
3064 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
3065 cmd.len = sizeof(spectrum);
3066 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
3067
bb8c093b 3068 if (iwl3945_is_associated(priv))
b481de9c 3069 spectrum.start_time =
bb8c093b 3070 iwl3945_add_beacon_time(priv->last_beacon_time,
b481de9c
ZY		 3071 add_time,
3072 le16_to_cpu(priv->rxon_timing.beacon_interval));
3073 else
3074 spectrum.start_time = 0;
3075
3076 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
3077 spectrum.channels[0].channel = params->channel;
3078 spectrum.channels[0].type = type;
3079 if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
3080 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
3081 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
3082
bb8c093b 3083 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 3084 if (rc)
3085 return rc;
3086
bb8c093b 3087 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 3088 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
3089 IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
3090 rc = -EIO;
3091 }
3092
3093 spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
3094 switch (spectrum_resp_status) {
3095 case 0: /* Command will be handled */
3096 if (res->u.spectrum.id != 0xff) {
bc434dd2
IS		 3097 IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
3098 res->u.spectrum.id);
b481de9c
ZY		 3099 priv->measurement_status &= ~MEASUREMENT_READY;
3100 }
3101 priv->measurement_status |= MEASUREMENT_ACTIVE;
3102 rc = 0;
3103 break;
3104
3105 case 1: /* Command will not be handled */
3106 rc = -EAGAIN;
3107 break;
3108 }
3109
3110 dev_kfree_skb_any(cmd.meta.u.skb);
3111
3112 return rc;
3113}
3114#endif
3115
bb8c093b
CH		 3116static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
3117 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3118{
bb8c093b
CH		 3119 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3120 struct iwl3945_alive_resp *palive;
b481de9c
ZY		 3121 struct delayed_work *pwork;
3122
3123 palive = &pkt->u.alive_frame;
3124
3125 IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
3126 "0x%01X 0x%01X\n",
3127 palive->is_valid, palive->ver_type,
3128 palive->ver_subtype);
3129
3130 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
3131 IWL_DEBUG_INFO("Initialization Alive received.\n");
3132 memcpy(&priv->card_alive_init,
3133 &pkt->u.alive_frame,
bb8c093b 3134 sizeof(struct iwl3945_init_alive_resp));
b481de9c
ZY		 3135 pwork = &priv->init_alive_start;
3136 } else {
3137 IWL_DEBUG_INFO("Runtime Alive received.\n");
3138 memcpy(&priv->card_alive, &pkt->u.alive_frame,
bb8c093b 3139 sizeof(struct iwl3945_alive_resp));
b481de9c 3140 pwork = &priv->alive_start;
bb8c093b 3141 iwl3945_disable_events(priv);
b481de9c
ZY		 3142 }
3143
3144 /* We delay the ALIVE response by 5ms to
3145 * give the HW RF Kill time to activate... */
3146 if (palive->is_valid == UCODE_VALID_OK)
3147 queue_delayed_work(priv->workqueue, pwork,
3148 msecs_to_jiffies(5));
3149 else
3150 IWL_WARNING("uCode did not respond OK.\n");
3151}
3152
bb8c093b
CH		 3153static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
3154 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3155{
bb8c093b 3156 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3157
3158 IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
3159 return;
3160}
3161
bb8c093b
CH		 3162static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
3163 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3164{
bb8c093b 3165 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3166
3167 IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
3168 "seq 0x%04X ser 0x%08X\n",
3169 le32_to_cpu(pkt->u.err_resp.error_type),
3170 get_cmd_string(pkt->u.err_resp.cmd_id),
3171 pkt->u.err_resp.cmd_id,
3172 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
3173 le32_to_cpu(pkt->u.err_resp.error_info));
3174}
3175
3176#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
3177
bb8c093b 3178static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3179{
bb8c093b
CH		 3180 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3181 struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
3182 struct iwl3945_csa_notification *csa = &(pkt->u.csa_notif);
b481de9c
ZY		 3183 IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
3184 le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
3185 rxon->channel = csa->channel;
3186 priv->staging_rxon.channel = csa->channel;
3187}
3188
bb8c093b
CH		 3189static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
3190 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3191{
c8b0e6e1 3192#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
bb8c093b
CH		 3193 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3194 struct iwl3945_spectrum_notification *report = &(pkt->u.spectrum_notif);
b481de9c
ZY		 3195
3196 if (!report->state) {
3197 IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
3198 "Spectrum Measure Notification: Start\n");
3199 return;
3200 }
3201
3202 memcpy(&priv->measure_report, report, sizeof(*report));
3203 priv->measurement_status |= MEASUREMENT_READY;
3204#endif
3205}
3206
bb8c093b
CH		 3207static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
3208 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3209{
c8b0e6e1 3210#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3211 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3212 struct iwl3945_sleep_notification *sleep = &(pkt->u.sleep_notif);
b481de9c
ZY		 3213 IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
3214 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
3215#endif
3216}
3217
bb8c093b
CH		 3218static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
3219 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3220{
bb8c093b 3221 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3222 IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
3223 "notification for %s:\n",
3224 le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
bb8c093b 3225 iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
b481de9c
ZY		 3226}
3227
bb8c093b 3228static void iwl3945_bg_beacon_update(struct work_struct *work)
b481de9c 3229{
bb8c093b
CH		 3230 struct iwl3945_priv *priv =
3231 container_of(work, struct iwl3945_priv, beacon_update);
b481de9c
ZY		 3232 struct sk_buff *beacon;
3233
3234 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 3235 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY		 3236
3237 if (!beacon) {
3238 IWL_ERROR("update beacon failed\n");
3239 return;
3240 }
3241
3242 mutex_lock(&priv->mutex);
3243 /* new beacon skb is allocated every time; dispose previous.*/
3244 if (priv->ibss_beacon)
3245 dev_kfree_skb(priv->ibss_beacon);
3246
3247 priv->ibss_beacon = beacon;
3248 mutex_unlock(&priv->mutex);
3249
bb8c093b 3250 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 3251}
3252
bb8c093b
CH		 3253static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
3254 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3255{
c8b0e6e1 3256#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3257 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3258 struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
b481de9c
ZY		 3259 u8 rate = beacon->beacon_notify_hdr.rate;
3260
3261 IWL_DEBUG_RX("beacon status %x retries %d iss %d "
3262 "tsf %d %d rate %d\n",
3263 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
3264 beacon->beacon_notify_hdr.failure_frame,
3265 le32_to_cpu(beacon->ibss_mgr_status),
3266 le32_to_cpu(beacon->high_tsf),
3267 le32_to_cpu(beacon->low_tsf), rate);
3268#endif
3269
3270 if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
3271 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
3272 queue_work(priv->workqueue, &priv->beacon_update);
3273}
3274
3275/* Service response to REPLY_SCAN_CMD (0x80) */
bb8c093b
CH		 3276static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
3277 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3278{
c8b0e6e1 3279#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3280 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3281 struct iwl3945_scanreq_notification *notif =
3282 (struct iwl3945_scanreq_notification *)pkt->u.raw;
b481de9c
ZY		 3283
3284 IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
3285#endif
3286}
3287
3288/* Service SCAN_START_NOTIFICATION (0x82) */
bb8c093b
CH		 3289static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
3290 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3291{
bb8c093b
CH		 3292 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3293 struct iwl3945_scanstart_notification *notif =
3294 (struct iwl3945_scanstart_notification *)pkt->u.raw;
b481de9c
ZY		 3295 priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
3296 IWL_DEBUG_SCAN("Scan start: "
3297 "%d [802.11%s] "
3298 "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
3299 notif->channel,
3300 notif->band ? "bg" : "a",
3301 notif->tsf_high,
3302 notif->tsf_low, notif->status, notif->beacon_timer);
3303}
3304
3305/* Service SCAN_RESULTS_NOTIFICATION (0x83) */
bb8c093b
CH		 3306static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
3307 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3308{
bb8c093b
CH		 3309 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3310 struct iwl3945_scanresults_notification *notif =
3311 (struct iwl3945_scanresults_notification *)pkt->u.raw;
b481de9c
ZY		 3312
3313 IWL_DEBUG_SCAN("Scan ch.res: "
3314 "%d [802.11%s] "
3315 "(TSF: 0x%08X:%08X) - %d "
3316 "elapsed=%lu usec (%dms since last)\n",
3317 notif->channel,
3318 notif->band ? "bg" : "a",
3319 le32_to_cpu(notif->tsf_high),
3320 le32_to_cpu(notif->tsf_low),
3321 le32_to_cpu(notif->statistics[0]),
3322 le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
3323 jiffies_to_msecs(elapsed_jiffies
3324 (priv->last_scan_jiffies, jiffies)));
3325
3326 priv->last_scan_jiffies = jiffies;
7878a5a4 3327 priv->next_scan_jiffies = 0;
b481de9c
ZY		 3328}
3329
3330/* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
bb8c093b
CH		 3331static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
3332 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3333{
bb8c093b
CH		 3334 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3335 struct iwl3945_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
b481de9c
ZY		 3336
3337 IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
3338 scan_notif->scanned_channels,
3339 scan_notif->tsf_low,
3340 scan_notif->tsf_high, scan_notif->status);
3341
3342 /* The HW is no longer scanning */
3343 clear_bit(STATUS_SCAN_HW, &priv->status);
3344
3345 /* The scan completion notification came in, so kill that timer... */
3346 cancel_delayed_work(&priv->scan_check);
3347
3348 IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
66b5004d
RR		 3349 (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ?
3350 "2.4" : "5.2",
b481de9c
ZY		 3351 jiffies_to_msecs(elapsed_jiffies
3352 (priv->scan_pass_start, jiffies)));
3353
66b5004d
RR		 3354 /* Remove this scanned band from the list of pending
3355 * bands to scan, band G precedes A in order of scanning
3356 * as seen in iwl3945_bg_request_scan */
3357 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ))
3358 priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ);
3359 else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ))
3360 priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ);
b481de9c
ZY		 3361
3362 /* If a request to abort was given, or the scan did not succeed
3363 * then we reset the scan state machine and terminate,
3364 * re-queuing another scan if one has been requested */
3365 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
3366 IWL_DEBUG_INFO("Aborted scan completed.\n");
3367 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
3368 } else {
3369 /* If there are more bands on this scan pass reschedule */
3370 if (priv->scan_bands > 0)
3371 goto reschedule;
3372 }
3373
3374 priv->last_scan_jiffies = jiffies;
7878a5a4 3375 priv->next_scan_jiffies = 0;
b481de9c
ZY		 3376 IWL_DEBUG_INFO("Setting scan to off\n");
3377
3378 clear_bit(STATUS_SCANNING, &priv->status);
3379
3380 IWL_DEBUG_INFO("Scan took %dms\n",
3381 jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
3382
3383 queue_work(priv->workqueue, &priv->scan_completed);
3384
3385 return;
3386
3387reschedule:
3388 priv->scan_pass_start = jiffies;
3389 queue_work(priv->workqueue, &priv->request_scan);
3390}
3391
3392/* Handle notification from uCode that card's power state is changing
3393 * due to software, hardware, or critical temperature RFKILL */
bb8c093b
CH		 3394static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
3395 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3396{
bb8c093b 3397 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3398 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
3399 unsigned long status = priv->status;
3400
3401 IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
3402 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3403 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
3404
bb8c093b 3405 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 3406 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3407
3408 if (flags & HW_CARD_DISABLED)
3409 set_bit(STATUS_RF_KILL_HW, &priv->status);
3410 else
3411 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3412
3413
3414 if (flags & SW_CARD_DISABLED)
3415 set_bit(STATUS_RF_KILL_SW, &priv->status);
3416 else
3417 clear_bit(STATUS_RF_KILL_SW, &priv->status);
3418
bb8c093b 3419 iwl3945_scan_cancel(priv);
b481de9c
ZY		 3420
3421 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
3422 test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
3423 (test_bit(STATUS_RF_KILL_SW, &status) !=
3424 test_bit(STATUS_RF_KILL_SW, &priv->status)))
3425 queue_work(priv->workqueue, &priv->rf_kill);
3426 else
3427 wake_up_interruptible(&priv->wait_command_queue);
3428}
3429
3430/**
bb8c093b 3431 * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY		 3432 *
3433 * Setup the RX handlers for each of the reply types sent from the uCode
3434 * to the host.
3435 *
3436 * This function chains into the hardware specific files for them to setup
3437 * any hardware specific handlers as well.
3438 */
bb8c093b 3439static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
b481de9c 3440{
bb8c093b
CH		 3441 priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
3442 priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
3443 priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
3444 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
b481de9c 3445 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
bb8c093b
CH		 3446 iwl3945_rx_spectrum_measure_notif;
3447 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
b481de9c 3448 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
bb8c093b
CH		 3449 iwl3945_rx_pm_debug_statistics_notif;
3450 priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
b481de9c 3451
9fbab516
BC		 3452 /*
3453 * The same handler is used for both the REPLY to a discrete
3454 * statistics request from the host as well as for the periodic
3455 * statistics notifications (after received beacons) from the uCode.
b481de9c 3456 */
bb8c093b
CH		 3457 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
3458 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
b481de9c 3459
bb8c093b
CH		 3460 priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
3461 priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
b481de9c 3462 priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
bb8c093b 3463 iwl3945_rx_scan_results_notif;
b481de9c 3464 priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
bb8c093b
CH		 3465 iwl3945_rx_scan_complete_notif;
3466 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
b481de9c 3467
9fbab516 3468 /* Set up hardware specific Rx handlers */
bb8c093b 3469 iwl3945_hw_rx_handler_setup(priv);
b481de9c
ZY		 3470}
3471
91c066f2
TW		 3472/**
3473 * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries
3474 * When FW advances 'R' index, all entries between old and new 'R' index
3475 * need to be reclaimed.
3476 */
3477static void iwl3945_cmd_queue_reclaim(struct iwl3945_priv *priv,
3478 int txq_id, int index)
3479{
3480 struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
3481 struct iwl3945_queue *q = &txq->q;
3482 int nfreed = 0;
3483
3484 if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) {
3485 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
3486 "is out of range [0-%d] %d %d.\n", txq_id,
3487 index, q->n_bd, q->write_ptr, q->read_ptr);
3488 return;
3489 }
3490
3491 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
3492 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
3493 if (nfreed > 1) {
3494 IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
3495 q->write_ptr, q->read_ptr);
3496 queue_work(priv->workqueue, &priv->restart);
3497 break;
3498 }
3499 nfreed++;
3500 }
3501}
3502
3503
b481de9c 3504/**
bb8c093b 3505 * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
b481de9c
ZY		 3506 * @rxb: Rx buffer to reclaim
3507 *
3508 * If an Rx buffer has an async callback associated with it the callback
3509 * will be executed. The attached skb (if present) will only be freed
3510 * if the callback returns 1
3511 */
bb8c093b
CH		 3512static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
3513 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3514{
bb8c093b 3515 struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
b481de9c
ZY		 3516 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3517 int txq_id = SEQ_TO_QUEUE(sequence);
3518 int index = SEQ_TO_INDEX(sequence);
3519 int huge = sequence & SEQ_HUGE_FRAME;
3520 int cmd_index;
bb8c093b 3521 struct iwl3945_cmd *cmd;
b481de9c 3522
b481de9c
ZY		 3523 BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
3524
3525 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
3526 cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
3527
3528 /* Input error checking is done when commands are added to queue. */
3529 if (cmd->meta.flags & CMD_WANT_SKB) {
3530 cmd->meta.source->u.skb = rxb->skb;
3531 rxb->skb = NULL;
3532 } else if (cmd->meta.u.callback &&
3533 !cmd->meta.u.callback(priv, cmd, rxb->skb))
3534 rxb->skb = NULL;
3535
91c066f2 3536 iwl3945_cmd_queue_reclaim(priv, txq_id, index);
b481de9c
ZY		 3537
3538 if (!(cmd->meta.flags & CMD_ASYNC)) {
3539 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
3540 wake_up_interruptible(&priv->wait_command_queue);
3541 }
3542}
3543
3544/************************** RX-FUNCTIONS ****************************/
3545/*
3546 * Rx theory of operation
3547 *
3548 * The host allocates 32 DMA target addresses and passes the host address
3549 * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
3550 * 0 to 31
3551 *
3552 * Rx Queue Indexes
3553 * The host/firmware share two index registers for managing the Rx buffers.
3554 *
3555 * The READ index maps to the first position that the firmware may be writing
3556 * to -- the driver can read up to (but not including) this position and get
3557 * good data.
3558 * The READ index is managed by the firmware once the card is enabled.
3559 *
3560 * The WRITE index maps to the last position the driver has read from -- the
3561 * position preceding WRITE is the last slot the firmware can place a packet.
3562 *
3563 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
3564 * WRITE = READ.
3565 *
9fbab516 3566 * During initialization, the host sets up the READ queue position to the first
b481de9c
ZY		 3567 * INDEX position, and WRITE to the last (READ - 1 wrapped)
3568 *
9fbab516 3569 * When the firmware places a packet in a buffer, it will advance the READ index
b481de9c
ZY		 3570 * and fire the RX interrupt. The driver can then query the READ index and
3571 * process as many packets as possible, moving the WRITE index forward as it
3572 * resets the Rx queue buffers with new memory.
3573 *
3574 * The management in the driver is as follows:
3575 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
3576 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
01ebd063 3577 * to replenish the iwl->rxq->rx_free.
bb8c093b 3578 * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
b481de9c
ZY		 3579 * iwl->rxq is replenished and the READ INDEX is updated (updating the
3580 * 'processed' and 'read' driver indexes as well)
3581 * + A received packet is processed and handed to the kernel network stack,
3582 * detached from the iwl->rxq. The driver 'processed' index is updated.
3583 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
3584 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
3585 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
3586 * were enough free buffers and RX_STALLED is set it is cleared.
3587 *
3588 *
3589 * Driver sequence:
3590 *
9fbab516
BC		 3591 * iwl3945_rx_queue_alloc() Allocates rx_free
3592 * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
bb8c093b 3593 * iwl3945_rx_queue_restock
9fbab516 3594 * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
b481de9c
ZY		 3595 * queue, updates firmware pointers, and updates
3596 * the WRITE index. If insufficient rx_free buffers
bb8c093b 3597 * are available, schedules iwl3945_rx_replenish
b481de9c
ZY		 3598 *
3599 * -- enable interrupts --
9fbab516 3600 * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the
b481de9c
ZY		 3601 * READ INDEX, detaching the SKB from the pool.
3602 * Moves the packet buffer from queue to rx_used.
bb8c093b 3603 * Calls iwl3945_rx_queue_restock to refill any empty
b481de9c
ZY		 3604 * slots.
3605 * ...
3606 *
3607 */
3608
3609/**
bb8c093b 3610 * iwl3945_rx_queue_space - Return number of free slots available in queue.
b481de9c 3611 */
bb8c093b 3612static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
b481de9c
ZY		 3613{
3614 int s = q->read - q->write;
3615 if (s <= 0)
3616 s += RX_QUEUE_SIZE;
3617 /* keep some buffer to not confuse full and empty queue */
3618 s -= 2;
3619 if (s < 0)
3620 s = 0;
3621 return s;
3622}
3623
3624/**
bb8c093b 3625 * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
b481de9c 3626 */
bb8c093b 3627int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
b481de9c
ZY		 3628{
3629 u32 reg = 0;
3630 int rc = 0;
3631 unsigned long flags;
3632
3633 spin_lock_irqsave(&q->lock, flags);
3634
3635 if (q->need_update == 0)
3636 goto exit_unlock;
3637
6440adb5 3638 /* If power-saving is in use, make sure device is awake */
b481de9c 3639 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
bb8c093b 3640 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY		 3641
3642 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
bb8c093b 3643 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 3644 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3645 goto exit_unlock;
3646 }
3647
bb8c093b 3648 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 3649 if (rc)
3650 goto exit_unlock;
3651
6440adb5 3652 /* Device expects a multiple of 8 */
bb8c093b 3653 iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
b481de9c 3654 q->write & ~0x7);
bb8c093b 3655 iwl3945_release_nic_access(priv);
6440adb5
CB		 3656
3657 /* Else device is assumed to be awake */
b481de9c 3658 } else
6440adb5 3659 /* Device expects a multiple of 8 */
bb8c093b 3660 iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
b481de9c
ZY		 3661
3662
3663 q->need_update = 0;
3664
3665 exit_unlock:
3666 spin_unlock_irqrestore(&q->lock, flags);
3667 return rc;
3668}
3669
3670/**
9fbab516 3671 * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
b481de9c 3672 */
bb8c093b 3673static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
b481de9c
ZY		 3674 dma_addr_t dma_addr)
3675{
3676 return cpu_to_le32((u32)dma_addr);
3677}
3678
3679/**
bb8c093b 3680 * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
b481de9c 3681 *
9fbab516 3682 * If there are slots in the RX queue that need to be restocked,
b481de9c 3683 * and we have free pre-allocated buffers, fill the ranks as much
9fbab516 3684 * as we can, pulling from rx_free.
b481de9c
ZY		 3685 *
3686 * This moves the 'write' index forward to catch up with 'processed', and
3687 * also updates the memory address in the firmware to reference the new
3688 * target buffer.
3689 */
bb8c093b 3690static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
b481de9c 3691{
bb8c093b 3692 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 3693 struct list_head *element;
bb8c093b 3694 struct iwl3945_rx_mem_buffer *rxb;
b481de9c
ZY		 3695 unsigned long flags;
3696 int write, rc;
3697
3698 spin_lock_irqsave(&rxq->lock, flags);
3699 write = rxq->write & ~0x7;
bb8c093b 3700 while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
6440adb5 3701 /* Get next free Rx buffer, remove from free list */
b481de9c 3702 element = rxq->rx_free.next;
bb8c093b 3703 rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
b481de9c 3704 list_del(element);
6440adb5
CB		 3705
3706 /* Point to Rx buffer via next RBD in circular buffer */
bb8c093b 3707 rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
b481de9c
ZY		 3708 rxq->queue[rxq->write] = rxb;
3709 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
3710 rxq->free_count--;
3711 }
3712 spin_unlock_irqrestore(&rxq->lock, flags);
3713 /* If the pre-allocated buffer pool is dropping low, schedule to
3714 * refill it */
3715 if (rxq->free_count <= RX_LOW_WATERMARK)
3716 queue_work(priv->workqueue, &priv->rx_replenish);
3717
3718
6440adb5
CB		 3719 /* If we've added more space for the firmware to place data, tell it.
3720 * Increment device's write pointer in multiples of 8. */
b481de9c
ZY		 3721 if ((write != (rxq->write & ~0x7))
3722 || (abs(rxq->write - rxq->read) > 7)) {
3723 spin_lock_irqsave(&rxq->lock, flags);
3724 rxq->need_update = 1;
3725 spin_unlock_irqrestore(&rxq->lock, flags);
bb8c093b 3726 rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 3727 if (rc)
3728 return rc;
3729 }
3730
3731 return 0;
3732}
3733
3734/**
bb8c093b 3735 * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
b481de9c
ZY		 3736 *
3737 * When moving to rx_free an SKB is allocated for the slot.
3738 *
bb8c093b 3739 * Also restock the Rx queue via iwl3945_rx_queue_restock.
01ebd063 3740 * This is called as a scheduled work item (except for during initialization)
b481de9c 3741 */
5c0eef96 3742static void iwl3945_rx_allocate(struct iwl3945_priv *priv)
b481de9c 3743{
bb8c093b 3744 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 3745 struct list_head *element;
bb8c093b 3746 struct iwl3945_rx_mem_buffer *rxb;
b481de9c
ZY		 3747 unsigned long flags;
3748 spin_lock_irqsave(&rxq->lock, flags);
3749 while (!list_empty(&rxq->rx_used)) {
3750 element = rxq->rx_used.next;
bb8c093b 3751 rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
6440adb5
CB		 3752
3753 /* Alloc a new receive buffer */
b481de9c
ZY		 3754 rxb->skb =
3755 alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
3756 if (!rxb->skb) {
3757 if (net_ratelimit())
3758 printk(KERN_CRIT DRV_NAME
3759 ": Can not allocate SKB buffers\n");
3760 /* We don't reschedule replenish work here -- we will
3761 * call the restock method and if it still needs
3762 * more buffers it will schedule replenish */
3763 break;
3764 }
12342c47
ZY		 3765
3766 /* If radiotap head is required, reserve some headroom here.
3767 * The physical head count is a variable rx_stats->phy_count.
3768 * We reserve 4 bytes here. Plus these extra bytes, the
3769 * headroom of the physical head should be enough for the
3770 * radiotap head that iwl3945 supported. See iwl3945_rt.
3771 */
3772 skb_reserve(rxb->skb, 4);
3773
b481de9c
ZY		 3774 priv->alloc_rxb_skb++;
3775 list_del(element);
6440adb5
CB		 3776
3777 /* Get physical address of RB/SKB */
b481de9c
ZY		 3778 rxb->dma_addr =
3779 pci_map_single(priv->pci_dev, rxb->skb->data,
3780 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3781 list_add_tail(&rxb->list, &rxq->rx_free);
3782 rxq->free_count++;
3783 }
3784 spin_unlock_irqrestore(&rxq->lock, flags);
5c0eef96
MA		 3785}
3786
3787/*
3788 * this should be called while priv->lock is locked
3789 */
4fd1f841 3790static void __iwl3945_rx_replenish(void *data)
5c0eef96
MA		 3791{
3792 struct iwl3945_priv *priv = data;
3793
3794 iwl3945_rx_allocate(priv);
3795 iwl3945_rx_queue_restock(priv);
3796}
3797
3798
3799void iwl3945_rx_replenish(void *data)
3800{
3801 struct iwl3945_priv *priv = data;
3802 unsigned long flags;
3803
3804 iwl3945_rx_allocate(priv);
b481de9c
ZY		 3805
3806 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 3807 iwl3945_rx_queue_restock(priv);
b481de9c
ZY		 3808 spin_unlock_irqrestore(&priv->lock, flags);
3809}
3810
3811/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
9fbab516 3812 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
b481de9c
ZY		 3813 * This free routine walks the list of POOL entries and if SKB is set to
3814 * non NULL it is unmapped and freed
3815 */
bb8c093b 3816static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY		 3817{
3818 int i;
3819 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
3820 if (rxq->pool[i].skb != NULL) {
3821 pci_unmap_single(priv->pci_dev,
3822 rxq->pool[i].dma_addr,
3823 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3824 dev_kfree_skb(rxq->pool[i].skb);
3825 }
3826 }
3827
3828 pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
3829 rxq->dma_addr);
3830 rxq->bd = NULL;
3831}
3832
bb8c093b 3833int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
b481de9c 3834{
bb8c093b 3835 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 3836 struct pci_dev *dev = priv->pci_dev;
3837 int i;
3838
3839 spin_lock_init(&rxq->lock);
3840 INIT_LIST_HEAD(&rxq->rx_free);
3841 INIT_LIST_HEAD(&rxq->rx_used);
6440adb5
CB		 3842
3843 /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
b481de9c
ZY		 3844 rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
3845 if (!rxq->bd)
3846 return -ENOMEM;
6440adb5 3847
b481de9c
ZY		 3848 /* Fill the rx_used queue with _all_ of the Rx buffers */
3849 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
3850 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
6440adb5 3851
b481de9c
ZY		 3852 /* Set us so that we have processed and used all buffers, but have
3853 * not restocked the Rx queue with fresh buffers */
3854 rxq->read = rxq->write = 0;
3855 rxq->free_count = 0;
3856 rxq->need_update = 0;
3857 return 0;
3858}
3859
bb8c093b 3860void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY		 3861{
3862 unsigned long flags;
3863 int i;
3864 spin_lock_irqsave(&rxq->lock, flags);
3865 INIT_LIST_HEAD(&rxq->rx_free);
3866 INIT_LIST_HEAD(&rxq->rx_used);
3867 /* Fill the rx_used queue with _all_ of the Rx buffers */
3868 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
3869 /* In the reset function, these buffers may have been allocated
3870 * to an SKB, so we need to unmap and free potential storage */
3871 if (rxq->pool[i].skb != NULL) {
3872 pci_unmap_single(priv->pci_dev,
3873 rxq->pool[i].dma_addr,
3874 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3875 priv->alloc_rxb_skb--;
3876 dev_kfree_skb(rxq->pool[i].skb);
3877 rxq->pool[i].skb = NULL;
3878 }
3879 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
3880 }
3881
3882 /* Set us so that we have processed and used all buffers, but have
3883 * not restocked the Rx queue with fresh buffers */
3884 rxq->read = rxq->write = 0;
3885 rxq->free_count = 0;
3886 spin_unlock_irqrestore(&rxq->lock, flags);
3887}
3888
3889/* Convert linear signal-to-noise ratio into dB */
3890static u8 ratio2dB[100] = {
3891/* 0 1 2 3 4 5 6 7 8 9 */
3892 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
3893 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
3894 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
3895 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
3896 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
3897 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
3898 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
3899 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
3900 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
3901 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
3902};
3903
3904/* Calculates a relative dB value from a ratio of linear
3905 * (i.e. not dB) signal levels.
3906 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
bb8c093b 3907int iwl3945_calc_db_from_ratio(int sig_ratio)
b481de9c 3908{
221c80cf
AB		 3909 /* 1000:1 or higher just report as 60 dB */
3910 if (sig_ratio >= 1000)
b481de9c
ZY		 3911 return 60;
3912
221c80cf 3913 /* 100:1 or higher, divide by 10 and use table,
b481de9c 3914 * add 20 dB to make up for divide by 10 */
221c80cf 3915 if (sig_ratio >= 100)
b481de9c
ZY		 3916 return (20 + (int)ratio2dB[sig_ratio/10]);
3917
3918 /* We shouldn't see this */
3919 if (sig_ratio < 1)
3920 return 0;
3921
3922 /* Use table for ratios 1:1 - 99:1 */
3923 return (int)ratio2dB[sig_ratio];
3924}
3925
3926#define PERFECT_RSSI (-20) /* dBm */
3927#define WORST_RSSI (-95) /* dBm */
3928#define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
3929
3930/* Calculate an indication of rx signal quality (a percentage, not dBm!).
3931 * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
3932 * about formulas used below. */
bb8c093b 3933int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
b481de9c
ZY		 3934{
3935 int sig_qual;
3936 int degradation = PERFECT_RSSI - rssi_dbm;
3937
3938 /* If we get a noise measurement, use signal-to-noise ratio (SNR)
3939 * as indicator; formula is (signal dbm - noise dbm).
3940 * SNR at or above 40 is a great signal (100%).
3941 * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
3942 * Weakest usable signal is usually 10 - 15 dB SNR. */
3943 if (noise_dbm) {
3944 if (rssi_dbm - noise_dbm >= 40)
3945 return 100;
3946 else if (rssi_dbm < noise_dbm)
3947 return 0;
3948 sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
3949
3950 /* Else use just the signal level.
3951 * This formula is a least squares fit of data points collected and
3952 * compared with a reference system that had a percentage (%) display
3953 * for signal quality. */
3954 } else
3955 sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
3956 (15 * RSSI_RANGE + 62 * degradation)) /
3957 (RSSI_RANGE * RSSI_RANGE);
3958
3959 if (sig_qual > 100)
3960 sig_qual = 100;
3961 else if (sig_qual < 1)
3962 sig_qual = 0;
3963
3964 return sig_qual;
3965}
3966
3967/**
9fbab516 3968 * iwl3945_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY		 3969 *
3970 * Uses the priv->rx_handlers callback function array to invoke
3971 * the appropriate handlers, including command responses,
3972 * frame-received notifications, and other notifications.
3973 */
bb8c093b 3974static void iwl3945_rx_handle(struct iwl3945_priv *priv)
b481de9c 3975{
bb8c093b
CH		 3976 struct iwl3945_rx_mem_buffer *rxb;
3977 struct iwl3945_rx_packet *pkt;
3978 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 3979 u32 r, i;
3980 int reclaim;
3981 unsigned long flags;
5c0eef96 3982 u8 fill_rx = 0;
d68ab680 3983 u32 count = 8;
b481de9c 3984
6440adb5
CB		 3985 /* uCode's read index (stored in shared DRAM) indicates the last Rx
3986 * buffer that the driver may process (last buffer filled by ucode). */
bb8c093b 3987 r = iwl3945_hw_get_rx_read(priv);
b481de9c
ZY		 3988 i = rxq->read;
3989
5c0eef96
MA		 3990 if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
3991 fill_rx = 1;
b481de9c
ZY		 3992 /* Rx interrupt, but nothing sent from uCode */
3993 if (i == r)
3994 IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
3995
3996 while (i != r) {
3997 rxb = rxq->queue[i];
3998
9fbab516 3999 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY		 4000 * then a bug has been introduced in the queue refilling
4001 * routines -- catch it here */
4002 BUG_ON(rxb == NULL);
4003
4004 rxq->queue[i] = NULL;
4005
4006 pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
4007 IWL_RX_BUF_SIZE,
4008 PCI_DMA_FROMDEVICE);
bb8c093b 4009 pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
b481de9c
ZY		 4010
4011 /* Reclaim a command buffer only if this packet is a response
4012 * to a (driver-originated) command.
4013 * If the packet (e.g. Rx frame) originated from uCode,
4014 * there is no command buffer to reclaim.
4015 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
4016 * but apparently a few don't get set; catch them here. */
4017 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
4018 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
4019 (pkt->hdr.cmd != REPLY_TX);
4020
4021 /* Based on type of command response or notification,
4022 * handle those that need handling via function in
bb8c093b 4023 * rx_handlers table. See iwl3945_setup_rx_handlers() */
b481de9c
ZY		 4024 if (priv->rx_handlers[pkt->hdr.cmd]) {
4025 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
4026 "r = %d, i = %d, %s, 0x%02x\n", r, i,
4027 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
4028 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
4029 } else {
4030 /* No handling needed */
4031 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
4032 "r %d i %d No handler needed for %s, 0x%02x\n",
4033 r, i, get_cmd_string(pkt->hdr.cmd),
4034 pkt->hdr.cmd);
4035 }
4036
4037 if (reclaim) {
9fbab516
BC		 4038 /* Invoke any callbacks, transfer the skb to caller, and
4039 * fire off the (possibly) blocking iwl3945_send_cmd()
b481de9c
ZY		 4040 * as we reclaim the driver command queue */
4041 if (rxb && rxb->skb)
bb8c093b 4042 iwl3945_tx_cmd_complete(priv, rxb);
b481de9c
ZY		 4043 else
4044 IWL_WARNING("Claim null rxb?\n");
4045 }
4046
4047 /* For now we just don't re-use anything. We can tweak this
4048 * later to try and re-use notification packets and SKBs that
4049 * fail to Rx correctly */
4050 if (rxb->skb != NULL) {
4051 priv->alloc_rxb_skb--;
4052 dev_kfree_skb_any(rxb->skb);
4053 rxb->skb = NULL;
4054 }
4055
4056 pci_unmap_single(priv->pci_dev, rxb->dma_addr,
4057 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
4058 spin_lock_irqsave(&rxq->lock, flags);
4059 list_add_tail(&rxb->list, &priv->rxq.rx_used);
4060 spin_unlock_irqrestore(&rxq->lock, flags);
4061 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA		 4062 /* If there are a lot of unused frames,
4063 * restock the Rx queue so ucode won't assert. */
4064 if (fill_rx) {
4065 count++;
4066 if (count >= 8) {
4067 priv->rxq.read = i;
4068 __iwl3945_rx_replenish(priv);
4069 count = 0;
4070 }
4071 }
b481de9c
ZY		 4072 }
4073
4074 /* Backtrack one entry */
4075 priv->rxq.read = i;
bb8c093b 4076 iwl3945_rx_queue_restock(priv);
b481de9c
ZY		 4077}
4078
6440adb5
CB		 4079/**
4080 * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
4081 */
bb8c093b
CH		 4082static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
4083 struct iwl3945_tx_queue *txq)
b481de9c
ZY		 4084{
4085 u32 reg = 0;
4086 int rc = 0;
4087 int txq_id = txq->q.id;
4088
4089 if (txq->need_update == 0)
4090 return rc;
4091
4092 /* if we're trying to save power */
4093 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
4094 /* wake up nic if it's powered down ...
4095 * uCode will wake up, and interrupt us again, so next
4096 * time we'll skip this part. */
bb8c093b 4097 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY		 4098
4099 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
4100 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
bb8c093b 4101 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 4102 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
4103 return rc;
4104 }
4105
4106 /* restore this queue's parameters in nic hardware. */
bb8c093b 4107 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 4108 if (rc)
4109 return rc;
bb8c093b 4110 iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
fc4b6853 4111 txq->q.write_ptr | (txq_id << 8));
bb8c093b 4112 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4113
4114 /* else not in power-save mode, uCode will never sleep when we're
4115 * trying to tx (during RFKILL, we're not trying to tx). */
4116 } else
bb8c093b 4117 iwl3945_write32(priv, HBUS_TARG_WRPTR,
fc4b6853 4118 txq->q.write_ptr | (txq_id << 8));
b481de9c
ZY		 4119
4120 txq->need_update = 0;
4121
4122 return rc;
4123}
4124
c8b0e6e1 4125#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4126static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon)
b481de9c 4127{
0795af57
JP		 4128 DECLARE_MAC_BUF(mac);
4129
b481de9c 4130 IWL_DEBUG_RADIO("RX CONFIG:\n");
bb8c093b 4131 iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
b481de9c
ZY		 4132 IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
4133 IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
4134 IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
4135 le32_to_cpu(rxon->filter_flags));
4136 IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
4137 IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
4138 rxon->ofdm_basic_rates);
4139 IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
0795af57
JP		 4140 IWL_DEBUG_RADIO("u8[6] node_addr: %s\n",
4141 print_mac(mac, rxon->node_addr));
4142 IWL_DEBUG_RADIO("u8[6] bssid_addr: %s\n",
4143 print_mac(mac, rxon->bssid_addr));
b481de9c
ZY		 4144 IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
4145}
4146#endif
4147
bb8c093b 4148static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
b481de9c
ZY		 4149{
4150 IWL_DEBUG_ISR("Enabling interrupts\n");
4151 set_bit(STATUS_INT_ENABLED, &priv->status);
bb8c093b 4152 iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
b481de9c
ZY		 4153}
4154
0359facc
MA		 4155
4156/* call this function to flush any scheduled tasklet */
4157static inline void iwl_synchronize_irq(struct iwl3945_priv *priv)
4158{
4159 /* wait to make sure we flush pedding tasklet*/
4160 synchronize_irq(priv->pci_dev->irq);
4161 tasklet_kill(&priv->irq_tasklet);
4162}
4163
4164
bb8c093b 4165static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
b481de9c
ZY		 4166{
4167 clear_bit(STATUS_INT_ENABLED, &priv->status);
4168
4169 /* disable interrupts from uCode/NIC to host */
bb8c093b 4170 iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY		 4171
4172 /* acknowledge/clear/reset any interrupts still pending
4173 * from uCode or flow handler (Rx/Tx DMA) */
bb8c093b
CH		 4174 iwl3945_write32(priv, CSR_INT, 0xffffffff);
4175 iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
b481de9c
ZY		 4176 IWL_DEBUG_ISR("Disabled interrupts\n");
4177}
4178
4179static const char *desc_lookup(int i)
4180{
4181 switch (i) {
4182 case 1:
4183 return "FAIL";
4184 case 2:
4185 return "BAD_PARAM";
4186 case 3:
4187 return "BAD_CHECKSUM";
4188 case 4:
4189 return "NMI_INTERRUPT";
4190 case 5:
4191 return "SYSASSERT";
4192 case 6:
4193 return "FATAL_ERROR";
4194 }
4195
4196 return "UNKNOWN";
4197}
4198
4199#define ERROR_START_OFFSET (1 * sizeof(u32))
4200#define ERROR_ELEM_SIZE (7 * sizeof(u32))
4201
bb8c093b 4202static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
b481de9c
ZY		 4203{
4204 u32 i;
4205 u32 desc, time, count, base, data1;
4206 u32 blink1, blink2, ilink1, ilink2;
4207 int rc;
4208
4209 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
4210
bb8c093b 4211 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 4212 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
4213 return;
4214 }
4215
bb8c093b 4216 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 4217 if (rc) {
4218 IWL_WARNING("Can not read from adapter at this time.\n");
4219 return;
4220 }
4221
bb8c093b 4222 count = iwl3945_read_targ_mem(priv, base);
b481de9c
ZY		 4223
4224 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
4225 IWL_ERROR("Start IWL Error Log Dump:\n");
2acae16e 4226 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
b481de9c
ZY		 4227 }
4228
4229 IWL_ERROR("Desc Time asrtPC blink2 "
4230 "ilink1 nmiPC Line\n");
4231 for (i = ERROR_START_OFFSET;
4232 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
4233 i += ERROR_ELEM_SIZE) {
bb8c093b 4234 desc = iwl3945_read_targ_mem(priv, base + i);
b481de9c 4235 time =
bb8c093b 4236 iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
b481de9c 4237 blink1 =
bb8c093b 4238 iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
b481de9c 4239 blink2 =
bb8c093b 4240 iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
b481de9c 4241 ilink1 =
bb8c093b 4242 iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
b481de9c 4243 ilink2 =
bb8c093b 4244 iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
b481de9c 4245 data1 =
bb8c093b 4246 iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
b481de9c
ZY		 4247
4248 IWL_ERROR
4249 ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
4250 desc_lookup(desc), desc, time, blink1, blink2,
4251 ilink1, ilink2, data1);
4252 }
4253
bb8c093b 4254 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4255
4256}
4257
f58177b9 4258#define EVENT_START_OFFSET (6 * sizeof(u32))
b481de9c
ZY		 4259
4260/**
bb8c093b 4261 * iwl3945_print_event_log - Dump error event log to syslog
b481de9c 4262 *
bb8c093b 4263 * NOTE: Must be called with iwl3945_grab_nic_access() already obtained!
b481de9c 4264 */
bb8c093b 4265static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
b481de9c
ZY		 4266 u32 num_events, u32 mode)
4267{
4268 u32 i;
4269 u32 base; /* SRAM byte address of event log header */
4270 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
4271 u32 ptr; /* SRAM byte address of log data */
4272 u32 ev, time, data; /* event log data */
4273
4274 if (num_events == 0)
4275 return;
4276
4277 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
4278
4279 if (mode == 0)
4280 event_size = 2 * sizeof(u32);
4281 else
4282 event_size = 3 * sizeof(u32);
4283
4284 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
4285
4286 /* "time" is actually "data" for mode 0 (no timestamp).
4287 * place event id # at far right for easier visual parsing. */
4288 for (i = 0; i < num_events; i++) {
bb8c093b 4289 ev = iwl3945_read_targ_mem(priv, ptr);
b481de9c 4290 ptr += sizeof(u32);
bb8c093b 4291 time = iwl3945_read_targ_mem(priv, ptr);
b481de9c
ZY		 4292 ptr += sizeof(u32);
4293 if (mode == 0)
4294 IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
4295 else {
bb8c093b 4296 data = iwl3945_read_targ_mem(priv, ptr);
b481de9c
ZY		 4297 ptr += sizeof(u32);
4298 IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
4299 }
4300 }
4301}
4302
bb8c093b 4303static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
b481de9c
ZY		 4304{
4305 int rc;
4306 u32 base; /* SRAM byte address of event log header */
4307 u32 capacity; /* event log capacity in # entries */
4308 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
4309 u32 num_wraps; /* # times uCode wrapped to top of log */
4310 u32 next_entry; /* index of next entry to be written by uCode */
4311 u32 size; /* # entries that we'll print */
4312
4313 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 4314 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 4315 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
4316 return;
4317 }
4318
bb8c093b 4319 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 4320 if (rc) {
4321 IWL_WARNING("Can not read from adapter at this time.\n");
4322 return;
4323 }
4324
4325 /* event log header */
bb8c093b
CH		 4326 capacity = iwl3945_read_targ_mem(priv, base);
4327 mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
4328 num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
4329 next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
b481de9c
ZY		 4330
4331 size = num_wraps ? capacity : next_entry;
4332
4333 /* bail out if nothing in log */
4334 if (size == 0) {
583fab37 4335 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
bb8c093b 4336 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4337 return;
4338 }
4339
583fab37 4340 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
b481de9c
ZY		 4341 size, num_wraps);
4342
4343 /* if uCode has wrapped back to top of log, start at the oldest entry,
4344 * i.e the next one that uCode would fill. */
4345 if (num_wraps)
bb8c093b 4346 iwl3945_print_event_log(priv, next_entry,
b481de9c
ZY		 4347 capacity - next_entry, mode);
4348
4349 /* (then/else) start at top of log */
bb8c093b 4350 iwl3945_print_event_log(priv, 0, next_entry, mode);
b481de9c 4351
bb8c093b 4352 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4353}
4354
4355/**
bb8c093b 4356 * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
b481de9c 4357 */
bb8c093b 4358static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
b481de9c 4359{
bb8c093b 4360 /* Set the FW error flag -- cleared on iwl3945_down */
b481de9c
ZY		 4361 set_bit(STATUS_FW_ERROR, &priv->status);
4362
4363 /* Cancel currently queued command. */
4364 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
4365
c8b0e6e1 4366#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 4367 if (iwl3945_debug_level & IWL_DL_FW_ERRORS) {
4368 iwl3945_dump_nic_error_log(priv);
4369 iwl3945_dump_nic_event_log(priv);
4370 iwl3945_print_rx_config_cmd(&priv->staging_rxon);
b481de9c
ZY		 4371 }
4372#endif
4373
4374 wake_up_interruptible(&priv->wait_command_queue);
4375
4376 /* Keep the restart process from trying to send host
4377 * commands by clearing the INIT status bit */
4378 clear_bit(STATUS_READY, &priv->status);
4379
4380 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
4381 IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
4382 "Restarting adapter due to uCode error.\n");
4383
bb8c093b 4384 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 4385 memcpy(&priv->recovery_rxon, &priv->active_rxon,
4386 sizeof(priv->recovery_rxon));
4387 priv->error_recovering = 1;
4388 }
4389 queue_work(priv->workqueue, &priv->restart);
4390 }
4391}
4392
bb8c093b 4393static void iwl3945_error_recovery(struct iwl3945_priv *priv)
b481de9c
ZY		 4394{
4395 unsigned long flags;
4396
4397 memcpy(&priv->staging_rxon, &priv->recovery_rxon,
4398 sizeof(priv->staging_rxon));
4399 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 4400 iwl3945_commit_rxon(priv);
b481de9c 4401
bb8c093b 4402 iwl3945_add_station(priv, priv->bssid, 1, 0);
b481de9c
ZY		 4403
4404 spin_lock_irqsave(&priv->lock, flags);
4405 priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
4406 priv->error_recovering = 0;
4407 spin_unlock_irqrestore(&priv->lock, flags);
4408}
4409
bb8c093b 4410static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
b481de9c
ZY		 4411{
4412 u32 inta, handled = 0;
4413 u32 inta_fh;
4414 unsigned long flags;
c8b0e6e1 4415#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 4416 u32 inta_mask;
4417#endif
4418
4419 spin_lock_irqsave(&priv->lock, flags);
4420
4421 /* Ack/clear/reset pending uCode interrupts.
4422 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
4423 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
bb8c093b
CH		 4424 inta = iwl3945_read32(priv, CSR_INT);
4425 iwl3945_write32(priv, CSR_INT, inta);
b481de9c
ZY		 4426
4427 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
4428 * Any new interrupts that happen after this, either while we're
4429 * in this tasklet, or later, will show up in next ISR/tasklet. */
bb8c093b
CH		 4430 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
4431 iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 4432
c8b0e6e1 4433#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4434 if (iwl3945_debug_level & IWL_DL_ISR) {
9fbab516
BC		 4435 /* just for debug */
4436 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
b481de9c
ZY		 4437 IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4438 inta, inta_mask, inta_fh);
4439 }
4440#endif
4441
4442 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
4443 * atomic, make sure that inta covers all the interrupts that
4444 * we've discovered, even if FH interrupt came in just after
4445 * reading CSR_INT. */
6f83eaa1 4446 if (inta_fh & CSR39_FH_INT_RX_MASK)
b481de9c 4447 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 4448 if (inta_fh & CSR39_FH_INT_TX_MASK)
b481de9c
ZY		 4449 inta |= CSR_INT_BIT_FH_TX;
4450
4451 /* Now service all interrupt bits discovered above. */
4452 if (inta & CSR_INT_BIT_HW_ERR) {
4453 IWL_ERROR("Microcode HW error detected. Restarting.\n");
4454
4455 /* Tell the device to stop sending interrupts */
bb8c093b 4456 iwl3945_disable_interrupts(priv);
b481de9c 4457
bb8c093b 4458 iwl3945_irq_handle_error(priv);
b481de9c
ZY		 4459
4460 handled |= CSR_INT_BIT_HW_ERR;
4461
4462 spin_unlock_irqrestore(&priv->lock, flags);
4463
4464 return;
4465 }
4466
c8b0e6e1 4467#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4468 if (iwl3945_debug_level & (IWL_DL_ISR)) {
b481de9c 4469 /* NIC fires this, but we don't use it, redundant with WAKEUP */
25c03d8e
JP		 4470 if (inta & CSR_INT_BIT_SCD)
4471 IWL_DEBUG_ISR("Scheduler finished to transmit "
4472 "the frame/frames.\n");
b481de9c
ZY		 4473
4474 /* Alive notification via Rx interrupt will do the real work */
4475 if (inta & CSR_INT_BIT_ALIVE)
4476 IWL_DEBUG_ISR("Alive interrupt\n");
4477 }
4478#endif
4479 /* Safely ignore these bits for debug checks below */
25c03d8e 4480 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c
ZY		 4481
4482 /* HW RF KILL switch toggled (4965 only) */
4483 if (inta & CSR_INT_BIT_RF_KILL) {
4484 int hw_rf_kill = 0;
bb8c093b 4485 if (!(iwl3945_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY		 4486 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
4487 hw_rf_kill = 1;
4488
4489 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR,
4490 "RF_KILL bit toggled to %s.\n",
4491 hw_rf_kill ? "disable radio":"enable radio");
4492
4493 /* Queue restart only if RF_KILL switch was set to "kill"
4494 * when we loaded driver, and is now set to "enable".
4495 * After we're Alive, RF_KILL gets handled by
3230455d 4496 * iwl3945_rx_card_state_notif() */
53e49093
ZY		 4497 if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) {
4498 clear_bit(STATUS_RF_KILL_HW, &priv->status);
b481de9c 4499 queue_work(priv->workqueue, &priv->restart);
53e49093 4500 }
b481de9c
ZY		 4501
4502 handled |= CSR_INT_BIT_RF_KILL;
4503 }
4504
4505 /* Chip got too hot and stopped itself (4965 only) */
4506 if (inta & CSR_INT_BIT_CT_KILL) {
4507 IWL_ERROR("Microcode CT kill error detected.\n");
4508 handled |= CSR_INT_BIT_CT_KILL;
4509 }
4510
4511 /* Error detected by uCode */
4512 if (inta & CSR_INT_BIT_SW_ERR) {
4513 IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
4514 inta);
bb8c093b 4515 iwl3945_irq_handle_error(priv);
b481de9c
ZY		 4516 handled |= CSR_INT_BIT_SW_ERR;
4517 }
4518
4519 /* uCode wakes up after power-down sleep */
4520 if (inta & CSR_INT_BIT_WAKEUP) {
4521 IWL_DEBUG_ISR("Wakeup interrupt\n");
bb8c093b
CH		 4522 iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
4523 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
4524 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
4525 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
4526 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
4527 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
4528 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
b481de9c
ZY		 4529
4530 handled |= CSR_INT_BIT_WAKEUP;
4531 }
4532
4533 /* All uCode command responses, including Tx command responses,
4534 * Rx "responses" (frame-received notification), and other
4535 * notifications from uCode come through here*/
4536 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
bb8c093b 4537 iwl3945_rx_handle(priv);
b481de9c
ZY		 4538 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
4539 }
4540
4541 if (inta & CSR_INT_BIT_FH_TX) {
4542 IWL_DEBUG_ISR("Tx interrupt\n");
4543
bb8c093b
CH		 4544 iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
4545 if (!iwl3945_grab_nic_access(priv)) {
4546 iwl3945_write_direct32(priv,
b481de9c
ZY		 4547 FH_TCSR_CREDIT
4548 (ALM_FH_SRVC_CHNL), 0x0);
bb8c093b 4549 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4550 }
4551 handled |= CSR_INT_BIT_FH_TX;
4552 }
4553
4554 if (inta & ~handled)
4555 IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
4556
4557 if (inta & ~CSR_INI_SET_MASK) {
4558 IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
4559 inta & ~CSR_INI_SET_MASK);
4560 IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
4561 }
4562
4563 /* Re-enable all interrupts */
0359facc
MA		 4564 /* only Re-enable if disabled by irq */
4565 if (test_bit(STATUS_INT_ENABLED, &priv->status))
4566 iwl3945_enable_interrupts(priv);
b481de9c 4567
c8b0e6e1 4568#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 4569 if (iwl3945_debug_level & (IWL_DL_ISR)) {
4570 inta = iwl3945_read32(priv, CSR_INT);
4571 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
4572 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY		 4573 IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4574 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
4575 }
4576#endif
4577 spin_unlock_irqrestore(&priv->lock, flags);
4578}
4579
bb8c093b 4580static irqreturn_t iwl3945_isr(int irq, void *data)
b481de9c 4581{
bb8c093b 4582 struct iwl3945_priv *priv = data;
b481de9c
ZY		 4583 u32 inta, inta_mask;
4584 u32 inta_fh;
4585 if (!priv)
4586 return IRQ_NONE;
4587
4588 spin_lock(&priv->lock);
4589
4590 /* Disable (but don't clear!) interrupts here to avoid
4591 * back-to-back ISRs and sporadic interrupts from our NIC.
4592 * If we have something to service, the tasklet will re-enable ints.
4593 * If we *don't* have something, we'll re-enable before leaving here. */
bb8c093b
CH		 4594 inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */
4595 iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY		 4596
4597 /* Discover which interrupts are active/pending */
bb8c093b
CH		 4598 inta = iwl3945_read32(priv, CSR_INT);
4599 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY		 4600
4601 /* Ignore interrupt if there's nothing in NIC to service.
4602 * This may be due to IRQ shared with another device,
4603 * or due to sporadic interrupts thrown from our NIC. */
4604 if (!inta && !inta_fh) {
4605 IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
4606 goto none;
4607 }
4608
4609 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
4610 /* Hardware disappeared */
4611 IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta);
cb4da1a3 4612 goto unplugged;
b481de9c
ZY		 4613 }
4614
4615 IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4616 inta, inta_mask, inta_fh);
4617
25c03d8e
JP		 4618 inta &= ~CSR_INT_BIT_SCD;
4619
bb8c093b 4620 /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
25c03d8e
JP		 4621 if (likely(inta || inta_fh))
4622 tasklet_schedule(&priv->irq_tasklet);
cb4da1a3 4623unplugged:
b481de9c
ZY		 4624 spin_unlock(&priv->lock);
4625
4626 return IRQ_HANDLED;
4627
4628 none:
4629 /* re-enable interrupts here since we don't have anything to service. */
0359facc
MA		 4630 /* only Re-enable if disabled by irq */
4631 if (test_bit(STATUS_INT_ENABLED, &priv->status))
4632 iwl3945_enable_interrupts(priv);
b481de9c
ZY		 4633 spin_unlock(&priv->lock);
4634 return IRQ_NONE;
4635}
4636
4637/************************** EEPROM BANDS ****************************
4638 *
bb8c093b 4639 * The iwl3945_eeprom_band definitions below provide the mapping from the
b481de9c
ZY		 4640 * EEPROM contents to the specific channel number supported for each
4641 * band.
4642 *
bb8c093b 4643 * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3
b481de9c
ZY		 4644 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
4645 * The specific geography and calibration information for that channel
4646 * is contained in the eeprom map itself.
4647 *
4648 * During init, we copy the eeprom information and channel map
4649 * information into priv->channel_info_24/52 and priv->channel_map_24/52
4650 *
4651 * channel_map_24/52 provides the index in the channel_info array for a
4652 * given channel. We have to have two separate maps as there is channel
4653 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
4654 * band_2
4655 *
4656 * A value of 0xff stored in the channel_map indicates that the channel
4657 * is not supported by the hardware at all.
4658 *
4659 * A value of 0xfe in the channel_map indicates that the channel is not
4660 * valid for Tx with the current hardware. This means that
4661 * while the system can tune and receive on a given channel, it may not
4662 * be able to associate or transmit any frames on that
4663 * channel. There is no corresponding channel information for that
4664 * entry.
4665 *
4666 *********************************************************************/
4667
4668/* 2.4 GHz */
bb8c093b 4669static const u8 iwl3945_eeprom_band_1[14] = {
b481de9c
ZY		 4670 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
4671};
4672
4673/* 5.2 GHz bands */
9fbab516 4674static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
b481de9c
ZY		 4675 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
4676};
4677
9fbab516 4678static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
b481de9c
ZY		 4679 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
4680};
4681
bb8c093b 4682static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
b481de9c
ZY		 4683 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
4684};
4685
bb8c093b 4686static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
b481de9c
ZY		 4687 145, 149, 153, 157, 161, 165
4688};
4689
bb8c093b 4690static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
b481de9c 4691 int *eeprom_ch_count,
bb8c093b 4692 const struct iwl3945_eeprom_channel
b481de9c
ZY		 4693 **eeprom_ch_info,
4694 const u8 **eeprom_ch_index)
4695{
4696 switch (band) {
4697 case 1: /* 2.4GHz band */
bb8c093b 4698 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
b481de9c 4699 *eeprom_ch_info = priv->eeprom.band_1_channels;
bb8c093b 4700 *eeprom_ch_index = iwl3945_eeprom_band_1;
b481de9c 4701 break;
9fbab516 4702 case 2: /* 4.9GHz band */
bb8c093b 4703 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
b481de9c 4704 *eeprom_ch_info = priv->eeprom.band_2_channels;
bb8c093b 4705 *eeprom_ch_index = iwl3945_eeprom_band_2;
b481de9c
ZY		 4706 break;
4707 case 3: /* 5.2GHz band */
bb8c093b 4708 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
b481de9c 4709 *eeprom_ch_info = priv->eeprom.band_3_channels;
bb8c093b 4710 *eeprom_ch_index = iwl3945_eeprom_band_3;
b481de9c 4711 break;
9fbab516 4712 case 4: /* 5.5GHz band */
bb8c093b 4713 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
b481de9c 4714 *eeprom_ch_info = priv->eeprom.band_4_channels;
bb8c093b 4715 *eeprom_ch_index = iwl3945_eeprom_band_4;
b481de9c 4716 break;
9fbab516 4717 case 5: /* 5.7GHz band */
bb8c093b 4718 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
b481de9c 4719 *eeprom_ch_info = priv->eeprom.band_5_channels;
bb8c093b 4720 *eeprom_ch_index = iwl3945_eeprom_band_5;
b481de9c
ZY		 4721 break;
4722 default:
4723 BUG();
4724 return;
4725 }
4726}
4727
6440adb5
CB		 4728/**
4729 * iwl3945_get_channel_info - Find driver's private channel info
4730 *
4731 * Based on band and channel number.
4732 */
bb8c093b 4733const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv,
8318d78a 4734 enum ieee80211_band band, u16 channel)
b481de9c
ZY		 4735{
4736 int i;
4737
8318d78a
JB		 4738 switch (band) {
4739 case IEEE80211_BAND_5GHZ:
b481de9c
ZY		 4740 for (i = 14; i < priv->channel_count; i++) {
4741 if (priv->channel_info[i].channel == channel)
4742 return &priv->channel_info[i];
4743 }
4744 break;
4745
8318d78a 4746 case IEEE80211_BAND_2GHZ:
b481de9c
ZY		 4747 if (channel >= 1 && channel <= 14)
4748 return &priv->channel_info[channel - 1];
4749 break;
8318d78a
JB		 4750 case IEEE80211_NUM_BANDS:
4751 WARN_ON(1);
b481de9c
ZY		 4752 }
4753
4754 return NULL;
4755}
4756
4757#define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
4758 ? # x " " : "")
4759
6440adb5
CB		 4760/**
4761 * iwl3945_init_channel_map - Set up driver's info for all possible channels
4762 */
bb8c093b 4763static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
b481de9c
ZY		 4764{
4765 int eeprom_ch_count = 0;
4766 const u8 *eeprom_ch_index = NULL;
bb8c093b 4767 const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL;
b481de9c 4768 int band, ch;
bb8c093b 4769 struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 4770
4771 if (priv->channel_count) {
4772 IWL_DEBUG_INFO("Channel map already initialized.\n");
4773 return 0;
4774 }
4775
4776 if (priv->eeprom.version < 0x2f) {
4777 IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
4778 priv->eeprom.version);
4779 return -EINVAL;
4780 }
4781
4782 IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
4783
4784 priv->channel_count =
bb8c093b
CH		 4785 ARRAY_SIZE(iwl3945_eeprom_band_1) +
4786 ARRAY_SIZE(iwl3945_eeprom_band_2) +
4787 ARRAY_SIZE(iwl3945_eeprom_band_3) +
4788 ARRAY_SIZE(iwl3945_eeprom_band_4) +
4789 ARRAY_SIZE(iwl3945_eeprom_band_5);
b481de9c
ZY		 4790
4791 IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
4792
bb8c093b 4793 priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) *
b481de9c
ZY		 4794 priv->channel_count, GFP_KERNEL);
4795 if (!priv->channel_info) {
4796 IWL_ERROR("Could not allocate channel_info\n");
4797 priv->channel_count = 0;
4798 return -ENOMEM;
4799 }
4800
4801 ch_info = priv->channel_info;
4802
4803 /* Loop through the 5 EEPROM bands adding them in order to the
4804 * channel map we maintain (that contains additional information than
4805 * what just in the EEPROM) */
4806 for (band = 1; band <= 5; band++) {
4807
bb8c093b 4808 iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
b481de9c
ZY		 4809 &eeprom_ch_info, &eeprom_ch_index);
4810
4811 /* Loop through each band adding each of the channels */
4812 for (ch = 0; ch < eeprom_ch_count; ch++) {
4813 ch_info->channel = eeprom_ch_index[ch];
8318d78a
JB		 4814 ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
4815 IEEE80211_BAND_5GHZ;
b481de9c
ZY		 4816
4817 /* permanently store EEPROM's channel regulatory flags
4818 * and max power in channel info database. */
4819 ch_info->eeprom = eeprom_ch_info[ch];
4820
4821 /* Copy the run-time flags so they are there even on
4822 * invalid channels */
4823 ch_info->flags = eeprom_ch_info[ch].flags;
4824
4825 if (!(is_channel_valid(ch_info))) {
4826 IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
4827 "No traffic\n",
4828 ch_info->channel,
4829 ch_info->flags,
4830 is_channel_a_band(ch_info) ?
4831 "5.2" : "2.4");
4832 ch_info++;
4833 continue;
4834 }
4835
4836 /* Initialize regulatory-based run-time data */
4837 ch_info->max_power_avg = ch_info->curr_txpow =
4838 eeprom_ch_info[ch].max_power_avg;
4839 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
4840 ch_info->min_power = 0;
4841
fe7c4040 4842 IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
b481de9c
ZY		 4843 " %ddBm): Ad-Hoc %ssupported\n",
4844 ch_info->channel,
4845 is_channel_a_band(ch_info) ?
4846 "5.2" : "2.4",
8211ef78 4847 CHECK_AND_PRINT(VALID),
b481de9c
ZY		 4848 CHECK_AND_PRINT(IBSS),
4849 CHECK_AND_PRINT(ACTIVE),
4850 CHECK_AND_PRINT(RADAR),
4851 CHECK_AND_PRINT(WIDE),
b481de9c
ZY		 4852 CHECK_AND_PRINT(DFS),
4853 eeprom_ch_info[ch].flags,
4854 eeprom_ch_info[ch].max_power_avg,
4855 ((eeprom_ch_info[ch].
4856 flags & EEPROM_CHANNEL_IBSS)
4857 && !(eeprom_ch_info[ch].
4858 flags & EEPROM_CHANNEL_RADAR))
4859 ? "" : "not ");
4860
4861 /* Set the user_txpower_limit to the highest power
4862 * supported by any channel */
4863 if (eeprom_ch_info[ch].max_power_avg >
4864 priv->user_txpower_limit)
4865 priv->user_txpower_limit =
4866 eeprom_ch_info[ch].max_power_avg;
4867
4868 ch_info++;
4869 }
4870 }
4871
6440adb5 4872 /* Set up txpower settings in driver for all channels */
b481de9c
ZY		 4873 if (iwl3945_txpower_set_from_eeprom(priv))
4874 return -EIO;
4875
4876 return 0;
4877}
4878
849e0dce
RC		 4879/*
4880 * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
4881 */
4882static void iwl3945_free_channel_map(struct iwl3945_priv *priv)
4883{
4884 kfree(priv->channel_info);
4885 priv->channel_count = 0;
4886}
4887
b481de9c
ZY		 4888/* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
4889 * sending probe req. This should be set long enough to hear probe responses
4890 * from more than one AP. */
4891#define IWL_ACTIVE_DWELL_TIME_24 (20) /* all times in msec */
4892#define IWL_ACTIVE_DWELL_TIME_52 (10)
4893
4894/* For faster active scanning, scan will move to the next channel if fewer than
4895 * PLCP_QUIET_THRESH packets are heard on this channel within
4896 * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
4897 * time if it's a quiet channel (nothing responded to our probe, and there's
4898 * no other traffic).
4899 * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
4900#define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
4901#define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(5) /* msec */
4902
4903/* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
4904 * Must be set longer than active dwell time.
4905 * For the most reliable scan, set > AP beacon interval (typically 100msec). */
4906#define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
4907#define IWL_PASSIVE_DWELL_TIME_52 (10)
4908#define IWL_PASSIVE_DWELL_BASE (100)
4909#define IWL_CHANNEL_TUNE_TIME 5
4910
8318d78a
JB		 4911static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv,
4912 enum ieee80211_band band)
b481de9c 4913{
8318d78a 4914 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 4915 return IWL_ACTIVE_DWELL_TIME_52;
4916 else
4917 return IWL_ACTIVE_DWELL_TIME_24;
4918}
4919
8318d78a
JB		 4920static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv,
4921 enum ieee80211_band band)
b481de9c 4922{
8318d78a
JB		 4923 u16 active = iwl3945_get_active_dwell_time(priv, band);
4924 u16 passive = (band == IEEE80211_BAND_2GHZ) ?
b481de9c
ZY		 4925 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
4926 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
4927
bb8c093b 4928 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 4929 /* If we're associated, we clamp the maximum passive
4930 * dwell time to be 98% of the beacon interval (minus
4931 * 2 * channel tune time) */
4932 passive = priv->beacon_int;
4933 if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
4934 passive = IWL_PASSIVE_DWELL_BASE;
4935 passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
4936 }
4937
4938 if (passive <= active)
4939 passive = active + 1;
4940
4941 return passive;
4942}
4943
8318d78a
JB		 4944static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv,
4945 enum ieee80211_band band,
b481de9c 4946 u8 is_active, u8 direct_mask,
bb8c093b 4947 struct iwl3945_scan_channel *scan_ch)
b481de9c
ZY		 4948{
4949 const struct ieee80211_channel *channels = NULL;
8318d78a 4950 const struct ieee80211_supported_band *sband;
bb8c093b 4951 const struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 4952 u16 passive_dwell = 0;
4953 u16 active_dwell = 0;
4954 int added, i;
4955
8318d78a
JB		 4956 sband = iwl3945_get_band(priv, band);
4957 if (!sband)
b481de9c
ZY		 4958 return 0;
4959
8318d78a 4960 channels = sband->channels;
b481de9c 4961
8318d78a
JB		 4962 active_dwell = iwl3945_get_active_dwell_time(priv, band);
4963 passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
b481de9c 4964
8318d78a 4965 for (i = 0, added = 0; i < sband->n_channels; i++) {
182e2e66
JB		 4966 if (channels[i].flags & IEEE80211_CHAN_DISABLED)
4967 continue;
4968
8318d78a 4969 scan_ch->channel = channels[i].hw_value;
b481de9c 4970
8318d78a 4971 ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
b481de9c 4972 if (!is_channel_valid(ch_info)) {
66b5004d 4973 IWL_DEBUG_SCAN("Channel %d is INVALID for this band.\n",
b481de9c
ZY		 4974 scan_ch->channel);
4975 continue;
4976 }
4977
4978 if (!is_active || is_channel_passive(ch_info) ||
8318d78a 4979 (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN))
b481de9c
ZY		 4980 scan_ch->type = 0; /* passive */
4981 else
4982 scan_ch->type = 1; /* active */
4983
4984 if (scan_ch->type & 1)
4985 scan_ch->type |= (direct_mask << 1);
4986
b481de9c
ZY		 4987 scan_ch->active_dwell = cpu_to_le16(active_dwell);
4988 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
4989
9fbab516 4990 /* Set txpower levels to defaults */
b481de9c
ZY		 4991 scan_ch->tpc.dsp_atten = 110;
4992 /* scan_pwr_info->tpc.dsp_atten; */
4993
4994 /*scan_pwr_info->tpc.tx_gain; */
8318d78a 4995 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 4996 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
4997 else {
4998 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
4999 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
9fbab516 5000 * power level:
8a1b0245 5001 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
b481de9c
ZY		 5002 */
5003 }
5004
5005 IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
5006 scan_ch->channel,
5007 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
5008 (scan_ch->type & 1) ?
5009 active_dwell : passive_dwell);
5010
5011 scan_ch++;
5012 added++;
5013 }
5014
5015 IWL_DEBUG_SCAN("total channels to scan %d \n", added);
5016 return added;
5017}
5018
bb8c093b 5019static void iwl3945_init_hw_rates(struct iwl3945_priv *priv,
b481de9c
ZY		 5020 struct ieee80211_rate *rates)
5021{
5022 int i;
5023
5024 for (i = 0; i < IWL_RATE_COUNT; i++) {
8318d78a
JB		 5025 rates[i].bitrate = iwl3945_rates[i].ieee * 5;
5026 rates[i].hw_value = i; /* Rate scaling will work on indexes */
5027 rates[i].hw_value_short = i;
5028 rates[i].flags = 0;
5029 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
b481de9c 5030 /*
8318d78a 5031 * If CCK != 1M then set short preamble rate flag.
b481de9c 5032 */
bb8c093b 5033 rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
8318d78a 5034 0 : IEEE80211_RATE_SHORT_PREAMBLE;
b481de9c 5035 }
b481de9c
ZY		 5036 }
5037}
5038
5039/**
bb8c093b 5040 * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
b481de9c 5041 */
bb8c093b 5042static int iwl3945_init_geos(struct iwl3945_priv *priv)
b481de9c 5043{
bb8c093b 5044 struct iwl3945_channel_info *ch;
8211ef78 5045 struct ieee80211_supported_band *sband;
b481de9c
ZY		 5046 struct ieee80211_channel *channels;
5047 struct ieee80211_channel *geo_ch;
5048 struct ieee80211_rate *rates;
5049 int i = 0;
b481de9c 5050
8318d78a
JB		 5051 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
5052 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
b481de9c
ZY		 5053 IWL_DEBUG_INFO("Geography modes already initialized.\n");
5054 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
5055 return 0;
5056 }
5057
b481de9c
ZY		 5058 channels = kzalloc(sizeof(struct ieee80211_channel) *
5059 priv->channel_count, GFP_KERNEL);
8318d78a 5060 if (!channels)
b481de9c 5061 return -ENOMEM;
b481de9c 5062
8211ef78 5063 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
b481de9c
ZY		 5064 GFP_KERNEL);
5065 if (!rates) {
b481de9c
ZY		 5066 kfree(channels);
5067 return -ENOMEM;
5068 }
5069
b481de9c 5070 /* 5.2GHz channels start after the 2.4GHz channels */
8211ef78
TW		 5071 sband = &priv->bands[IEEE80211_BAND_5GHZ];
5072 sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
5073 /* just OFDM */
5074 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
5075 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
5076
5077 sband = &priv->bands[IEEE80211_BAND_2GHZ];
5078 sband->channels = channels;
5079 /* OFDM & CCK */
5080 sband->bitrates = rates;
5081 sband->n_bitrates = IWL_RATE_COUNT;
b481de9c
ZY		 5082
5083 priv->ieee_channels = channels;
5084 priv->ieee_rates = rates;
5085
bb8c093b 5086 iwl3945_init_hw_rates(priv, rates);
b481de9c 5087
8211ef78 5088 for (i = 0; i < priv->channel_count; i++) {
b481de9c
ZY		 5089 ch = &priv->channel_info[i];
5090
8211ef78
TW		 5091 /* FIXME: might be removed if scan is OK*/
5092 if (!is_channel_valid(ch))
b481de9c 5093 continue;
b481de9c
ZY		 5094
5095 if (is_channel_a_band(ch))
8211ef78 5096 sband = &priv->bands[IEEE80211_BAND_5GHZ];
8318d78a 5097 else
8211ef78 5098 sband = &priv->bands[IEEE80211_BAND_2GHZ];
b481de9c 5099
8211ef78
TW		 5100 geo_ch = &sband->channels[sband->n_channels++];
5101
5102 geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
8318d78a
JB		 5103 geo_ch->max_power = ch->max_power_avg;
5104 geo_ch->max_antenna_gain = 0xff;
7b72304d 5105 geo_ch->hw_value = ch->channel;
b481de9c
ZY		 5106
5107 if (is_channel_valid(ch)) {
8318d78a
JB		 5108 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
5109 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
b481de9c 5110
8318d78a
JB		 5111 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
5112 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
b481de9c
ZY		 5113
5114 if (ch->flags & EEPROM_CHANNEL_RADAR)
8318d78a 5115 geo_ch->flags |= IEEE80211_CHAN_RADAR;
b481de9c
ZY		 5116
5117 if (ch->max_power_avg > priv->max_channel_txpower_limit)
5118 priv->max_channel_txpower_limit =
5119 ch->max_power_avg;
8211ef78 5120 } else {
8318d78a 5121 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
8211ef78
TW		 5122 }
5123
5124 /* Save flags for reg domain usage */
5125 geo_ch->orig_flags = geo_ch->flags;
5126
5127 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
5128 ch->channel, geo_ch->center_freq,
5129 is_channel_a_band(ch) ? "5.2" : "2.4",
5130 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
5131 "restricted" : "valid",
5132 geo_ch->flags);
b481de9c
ZY		 5133 }
5134
82b9a121
TW		 5135 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
5136 priv->cfg->sku & IWL_SKU_A) {
b481de9c
ZY		 5137 printk(KERN_INFO DRV_NAME
5138 ": Incorrectly detected BG card as ABG. Please send "
5139 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
5140 priv->pci_dev->device, priv->pci_dev->subsystem_device);
82b9a121 5141 priv->cfg->sku &= ~IWL_SKU_A;
b481de9c
ZY		 5142 }
5143
5144 printk(KERN_INFO DRV_NAME
5145 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
8318d78a
JB		 5146 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
5147 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
b481de9c 5148
e0e0a67e
JL		 5149 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
5150 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
5151 &priv->bands[IEEE80211_BAND_2GHZ];
5152 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
5153 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
5154 &priv->bands[IEEE80211_BAND_5GHZ];
b481de9c 5155
b481de9c
ZY		 5156 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
5157
5158 return 0;
5159}
5160
849e0dce
RC		 5161/*
5162 * iwl3945_free_geos - undo allocations in iwl3945_init_geos
5163 */
5164static void iwl3945_free_geos(struct iwl3945_priv *priv)
5165{
849e0dce
RC		 5166 kfree(priv->ieee_channels);
5167 kfree(priv->ieee_rates);
5168 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
5169}
5170
b481de9c
ZY		 5171/******************************************************************************
5172 *
5173 * uCode download functions
5174 *
5175 ******************************************************************************/
5176
bb8c093b 5177static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv)
b481de9c 5178{
98c92211
TW		 5179 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
5180 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
5181 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
5182 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
5183 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
5184 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY		 5185}
5186
5187/**
bb8c093b 5188 * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
b481de9c
ZY		 5189 * looking at all data.
5190 */
bb8c093b 5191static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 * image, u32 len)
b481de9c
ZY		 5192{
5193 u32 val;
5194 u32 save_len = len;
5195 int rc = 0;
5196 u32 errcnt;
5197
5198 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5199
bb8c093b 5200 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5201 if (rc)
5202 return rc;
5203
bb8c093b 5204 iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
b481de9c
ZY		 5205
5206 errcnt = 0;
5207 for (; len > 0; len -= sizeof(u32), image++) {
5208 /* read data comes through single port, auto-incr addr */
5209 /* NOTE: Use the debugless read so we don't flood kernel log
5210 * if IWL_DL_IO is set */
bb8c093b 5211 val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY		 5212 if (val != le32_to_cpu(*image)) {
5213 IWL_ERROR("uCode INST section is invalid at "
5214 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5215 save_len - len, val, le32_to_cpu(*image));
5216 rc = -EIO;
5217 errcnt++;
5218 if (errcnt >= 20)
5219 break;
5220 }
5221 }
5222
bb8c093b 5223 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5224
5225 if (!errcnt)
bc434dd2 5226 IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
b481de9c
ZY		 5227
5228 return rc;
5229}
5230
5231
5232/**
bb8c093b 5233 * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
b481de9c
ZY		 5234 * using sample data 100 bytes apart. If these sample points are good,
5235 * it's a pretty good bet that everything between them is good, too.
5236 */
bb8c093b 5237static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len)
b481de9c
ZY		 5238{
5239 u32 val;
5240 int rc = 0;
5241 u32 errcnt = 0;
5242 u32 i;
5243
5244 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5245
bb8c093b 5246 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5247 if (rc)
5248 return rc;
5249
5250 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
5251 /* read data comes through single port, auto-incr addr */
5252 /* NOTE: Use the debugless read so we don't flood kernel log
5253 * if IWL_DL_IO is set */
bb8c093b 5254 iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
b481de9c 5255 i + RTC_INST_LOWER_BOUND);
bb8c093b 5256 val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY		 5257 if (val != le32_to_cpu(*image)) {
5258#if 0 /* Enable this if you want to see details */
5259 IWL_ERROR("uCode INST section is invalid at "
5260 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5261 i, val, *image);
5262#endif
5263 rc = -EIO;
5264 errcnt++;
5265 if (errcnt >= 3)
5266 break;
5267 }
5268 }
5269
bb8c093b 5270 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5271
5272 return rc;
5273}
5274
5275
5276/**
bb8c093b 5277 * iwl3945_verify_ucode - determine which instruction image is in SRAM,
b481de9c
ZY		 5278 * and verify its contents
5279 */
bb8c093b 5280static int iwl3945_verify_ucode(struct iwl3945_priv *priv)
b481de9c
ZY		 5281{
5282 __le32 *image;
5283 u32 len;
5284 int rc = 0;
5285
5286 /* Try bootstrap */
5287 image = (__le32 *)priv->ucode_boot.v_addr;
5288 len = priv->ucode_boot.len;
bb8c093b 5289 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5290 if (rc == 0) {
5291 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
5292 return 0;
5293 }
5294
5295 /* Try initialize */
5296 image = (__le32 *)priv->ucode_init.v_addr;
5297 len = priv->ucode_init.len;
bb8c093b 5298 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5299 if (rc == 0) {
5300 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
5301 return 0;
5302 }
5303
5304 /* Try runtime/protocol */
5305 image = (__le32 *)priv->ucode_code.v_addr;
5306 len = priv->ucode_code.len;
bb8c093b 5307 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5308 if (rc == 0) {
5309 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
5310 return 0;
5311 }
5312
5313 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
5314
9fbab516
BC		 5315 /* Since nothing seems to match, show first several data entries in
5316 * instruction SRAM, so maybe visual inspection will give a clue.
5317 * Selection of bootstrap image (vs. other images) is arbitrary. */
b481de9c
ZY		 5318 image = (__le32 *)priv->ucode_boot.v_addr;
5319 len = priv->ucode_boot.len;
bb8c093b 5320 rc = iwl3945_verify_inst_full(priv, image, len);
b481de9c
ZY		 5321
5322 return rc;
5323}
5324
5325
5326/* check contents of special bootstrap uCode SRAM */
bb8c093b 5327static int iwl3945_verify_bsm(struct iwl3945_priv *priv)
b481de9c
ZY		 5328{
5329 __le32 *image = priv->ucode_boot.v_addr;
5330 u32 len = priv->ucode_boot.len;
5331 u32 reg;
5332 u32 val;
5333
5334 IWL_DEBUG_INFO("Begin verify bsm\n");
5335
5336 /* verify BSM SRAM contents */
bb8c093b 5337 val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG);
b481de9c
ZY		 5338 for (reg = BSM_SRAM_LOWER_BOUND;
5339 reg < BSM_SRAM_LOWER_BOUND + len;
5340 reg += sizeof(u32), image ++) {
bb8c093b 5341 val = iwl3945_read_prph(priv, reg);
b481de9c
ZY		 5342 if (val != le32_to_cpu(*image)) {
5343 IWL_ERROR("BSM uCode verification failed at "
5344 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
5345 BSM_SRAM_LOWER_BOUND,
5346 reg - BSM_SRAM_LOWER_BOUND, len,
5347 val, le32_to_cpu(*image));
5348 return -EIO;
5349 }
5350 }
5351
5352 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
5353
5354 return 0;
5355}
5356
5357/**
bb8c093b 5358 * iwl3945_load_bsm - Load bootstrap instructions
b481de9c
ZY		 5359 *
5360 * BSM operation:
5361 *
5362 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
5363 * in special SRAM that does not power down during RFKILL. When powering back
5364 * up after power-saving sleeps (or during initial uCode load), the BSM loads
5365 * the bootstrap program into the on-board processor, and starts it.
5366 *
5367 * The bootstrap program loads (via DMA) instructions and data for a new
5368 * program from host DRAM locations indicated by the host driver in the
5369 * BSM_DRAM_* registers. Once the new program is loaded, it starts
5370 * automatically.
5371 *
5372 * When initializing the NIC, the host driver points the BSM to the
5373 * "initialize" uCode image. This uCode sets up some internal data, then
5374 * notifies host via "initialize alive" that it is complete.
5375 *
5376 * The host then replaces the BSM_DRAM_* pointer values to point to the
5377 * normal runtime uCode instructions and a backup uCode data cache buffer
5378 * (filled initially with starting data values for the on-board processor),
5379 * then triggers the "initialize" uCode to load and launch the runtime uCode,
5380 * which begins normal operation.
5381 *
5382 * When doing a power-save shutdown, runtime uCode saves data SRAM into
5383 * the backup data cache in DRAM before SRAM is powered down.
5384 *
5385 * When powering back up, the BSM loads the bootstrap program. This reloads
5386 * the runtime uCode instructions and the backup data cache into SRAM,
5387 * and re-launches the runtime uCode from where it left off.
5388 */
bb8c093b 5389static int iwl3945_load_bsm(struct iwl3945_priv *priv)
b481de9c
ZY		 5390{
5391 __le32 *image = priv->ucode_boot.v_addr;
5392 u32 len = priv->ucode_boot.len;
5393 dma_addr_t pinst;
5394 dma_addr_t pdata;
5395 u32 inst_len;
5396 u32 data_len;
5397 int rc;
5398 int i;
5399 u32 done;
5400 u32 reg_offset;
5401
5402 IWL_DEBUG_INFO("Begin load bsm\n");
5403
5404 /* make sure bootstrap program is no larger than BSM's SRAM size */
5405 if (len > IWL_MAX_BSM_SIZE)
5406 return -EINVAL;
5407
5408 /* Tell bootstrap uCode where to find the "Initialize" uCode
9fbab516 5409 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
bb8c093b 5410 * NOTE: iwl3945_initialize_alive_start() will replace these values,
b481de9c
ZY		 5411 * after the "initialize" uCode has run, to point to
5412 * runtime/protocol instructions and backup data cache. */
5413 pinst = priv->ucode_init.p_addr;
5414 pdata = priv->ucode_init_data.p_addr;
5415 inst_len = priv->ucode_init.len;
5416 data_len = priv->ucode_init_data.len;
5417
bb8c093b 5418 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5419 if (rc)
5420 return rc;
5421
bb8c093b
CH		 5422 iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5423 iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5424 iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
5425 iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
b481de9c
ZY		 5426
5427 /* Fill BSM memory with bootstrap instructions */
5428 for (reg_offset = BSM_SRAM_LOWER_BOUND;
5429 reg_offset < BSM_SRAM_LOWER_BOUND + len;
5430 reg_offset += sizeof(u32), image++)
bb8c093b 5431 _iwl3945_write_prph(priv, reg_offset,
b481de9c
ZY		 5432 le32_to_cpu(*image));
5433
bb8c093b 5434 rc = iwl3945_verify_bsm(priv);
b481de9c 5435 if (rc) {
bb8c093b 5436 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5437 return rc;
5438 }
5439
5440 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
bb8c093b
CH		 5441 iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
5442 iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG,
b481de9c 5443 RTC_INST_LOWER_BOUND);
bb8c093b 5444 iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
b481de9c
ZY		 5445
5446 /* Load bootstrap code into instruction SRAM now,
5447 * to prepare to load "initialize" uCode */
bb8c093b 5448 iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY		 5449 BSM_WR_CTRL_REG_BIT_START);
5450
5451 /* Wait for load of bootstrap uCode to finish */
5452 for (i = 0; i < 100; i++) {
bb8c093b 5453 done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG);
b481de9c
ZY		 5454 if (!(done & BSM_WR_CTRL_REG_BIT_START))
5455 break;
5456 udelay(10);
5457 }
5458 if (i < 100)
5459 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
5460 else {
5461 IWL_ERROR("BSM write did not complete!\n");
5462 return -EIO;
5463 }
5464
5465 /* Enable future boot loads whenever power management unit triggers it
5466 * (e.g. when powering back up after power-save shutdown) */
bb8c093b 5467 iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY		 5468 BSM_WR_CTRL_REG_BIT_START_EN);
5469
bb8c093b 5470 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5471
5472 return 0;
5473}
5474
bb8c093b 5475static void iwl3945_nic_start(struct iwl3945_priv *priv)
b481de9c
ZY		 5476{
5477 /* Remove all resets to allow NIC to operate */
bb8c093b 5478 iwl3945_write32(priv, CSR_RESET, 0);
b481de9c
ZY		 5479}
5480
5481/**
bb8c093b 5482 * iwl3945_read_ucode - Read uCode images from disk file.
b481de9c
ZY		 5483 *
5484 * Copy into buffers for card to fetch via bus-mastering
5485 */
bb8c093b 5486static int iwl3945_read_ucode(struct iwl3945_priv *priv)
b481de9c 5487{
bb8c093b 5488 struct iwl3945_ucode *ucode;
90e759d1 5489 int ret = 0;
b481de9c
ZY		 5490 const struct firmware *ucode_raw;
5491 /* firmware file name contains uCode/driver compatibility version */
4bf775cd 5492 const char *name = priv->cfg->fw_name;
b481de9c
ZY		 5493 u8 *src;
5494 size_t len;
5495 u32 ver, inst_size, data_size, init_size, init_data_size, boot_size;
5496
5497 /* Ask kernel firmware_class module to get the boot firmware off disk.
5498 * request_firmware() is synchronous, file is in memory on return. */
90e759d1
TW		 5499 ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev);
5500 if (ret < 0) {
5501 IWL_ERROR("%s firmware file req failed: Reason %d\n",
5502 name, ret);
b481de9c
ZY		 5503 goto error;
5504 }
5505
5506 IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
5507 name, ucode_raw->size);
5508
5509 /* Make sure that we got at least our header! */
5510 if (ucode_raw->size < sizeof(*ucode)) {
5511 IWL_ERROR("File size way too small!\n");
90e759d1 5512 ret = -EINVAL;
b481de9c
ZY		 5513 goto err_release;
5514 }
5515
5516 /* Data from ucode file: header followed by uCode images */
5517 ucode = (void *)ucode_raw->data;
5518
5519 ver = le32_to_cpu(ucode->ver);
5520 inst_size = le32_to_cpu(ucode->inst_size);
5521 data_size = le32_to_cpu(ucode->data_size);
5522 init_size = le32_to_cpu(ucode->init_size);
5523 init_data_size = le32_to_cpu(ucode->init_data_size);
5524 boot_size = le32_to_cpu(ucode->boot_size);
5525
5526 IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver);
bc434dd2
IS		 5527 IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
5528 IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
5529 IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
5530 IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
5531 IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
b481de9c
ZY		 5532
5533 /* Verify size of file vs. image size info in file's header */
5534 if (ucode_raw->size < sizeof(*ucode) +
5535 inst_size + data_size + init_size +
5536 init_data_size + boot_size) {
5537
5538 IWL_DEBUG_INFO("uCode file size %d too small\n",
5539 (int)ucode_raw->size);
90e759d1 5540 ret = -EINVAL;
b481de9c
ZY		 5541 goto err_release;
5542 }
5543
5544 /* Verify that uCode images will fit in card's SRAM */
5545 if (inst_size > IWL_MAX_INST_SIZE) {
90e759d1
TW		 5546 IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
5547 inst_size);
5548 ret = -EINVAL;
b481de9c
ZY		 5549 goto err_release;
5550 }
5551
5552 if (data_size > IWL_MAX_DATA_SIZE) {
90e759d1
TW		 5553 IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
5554 data_size);
5555 ret = -EINVAL;
b481de9c
ZY		 5556 goto err_release;
5557 }
5558 if (init_size > IWL_MAX_INST_SIZE) {
90e759d1
TW		 5559 IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
5560 init_size);
5561 ret = -EINVAL;
b481de9c
ZY		 5562 goto err_release;
5563 }
5564 if (init_data_size > IWL_MAX_DATA_SIZE) {
90e759d1
TW		 5565 IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
5566 init_data_size);
5567 ret = -EINVAL;
b481de9c
ZY		 5568 goto err_release;
5569 }
5570 if (boot_size > IWL_MAX_BSM_SIZE) {
90e759d1
TW		 5571 IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
5572 boot_size);
5573 ret = -EINVAL;
b481de9c
ZY		 5574 goto err_release;
5575 }
5576
5577 /* Allocate ucode buffers for card's bus-master loading ... */
5578
5579 /* Runtime instructions and 2 copies of data:
5580 * 1) unmodified from disk
5581 * 2) backup cache for save/restore during power-downs */
5582 priv->ucode_code.len = inst_size;
98c92211 5583 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY		 5584
5585 priv->ucode_data.len = data_size;
98c92211 5586 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY		 5587
5588 priv->ucode_data_backup.len = data_size;
98c92211 5589 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 5590
90e759d1
TW		 5591 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
5592 !priv->ucode_data_backup.v_addr)
5593 goto err_pci_alloc;
b481de9c
ZY		 5594
5595 /* Initialization instructions and data */
90e759d1
TW		 5596 if (init_size && init_data_size) {
5597 priv->ucode_init.len = init_size;
98c92211 5598 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW		 5599
5600 priv->ucode_init_data.len = init_data_size;
98c92211 5601 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW		 5602
5603 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
5604 goto err_pci_alloc;
5605 }
b481de9c
ZY		 5606
5607 /* Bootstrap (instructions only, no data) */
90e759d1
TW		 5608 if (boot_size) {
5609 priv->ucode_boot.len = boot_size;
98c92211 5610 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 5611
90e759d1
TW		 5612 if (!priv->ucode_boot.v_addr)
5613 goto err_pci_alloc;
5614 }
b481de9c
ZY		 5615
5616 /* Copy images into buffers for card's bus-master reads ... */
5617
5618 /* Runtime instructions (first block of data in file) */
5619 src = &ucode->data[0];
5620 len = priv->ucode_code.len;
90e759d1 5621 IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c
ZY		 5622 memcpy(priv->ucode_code.v_addr, src, len);
5623 IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
5624 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
5625
5626 /* Runtime data (2nd block)
bb8c093b 5627 * NOTE: Copy into backup buffer will be done in iwl3945_up() */
b481de9c
ZY		 5628 src = &ucode->data[inst_size];
5629 len = priv->ucode_data.len;
90e759d1 5630 IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY		 5631 memcpy(priv->ucode_data.v_addr, src, len);
5632 memcpy(priv->ucode_data_backup.v_addr, src, len);
5633
5634 /* Initialization instructions (3rd block) */
5635 if (init_size) {
5636 src = &ucode->data[inst_size + data_size];
5637 len = priv->ucode_init.len;
90e759d1
TW		 5638 IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
5639 len);
b481de9c
ZY		 5640 memcpy(priv->ucode_init.v_addr, src, len);
5641 }
5642
5643 /* Initialization data (4th block) */
5644 if (init_data_size) {
5645 src = &ucode->data[inst_size + data_size + init_size];
5646 len = priv->ucode_init_data.len;
5647 IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
5648 (int)len);
5649 memcpy(priv->ucode_init_data.v_addr, src, len);
5650 }
5651
5652 /* Bootstrap instructions (5th block) */
5653 src = &ucode->data[inst_size + data_size + init_size + init_data_size];
5654 len = priv->ucode_boot.len;
5655 IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
5656 (int)len);
5657 memcpy(priv->ucode_boot.v_addr, src, len);
5658
5659 /* We have our copies now, allow OS release its copies */
5660 release_firmware(ucode_raw);
5661 return 0;
5662
5663 err_pci_alloc:
5664 IWL_ERROR("failed to allocate pci memory\n");
90e759d1 5665 ret = -ENOMEM;
bb8c093b 5666 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY		 5667
5668 err_release:
5669 release_firmware(ucode_raw);
5670
5671 error:
90e759d1 5672 return ret;
b481de9c
ZY		 5673}
5674
5675
5676/**
bb8c093b 5677 * iwl3945_set_ucode_ptrs - Set uCode address location
b481de9c
ZY		 5678 *
5679 * Tell initialization uCode where to find runtime uCode.
5680 *
5681 * BSM registers initially contain pointers to initialization uCode.
5682 * We need to replace them to load runtime uCode inst and data,
5683 * and to save runtime data when powering down.
5684 */
bb8c093b 5685static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv)
b481de9c
ZY		 5686{
5687 dma_addr_t pinst;
5688 dma_addr_t pdata;
5689 int rc = 0;
5690 unsigned long flags;
5691
5692 /* bits 31:0 for 3945 */
5693 pinst = priv->ucode_code.p_addr;
5694 pdata = priv->ucode_data_backup.p_addr;
5695
5696 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5697 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5698 if (rc) {
5699 spin_unlock_irqrestore(&priv->lock, flags);
5700 return rc;
5701 }
5702
5703 /* Tell bootstrap uCode where to find image to load */
bb8c093b
CH		 5704 iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5705 iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5706 iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
b481de9c
ZY		 5707 priv->ucode_data.len);
5708
5709 /* Inst bytecount must be last to set up, bit 31 signals uCode
5710 * that all new ptr/size info is in place */
bb8c093b 5711 iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
b481de9c
ZY		 5712 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
5713
bb8c093b 5714 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5715
5716 spin_unlock_irqrestore(&priv->lock, flags);
5717
5718 IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
5719
5720 return rc;
5721}
5722
5723/**
bb8c093b 5724 * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
b481de9c
ZY		 5725 *
5726 * Called after REPLY_ALIVE notification received from "initialize" uCode.
5727 *
b481de9c 5728 * Tell "initialize" uCode to go ahead and load the runtime uCode.
9fbab516 5729 */
bb8c093b 5730static void iwl3945_init_alive_start(struct iwl3945_priv *priv)
b481de9c
ZY		 5731{
5732 /* Check alive response for "valid" sign from uCode */
5733 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
5734 /* We had an error bringing up the hardware, so take it
5735 * all the way back down so we can try again */
5736 IWL_DEBUG_INFO("Initialize Alive failed.\n");
5737 goto restart;
5738 }
5739
5740 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
5741 * This is a paranoid check, because we would not have gotten the
5742 * "initialize" alive if code weren't properly loaded. */
bb8c093b 5743 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY		 5744 /* Runtime instruction load was bad;
5745 * take it all the way back down so we can try again */
5746 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
5747 goto restart;
5748 }
5749
5750 /* Send pointers to protocol/runtime uCode image ... init code will
5751 * load and launch runtime uCode, which will send us another "Alive"
5752 * notification. */
5753 IWL_DEBUG_INFO("Initialization Alive received.\n");
bb8c093b 5754 if (iwl3945_set_ucode_ptrs(priv)) {
b481de9c
ZY		 5755 /* Runtime instruction load won't happen;
5756 * take it all the way back down so we can try again */
5757 IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
5758 goto restart;
5759 }
5760 return;
5761
5762 restart:
5763 queue_work(priv->workqueue, &priv->restart);
5764}
5765
5766
5767/**
bb8c093b 5768 * iwl3945_alive_start - called after REPLY_ALIVE notification received
b481de9c 5769 * from protocol/runtime uCode (initialization uCode's
bb8c093b 5770 * Alive gets handled by iwl3945_init_alive_start()).
b481de9c 5771 */
bb8c093b 5772static void iwl3945_alive_start(struct iwl3945_priv *priv)
b481de9c
ZY		 5773{
5774 int rc = 0;
5775 int thermal_spin = 0;
5776 u32 rfkill;
5777
5778 IWL_DEBUG_INFO("Runtime Alive received.\n");
5779
5780 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
5781 /* We had an error bringing up the hardware, so take it
5782 * all the way back down so we can try again */
5783 IWL_DEBUG_INFO("Alive failed.\n");
5784 goto restart;
5785 }
5786
5787 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
5788 * This is a paranoid check, because we would not have gotten the
5789 * "runtime" alive if code weren't properly loaded. */
bb8c093b 5790 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY		 5791 /* Runtime instruction load was bad;
5792 * take it all the way back down so we can try again */
5793 IWL_DEBUG_INFO("Bad runtime uCode load.\n");
5794 goto restart;
5795 }
5796
bb8c093b 5797 iwl3945_clear_stations_table(priv);
b481de9c 5798
bb8c093b 5799 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5800 if (rc) {
5801 IWL_WARNING("Can not read rfkill status from adapter\n");
5802 return;
5803 }
5804
bb8c093b 5805 rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG);
b481de9c 5806 IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
bb8c093b 5807 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5808
5809 if (rfkill & 0x1) {
5810 clear_bit(STATUS_RF_KILL_HW, &priv->status);
5811 /* if rfkill is not on, then wait for thermal
5812 * sensor in adapter to kick in */
bb8c093b 5813 while (iwl3945_hw_get_temperature(priv) == 0) {
b481de9c
ZY		 5814 thermal_spin++;
5815 udelay(10);
5816 }
5817
5818 if (thermal_spin)
5819 IWL_DEBUG_INFO("Thermal calibration took %dus\n",
5820 thermal_spin * 10);
5821 } else
5822 set_bit(STATUS_RF_KILL_HW, &priv->status);
5823
9fbab516 5824 /* After the ALIVE response, we can send commands to 3945 uCode */
b481de9c
ZY		 5825 set_bit(STATUS_ALIVE, &priv->status);
5826
5827 /* Clear out the uCode error bit if it is set */
5828 clear_bit(STATUS_FW_ERROR, &priv->status);
5829
bb8c093b 5830 if (iwl3945_is_rfkill(priv))
b481de9c
ZY		 5831 return;
5832
36d6825b 5833 ieee80211_wake_queues(priv->hw);
b481de9c
ZY		 5834
5835 priv->active_rate = priv->rates_mask;
5836 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
5837
bb8c093b 5838 iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
b481de9c 5839
bb8c093b
CH		 5840 if (iwl3945_is_associated(priv)) {
5841 struct iwl3945_rxon_cmd *active_rxon =
5842 (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
b481de9c
ZY		 5843
5844 memcpy(&priv->staging_rxon, &priv->active_rxon,
5845 sizeof(priv->staging_rxon));
5846 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5847 } else {
5848 /* Initialize our rx_config data */
bb8c093b 5849 iwl3945_connection_init_rx_config(priv);
b481de9c
ZY		 5850 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
5851 }
5852
9fbab516 5853 /* Configure Bluetooth device coexistence support */
bb8c093b 5854 iwl3945_send_bt_config(priv);
b481de9c
ZY		 5855
5856 /* Configure the adapter for unassociated operation */
bb8c093b 5857 iwl3945_commit_rxon(priv);
b481de9c 5858
b481de9c
ZY		 5859 iwl3945_reg_txpower_periodic(priv);
5860
fe00b5a5
RC		 5861 iwl3945_led_register(priv);
5862
b481de9c 5863 IWL_DEBUG_INFO("ALIVE processing complete.\n");
a9f46786 5864 set_bit(STATUS_READY, &priv->status);
5a66926a 5865 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY		 5866
5867 if (priv->error_recovering)
bb8c093b 5868 iwl3945_error_recovery(priv);
b481de9c 5869
84363e6e 5870 ieee80211_notify_mac(priv->hw, IEEE80211_NOTIFY_RE_ASSOC);
b481de9c
ZY		 5871 return;
5872
5873 restart:
5874 queue_work(priv->workqueue, &priv->restart);
5875}
5876
bb8c093b 5877static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv);
b481de9c 5878
bb8c093b 5879static void __iwl3945_down(struct iwl3945_priv *priv)
b481de9c
ZY		 5880{
5881 unsigned long flags;
5882 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
5883 struct ieee80211_conf *conf = NULL;
5884
5885 IWL_DEBUG_INFO(DRV_NAME " is going down\n");
5886
5887 conf = ieee80211_get_hw_conf(priv->hw);
5888
5889 if (!exit_pending)
5890 set_bit(STATUS_EXIT_PENDING, &priv->status);
5891
ab53d8af 5892 iwl3945_led_unregister(priv);
bb8c093b 5893 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 5894
5895 /* Unblock any waiting calls */
5896 wake_up_interruptible_all(&priv->wait_command_queue);
5897
b481de9c
ZY		 5898 /* Wipe out the EXIT_PENDING status bit if we are not actually
5899 * exiting the module */
5900 if (!exit_pending)
5901 clear_bit(STATUS_EXIT_PENDING, &priv->status);
5902
5903 /* stop and reset the on-board processor */
bb8c093b 5904 iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY		 5905
5906 /* tell the device to stop sending interrupts */
0359facc 5907 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5908 iwl3945_disable_interrupts(priv);
0359facc
MA		 5909 spin_unlock_irqrestore(&priv->lock, flags);
5910 iwl_synchronize_irq(priv);
b481de9c
ZY		 5911
5912 if (priv->mac80211_registered)
5913 ieee80211_stop_queues(priv->hw);
5914
bb8c093b 5915 /* If we have not previously called iwl3945_init() then
b481de9c 5916 * clear all bits but the RF Kill and SUSPEND bits and return */
bb8c093b 5917 if (!iwl3945_is_init(priv)) {
b481de9c
ZY		 5918 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
5919 STATUS_RF_KILL_HW |
5920 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
5921 STATUS_RF_KILL_SW |
9788864e
RC		 5922 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
5923 STATUS_GEO_CONFIGURED |
b481de9c 5924 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
ebef2008
AK		 5925 STATUS_IN_SUSPEND |
5926 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
5927 STATUS_EXIT_PENDING;
b481de9c
ZY		 5928 goto exit;
5929 }
5930
5931 /* ...otherwise clear out all the status bits but the RF Kill and
5932 * SUSPEND bits and continue taking the NIC down. */
5933 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
5934 STATUS_RF_KILL_HW |
5935 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
5936 STATUS_RF_KILL_SW |
9788864e
RC		 5937 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
5938 STATUS_GEO_CONFIGURED |
b481de9c
ZY		 5939 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
5940 STATUS_IN_SUSPEND |
5941 test_bit(STATUS_FW_ERROR, &priv->status) <<
ebef2008
AK		 5942 STATUS_FW_ERROR |
5943 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
5944 STATUS_EXIT_PENDING;
b481de9c
ZY		 5945
5946 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5947 iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY		 5948 spin_unlock_irqrestore(&priv->lock, flags);
5949
bb8c093b
CH		 5950 iwl3945_hw_txq_ctx_stop(priv);
5951 iwl3945_hw_rxq_stop(priv);
b481de9c
ZY		 5952
5953 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH		 5954 if (!iwl3945_grab_nic_access(priv)) {
5955 iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
b481de9c 5956 APMG_CLK_VAL_DMA_CLK_RQT);
bb8c093b 5957 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5958 }
5959 spin_unlock_irqrestore(&priv->lock, flags);
5960
5961 udelay(5);
5962
bb8c093b
CH		 5963 iwl3945_hw_nic_stop_master(priv);
5964 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
5965 iwl3945_hw_nic_reset(priv);
b481de9c
ZY		 5966
5967 exit:
bb8c093b 5968 memset(&priv->card_alive, 0, sizeof(struct iwl3945_alive_resp));
b481de9c
ZY		 5969
5970 if (priv->ibss_beacon)
5971 dev_kfree_skb(priv->ibss_beacon);
5972 priv->ibss_beacon = NULL;
5973
5974 /* clear out any free frames */
bb8c093b 5975 iwl3945_clear_free_frames(priv);
b481de9c
ZY		 5976}
5977
bb8c093b 5978static void iwl3945_down(struct iwl3945_priv *priv)
b481de9c
ZY		 5979{
5980 mutex_lock(&priv->mutex);
bb8c093b 5981 __iwl3945_down(priv);
b481de9c 5982 mutex_unlock(&priv->mutex);
b24d22b1 5983
bb8c093b 5984 iwl3945_cancel_deferred_work(priv);
b481de9c
ZY		 5985}
5986
5987#define MAX_HW_RESTARTS 5
5988
bb8c093b 5989static int __iwl3945_up(struct iwl3945_priv *priv)
b481de9c
ZY		 5990{
5991 int rc, i;
5992
5993 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
5994 IWL_WARNING("Exit pending; will not bring the NIC up\n");
5995 return -EIO;
5996 }
5997
5998 if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
5999 IWL_WARNING("Radio disabled by SW RF kill (module "
6000 "parameter)\n");
e655b9f0
ZY		 6001 return -ENODEV;
6002 }
6003
e903fbd4
RC		 6004 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
6005 IWL_ERROR("ucode not available for device bringup\n");
6006 return -EIO;
6007 }
6008
e655b9f0
ZY		 6009 /* If platform's RF_KILL switch is NOT set to KILL */
6010 if (iwl3945_read32(priv, CSR_GP_CNTRL) &
6011 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
6012 clear_bit(STATUS_RF_KILL_HW, &priv->status);
6013 else {
6014 set_bit(STATUS_RF_KILL_HW, &priv->status);
6015 if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
ebef2008 6016 iwl3945_rfkill_set_hw_state(priv);
e655b9f0
ZY		 6017 IWL_WARNING("Radio disabled by HW RF Kill switch\n");
6018 return -ENODEV;
6019 }
b481de9c 6020 }
ebef2008 6021 iwl3945_rfkill_set_hw_state(priv);
bb8c093b 6022 iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 6023
bb8c093b 6024 rc = iwl3945_hw_nic_init(priv);
b481de9c
ZY		 6025 if (rc) {
6026 IWL_ERROR("Unable to int nic\n");
6027 return rc;
6028 }
6029
6030 /* make sure rfkill handshake bits are cleared */
bb8c093b
CH		 6031 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
6032 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 6033 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
6034
6035 /* clear (again), then enable host interrupts */
bb8c093b
CH		 6036 iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
6037 iwl3945_enable_interrupts(priv);
b481de9c
ZY		 6038
6039 /* really make sure rfkill handshake bits are cleared */
bb8c093b
CH		 6040 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
6041 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 6042
6043 /* Copy original ucode data image from disk into backup cache.
6044 * This will be used to initialize the on-board processor's
6045 * data SRAM for a clean start when the runtime program first loads. */
6046 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 6047 priv->ucode_data.len);
b481de9c 6048
e655b9f0
ZY		 6049 /* We return success when we resume from suspend and rf_kill is on. */
6050 if (test_bit(STATUS_RF_KILL_HW, &priv->status))
6051 return 0;
6052
b481de9c
ZY		 6053 for (i = 0; i < MAX_HW_RESTARTS; i++) {
6054
bb8c093b 6055 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 6056
6057 /* load bootstrap state machine,
6058 * load bootstrap program into processor's memory,
6059 * prepare to load the "initialize" uCode */
bb8c093b 6060 rc = iwl3945_load_bsm(priv);
b481de9c
ZY		 6061
6062 if (rc) {
6063 IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
6064 continue;
6065 }
6066
6067 /* start card; "initialize" will load runtime ucode */
bb8c093b 6068 iwl3945_nic_start(priv);
b481de9c 6069
b481de9c
ZY		 6070 IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
6071
6072 return 0;
6073 }
6074
6075 set_bit(STATUS_EXIT_PENDING, &priv->status);
bb8c093b 6076 __iwl3945_down(priv);
ebef2008 6077 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY		 6078
6079 /* tried to restart and config the device for as long as our
6080 * patience could withstand */
6081 IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
6082 return -EIO;
6083}
6084
6085
6086/*****************************************************************************
6087 *
6088 * Workqueue callbacks
6089 *
6090 *****************************************************************************/
6091
bb8c093b 6092static void iwl3945_bg_init_alive_start(struct work_struct *data)
b481de9c 6093{
bb8c093b
CH		 6094 struct iwl3945_priv *priv =
6095 container_of(data, struct iwl3945_priv, init_alive_start.work);
b481de9c
ZY		 6096
6097 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6098 return;
6099
6100 mutex_lock(&priv->mutex);
bb8c093b 6101 iwl3945_init_alive_start(priv);
b481de9c
ZY		 6102 mutex_unlock(&priv->mutex);
6103}
6104
bb8c093b 6105static void iwl3945_bg_alive_start(struct work_struct *data)
b481de9c 6106{
bb8c093b
CH		 6107 struct iwl3945_priv *priv =
6108 container_of(data, struct iwl3945_priv, alive_start.work);
b481de9c
ZY		 6109
6110 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6111 return;
6112
6113 mutex_lock(&priv->mutex);
bb8c093b 6114 iwl3945_alive_start(priv);
b481de9c
ZY		 6115 mutex_unlock(&priv->mutex);
6116}
6117
bb8c093b 6118static void iwl3945_bg_rf_kill(struct work_struct *work)
b481de9c 6119{
bb8c093b 6120 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill);
b481de9c
ZY		 6121
6122 wake_up_interruptible(&priv->wait_command_queue);
6123
6124 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6125 return;
6126
6127 mutex_lock(&priv->mutex);
6128
bb8c093b 6129 if (!iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 6130 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
6131 "HW and/or SW RF Kill no longer active, restarting "
6132 "device\n");
6133 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
6134 queue_work(priv->workqueue, &priv->restart);
6135 } else {
6136
6137 if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
6138 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
6139 "disabled by SW switch\n");
6140 else
6141 IWL_WARNING("Radio Frequency Kill Switch is On:\n"
6142 "Kill switch must be turned off for "
6143 "wireless networking to work.\n");
6144 }
ebef2008
AK		 6145
6146 iwl3945_rfkill_set_hw_state(priv);
b481de9c
ZY		 6147 mutex_unlock(&priv->mutex);
6148}
6149
5ec03976
AK		 6150static void iwl3945_bg_set_monitor(struct work_struct *work)
6151{
6152 struct iwl3945_priv *priv = container_of(work,
6153 struct iwl3945_priv, set_monitor);
6154
6155 IWL_DEBUG(IWL_DL_STATE, "setting monitor mode\n");
6156
6157 mutex_lock(&priv->mutex);
6158
6159 if (!iwl3945_is_ready(priv))
6160 IWL_DEBUG(IWL_DL_STATE, "leave - not ready\n");
6161 else
6162 if (iwl3945_set_mode(priv, IEEE80211_IF_TYPE_MNTR) != 0)
6163 IWL_ERROR("iwl3945_set_mode() failed\n");
6164
6165 mutex_unlock(&priv->mutex);
6166}
6167
b481de9c
ZY		 6168#define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
6169
bb8c093b 6170static void iwl3945_bg_scan_check(struct work_struct *data)
b481de9c 6171{
bb8c093b
CH		 6172 struct iwl3945_priv *priv =
6173 container_of(data, struct iwl3945_priv, scan_check.work);
b481de9c
ZY		 6174
6175 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6176 return;
6177
6178 mutex_lock(&priv->mutex);
6179 if (test_bit(STATUS_SCANNING, &priv->status) ||
6180 test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6181 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
6182 "Scan completion watchdog resetting adapter (%dms)\n",
6183 jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
15e869d8 6184
b481de9c 6185 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
bb8c093b 6186 iwl3945_send_scan_abort(priv);
b481de9c
ZY		 6187 }
6188 mutex_unlock(&priv->mutex);
6189}
6190
bb8c093b 6191static void iwl3945_bg_request_scan(struct work_struct *data)
b481de9c 6192{
bb8c093b
CH		 6193 struct iwl3945_priv *priv =
6194 container_of(data, struct iwl3945_priv, request_scan);
6195 struct iwl3945_host_cmd cmd = {
b481de9c 6196 .id = REPLY_SCAN_CMD,
bb8c093b 6197 .len = sizeof(struct iwl3945_scan_cmd),
b481de9c
ZY		 6198 .meta.flags = CMD_SIZE_HUGE,
6199 };
6200 int rc = 0;
bb8c093b 6201 struct iwl3945_scan_cmd *scan;
b481de9c
ZY		 6202 struct ieee80211_conf *conf = NULL;
6203 u8 direct_mask;
8318d78a 6204 enum ieee80211_band band;
b481de9c
ZY		 6205
6206 conf = ieee80211_get_hw_conf(priv->hw);
6207
6208 mutex_lock(&priv->mutex);
6209
bb8c093b 6210 if (!iwl3945_is_ready(priv)) {
b481de9c
ZY		 6211 IWL_WARNING("request scan called when driver not ready.\n");
6212 goto done;
6213 }
6214
6215 /* Make sure the scan wasn't cancelled before this queued work
6216 * was given the chance to run... */
6217 if (!test_bit(STATUS_SCANNING, &priv->status))
6218 goto done;
6219
6220 /* This should never be called or scheduled if there is currently
6221 * a scan active in the hardware. */
6222 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
6223 IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
6224 "Ignoring second request.\n");
6225 rc = -EIO;
6226 goto done;
6227 }
6228
6229 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
6230 IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
6231 goto done;
6232 }
6233
6234 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6235 IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
6236 goto done;
6237 }
6238
bb8c093b 6239 if (iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 6240 IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
6241 goto done;
6242 }
6243
6244 if (!test_bit(STATUS_READY, &priv->status)) {
6245 IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
6246 goto done;
6247 }
6248
6249 if (!priv->scan_bands) {
6250 IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
6251 goto done;
6252 }
6253
6254 if (!priv->scan) {
bb8c093b 6255 priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
b481de9c
ZY		 6256 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
6257 if (!priv->scan) {
6258 rc = -ENOMEM;
6259 goto done;
6260 }
6261 }
6262 scan = priv->scan;
bb8c093b 6263 memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
b481de9c
ZY		 6264
6265 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
6266 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
6267
bb8c093b 6268 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 6269 u16 interval = 0;
6270 u32 extra;
6271 u32 suspend_time = 100;
6272 u32 scan_suspend_time = 100;
6273 unsigned long flags;
6274
6275 IWL_DEBUG_INFO("Scanning while associated...\n");
6276
6277 spin_lock_irqsave(&priv->lock, flags);
6278 interval = priv->beacon_int;
6279 spin_unlock_irqrestore(&priv->lock, flags);
6280
6281 scan->suspend_time = 0;
15e869d8 6282 scan->max_out_time = cpu_to_le32(200 * 1024);
b481de9c
ZY		 6283 if (!interval)
6284 interval = suspend_time;
6285 /*
6286 * suspend time format:
6287 * 0-19: beacon interval in usec (time before exec.)
6288 * 20-23: 0
6289 * 24-31: number of beacons (suspend between channels)
6290 */
6291
6292 extra = (suspend_time / interval) << 24;
6293 scan_suspend_time = 0xFF0FFFFF &
6294 (extra | ((suspend_time % interval) * 1024));
6295
6296 scan->suspend_time = cpu_to_le32(scan_suspend_time);
6297 IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
6298 scan_suspend_time, interval);
6299 }
6300
6301 /* We should add the ability for user to lock to PASSIVE ONLY */
6302 if (priv->one_direct_scan) {
6303 IWL_DEBUG_SCAN
6304 ("Kicking off one direct scan for '%s'\n",
bb8c093b 6305 iwl3945_escape_essid(priv->direct_ssid,
b481de9c
ZY		 6306 priv->direct_ssid_len));
6307 scan->direct_scan[0].id = WLAN_EID_SSID;
6308 scan->direct_scan[0].len = priv->direct_ssid_len;
6309 memcpy(scan->direct_scan[0].ssid,
6310 priv->direct_ssid, priv->direct_ssid_len);
6311 direct_mask = 1;
bb8c093b 6312 } else if (!iwl3945_is_associated(priv) && priv->essid_len) {
786b4557
BM		 6313 IWL_DEBUG_SCAN
6314 ("Kicking off one direct scan for '%s' when not associated\n",
6315 iwl3945_escape_essid(priv->essid, priv->essid_len));
b481de9c
ZY		 6316 scan->direct_scan[0].id = WLAN_EID_SSID;
6317 scan->direct_scan[0].len = priv->essid_len;
6318 memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len);
6319 direct_mask = 1;
786b4557
BM		 6320 } else {
6321 IWL_DEBUG_SCAN("Kicking off one indirect scan.\n");
b481de9c 6322 direct_mask = 0;
786b4557 6323 }
b481de9c
ZY		 6324
6325 /* We don't build a direct scan probe request; the uCode will do
6326 * that based on the direct_mask added to each channel entry */
6327 scan->tx_cmd.len = cpu_to_le16(
bb8c093b 6328 iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
18904f58 6329 IWL_MAX_SCAN_SIZE - sizeof(*scan), 0));
b481de9c
ZY		 6330 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
6331 scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
6332 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
6333
6334 /* flags + rate selection */
6335
66b5004d 6336 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
b481de9c
ZY		 6337 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
6338 scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
6339 scan->good_CRC_th = 0;
8318d78a 6340 band = IEEE80211_BAND_2GHZ;
66b5004d 6341 } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
b481de9c
ZY		 6342 scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
6343 scan->good_CRC_th = IWL_GOOD_CRC_TH;
8318d78a 6344 band = IEEE80211_BAND_5GHZ;
66b5004d 6345 } else {
b481de9c
ZY		 6346 IWL_WARNING("Invalid scan band count\n");
6347 goto done;
6348 }
6349
6350 /* select Rx antennas */
6351 scan->flags |= iwl3945_get_antenna_flags(priv);
6352
6353 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR)
6354 scan->filter_flags = RXON_FILTER_PROMISC_MSK;
6355
786b4557 6356 if (direct_mask)
26c0f03f
RC		 6357 scan->channel_count =
6358 iwl3945_get_channels_for_scan(
6359 priv, band, 1, /* active */
6360 direct_mask,
6361 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
786b4557 6362 else
26c0f03f
RC		 6363 scan->channel_count =
6364 iwl3945_get_channels_for_scan(
6365 priv, band, 0, /* passive */
6366 direct_mask,
6367 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
b481de9c
ZY		 6368
6369 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
bb8c093b 6370 scan->channel_count * sizeof(struct iwl3945_scan_channel);
b481de9c
ZY		 6371 cmd.data = scan;
6372 scan->len = cpu_to_le16(cmd.len);
6373
6374 set_bit(STATUS_SCAN_HW, &priv->status);
bb8c093b 6375 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 6376 if (rc)
6377 goto done;
6378
6379 queue_delayed_work(priv->workqueue, &priv->scan_check,
6380 IWL_SCAN_CHECK_WATCHDOG);
6381
6382 mutex_unlock(&priv->mutex);
6383 return;
6384
6385 done:
01ebd063 6386 /* inform mac80211 scan aborted */
b481de9c
ZY		 6387 queue_work(priv->workqueue, &priv->scan_completed);
6388 mutex_unlock(&priv->mutex);
6389}
6390
bb8c093b 6391static void iwl3945_bg_up(struct work_struct *data)
b481de9c 6392{
bb8c093b 6393 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up);
b481de9c
ZY		 6394
6395 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6396 return;
6397
6398 mutex_lock(&priv->mutex);
bb8c093b 6399 __iwl3945_up(priv);
b481de9c
ZY		 6400 mutex_unlock(&priv->mutex);
6401}
6402
bb8c093b 6403static void iwl3945_bg_restart(struct work_struct *data)
b481de9c 6404{
bb8c093b 6405 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart);
b481de9c
ZY		 6406
6407 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6408 return;
6409
bb8c093b 6410 iwl3945_down(priv);
b481de9c
ZY		 6411 queue_work(priv->workqueue, &priv->up);
6412}
6413
bb8c093b 6414static void iwl3945_bg_rx_replenish(struct work_struct *data)
b481de9c 6415{
bb8c093b
CH		 6416 struct iwl3945_priv *priv =
6417 container_of(data, struct iwl3945_priv, rx_replenish);
b481de9c
ZY		 6418
6419 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6420 return;
6421
6422 mutex_lock(&priv->mutex);
bb8c093b 6423 iwl3945_rx_replenish(priv);
b481de9c
ZY		 6424 mutex_unlock(&priv->mutex);
6425}
6426
7878a5a4
MA		 6427#define IWL_DELAY_NEXT_SCAN (HZ*2)
6428
bb8c093b 6429static void iwl3945_bg_post_associate(struct work_struct *data)
b481de9c 6430{
bb8c093b 6431 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv,
b481de9c
ZY		 6432 post_associate.work);
6433
6434 int rc = 0;
6435 struct ieee80211_conf *conf = NULL;
0795af57 6436 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 6437
6438 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
6439 IWL_ERROR("%s Should not be called in AP mode\n", __FUNCTION__);
6440 return;
6441 }
6442
6443
0795af57
JP		 6444 IWL_DEBUG_ASSOC("Associated as %d to: %s\n",
6445 priv->assoc_id,
6446 print_mac(mac, priv->active_rxon.bssid_addr));
b481de9c
ZY		 6447
6448 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6449 return;
6450
6451 mutex_lock(&priv->mutex);
6452
32bfd35d 6453 if (!priv->vif || !priv->is_open) {
6ef89d0a
MA		 6454 mutex_unlock(&priv->mutex);
6455 return;
6456 }
bb8c093b 6457 iwl3945_scan_cancel_timeout(priv, 200);
15e869d8 6458
b481de9c
ZY		 6459 conf = ieee80211_get_hw_conf(priv->hw);
6460
6461 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6462 iwl3945_commit_rxon(priv);
b481de9c 6463
bb8c093b
CH		 6464 memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
6465 iwl3945_setup_rxon_timing(priv);
6466 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY		 6467 sizeof(priv->rxon_timing), &priv->rxon_timing);
6468 if (rc)
6469 IWL_WARNING("REPLY_RXON_TIMING failed - "
6470 "Attempting to continue.\n");
6471
6472 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
6473
6474 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
6475
6476 IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
6477 priv->assoc_id, priv->beacon_int);
6478
6479 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
6480 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
6481 else
6482 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
6483
6484 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
6485 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
6486 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
6487 else
6488 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
6489
6490 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
6491 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
6492
6493 }
6494
bb8c093b 6495 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6496
6497 switch (priv->iw_mode) {
6498 case IEEE80211_IF_TYPE_STA:
bb8c093b 6499 iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
b481de9c
ZY		 6500 break;
6501
6502 case IEEE80211_IF_TYPE_IBSS:
6503
6504 /* clear out the station table */
bb8c093b 6505 iwl3945_clear_stations_table(priv);
b481de9c 6506
bb8c093b
CH		 6507 iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
6508 iwl3945_add_station(priv, priv->bssid, 0, 0);
b481de9c 6509 iwl3945_sync_sta(priv, IWL_STA_ID,
8318d78a 6510 (priv->band == IEEE80211_BAND_5GHZ) ?
b481de9c
ZY		 6511 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
6512 CMD_ASYNC);
bb8c093b
CH		 6513 iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
6514 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 6515
6516 break;
6517
6518 default:
6519 IWL_ERROR("%s Should not be called in %d mode\n",
bc434dd2 6520 __FUNCTION__, priv->iw_mode);
b481de9c
ZY		 6521 break;
6522 }
6523
bb8c093b 6524 iwl3945_sequence_reset(priv);
b481de9c 6525
bb8c093b 6526 iwl3945_activate_qos(priv, 0);
292ae174 6527
7878a5a4
MA		 6528 /* we have just associated, don't start scan too early */
6529 priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
b481de9c
ZY		 6530 mutex_unlock(&priv->mutex);
6531}
6532
bb8c093b 6533static void iwl3945_bg_abort_scan(struct work_struct *work)
b481de9c 6534{
bb8c093b 6535 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan);
b481de9c 6536
bb8c093b 6537 if (!iwl3945_is_ready(priv))
b481de9c
ZY		 6538 return;
6539
6540 mutex_lock(&priv->mutex);
6541
6542 set_bit(STATUS_SCAN_ABORTING, &priv->status);
bb8c093b 6543 iwl3945_send_scan_abort(priv);
b481de9c
ZY		 6544
6545 mutex_unlock(&priv->mutex);
6546}
6547
76bb77e0
ZY		 6548static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf);
6549
bb8c093b 6550static void iwl3945_bg_scan_completed(struct work_struct *work)
b481de9c 6551{
bb8c093b
CH		 6552 struct iwl3945_priv *priv =
6553 container_of(work, struct iwl3945_priv, scan_completed);
b481de9c
ZY		 6554
6555 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
6556
6557 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6558 return;
6559
a0646470
ZY		 6560 if (test_bit(STATUS_CONF_PENDING, &priv->status))
6561 iwl3945_mac_config(priv->hw, ieee80211_get_hw_conf(priv->hw));
76bb77e0 6562
b481de9c
ZY		 6563 ieee80211_scan_completed(priv->hw);
6564
6565 /* Since setting the TXPOWER may have been deferred while
6566 * performing the scan, fire one off */
6567 mutex_lock(&priv->mutex);
bb8c093b 6568 iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 6569 mutex_unlock(&priv->mutex);
6570}
6571
6572/*****************************************************************************
6573 *
6574 * mac80211 entry point functions
6575 *
6576 *****************************************************************************/
6577
5a66926a
ZY		 6578#define UCODE_READY_TIMEOUT (2 * HZ)
6579
bb8c093b 6580static int iwl3945_mac_start(struct ieee80211_hw *hw)
b481de9c 6581{
bb8c093b 6582 struct iwl3945_priv *priv = hw->priv;
5a66926a 6583 int ret;
b481de9c
ZY		 6584
6585 IWL_DEBUG_MAC80211("enter\n");
6586
5a66926a
ZY		 6587 if (pci_enable_device(priv->pci_dev)) {
6588 IWL_ERROR("Fail to pci_enable_device\n");
6589 return -ENODEV;
6590 }
6591 pci_restore_state(priv->pci_dev);
6592 pci_enable_msi(priv->pci_dev);
6593
6594 ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
6595 DRV_NAME, priv);
6596 if (ret) {
6597 IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq);
6598 goto out_disable_msi;
6599 }
6600
b481de9c
ZY		 6601 /* we should be verifying the device is ready to be opened */
6602 mutex_lock(&priv->mutex);
6603
5a66926a
ZY		 6604 memset(&priv->staging_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
6605 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
6606 * ucode filename and max sizes are card-specific. */
6607
6608 if (!priv->ucode_code.len) {
6609 ret = iwl3945_read_ucode(priv);
6610 if (ret) {
6611 IWL_ERROR("Could not read microcode: %d\n", ret);
6612 mutex_unlock(&priv->mutex);
6613 goto out_release_irq;
6614 }
6615 }
b481de9c 6616
e655b9f0 6617 ret = __iwl3945_up(priv);
b481de9c
ZY		 6618
6619 mutex_unlock(&priv->mutex);
5a66926a 6620
e655b9f0
ZY		 6621 if (ret)
6622 goto out_release_irq;
6623
6624 IWL_DEBUG_INFO("Start UP work.\n");
6625
6626 if (test_bit(STATUS_IN_SUSPEND, &priv->status))
6627 return 0;
6628
5a66926a
ZY		 6629 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
6630 * mac80211 will not be run successfully. */
6631 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
6632 test_bit(STATUS_READY, &priv->status),
6633 UCODE_READY_TIMEOUT);
6634 if (!ret) {
6635 if (!test_bit(STATUS_READY, &priv->status)) {
6636 IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n",
6637 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6638 ret = -ETIMEDOUT;
6639 goto out_release_irq;
6640 }
6641 }
6642
e655b9f0 6643 priv->is_open = 1;
b481de9c
ZY		 6644 IWL_DEBUG_MAC80211("leave\n");
6645 return 0;
5a66926a
ZY		 6646
6647out_release_irq:
6648 free_irq(priv->pci_dev->irq, priv);
6649out_disable_msi:
6650 pci_disable_msi(priv->pci_dev);
e655b9f0
ZY		 6651 pci_disable_device(priv->pci_dev);
6652 priv->is_open = 0;
6653 IWL_DEBUG_MAC80211("leave - failed\n");
5a66926a 6654 return ret;
b481de9c
ZY		 6655}
6656
bb8c093b 6657static void iwl3945_mac_stop(struct ieee80211_hw *hw)
b481de9c 6658{
bb8c093b 6659 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6660
6661 IWL_DEBUG_MAC80211("enter\n");
6ef89d0a 6662
e655b9f0
ZY		 6663 if (!priv->is_open) {
6664 IWL_DEBUG_MAC80211("leave - skip\n");
6665 return;
6666 }
6667
b481de9c 6668 priv->is_open = 0;
5a66926a
ZY		 6669
6670 if (iwl3945_is_ready_rf(priv)) {
e655b9f0
ZY		 6671 /* stop mac, cancel any scan request and clear
6672 * RXON_FILTER_ASSOC_MSK BIT
6673 */
5a66926a
ZY		 6674 mutex_lock(&priv->mutex);
6675 iwl3945_scan_cancel_timeout(priv, 100);
6676 cancel_delayed_work(&priv->post_associate);
fde3571f 6677 mutex_unlock(&priv->mutex);
fde3571f
MA		 6678 }
6679
5a66926a
ZY		 6680 iwl3945_down(priv);
6681
6682 flush_workqueue(priv->workqueue);
6683 free_irq(priv->pci_dev->irq, priv);
6684 pci_disable_msi(priv->pci_dev);
6685 pci_save_state(priv->pci_dev);
6686 pci_disable_device(priv->pci_dev);
6ef89d0a 6687
b481de9c 6688 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 6689}
6690
e039fa4a 6691static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 6692{
bb8c093b 6693 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6694
6695 IWL_DEBUG_MAC80211("enter\n");
6696
b481de9c 6697 IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 6698 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 6699
e039fa4a 6700 if (iwl3945_tx_skb(priv, skb))
b481de9c
ZY		 6701 dev_kfree_skb_any(skb);
6702
6703 IWL_DEBUG_MAC80211("leave\n");
6704 return 0;
6705}
6706
bb8c093b 6707static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
b481de9c
ZY		 6708 struct ieee80211_if_init_conf *conf)
6709{
bb8c093b 6710 struct iwl3945_priv *priv = hw->priv;
b481de9c 6711 unsigned long flags;
0795af57 6712 DECLARE_MAC_BUF(mac);
b481de9c 6713
32bfd35d 6714 IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
b481de9c 6715
32bfd35d
JB		 6716 if (priv->vif) {
6717 IWL_DEBUG_MAC80211("leave - vif != NULL\n");
864792e3 6718 return -EOPNOTSUPP;
b481de9c
ZY		 6719 }
6720
6721 spin_lock_irqsave(&priv->lock, flags);
32bfd35d 6722 priv->vif = conf->vif;
b481de9c
ZY		 6723
6724 spin_unlock_irqrestore(&priv->lock, flags);
6725
6726 mutex_lock(&priv->mutex);
864792e3
TW		 6727
6728 if (conf->mac_addr) {
6729 IWL_DEBUG_MAC80211("Set: %s\n", print_mac(mac, conf->mac_addr));
6730 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
6731 }
6732
5a66926a
ZY		 6733 if (iwl3945_is_ready(priv))
6734 iwl3945_set_mode(priv, conf->type);
b481de9c 6735
b481de9c
ZY		 6736 mutex_unlock(&priv->mutex);
6737
5a66926a 6738 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 6739 return 0;
6740}
6741
6742/**
bb8c093b 6743 * iwl3945_mac_config - mac80211 config callback
b481de9c
ZY		 6744 *
6745 * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
6746 * be set inappropriately and the driver currently sets the hardware up to
6747 * use it whenever needed.
6748 */
bb8c093b 6749static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
b481de9c 6750{
bb8c093b
CH		 6751 struct iwl3945_priv *priv = hw->priv;
6752 const struct iwl3945_channel_info *ch_info;
b481de9c 6753 unsigned long flags;
76bb77e0 6754 int ret = 0;
b481de9c
ZY		 6755
6756 mutex_lock(&priv->mutex);
8318d78a 6757 IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
b481de9c 6758
12342c47
ZY		 6759 priv->add_radiotap = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
6760
bb8c093b 6761 if (!iwl3945_is_ready(priv)) {
b481de9c 6762 IWL_DEBUG_MAC80211("leave - not ready\n");
76bb77e0
ZY		 6763 ret = -EIO;
6764 goto out;
b481de9c
ZY		 6765 }
6766
bb8c093b 6767 if (unlikely(!iwl3945_param_disable_hw_scan &&
b481de9c 6768 test_bit(STATUS_SCANNING, &priv->status))) {
a0646470
ZY		 6769 IWL_DEBUG_MAC80211("leave - scanning\n");
6770 set_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 6771 mutex_unlock(&priv->mutex);
a0646470 6772 return 0;
b481de9c
ZY		 6773 }
6774
6775 spin_lock_irqsave(&priv->lock, flags);
6776
8318d78a
JB		 6777 ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
6778 conf->channel->hw_value);
b481de9c 6779 if (!is_channel_valid(ch_info)) {
66b5004d 6780 IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this band.\n",
8318d78a 6781 conf->channel->hw_value, conf->channel->band);
b481de9c
ZY		 6782 IWL_DEBUG_MAC80211("leave - invalid channel\n");
6783 spin_unlock_irqrestore(&priv->lock, flags);
76bb77e0
ZY		 6784 ret = -EINVAL;
6785 goto out;
b481de9c
ZY		 6786 }
6787
8318d78a 6788 iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
b481de9c 6789
8318d78a 6790 iwl3945_set_flags_for_phymode(priv, conf->channel->band);
b481de9c
ZY		 6791
6792 /* The list of supported rates and rate mask can be different
6793 * for each phymode; since the phymode may have changed, reset
6794 * the rate mask to what mac80211 lists */
bb8c093b 6795 iwl3945_set_rate(priv);
b481de9c
ZY		 6796
6797 spin_unlock_irqrestore(&priv->lock, flags);
6798
6799#ifdef IEEE80211_CONF_CHANNEL_SWITCH
6800 if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
bb8c093b 6801 iwl3945_hw_channel_switch(priv, conf->channel);
76bb77e0 6802 goto out;
b481de9c
ZY		 6803 }
6804#endif
6805
bb8c093b 6806 iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
b481de9c
ZY		 6807
6808 if (!conf->radio_enabled) {
6809 IWL_DEBUG_MAC80211("leave - radio disabled\n");
76bb77e0 6810 goto out;
b481de9c
ZY		 6811 }
6812
bb8c093b 6813 if (iwl3945_is_rfkill(priv)) {
b481de9c 6814 IWL_DEBUG_MAC80211("leave - RF kill\n");
76bb77e0
ZY		 6815 ret = -EIO;
6816 goto out;
b481de9c
ZY		 6817 }
6818
bb8c093b 6819 iwl3945_set_rate(priv);
b481de9c
ZY		 6820
6821 if (memcmp(&priv->active_rxon,
6822 &priv->staging_rxon, sizeof(priv->staging_rxon)))
bb8c093b 6823 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6824 else
6825 IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
6826
6827 IWL_DEBUG_MAC80211("leave\n");
6828
76bb77e0 6829out:
a0646470 6830 clear_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 6831 mutex_unlock(&priv->mutex);
76bb77e0 6832 return ret;
b481de9c
ZY		 6833}
6834
bb8c093b 6835static void iwl3945_config_ap(struct iwl3945_priv *priv)
b481de9c
ZY		 6836{
6837 int rc = 0;
6838
d986bcd1 6839 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY		 6840 return;
6841
6842 /* The following should be done only at AP bring up */
5d1e2325 6843 if (!(iwl3945_is_associated(priv))) {
b481de9c
ZY		 6844
6845 /* RXON - unassoc (to set timing command) */
6846 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6847 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6848
6849 /* RXON Timing */
bb8c093b
CH		 6850 memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
6851 iwl3945_setup_rxon_timing(priv);
6852 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY		 6853 sizeof(priv->rxon_timing), &priv->rxon_timing);
6854 if (rc)
6855 IWL_WARNING("REPLY_RXON_TIMING failed - "
6856 "Attempting to continue.\n");
6857
6858 /* FIXME: what should be the assoc_id for AP? */
6859 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
6860 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
6861 priv->staging_rxon.flags |=
6862 RXON_FLG_SHORT_PREAMBLE_MSK;
6863 else
6864 priv->staging_rxon.flags &=
6865 ~RXON_FLG_SHORT_PREAMBLE_MSK;
6866
6867 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
6868 if (priv->assoc_capability &
6869 WLAN_CAPABILITY_SHORT_SLOT_TIME)
6870 priv->staging_rxon.flags |=
6871 RXON_FLG_SHORT_SLOT_MSK;
6872 else
6873 priv->staging_rxon.flags &=
6874 ~RXON_FLG_SHORT_SLOT_MSK;
6875
6876 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
6877 priv->staging_rxon.flags &=
6878 ~RXON_FLG_SHORT_SLOT_MSK;
6879 }
6880 /* restore RXON assoc */
6881 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
bb8c093b
CH		 6882 iwl3945_commit_rxon(priv);
6883 iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
556f8db7 6884 }
bb8c093b 6885 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 6886
6887 /* FIXME - we need to add code here to detect a totally new
6888 * configuration, reset the AP, unassoc, rxon timing, assoc,
6889 * clear sta table, add BCAST sta... */
6890}
6891
32bfd35d
JB		 6892static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
6893 struct ieee80211_vif *vif,
b481de9c
ZY		 6894 struct ieee80211_if_conf *conf)
6895{
bb8c093b 6896 struct iwl3945_priv *priv = hw->priv;
0795af57 6897 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 6898 unsigned long flags;
6899 int rc;
6900
6901 if (conf == NULL)
6902 return -EIO;
6903
b716bb91
EG		 6904 if (priv->vif != vif) {
6905 IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
b716bb91
EG		 6906 return 0;
6907 }
6908
4150c572
JB		 6909 /* XXX: this MUST use conf->mac_addr */
6910
b481de9c
ZY		 6911 if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
6912 (!conf->beacon || !conf->ssid_len)) {
6913 IWL_DEBUG_MAC80211
6914 ("Leaving in AP mode because HostAPD is not ready.\n");
6915 return 0;
6916 }
6917
5a66926a
ZY		 6918 if (!iwl3945_is_alive(priv))
6919 return -EAGAIN;
6920
b481de9c
ZY		 6921 mutex_lock(&priv->mutex);
6922
b481de9c 6923 if (conf->bssid)
0795af57
JP		 6924 IWL_DEBUG_MAC80211("bssid: %s\n",
6925 print_mac(mac, conf->bssid));
b481de9c 6926
4150c572
JB		 6927/*
6928 * very dubious code was here; the probe filtering flag is never set:
6929 *
b481de9c
ZY		 6930 if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
6931 !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
4150c572 6932 */
b481de9c
ZY		 6933
6934 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
6935 if (!conf->bssid) {
6936 conf->bssid = priv->mac_addr;
6937 memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
0795af57
JP		 6938 IWL_DEBUG_MAC80211("bssid was set to: %s\n",
6939 print_mac(mac, conf->bssid));
b481de9c
ZY		 6940 }
6941 if (priv->ibss_beacon)
6942 dev_kfree_skb(priv->ibss_beacon);
6943
6944 priv->ibss_beacon = conf->beacon;
6945 }
6946
fde3571f
MA		 6947 if (iwl3945_is_rfkill(priv))
6948 goto done;
6949
b481de9c
ZY		 6950 if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
6951 !is_multicast_ether_addr(conf->bssid)) {
6952 /* If there is currently a HW scan going on in the background
6953 * then we need to cancel it else the RXON below will fail. */
bb8c093b 6954 if (iwl3945_scan_cancel_timeout(priv, 100)) {
b481de9c
ZY		 6955 IWL_WARNING("Aborted scan still in progress "
6956 "after 100ms\n");
6957 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
6958 mutex_unlock(&priv->mutex);
6959 return -EAGAIN;
6960 }
6961 memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
6962
6963 /* TODO: Audit driver for usage of these members and see
6964 * if mac80211 deprecates them (priv->bssid looks like it
6965 * shouldn't be there, but I haven't scanned the IBSS code
6966 * to verify) - jpk */
6967 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
6968
6969 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
bb8c093b 6970 iwl3945_config_ap(priv);
b481de9c 6971 else {
bb8c093b 6972 rc = iwl3945_commit_rxon(priv);
b481de9c 6973 if ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && rc)
bb8c093b 6974 iwl3945_add_station(priv,
556f8db7 6975 priv->active_rxon.bssid_addr, 1, 0);
b481de9c
ZY		 6976 }
6977
6978 } else {
bb8c093b 6979 iwl3945_scan_cancel_timeout(priv, 100);
b481de9c 6980 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6981 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6982 }
6983
fde3571f 6984 done:
b481de9c
ZY		 6985 spin_lock_irqsave(&priv->lock, flags);
6986 if (!conf->ssid_len)
6987 memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
6988 else
6989 memcpy(priv->essid, conf->ssid, conf->ssid_len);
6990
6991 priv->essid_len = conf->ssid_len;
6992 spin_unlock_irqrestore(&priv->lock, flags);
6993
6994 IWL_DEBUG_MAC80211("leave\n");
6995 mutex_unlock(&priv->mutex);
6996
6997 return 0;
6998}
6999
bb8c093b 7000static void iwl3945_configure_filter(struct ieee80211_hw *hw,
4150c572
JB		 7001 unsigned int changed_flags,
7002 unsigned int *total_flags,
7003 int mc_count, struct dev_addr_list *mc_list)
7004{
5ec03976 7005 struct iwl3945_priv *priv = hw->priv;
25b3f57c
RF		 7006
7007 if (changed_flags & (*total_flags) & FIF_OTHER_BSS) {
7008 IWL_DEBUG_MAC80211("Enter: type %d (0x%x, 0x%x)\n",
7009 IEEE80211_IF_TYPE_MNTR,
7010 changed_flags, *total_flags);
7011 /* queue work 'cuz mac80211 is holding a lock which
7012 * prevents us from issuing (synchronous) f/w cmds */
7013 queue_work(priv->workqueue, &priv->set_monitor);
5ec03976 7014 }
25b3f57c
RF		 7015 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI |
7016 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
4150c572
JB		 7017}
7018
bb8c093b 7019static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
b481de9c
ZY		 7020 struct ieee80211_if_init_conf *conf)
7021{
bb8c093b 7022 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7023
7024 IWL_DEBUG_MAC80211("enter\n");
7025
7026 mutex_lock(&priv->mutex);
6ef89d0a 7027
fde3571f
MA		 7028 if (iwl3945_is_ready_rf(priv)) {
7029 iwl3945_scan_cancel_timeout(priv, 100);
7030 cancel_delayed_work(&priv->post_associate);
7031 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
7032 iwl3945_commit_rxon(priv);
7033 }
32bfd35d
JB		 7034 if (priv->vif == conf->vif) {
7035 priv->vif = NULL;
b481de9c
ZY		 7036 memset(priv->bssid, 0, ETH_ALEN);
7037 memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
7038 priv->essid_len = 0;
7039 }
7040 mutex_unlock(&priv->mutex);
7041
7042 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 7043}
7044
bb8c093b 7045static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
b481de9c
ZY		 7046{
7047 int rc = 0;
7048 unsigned long flags;
bb8c093b 7049 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7050
7051 IWL_DEBUG_MAC80211("enter\n");
7052
15e869d8 7053 mutex_lock(&priv->mutex);
b481de9c
ZY		 7054 spin_lock_irqsave(&priv->lock, flags);
7055
bb8c093b 7056 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7057 rc = -EIO;
7058 IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
7059 goto out_unlock;
7060 }
7061
7062 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { /* APs don't scan */
7063 rc = -EIO;
7064 IWL_ERROR("ERROR: APs don't scan\n");
7065 goto out_unlock;
7066 }
7067
7878a5a4
MA		 7068 /* we don't schedule scan within next_scan_jiffies period */
7069 if (priv->next_scan_jiffies &&
7070 time_after(priv->next_scan_jiffies, jiffies)) {
7071 rc = -EAGAIN;
7072 goto out_unlock;
7073 }
15dbf1b7
BM		 7074 /* if we just finished scan ask for delay for a broadcast scan */
7075 if ((len == 0) && priv->last_scan_jiffies &&
7076 time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN,
7077 jiffies)) {
b481de9c
ZY		 7078 rc = -EAGAIN;
7079 goto out_unlock;
7080 }
7081 if (len) {
7878a5a4 7082 IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
bb8c093b 7083 iwl3945_escape_essid(ssid, len), (int)len);
b481de9c
ZY		 7084
7085 priv->one_direct_scan = 1;
7086 priv->direct_ssid_len = (u8)
7087 min((u8) len, (u8) IW_ESSID_MAX_SIZE);
7088 memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
6ef89d0a
MA		 7089 } else
7090 priv->one_direct_scan = 0;
b481de9c 7091
bb8c093b 7092 rc = iwl3945_scan_initiate(priv);
b481de9c
ZY		 7093
7094 IWL_DEBUG_MAC80211("leave\n");
7095
7096out_unlock:
7097 spin_unlock_irqrestore(&priv->lock, flags);
15e869d8 7098 mutex_unlock(&priv->mutex);
b481de9c
ZY		 7099
7100 return rc;
7101}
7102
bb8c093b 7103static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
b481de9c
ZY		 7104 const u8 *local_addr, const u8 *addr,
7105 struct ieee80211_key_conf *key)
7106{
bb8c093b 7107 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7108 int rc = 0;
7109 u8 sta_id;
7110
7111 IWL_DEBUG_MAC80211("enter\n");
7112
bb8c093b 7113 if (!iwl3945_param_hwcrypto) {
b481de9c
ZY		 7114 IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
7115 return -EOPNOTSUPP;
7116 }
7117
7118 if (is_zero_ether_addr(addr))
7119 /* only support pairwise keys */
7120 return -EOPNOTSUPP;
7121
bb8c093b 7122 sta_id = iwl3945_hw_find_station(priv, addr);
b481de9c 7123 if (sta_id == IWL_INVALID_STATION) {
0795af57
JP		 7124 DECLARE_MAC_BUF(mac);
7125
7126 IWL_DEBUG_MAC80211("leave - %s not in station map.\n",
7127 print_mac(mac, addr));
b481de9c
ZY		 7128 return -EINVAL;
7129 }
7130
7131 mutex_lock(&priv->mutex);
7132
bb8c093b 7133 iwl3945_scan_cancel_timeout(priv, 100);
15e869d8 7134
b481de9c
ZY		 7135 switch (cmd) {
7136 case SET_KEY:
bb8c093b 7137 rc = iwl3945_update_sta_key_info(priv, key, sta_id);
b481de9c 7138 if (!rc) {
bb8c093b
CH		 7139 iwl3945_set_rxon_hwcrypto(priv, 1);
7140 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7141 key->hw_key_idx = sta_id;
7142 IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
7143 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
7144 }
7145 break;
7146 case DISABLE_KEY:
bb8c093b 7147 rc = iwl3945_clear_sta_key_info(priv, sta_id);
b481de9c 7148 if (!rc) {
bb8c093b
CH		 7149 iwl3945_set_rxon_hwcrypto(priv, 0);
7150 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7151 IWL_DEBUG_MAC80211("disable hwcrypto key\n");
7152 }
7153 break;
7154 default:
7155 rc = -EINVAL;
7156 }
7157
7158 IWL_DEBUG_MAC80211("leave\n");
7159 mutex_unlock(&priv->mutex);
7160
7161 return rc;
7162}
7163
e100bb64 7164static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
b481de9c
ZY		 7165 const struct ieee80211_tx_queue_params *params)
7166{
bb8c093b 7167 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7168 unsigned long flags;
7169 int q;
b481de9c
ZY		 7170
7171 IWL_DEBUG_MAC80211("enter\n");
7172
bb8c093b 7173 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7174 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7175 return -EIO;
7176 }
7177
7178 if (queue >= AC_NUM) {
7179 IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
7180 return 0;
7181 }
7182
b481de9c
ZY		 7183 if (!priv->qos_data.qos_enable) {
7184 priv->qos_data.qos_active = 0;
7185 IWL_DEBUG_MAC80211("leave - qos not enabled\n");
7186 return 0;
7187 }
7188 q = AC_NUM - 1 - queue;
7189
7190 spin_lock_irqsave(&priv->lock, flags);
7191
7192 priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
7193 priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
7194 priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
7195 priv->qos_data.def_qos_parm.ac[q].edca_txop =
3330d7be 7196 cpu_to_le16((params->txop * 32));
b481de9c
ZY		 7197
7198 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
7199 priv->qos_data.qos_active = 1;
7200
7201 spin_unlock_irqrestore(&priv->lock, flags);
7202
7203 mutex_lock(&priv->mutex);
7204 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
bb8c093b
CH		 7205 iwl3945_activate_qos(priv, 1);
7206 else if (priv->assoc_id && iwl3945_is_associated(priv))
7207 iwl3945_activate_qos(priv, 0);
b481de9c
ZY		 7208
7209 mutex_unlock(&priv->mutex);
7210
b481de9c
ZY		 7211 IWL_DEBUG_MAC80211("leave\n");
7212 return 0;
7213}
7214
bb8c093b 7215static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
b481de9c
ZY		 7216 struct ieee80211_tx_queue_stats *stats)
7217{
bb8c093b 7218 struct iwl3945_priv *priv = hw->priv;
b481de9c 7219 int i, avail;
bb8c093b
CH		 7220 struct iwl3945_tx_queue *txq;
7221 struct iwl3945_queue *q;
b481de9c
ZY		 7222 unsigned long flags;
7223
7224 IWL_DEBUG_MAC80211("enter\n");
7225
bb8c093b 7226 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7227 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7228 return -EIO;
7229 }
7230
7231 spin_lock_irqsave(&priv->lock, flags);
7232
7233 for (i = 0; i < AC_NUM; i++) {
7234 txq = &priv->txq[i];
7235 q = &txq->q;
bb8c093b 7236 avail = iwl3945_queue_space(q);
b481de9c 7237
57ffc589
JB		 7238 stats[i].len = q->n_window - avail;
7239 stats[i].limit = q->n_window - q->high_mark;
7240 stats[i].count = q->n_window;
b481de9c
ZY		 7241
7242 }
7243 spin_unlock_irqrestore(&priv->lock, flags);
7244
7245 IWL_DEBUG_MAC80211("leave\n");
7246
7247 return 0;
7248}
7249
bb8c093b 7250static int iwl3945_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY		 7251 struct ieee80211_low_level_stats *stats)
7252{
7253 IWL_DEBUG_MAC80211("enter\n");
7254 IWL_DEBUG_MAC80211("leave\n");
7255
7256 return 0;
7257}
7258
bb8c093b 7259static u64 iwl3945_mac_get_tsf(struct ieee80211_hw *hw)
b481de9c
ZY		 7260{
7261 IWL_DEBUG_MAC80211("enter\n");
7262 IWL_DEBUG_MAC80211("leave\n");
7263
7264 return 0;
7265}
7266
bb8c093b 7267static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
b481de9c 7268{
bb8c093b 7269 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7270 unsigned long flags;
7271
7272 mutex_lock(&priv->mutex);
7273 IWL_DEBUG_MAC80211("enter\n");
7274
bb8c093b 7275 iwl3945_reset_qos(priv);
292ae174 7276
b481de9c
ZY		 7277 cancel_delayed_work(&priv->post_associate);
7278
7279 spin_lock_irqsave(&priv->lock, flags);
7280 priv->assoc_id = 0;
7281 priv->assoc_capability = 0;
7282 priv->call_post_assoc_from_beacon = 0;
7283
7284 /* new association get rid of ibss beacon skb */
7285 if (priv->ibss_beacon)
7286 dev_kfree_skb(priv->ibss_beacon);
7287
7288 priv->ibss_beacon = NULL;
7289
7290 priv->beacon_int = priv->hw->conf.beacon_int;
7291 priv->timestamp1 = 0;
7292 priv->timestamp0 = 0;
7293 if ((priv->iw_mode == IEEE80211_IF_TYPE_STA))
7294 priv->beacon_int = 0;
7295
7296 spin_unlock_irqrestore(&priv->lock, flags);
7297
fde3571f
MA		 7298 if (!iwl3945_is_ready_rf(priv)) {
7299 IWL_DEBUG_MAC80211("leave - not ready\n");
7300 mutex_unlock(&priv->mutex);
7301 return;
7302 }
7303
15e869d8
MA		 7304 /* we are restarting association process
7305 * clear RXON_FILTER_ASSOC_MSK bit
7306 */
7307 if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
bb8c093b 7308 iwl3945_scan_cancel_timeout(priv, 100);
15e869d8 7309 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 7310 iwl3945_commit_rxon(priv);
15e869d8
MA		 7311 }
7312
b481de9c
ZY		 7313 /* Per mac80211.h: This is only used in IBSS mode... */
7314 if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
15e869d8 7315
b481de9c
ZY		 7316 IWL_DEBUG_MAC80211("leave - not in IBSS\n");
7317 mutex_unlock(&priv->mutex);
7318 return;
b481de9c
ZY		 7319 }
7320
bb8c093b 7321 iwl3945_set_rate(priv);
b481de9c
ZY		 7322
7323 mutex_unlock(&priv->mutex);
7324
7325 IWL_DEBUG_MAC80211("leave\n");
7326
7327}
7328
e039fa4a 7329static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 7330{
bb8c093b 7331 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7332 unsigned long flags;
7333
7334 mutex_lock(&priv->mutex);
7335 IWL_DEBUG_MAC80211("enter\n");
7336
bb8c093b 7337 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7338 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7339 mutex_unlock(&priv->mutex);
7340 return -EIO;
7341 }
7342
7343 if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
7344 IWL_DEBUG_MAC80211("leave - not IBSS\n");
7345 mutex_unlock(&priv->mutex);
7346 return -EIO;
7347 }
7348
7349 spin_lock_irqsave(&priv->lock, flags);
7350
7351 if (priv->ibss_beacon)
7352 dev_kfree_skb(priv->ibss_beacon);
7353
7354 priv->ibss_beacon = skb;
7355
7356 priv->assoc_id = 0;
7357
7358 IWL_DEBUG_MAC80211("leave\n");
7359 spin_unlock_irqrestore(&priv->lock, flags);
7360
bb8c093b 7361 iwl3945_reset_qos(priv);
b481de9c
ZY		 7362
7363 queue_work(priv->workqueue, &priv->post_associate.work);
7364
7365 mutex_unlock(&priv->mutex);
7366
7367 return 0;
7368}
7369
7370/*****************************************************************************
7371 *
7372 * sysfs attributes
7373 *
7374 *****************************************************************************/
7375
c8b0e6e1 7376#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 7377
7378/*
7379 * The following adds a new attribute to the sysfs representation
7380 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
7381 * used for controlling the debug level.
7382 *
7383 * See the level definitions in iwl for details.
7384 */
7385
7386static ssize_t show_debug_level(struct device_driver *d, char *buf)
7387{
bb8c093b 7388 return sprintf(buf, "0x%08X\n", iwl3945_debug_level);
b481de9c
ZY		 7389}
7390static ssize_t store_debug_level(struct device_driver *d,
7391 const char *buf, size_t count)
7392{
7393 char *p = (char *)buf;
7394 u32 val;
7395
7396 val = simple_strtoul(p, &p, 0);
7397 if (p == buf)
7398 printk(KERN_INFO DRV_NAME
7399 ": %s is not in hex or decimal form.\n", buf);
7400 else
bb8c093b 7401 iwl3945_debug_level = val;
b481de9c
ZY		 7402
7403 return strnlen(buf, count);
7404}
7405
7406static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
7407 show_debug_level, store_debug_level);
7408
c8b0e6e1 7409#endif /* CONFIG_IWL3945_DEBUG */
b481de9c 7410
b481de9c
ZY		 7411static ssize_t show_temperature(struct device *d,
7412 struct device_attribute *attr, char *buf)
7413{
bb8c093b 7414 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c 7415
bb8c093b 7416 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7417 return -EAGAIN;
7418
bb8c093b 7419 return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
b481de9c
ZY		 7420}
7421
7422static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
7423
7424static ssize_t show_rs_window(struct device *d,
7425 struct device_attribute *attr,
7426 char *buf)
7427{
bb8c093b
CH		 7428 struct iwl3945_priv *priv = d->driver_data;
7429 return iwl3945_fill_rs_info(priv->hw, buf, IWL_AP_ID);
b481de9c
ZY		 7430}
7431static DEVICE_ATTR(rs_window, S_IRUGO, show_rs_window, NULL);
7432
7433static ssize_t show_tx_power(struct device *d,
7434 struct device_attribute *attr, char *buf)
7435{
bb8c093b 7436 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7437 return sprintf(buf, "%d\n", priv->user_txpower_limit);
7438}
7439
7440static ssize_t store_tx_power(struct device *d,
7441 struct device_attribute *attr,
7442 const char *buf, size_t count)
7443{
bb8c093b 7444 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7445 char *p = (char *)buf;
7446 u32 val;
7447
7448 val = simple_strtoul(p, &p, 10);
7449 if (p == buf)
7450 printk(KERN_INFO DRV_NAME
7451 ": %s is not in decimal form.\n", buf);
7452 else
bb8c093b 7453 iwl3945_hw_reg_set_txpower(priv, val);
b481de9c
ZY		 7454
7455 return count;
7456}
7457
7458static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
7459
7460static ssize_t show_flags(struct device *d,
7461 struct device_attribute *attr, char *buf)
7462{
bb8c093b 7463 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7464
7465 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
7466}
7467
7468static ssize_t store_flags(struct device *d,
7469 struct device_attribute *attr,
7470 const char *buf, size_t count)
7471{
bb8c093b 7472 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7473 u32 flags = simple_strtoul(buf, NULL, 0);
7474
7475 mutex_lock(&priv->mutex);
7476 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
7477 /* Cancel any currently running scans... */
bb8c093b 7478 if (iwl3945_scan_cancel_timeout(priv, 100))
b481de9c
ZY		 7479 IWL_WARNING("Could not cancel scan.\n");
7480 else {
7481 IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
7482 flags);
7483 priv->staging_rxon.flags = cpu_to_le32(flags);
bb8c093b 7484 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7485 }
7486 }
7487 mutex_unlock(&priv->mutex);
7488
7489 return count;
7490}
7491
7492static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
7493
7494static ssize_t show_filter_flags(struct device *d,
7495 struct device_attribute *attr, char *buf)
7496{
bb8c093b 7497 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7498
7499 return sprintf(buf, "0x%04X\n",
7500 le32_to_cpu(priv->active_rxon.filter_flags));
7501}
7502
7503static ssize_t store_filter_flags(struct device *d,
7504 struct device_attribute *attr,
7505 const char *buf, size_t count)
7506{
bb8c093b 7507 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7508 u32 filter_flags = simple_strtoul(buf, NULL, 0);
7509
7510 mutex_lock(&priv->mutex);
7511 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
7512 /* Cancel any currently running scans... */
bb8c093b 7513 if (iwl3945_scan_cancel_timeout(priv, 100))
b481de9c
ZY		 7514 IWL_WARNING("Could not cancel scan.\n");
7515 else {
7516 IWL_DEBUG_INFO("Committing rxon.filter_flags = "
7517 "0x%04X\n", filter_flags);
7518 priv->staging_rxon.filter_flags =
7519 cpu_to_le32(filter_flags);
bb8c093b 7520 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7521 }
7522 }
7523 mutex_unlock(&priv->mutex);
7524
7525 return count;
7526}
7527
7528static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
7529 store_filter_flags);
7530
c8b0e6e1 7531#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 7532
7533static ssize_t show_measurement(struct device *d,
7534 struct device_attribute *attr, char *buf)
7535{
bb8c093b
CH		 7536 struct iwl3945_priv *priv = dev_get_drvdata(d);
7537 struct iwl3945_spectrum_notification measure_report;
b481de9c
ZY		 7538 u32 size = sizeof(measure_report), len = 0, ofs = 0;
7539 u8 *data = (u8 *) & measure_report;
7540 unsigned long flags;
7541
7542 spin_lock_irqsave(&priv->lock, flags);
7543 if (!(priv->measurement_status & MEASUREMENT_READY)) {
7544 spin_unlock_irqrestore(&priv->lock, flags);
7545 return 0;
7546 }
7547 memcpy(&measure_report, &priv->measure_report, size);
7548 priv->measurement_status = 0;
7549 spin_unlock_irqrestore(&priv->lock, flags);
7550
7551 while (size && (PAGE_SIZE - len)) {
7552 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
7553 PAGE_SIZE - len, 1);
7554 len = strlen(buf);
7555 if (PAGE_SIZE - len)
7556 buf[len++] = '\n';
7557
7558 ofs += 16;
7559 size -= min(size, 16U);
7560 }
7561
7562 return len;
7563}
7564
7565static ssize_t store_measurement(struct device *d,
7566 struct device_attribute *attr,
7567 const char *buf, size_t count)
7568{
bb8c093b 7569 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7570 struct ieee80211_measurement_params params = {
7571 .channel = le16_to_cpu(priv->active_rxon.channel),
7572 .start_time = cpu_to_le64(priv->last_tsf),
7573 .duration = cpu_to_le16(1),
7574 };
7575 u8 type = IWL_MEASURE_BASIC;
7576 u8 buffer[32];
7577 u8 channel;
7578
7579 if (count) {
7580 char *p = buffer;
7581 strncpy(buffer, buf, min(sizeof(buffer), count));
7582 channel = simple_strtoul(p, NULL, 0);
7583 if (channel)
7584 params.channel = channel;
7585
7586 p = buffer;
7587 while (*p && *p != ' ')
7588 p++;
7589 if (*p)
7590 type = simple_strtoul(p + 1, NULL, 0);
7591 }
7592
7593 IWL_DEBUG_INFO("Invoking measurement of type %d on "
7594 "channel %d (for '%s')\n", type, params.channel, buf);
bb8c093b 7595 iwl3945_get_measurement(priv, &params, type);
b481de9c
ZY		 7596
7597 return count;
7598}
7599
7600static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
7601 show_measurement, store_measurement);
c8b0e6e1 7602#endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
b481de9c 7603
b481de9c
ZY		 7604static ssize_t store_retry_rate(struct device *d,
7605 struct device_attribute *attr,
7606 const char *buf, size_t count)
7607{
bb8c093b 7608 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7609
7610 priv->retry_rate = simple_strtoul(buf, NULL, 0);
7611 if (priv->retry_rate <= 0)
7612 priv->retry_rate = 1;
7613
7614 return count;
7615}
7616
7617static ssize_t show_retry_rate(struct device *d,
7618 struct device_attribute *attr, char *buf)
7619{
bb8c093b 7620 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7621 return sprintf(buf, "%d", priv->retry_rate);
7622}
7623
7624static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
7625 store_retry_rate);
7626
7627static ssize_t store_power_level(struct device *d,
7628 struct device_attribute *attr,
7629 const char *buf, size_t count)
7630{
bb8c093b 7631 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7632 int rc;
7633 int mode;
7634
7635 mode = simple_strtoul(buf, NULL, 0);
7636 mutex_lock(&priv->mutex);
7637
bb8c093b 7638 if (!iwl3945_is_ready(priv)) {
b481de9c
ZY		 7639 rc = -EAGAIN;
7640 goto out;
7641 }
7642
7643 if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
7644 mode = IWL_POWER_AC;
7645 else
7646 mode |= IWL_POWER_ENABLED;
7647
7648 if (mode != priv->power_mode) {
bb8c093b 7649 rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
b481de9c
ZY		 7650 if (rc) {
7651 IWL_DEBUG_MAC80211("failed setting power mode.\n");
7652 goto out;
7653 }
7654 priv->power_mode = mode;
7655 }
7656
7657 rc = count;
7658
7659 out:
7660 mutex_unlock(&priv->mutex);
7661 return rc;
7662}
7663
7664#define MAX_WX_STRING 80
7665
7666/* Values are in microsecond */
7667static const s32 timeout_duration[] = {
7668 350000,
7669 250000,
7670 75000,
7671 37000,
7672 25000,
7673};
7674static const s32 period_duration[] = {
7675 400000,
7676 700000,
7677 1000000,
7678 1000000,
7679 1000000
7680};
7681
7682static ssize_t show_power_level(struct device *d,
7683 struct device_attribute *attr, char *buf)
7684{
bb8c093b 7685 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7686 int level = IWL_POWER_LEVEL(priv->power_mode);
7687 char *p = buf;
7688
7689 p += sprintf(p, "%d ", level);
7690 switch (level) {
7691 case IWL_POWER_MODE_CAM:
7692 case IWL_POWER_AC:
7693 p += sprintf(p, "(AC)");
7694 break;
7695 case IWL_POWER_BATTERY:
7696 p += sprintf(p, "(BATTERY)");
7697 break;
7698 default:
7699 p += sprintf(p,
7700 "(Timeout %dms, Period %dms)",
7701 timeout_duration[level - 1] / 1000,
7702 period_duration[level - 1] / 1000);
7703 }
7704
7705 if (!(priv->power_mode & IWL_POWER_ENABLED))
7706 p += sprintf(p, " OFF\n");
7707 else
7708 p += sprintf(p, " \n");
7709
7710 return (p - buf + 1);
7711
7712}
7713
7714static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
7715 store_power_level);
7716
7717static ssize_t show_channels(struct device *d,
7718 struct device_attribute *attr, char *buf)
7719{
8318d78a
JB		 7720 /* all this shit doesn't belong into sysfs anyway */
7721 return 0;
b481de9c
ZY		 7722}
7723
7724static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
7725
7726static ssize_t show_statistics(struct device *d,
7727 struct device_attribute *attr, char *buf)
7728{
bb8c093b
CH		 7729 struct iwl3945_priv *priv = dev_get_drvdata(d);
7730 u32 size = sizeof(struct iwl3945_notif_statistics);
b481de9c
ZY		 7731 u32 len = 0, ofs = 0;
7732 u8 *data = (u8 *) & priv->statistics;
7733 int rc = 0;
7734
bb8c093b 7735 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7736 return -EAGAIN;
7737
7738 mutex_lock(&priv->mutex);
bb8c093b 7739 rc = iwl3945_send_statistics_request(priv);
b481de9c
ZY		 7740 mutex_unlock(&priv->mutex);
7741
7742 if (rc) {
7743 len = sprintf(buf,
7744 "Error sending statistics request: 0x%08X\n", rc);
7745 return len;
7746 }
7747
7748 while (size && (PAGE_SIZE - len)) {
7749 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
7750 PAGE_SIZE - len, 1);
7751 len = strlen(buf);
7752 if (PAGE_SIZE - len)
7753 buf[len++] = '\n';
7754
7755 ofs += 16;
7756 size -= min(size, 16U);
7757 }
7758
7759 return len;
7760}
7761
7762static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
7763
7764static ssize_t show_antenna(struct device *d,
7765 struct device_attribute *attr, char *buf)
7766{
bb8c093b 7767 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c 7768
bb8c093b 7769 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7770 return -EAGAIN;
7771
7772 return sprintf(buf, "%d\n", priv->antenna);
7773}
7774
7775static ssize_t store_antenna(struct device *d,
7776 struct device_attribute *attr,
7777 const char *buf, size_t count)
7778{
7779 int ant;
bb8c093b 7780 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7781
7782 if (count == 0)
7783 return 0;
7784
7785 if (sscanf(buf, "%1i", &ant) != 1) {
7786 IWL_DEBUG_INFO("not in hex or decimal form.\n");
7787 return count;
7788 }
7789
7790 if ((ant >= 0) && (ant <= 2)) {
7791 IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
bb8c093b 7792 priv->antenna = (enum iwl3945_antenna)ant;
b481de9c
ZY		 7793 } else
7794 IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
7795
7796
7797 return count;
7798}
7799
7800static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
7801
7802static ssize_t show_status(struct device *d,
7803 struct device_attribute *attr, char *buf)
7804{
bb8c093b
CH		 7805 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
7806 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7807 return -EAGAIN;
7808 return sprintf(buf, "0x%08x\n", (int)priv->status);
7809}
7810
7811static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
7812
7813static ssize_t dump_error_log(struct device *d,
7814 struct device_attribute *attr,
7815 const char *buf, size_t count)
7816{
7817 char *p = (char *)buf;
7818
7819 if (p[0] == '1')
bb8c093b 7820 iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data);
b481de9c
ZY		 7821
7822 return strnlen(buf, count);
7823}
7824
7825static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
7826
7827static ssize_t dump_event_log(struct device *d,
7828 struct device_attribute *attr,
7829 const char *buf, size_t count)
7830{
7831 char *p = (char *)buf;
7832
7833 if (p[0] == '1')
bb8c093b 7834 iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data);
b481de9c
ZY		 7835
7836 return strnlen(buf, count);
7837}
7838
7839static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
7840
7841/*****************************************************************************
7842 *
7843 * driver setup and teardown
7844 *
7845 *****************************************************************************/
7846
bb8c093b 7847static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv)
b481de9c
ZY		 7848{
7849 priv->workqueue = create_workqueue(DRV_NAME);
7850
7851 init_waitqueue_head(&priv->wait_command_queue);
7852
bb8c093b
CH		 7853 INIT_WORK(&priv->up, iwl3945_bg_up);
7854 INIT_WORK(&priv->restart, iwl3945_bg_restart);
7855 INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
7856 INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
7857 INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
7858 INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
7859 INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
7860 INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
5ec03976 7861 INIT_WORK(&priv->set_monitor, iwl3945_bg_set_monitor);
bb8c093b
CH		 7862 INIT_DELAYED_WORK(&priv->post_associate, iwl3945_bg_post_associate);
7863 INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
7864 INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
7865 INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
7866
7867 iwl3945_hw_setup_deferred_work(priv);
b481de9c
ZY		 7868
7869 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
bb8c093b 7870 iwl3945_irq_tasklet, (unsigned long)priv);
b481de9c
ZY		 7871}
7872
bb8c093b 7873static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv)
b481de9c 7874{
bb8c093b 7875 iwl3945_hw_cancel_deferred_work(priv);
b481de9c 7876
e47eb6ad 7877 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY		 7878 cancel_delayed_work(&priv->scan_check);
7879 cancel_delayed_work(&priv->alive_start);
7880 cancel_delayed_work(&priv->post_associate);
7881 cancel_work_sync(&priv->beacon_update);
7882}
7883
bb8c093b 7884static struct attribute *iwl3945_sysfs_entries[] = {
b481de9c
ZY		 7885 &dev_attr_antenna.attr,
7886 &dev_attr_channels.attr,
7887 &dev_attr_dump_errors.attr,
7888 &dev_attr_dump_events.attr,
7889 &dev_attr_flags.attr,
7890 &dev_attr_filter_flags.attr,
c8b0e6e1 7891#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 7892 &dev_attr_measurement.attr,
7893#endif
7894 &dev_attr_power_level.attr,
b481de9c 7895 &dev_attr_retry_rate.attr,
b481de9c
ZY		 7896 &dev_attr_rs_window.attr,
7897 &dev_attr_statistics.attr,
7898 &dev_attr_status.attr,
7899 &dev_attr_temperature.attr,
b481de9c
ZY		 7900 &dev_attr_tx_power.attr,
7901
7902 NULL
7903};
7904
bb8c093b 7905static struct attribute_group iwl3945_attribute_group = {
b481de9c 7906 .name = NULL, /* put in device directory */
bb8c093b 7907 .attrs = iwl3945_sysfs_entries,
b481de9c
ZY		 7908};
7909
bb8c093b
CH		 7910static struct ieee80211_ops iwl3945_hw_ops = {
7911 .tx = iwl3945_mac_tx,
7912 .start = iwl3945_mac_start,
7913 .stop = iwl3945_mac_stop,
7914 .add_interface = iwl3945_mac_add_interface,
7915 .remove_interface = iwl3945_mac_remove_interface,
7916 .config = iwl3945_mac_config,
7917 .config_interface = iwl3945_mac_config_interface,
7918 .configure_filter = iwl3945_configure_filter,
7919 .set_key = iwl3945_mac_set_key,
7920 .get_stats = iwl3945_mac_get_stats,
7921 .get_tx_stats = iwl3945_mac_get_tx_stats,
7922 .conf_tx = iwl3945_mac_conf_tx,
7923 .get_tsf = iwl3945_mac_get_tsf,
7924 .reset_tsf = iwl3945_mac_reset_tsf,
7925 .beacon_update = iwl3945_mac_beacon_update,
7926 .hw_scan = iwl3945_mac_hw_scan
b481de9c
ZY		 7927};
7928
bb8c093b 7929static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY		 7930{
7931 int err = 0;
bb8c093b 7932 struct iwl3945_priv *priv;
b481de9c 7933 struct ieee80211_hw *hw;
82b9a121 7934 struct iwl_3945_cfg *cfg = (struct iwl_3945_cfg *)(ent->driver_data);
b481de9c 7935 int i;
0359facc 7936 unsigned long flags;
5a66926a 7937 DECLARE_MAC_BUF(mac);
b481de9c 7938
6440adb5
CB		 7939 /* Disabling hardware scan means that mac80211 will perform scans
7940 * "the hard way", rather than using device's scan. */
bb8c093b 7941 if (iwl3945_param_disable_hw_scan) {
b481de9c 7942 IWL_DEBUG_INFO("Disabling hw_scan\n");
bb8c093b 7943 iwl3945_hw_ops.hw_scan = NULL;
b481de9c
ZY		 7944 }
7945
dfe7d458 7946 if ((iwl3945_param_queues_num > IWL39_MAX_NUM_QUEUES) ||
bb8c093b 7947 (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) {
b481de9c 7948 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
dfe7d458 7949 IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES);
b481de9c
ZY		 7950 err = -EINVAL;
7951 goto out;
7952 }
7953
7954 /* mac80211 allocates memory for this device instance, including
7955 * space for this driver's private structure */
bb8c093b 7956 hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops);
b481de9c
ZY		 7957 if (hw == NULL) {
7958 IWL_ERROR("Can not allocate network device\n");
7959 err = -ENOMEM;
7960 goto out;
7961 }
7962 SET_IEEE80211_DEV(hw, &pdev->dev);
7963
f51359a8
JB		 7964 hw->rate_control_algorithm = "iwl-3945-rs";
7965
b481de9c
ZY		 7966 IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
7967 priv = hw->priv;
7968 priv->hw = hw;
7969
7970 priv->pci_dev = pdev;
82b9a121 7971 priv->cfg = cfg;
6440adb5
CB		 7972
7973 /* Select antenna (may be helpful if only one antenna is connected) */
bb8c093b 7974 priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna;
c8b0e6e1 7975#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 7976 iwl3945_debug_level = iwl3945_param_debug;
b481de9c
ZY		 7977 atomic_set(&priv->restrict_refcnt, 0);
7978#endif
7979 priv->retry_rate = 1;
7980
7981 priv->ibss_beacon = NULL;
7982
566bfe5a
BR		 7983 /* Tell mac80211 our characteristics */
7984 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
7985 IEEE80211_HW_SIGNAL_DBM |
7986 IEEE80211_HW_NOISE_DBM;
b481de9c 7987
6440adb5 7988 /* 4 EDCA QOS priorities */
b481de9c
ZY		 7989 hw->queues = 4;
7990
7991 spin_lock_init(&priv->lock);
7992 spin_lock_init(&priv->power_data.lock);
7993 spin_lock_init(&priv->sta_lock);
7994 spin_lock_init(&priv->hcmd_lock);
7995
7996 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
7997 INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
7998
7999 INIT_LIST_HEAD(&priv->free_frames);
8000
8001 mutex_init(&priv->mutex);
8002 if (pci_enable_device(pdev)) {
8003 err = -ENODEV;
8004 goto out_ieee80211_free_hw;
8005 }
8006
8007 pci_set_master(pdev);
8008
6440adb5 8009 /* Clear the driver's (not device's) station table */
bb8c093b 8010 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 8011
8012 priv->data_retry_limit = -1;
8013 priv->ieee_channels = NULL;
8014 priv->ieee_rates = NULL;
8318d78a 8015 priv->band = IEEE80211_BAND_2GHZ;
b481de9c
ZY		 8016
8017 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
8018 if (!err)
8019 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
8020 if (err) {
8021 printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
8022 goto out_pci_disable_device;
8023 }
8024
8025 pci_set_drvdata(pdev, priv);
8026 err = pci_request_regions(pdev, DRV_NAME);
8027 if (err)
8028 goto out_pci_disable_device;
6440adb5 8029
b481de9c
ZY		 8030 /* We disable the RETRY_TIMEOUT register (0x41) to keep
8031 * PCI Tx retries from interfering with C3 CPU state */
8032 pci_write_config_byte(pdev, 0x41, 0x00);
6440adb5 8033
b481de9c
ZY		 8034 priv->hw_base = pci_iomap(pdev, 0, 0);
8035 if (!priv->hw_base) {
8036 err = -ENODEV;
8037 goto out_pci_release_regions;
8038 }
8039
8040 IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
8041 (unsigned long long) pci_resource_len(pdev, 0));
8042 IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
8043
8044 /* Initialize module parameter values here */
8045
6440adb5 8046 /* Disable radio (SW RF KILL) via parameter when loading driver */
bb8c093b 8047 if (iwl3945_param_disable) {
b481de9c
ZY		 8048 set_bit(STATUS_RF_KILL_SW, &priv->status);
8049 IWL_DEBUG_INFO("Radio disabled.\n");
8050 }
8051
8052 priv->iw_mode = IEEE80211_IF_TYPE_STA;
8053
b481de9c 8054 printk(KERN_INFO DRV_NAME
82b9a121 8055 ": Detected Intel Wireless WiFi Link %s\n", priv->cfg->name);
b481de9c
ZY		 8056
8057 /* Device-specific setup */
bb8c093b 8058 if (iwl3945_hw_set_hw_setting(priv)) {
b481de9c 8059 IWL_ERROR("failed to set hw settings\n");
b481de9c
ZY		 8060 goto out_iounmap;
8061 }
8062
bb8c093b 8063 if (iwl3945_param_qos_enable)
b481de9c
ZY		 8064 priv->qos_data.qos_enable = 1;
8065
bb8c093b 8066 iwl3945_reset_qos(priv);
b481de9c
ZY		 8067
8068 priv->qos_data.qos_active = 0;
8069 priv->qos_data.qos_cap.val = 0;
b481de9c 8070
8318d78a 8071 iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
bb8c093b
CH		 8072 iwl3945_setup_deferred_work(priv);
8073 iwl3945_setup_rx_handlers(priv);
b481de9c
ZY		 8074
8075 priv->rates_mask = IWL_RATES_MASK;
8076 /* If power management is turned on, default to AC mode */
8077 priv->power_mode = IWL_POWER_AC;
8078 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
8079
0359facc 8080 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 8081 iwl3945_disable_interrupts(priv);
0359facc 8082 spin_unlock_irqrestore(&priv->lock, flags);
49df2b33 8083
bb8c093b 8084 err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c
ZY		 8085 if (err) {
8086 IWL_ERROR("failed to create sysfs device attributes\n");
b481de9c
ZY		 8087 goto out_release_irq;
8088 }
8089
5a66926a
ZY		 8090 /* nic init */
8091 iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
8092 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
8093
8094 iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
8095 err = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
8096 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
8097 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
8098 if (err < 0) {
8099 IWL_DEBUG_INFO("Failed to init the card\n");
8100 goto out_remove_sysfs;
8101 }
8102 /* Read the EEPROM */
8103 err = iwl3945_eeprom_init(priv);
b481de9c 8104 if (err) {
5a66926a
ZY		 8105 IWL_ERROR("Unable to init EEPROM\n");
8106 goto out_remove_sysfs;
b481de9c 8107 }
5a66926a
ZY		 8108 /* MAC Address location in EEPROM same for 3945/4965 */
8109 get_eeprom_mac(priv, priv->mac_addr);
8110 IWL_DEBUG_INFO("MAC address: %s\n", print_mac(mac, priv->mac_addr));
8111 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
b481de9c 8112
849e0dce
RC		 8113 err = iwl3945_init_channel_map(priv);
8114 if (err) {
8115 IWL_ERROR("initializing regulatory failed: %d\n", err);
8116 goto out_remove_sysfs;
8117 }
8118
8119 err = iwl3945_init_geos(priv);
8120 if (err) {
8121 IWL_ERROR("initializing geos failed: %d\n", err);
8122 goto out_free_channel_map;
8123 }
849e0dce 8124
5a66926a
ZY		 8125 err = ieee80211_register_hw(priv->hw);
8126 if (err) {
8127 IWL_ERROR("Failed to register network device (error %d)\n", err);
849e0dce 8128 goto out_free_geos;
5a66926a 8129 }
b481de9c 8130
5a66926a
ZY		 8131 priv->hw->conf.beacon_int = 100;
8132 priv->mac80211_registered = 1;
8133 pci_save_state(pdev);
8134 pci_disable_device(pdev);
b481de9c 8135
ebef2008
AK		 8136 err = iwl3945_rfkill_init(priv);
8137 if (err)
8138 IWL_ERROR("Unable to initialize RFKILL system. "
8139 "Ignoring error: %d\n", err);
8140
b481de9c
ZY		 8141 return 0;
8142
849e0dce
RC		 8143 out_free_geos:
8144 iwl3945_free_geos(priv);
8145 out_free_channel_map:
8146 iwl3945_free_channel_map(priv);
5a66926a 8147 out_remove_sysfs:
bb8c093b 8148 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c
ZY		 8149
8150 out_release_irq:
b481de9c
ZY		 8151 destroy_workqueue(priv->workqueue);
8152 priv->workqueue = NULL;
bb8c093b 8153 iwl3945_unset_hw_setting(priv);
b481de9c
ZY		 8154
8155 out_iounmap:
8156 pci_iounmap(pdev, priv->hw_base);
8157 out_pci_release_regions:
8158 pci_release_regions(pdev);
8159 out_pci_disable_device:
8160 pci_disable_device(pdev);
8161 pci_set_drvdata(pdev, NULL);
8162 out_ieee80211_free_hw:
8163 ieee80211_free_hw(priv->hw);
8164 out:
8165 return err;
8166}
8167
c83dbf68 8168static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
b481de9c 8169{
bb8c093b 8170 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c
ZY		 8171 struct list_head *p, *q;
8172 int i;
0359facc 8173 unsigned long flags;
b481de9c
ZY		 8174
8175 if (!priv)
8176 return;
8177
8178 IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
8179
b481de9c 8180 set_bit(STATUS_EXIT_PENDING, &priv->status);
b24d22b1 8181
bb8c093b 8182 iwl3945_down(priv);
b481de9c 8183
0359facc
MA		 8184 /* make sure we flush any pending irq or
8185 * tasklet for the driver
8186 */
8187 spin_lock_irqsave(&priv->lock, flags);
8188 iwl3945_disable_interrupts(priv);
8189 spin_unlock_irqrestore(&priv->lock, flags);
8190
8191 iwl_synchronize_irq(priv);
8192
b481de9c
ZY		 8193 /* Free MAC hash list for ADHOC */
8194 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) {
8195 list_for_each_safe(p, q, &priv->ibss_mac_hash[i]) {
8196 list_del(p);
bb8c093b 8197 kfree(list_entry(p, struct iwl3945_ibss_seq, list));
b481de9c
ZY		 8198 }
8199 }
8200
bb8c093b 8201 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 8202
ebef2008 8203 iwl3945_rfkill_unregister(priv);
bb8c093b 8204 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY		 8205
8206 if (priv->rxq.bd)
bb8c093b
CH		 8207 iwl3945_rx_queue_free(priv, &priv->rxq);
8208 iwl3945_hw_txq_ctx_free(priv);
b481de9c 8209
bb8c093b
CH		 8210 iwl3945_unset_hw_setting(priv);
8211 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 8212
8213 if (priv->mac80211_registered) {
8214 ieee80211_unregister_hw(priv->hw);
b481de9c
ZY		 8215 }
8216
6ef89d0a
MA		 8217 /*netif_stop_queue(dev); */
8218 flush_workqueue(priv->workqueue);
8219
bb8c093b 8220 /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
b481de9c
ZY		 8221 * priv->workqueue... so we can't take down the workqueue
8222 * until now... */
8223 destroy_workqueue(priv->workqueue);
8224 priv->workqueue = NULL;
8225
b481de9c
ZY		 8226 pci_iounmap(pdev, priv->hw_base);
8227 pci_release_regions(pdev);
8228 pci_disable_device(pdev);
8229 pci_set_drvdata(pdev, NULL);
8230
849e0dce
RC		 8231 iwl3945_free_channel_map(priv);
8232 iwl3945_free_geos(priv);
261415f7 8233 kfree(priv->scan);
b481de9c
ZY		 8234 if (priv->ibss_beacon)
8235 dev_kfree_skb(priv->ibss_beacon);
8236
8237 ieee80211_free_hw(priv->hw);
8238}
8239
8240#ifdef CONFIG_PM
8241
bb8c093b 8242static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
b481de9c 8243{
bb8c093b 8244 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c 8245
e655b9f0
ZY		 8246 if (priv->is_open) {
8247 set_bit(STATUS_IN_SUSPEND, &priv->status);
8248 iwl3945_mac_stop(priv->hw);
8249 priv->is_open = 1;
8250 }
b481de9c 8251
b481de9c
ZY		 8252 pci_set_power_state(pdev, PCI_D3hot);
8253
b481de9c
ZY		 8254 return 0;
8255}
8256
bb8c093b 8257static int iwl3945_pci_resume(struct pci_dev *pdev)
b481de9c 8258{
bb8c093b 8259 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c 8260
b481de9c 8261 pci_set_power_state(pdev, PCI_D0);
b481de9c 8262
e655b9f0
ZY		 8263 if (priv->is_open)
8264 iwl3945_mac_start(priv->hw);
b481de9c 8265
e655b9f0 8266 clear_bit(STATUS_IN_SUSPEND, &priv->status);
b481de9c
ZY		 8267 return 0;
8268}
8269
8270#endif /* CONFIG_PM */
8271
ebef2008
AK		 8272/*************** RFKILL FUNCTIONS **********/
8273#ifdef CONFIG_IWLWIFI_RFKILL
8274/* software rf-kill from user */
8275static int iwl3945_rfkill_soft_rf_kill(void *data, enum rfkill_state state)
8276{
8277 struct iwl3945_priv *priv = data;
8278 int err = 0;
8279
8280 if (!priv->rfkill_mngr.rfkill)
8281 return 0;
8282
8283 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
8284 return 0;
8285
8286 IWL_DEBUG_RF_KILL("we recieved soft RFKILL set to state %d\n", state);
8287 mutex_lock(&priv->mutex);
8288
8289 switch (state) {
8290 case RFKILL_STATE_ON:
8291 iwl3945_radio_kill_sw(priv, 0);
8292 /* if HW rf-kill is set dont allow ON state */
8293 if (iwl3945_is_rfkill(priv))
8294 err = -EBUSY;
8295 break;
8296 case RFKILL_STATE_OFF:
8297 iwl3945_radio_kill_sw(priv, 1);
8298 if (!iwl3945_is_rfkill(priv))
8299 err = -EBUSY;
8300 break;
8301 }
8302 mutex_unlock(&priv->mutex);
8303
8304 return err;
8305}
8306
8307int iwl3945_rfkill_init(struct iwl3945_priv *priv)
8308{
8309 struct device *device = wiphy_dev(priv->hw->wiphy);
8310 int ret = 0;
8311
8312 BUG_ON(device == NULL);
8313
8314 IWL_DEBUG_RF_KILL("Initializing RFKILL.\n");
8315 priv->rfkill_mngr.rfkill = rfkill_allocate(device, RFKILL_TYPE_WLAN);
8316 if (!priv->rfkill_mngr.rfkill) {
8317 IWL_ERROR("Unable to allocate rfkill device.\n");
8318 ret = -ENOMEM;
8319 goto error;
8320 }
8321
8322 priv->rfkill_mngr.rfkill->name = priv->cfg->name;
8323 priv->rfkill_mngr.rfkill->data = priv;
8324 priv->rfkill_mngr.rfkill->state = RFKILL_STATE_ON;
8325 priv->rfkill_mngr.rfkill->toggle_radio = iwl3945_rfkill_soft_rf_kill;
8326 priv->rfkill_mngr.rfkill->user_claim_unsupported = 1;
8327
8328 priv->rfkill_mngr.rfkill->dev.class->suspend = NULL;
8329 priv->rfkill_mngr.rfkill->dev.class->resume = NULL;
8330
8331 priv->rfkill_mngr.input_dev = input_allocate_device();
8332 if (!priv->rfkill_mngr.input_dev) {
8333 IWL_ERROR("Unable to allocate rfkill input device.\n");
8334 ret = -ENOMEM;
8335 goto freed_rfkill;
8336 }
8337
8338 priv->rfkill_mngr.input_dev->name = priv->cfg->name;
8339 priv->rfkill_mngr.input_dev->phys = wiphy_name(priv->hw->wiphy);
8340 priv->rfkill_mngr.input_dev->id.bustype = BUS_HOST;
8341 priv->rfkill_mngr.input_dev->id.vendor = priv->pci_dev->vendor;
8342 priv->rfkill_mngr.input_dev->dev.parent = device;
8343 priv->rfkill_mngr.input_dev->evbit[0] = BIT(EV_KEY);
8344 set_bit(KEY_WLAN, priv->rfkill_mngr.input_dev->keybit);
8345
8346 ret = rfkill_register(priv->rfkill_mngr.rfkill);
8347 if (ret) {
8348 IWL_ERROR("Unable to register rfkill: %d\n", ret);
8349 goto free_input_dev;
8350 }
8351
8352 ret = input_register_device(priv->rfkill_mngr.input_dev);
8353 if (ret) {
8354 IWL_ERROR("Unable to register rfkill input device: %d\n", ret);
8355 goto unregister_rfkill;
8356 }
8357
8358 IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
8359 return ret;
8360
8361unregister_rfkill:
8362 rfkill_unregister(priv->rfkill_mngr.rfkill);
8363 priv->rfkill_mngr.rfkill = NULL;
8364
8365free_input_dev:
8366 input_free_device(priv->rfkill_mngr.input_dev);
8367 priv->rfkill_mngr.input_dev = NULL;
8368
8369freed_rfkill:
8370 if (priv->rfkill_mngr.rfkill != NULL)
8371 rfkill_free(priv->rfkill_mngr.rfkill);
8372 priv->rfkill_mngr.rfkill = NULL;
8373
8374error:
8375 IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
8376 return ret;
8377}
8378
8379void iwl3945_rfkill_unregister(struct iwl3945_priv *priv)
8380{
8381
8382 if (priv->rfkill_mngr.input_dev)
8383 input_unregister_device(priv->rfkill_mngr.input_dev);
8384
8385 if (priv->rfkill_mngr.rfkill)
8386 rfkill_unregister(priv->rfkill_mngr.rfkill);
8387
8388 priv->rfkill_mngr.input_dev = NULL;
8389 priv->rfkill_mngr.rfkill = NULL;
8390}
8391
8392/* set rf-kill to the right state. */
8393void iwl3945_rfkill_set_hw_state(struct iwl3945_priv *priv)
8394{
8395
8396 if (!priv->rfkill_mngr.rfkill)
8397 return;
8398
8399 if (!iwl3945_is_rfkill(priv))
8400 priv->rfkill_mngr.rfkill->state = RFKILL_STATE_ON;
8401 else
8402 priv->rfkill_mngr.rfkill->state = RFKILL_STATE_OFF;
8403}
8404#endif
8405
b481de9c
ZY		 8406/*****************************************************************************
8407 *
8408 * driver and module entry point
8409 *
8410 *****************************************************************************/
8411
bb8c093b 8412static struct pci_driver iwl3945_driver = {
b481de9c 8413 .name = DRV_NAME,
bb8c093b
CH		 8414 .id_table = iwl3945_hw_card_ids,
8415 .probe = iwl3945_pci_probe,
8416 .remove = __devexit_p(iwl3945_pci_remove),
b481de9c 8417#ifdef CONFIG_PM
bb8c093b
CH		 8418 .suspend = iwl3945_pci_suspend,
8419 .resume = iwl3945_pci_resume,
b481de9c
ZY		 8420#endif
8421};
8422
bb8c093b 8423static int __init iwl3945_init(void)
b481de9c
ZY		 8424{
8425
8426 int ret;
8427 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
8428 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2
RC		 8429
8430 ret = iwl3945_rate_control_register();
8431 if (ret) {
8432 IWL_ERROR("Unable to register rate control algorithm: %d\n", ret);
8433 return ret;
8434 }
8435
bb8c093b 8436 ret = pci_register_driver(&iwl3945_driver);
b481de9c
ZY		 8437 if (ret) {
8438 IWL_ERROR("Unable to initialize PCI module\n");
897e1cf2 8439 goto error_register;
b481de9c 8440 }
c8b0e6e1 8441#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8442 ret = driver_create_file(&iwl3945_driver.driver, &driver_attr_debug_level);
b481de9c
ZY		 8443 if (ret) {
8444 IWL_ERROR("Unable to create driver sysfs file\n");
897e1cf2 8445 goto error_debug;
b481de9c
ZY		 8446 }
8447#endif
8448
8449 return ret;
897e1cf2
RC		 8450
8451#ifdef CONFIG_IWL3945_DEBUG
8452error_debug:
8453 pci_unregister_driver(&iwl3945_driver);
8454#endif
8455error_register:
8456 iwl3945_rate_control_unregister();
8457 return ret;
b481de9c
ZY		 8458}
8459
bb8c093b 8460static void __exit iwl3945_exit(void)
b481de9c 8461{
c8b0e6e1 8462#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8463 driver_remove_file(&iwl3945_driver.driver, &driver_attr_debug_level);
b481de9c 8464#endif
bb8c093b 8465 pci_unregister_driver(&iwl3945_driver);
897e1cf2 8466 iwl3945_rate_control_unregister();
b481de9c
ZY		 8467}
8468
bb8c093b 8469module_param_named(antenna, iwl3945_param_antenna, int, 0444);
b481de9c 8470MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
bb8c093b 8471module_param_named(disable, iwl3945_param_disable, int, 0444);
b481de9c 8472MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
bb8c093b 8473module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444);
b481de9c
ZY		 8474MODULE_PARM_DESC(hwcrypto,
8475 "using hardware crypto engine (default 0 [software])\n");
bb8c093b 8476module_param_named(debug, iwl3945_param_debug, int, 0444);
b481de9c 8477MODULE_PARM_DESC(debug, "debug output mask");
bb8c093b 8478module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444);
b481de9c
ZY		 8479MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
8480
bb8c093b 8481module_param_named(queues_num, iwl3945_param_queues_num, int, 0444);
b481de9c
ZY		 8482MODULE_PARM_DESC(queues_num, "number of hw queues.");
8483
8484/* QoS */
bb8c093b 8485module_param_named(qos_enable, iwl3945_param_qos_enable, int, 0444);
b481de9c
ZY		 8486MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
8487
bb8c093b
CH		 8488module_exit(iwl3945_exit);
8489module_init(iwl3945_init);
Linux kernel - Deliverables
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