Merge branch 'hwmon-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jdelv...
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl3945-base.c
CommitLineData
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1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
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4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
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26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
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30#include <linux/kernel.h>
31#include <linux/module.h>
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32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
36#include <linux/skbuff.h>
37#include <linux/netdevice.h>
38#include <linux/wireless.h>
39#include <linux/firmware.h>
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40#include <linux/etherdevice.h>
41#include <linux/if_arp.h>
42
43#include <net/ieee80211_radiotap.h>
7e272fcf 44#include <net/lib80211.h>
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45#include <net/mac80211.h>
46
47#include <asm/div64.h>
48
a3139c59
SO
49#define DRV_NAME "iwl3945"
50
dbb6654c
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51#include "iwl-fh.h"
52#include "iwl-3945-fh.h"
600c0e11 53#include "iwl-commands.h"
17f841cd 54#include "iwl-sta.h"
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55#include "iwl-3945.h"
56#include "iwl-helpers.h"
5747d47f 57#include "iwl-core.h"
d20b3c65 58#include "iwl-dev.h"
b481de9c 59
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60/*
61 * module name, copyright, version, etc.
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62 */
63
64#define DRV_DESCRIPTION \
65"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
66
d08853a3 67#ifdef CONFIG_IWLWIFI_DEBUG
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68#define VD "d"
69#else
70#define VD
71#endif
72
c8b0e6e1 73#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
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74#define VS "s"
75#else
76#define VS
77#endif
78
eaa686c3 79#define IWL39_VERSION "1.2.26k" VD VS
01f8162a 80#define DRV_COPYRIGHT "Copyright(c) 2003-2009 Intel Corporation"
a7b75207 81#define DRV_AUTHOR "<ilw@linux.intel.com>"
eaa686c3 82#define DRV_VERSION IWL39_VERSION
b481de9c 83
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84
85MODULE_DESCRIPTION(DRV_DESCRIPTION);
86MODULE_VERSION(DRV_VERSION);
a7b75207 87MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
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88MODULE_LICENSE("GPL");
89
df878d8f
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90 /* module parameters */
91struct iwl_mod_params iwl3945_mod_params = {
92 .num_of_queues = IWL39_MAX_NUM_QUEUES,
9c74d9fb 93 .sw_crypto = 1,
af48d048 94 .restart_fw = 1,
df878d8f
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95 /* the rest are 0 by default */
96};
97
7e4bca5e
SO
98/**
99 * iwl3945_get_antenna_flags - Get antenna flags for RXON command
100 * @priv: eeprom and antenna fields are used to determine antenna flags
101 *
102 * priv->eeprom39 is used to determine if antenna AUX/MAIN are reversed
103 * iwl3945_mod_params.antenna specifies the antenna diversity mode:
104 *
105 * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
106 * IWL_ANTENNA_MAIN - Force MAIN antenna
107 * IWL_ANTENNA_AUX - Force AUX antenna
108 */
109__le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv)
110{
111 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
112
113 switch (iwl3945_mod_params.antenna) {
114 case IWL_ANTENNA_DIVERSITY:
115 return 0;
116
117 case IWL_ANTENNA_MAIN:
118 if (eeprom->antenna_switch_type)
119 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
120 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
121
122 case IWL_ANTENNA_AUX:
123 if (eeprom->antenna_switch_type)
124 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
125 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
126 }
127
128 /* bad antenna selector value */
129 IWL_ERR(priv, "Bad antenna selector value (0x%x)\n",
130 iwl3945_mod_params.antenna);
131
132 return 0; /* "diversity" is default if error */
133}
134
6e21f15c 135static int iwl3945_set_ccmp_dynamic_key_info(struct iwl_priv *priv,
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136 struct ieee80211_key_conf *keyconf,
137 u8 sta_id)
138{
139 unsigned long flags;
140 __le16 key_flags = 0;
6e21f15c
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141 int ret;
142
143 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
144 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
145
146 if (sta_id == priv->hw_params.bcast_sta_id)
147 key_flags |= STA_KEY_MULTICAST_MSK;
148
149 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
150 keyconf->hw_key_idx = keyconf->keyidx;
151 key_flags &= ~STA_KEY_FLG_INVALID;
b481de9c 152
b481de9c 153 spin_lock_irqsave(&priv->sta_lock, flags);
c587de0b
TW
154 priv->stations[sta_id].keyinfo.alg = keyconf->alg;
155 priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
156 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
b481de9c
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157 keyconf->keylen);
158
c587de0b 159 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
b481de9c 160 keyconf->keylen);
6e21f15c 161
c587de0b 162 if ((priv->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK)
6e21f15c 163 == STA_KEY_FLG_NO_ENC)
c587de0b 164 priv->stations[sta_id].sta.key.key_offset =
6e21f15c
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165 iwl_get_free_ucode_key_index(priv);
166 /* else, we are overriding an existing key => no need to allocated room
167 * in uCode. */
168
c587de0b 169 WARN(priv->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
6e21f15c
AK
170 "no space for a new key");
171
c587de0b
TW
172 priv->stations[sta_id].sta.key.key_flags = key_flags;
173 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
174 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
b481de9c 175
6e21f15c
AK
176 IWL_DEBUG_INFO(priv, "hwcrypto: modify ucode station key info\n");
177
c587de0b 178 ret = iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
6e21f15c 179
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180 spin_unlock_irqrestore(&priv->sta_lock, flags);
181
6e21f15c
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182 return ret;
183}
184
185static int iwl3945_set_tkip_dynamic_key_info(struct iwl_priv *priv,
186 struct ieee80211_key_conf *keyconf,
187 u8 sta_id)
188{
189 return -EOPNOTSUPP;
190}
191
192static int iwl3945_set_wep_dynamic_key_info(struct iwl_priv *priv,
193 struct ieee80211_key_conf *keyconf,
194 u8 sta_id)
195{
196 return -EOPNOTSUPP;
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197}
198
4a8a4322 199static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id)
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200{
201 unsigned long flags;
202
203 spin_lock_irqsave(&priv->sta_lock, flags);
c587de0b
TW
204 memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl_hw_key));
205 memset(&priv->stations[sta_id].sta.key, 0,
4c897253 206 sizeof(struct iwl4965_keyinfo));
c587de0b
TW
207 priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
208 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
209 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
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210 spin_unlock_irqrestore(&priv->sta_lock, flags);
211
e1623446 212 IWL_DEBUG_INFO(priv, "hwcrypto: clear ucode station key info\n");
c587de0b 213 iwl_send_add_sta(priv, &priv->stations[sta_id].sta, 0);
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214 return 0;
215}
216
fa11d525 217static int iwl3945_set_dynamic_key(struct iwl_priv *priv,
6e21f15c
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218 struct ieee80211_key_conf *keyconf, u8 sta_id)
219{
220 int ret = 0;
221
222 keyconf->hw_key_idx = HW_KEY_DYNAMIC;
223
224 switch (keyconf->alg) {
225 case ALG_CCMP:
226 ret = iwl3945_set_ccmp_dynamic_key_info(priv, keyconf, sta_id);
227 break;
228 case ALG_TKIP:
229 ret = iwl3945_set_tkip_dynamic_key_info(priv, keyconf, sta_id);
230 break;
231 case ALG_WEP:
232 ret = iwl3945_set_wep_dynamic_key_info(priv, keyconf, sta_id);
233 break;
234 default:
1e680233 235 IWL_ERR(priv, "Unknown alg: %s alg = %d\n", __func__, keyconf->alg);
6e21f15c
AK
236 ret = -EINVAL;
237 }
238
239 IWL_DEBUG_WEP(priv, "Set dynamic key: alg= %d len=%d idx=%d sta=%d ret=%d\n",
240 keyconf->alg, keyconf->keylen, keyconf->keyidx,
241 sta_id, ret);
242
243 return ret;
244}
245
246static int iwl3945_remove_static_key(struct iwl_priv *priv)
247{
248 int ret = -EOPNOTSUPP;
249
250 return ret;
251}
252
253static int iwl3945_set_static_key(struct iwl_priv *priv,
254 struct ieee80211_key_conf *key)
255{
256 if (key->alg == ALG_WEP)
257 return -EOPNOTSUPP;
258
259 IWL_ERR(priv, "Static key invalid: alg %d\n", key->alg);
260 return -EINVAL;
261}
262
4a8a4322 263static void iwl3945_clear_free_frames(struct iwl_priv *priv)
b481de9c
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264{
265 struct list_head *element;
266
e1623446 267 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
b481de9c
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268 priv->frames_count);
269
270 while (!list_empty(&priv->free_frames)) {
271 element = priv->free_frames.next;
272 list_del(element);
bb8c093b 273 kfree(list_entry(element, struct iwl3945_frame, list));
b481de9c
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274 priv->frames_count--;
275 }
276
277 if (priv->frames_count) {
39aadf8c 278 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
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279 priv->frames_count);
280 priv->frames_count = 0;
281 }
282}
283
4a8a4322 284static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv)
b481de9c 285{
bb8c093b 286 struct iwl3945_frame *frame;
b481de9c
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287 struct list_head *element;
288 if (list_empty(&priv->free_frames)) {
289 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
290 if (!frame) {
15b1687c 291 IWL_ERR(priv, "Could not allocate frame!\n");
b481de9c
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292 return NULL;
293 }
294
295 priv->frames_count++;
296 return frame;
297 }
298
299 element = priv->free_frames.next;
300 list_del(element);
bb8c093b 301 return list_entry(element, struct iwl3945_frame, list);
b481de9c
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302}
303
4a8a4322 304static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame)
b481de9c
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305{
306 memset(frame, 0, sizeof(*frame));
307 list_add(&frame->list, &priv->free_frames);
308}
309
4a8a4322 310unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv,
b481de9c 311 struct ieee80211_hdr *hdr,
73ec1cc2 312 int left)
b481de9c
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313{
314
8ccde88a 315 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB
316 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
317 (priv->iw_mode != NL80211_IFTYPE_AP)))
b481de9c
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318 return 0;
319
320 if (priv->ibss_beacon->len > left)
321 return 0;
322
323 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
324
325 return priv->ibss_beacon->len;
326}
327
4a8a4322 328static int iwl3945_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 329{
bb8c093b 330 struct iwl3945_frame *frame;
b481de9c
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331 unsigned int frame_size;
332 int rc;
333 u8 rate;
334
bb8c093b 335 frame = iwl3945_get_free_frame(priv);
b481de9c
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336
337 if (!frame) {
15b1687c 338 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
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339 "command.\n");
340 return -ENOMEM;
341 }
342
8ccde88a 343 rate = iwl_rate_get_lowest_plcp(priv);
b481de9c 344
bb8c093b 345 frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 346
518099a8 347 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
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348 &frame->u.cmd[0]);
349
bb8c093b 350 iwl3945_free_frame(priv, frame);
b481de9c
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351
352 return rc;
353}
354
4a8a4322 355static void iwl3945_unset_hw_params(struct iwl_priv *priv)
b481de9c 356{
3832ec9d 357 if (priv->shared_virt)
b481de9c 358 pci_free_consistent(priv->pci_dev,
bb8c093b 359 sizeof(struct iwl3945_shared),
3832ec9d
AK
360 priv->shared_virt,
361 priv->shared_phys);
b481de9c
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362}
363
b481de9c 364#define MAX_UCODE_BEACON_INTERVAL 1024
c1b4aa3f 365#define INTEL_CONN_LISTEN_INTERVAL cpu_to_le16(0xA)
b481de9c 366
bb8c093b 367static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
b481de9c
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368{
369 u16 new_val = 0;
370 u16 beacon_factor = 0;
371
372 beacon_factor =
373 (beacon_val + MAX_UCODE_BEACON_INTERVAL)
374 / MAX_UCODE_BEACON_INTERVAL;
375 new_val = beacon_val / beacon_factor;
376
377 return cpu_to_le16(new_val);
378}
379
4a8a4322 380static void iwl3945_setup_rxon_timing(struct iwl_priv *priv)
b481de9c
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381{
382 u64 interval_tm_unit;
383 u64 tsf, result;
384 unsigned long flags;
385 struct ieee80211_conf *conf = NULL;
386 u16 beacon_int = 0;
387
388 conf = ieee80211_get_hw_conf(priv->hw);
389
390 spin_lock_irqsave(&priv->lock, flags);
28afaf91 391 priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
b481de9c
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392 priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
393
28afaf91 394 tsf = priv->timestamp;
b481de9c
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395
396 beacon_int = priv->beacon_int;
397 spin_unlock_irqrestore(&priv->lock, flags);
398
05c914fe 399 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
b481de9c
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400 if (beacon_int == 0) {
401 priv->rxon_timing.beacon_interval = cpu_to_le16(100);
402 priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
403 } else {
404 priv->rxon_timing.beacon_interval =
405 cpu_to_le16(beacon_int);
406 priv->rxon_timing.beacon_interval =
bb8c093b 407 iwl3945_adjust_beacon_interval(
b481de9c
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408 le16_to_cpu(priv->rxon_timing.beacon_interval));
409 }
410
411 priv->rxon_timing.atim_window = 0;
412 } else {
413 priv->rxon_timing.beacon_interval =
57c4d7b4
JB
414 iwl3945_adjust_beacon_interval(
415 priv->vif->bss_conf.beacon_int);
b481de9c
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416 /* TODO: we need to get atim_window from upper stack
417 * for now we set to 0 */
418 priv->rxon_timing.atim_window = 0;
419 }
420
421 interval_tm_unit =
422 (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
423 result = do_div(tsf, interval_tm_unit);
424 priv->rxon_timing.beacon_init_val =
425 cpu_to_le32((u32) ((u64) interval_tm_unit - result));
426
e1623446
TW
427 IWL_DEBUG_ASSOC(priv,
428 "beacon interval %d beacon timer %d beacon tim %d\n",
b481de9c
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429 le16_to_cpu(priv->rxon_timing.beacon_interval),
430 le32_to_cpu(priv->rxon_timing.beacon_init_val),
431 le16_to_cpu(priv->rxon_timing.atim_window));
432}
433
4a8a4322 434static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv,
e039fa4a 435 struct ieee80211_tx_info *info,
c2d79b48 436 struct iwl_cmd *cmd,
b481de9c 437 struct sk_buff *skb_frag,
6e21f15c 438 int sta_id)
b481de9c 439{
e52119c5 440 struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
c587de0b 441 struct iwl_hw_key *keyinfo = &priv->stations[sta_id].keyinfo;
b481de9c
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442
443 switch (keyinfo->alg) {
444 case ALG_CCMP:
e52119c5
WT
445 tx->sec_ctl = TX_CMD_SEC_CCM;
446 memcpy(tx->key, keyinfo->key, keyinfo->keylen);
e1623446 447 IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
b481de9c
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448 break;
449
450 case ALG_TKIP:
b481de9c
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451 break;
452
453 case ALG_WEP:
e52119c5 454 tx->sec_ctl = TX_CMD_SEC_WEP |
e039fa4a 455 (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
b481de9c
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456
457 if (keyinfo->keylen == 13)
e52119c5 458 tx->sec_ctl |= TX_CMD_SEC_KEY128;
b481de9c 459
e52119c5 460 memcpy(&tx->key[3], keyinfo->key, keyinfo->keylen);
b481de9c 461
e1623446 462 IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
e039fa4a 463 "with key %d\n", info->control.hw_key->hw_key_idx);
b481de9c
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464 break;
465
b481de9c 466 default:
978785a3 467 IWL_ERR(priv, "Unknown encode alg %d\n", keyinfo->alg);
b481de9c
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468 break;
469 }
470}
471
472/*
473 * handle build REPLY_TX command notification.
474 */
4a8a4322 475static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv,
c2d79b48 476 struct iwl_cmd *cmd,
e039fa4a 477 struct ieee80211_tx_info *info,
e52119c5 478 struct ieee80211_hdr *hdr, u8 std_id)
b481de9c 479{
e52119c5
WT
480 struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
481 __le32 tx_flags = tx->tx_flags;
fd7c8a40 482 __le16 fc = hdr->frame_control;
e6a9854b 483 u8 rc_flags = info->control.rates[0].flags;
b481de9c 484
e52119c5 485 tx->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e039fa4a 486 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
b481de9c 487 tx_flags |= TX_CMD_FLG_ACK_MSK;
fd7c8a40 488 if (ieee80211_is_mgmt(fc))
b481de9c 489 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
fd7c8a40 490 if (ieee80211_is_probe_resp(fc) &&
b481de9c
ZY
491 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
492 tx_flags |= TX_CMD_FLG_TSF_MSK;
493 } else {
494 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
495 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
496 }
497
e52119c5 498 tx->sta_id = std_id;
8b7b1e05 499 if (ieee80211_has_morefrags(fc))
b481de9c
ZY
500 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
501
fd7c8a40
HH
502 if (ieee80211_is_data_qos(fc)) {
503 u8 *qc = ieee80211_get_qos_ctl(hdr);
e52119c5 504 tx->tid_tspec = qc[0] & 0xf;
b481de9c 505 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 506 } else {
b481de9c 507 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 508 }
b481de9c 509
e6a9854b 510 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
b481de9c
ZY
511 tx_flags |= TX_CMD_FLG_RTS_MSK;
512 tx_flags &= ~TX_CMD_FLG_CTS_MSK;
e6a9854b 513 } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
b481de9c
ZY
514 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
515 tx_flags |= TX_CMD_FLG_CTS_MSK;
516 }
517
518 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
519 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
520
521 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
fd7c8a40
HH
522 if (ieee80211_is_mgmt(fc)) {
523 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
e52119c5 524 tx->timeout.pm_frame_timeout = cpu_to_le16(3);
b481de9c 525 else
e52119c5 526 tx->timeout.pm_frame_timeout = cpu_to_le16(2);
ab53d8af 527 } else {
e52119c5 528 tx->timeout.pm_frame_timeout = 0;
5c8df2d5 529#ifdef CONFIG_IWLWIFI_LEDS
ab53d8af
MA
530 priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
531#endif
532 }
b481de9c 533
e52119c5
WT
534 tx->driver_txop = 0;
535 tx->tx_flags = tx_flags;
536 tx->next_frame_len = 0;
b481de9c
ZY
537}
538
b481de9c
ZY
539/*
540 * start REPLY_TX command process
541 */
4a8a4322 542static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
b481de9c
ZY
543{
544 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
e039fa4a 545 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
e52119c5 546 struct iwl3945_tx_cmd *tx;
188cf6c7 547 struct iwl_tx_queue *txq = NULL;
d20b3c65 548 struct iwl_queue *q = NULL;
e52119c5 549 struct iwl_cmd *out_cmd = NULL;
b481de9c
ZY
550 dma_addr_t phys_addr;
551 dma_addr_t txcmd_phys;
e52119c5 552 int txq_id = skb_get_queue_mapping(skb);
df833b1d 553 u16 len, idx, len_org, hdr_len; /* TODO: len_org is not used */
54dbb525
TW
554 u8 id;
555 u8 unicast;
b481de9c 556 u8 sta_id;
54dbb525 557 u8 tid = 0;
b481de9c 558 u16 seq_number = 0;
fd7c8a40 559 __le16 fc;
b481de9c 560 u8 wait_write_ptr = 0;
54dbb525 561 u8 *qc = NULL;
b481de9c
ZY
562 unsigned long flags;
563 int rc;
564
565 spin_lock_irqsave(&priv->lock, flags);
775a6e27 566 if (iwl_is_rfkill(priv)) {
e1623446 567 IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
b481de9c
ZY
568 goto drop_unlock;
569 }
570
e039fa4a 571 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
15b1687c 572 IWL_ERR(priv, "ERROR: No TX rate available.\n");
b481de9c
ZY
573 goto drop_unlock;
574 }
575
576 unicast = !is_multicast_ether_addr(hdr->addr1);
577 id = 0;
578
fd7c8a40 579 fc = hdr->frame_control;
b481de9c 580
d08853a3 581#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c 582 if (ieee80211_is_auth(fc))
e1623446 583 IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
fd7c8a40 584 else if (ieee80211_is_assoc_req(fc))
e1623446 585 IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
fd7c8a40 586 else if (ieee80211_is_reassoc_req(fc))
e1623446 587 IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
b481de9c
ZY
588#endif
589
7878a5a4 590 /* drop all data frame if we are not associated */
914233d6 591 if (ieee80211_is_data(fc) &&
279b05d4 592 (!iwl_is_monitor_mode(priv)) && /* packet injection */
8ccde88a 593 (!iwl_is_associated(priv) ||
05c914fe 594 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
e1623446 595 IWL_DEBUG_DROP(priv, "Dropping - !iwl_is_associated\n");
b481de9c
ZY
596 goto drop_unlock;
597 }
598
599 spin_unlock_irqrestore(&priv->lock, flags);
600
7294ec95 601 hdr_len = ieee80211_hdrlen(fc);
6440adb5
CB
602
603 /* Find (or create) index into station table for destination station */
f5d30266 604 sta_id = iwl_get_sta_id(priv, hdr);
b481de9c 605 if (sta_id == IWL_INVALID_STATION) {
e1623446 606 IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
e174961c 607 hdr->addr1);
b481de9c
ZY
608 goto drop;
609 }
610
e1623446 611 IWL_DEBUG_RATE(priv, "station Id %d\n", sta_id);
b481de9c 612
fd7c8a40
HH
613 if (ieee80211_is_data_qos(fc)) {
614 qc = ieee80211_get_qos_ctl(hdr);
7294ec95 615 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
c587de0b 616 seq_number = priv->stations[sta_id].tid[tid].seq_number &
b481de9c
ZY
617 IEEE80211_SCTL_SEQ;
618 hdr->seq_ctrl = cpu_to_le16(seq_number) |
619 (hdr->seq_ctrl &
c1b4aa3f 620 cpu_to_le16(IEEE80211_SCTL_FRAG));
b481de9c
ZY
621 seq_number += 0x10;
622 }
6440adb5
CB
623
624 /* Descriptor for chosen Tx queue */
188cf6c7 625 txq = &priv->txq[txq_id];
b481de9c
ZY
626 q = &txq->q;
627
628 spin_lock_irqsave(&priv->lock, flags);
629
fc4b6853 630 idx = get_cmd_index(q, q->write_ptr, 0);
b481de9c 631
6440adb5 632 /* Set up driver data for this TFD */
dbb6654c 633 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
fc4b6853 634 txq->txb[q->write_ptr].skb[0] = skb;
6440adb5
CB
635
636 /* Init first empty entry in queue's array of Tx/cmd buffers */
188cf6c7 637 out_cmd = txq->cmd[idx];
e52119c5 638 tx = (struct iwl3945_tx_cmd *)out_cmd->cmd.payload;
b481de9c 639 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
e52119c5 640 memset(tx, 0, sizeof(*tx));
6440adb5
CB
641
642 /*
643 * Set up the Tx-command (not MAC!) header.
644 * Store the chosen Tx queue and TFD index within the sequence field;
645 * after Tx, uCode's Tx response will return this value so driver can
646 * locate the frame within the tx queue and do post-tx processing.
647 */
b481de9c
ZY
648 out_cmd->hdr.cmd = REPLY_TX;
649 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
fc4b6853 650 INDEX_TO_SEQ(q->write_ptr)));
6440adb5
CB
651
652 /* Copy MAC header from skb into command buffer */
e52119c5 653 memcpy(tx->hdr, hdr, hdr_len);
b481de9c 654
df833b1d
RC
655
656 if (info->control.hw_key)
657 iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, sta_id);
658
659 /* TODO need this for burst mode later on */
660 iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, sta_id);
661
662 /* set is_hcca to 0; it probably will never be implemented */
663 iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
664
665 /* Total # bytes to be transmitted */
666 len = (u16)skb->len;
667 tx->len = cpu_to_le16(len);
668
669
670 tx->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
671 tx->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
672
673 if (!ieee80211_has_morefrags(hdr->frame_control)) {
674 txq->need_update = 1;
675 if (qc)
c587de0b 676 priv->stations[sta_id].tid[tid].seq_number = seq_number;
df833b1d
RC
677 } else {
678 wait_write_ptr = 1;
679 txq->need_update = 0;
680 }
681
682 IWL_DEBUG_TX(priv, "sequence nr = 0X%x \n",
683 le16_to_cpu(out_cmd->hdr.sequence));
684 IWL_DEBUG_TX(priv, "tx_flags = 0X%x \n", le32_to_cpu(tx->tx_flags));
685 iwl_print_hex_dump(priv, IWL_DL_TX, tx, sizeof(*tx));
686 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx->hdr,
687 ieee80211_hdrlen(fc));
688
6440adb5
CB
689 /*
690 * Use the first empty entry in this queue's command buffer array
691 * to contain the Tx command and MAC header concatenated together
692 * (payload data will be in another buffer).
693 * Size of this varies, due to varying MAC header length.
694 * If end is not dword aligned, we'll have 2 extra bytes at the end
695 * of the MAC header (device reads on dword boundaries).
696 * We'll tell device about this padding later.
697 */
3832ec9d 698 len = sizeof(struct iwl3945_tx_cmd) +
4c897253 699 sizeof(struct iwl_cmd_header) + hdr_len;
b481de9c
ZY
700
701 len_org = len;
702 len = (len + 3) & ~3;
703
704 if (len_org != len)
705 len_org = 1;
706 else
707 len_org = 0;
708
6440adb5
CB
709 /* Physical address of this Tx command's header (not MAC header!),
710 * within command buffer array. */
df833b1d
RC
711 txcmd_phys = pci_map_single(priv->pci_dev, &out_cmd->hdr,
712 len, PCI_DMA_TODEVICE);
713 /* we do not map meta data ... so we can safely access address to
714 * provide to unmap command*/
188cf6c7 715 pci_unmap_addr_set(&out_cmd->meta, mapping, txcmd_phys);
df833b1d 716 pci_unmap_len_set(&out_cmd->meta, len, len);
b481de9c 717
6440adb5
CB
718 /* Add buffer containing Tx command and MAC(!) header to TFD's
719 * first entry */
7aaa1d79
SO
720 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
721 txcmd_phys, len, 1, 0);
b481de9c 722
b481de9c 723
6440adb5
CB
724 /* Set up TFD's 2nd entry to point directly to remainder of skb,
725 * if any (802.11 null frames have no payload). */
b481de9c
ZY
726 len = skb->len - hdr_len;
727 if (len) {
728 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
729 len, PCI_DMA_TODEVICE);
7aaa1d79
SO
730 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
731 phys_addr, len,
732 0, U32_PAD(len));
b481de9c
ZY
733 }
734
b481de9c 735
6440adb5 736 /* Tell device the write index *just past* this latest filled TFD */
c54b679d 737 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
4f3602c8 738 rc = iwl_txq_update_write_ptr(priv, txq);
b481de9c
ZY
739 spin_unlock_irqrestore(&priv->lock, flags);
740
741 if (rc)
742 return rc;
743
d20b3c65 744 if ((iwl_queue_space(q) < q->high_mark)
b481de9c
ZY
745 && priv->mac80211_registered) {
746 if (wait_write_ptr) {
747 spin_lock_irqsave(&priv->lock, flags);
748 txq->need_update = 1;
4f3602c8 749 iwl_txq_update_write_ptr(priv, txq);
b481de9c
ZY
750 spin_unlock_irqrestore(&priv->lock, flags);
751 }
752
e4e72fb4 753 iwl_stop_queue(priv, skb_get_queue_mapping(skb));
b481de9c
ZY
754 }
755
756 return 0;
757
758drop_unlock:
759 spin_unlock_irqrestore(&priv->lock, flags);
760drop:
761 return -1;
762}
763
c8b0e6e1 764#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY
765
766#include "iwl-spectrum.h"
767
768#define BEACON_TIME_MASK_LOW 0x00FFFFFF
769#define BEACON_TIME_MASK_HIGH 0xFF000000
770#define TIME_UNIT 1024
771
772/*
773 * extended beacon time format
774 * time in usec will be changed into a 32-bit value in 8:24 format
775 * the high 1 byte is the beacon counts
776 * the lower 3 bytes is the time in usec within one beacon interval
777 */
778
bb8c093b 779static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
b481de9c
ZY
780{
781 u32 quot;
782 u32 rem;
783 u32 interval = beacon_interval * 1024;
784
785 if (!interval || !usec)
786 return 0;
787
788 quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
789 rem = (usec % interval) & BEACON_TIME_MASK_LOW;
790
791 return (quot << 24) + rem;
792}
793
794/* base is usually what we get from ucode with each received frame,
795 * the same as HW timer counter counting down
796 */
797
bb8c093b 798static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
b481de9c
ZY
799{
800 u32 base_low = base & BEACON_TIME_MASK_LOW;
801 u32 addon_low = addon & BEACON_TIME_MASK_LOW;
802 u32 interval = beacon_interval * TIME_UNIT;
803 u32 res = (base & BEACON_TIME_MASK_HIGH) +
804 (addon & BEACON_TIME_MASK_HIGH);
805
806 if (base_low > addon_low)
807 res += base_low - addon_low;
808 else if (base_low < addon_low) {
809 res += interval + base_low - addon_low;
810 res += (1 << 24);
811 } else
812 res += (1 << 24);
813
814 return cpu_to_le32(res);
815}
816
4a8a4322 817static int iwl3945_get_measurement(struct iwl_priv *priv,
b481de9c
ZY
818 struct ieee80211_measurement_params *params,
819 u8 type)
820{
600c0e11 821 struct iwl_spectrum_cmd spectrum;
3d24a9f7 822 struct iwl_rx_packet *res;
c2d79b48 823 struct iwl_host_cmd cmd = {
b481de9c
ZY
824 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
825 .data = (void *)&spectrum,
826 .meta.flags = CMD_WANT_SKB,
827 };
828 u32 add_time = le64_to_cpu(params->start_time);
829 int rc;
830 int spectrum_resp_status;
831 int duration = le16_to_cpu(params->duration);
832
8ccde88a 833 if (iwl_is_associated(priv))
b481de9c 834 add_time =
bb8c093b 835 iwl3945_usecs_to_beacons(
b481de9c
ZY
836 le64_to_cpu(params->start_time) - priv->last_tsf,
837 le16_to_cpu(priv->rxon_timing.beacon_interval));
838
839 memset(&spectrum, 0, sizeof(spectrum));
840
841 spectrum.channel_count = cpu_to_le16(1);
842 spectrum.flags =
843 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
844 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
845 cmd.len = sizeof(spectrum);
846 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
847
8ccde88a 848 if (iwl_is_associated(priv))
b481de9c 849 spectrum.start_time =
bb8c093b 850 iwl3945_add_beacon_time(priv->last_beacon_time,
b481de9c
ZY
851 add_time,
852 le16_to_cpu(priv->rxon_timing.beacon_interval));
853 else
854 spectrum.start_time = 0;
855
856 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
857 spectrum.channels[0].channel = params->channel;
858 spectrum.channels[0].type = type;
8ccde88a 859 if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
b481de9c
ZY
860 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
861 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
862
518099a8 863 rc = iwl_send_cmd_sync(priv, &cmd);
b481de9c
ZY
864 if (rc)
865 return rc;
866
3d24a9f7 867 res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
b481de9c 868 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
15b1687c 869 IWL_ERR(priv, "Bad return from REPLY_RX_ON_ASSOC command\n");
b481de9c
ZY
870 rc = -EIO;
871 }
872
873 spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
874 switch (spectrum_resp_status) {
875 case 0: /* Command will be handled */
876 if (res->u.spectrum.id != 0xff) {
e1623446 877 IWL_DEBUG_INFO(priv, "Replaced existing measurement: %d\n",
bc434dd2 878 res->u.spectrum.id);
b481de9c
ZY
879 priv->measurement_status &= ~MEASUREMENT_READY;
880 }
881 priv->measurement_status |= MEASUREMENT_ACTIVE;
882 rc = 0;
883 break;
884
885 case 1: /* Command will not be handled */
886 rc = -EAGAIN;
887 break;
888 }
889
890 dev_kfree_skb_any(cmd.meta.u.skb);
891
892 return rc;
893}
894#endif
895
4a8a4322 896static void iwl3945_rx_reply_alive(struct iwl_priv *priv,
6100b588 897 struct iwl_rx_mem_buffer *rxb)
b481de9c 898{
3d24a9f7
TW
899 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
900 struct iwl_alive_resp *palive;
b481de9c
ZY
901 struct delayed_work *pwork;
902
903 palive = &pkt->u.alive_frame;
904
e1623446 905 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY
906 "0x%01X 0x%01X\n",
907 palive->is_valid, palive->ver_type,
908 palive->ver_subtype);
909
910 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 911 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
3d24a9f7
TW
912 memcpy(&priv->card_alive_init, &pkt->u.alive_frame,
913 sizeof(struct iwl_alive_resp));
b481de9c
ZY
914 pwork = &priv->init_alive_start;
915 } else {
e1623446 916 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 917 memcpy(&priv->card_alive, &pkt->u.alive_frame,
3d24a9f7 918 sizeof(struct iwl_alive_resp));
b481de9c 919 pwork = &priv->alive_start;
bb8c093b 920 iwl3945_disable_events(priv);
b481de9c
ZY
921 }
922
923 /* We delay the ALIVE response by 5ms to
924 * give the HW RF Kill time to activate... */
925 if (palive->is_valid == UCODE_VALID_OK)
926 queue_delayed_work(priv->workqueue, pwork,
927 msecs_to_jiffies(5));
928 else
39aadf8c 929 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY
930}
931
4a8a4322 932static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv,
6100b588 933 struct iwl_rx_mem_buffer *rxb)
b481de9c 934{
c7e035a9 935#ifdef CONFIG_IWLWIFI_DEBUG
3d24a9f7 936 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
c7e035a9 937#endif
b481de9c 938
e1623446 939 IWL_DEBUG_RX(priv, "Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
b481de9c
ZY
940 return;
941}
942
bb8c093b 943static void iwl3945_bg_beacon_update(struct work_struct *work)
b481de9c 944{
4a8a4322
AK
945 struct iwl_priv *priv =
946 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY
947 struct sk_buff *beacon;
948
949 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 950 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY
951
952 if (!beacon) {
15b1687c 953 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY
954 return;
955 }
956
957 mutex_lock(&priv->mutex);
958 /* new beacon skb is allocated every time; dispose previous.*/
959 if (priv->ibss_beacon)
960 dev_kfree_skb(priv->ibss_beacon);
961
962 priv->ibss_beacon = beacon;
963 mutex_unlock(&priv->mutex);
964
bb8c093b 965 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
966}
967
4a8a4322 968static void iwl3945_rx_beacon_notif(struct iwl_priv *priv,
6100b588 969 struct iwl_rx_mem_buffer *rxb)
b481de9c 970{
d08853a3 971#ifdef CONFIG_IWLWIFI_DEBUG
3d24a9f7 972 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
bb8c093b 973 struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
b481de9c
ZY
974 u8 rate = beacon->beacon_notify_hdr.rate;
975
e1623446 976 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c
ZY
977 "tsf %d %d rate %d\n",
978 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
979 beacon->beacon_notify_hdr.failure_frame,
980 le32_to_cpu(beacon->ibss_mgr_status),
981 le32_to_cpu(beacon->high_tsf),
982 le32_to_cpu(beacon->low_tsf), rate);
983#endif
984
05c914fe 985 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY
986 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
987 queue_work(priv->workqueue, &priv->beacon_update);
988}
989
b481de9c
ZY
990/* Handle notification from uCode that card's power state is changing
991 * due to software, hardware, or critical temperature RFKILL */
4a8a4322 992static void iwl3945_rx_card_state_notif(struct iwl_priv *priv,
6100b588 993 struct iwl_rx_mem_buffer *rxb)
b481de9c 994{
3d24a9f7 995 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY
996 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
997 unsigned long status = priv->status;
998
e1623446 999 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
b481de9c
ZY
1000 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
1001 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
1002
5d49f498 1003 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
1004 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1005
1006 if (flags & HW_CARD_DISABLED)
1007 set_bit(STATUS_RF_KILL_HW, &priv->status);
1008 else
1009 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1010
1011
af0053d6 1012 iwl_scan_cancel(priv);
b481de9c
ZY
1013
1014 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB
1015 test_bit(STATUS_RF_KILL_HW, &priv->status)))
1016 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
1017 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY
1018 else
1019 wake_up_interruptible(&priv->wait_command_queue);
1020}
1021
1022/**
bb8c093b 1023 * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY
1024 *
1025 * Setup the RX handlers for each of the reply types sent from the uCode
1026 * to the host.
1027 *
1028 * This function chains into the hardware specific files for them to setup
1029 * any hardware specific handlers as well.
1030 */
4a8a4322 1031static void iwl3945_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 1032{
bb8c093b
CH
1033 priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
1034 priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
261b9c33 1035 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
8ccde88a 1036 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
030f05ed 1037 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 1038 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
030f05ed 1039 iwl_rx_pm_debug_statistics_notif;
bb8c093b 1040 priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
b481de9c 1041
9fbab516
BC
1042 /*
1043 * The same handler is used for both the REPLY to a discrete
1044 * statistics request from the host as well as for the periodic
1045 * statistics notifications (after received beacons) from the uCode.
b481de9c 1046 */
bb8c093b
CH
1047 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
1048 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
b481de9c 1049
261b9c33 1050 iwl_setup_spectrum_handlers(priv);
cade0eb2 1051 iwl_setup_rx_scan_handlers(priv);
bb8c093b 1052 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
b481de9c 1053
9fbab516 1054 /* Set up hardware specific Rx handlers */
bb8c093b 1055 iwl3945_hw_rx_handler_setup(priv);
b481de9c
ZY
1056}
1057
b481de9c
ZY
1058/************************** RX-FUNCTIONS ****************************/
1059/*
1060 * Rx theory of operation
1061 *
1062 * The host allocates 32 DMA target addresses and passes the host address
1063 * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
1064 * 0 to 31
1065 *
1066 * Rx Queue Indexes
1067 * The host/firmware share two index registers for managing the Rx buffers.
1068 *
1069 * The READ index maps to the first position that the firmware may be writing
1070 * to -- the driver can read up to (but not including) this position and get
1071 * good data.
1072 * The READ index is managed by the firmware once the card is enabled.
1073 *
1074 * The WRITE index maps to the last position the driver has read from -- the
1075 * position preceding WRITE is the last slot the firmware can place a packet.
1076 *
1077 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
1078 * WRITE = READ.
1079 *
9fbab516 1080 * During initialization, the host sets up the READ queue position to the first
b481de9c
ZY
1081 * INDEX position, and WRITE to the last (READ - 1 wrapped)
1082 *
9fbab516 1083 * When the firmware places a packet in a buffer, it will advance the READ index
b481de9c
ZY
1084 * and fire the RX interrupt. The driver can then query the READ index and
1085 * process as many packets as possible, moving the WRITE index forward as it
1086 * resets the Rx queue buffers with new memory.
1087 *
1088 * The management in the driver is as follows:
1089 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
1090 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
01ebd063 1091 * to replenish the iwl->rxq->rx_free.
bb8c093b 1092 * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
b481de9c
ZY
1093 * iwl->rxq is replenished and the READ INDEX is updated (updating the
1094 * 'processed' and 'read' driver indexes as well)
1095 * + A received packet is processed and handed to the kernel network stack,
1096 * detached from the iwl->rxq. The driver 'processed' index is updated.
1097 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
1098 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
1099 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
1100 * were enough free buffers and RX_STALLED is set it is cleared.
1101 *
1102 *
1103 * Driver sequence:
1104 *
9fbab516 1105 * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
bb8c093b 1106 * iwl3945_rx_queue_restock
9fbab516 1107 * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
b481de9c
ZY
1108 * queue, updates firmware pointers, and updates
1109 * the WRITE index. If insufficient rx_free buffers
bb8c093b 1110 * are available, schedules iwl3945_rx_replenish
b481de9c
ZY
1111 *
1112 * -- enable interrupts --
6100b588 1113 * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the
b481de9c
ZY
1114 * READ INDEX, detaching the SKB from the pool.
1115 * Moves the packet buffer from queue to rx_used.
bb8c093b 1116 * Calls iwl3945_rx_queue_restock to refill any empty
b481de9c
ZY
1117 * slots.
1118 * ...
1119 *
1120 */
1121
b481de9c 1122/**
9fbab516 1123 * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
b481de9c 1124 */
4a8a4322 1125static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv,
b481de9c
ZY
1126 dma_addr_t dma_addr)
1127{
1128 return cpu_to_le32((u32)dma_addr);
1129}
1130
1131/**
bb8c093b 1132 * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
b481de9c 1133 *
9fbab516 1134 * If there are slots in the RX queue that need to be restocked,
b481de9c 1135 * and we have free pre-allocated buffers, fill the ranks as much
9fbab516 1136 * as we can, pulling from rx_free.
b481de9c
ZY
1137 *
1138 * This moves the 'write' index forward to catch up with 'processed', and
1139 * also updates the memory address in the firmware to reference the new
1140 * target buffer.
1141 */
4a8a4322 1142static int iwl3945_rx_queue_restock(struct iwl_priv *priv)
b481de9c 1143{
cc2f362c 1144 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c 1145 struct list_head *element;
6100b588 1146 struct iwl_rx_mem_buffer *rxb;
b481de9c
ZY
1147 unsigned long flags;
1148 int write, rc;
1149
1150 spin_lock_irqsave(&rxq->lock, flags);
1151 write = rxq->write & ~0x7;
37d68317 1152 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
6440adb5 1153 /* Get next free Rx buffer, remove from free list */
b481de9c 1154 element = rxq->rx_free.next;
6100b588 1155 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
b481de9c 1156 list_del(element);
6440adb5
CB
1157
1158 /* Point to Rx buffer via next RBD in circular buffer */
6100b588 1159 rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->real_dma_addr);
b481de9c
ZY
1160 rxq->queue[rxq->write] = rxb;
1161 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
1162 rxq->free_count--;
1163 }
1164 spin_unlock_irqrestore(&rxq->lock, flags);
1165 /* If the pre-allocated buffer pool is dropping low, schedule to
1166 * refill it */
1167 if (rxq->free_count <= RX_LOW_WATERMARK)
1168 queue_work(priv->workqueue, &priv->rx_replenish);
1169
1170
6440adb5
CB
1171 /* If we've added more space for the firmware to place data, tell it.
1172 * Increment device's write pointer in multiples of 8. */
d14d4440 1173 if ((rxq->write_actual != (rxq->write & ~0x7))
b481de9c
ZY
1174 || (abs(rxq->write - rxq->read) > 7)) {
1175 spin_lock_irqsave(&rxq->lock, flags);
1176 rxq->need_update = 1;
1177 spin_unlock_irqrestore(&rxq->lock, flags);
141c43a3 1178 rc = iwl_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY
1179 if (rc)
1180 return rc;
1181 }
1182
1183 return 0;
1184}
1185
1186/**
bb8c093b 1187 * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
b481de9c
ZY
1188 *
1189 * When moving to rx_free an SKB is allocated for the slot.
1190 *
bb8c093b 1191 * Also restock the Rx queue via iwl3945_rx_queue_restock.
01ebd063 1192 * This is called as a scheduled work item (except for during initialization)
b481de9c 1193 */
d14d4440 1194static void iwl3945_rx_allocate(struct iwl_priv *priv, gfp_t priority)
b481de9c 1195{
cc2f362c 1196 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c 1197 struct list_head *element;
6100b588 1198 struct iwl_rx_mem_buffer *rxb;
b481de9c 1199 unsigned long flags;
72240498
AK
1200
1201 while (1) {
1202 spin_lock_irqsave(&rxq->lock, flags);
1203
1204 if (list_empty(&rxq->rx_used)) {
1205 spin_unlock_irqrestore(&rxq->lock, flags);
1206 return;
1207 }
1208
b481de9c 1209 element = rxq->rx_used.next;
6100b588 1210 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
72240498
AK
1211 list_del(element);
1212 spin_unlock_irqrestore(&rxq->lock, flags);
6440adb5
CB
1213
1214 /* Alloc a new receive buffer */
b481de9c 1215 rxb->skb =
1e33dc64 1216 alloc_skb(priv->hw_params.rx_buf_size,
d14d4440 1217 priority);
b481de9c
ZY
1218 if (!rxb->skb) {
1219 if (net_ratelimit())
978785a3 1220 IWL_CRIT(priv, ": Can not allocate SKB buffers\n");
b481de9c
ZY
1221 /* We don't reschedule replenish work here -- we will
1222 * call the restock method and if it still needs
1223 * more buffers it will schedule replenish */
1224 break;
1225 }
12342c47
ZY
1226
1227 /* If radiotap head is required, reserve some headroom here.
1228 * The physical head count is a variable rx_stats->phy_count.
1229 * We reserve 4 bytes here. Plus these extra bytes, the
1230 * headroom of the physical head should be enough for the
1231 * radiotap head that iwl3945 supported. See iwl3945_rt.
1232 */
1233 skb_reserve(rxb->skb, 4);
1234
6440adb5 1235 /* Get physical address of RB/SKB */
1e33dc64
WT
1236 rxb->real_dma_addr = pci_map_single(priv->pci_dev,
1237 rxb->skb->data,
1238 priv->hw_params.rx_buf_size,
1239 PCI_DMA_FROMDEVICE);
72240498
AK
1240
1241 spin_lock_irqsave(&rxq->lock, flags);
b481de9c 1242 list_add_tail(&rxb->list, &rxq->rx_free);
72240498 1243 priv->alloc_rxb_skb++;
b481de9c 1244 rxq->free_count++;
72240498 1245 spin_unlock_irqrestore(&rxq->lock, flags);
b481de9c 1246 }
5c0eef96
MA
1247}
1248
df833b1d
RC
1249void iwl3945_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
1250{
1251 unsigned long flags;
1252 int i;
1253 spin_lock_irqsave(&rxq->lock, flags);
1254 INIT_LIST_HEAD(&rxq->rx_free);
1255 INIT_LIST_HEAD(&rxq->rx_used);
1256 /* Fill the rx_used queue with _all_ of the Rx buffers */
1257 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
1258 /* In the reset function, these buffers may have been allocated
1259 * to an SKB, so we need to unmap and free potential storage */
1260 if (rxq->pool[i].skb != NULL) {
1261 pci_unmap_single(priv->pci_dev,
1262 rxq->pool[i].real_dma_addr,
1263 priv->hw_params.rx_buf_size,
1264 PCI_DMA_FROMDEVICE);
1265 priv->alloc_rxb_skb--;
1266 dev_kfree_skb(rxq->pool[i].skb);
1267 rxq->pool[i].skb = NULL;
1268 }
1269 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
1270 }
1271
1272 /* Set us so that we have processed and used all buffers, but have
1273 * not restocked the Rx queue with fresh buffers */
1274 rxq->read = rxq->write = 0;
1275 rxq->free_count = 0;
d14d4440 1276 rxq->write_actual = 0;
df833b1d
RC
1277 spin_unlock_irqrestore(&rxq->lock, flags);
1278}
df833b1d 1279
5c0eef96
MA
1280void iwl3945_rx_replenish(void *data)
1281{
4a8a4322 1282 struct iwl_priv *priv = data;
5c0eef96
MA
1283 unsigned long flags;
1284
d14d4440 1285 iwl3945_rx_allocate(priv, GFP_KERNEL);
b481de9c
ZY
1286
1287 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 1288 iwl3945_rx_queue_restock(priv);
b481de9c
ZY
1289 spin_unlock_irqrestore(&priv->lock, flags);
1290}
1291
d14d4440
AK
1292static void iwl3945_rx_replenish_now(struct iwl_priv *priv)
1293{
1294 iwl3945_rx_allocate(priv, GFP_ATOMIC);
1295
1296 iwl3945_rx_queue_restock(priv);
1297}
1298
1299
df833b1d
RC
1300/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
1301 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
1302 * This free routine walks the list of POOL entries and if SKB is set to
1303 * non NULL it is unmapped and freed
1304 */
1305static void iwl3945_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
1306{
1307 int i;
1308 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
1309 if (rxq->pool[i].skb != NULL) {
1310 pci_unmap_single(priv->pci_dev,
1311 rxq->pool[i].real_dma_addr,
1312 priv->hw_params.rx_buf_size,
1313 PCI_DMA_FROMDEVICE);
1314 dev_kfree_skb(rxq->pool[i].skb);
1315 }
1316 }
1317
1318 pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
1319 rxq->dma_addr);
1320 pci_free_consistent(priv->pci_dev, sizeof(struct iwl_rb_status),
1321 rxq->rb_stts, rxq->rb_stts_dma);
1322 rxq->bd = NULL;
1323 rxq->rb_stts = NULL;
1324}
df833b1d
RC
1325
1326
b481de9c
ZY
1327/* Convert linear signal-to-noise ratio into dB */
1328static u8 ratio2dB[100] = {
1329/* 0 1 2 3 4 5 6 7 8 9 */
1330 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
1331 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
1332 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
1333 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
1334 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
1335 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
1336 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
1337 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
1338 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
1339 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
1340};
1341
1342/* Calculates a relative dB value from a ratio of linear
1343 * (i.e. not dB) signal levels.
1344 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
bb8c093b 1345int iwl3945_calc_db_from_ratio(int sig_ratio)
b481de9c 1346{
221c80cf
AB
1347 /* 1000:1 or higher just report as 60 dB */
1348 if (sig_ratio >= 1000)
b481de9c
ZY
1349 return 60;
1350
221c80cf 1351 /* 100:1 or higher, divide by 10 and use table,
b481de9c 1352 * add 20 dB to make up for divide by 10 */
221c80cf 1353 if (sig_ratio >= 100)
3ac7f146 1354 return 20 + (int)ratio2dB[sig_ratio/10];
b481de9c
ZY
1355
1356 /* We shouldn't see this */
1357 if (sig_ratio < 1)
1358 return 0;
1359
1360 /* Use table for ratios 1:1 - 99:1 */
1361 return (int)ratio2dB[sig_ratio];
1362}
1363
1364#define PERFECT_RSSI (-20) /* dBm */
1365#define WORST_RSSI (-95) /* dBm */
1366#define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
1367
1368/* Calculate an indication of rx signal quality (a percentage, not dBm!).
1369 * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
1370 * about formulas used below. */
bb8c093b 1371int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
b481de9c
ZY
1372{
1373 int sig_qual;
1374 int degradation = PERFECT_RSSI - rssi_dbm;
1375
1376 /* If we get a noise measurement, use signal-to-noise ratio (SNR)
1377 * as indicator; formula is (signal dbm - noise dbm).
1378 * SNR at or above 40 is a great signal (100%).
1379 * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
1380 * Weakest usable signal is usually 10 - 15 dB SNR. */
1381 if (noise_dbm) {
1382 if (rssi_dbm - noise_dbm >= 40)
1383 return 100;
1384 else if (rssi_dbm < noise_dbm)
1385 return 0;
1386 sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
1387
1388 /* Else use just the signal level.
1389 * This formula is a least squares fit of data points collected and
1390 * compared with a reference system that had a percentage (%) display
1391 * for signal quality. */
1392 } else
1393 sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
1394 (15 * RSSI_RANGE + 62 * degradation)) /
1395 (RSSI_RANGE * RSSI_RANGE);
1396
1397 if (sig_qual > 100)
1398 sig_qual = 100;
1399 else if (sig_qual < 1)
1400 sig_qual = 0;
1401
1402 return sig_qual;
1403}
1404
1405/**
9fbab516 1406 * iwl3945_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
1407 *
1408 * Uses the priv->rx_handlers callback function array to invoke
1409 * the appropriate handlers, including command responses,
1410 * frame-received notifications, and other notifications.
1411 */
4a8a4322 1412static void iwl3945_rx_handle(struct iwl_priv *priv)
b481de9c 1413{
6100b588 1414 struct iwl_rx_mem_buffer *rxb;
3d24a9f7 1415 struct iwl_rx_packet *pkt;
cc2f362c 1416 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
1417 u32 r, i;
1418 int reclaim;
1419 unsigned long flags;
5c0eef96 1420 u8 fill_rx = 0;
d68ab680 1421 u32 count = 8;
d14d4440 1422 int total_empty = 0;
b481de9c 1423
6440adb5
CB
1424 /* uCode's read index (stored in shared DRAM) indicates the last Rx
1425 * buffer that the driver may process (last buffer filled by ucode). */
8cd812bc 1426 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY
1427 i = rxq->read;
1428
d14d4440
AK
1429 /* calculate total frames need to be restock after handling RX */
1430 total_empty = r - priv->rxq.write_actual;
1431 if (total_empty < 0)
1432 total_empty += RX_QUEUE_SIZE;
1433
1434 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96 1435 fill_rx = 1;
b481de9c
ZY
1436 /* Rx interrupt, but nothing sent from uCode */
1437 if (i == r)
e1623446 1438 IWL_DEBUG(priv, IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
b481de9c
ZY
1439
1440 while (i != r) {
1441 rxb = rxq->queue[i];
1442
9fbab516 1443 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
1444 * then a bug has been introduced in the queue refilling
1445 * routines -- catch it here */
1446 BUG_ON(rxb == NULL);
1447
1448 rxq->queue[i] = NULL;
1449
df833b1d
RC
1450 pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
1451 priv->hw_params.rx_buf_size,
1452 PCI_DMA_FROMDEVICE);
3d24a9f7 1453 pkt = (struct iwl_rx_packet *)rxb->skb->data;
b481de9c
ZY
1454
1455 /* Reclaim a command buffer only if this packet is a response
1456 * to a (driver-originated) command.
1457 * If the packet (e.g. Rx frame) originated from uCode,
1458 * there is no command buffer to reclaim.
1459 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1460 * but apparently a few don't get set; catch them here. */
1461 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
1462 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
1463 (pkt->hdr.cmd != REPLY_TX);
1464
1465 /* Based on type of command response or notification,
1466 * handle those that need handling via function in
bb8c093b 1467 * rx_handlers table. See iwl3945_setup_rx_handlers() */
b481de9c 1468 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 1469 IWL_DEBUG(priv, IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR,
b481de9c
ZY
1470 "r = %d, i = %d, %s, 0x%02x\n", r, i,
1471 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
1472 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
86ddbf62 1473 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
b481de9c
ZY
1474 } else {
1475 /* No handling needed */
e1623446 1476 IWL_DEBUG(priv, IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR,
b481de9c
ZY
1477 "r %d i %d No handler needed for %s, 0x%02x\n",
1478 r, i, get_cmd_string(pkt->hdr.cmd),
1479 pkt->hdr.cmd);
1480 }
1481
1482 if (reclaim) {
9fbab516 1483 /* Invoke any callbacks, transfer the skb to caller, and
518099a8 1484 * fire off the (possibly) blocking iwl_send_cmd()
b481de9c
ZY
1485 * as we reclaim the driver command queue */
1486 if (rxb && rxb->skb)
732587ab 1487 iwl_tx_cmd_complete(priv, rxb);
b481de9c 1488 else
39aadf8c 1489 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY
1490 }
1491
1492 /* For now we just don't re-use anything. We can tweak this
1493 * later to try and re-use notification packets and SKBs that
1494 * fail to Rx correctly */
1495 if (rxb->skb != NULL) {
1496 priv->alloc_rxb_skb--;
1497 dev_kfree_skb_any(rxb->skb);
1498 rxb->skb = NULL;
1499 }
1500
b481de9c
ZY
1501 spin_lock_irqsave(&rxq->lock, flags);
1502 list_add_tail(&rxb->list, &priv->rxq.rx_used);
1503 spin_unlock_irqrestore(&rxq->lock, flags);
1504 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
1505 /* If there are a lot of unused frames,
1506 * restock the Rx queue so ucode won't assert. */
1507 if (fill_rx) {
1508 count++;
1509 if (count >= 8) {
1510 priv->rxq.read = i;
d14d4440 1511 iwl3945_rx_replenish_now(priv);
5c0eef96
MA
1512 count = 0;
1513 }
1514 }
b481de9c
ZY
1515 }
1516
1517 /* Backtrack one entry */
1518 priv->rxq.read = i;
d14d4440
AK
1519 if (fill_rx)
1520 iwl3945_rx_replenish_now(priv);
1521 else
1522 iwl3945_rx_queue_restock(priv);
b481de9c
ZY
1523}
1524
0359facc 1525/* call this function to flush any scheduled tasklet */
4a8a4322 1526static inline void iwl_synchronize_irq(struct iwl_priv *priv)
0359facc 1527{
a96a27f9 1528 /* wait to make sure we flush pending tasklet*/
0359facc
MA
1529 synchronize_irq(priv->pci_dev->irq);
1530 tasklet_kill(&priv->irq_tasklet);
1531}
1532
b481de9c
ZY
1533static const char *desc_lookup(int i)
1534{
1535 switch (i) {
1536 case 1:
1537 return "FAIL";
1538 case 2:
1539 return "BAD_PARAM";
1540 case 3:
1541 return "BAD_CHECKSUM";
1542 case 4:
1543 return "NMI_INTERRUPT";
1544 case 5:
1545 return "SYSASSERT";
1546 case 6:
1547 return "FATAL_ERROR";
1548 }
1549
1550 return "UNKNOWN";
1551}
1552
1553#define ERROR_START_OFFSET (1 * sizeof(u32))
1554#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1555
4a8a4322 1556static void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
b481de9c
ZY
1557{
1558 u32 i;
1559 u32 desc, time, count, base, data1;
1560 u32 blink1, blink2, ilink1, ilink2;
b481de9c
ZY
1561
1562 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1563
bb8c093b 1564 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 1565 IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
b481de9c
ZY
1566 return;
1567 }
1568
b481de9c 1569
5d49f498 1570 count = iwl_read_targ_mem(priv, base);
b481de9c
ZY
1571
1572 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
15b1687c
WT
1573 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1574 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1575 priv->status, count);
b481de9c
ZY
1576 }
1577
15b1687c 1578 IWL_ERR(priv, "Desc Time asrtPC blink2 "
b481de9c
ZY
1579 "ilink1 nmiPC Line\n");
1580 for (i = ERROR_START_OFFSET;
1581 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
1582 i += ERROR_ELEM_SIZE) {
5d49f498 1583 desc = iwl_read_targ_mem(priv, base + i);
b481de9c 1584 time =
5d49f498 1585 iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32));
b481de9c 1586 blink1 =
5d49f498 1587 iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32));
b481de9c 1588 blink2 =
5d49f498 1589 iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32));
b481de9c 1590 ilink1 =
5d49f498 1591 iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32));
b481de9c 1592 ilink2 =
5d49f498 1593 iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32));
b481de9c 1594 data1 =
5d49f498 1595 iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32));
b481de9c 1596
15b1687c
WT
1597 IWL_ERR(priv,
1598 "%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
1599 desc_lookup(desc), desc, time, blink1, blink2,
1600 ilink1, ilink2, data1);
b481de9c
ZY
1601 }
1602
b481de9c
ZY
1603}
1604
f58177b9 1605#define EVENT_START_OFFSET (6 * sizeof(u32))
b481de9c
ZY
1606
1607/**
bb8c093b 1608 * iwl3945_print_event_log - Dump error event log to syslog
b481de9c 1609 *
b481de9c 1610 */
4a8a4322 1611static void iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
b481de9c
ZY
1612 u32 num_events, u32 mode)
1613{
1614 u32 i;
1615 u32 base; /* SRAM byte address of event log header */
1616 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1617 u32 ptr; /* SRAM byte address of log data */
1618 u32 ev, time, data; /* event log data */
1619
1620 if (num_events == 0)
1621 return;
1622
1623 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1624
1625 if (mode == 0)
1626 event_size = 2 * sizeof(u32);
1627 else
1628 event_size = 3 * sizeof(u32);
1629
1630 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1631
1632 /* "time" is actually "data" for mode 0 (no timestamp).
1633 * place event id # at far right for easier visual parsing. */
1634 for (i = 0; i < num_events; i++) {
5d49f498 1635 ev = iwl_read_targ_mem(priv, ptr);
b481de9c 1636 ptr += sizeof(u32);
5d49f498 1637 time = iwl_read_targ_mem(priv, ptr);
b481de9c 1638 ptr += sizeof(u32);
15b1687c
WT
1639 if (mode == 0) {
1640 /* data, ev */
1641 IWL_ERR(priv, "0x%08x\t%04u\n", time, ev);
1642 } else {
5d49f498 1643 data = iwl_read_targ_mem(priv, ptr);
b481de9c 1644 ptr += sizeof(u32);
15b1687c 1645 IWL_ERR(priv, "%010u\t0x%08x\t%04u\n", time, data, ev);
b481de9c
ZY
1646 }
1647 }
1648}
1649
4a8a4322 1650static void iwl3945_dump_nic_event_log(struct iwl_priv *priv)
b481de9c 1651{
b481de9c
ZY
1652 u32 base; /* SRAM byte address of event log header */
1653 u32 capacity; /* event log capacity in # entries */
1654 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1655 u32 num_wraps; /* # times uCode wrapped to top of log */
1656 u32 next_entry; /* index of next entry to be written by uCode */
1657 u32 size; /* # entries that we'll print */
1658
1659 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 1660 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 1661 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
b481de9c
ZY
1662 return;
1663 }
1664
b481de9c 1665 /* event log header */
5d49f498
AK
1666 capacity = iwl_read_targ_mem(priv, base);
1667 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1668 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1669 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
b481de9c
ZY
1670
1671 size = num_wraps ? capacity : next_entry;
1672
1673 /* bail out if nothing in log */
1674 if (size == 0) {
15b1687c 1675 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
b481de9c
ZY
1676 return;
1677 }
1678
15b1687c 1679 IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
b481de9c
ZY
1680 size, num_wraps);
1681
1682 /* if uCode has wrapped back to top of log, start at the oldest entry,
1683 * i.e the next one that uCode would fill. */
1684 if (num_wraps)
bb8c093b 1685 iwl3945_print_event_log(priv, next_entry,
b481de9c
ZY
1686 capacity - next_entry, mode);
1687
1688 /* (then/else) start at top of log */
bb8c093b 1689 iwl3945_print_event_log(priv, 0, next_entry, mode);
b481de9c 1690
b481de9c
ZY
1691}
1692
4a8a4322 1693static void iwl3945_irq_tasklet(struct iwl_priv *priv)
b481de9c
ZY
1694{
1695 u32 inta, handled = 0;
1696 u32 inta_fh;
1697 unsigned long flags;
d08853a3 1698#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
1699 u32 inta_mask;
1700#endif
1701
1702 spin_lock_irqsave(&priv->lock, flags);
1703
1704 /* Ack/clear/reset pending uCode interrupts.
1705 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1706 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
5d49f498
AK
1707 inta = iwl_read32(priv, CSR_INT);
1708 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY
1709
1710 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1711 * Any new interrupts that happen after this, either while we're
1712 * in this tasklet, or later, will show up in next ISR/tasklet. */
5d49f498
AK
1713 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1714 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 1715
d08853a3 1716#ifdef CONFIG_IWLWIFI_DEBUG
40b8ec0b 1717 if (priv->debug_level & IWL_DL_ISR) {
9fbab516 1718 /* just for debug */
5d49f498 1719 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 1720 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY
1721 inta, inta_mask, inta_fh);
1722 }
1723#endif
1724
1725 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1726 * atomic, make sure that inta covers all the interrupts that
1727 * we've discovered, even if FH interrupt came in just after
1728 * reading CSR_INT. */
6f83eaa1 1729 if (inta_fh & CSR39_FH_INT_RX_MASK)
b481de9c 1730 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 1731 if (inta_fh & CSR39_FH_INT_TX_MASK)
b481de9c
ZY
1732 inta |= CSR_INT_BIT_FH_TX;
1733
1734 /* Now service all interrupt bits discovered above. */
1735 if (inta & CSR_INT_BIT_HW_ERR) {
15b1687c 1736 IWL_ERR(priv, "Microcode HW error detected. Restarting.\n");
b481de9c
ZY
1737
1738 /* Tell the device to stop sending interrupts */
ed3b932e 1739 iwl_disable_interrupts(priv);
b481de9c 1740
86ddbf62 1741 priv->isr_stats.hw++;
8ccde88a 1742 iwl_irq_handle_error(priv);
b481de9c
ZY
1743
1744 handled |= CSR_INT_BIT_HW_ERR;
1745
1746 spin_unlock_irqrestore(&priv->lock, flags);
1747
1748 return;
1749 }
1750
d08853a3 1751#ifdef CONFIG_IWLWIFI_DEBUG
40b8ec0b 1752 if (priv->debug_level & (IWL_DL_ISR)) {
b481de9c 1753 /* NIC fires this, but we don't use it, redundant with WAKEUP */
86ddbf62 1754 if (inta & CSR_INT_BIT_SCD) {
e1623446 1755 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1756 "the frame/frames.\n");
86ddbf62
AK
1757 priv->isr_stats.sch++;
1758 }
b481de9c
ZY
1759
1760 /* Alive notification via Rx interrupt will do the real work */
86ddbf62 1761 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 1762 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
86ddbf62
AK
1763 priv->isr_stats.alive++;
1764 }
b481de9c
ZY
1765 }
1766#endif
1767 /* Safely ignore these bits for debug checks below */
25c03d8e 1768 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1769
b481de9c
ZY
1770 /* Error detected by uCode */
1771 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT
1772 IWL_ERR(priv, "Microcode SW error detected. "
1773 "Restarting 0x%X.\n", inta);
86ddbf62
AK
1774 priv->isr_stats.sw++;
1775 priv->isr_stats.sw_err = inta;
8ccde88a 1776 iwl_irq_handle_error(priv);
b481de9c
ZY
1777 handled |= CSR_INT_BIT_SW_ERR;
1778 }
1779
1780 /* uCode wakes up after power-down sleep */
1781 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1782 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
141c43a3 1783 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
4f3602c8
SO
1784 iwl_txq_update_write_ptr(priv, &priv->txq[0]);
1785 iwl_txq_update_write_ptr(priv, &priv->txq[1]);
1786 iwl_txq_update_write_ptr(priv, &priv->txq[2]);
1787 iwl_txq_update_write_ptr(priv, &priv->txq[3]);
1788 iwl_txq_update_write_ptr(priv, &priv->txq[4]);
1789 iwl_txq_update_write_ptr(priv, &priv->txq[5]);
b481de9c 1790
86ddbf62 1791 priv->isr_stats.wakeup++;
b481de9c
ZY
1792 handled |= CSR_INT_BIT_WAKEUP;
1793 }
1794
1795 /* All uCode command responses, including Tx command responses,
1796 * Rx "responses" (frame-received notification), and other
1797 * notifications from uCode come through here*/
1798 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
bb8c093b 1799 iwl3945_rx_handle(priv);
86ddbf62 1800 priv->isr_stats.rx++;
b481de9c
ZY
1801 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1802 }
1803
1804 if (inta & CSR_INT_BIT_FH_TX) {
e1623446 1805 IWL_DEBUG_ISR(priv, "Tx interrupt\n");
86ddbf62 1806 priv->isr_stats.tx++;
b481de9c 1807
5d49f498 1808 iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
a8b50a0a
MA
1809 iwl_write_direct32(priv, FH39_TCSR_CREDIT
1810 (FH39_SRVC_CHNL), 0x0);
b481de9c
ZY
1811 handled |= CSR_INT_BIT_FH_TX;
1812 }
1813
86ddbf62 1814 if (inta & ~handled) {
15b1687c 1815 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
86ddbf62
AK
1816 priv->isr_stats.unhandled++;
1817 }
b481de9c 1818
40cefda9 1819 if (inta & ~priv->inta_mask) {
39aadf8c 1820 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1821 inta & ~priv->inta_mask);
39aadf8c 1822 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY
1823 }
1824
1825 /* Re-enable all interrupts */
0359facc
MA
1826 /* only Re-enable if disabled by irq */
1827 if (test_bit(STATUS_INT_ENABLED, &priv->status))
ed3b932e 1828 iwl_enable_interrupts(priv);
b481de9c 1829
d08853a3 1830#ifdef CONFIG_IWLWIFI_DEBUG
40b8ec0b 1831 if (priv->debug_level & (IWL_DL_ISR)) {
5d49f498
AK
1832 inta = iwl_read32(priv, CSR_INT);
1833 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1834 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1835 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY
1836 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1837 }
1838#endif
1839 spin_unlock_irqrestore(&priv->lock, flags);
1840}
1841
4a8a4322 1842static int iwl3945_get_channels_for_scan(struct iwl_priv *priv,
8318d78a 1843 enum ieee80211_band band,
f9340520 1844 u8 is_active, u8 n_probes,
bb8c093b 1845 struct iwl3945_scan_channel *scan_ch)
b481de9c
ZY
1846{
1847 const struct ieee80211_channel *channels = NULL;
8318d78a 1848 const struct ieee80211_supported_band *sband;
d20b3c65 1849 const struct iwl_channel_info *ch_info;
b481de9c
ZY
1850 u16 passive_dwell = 0;
1851 u16 active_dwell = 0;
1852 int added, i;
1853
cbba18c6 1854 sband = iwl_get_hw_mode(priv, band);
8318d78a 1855 if (!sband)
b481de9c
ZY
1856 return 0;
1857
8318d78a 1858 channels = sband->channels;
b481de9c 1859
77fecfb8
SO
1860 active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
1861 passive_dwell = iwl_get_passive_dwell_time(priv, band);
b481de9c 1862
8f4807a1
AK
1863 if (passive_dwell <= active_dwell)
1864 passive_dwell = active_dwell + 1;
1865
8318d78a 1866 for (i = 0, added = 0; i < sband->n_channels; i++) {
182e2e66
JB
1867 if (channels[i].flags & IEEE80211_CHAN_DISABLED)
1868 continue;
1869
8318d78a 1870 scan_ch->channel = channels[i].hw_value;
b481de9c 1871
e6148917 1872 ch_info = iwl_get_channel_info(priv, band, scan_ch->channel);
b481de9c 1873 if (!is_channel_valid(ch_info)) {
e1623446 1874 IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
b481de9c
ZY
1875 scan_ch->channel);
1876 continue;
1877 }
1878
011a0330
AK
1879 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1880 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1881 /* If passive , set up for auto-switch
1882 * and use long active_dwell time.
1883 */
b481de9c 1884 if (!is_active || is_channel_passive(ch_info) ||
011a0330 1885 (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
b481de9c 1886 scan_ch->type = 0; /* passive */
011a0330
AK
1887 if (IWL_UCODE_API(priv->ucode_ver) == 1)
1888 scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
1889 } else {
b481de9c 1890 scan_ch->type = 1; /* active */
011a0330 1891 }
b481de9c 1892
011a0330
AK
1893 /* Set direct probe bits. These may be used both for active
1894 * scan channels (probes gets sent right away),
1895 * or for passive channels (probes get se sent only after
1896 * hearing clear Rx packet).*/
1897 if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
1898 if (n_probes)
0d21044e 1899 scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes);
011a0330
AK
1900 } else {
1901 /* uCode v1 does not allow setting direct probe bits on
1902 * passive channel. */
1903 if ((scan_ch->type & 1) && n_probes)
0d21044e 1904 scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes);
011a0330 1905 }
b481de9c 1906
9fbab516 1907 /* Set txpower levels to defaults */
b481de9c
ZY
1908 scan_ch->tpc.dsp_atten = 110;
1909 /* scan_pwr_info->tpc.dsp_atten; */
1910
1911 /*scan_pwr_info->tpc.tx_gain; */
8318d78a 1912 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY
1913 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
1914 else {
1915 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
1916 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
9fbab516 1917 * power level:
8a1b0245 1918 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
b481de9c
ZY
1919 */
1920 }
1921
e1623446 1922 IWL_DEBUG_SCAN(priv, "Scanning %d [%s %d]\n",
b481de9c
ZY
1923 scan_ch->channel,
1924 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
1925 (scan_ch->type & 1) ?
1926 active_dwell : passive_dwell);
1927
1928 scan_ch++;
1929 added++;
1930 }
1931
e1623446 1932 IWL_DEBUG_SCAN(priv, "total channels to scan %d \n", added);
b481de9c
ZY
1933 return added;
1934}
1935
4a8a4322 1936static void iwl3945_init_hw_rates(struct iwl_priv *priv,
b481de9c
ZY
1937 struct ieee80211_rate *rates)
1938{
1939 int i;
1940
1941 for (i = 0; i < IWL_RATE_COUNT; i++) {
8318d78a
JB
1942 rates[i].bitrate = iwl3945_rates[i].ieee * 5;
1943 rates[i].hw_value = i; /* Rate scaling will work on indexes */
1944 rates[i].hw_value_short = i;
1945 rates[i].flags = 0;
d9829a67 1946 if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
b481de9c 1947 /*
8318d78a 1948 * If CCK != 1M then set short preamble rate flag.
b481de9c 1949 */
bb8c093b 1950 rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
8318d78a 1951 0 : IEEE80211_RATE_SHORT_PREAMBLE;
b481de9c 1952 }
b481de9c
ZY
1953 }
1954}
1955
b481de9c
ZY
1956/******************************************************************************
1957 *
1958 * uCode download functions
1959 *
1960 ******************************************************************************/
1961
4a8a4322 1962static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1963{
98c92211
TW
1964 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1965 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1966 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1967 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1968 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1969 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY
1970}
1971
1972/**
bb8c093b 1973 * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
b481de9c
ZY
1974 * looking at all data.
1975 */
4a8a4322 1976static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len)
b481de9c
ZY
1977{
1978 u32 val;
1979 u32 save_len = len;
1980 int rc = 0;
1981 u32 errcnt;
1982
e1623446 1983 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b481de9c 1984
5d49f498 1985 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 1986 IWL39_RTC_INST_LOWER_BOUND);
b481de9c
ZY
1987
1988 errcnt = 0;
1989 for (; len > 0; len -= sizeof(u32), image++) {
1990 /* read data comes through single port, auto-incr addr */
1991 /* NOTE: Use the debugless read so we don't flood kernel log
1992 * if IWL_DL_IO is set */
5d49f498 1993 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c 1994 if (val != le32_to_cpu(*image)) {
15b1687c 1995 IWL_ERR(priv, "uCode INST section is invalid at "
b481de9c
ZY
1996 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1997 save_len - len, val, le32_to_cpu(*image));
1998 rc = -EIO;
1999 errcnt++;
2000 if (errcnt >= 20)
2001 break;
2002 }
2003 }
2004
b481de9c
ZY
2005
2006 if (!errcnt)
e1623446
TW
2007 IWL_DEBUG_INFO(priv,
2008 "ucode image in INSTRUCTION memory is good\n");
b481de9c
ZY
2009
2010 return rc;
2011}
2012
2013
2014/**
bb8c093b 2015 * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
b481de9c
ZY
2016 * using sample data 100 bytes apart. If these sample points are good,
2017 * it's a pretty good bet that everything between them is good, too.
2018 */
4a8a4322 2019static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
b481de9c
ZY
2020{
2021 u32 val;
2022 int rc = 0;
2023 u32 errcnt = 0;
2024 u32 i;
2025
e1623446 2026 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b481de9c 2027
b481de9c
ZY
2028 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
2029 /* read data comes through single port, auto-incr addr */
2030 /* NOTE: Use the debugless read so we don't flood kernel log
2031 * if IWL_DL_IO is set */
5d49f498 2032 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 2033 i + IWL39_RTC_INST_LOWER_BOUND);
5d49f498 2034 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY
2035 if (val != le32_to_cpu(*image)) {
2036#if 0 /* Enable this if you want to see details */
15b1687c 2037 IWL_ERR(priv, "uCode INST section is invalid at "
b481de9c
ZY
2038 "offset 0x%x, is 0x%x, s/b 0x%x\n",
2039 i, val, *image);
2040#endif
2041 rc = -EIO;
2042 errcnt++;
2043 if (errcnt >= 3)
2044 break;
2045 }
2046 }
2047
b481de9c
ZY
2048 return rc;
2049}
2050
2051
2052/**
bb8c093b 2053 * iwl3945_verify_ucode - determine which instruction image is in SRAM,
b481de9c
ZY
2054 * and verify its contents
2055 */
4a8a4322 2056static int iwl3945_verify_ucode(struct iwl_priv *priv)
b481de9c
ZY
2057{
2058 __le32 *image;
2059 u32 len;
2060 int rc = 0;
2061
2062 /* Try bootstrap */
2063 image = (__le32 *)priv->ucode_boot.v_addr;
2064 len = priv->ucode_boot.len;
bb8c093b 2065 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c 2066 if (rc == 0) {
e1623446 2067 IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
b481de9c
ZY
2068 return 0;
2069 }
2070
2071 /* Try initialize */
2072 image = (__le32 *)priv->ucode_init.v_addr;
2073 len = priv->ucode_init.len;
bb8c093b 2074 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c 2075 if (rc == 0) {
e1623446 2076 IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
b481de9c
ZY
2077 return 0;
2078 }
2079
2080 /* Try runtime/protocol */
2081 image = (__le32 *)priv->ucode_code.v_addr;
2082 len = priv->ucode_code.len;
bb8c093b 2083 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c 2084 if (rc == 0) {
e1623446 2085 IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
b481de9c
ZY
2086 return 0;
2087 }
2088
15b1687c 2089 IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
b481de9c 2090
9fbab516
BC
2091 /* Since nothing seems to match, show first several data entries in
2092 * instruction SRAM, so maybe visual inspection will give a clue.
2093 * Selection of bootstrap image (vs. other images) is arbitrary. */
b481de9c
ZY
2094 image = (__le32 *)priv->ucode_boot.v_addr;
2095 len = priv->ucode_boot.len;
bb8c093b 2096 rc = iwl3945_verify_inst_full(priv, image, len);
b481de9c
ZY
2097
2098 return rc;
2099}
2100
4a8a4322 2101static void iwl3945_nic_start(struct iwl_priv *priv)
b481de9c
ZY
2102{
2103 /* Remove all resets to allow NIC to operate */
5d49f498 2104 iwl_write32(priv, CSR_RESET, 0);
b481de9c
ZY
2105}
2106
2107/**
bb8c093b 2108 * iwl3945_read_ucode - Read uCode images from disk file.
b481de9c
ZY
2109 *
2110 * Copy into buffers for card to fetch via bus-mastering
2111 */
4a8a4322 2112static int iwl3945_read_ucode(struct iwl_priv *priv)
b481de9c 2113{
a78fe754 2114 struct iwl_ucode *ucode;
a0987a8d 2115 int ret = -EINVAL, index;
b481de9c
ZY
2116 const struct firmware *ucode_raw;
2117 /* firmware file name contains uCode/driver compatibility version */
a0987a8d
RC
2118 const char *name_pre = priv->cfg->fw_name_pre;
2119 const unsigned int api_max = priv->cfg->ucode_api_max;
2120 const unsigned int api_min = priv->cfg->ucode_api_min;
2121 char buf[25];
b481de9c
ZY
2122 u8 *src;
2123 size_t len;
a0987a8d 2124 u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
b481de9c
ZY
2125
2126 /* Ask kernel firmware_class module to get the boot firmware off disk.
2127 * request_firmware() is synchronous, file is in memory on return. */
a0987a8d
RC
2128 for (index = api_max; index >= api_min; index--) {
2129 sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
2130 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
2131 if (ret < 0) {
15b1687c 2132 IWL_ERR(priv, "%s firmware file req failed: %d\n",
a0987a8d
RC
2133 buf, ret);
2134 if (ret == -ENOENT)
2135 continue;
2136 else
2137 goto error;
2138 } else {
2139 if (index < api_max)
15b1687c
WT
2140 IWL_ERR(priv, "Loaded firmware %s, "
2141 "which is deprecated. "
2142 " Please use API v%u instead.\n",
a0987a8d 2143 buf, api_max);
e1623446
TW
2144 IWL_DEBUG_INFO(priv, "Got firmware '%s' file "
2145 "(%zd bytes) from disk\n",
a0987a8d
RC
2146 buf, ucode_raw->size);
2147 break;
2148 }
b481de9c
ZY
2149 }
2150
a0987a8d
RC
2151 if (ret < 0)
2152 goto error;
b481de9c
ZY
2153
2154 /* Make sure that we got at least our header! */
2155 if (ucode_raw->size < sizeof(*ucode)) {
15b1687c 2156 IWL_ERR(priv, "File size way too small!\n");
90e759d1 2157 ret = -EINVAL;
b481de9c
ZY
2158 goto err_release;
2159 }
2160
2161 /* Data from ucode file: header followed by uCode images */
2162 ucode = (void *)ucode_raw->data;
2163
c02b3acd 2164 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 2165 api_ver = IWL_UCODE_API(priv->ucode_ver);
b481de9c
ZY
2166 inst_size = le32_to_cpu(ucode->inst_size);
2167 data_size = le32_to_cpu(ucode->data_size);
2168 init_size = le32_to_cpu(ucode->init_size);
2169 init_data_size = le32_to_cpu(ucode->init_data_size);
2170 boot_size = le32_to_cpu(ucode->boot_size);
2171
a0987a8d
RC
2172 /* api_ver should match the api version forming part of the
2173 * firmware filename ... but we don't check for that and only rely
877d0310 2174 * on the API version read from firmware header from here on forward */
a0987a8d
RC
2175
2176 if (api_ver < api_min || api_ver > api_max) {
15b1687c 2177 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC
2178 "Driver supports v%u, firmware is v%u.\n",
2179 api_max, api_ver);
2180 priv->ucode_ver = 0;
2181 ret = -EINVAL;
2182 goto err_release;
2183 }
2184 if (api_ver != api_max)
15b1687c 2185 IWL_ERR(priv, "Firmware has old API version. Expected %u, "
a0987a8d
RC
2186 "got %u. New firmware can be obtained "
2187 "from http://www.intellinuxwireless.org.\n",
2188 api_max, api_ver);
2189
978785a3
TW
2190 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
2191 IWL_UCODE_MAJOR(priv->ucode_ver),
2192 IWL_UCODE_MINOR(priv->ucode_ver),
2193 IWL_UCODE_API(priv->ucode_ver),
2194 IWL_UCODE_SERIAL(priv->ucode_ver));
2195
e1623446 2196 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
a0987a8d 2197 priv->ucode_ver);
e1623446
TW
2198 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
2199 inst_size);
2200 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
2201 data_size);
2202 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
2203 init_size);
2204 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
2205 init_data_size);
2206 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
2207 boot_size);
b481de9c 2208
a0987a8d 2209
b481de9c
ZY
2210 /* Verify size of file vs. image size info in file's header */
2211 if (ucode_raw->size < sizeof(*ucode) +
2212 inst_size + data_size + init_size +
2213 init_data_size + boot_size) {
2214
e1623446
TW
2215 IWL_DEBUG_INFO(priv, "uCode file size %zd too small\n",
2216 ucode_raw->size);
90e759d1 2217 ret = -EINVAL;
b481de9c
ZY
2218 goto err_release;
2219 }
2220
2221 /* Verify that uCode images will fit in card's SRAM */
250bdd21 2222 if (inst_size > IWL39_MAX_INST_SIZE) {
e1623446 2223 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
90e759d1
TW
2224 inst_size);
2225 ret = -EINVAL;
b481de9c
ZY
2226 goto err_release;
2227 }
2228
250bdd21 2229 if (data_size > IWL39_MAX_DATA_SIZE) {
e1623446 2230 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
90e759d1
TW
2231 data_size);
2232 ret = -EINVAL;
b481de9c
ZY
2233 goto err_release;
2234 }
250bdd21 2235 if (init_size > IWL39_MAX_INST_SIZE) {
e1623446
TW
2236 IWL_DEBUG_INFO(priv,
2237 "uCode init instr len %d too large to fit in\n",
90e759d1
TW
2238 init_size);
2239 ret = -EINVAL;
b481de9c
ZY
2240 goto err_release;
2241 }
250bdd21 2242 if (init_data_size > IWL39_MAX_DATA_SIZE) {
e1623446
TW
2243 IWL_DEBUG_INFO(priv,
2244 "uCode init data len %d too large to fit in\n",
90e759d1
TW
2245 init_data_size);
2246 ret = -EINVAL;
b481de9c
ZY
2247 goto err_release;
2248 }
250bdd21 2249 if (boot_size > IWL39_MAX_BSM_SIZE) {
e1623446
TW
2250 IWL_DEBUG_INFO(priv,
2251 "uCode boot instr len %d too large to fit in\n",
90e759d1
TW
2252 boot_size);
2253 ret = -EINVAL;
b481de9c
ZY
2254 goto err_release;
2255 }
2256
2257 /* Allocate ucode buffers for card's bus-master loading ... */
2258
2259 /* Runtime instructions and 2 copies of data:
2260 * 1) unmodified from disk
2261 * 2) backup cache for save/restore during power-downs */
2262 priv->ucode_code.len = inst_size;
98c92211 2263 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY
2264
2265 priv->ucode_data.len = data_size;
98c92211 2266 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY
2267
2268 priv->ucode_data_backup.len = data_size;
98c92211 2269 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 2270
90e759d1
TW
2271 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2272 !priv->ucode_data_backup.v_addr)
2273 goto err_pci_alloc;
b481de9c
ZY
2274
2275 /* Initialization instructions and data */
90e759d1
TW
2276 if (init_size && init_data_size) {
2277 priv->ucode_init.len = init_size;
98c92211 2278 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW
2279
2280 priv->ucode_init_data.len = init_data_size;
98c92211 2281 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW
2282
2283 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2284 goto err_pci_alloc;
2285 }
b481de9c
ZY
2286
2287 /* Bootstrap (instructions only, no data) */
90e759d1
TW
2288 if (boot_size) {
2289 priv->ucode_boot.len = boot_size;
98c92211 2290 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 2291
90e759d1
TW
2292 if (!priv->ucode_boot.v_addr)
2293 goto err_pci_alloc;
2294 }
b481de9c
ZY
2295
2296 /* Copy images into buffers for card's bus-master reads ... */
2297
2298 /* Runtime instructions (first block of data in file) */
2299 src = &ucode->data[0];
2300 len = priv->ucode_code.len;
e1623446
TW
2301 IWL_DEBUG_INFO(priv,
2302 "Copying (but not loading) uCode instr len %zd\n", len);
b481de9c 2303 memcpy(priv->ucode_code.v_addr, src, len);
e1623446 2304 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY
2305 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2306
2307 /* Runtime data (2nd block)
bb8c093b 2308 * NOTE: Copy into backup buffer will be done in iwl3945_up() */
b481de9c
ZY
2309 src = &ucode->data[inst_size];
2310 len = priv->ucode_data.len;
e1623446
TW
2311 IWL_DEBUG_INFO(priv,
2312 "Copying (but not loading) uCode data len %zd\n", len);
b481de9c
ZY
2313 memcpy(priv->ucode_data.v_addr, src, len);
2314 memcpy(priv->ucode_data_backup.v_addr, src, len);
2315
2316 /* Initialization instructions (3rd block) */
2317 if (init_size) {
2318 src = &ucode->data[inst_size + data_size];
2319 len = priv->ucode_init.len;
e1623446
TW
2320 IWL_DEBUG_INFO(priv,
2321 "Copying (but not loading) init instr len %zd\n", len);
b481de9c
ZY
2322 memcpy(priv->ucode_init.v_addr, src, len);
2323 }
2324
2325 /* Initialization data (4th block) */
2326 if (init_data_size) {
2327 src = &ucode->data[inst_size + data_size + init_size];
2328 len = priv->ucode_init_data.len;
e1623446
TW
2329 IWL_DEBUG_INFO(priv,
2330 "Copying (but not loading) init data len %zd\n", len);
b481de9c
ZY
2331 memcpy(priv->ucode_init_data.v_addr, src, len);
2332 }
2333
2334 /* Bootstrap instructions (5th block) */
2335 src = &ucode->data[inst_size + data_size + init_size + init_data_size];
2336 len = priv->ucode_boot.len;
e1623446
TW
2337 IWL_DEBUG_INFO(priv,
2338 "Copying (but not loading) boot instr len %zd\n", len);
b481de9c
ZY
2339 memcpy(priv->ucode_boot.v_addr, src, len);
2340
2341 /* We have our copies now, allow OS release its copies */
2342 release_firmware(ucode_raw);
2343 return 0;
2344
2345 err_pci_alloc:
15b1687c 2346 IWL_ERR(priv, "failed to allocate pci memory\n");
90e759d1 2347 ret = -ENOMEM;
bb8c093b 2348 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY
2349
2350 err_release:
2351 release_firmware(ucode_raw);
2352
2353 error:
90e759d1 2354 return ret;
b481de9c
ZY
2355}
2356
2357
2358/**
bb8c093b 2359 * iwl3945_set_ucode_ptrs - Set uCode address location
b481de9c
ZY
2360 *
2361 * Tell initialization uCode where to find runtime uCode.
2362 *
2363 * BSM registers initially contain pointers to initialization uCode.
2364 * We need to replace them to load runtime uCode inst and data,
2365 * and to save runtime data when powering down.
2366 */
4a8a4322 2367static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv)
b481de9c
ZY
2368{
2369 dma_addr_t pinst;
2370 dma_addr_t pdata;
b481de9c
ZY
2371
2372 /* bits 31:0 for 3945 */
2373 pinst = priv->ucode_code.p_addr;
2374 pdata = priv->ucode_data_backup.p_addr;
2375
b481de9c 2376 /* Tell bootstrap uCode where to find image to load */
5d49f498
AK
2377 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2378 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2379 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
b481de9c
ZY
2380 priv->ucode_data.len);
2381
a96a27f9 2382 /* Inst byte count must be last to set up, bit 31 signals uCode
b481de9c 2383 * that all new ptr/size info is in place */
5d49f498 2384 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
b481de9c
ZY
2385 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
2386
e1623446 2387 IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n");
b481de9c 2388
a8b50a0a 2389 return 0;
b481de9c
ZY
2390}
2391
2392/**
bb8c093b 2393 * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
b481de9c
ZY
2394 *
2395 * Called after REPLY_ALIVE notification received from "initialize" uCode.
2396 *
b481de9c 2397 * Tell "initialize" uCode to go ahead and load the runtime uCode.
9fbab516 2398 */
4a8a4322 2399static void iwl3945_init_alive_start(struct iwl_priv *priv)
b481de9c
ZY
2400{
2401 /* Check alive response for "valid" sign from uCode */
2402 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
2403 /* We had an error bringing up the hardware, so take it
2404 * all the way back down so we can try again */
e1623446 2405 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
b481de9c
ZY
2406 goto restart;
2407 }
2408
2409 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
2410 * This is a paranoid check, because we would not have gotten the
2411 * "initialize" alive if code weren't properly loaded. */
bb8c093b 2412 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY
2413 /* Runtime instruction load was bad;
2414 * take it all the way back down so we can try again */
e1623446 2415 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
b481de9c
ZY
2416 goto restart;
2417 }
2418
2419 /* Send pointers to protocol/runtime uCode image ... init code will
2420 * load and launch runtime uCode, which will send us another "Alive"
2421 * notification. */
e1623446 2422 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
bb8c093b 2423 if (iwl3945_set_ucode_ptrs(priv)) {
b481de9c
ZY
2424 /* Runtime instruction load won't happen;
2425 * take it all the way back down so we can try again */
e1623446 2426 IWL_DEBUG_INFO(priv, "Couldn't set up uCode pointers.\n");
b481de9c
ZY
2427 goto restart;
2428 }
2429 return;
2430
2431 restart:
2432 queue_work(priv->workqueue, &priv->restart);
2433}
2434
b481de9c 2435/**
bb8c093b 2436 * iwl3945_alive_start - called after REPLY_ALIVE notification received
b481de9c 2437 * from protocol/runtime uCode (initialization uCode's
bb8c093b 2438 * Alive gets handled by iwl3945_init_alive_start()).
b481de9c 2439 */
4a8a4322 2440static void iwl3945_alive_start(struct iwl_priv *priv)
b481de9c 2441{
b481de9c
ZY
2442 int thermal_spin = 0;
2443 u32 rfkill;
2444
e1623446 2445 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY
2446
2447 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2448 /* We had an error bringing up the hardware, so take it
2449 * all the way back down so we can try again */
e1623446 2450 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY
2451 goto restart;
2452 }
2453
2454 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2455 * This is a paranoid check, because we would not have gotten the
2456 * "runtime" alive if code weren't properly loaded. */
bb8c093b 2457 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY
2458 /* Runtime instruction load was bad;
2459 * take it all the way back down so we can try again */
e1623446 2460 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY
2461 goto restart;
2462 }
2463
c587de0b 2464 iwl_clear_stations_table(priv);
b481de9c 2465
5d49f498 2466 rfkill = iwl_read_prph(priv, APMG_RFKILL_REG);
e1623446 2467 IWL_DEBUG_INFO(priv, "RFKILL status: 0x%x\n", rfkill);
b481de9c
ZY
2468
2469 if (rfkill & 0x1) {
2470 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a96a27f9 2471 /* if RFKILL is not on, then wait for thermal
b481de9c 2472 * sensor in adapter to kick in */
bb8c093b 2473 while (iwl3945_hw_get_temperature(priv) == 0) {
b481de9c
ZY
2474 thermal_spin++;
2475 udelay(10);
2476 }
2477
2478 if (thermal_spin)
e1623446 2479 IWL_DEBUG_INFO(priv, "Thermal calibration took %dus\n",
b481de9c
ZY
2480 thermal_spin * 10);
2481 } else
2482 set_bit(STATUS_RF_KILL_HW, &priv->status);
2483
9fbab516 2484 /* After the ALIVE response, we can send commands to 3945 uCode */
b481de9c
ZY
2485 set_bit(STATUS_ALIVE, &priv->status);
2486
775a6e27 2487 if (iwl_is_rfkill(priv))
b481de9c
ZY
2488 return;
2489
36d6825b 2490 ieee80211_wake_queues(priv->hw);
b481de9c
ZY
2491
2492 priv->active_rate = priv->rates_mask;
2493 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
2494
d25aabb0 2495 iwl_power_update_mode(priv, false);
b481de9c 2496
8ccde88a 2497 if (iwl_is_associated(priv)) {
bb8c093b 2498 struct iwl3945_rxon_cmd *active_rxon =
8ccde88a 2499 (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
b481de9c 2500
8ccde88a
SO
2501 memcpy(&priv->staging_rxon, &priv->active_rxon,
2502 sizeof(priv->staging_rxon));
b481de9c
ZY
2503 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2504 } else {
2505 /* Initialize our rx_config data */
8ccde88a 2506 iwl_connection_init_rx_config(priv, priv->iw_mode);
b481de9c
ZY
2507 }
2508
9fbab516 2509 /* Configure Bluetooth device coexistence support */
17f841cd 2510 iwl_send_bt_config(priv);
b481de9c
ZY
2511
2512 /* Configure the adapter for unassociated operation */
e0158e61 2513 iwlcore_commit_rxon(priv);
b481de9c 2514
b481de9c
ZY
2515 iwl3945_reg_txpower_periodic(priv);
2516
fe00b5a5
RC
2517 iwl3945_led_register(priv);
2518
e1623446 2519 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 2520 set_bit(STATUS_READY, &priv->status);
5a66926a 2521 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 2522
9bdf5eca
MA
2523 /* reassociate for ADHOC mode */
2524 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
2525 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
2526 priv->vif);
2527 if (beacon)
9944b938 2528 iwl_mac_beacon_update(priv->hw, beacon);
9bdf5eca
MA
2529 }
2530
f45c2714 2531 if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
727882d6 2532 iwl_set_mode(priv, priv->iw_mode);
f45c2714 2533
b481de9c
ZY
2534 return;
2535
2536 restart:
2537 queue_work(priv->workqueue, &priv->restart);
2538}
2539
4a8a4322 2540static void iwl3945_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 2541
4a8a4322 2542static void __iwl3945_down(struct iwl_priv *priv)
b481de9c
ZY
2543{
2544 unsigned long flags;
2545 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2546 struct ieee80211_conf *conf = NULL;
2547
e1623446 2548 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c
ZY
2549
2550 conf = ieee80211_get_hw_conf(priv->hw);
2551
2552 if (!exit_pending)
2553 set_bit(STATUS_EXIT_PENDING, &priv->status);
2554
ab53d8af 2555 iwl3945_led_unregister(priv);
c587de0b 2556 iwl_clear_stations_table(priv);
b481de9c
ZY
2557
2558 /* Unblock any waiting calls */
2559 wake_up_interruptible_all(&priv->wait_command_queue);
2560
b481de9c
ZY
2561 /* Wipe out the EXIT_PENDING status bit if we are not actually
2562 * exiting the module */
2563 if (!exit_pending)
2564 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2565
2566 /* stop and reset the on-board processor */
5d49f498 2567 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY
2568
2569 /* tell the device to stop sending interrupts */
0359facc 2570 spin_lock_irqsave(&priv->lock, flags);
ed3b932e 2571 iwl_disable_interrupts(priv);
0359facc
MA
2572 spin_unlock_irqrestore(&priv->lock, flags);
2573 iwl_synchronize_irq(priv);
b481de9c
ZY
2574
2575 if (priv->mac80211_registered)
2576 ieee80211_stop_queues(priv->hw);
2577
bb8c093b 2578 /* If we have not previously called iwl3945_init() then
6da3a13e 2579 * clear all bits but the RF Kill bits and return */
775a6e27 2580 if (!iwl_is_init(priv)) {
b481de9c
ZY
2581 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2582 STATUS_RF_KILL_HW |
9788864e
RC
2583 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2584 STATUS_GEO_CONFIGURED |
ebef2008
AK
2585 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2586 STATUS_EXIT_PENDING;
b481de9c
ZY
2587 goto exit;
2588 }
2589
6da3a13e 2590 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 2591 * bit and continue taking the NIC down. */
b481de9c
ZY
2592 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2593 STATUS_RF_KILL_HW |
9788864e
RC
2594 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2595 STATUS_GEO_CONFIGURED |
b481de9c 2596 test_bit(STATUS_FW_ERROR, &priv->status) <<
ebef2008
AK
2597 STATUS_FW_ERROR |
2598 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2599 STATUS_EXIT_PENDING;
b481de9c 2600
e9414b6b 2601 priv->cfg->ops->lib->apm_ops.reset(priv);
b481de9c 2602 spin_lock_irqsave(&priv->lock, flags);
5d49f498 2603 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY
2604 spin_unlock_irqrestore(&priv->lock, flags);
2605
bb8c093b
CH
2606 iwl3945_hw_txq_ctx_stop(priv);
2607 iwl3945_hw_rxq_stop(priv);
b481de9c 2608
a8b50a0a
MA
2609 iwl_write_prph(priv, APMG_CLK_DIS_REG,
2610 APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY
2611
2612 udelay(5);
2613
6da3a13e 2614 if (exit_pending)
e9414b6b
AM
2615 priv->cfg->ops->lib->apm_ops.stop(priv);
2616 else
2617 priv->cfg->ops->lib->apm_ops.reset(priv);
2618
b481de9c 2619 exit:
3d24a9f7 2620 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY
2621
2622 if (priv->ibss_beacon)
2623 dev_kfree_skb(priv->ibss_beacon);
2624 priv->ibss_beacon = NULL;
2625
2626 /* clear out any free frames */
bb8c093b 2627 iwl3945_clear_free_frames(priv);
b481de9c
ZY
2628}
2629
4a8a4322 2630static void iwl3945_down(struct iwl_priv *priv)
b481de9c
ZY
2631{
2632 mutex_lock(&priv->mutex);
bb8c093b 2633 __iwl3945_down(priv);
b481de9c 2634 mutex_unlock(&priv->mutex);
b24d22b1 2635
bb8c093b 2636 iwl3945_cancel_deferred_work(priv);
b481de9c
ZY
2637}
2638
2639#define MAX_HW_RESTARTS 5
2640
4a8a4322 2641static int __iwl3945_up(struct iwl_priv *priv)
b481de9c
ZY
2642{
2643 int rc, i;
2644
2645 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 2646 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY
2647 return -EIO;
2648 }
2649
e903fbd4 2650 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 2651 IWL_ERR(priv, "ucode not available for device bring up\n");
e903fbd4
RC
2652 return -EIO;
2653 }
2654
e655b9f0 2655 /* If platform's RF_KILL switch is NOT set to KILL */
5d49f498 2656 if (iwl_read32(priv, CSR_GP_CNTRL) &
e655b9f0
ZY
2657 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2658 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2659 else {
2660 set_bit(STATUS_RF_KILL_HW, &priv->status);
6da3a13e
WYG
2661 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2662 return -ENODEV;
b481de9c 2663 }
80fcc9e2 2664
5d49f498 2665 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 2666
bb8c093b 2667 rc = iwl3945_hw_nic_init(priv);
b481de9c 2668 if (rc) {
15b1687c 2669 IWL_ERR(priv, "Unable to int nic\n");
b481de9c
ZY
2670 return rc;
2671 }
2672
2673 /* make sure rfkill handshake bits are cleared */
5d49f498
AK
2674 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2675 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY
2676 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2677
2678 /* clear (again), then enable host interrupts */
5d49f498 2679 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
ed3b932e 2680 iwl_enable_interrupts(priv);
b481de9c
ZY
2681
2682 /* really make sure rfkill handshake bits are cleared */
5d49f498
AK
2683 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2684 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
2685
2686 /* Copy original ucode data image from disk into backup cache.
2687 * This will be used to initialize the on-board processor's
2688 * data SRAM for a clean start when the runtime program first loads. */
2689 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 2690 priv->ucode_data.len);
b481de9c 2691
e655b9f0
ZY
2692 /* We return success when we resume from suspend and rf_kill is on. */
2693 if (test_bit(STATUS_RF_KILL_HW, &priv->status))
2694 return 0;
2695
b481de9c
ZY
2696 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2697
c587de0b 2698 iwl_clear_stations_table(priv);
b481de9c
ZY
2699
2700 /* load bootstrap state machine,
2701 * load bootstrap program into processor's memory,
2702 * prepare to load the "initialize" uCode */
0164b9b4 2703 priv->cfg->ops->lib->load_ucode(priv);
b481de9c
ZY
2704
2705 if (rc) {
15b1687c
WT
2706 IWL_ERR(priv,
2707 "Unable to set up bootstrap uCode: %d\n", rc);
b481de9c
ZY
2708 continue;
2709 }
2710
2711 /* start card; "initialize" will load runtime ucode */
bb8c093b 2712 iwl3945_nic_start(priv);
b481de9c 2713
e1623446 2714 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY
2715
2716 return 0;
2717 }
2718
2719 set_bit(STATUS_EXIT_PENDING, &priv->status);
bb8c093b 2720 __iwl3945_down(priv);
ebef2008 2721 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY
2722
2723 /* tried to restart and config the device for as long as our
2724 * patience could withstand */
15b1687c 2725 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY
2726 return -EIO;
2727}
2728
2729
2730/*****************************************************************************
2731 *
2732 * Workqueue callbacks
2733 *
2734 *****************************************************************************/
2735
bb8c093b 2736static void iwl3945_bg_init_alive_start(struct work_struct *data)
b481de9c 2737{
4a8a4322
AK
2738 struct iwl_priv *priv =
2739 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY
2740
2741 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2742 return;
2743
2744 mutex_lock(&priv->mutex);
bb8c093b 2745 iwl3945_init_alive_start(priv);
b481de9c
ZY
2746 mutex_unlock(&priv->mutex);
2747}
2748
bb8c093b 2749static void iwl3945_bg_alive_start(struct work_struct *data)
b481de9c 2750{
4a8a4322
AK
2751 struct iwl_priv *priv =
2752 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY
2753
2754 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2755 return;
2756
2757 mutex_lock(&priv->mutex);
bb8c093b 2758 iwl3945_alive_start(priv);
b481de9c
ZY
2759 mutex_unlock(&priv->mutex);
2760}
2761
2663516d
HS
2762static void iwl3945_rfkill_poll(struct work_struct *data)
2763{
2764 struct iwl_priv *priv =
2765 container_of(data, struct iwl_priv, rfkill_poll.work);
2663516d
HS
2766
2767 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2768 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2769 else
2770 set_bit(STATUS_RF_KILL_HW, &priv->status);
2771
a60e77e5
JB
2772 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
2773 test_bit(STATUS_RF_KILL_HW, &priv->status));
2663516d
HS
2774
2775 queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
2776 round_jiffies_relative(2 * HZ));
2777
2778}
2779
b481de9c 2780#define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
bb8c093b 2781static void iwl3945_bg_request_scan(struct work_struct *data)
b481de9c 2782{
4a8a4322
AK
2783 struct iwl_priv *priv =
2784 container_of(data, struct iwl_priv, request_scan);
c2d79b48 2785 struct iwl_host_cmd cmd = {
b481de9c 2786 .id = REPLY_SCAN_CMD,
bb8c093b 2787 .len = sizeof(struct iwl3945_scan_cmd),
b481de9c
ZY
2788 .meta.flags = CMD_SIZE_HUGE,
2789 };
2790 int rc = 0;
bb8c093b 2791 struct iwl3945_scan_cmd *scan;
b481de9c 2792 struct ieee80211_conf *conf = NULL;
1ecf9fc1 2793 u8 n_probes = 0;
8318d78a 2794 enum ieee80211_band band;
1ecf9fc1 2795 bool is_active = false;
b481de9c
ZY
2796
2797 conf = ieee80211_get_hw_conf(priv->hw);
2798
2799 mutex_lock(&priv->mutex);
2800
fbc9f97b
RC
2801 cancel_delayed_work(&priv->scan_check);
2802
775a6e27 2803 if (!iwl_is_ready(priv)) {
39aadf8c 2804 IWL_WARN(priv, "request scan called when driver not ready.\n");
b481de9c
ZY
2805 goto done;
2806 }
2807
a96a27f9 2808 /* Make sure the scan wasn't canceled before this queued work
b481de9c
ZY
2809 * was given the chance to run... */
2810 if (!test_bit(STATUS_SCANNING, &priv->status))
2811 goto done;
2812
2813 /* This should never be called or scheduled if there is currently
2814 * a scan active in the hardware. */
2815 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
e1623446
TW
2816 IWL_DEBUG_INFO(priv, "Multiple concurrent scan requests "
2817 "Ignoring second request.\n");
b481de9c
ZY
2818 rc = -EIO;
2819 goto done;
2820 }
2821
2822 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
e1623446 2823 IWL_DEBUG_SCAN(priv, "Aborting scan due to device shutdown\n");
b481de9c
ZY
2824 goto done;
2825 }
2826
2827 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
e1623446
TW
2828 IWL_DEBUG_HC(priv,
2829 "Scan request while abort pending. Queuing.\n");
b481de9c
ZY
2830 goto done;
2831 }
2832
775a6e27 2833 if (iwl_is_rfkill(priv)) {
e1623446 2834 IWL_DEBUG_HC(priv, "Aborting scan due to RF Kill activation\n");
b481de9c
ZY
2835 goto done;
2836 }
2837
2838 if (!test_bit(STATUS_READY, &priv->status)) {
e1623446
TW
2839 IWL_DEBUG_HC(priv,
2840 "Scan request while uninitialized. Queuing.\n");
b481de9c
ZY
2841 goto done;
2842 }
2843
2844 if (!priv->scan_bands) {
e1623446 2845 IWL_DEBUG_HC(priv, "Aborting scan due to no requested bands\n");
b481de9c
ZY
2846 goto done;
2847 }
2848
805cee5b
WT
2849 if (!priv->scan) {
2850 priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
b481de9c 2851 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
805cee5b 2852 if (!priv->scan) {
b481de9c
ZY
2853 rc = -ENOMEM;
2854 goto done;
2855 }
2856 }
805cee5b 2857 scan = priv->scan;
bb8c093b 2858 memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
b481de9c
ZY
2859
2860 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
2861 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
2862
8ccde88a 2863 if (iwl_is_associated(priv)) {
b481de9c
ZY
2864 u16 interval = 0;
2865 u32 extra;
2866 u32 suspend_time = 100;
2867 u32 scan_suspend_time = 100;
2868 unsigned long flags;
2869
e1623446 2870 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
b481de9c
ZY
2871
2872 spin_lock_irqsave(&priv->lock, flags);
2873 interval = priv->beacon_int;
2874 spin_unlock_irqrestore(&priv->lock, flags);
2875
2876 scan->suspend_time = 0;
15e869d8 2877 scan->max_out_time = cpu_to_le32(200 * 1024);
b481de9c
ZY
2878 if (!interval)
2879 interval = suspend_time;
2880 /*
2881 * suspend time format:
2882 * 0-19: beacon interval in usec (time before exec.)
2883 * 20-23: 0
2884 * 24-31: number of beacons (suspend between channels)
2885 */
2886
2887 extra = (suspend_time / interval) << 24;
2888 scan_suspend_time = 0xFF0FFFFF &
2889 (extra | ((suspend_time % interval) * 1024));
2890
2891 scan->suspend_time = cpu_to_le32(scan_suspend_time);
e1623446 2892 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
b481de9c
ZY
2893 scan_suspend_time, interval);
2894 }
2895
1ecf9fc1
JB
2896 if (priv->scan_request->n_ssids) {
2897 int i, p = 0;
2898 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
2899 for (i = 0; i < priv->scan_request->n_ssids; i++) {
2900 /* always does wildcard anyway */
2901 if (!priv->scan_request->ssids[i].ssid_len)
2902 continue;
2903 scan->direct_scan[p].id = WLAN_EID_SSID;
2904 scan->direct_scan[p].len =
2905 priv->scan_request->ssids[i].ssid_len;
2906 memcpy(scan->direct_scan[p].ssid,
2907 priv->scan_request->ssids[i].ssid,
2908 priv->scan_request->ssids[i].ssid_len);
2909 n_probes++;
2910 p++;
2911 }
2912 is_active = true;
f9340520 2913 } else
1ecf9fc1 2914 IWL_DEBUG_SCAN(priv, "Kicking off passive scan.\n");
b481de9c
ZY
2915
2916 /* We don't build a direct scan probe request; the uCode will do
2917 * that based on the direct_mask added to each channel entry */
b481de9c 2918 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
3832ec9d 2919 scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY
2920 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2921
2922 /* flags + rate selection */
2923
66b5004d 2924 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
b481de9c
ZY
2925 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
2926 scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
2927 scan->good_CRC_th = 0;
8318d78a 2928 band = IEEE80211_BAND_2GHZ;
66b5004d 2929 } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
b481de9c 2930 scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
b097ad29
JB
2931 /*
2932 * If active scaning is requested but a certain channel
2933 * is marked passive, we can do active scanning if we
2934 * detect transmissions.
2935 */
2936 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH : 0;
8318d78a 2937 band = IEEE80211_BAND_5GHZ;
66b5004d 2938 } else {
39aadf8c 2939 IWL_WARN(priv, "Invalid scan band count\n");
b481de9c
ZY
2940 goto done;
2941 }
2942
77fecfb8 2943 scan->tx_cmd.len = cpu_to_le16(
1ecf9fc1
JB
2944 iwl_fill_probe_req(priv,
2945 (struct ieee80211_mgmt *)scan->data,
2946 priv->scan_request->ie,
2947 priv->scan_request->ie_len,
2948 IWL_MAX_SCAN_SIZE - sizeof(*scan)));
77fecfb8 2949
b481de9c
ZY
2950 /* select Rx antennas */
2951 scan->flags |= iwl3945_get_antenna_flags(priv);
2952
279b05d4 2953 if (iwl_is_monitor_mode(priv))
b481de9c
ZY
2954 scan->filter_flags = RXON_FILTER_PROMISC_MSK;
2955
f9340520 2956 scan->channel_count =
1ecf9fc1 2957 iwl3945_get_channels_for_scan(priv, band, is_active, n_probes,
f9340520 2958 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
b481de9c 2959
14b54336 2960 if (scan->channel_count == 0) {
e1623446 2961 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
14b54336
RC
2962 goto done;
2963 }
2964
b481de9c 2965 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
bb8c093b 2966 scan->channel_count * sizeof(struct iwl3945_scan_channel);
b481de9c
ZY
2967 cmd.data = scan;
2968 scan->len = cpu_to_le16(cmd.len);
2969
2970 set_bit(STATUS_SCAN_HW, &priv->status);
518099a8 2971 rc = iwl_send_cmd_sync(priv, &cmd);
b481de9c
ZY
2972 if (rc)
2973 goto done;
2974
2975 queue_delayed_work(priv->workqueue, &priv->scan_check,
2976 IWL_SCAN_CHECK_WATCHDOG);
2977
2978 mutex_unlock(&priv->mutex);
2979 return;
2980
2981 done:
2420ebc1
MA
2982 /* can not perform scan make sure we clear scanning
2983 * bits from status so next scan request can be performed.
2984 * if we dont clear scanning status bit here all next scan
2985 * will fail
2986 */
2987 clear_bit(STATUS_SCAN_HW, &priv->status);
2988 clear_bit(STATUS_SCANNING, &priv->status);
2989
01ebd063 2990 /* inform mac80211 scan aborted */
b481de9c
ZY
2991 queue_work(priv->workqueue, &priv->scan_completed);
2992 mutex_unlock(&priv->mutex);
2993}
2994
bb8c093b 2995static void iwl3945_bg_up(struct work_struct *data)
b481de9c 2996{
4a8a4322 2997 struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
b481de9c
ZY
2998
2999 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3000 return;
3001
3002 mutex_lock(&priv->mutex);
bb8c093b 3003 __iwl3945_up(priv);
b481de9c
ZY
3004 mutex_unlock(&priv->mutex);
3005}
3006
bb8c093b 3007static void iwl3945_bg_restart(struct work_struct *data)
b481de9c 3008{
4a8a4322 3009 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY
3010
3011 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3012 return;
3013
19cc1087
JB
3014 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
3015 mutex_lock(&priv->mutex);
3016 priv->vif = NULL;
3017 priv->is_open = 0;
3018 mutex_unlock(&priv->mutex);
3019 iwl3945_down(priv);
3020 ieee80211_restart_hw(priv->hw);
3021 } else {
3022 iwl3945_down(priv);
3023 queue_work(priv->workqueue, &priv->up);
3024 }
b481de9c
ZY
3025}
3026
bb8c093b 3027static void iwl3945_bg_rx_replenish(struct work_struct *data)
b481de9c 3028{
4a8a4322
AK
3029 struct iwl_priv *priv =
3030 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY
3031
3032 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3033 return;
3034
3035 mutex_lock(&priv->mutex);
bb8c093b 3036 iwl3945_rx_replenish(priv);
b481de9c
ZY
3037 mutex_unlock(&priv->mutex);
3038}
3039
7878a5a4
MA
3040#define IWL_DELAY_NEXT_SCAN (HZ*2)
3041
5bbe233b 3042void iwl3945_post_associate(struct iwl_priv *priv)
b481de9c 3043{
b481de9c
ZY
3044 int rc = 0;
3045 struct ieee80211_conf *conf = NULL;
3046
05c914fe 3047 if (priv->iw_mode == NL80211_IFTYPE_AP) {
15b1687c 3048 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY
3049 return;
3050 }
3051
3052
e1623446 3053 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
8ccde88a 3054 priv->assoc_id, priv->active_rxon.bssid_addr);
b481de9c
ZY
3055
3056 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3057 return;
3058
322a9811 3059 if (!priv->vif || !priv->is_open)
6ef89d0a 3060 return;
322a9811 3061
af0053d6 3062 iwl_scan_cancel_timeout(priv, 200);
15e869d8 3063
b481de9c
ZY
3064 conf = ieee80211_get_hw_conf(priv->hw);
3065
8ccde88a 3066 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 3067 iwlcore_commit_rxon(priv);
b481de9c 3068
28afaf91 3069 memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
bb8c093b 3070 iwl3945_setup_rxon_timing(priv);
518099a8 3071 rc = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY
3072 sizeof(priv->rxon_timing), &priv->rxon_timing);
3073 if (rc)
39aadf8c 3074 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
3075 "Attempting to continue.\n");
3076
8ccde88a 3077 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c 3078
8ccde88a 3079 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
b481de9c 3080
e1623446 3081 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
b481de9c
ZY
3082 priv->assoc_id, priv->beacon_int);
3083
3084 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
8ccde88a 3085 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 3086 else
8ccde88a 3087 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 3088
8ccde88a 3089 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
b481de9c 3090 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
8ccde88a 3091 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
b481de9c 3092 else
8ccde88a 3093 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c 3094
05c914fe 3095 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
8ccde88a 3096 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c
ZY
3097
3098 }
3099
e0158e61 3100 iwlcore_commit_rxon(priv);
b481de9c
ZY
3101
3102 switch (priv->iw_mode) {
05c914fe 3103 case NL80211_IFTYPE_STATION:
bb8c093b 3104 iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
b481de9c
ZY
3105 break;
3106
05c914fe 3107 case NL80211_IFTYPE_ADHOC:
b481de9c 3108
ce546fd2 3109 priv->assoc_id = 1;
c587de0b 3110 iwl_add_station(priv, priv->bssid, 0, CMD_SYNC, NULL);
b481de9c 3111 iwl3945_sync_sta(priv, IWL_STA_ID,
8318d78a 3112 (priv->band == IEEE80211_BAND_5GHZ) ?
b481de9c
ZY
3113 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
3114 CMD_ASYNC);
bb8c093b
CH
3115 iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
3116 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
3117
3118 break;
3119
3120 default:
15b1687c 3121 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3ac7f146 3122 __func__, priv->iw_mode);
b481de9c
ZY
3123 break;
3124 }
3125
14d2aac5 3126 iwl_activate_qos(priv, 0);
292ae174 3127
7878a5a4
MA
3128 /* we have just associated, don't start scan too early */
3129 priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
cd56d331
AK
3130}
3131
b481de9c
ZY
3132/*****************************************************************************
3133 *
3134 * mac80211 entry point functions
3135 *
3136 *****************************************************************************/
3137
5a66926a
ZY
3138#define UCODE_READY_TIMEOUT (2 * HZ)
3139
bb8c093b 3140static int iwl3945_mac_start(struct ieee80211_hw *hw)
b481de9c 3141{
4a8a4322 3142 struct iwl_priv *priv = hw->priv;
5a66926a 3143 int ret;
b481de9c 3144
e1623446 3145 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY
3146
3147 /* we should be verifying the device is ready to be opened */
3148 mutex_lock(&priv->mutex);
3149
8ccde88a 3150 memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
5a66926a
ZY
3151 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
3152 * ucode filename and max sizes are card-specific. */
3153
3154 if (!priv->ucode_code.len) {
3155 ret = iwl3945_read_ucode(priv);
3156 if (ret) {
15b1687c 3157 IWL_ERR(priv, "Could not read microcode: %d\n", ret);
5a66926a
ZY
3158 mutex_unlock(&priv->mutex);
3159 goto out_release_irq;
3160 }
3161 }
b481de9c 3162
e655b9f0 3163 ret = __iwl3945_up(priv);
b481de9c
ZY
3164
3165 mutex_unlock(&priv->mutex);
5a66926a 3166
e655b9f0
ZY
3167 if (ret)
3168 goto out_release_irq;
3169
e1623446 3170 IWL_DEBUG_INFO(priv, "Start UP work.\n");
e655b9f0 3171
5a66926a
ZY
3172 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
3173 * mac80211 will not be run successfully. */
3174 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3175 test_bit(STATUS_READY, &priv->status),
3176 UCODE_READY_TIMEOUT);
3177 if (!ret) {
3178 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c
WT
3179 IWL_ERR(priv,
3180 "Wait for START_ALIVE timeout after %dms.\n",
3181 jiffies_to_msecs(UCODE_READY_TIMEOUT));
5a66926a
ZY
3182 ret = -ETIMEDOUT;
3183 goto out_release_irq;
3184 }
3185 }
3186
2663516d
HS
3187 /* ucode is running and will send rfkill notifications,
3188 * no need to poll the killswitch state anymore */
3189 cancel_delayed_work(&priv->rfkill_poll);
3190
e655b9f0 3191 priv->is_open = 1;
e1623446 3192 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 3193 return 0;
5a66926a
ZY
3194
3195out_release_irq:
e655b9f0 3196 priv->is_open = 0;
e1623446 3197 IWL_DEBUG_MAC80211(priv, "leave - failed\n");
5a66926a 3198 return ret;
b481de9c
ZY
3199}
3200
bb8c093b 3201static void iwl3945_mac_stop(struct ieee80211_hw *hw)
b481de9c 3202{
4a8a4322 3203 struct iwl_priv *priv = hw->priv;
b481de9c 3204
e1623446 3205 IWL_DEBUG_MAC80211(priv, "enter\n");
6ef89d0a 3206
e655b9f0 3207 if (!priv->is_open) {
e1623446 3208 IWL_DEBUG_MAC80211(priv, "leave - skip\n");
e655b9f0
ZY
3209 return;
3210 }
3211
b481de9c 3212 priv->is_open = 0;
5a66926a 3213
775a6e27 3214 if (iwl_is_ready_rf(priv)) {
e655b9f0
ZY
3215 /* stop mac, cancel any scan request and clear
3216 * RXON_FILTER_ASSOC_MSK BIT
3217 */
5a66926a 3218 mutex_lock(&priv->mutex);
af0053d6 3219 iwl_scan_cancel_timeout(priv, 100);
fde3571f 3220 mutex_unlock(&priv->mutex);
fde3571f
MA
3221 }
3222
5a66926a
ZY
3223 iwl3945_down(priv);
3224
3225 flush_workqueue(priv->workqueue);
2663516d
HS
3226
3227 /* start polling the killswitch state again */
3228 queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
3229 round_jiffies_relative(2 * HZ));
6ef89d0a 3230
e1623446 3231 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
3232}
3233
e039fa4a 3234static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 3235{
4a8a4322 3236 struct iwl_priv *priv = hw->priv;
b481de9c 3237
e1623446 3238 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3239
e1623446 3240 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 3241 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 3242
e039fa4a 3243 if (iwl3945_tx_skb(priv, skb))
b481de9c
ZY
3244 dev_kfree_skb_any(skb);
3245
e1623446 3246 IWL_DEBUG_MAC80211(priv, "leave\n");
637f8837 3247 return NETDEV_TX_OK;
b481de9c
ZY
3248}
3249
60690a6a 3250void iwl3945_config_ap(struct iwl_priv *priv)
b481de9c
ZY
3251{
3252 int rc = 0;
3253
d986bcd1 3254 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY
3255 return;
3256
3257 /* The following should be done only at AP bring up */
8ccde88a 3258 if (!(iwl_is_associated(priv))) {
b481de9c
ZY
3259
3260 /* RXON - unassoc (to set timing command) */
8ccde88a 3261 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 3262 iwlcore_commit_rxon(priv);
b481de9c
ZY
3263
3264 /* RXON Timing */
28afaf91 3265 memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
bb8c093b 3266 iwl3945_setup_rxon_timing(priv);
518099a8
SO
3267 rc = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
3268 sizeof(priv->rxon_timing),
3269 &priv->rxon_timing);
b481de9c 3270 if (rc)
39aadf8c 3271 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
3272 "Attempting to continue.\n");
3273
3274 /* FIXME: what should be the assoc_id for AP? */
8ccde88a 3275 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
b481de9c 3276 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
8ccde88a 3277 priv->staging_rxon.flags |=
b481de9c
ZY
3278 RXON_FLG_SHORT_PREAMBLE_MSK;
3279 else
8ccde88a 3280 priv->staging_rxon.flags &=
b481de9c
ZY
3281 ~RXON_FLG_SHORT_PREAMBLE_MSK;
3282
8ccde88a 3283 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
b481de9c
ZY
3284 if (priv->assoc_capability &
3285 WLAN_CAPABILITY_SHORT_SLOT_TIME)
8ccde88a 3286 priv->staging_rxon.flags |=
b481de9c
ZY
3287 RXON_FLG_SHORT_SLOT_MSK;
3288 else
8ccde88a 3289 priv->staging_rxon.flags &=
b481de9c
ZY
3290 ~RXON_FLG_SHORT_SLOT_MSK;
3291
05c914fe 3292 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
8ccde88a 3293 priv->staging_rxon.flags &=
b481de9c
ZY
3294 ~RXON_FLG_SHORT_SLOT_MSK;
3295 }
3296 /* restore RXON assoc */
8ccde88a 3297 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
e0158e61 3298 iwlcore_commit_rxon(priv);
c587de0b 3299 iwl_add_station(priv, iwl_bcast_addr, 0, CMD_SYNC, NULL);
556f8db7 3300 }
bb8c093b 3301 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
3302
3303 /* FIXME - we need to add code here to detect a totally new
3304 * configuration, reset the AP, unassoc, rxon timing, assoc,
3305 * clear sta table, add BCAST sta... */
3306}
3307
bb8c093b 3308static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB
3309 struct ieee80211_vif *vif,
3310 struct ieee80211_sta *sta,
3311 struct ieee80211_key_conf *key)
b481de9c 3312{
4a8a4322 3313 struct iwl_priv *priv = hw->priv;
dc822b5d 3314 const u8 *addr;
6e21f15c
AK
3315 int ret = 0;
3316 u8 sta_id = IWL_INVALID_STATION;
3317 u8 static_key;
b481de9c 3318
e1623446 3319 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3320
df878d8f 3321 if (iwl3945_mod_params.sw_crypto) {
e1623446 3322 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY
3323 return -EOPNOTSUPP;
3324 }
3325
42986796 3326 addr = sta ? sta->addr : iwl_bcast_addr;
6e21f15c
AK
3327 static_key = !iwl_is_associated(priv);
3328
3329 if (!static_key) {
c587de0b 3330 sta_id = iwl_find_station(priv, addr);
6e21f15c 3331 if (sta_id == IWL_INVALID_STATION) {
12514396 3332 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
6e21f15c
AK
3333 addr);
3334 return -EINVAL;
3335 }
b481de9c
ZY
3336 }
3337
3338 mutex_lock(&priv->mutex);
af0053d6 3339 iwl_scan_cancel_timeout(priv, 100);
6e21f15c 3340 mutex_unlock(&priv->mutex);
15e869d8 3341
b481de9c 3342 switch (cmd) {
6e21f15c
AK
3343 case SET_KEY:
3344 if (static_key)
3345 ret = iwl3945_set_static_key(priv, key);
3346 else
3347 ret = iwl3945_set_dynamic_key(priv, key, sta_id);
3348 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY
3349 break;
3350 case DISABLE_KEY:
6e21f15c
AK
3351 if (static_key)
3352 ret = iwl3945_remove_static_key(priv);
3353 else
3354 ret = iwl3945_clear_sta_key_info(priv, sta_id);
3355 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY
3356 break;
3357 default:
42986796 3358 ret = -EINVAL;
b481de9c
ZY
3359 }
3360
e1623446 3361 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 3362
42986796 3363 return ret;
b481de9c
ZY
3364}
3365
b481de9c
ZY
3366/*****************************************************************************
3367 *
3368 * sysfs attributes
3369 *
3370 *****************************************************************************/
3371
d08853a3 3372#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
3373
3374/*
3375 * The following adds a new attribute to the sysfs representation
3376 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
3377 * used for controlling the debug level.
3378 *
3379 * See the level definitions in iwl for details.
3380 */
40b8ec0b
SO
3381static ssize_t show_debug_level(struct device *d,
3382 struct device_attribute *attr, char *buf)
b481de9c 3383{
928841b1 3384 struct iwl_priv *priv = dev_get_drvdata(d);
40b8ec0b
SO
3385
3386 return sprintf(buf, "0x%08X\n", priv->debug_level);
b481de9c 3387}
40b8ec0b
SO
3388static ssize_t store_debug_level(struct device *d,
3389 struct device_attribute *attr,
b481de9c
ZY
3390 const char *buf, size_t count)
3391{
928841b1 3392 struct iwl_priv *priv = dev_get_drvdata(d);
40b8ec0b
SO
3393 unsigned long val;
3394 int ret;
b481de9c 3395
40b8ec0b
SO
3396 ret = strict_strtoul(buf, 0, &val);
3397 if (ret)
978785a3 3398 IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf);
b481de9c 3399 else
40b8ec0b 3400 priv->debug_level = val;
b481de9c
ZY
3401
3402 return strnlen(buf, count);
3403}
3404
40b8ec0b
SO
3405static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
3406 show_debug_level, store_debug_level);
b481de9c 3407
d08853a3 3408#endif /* CONFIG_IWLWIFI_DEBUG */
b481de9c 3409
b481de9c
ZY
3410static ssize_t show_temperature(struct device *d,
3411 struct device_attribute *attr, char *buf)
3412{
928841b1 3413 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3414
775a6e27 3415 if (!iwl_is_alive(priv))
b481de9c
ZY
3416 return -EAGAIN;
3417
bb8c093b 3418 return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
b481de9c
ZY
3419}
3420
3421static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
3422
b481de9c
ZY
3423static ssize_t show_tx_power(struct device *d,
3424 struct device_attribute *attr, char *buf)
3425{
928841b1 3426 struct iwl_priv *priv = dev_get_drvdata(d);
62ea9c5b 3427 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
b481de9c
ZY
3428}
3429
3430static ssize_t store_tx_power(struct device *d,
3431 struct device_attribute *attr,
3432 const char *buf, size_t count)
3433{
928841b1 3434 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3435 char *p = (char *)buf;
3436 u32 val;
3437
3438 val = simple_strtoul(p, &p, 10);
3439 if (p == buf)
978785a3 3440 IWL_INFO(priv, ": %s is not in decimal form.\n", buf);
b481de9c 3441 else
bb8c093b 3442 iwl3945_hw_reg_set_txpower(priv, val);
b481de9c
ZY
3443
3444 return count;
3445}
3446
3447static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
3448
3449static ssize_t show_flags(struct device *d,
3450 struct device_attribute *attr, char *buf)
3451{
928841b1 3452 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3453
8ccde88a 3454 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
b481de9c
ZY
3455}
3456
3457static ssize_t store_flags(struct device *d,
3458 struct device_attribute *attr,
3459 const char *buf, size_t count)
3460{
928841b1 3461 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3462 u32 flags = simple_strtoul(buf, NULL, 0);
3463
3464 mutex_lock(&priv->mutex);
8ccde88a 3465 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
b481de9c 3466 /* Cancel any currently running scans... */
af0053d6 3467 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 3468 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 3469 else {
e1623446 3470 IWL_DEBUG_INFO(priv, "Committing rxon.flags = 0x%04X\n",
b481de9c 3471 flags);
8ccde88a 3472 priv->staging_rxon.flags = cpu_to_le32(flags);
e0158e61 3473 iwlcore_commit_rxon(priv);
b481de9c
ZY
3474 }
3475 }
3476 mutex_unlock(&priv->mutex);
3477
3478 return count;
3479}
3480
3481static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
3482
3483static ssize_t show_filter_flags(struct device *d,
3484 struct device_attribute *attr, char *buf)
3485{
928841b1 3486 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3487
3488 return sprintf(buf, "0x%04X\n",
8ccde88a 3489 le32_to_cpu(priv->active_rxon.filter_flags));
b481de9c
ZY
3490}
3491
3492static ssize_t store_filter_flags(struct device *d,
3493 struct device_attribute *attr,
3494 const char *buf, size_t count)
3495{
928841b1 3496 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3497 u32 filter_flags = simple_strtoul(buf, NULL, 0);
3498
3499 mutex_lock(&priv->mutex);
8ccde88a 3500 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
b481de9c 3501 /* Cancel any currently running scans... */
af0053d6 3502 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 3503 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 3504 else {
e1623446 3505 IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
b481de9c 3506 "0x%04X\n", filter_flags);
8ccde88a 3507 priv->staging_rxon.filter_flags =
b481de9c 3508 cpu_to_le32(filter_flags);
e0158e61 3509 iwlcore_commit_rxon(priv);
b481de9c
ZY
3510 }
3511 }
3512 mutex_unlock(&priv->mutex);
3513
3514 return count;
3515}
3516
3517static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
3518 store_filter_flags);
3519
c8b0e6e1 3520#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY
3521
3522static ssize_t show_measurement(struct device *d,
3523 struct device_attribute *attr, char *buf)
3524{
4a8a4322 3525 struct iwl_priv *priv = dev_get_drvdata(d);
600c0e11 3526 struct iwl_spectrum_notification measure_report;
b481de9c 3527 u32 size = sizeof(measure_report), len = 0, ofs = 0;
3ac7f146 3528 u8 *data = (u8 *)&measure_report;
b481de9c
ZY
3529 unsigned long flags;
3530
3531 spin_lock_irqsave(&priv->lock, flags);
3532 if (!(priv->measurement_status & MEASUREMENT_READY)) {
3533 spin_unlock_irqrestore(&priv->lock, flags);
3534 return 0;
3535 }
3536 memcpy(&measure_report, &priv->measure_report, size);
3537 priv->measurement_status = 0;
3538 spin_unlock_irqrestore(&priv->lock, flags);
3539
3540 while (size && (PAGE_SIZE - len)) {
3541 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3542 PAGE_SIZE - len, 1);
3543 len = strlen(buf);
3544 if (PAGE_SIZE - len)
3545 buf[len++] = '\n';
3546
3547 ofs += 16;
3548 size -= min(size, 16U);
3549 }
3550
3551 return len;
3552}
3553
3554static ssize_t store_measurement(struct device *d,
3555 struct device_attribute *attr,
3556 const char *buf, size_t count)
3557{
4a8a4322 3558 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3559 struct ieee80211_measurement_params params = {
8ccde88a 3560 .channel = le16_to_cpu(priv->active_rxon.channel),
b481de9c
ZY
3561 .start_time = cpu_to_le64(priv->last_tsf),
3562 .duration = cpu_to_le16(1),
3563 };
3564 u8 type = IWL_MEASURE_BASIC;
3565 u8 buffer[32];
3566 u8 channel;
3567
3568 if (count) {
3569 char *p = buffer;
3570 strncpy(buffer, buf, min(sizeof(buffer), count));
3571 channel = simple_strtoul(p, NULL, 0);
3572 if (channel)
3573 params.channel = channel;
3574
3575 p = buffer;
3576 while (*p && *p != ' ')
3577 p++;
3578 if (*p)
3579 type = simple_strtoul(p + 1, NULL, 0);
3580 }
3581
e1623446 3582 IWL_DEBUG_INFO(priv, "Invoking measurement of type %d on "
b481de9c 3583 "channel %d (for '%s')\n", type, params.channel, buf);
bb8c093b 3584 iwl3945_get_measurement(priv, &params, type);
b481de9c
ZY
3585
3586 return count;
3587}
3588
3589static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
3590 show_measurement, store_measurement);
c8b0e6e1 3591#endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
b481de9c 3592
b481de9c
ZY
3593static ssize_t store_retry_rate(struct device *d,
3594 struct device_attribute *attr,
3595 const char *buf, size_t count)
3596{
4a8a4322 3597 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3598
3599 priv->retry_rate = simple_strtoul(buf, NULL, 0);
3600 if (priv->retry_rate <= 0)
3601 priv->retry_rate = 1;
3602
3603 return count;
3604}
3605
3606static ssize_t show_retry_rate(struct device *d,
3607 struct device_attribute *attr, char *buf)
3608{
4a8a4322 3609 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3610 return sprintf(buf, "%d", priv->retry_rate);
3611}
3612
3613static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
3614 store_retry_rate);
3615
d25aabb0 3616
b481de9c
ZY
3617static ssize_t store_power_level(struct device *d,
3618 struct device_attribute *attr,
3619 const char *buf, size_t count)
3620{
4a8a4322 3621 struct iwl_priv *priv = dev_get_drvdata(d);
d25aabb0
WT
3622 int ret;
3623 unsigned long mode;
3624
b481de9c 3625
b481de9c
ZY
3626 mutex_lock(&priv->mutex);
3627
d25aabb0
WT
3628 ret = strict_strtoul(buf, 10, &mode);
3629 if (ret)
3630 goto out;
b481de9c 3631
d25aabb0
WT
3632 ret = iwl_power_set_user_mode(priv, mode);
3633 if (ret) {
3634 IWL_DEBUG_MAC80211(priv, "failed setting power mode.\n");
3635 goto out;
b481de9c 3636 }
d25aabb0 3637 ret = count;
b481de9c
ZY
3638
3639 out:
3640 mutex_unlock(&priv->mutex);
d25aabb0 3641 return ret;
b481de9c
ZY
3642}
3643
d25aabb0
WT
3644static ssize_t show_power_level(struct device *d,
3645 struct device_attribute *attr, char *buf)
3646{
3647 struct iwl_priv *priv = dev_get_drvdata(d);
3648 int mode = priv->power_data.user_power_setting;
d25aabb0
WT
3649 int level = priv->power_data.power_mode;
3650 char *p = buf;
3651
7af2c460
JB
3652 p += sprintf(p, "INDEX:%d\t", level);
3653 p += sprintf(p, "USER:%d\n", mode);
d25aabb0
WT
3654 return p - buf + 1;
3655}
3656
3657static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR,
3658 show_power_level, store_power_level);
3659
b481de9c
ZY
3660#define MAX_WX_STRING 80
3661
3662/* Values are in microsecond */
3663static const s32 timeout_duration[] = {
3664 350000,
3665 250000,
3666 75000,
3667 37000,
3668 25000,
3669};
3670static const s32 period_duration[] = {
3671 400000,
3672 700000,
3673 1000000,
3674 1000000,
3675 1000000
3676};
3677
b481de9c
ZY
3678static ssize_t show_channels(struct device *d,
3679 struct device_attribute *attr, char *buf)
3680{
8318d78a
JB
3681 /* all this shit doesn't belong into sysfs anyway */
3682 return 0;
b481de9c
ZY
3683}
3684
3685static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
3686
3687static ssize_t show_statistics(struct device *d,
3688 struct device_attribute *attr, char *buf)
3689{
4a8a4322 3690 struct iwl_priv *priv = dev_get_drvdata(d);
bb8c093b 3691 u32 size = sizeof(struct iwl3945_notif_statistics);
b481de9c 3692 u32 len = 0, ofs = 0;
f2c7e521 3693 u8 *data = (u8 *)&priv->statistics_39;
b481de9c
ZY
3694 int rc = 0;
3695
775a6e27 3696 if (!iwl_is_alive(priv))
b481de9c
ZY
3697 return -EAGAIN;
3698
3699 mutex_lock(&priv->mutex);
17f841cd 3700 rc = iwl_send_statistics_request(priv, 0);
b481de9c
ZY
3701 mutex_unlock(&priv->mutex);
3702
3703 if (rc) {
3704 len = sprintf(buf,
3705 "Error sending statistics request: 0x%08X\n", rc);
3706 return len;
3707 }
3708
3709 while (size && (PAGE_SIZE - len)) {
3710 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3711 PAGE_SIZE - len, 1);
3712 len = strlen(buf);
3713 if (PAGE_SIZE - len)
3714 buf[len++] = '\n';
3715
3716 ofs += 16;
3717 size -= min(size, 16U);
3718 }
3719
3720 return len;
3721}
3722
3723static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
3724
3725static ssize_t show_antenna(struct device *d,
3726 struct device_attribute *attr, char *buf)
3727{
4a8a4322 3728 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3729
775a6e27 3730 if (!iwl_is_alive(priv))
b481de9c
ZY
3731 return -EAGAIN;
3732
7e4bca5e 3733 return sprintf(buf, "%d\n", iwl3945_mod_params.antenna);
b481de9c
ZY
3734}
3735
3736static ssize_t store_antenna(struct device *d,
3737 struct device_attribute *attr,
3738 const char *buf, size_t count)
3739{
7530f85f 3740 struct iwl_priv *priv __maybe_unused = dev_get_drvdata(d);
b481de9c 3741 int ant;
b481de9c
ZY
3742
3743 if (count == 0)
3744 return 0;
3745
3746 if (sscanf(buf, "%1i", &ant) != 1) {
e1623446 3747 IWL_DEBUG_INFO(priv, "not in hex or decimal form.\n");
b481de9c
ZY
3748 return count;
3749 }
3750
3751 if ((ant >= 0) && (ant <= 2)) {
e1623446 3752 IWL_DEBUG_INFO(priv, "Setting antenna select to %d.\n", ant);
7e4bca5e 3753 iwl3945_mod_params.antenna = (enum iwl3945_antenna)ant;
b481de9c 3754 } else
e1623446 3755 IWL_DEBUG_INFO(priv, "Bad antenna select value %d.\n", ant);
b481de9c
ZY
3756
3757
3758 return count;
3759}
3760
3761static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
3762
3763static ssize_t show_status(struct device *d,
3764 struct device_attribute *attr, char *buf)
3765{
928841b1 3766 struct iwl_priv *priv = dev_get_drvdata(d);
775a6e27 3767 if (!iwl_is_alive(priv))
b481de9c
ZY
3768 return -EAGAIN;
3769 return sprintf(buf, "0x%08x\n", (int)priv->status);
3770}
3771
3772static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
3773
3774static ssize_t dump_error_log(struct device *d,
3775 struct device_attribute *attr,
3776 const char *buf, size_t count)
3777{
928841b1 3778 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3779 char *p = (char *)buf;
3780
3781 if (p[0] == '1')
928841b1 3782 iwl3945_dump_nic_error_log(priv);
b481de9c
ZY
3783
3784 return strnlen(buf, count);
3785}
3786
3787static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
3788
3789static ssize_t dump_event_log(struct device *d,
3790 struct device_attribute *attr,
3791 const char *buf, size_t count)
3792{
928841b1 3793 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3794 char *p = (char *)buf;
3795
3796 if (p[0] == '1')
928841b1 3797 iwl3945_dump_nic_event_log(priv);
b481de9c
ZY
3798
3799 return strnlen(buf, count);
3800}
3801
3802static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
3803
3804/*****************************************************************************
3805 *
a96a27f9 3806 * driver setup and tear down
b481de9c
ZY
3807 *
3808 *****************************************************************************/
3809
4a8a4322 3810static void iwl3945_setup_deferred_work(struct iwl_priv *priv)
b481de9c 3811{
d21050c7 3812 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY
3813
3814 init_waitqueue_head(&priv->wait_command_queue);
3815
bb8c093b
CH
3816 INIT_WORK(&priv->up, iwl3945_bg_up);
3817 INIT_WORK(&priv->restart, iwl3945_bg_restart);
3818 INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
bb8c093b 3819 INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
bb8c093b
CH
3820 INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
3821 INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
2663516d 3822 INIT_DELAYED_WORK(&priv->rfkill_poll, iwl3945_rfkill_poll);
77fecfb8
SO
3823 INIT_WORK(&priv->scan_completed, iwl_bg_scan_completed);
3824 INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
3825 INIT_WORK(&priv->abort_scan, iwl_bg_abort_scan);
3826 INIT_DELAYED_WORK(&priv->scan_check, iwl_bg_scan_check);
bb8c093b
CH
3827
3828 iwl3945_hw_setup_deferred_work(priv);
b481de9c
ZY
3829
3830 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
bb8c093b 3831 iwl3945_irq_tasklet, (unsigned long)priv);
b481de9c
ZY
3832}
3833
4a8a4322 3834static void iwl3945_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 3835{
bb8c093b 3836 iwl3945_hw_cancel_deferred_work(priv);
b481de9c 3837
e47eb6ad 3838 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY
3839 cancel_delayed_work(&priv->scan_check);
3840 cancel_delayed_work(&priv->alive_start);
b481de9c
ZY
3841 cancel_work_sync(&priv->beacon_update);
3842}
3843
bb8c093b 3844static struct attribute *iwl3945_sysfs_entries[] = {
b481de9c
ZY
3845 &dev_attr_antenna.attr,
3846 &dev_attr_channels.attr,
3847 &dev_attr_dump_errors.attr,
3848 &dev_attr_dump_events.attr,
3849 &dev_attr_flags.attr,
3850 &dev_attr_filter_flags.attr,
c8b0e6e1 3851#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY
3852 &dev_attr_measurement.attr,
3853#endif
3854 &dev_attr_power_level.attr,
b481de9c 3855 &dev_attr_retry_rate.attr,
b481de9c
ZY
3856 &dev_attr_statistics.attr,
3857 &dev_attr_status.attr,
3858 &dev_attr_temperature.attr,
b481de9c 3859 &dev_attr_tx_power.attr,
d08853a3 3860#ifdef CONFIG_IWLWIFI_DEBUG
40b8ec0b
SO
3861 &dev_attr_debug_level.attr,
3862#endif
b481de9c
ZY
3863 NULL
3864};
3865
bb8c093b 3866static struct attribute_group iwl3945_attribute_group = {
b481de9c 3867 .name = NULL, /* put in device directory */
bb8c093b 3868 .attrs = iwl3945_sysfs_entries,
b481de9c
ZY
3869};
3870
bb8c093b
CH
3871static struct ieee80211_ops iwl3945_hw_ops = {
3872 .tx = iwl3945_mac_tx,
3873 .start = iwl3945_mac_start,
3874 .stop = iwl3945_mac_stop,
cbb6ab94 3875 .add_interface = iwl_mac_add_interface,
d8052319 3876 .remove_interface = iwl_mac_remove_interface,
4808368d 3877 .config = iwl_mac_config,
8ccde88a 3878 .configure_filter = iwl_configure_filter,
bb8c093b 3879 .set_key = iwl3945_mac_set_key,
aa89f31e 3880 .get_tx_stats = iwl_mac_get_tx_stats,
488829f1 3881 .conf_tx = iwl_mac_conf_tx,
bd564261 3882 .reset_tsf = iwl_mac_reset_tsf,
5bbe233b 3883 .bss_info_changed = iwl_bss_info_changed,
e9dde6f6 3884 .hw_scan = iwl_mac_hw_scan
b481de9c
ZY
3885};
3886
e52119c5 3887static int iwl3945_init_drv(struct iwl_priv *priv)
90a30a02
KA
3888{
3889 int ret;
e6148917 3890 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
90a30a02
KA
3891
3892 priv->retry_rate = 1;
3893 priv->ibss_beacon = NULL;
3894
3895 spin_lock_init(&priv->lock);
90a30a02
KA
3896 spin_lock_init(&priv->sta_lock);
3897 spin_lock_init(&priv->hcmd_lock);
3898
3899 INIT_LIST_HEAD(&priv->free_frames);
3900
3901 mutex_init(&priv->mutex);
3902
3903 /* Clear the driver's (not device's) station table */
c587de0b 3904 iwl_clear_stations_table(priv);
90a30a02
KA
3905
3906 priv->data_retry_limit = -1;
3907 priv->ieee_channels = NULL;
3908 priv->ieee_rates = NULL;
3909 priv->band = IEEE80211_BAND_2GHZ;
3910
3911 priv->iw_mode = NL80211_IFTYPE_STATION;
3912
3913 iwl_reset_qos(priv);
3914
3915 priv->qos_data.qos_active = 0;
3916 priv->qos_data.qos_cap.val = 0;
3917
3918 priv->rates_mask = IWL_RATES_MASK;
d25aabb0
WT
3919 /* If power management is turned on, default to CAM mode */
3920 priv->power_mode = IWL_POWER_MODE_CAM;
62ea9c5b 3921 priv->tx_power_user_lmt = IWL_DEFAULT_TX_POWER;
90a30a02 3922
e6148917
SO
3923 if (eeprom->version < EEPROM_3945_EEPROM_VERSION) {
3924 IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n",
3925 eeprom->version);
3926 ret = -EINVAL;
3927 goto err;
3928 }
3929 ret = iwl_init_channel_map(priv);
90a30a02
KA
3930 if (ret) {
3931 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3932 goto err;
3933 }
3934
e6148917
SO
3935 /* Set up txpower settings in driver for all channels */
3936 if (iwl3945_txpower_set_from_eeprom(priv)) {
3937 ret = -EIO;
3938 goto err_free_channel_map;
3939 }
3940
534166de 3941 ret = iwlcore_init_geos(priv);
90a30a02
KA
3942 if (ret) {
3943 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3944 goto err_free_channel_map;
3945 }
534166de
SO
3946 iwl3945_init_hw_rates(priv, priv->ieee_rates);
3947
2a4ddaab
AK
3948 return 0;
3949
3950err_free_channel_map:
3951 iwl_free_channel_map(priv);
3952err:
3953 return ret;
3954}
3955
3956static int iwl3945_setup_mac(struct iwl_priv *priv)
3957{
3958 int ret;
3959 struct ieee80211_hw *hw = priv->hw;
3960
3961 hw->rate_control_algorithm = "iwl-3945-rs";
3962 hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
3963
3964 /* Tell mac80211 our characteristics */
3965 hw->flags = IEEE80211_HW_SIGNAL_DBM |
b1c6019b
MA
3966 IEEE80211_HW_NOISE_DBM |
3967 IEEE80211_HW_SPECTRUM_MGMT;
2a4ddaab
AK
3968
3969 hw->wiphy->interface_modes =
3970 BIT(NL80211_IFTYPE_STATION) |
3971 BIT(NL80211_IFTYPE_ADHOC);
3972
3973 hw->wiphy->custom_regulatory = true;
3974
1ecf9fc1
JB
3975 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX_3945;
3976 /* we create the 802.11 header and a zero-length SSID element */
3977 hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
d60cc91a 3978
2a4ddaab
AK
3979 /* Default value; 4 EDCA QOS priorities */
3980 hw->queues = 4;
3981
534166de
SO
3982 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3983 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3984 &priv->bands[IEEE80211_BAND_2GHZ];
2a4ddaab 3985
534166de
SO
3986 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3987 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3988 &priv->bands[IEEE80211_BAND_5GHZ];
90a30a02 3989
2a4ddaab
AK
3990 ret = ieee80211_register_hw(priv->hw);
3991 if (ret) {
3992 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3993 return ret;
3994 }
3995 priv->mac80211_registered = 1;
90a30a02 3996
2a4ddaab 3997 return 0;
90a30a02
KA
3998}
3999
bb8c093b 4000static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY
4001{
4002 int err = 0;
4a8a4322 4003 struct iwl_priv *priv;
b481de9c 4004 struct ieee80211_hw *hw;
c0f20d91 4005 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
e6148917 4006 struct iwl3945_eeprom *eeprom;
0359facc 4007 unsigned long flags;
b481de9c 4008
cee53ddb
KA
4009 /***********************
4010 * 1. Allocating HW data
4011 * ********************/
4012
b481de9c
ZY
4013 /* mac80211 allocates memory for this device instance, including
4014 * space for this driver's private structure */
90a30a02 4015 hw = iwl_alloc_all(cfg, &iwl3945_hw_ops);
b481de9c 4016 if (hw == NULL) {
a3139c59 4017 printk(KERN_ERR DRV_NAME "Can not allocate network device\n");
b481de9c
ZY
4018 err = -ENOMEM;
4019 goto out;
4020 }
b481de9c 4021 priv = hw->priv;
90a30a02 4022 SET_IEEE80211_DEV(hw, &pdev->dev);
6440adb5 4023
df878d8f
KA
4024 if ((iwl3945_mod_params.num_of_queues > IWL39_MAX_NUM_QUEUES) ||
4025 (iwl3945_mod_params.num_of_queues < IWL_MIN_NUM_QUEUES)) {
15b1687c
WT
4026 IWL_ERR(priv,
4027 "invalid queues_num, should be between %d and %d\n",
4028 IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES);
a3139c59 4029 err = -EINVAL;
c8f16138 4030 goto out_ieee80211_free_hw;
a3139c59
SO
4031 }
4032
90a30a02
KA
4033 /*
4034 * Disabling hardware scan means that mac80211 will perform scans
4035 * "the hard way", rather than using device's scan.
4036 */
df878d8f 4037 if (iwl3945_mod_params.disable_hw_scan) {
e1623446 4038 IWL_DEBUG_INFO(priv, "Disabling hw_scan\n");
40b8ec0b
SO
4039 iwl3945_hw_ops.hw_scan = NULL;
4040 }
4041
90a30a02 4042
e1623446 4043 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
90a30a02
KA
4044 priv->cfg = cfg;
4045 priv->pci_dev = pdev;
40cefda9 4046 priv->inta_mask = CSR_INI_SET_MASK;
cee53ddb 4047
d08853a3 4048#ifdef CONFIG_IWLWIFI_DEBUG
df878d8f 4049 priv->debug_level = iwl3945_mod_params.debug;
b481de9c
ZY
4050 atomic_set(&priv->restrict_refcnt, 0);
4051#endif
b481de9c 4052
cee53ddb
KA
4053 /***************************
4054 * 2. Initializing PCI bus
4055 * *************************/
b481de9c
ZY
4056 if (pci_enable_device(pdev)) {
4057 err = -ENODEV;
4058 goto out_ieee80211_free_hw;
4059 }
4060
4061 pci_set_master(pdev);
4062
284901a9 4063 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
b481de9c 4064 if (!err)
284901a9 4065 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
b481de9c 4066 if (err) {
978785a3 4067 IWL_WARN(priv, "No suitable DMA available.\n");
b481de9c
ZY
4068 goto out_pci_disable_device;
4069 }
4070
4071 pci_set_drvdata(pdev, priv);
4072 err = pci_request_regions(pdev, DRV_NAME);
4073 if (err)
4074 goto out_pci_disable_device;
6440adb5 4075
cee53ddb
KA
4076 /***********************
4077 * 3. Read REV Register
4078 * ********************/
b481de9c
ZY
4079 priv->hw_base = pci_iomap(pdev, 0, 0);
4080 if (!priv->hw_base) {
4081 err = -ENODEV;
4082 goto out_pci_release_regions;
4083 }
4084
e1623446 4085 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
b481de9c 4086 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 4087 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
b481de9c 4088
cee53ddb
KA
4089 /* We disable the RETRY_TIMEOUT register (0x41) to keep
4090 * PCI Tx retries from interfering with C3 CPU state */
4091 pci_write_config_byte(pdev, 0x41, 0x00);
b481de9c 4092
a8b50a0a
MA
4093 /* this spin lock will be used in apm_ops.init and EEPROM access
4094 * we should init now
4095 */
4096 spin_lock_init(&priv->reg_lock);
4097
90a30a02
KA
4098 /* amp init */
4099 err = priv->cfg->ops->lib->apm_ops.init(priv);
cee53ddb 4100 if (err < 0) {
d5df2a16 4101 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
90a30a02 4102 goto out_iounmap;
cee53ddb 4103 }
b481de9c 4104
cee53ddb
KA
4105 /***********************
4106 * 4. Read EEPROM
4107 * ********************/
90a30a02 4108
cee53ddb 4109 /* Read the EEPROM */
e6148917 4110 err = iwl_eeprom_init(priv);
cee53ddb 4111 if (err) {
15b1687c 4112 IWL_ERR(priv, "Unable to init EEPROM\n");
c8f16138 4113 goto out_iounmap;
cee53ddb
KA
4114 }
4115 /* MAC Address location in EEPROM same for 3945/4965 */
e6148917
SO
4116 eeprom = (struct iwl3945_eeprom *)priv->eeprom;
4117 memcpy(priv->mac_addr, eeprom->mac_address, ETH_ALEN);
e1623446 4118 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
cee53ddb 4119 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
b481de9c 4120
cee53ddb
KA
4121 /***********************
4122 * 5. Setup HW Constants
4123 * ********************/
b481de9c 4124 /* Device-specific setup */
3832ec9d 4125 if (iwl3945_hw_set_hw_params(priv)) {
15b1687c 4126 IWL_ERR(priv, "failed to set hw settings\n");
c8f16138 4127 goto out_eeprom_free;
b481de9c
ZY
4128 }
4129
cee53ddb
KA
4130 /***********************
4131 * 6. Setup priv
4132 * ********************/
cee53ddb 4133
90a30a02 4134 err = iwl3945_init_drv(priv);
b481de9c 4135 if (err) {
90a30a02 4136 IWL_ERR(priv, "initializing driver failed\n");
c8f16138 4137 goto out_unset_hw_params;
b481de9c
ZY
4138 }
4139
978785a3
TW
4140 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n",
4141 priv->cfg->name);
cee53ddb 4142
cee53ddb 4143 /***********************
09f9bf79 4144 * 7. Setup Services
cee53ddb
KA
4145 * ********************/
4146
4147 spin_lock_irqsave(&priv->lock, flags);
ed3b932e 4148 iwl_disable_interrupts(priv);
cee53ddb
KA
4149 spin_unlock_irqrestore(&priv->lock, flags);
4150
2663516d
HS
4151 pci_enable_msi(priv->pci_dev);
4152
ef850d7c
MA
4153 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
4154 IRQF_SHARED, DRV_NAME, priv);
2663516d
HS
4155 if (err) {
4156 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4157 goto out_disable_msi;
4158 }
4159
cee53ddb 4160 err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
849e0dce 4161 if (err) {
15b1687c 4162 IWL_ERR(priv, "failed to create sysfs device attributes\n");
90a30a02 4163 goto out_release_irq;
849e0dce 4164 }
849e0dce 4165
8ccde88a
SO
4166 iwl_set_rxon_channel(priv,
4167 &priv->bands[IEEE80211_BAND_2GHZ].channels[5]);
cee53ddb
KA
4168 iwl3945_setup_deferred_work(priv);
4169 iwl3945_setup_rx_handlers(priv);
4170
cee53ddb 4171 /*********************************
09f9bf79 4172 * 8. Setup and Register mac80211
cee53ddb
KA
4173 * *******************************/
4174
2a4ddaab 4175 iwl_enable_interrupts(priv);
b481de9c 4176
2a4ddaab
AK
4177 err = iwl3945_setup_mac(priv);
4178 if (err)
4179 goto out_remove_sysfs;
cee53ddb 4180
a75fbe8d
AK
4181 err = iwl_dbgfs_register(priv, DRV_NAME);
4182 if (err)
4183 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
4184
2663516d
HS
4185 /* Start monitoring the killswitch */
4186 queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
4187 2 * HZ);
4188
b481de9c
ZY
4189 return 0;
4190
cee53ddb 4191 out_remove_sysfs:
c8f16138
RC
4192 destroy_workqueue(priv->workqueue);
4193 priv->workqueue = NULL;
cee53ddb 4194 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 4195 out_release_irq:
2663516d 4196 free_irq(priv->pci_dev->irq, priv);
2663516d
HS
4197 out_disable_msi:
4198 pci_disable_msi(priv->pci_dev);
c8f16138
RC
4199 iwlcore_free_geos(priv);
4200 iwl_free_channel_map(priv);
4201 out_unset_hw_params:
4202 iwl3945_unset_hw_params(priv);
4203 out_eeprom_free:
4204 iwl_eeprom_free(priv);
b481de9c
ZY
4205 out_iounmap:
4206 pci_iounmap(pdev, priv->hw_base);
4207 out_pci_release_regions:
4208 pci_release_regions(pdev);
4209 out_pci_disable_device:
b481de9c 4210 pci_set_drvdata(pdev, NULL);
623d563e 4211 pci_disable_device(pdev);
b481de9c
ZY
4212 out_ieee80211_free_hw:
4213 ieee80211_free_hw(priv->hw);
4214 out:
4215 return err;
4216}
4217
c83dbf68 4218static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
b481de9c 4219{
4a8a4322 4220 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 4221 unsigned long flags;
b481de9c
ZY
4222
4223 if (!priv)
4224 return;
4225
e1623446 4226 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 4227
a75fbe8d
AK
4228 iwl_dbgfs_unregister(priv);
4229
b481de9c 4230 set_bit(STATUS_EXIT_PENDING, &priv->status);
b24d22b1 4231
d552bfb6
KA
4232 if (priv->mac80211_registered) {
4233 ieee80211_unregister_hw(priv->hw);
4234 priv->mac80211_registered = 0;
4235 } else {
4236 iwl3945_down(priv);
4237 }
b481de9c 4238
0359facc
MA
4239 /* make sure we flush any pending irq or
4240 * tasklet for the driver
4241 */
4242 spin_lock_irqsave(&priv->lock, flags);
ed3b932e 4243 iwl_disable_interrupts(priv);
0359facc
MA
4244 spin_unlock_irqrestore(&priv->lock, flags);
4245
4246 iwl_synchronize_irq(priv);
4247
bb8c093b 4248 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 4249
71d449b5 4250 cancel_delayed_work_sync(&priv->rfkill_poll);
2663516d 4251
bb8c093b 4252 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY
4253
4254 if (priv->rxq.bd)
df833b1d 4255 iwl3945_rx_queue_free(priv, &priv->rxq);
bb8c093b 4256 iwl3945_hw_txq_ctx_free(priv);
b481de9c 4257
3832ec9d 4258 iwl3945_unset_hw_params(priv);
c587de0b 4259 iwl_clear_stations_table(priv);
b481de9c 4260
6ef89d0a
MA
4261 /*netif_stop_queue(dev); */
4262 flush_workqueue(priv->workqueue);
4263
bb8c093b 4264 /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
b481de9c
ZY
4265 * priv->workqueue... so we can't take down the workqueue
4266 * until now... */
4267 destroy_workqueue(priv->workqueue);
4268 priv->workqueue = NULL;
4269
2663516d
HS
4270 free_irq(pdev->irq, priv);
4271 pci_disable_msi(pdev);
4272
b481de9c
ZY
4273 pci_iounmap(pdev, priv->hw_base);
4274 pci_release_regions(pdev);
4275 pci_disable_device(pdev);
4276 pci_set_drvdata(pdev, NULL);
4277
e6148917 4278 iwl_free_channel_map(priv);
534166de 4279 iwlcore_free_geos(priv);
805cee5b 4280 kfree(priv->scan);
b481de9c
ZY
4281 if (priv->ibss_beacon)
4282 dev_kfree_skb(priv->ibss_beacon);
4283
4284 ieee80211_free_hw(priv->hw);
4285}
4286
b481de9c
ZY
4287
4288/*****************************************************************************
4289 *
4290 * driver and module entry point
4291 *
4292 *****************************************************************************/
4293
bb8c093b 4294static struct pci_driver iwl3945_driver = {
b481de9c 4295 .name = DRV_NAME,
bb8c093b
CH
4296 .id_table = iwl3945_hw_card_ids,
4297 .probe = iwl3945_pci_probe,
4298 .remove = __devexit_p(iwl3945_pci_remove),
b481de9c 4299#ifdef CONFIG_PM
6da3a13e
WYG
4300 .suspend = iwl_pci_suspend,
4301 .resume = iwl_pci_resume,
b481de9c
ZY
4302#endif
4303};
4304
bb8c093b 4305static int __init iwl3945_init(void)
b481de9c
ZY
4306{
4307
4308 int ret;
4309 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
4310 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2
RC
4311
4312 ret = iwl3945_rate_control_register();
4313 if (ret) {
a3139c59
SO
4314 printk(KERN_ERR DRV_NAME
4315 "Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC
4316 return ret;
4317 }
4318
bb8c093b 4319 ret = pci_register_driver(&iwl3945_driver);
b481de9c 4320 if (ret) {
a3139c59 4321 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
897e1cf2 4322 goto error_register;
b481de9c 4323 }
b481de9c
ZY
4324
4325 return ret;
897e1cf2 4326
897e1cf2
RC
4327error_register:
4328 iwl3945_rate_control_unregister();
4329 return ret;
b481de9c
ZY
4330}
4331
bb8c093b 4332static void __exit iwl3945_exit(void)
b481de9c 4333{
bb8c093b 4334 pci_unregister_driver(&iwl3945_driver);
897e1cf2 4335 iwl3945_rate_control_unregister();
b481de9c
ZY
4336}
4337
a0987a8d 4338MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
25cb6cad 4339
df878d8f 4340module_param_named(antenna, iwl3945_mod_params.antenna, int, 0444);
b481de9c 4341MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
9c74d9fb
SO
4342module_param_named(swcrypto, iwl3945_mod_params.sw_crypto, int, 0444);
4343MODULE_PARM_DESC(swcrypto,
4344 "using software crypto (default 1 [software])\n");
df878d8f 4345module_param_named(debug, iwl3945_mod_params.debug, uint, 0444);
b481de9c 4346MODULE_PARM_DESC(debug, "debug output mask");
df878d8f 4347module_param_named(disable_hw_scan, iwl3945_mod_params.disable_hw_scan, int, 0444);
b481de9c
ZY
4348MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
4349
df878d8f 4350module_param_named(queues_num, iwl3945_mod_params.num_of_queues, int, 0444);
b481de9c
ZY
4351MODULE_PARM_DESC(queues_num, "number of hw queues.");
4352
af48d048
SO
4353module_param_named(fw_restart3945, iwl3945_mod_params.restart_fw, int, 0444);
4354MODULE_PARM_DESC(fw_restart3945, "restart firmware in case of error");
4355
bb8c093b
CH
4356module_exit(iwl3945_exit);
4357module_init(iwl3945_init);
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