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iwlwifi: use ieee80211_frequency_to_channel
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl3945-base.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
b481de9c
ZY		 30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/version.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/dma-mapping.h>
36#include <linux/delay.h>
37#include <linux/skbuff.h>
38#include <linux/netdevice.h>
39#include <linux/wireless.h>
40#include <linux/firmware.h>
b481de9c
ZY		 41#include <linux/etherdevice.h>
42#include <linux/if_arp.h>
43
44#include <net/ieee80211_radiotap.h>
45#include <net/mac80211.h>
46
47#include <asm/div64.h>
48
82b9a121 49#include "iwl-3945-core.h"
b481de9c
ZY		 50#include "iwl-3945.h"
51#include "iwl-helpers.h"
52
c8b0e6e1 53#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 54u32 iwl3945_debug_level;
b481de9c
ZY		 55#endif
56
bb8c093b
CH		 57static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
58 struct iwl3945_tx_queue *txq);
416e1438 59
b481de9c
ZY		 60/******************************************************************************
61 *
62 * module boiler plate
63 *
64 ******************************************************************************/
65
66/* module parameters */
6440adb5
CB		 67static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */
68static int iwl3945_param_debug; /* def: 0 = minimal debug log messages */
69static int iwl3945_param_disable; /* def: 0 = enable radio */
9fbab516 70static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */
6440adb5
CB		 71int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */
72static int iwl3945_param_qos_enable = 1; /* def: 1 = use quality of service */
73int iwl3945_param_queues_num = IWL_MAX_NUM_QUEUES; /* def: 8 Tx queues */
b481de9c
ZY		 74
75/*
76 * module name, copyright, version, etc.
77 * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
78 */
79
80#define DRV_DESCRIPTION \
81"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
82
c8b0e6e1 83#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 84#define VD "d"
85#else
86#define VD
87#endif
88
c8b0e6e1 89#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 90#define VS "s"
91#else
92#define VS
93#endif
94
b9e0b449 95#define IWLWIFI_VERSION "1.2.26k" VD VS
eb7ae89c 96#define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation"
b481de9c
ZY		 97#define DRV_VERSION IWLWIFI_VERSION
98
b481de9c
ZY		 99
100MODULE_DESCRIPTION(DRV_DESCRIPTION);
101MODULE_VERSION(DRV_VERSION);
102MODULE_AUTHOR(DRV_COPYRIGHT);
103MODULE_LICENSE("GPL");
104
416e1438 105static __le16 *ieee80211_get_qos_ctrl(struct ieee80211_hdr *hdr)
b481de9c
ZY		 106{
107 u16 fc = le16_to_cpu(hdr->frame_control);
108 int hdr_len = ieee80211_get_hdrlen(fc);
109
110 if ((fc & 0x00cc) == (IEEE80211_STYPE_QOS_DATA | IEEE80211_FTYPE_DATA))
111 return (__le16 *) ((u8 *) hdr + hdr_len - QOS_CONTROL_LEN);
112 return NULL;
113}
114
8318d78a
JB		 115static const struct ieee80211_supported_band *iwl3945_get_band(
116 struct iwl3945_priv *priv, enum ieee80211_band band)
b481de9c 117{
8318d78a 118 return priv->hw->wiphy->bands[band];
b481de9c
ZY		 119}
120
bb8c093b 121static int iwl3945_is_empty_essid(const char *essid, int essid_len)
b481de9c
ZY		 122{
123 /* Single white space is for Linksys APs */
124 if (essid_len == 1 && essid[0] == ' ')
125 return 1;
126
127 /* Otherwise, if the entire essid is 0, we assume it is hidden */
128 while (essid_len) {
129 essid_len--;
130 if (essid[essid_len] != '\0')
131 return 0;
132 }
133
134 return 1;
135}
136
bb8c093b 137static const char *iwl3945_escape_essid(const char *essid, u8 essid_len)
b481de9c
ZY		 138{
139 static char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
140 const char *s = essid;
141 char *d = escaped;
142
bb8c093b 143 if (iwl3945_is_empty_essid(essid, essid_len)) {
b481de9c
ZY		 144 memcpy(escaped, "<hidden>", sizeof("<hidden>"));
145 return escaped;
146 }
147
148 essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE);
149 while (essid_len--) {
150 if (*s == '\0') {
151 *d++ = '\\';
152 *d++ = '0';
153 s++;
154 } else
155 *d++ = *s++;
156 }
157 *d = '\0';
158 return escaped;
159}
160
b481de9c
ZY		 161/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
162 * DMA services
163 *
164 * Theory of operation
165 *
6440adb5
CB		 166 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
167 * of buffer descriptors, each of which points to one or more data buffers for
168 * the device to read from or fill. Driver and device exchange status of each
169 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
170 * entries in each circular buffer, to protect against confusing empty and full
171 * queue states.
172 *
173 * The device reads or writes the data in the queues via the device's several
174 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
b481de9c
ZY		 175 *
176 * For Tx queue, there are low mark and high mark limits. If, after queuing
177 * the packet for Tx, free space become < low mark, Tx queue stopped. When
178 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
179 * Tx queue resumed.
180 *
6440adb5
CB		 181 * The 3945 operates with six queues: One receive queue, one transmit queue
182 * (#4) for sending commands to the device firmware, and four transmit queues
183 * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
b481de9c
ZY		 184 ***************************************************/
185
c54b679d 186int iwl3945_queue_space(const struct iwl3945_queue *q)
b481de9c 187{
fc4b6853 188 int s = q->read_ptr - q->write_ptr;
b481de9c 189
fc4b6853 190 if (q->read_ptr > q->write_ptr)
b481de9c
ZY		 191 s -= q->n_bd;
192
193 if (s <= 0)
194 s += q->n_window;
195 /* keep some reserve to not confuse empty and full situations */
196 s -= 2;
197 if (s < 0)
198 s = 0;
199 return s;
200}
201
c54b679d 202int iwl3945_x2_queue_used(const struct iwl3945_queue *q, int i)
b481de9c 203{
fc4b6853
TW		 204 return q->write_ptr > q->read_ptr ?
205 (i >= q->read_ptr && i < q->write_ptr) :
206 !(i < q->read_ptr && i >= q->write_ptr);
b481de9c
ZY		 207}
208
c54b679d 209
bb8c093b 210static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge)
b481de9c 211{
6440adb5 212 /* This is for scan command, the big buffer at end of command array */
b481de9c 213 if (is_huge)
6440adb5 214 return q->n_window; /* must be power of 2 */
b481de9c 215
6440adb5 216 /* Otherwise, use normal size buffers */
b481de9c
ZY		 217 return index & (q->n_window - 1);
218}
219
6440adb5
CB		 220/**
221 * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
222 */
bb8c093b 223static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q,
b481de9c
ZY		 224 int count, int slots_num, u32 id)
225{
226 q->n_bd = count;
227 q->n_window = slots_num;
228 q->id = id;
229
c54b679d
TW		 230 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
231 * and iwl_queue_dec_wrap are broken. */
b481de9c
ZY		 232 BUG_ON(!is_power_of_2(count));
233
234 /* slots_num must be power-of-two size, otherwise
235 * get_cmd_index is broken. */
236 BUG_ON(!is_power_of_2(slots_num));
237
238 q->low_mark = q->n_window / 4;
239 if (q->low_mark < 4)
240 q->low_mark = 4;
241
242 q->high_mark = q->n_window / 8;
243 if (q->high_mark < 2)
244 q->high_mark = 2;
245
fc4b6853 246 q->write_ptr = q->read_ptr = 0;
b481de9c
ZY		 247
248 return 0;
249}
250
6440adb5
CB		 251/**
252 * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
253 */
bb8c093b
CH		 254static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
255 struct iwl3945_tx_queue *txq, u32 id)
b481de9c
ZY		 256{
257 struct pci_dev *dev = priv->pci_dev;
258
6440adb5
CB		 259 /* Driver private data, only for Tx (not command) queues,
260 * not shared with device. */
b481de9c
ZY		 261 if (id != IWL_CMD_QUEUE_NUM) {
262 txq->txb = kmalloc(sizeof(txq->txb[0]) *
263 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
264 if (!txq->txb) {
01ebd063 265 IWL_ERROR("kmalloc for auxiliary BD "
b481de9c
ZY		 266 "structures failed\n");
267 goto error;
268 }
269 } else
270 txq->txb = NULL;
271
6440adb5
CB		 272 /* Circular buffer of transmit frame descriptors (TFDs),
273 * shared with device */
b481de9c
ZY		 274 txq->bd = pci_alloc_consistent(dev,
275 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
276 &txq->q.dma_addr);
277
278 if (!txq->bd) {
279 IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
280 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
281 goto error;
282 }
283 txq->q.id = id;
284
285 return 0;
286
287 error:
288 if (txq->txb) {
289 kfree(txq->txb);
290 txq->txb = NULL;
291 }
292
293 return -ENOMEM;
294}
295
6440adb5
CB		 296/**
297 * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
298 */
bb8c093b
CH		 299int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
300 struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
b481de9c
ZY		 301{
302 struct pci_dev *dev = priv->pci_dev;
303 int len;
304 int rc = 0;
305
6440adb5
CB		 306 /*
307 * Alloc buffer array for commands (Tx or other types of commands).
308 * For the command queue (#4), allocate command space + one big
309 * command for scan, since scan command is very huge; the system will
310 * not have two scans at the same time, so only one is needed.
311 * For data Tx queues (all other queues), no super-size command
312 * space is needed.
313 */
bb8c093b 314 len = sizeof(struct iwl3945_cmd) * slots_num;
b481de9c
ZY		 315 if (txq_id == IWL_CMD_QUEUE_NUM)
316 len += IWL_MAX_SCAN_SIZE;
317 txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
318 if (!txq->cmd)
319 return -ENOMEM;
320
6440adb5 321 /* Alloc driver data array and TFD circular buffer */
bb8c093b 322 rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
b481de9c
ZY		 323 if (rc) {
324 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
325
326 return -ENOMEM;
327 }
328 txq->need_update = 0;
329
330 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
c54b679d 331 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
b481de9c 332 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
6440adb5
CB		 333
334 /* Initialize queue high/low-water, head/tail indexes */
bb8c093b 335 iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
b481de9c 336
6440adb5 337 /* Tell device where to find queue, enable DMA channel. */
bb8c093b 338 iwl3945_hw_tx_queue_init(priv, txq);
b481de9c
ZY		 339
340 return 0;
341}
342
343/**
bb8c093b 344 * iwl3945_tx_queue_free - Deallocate DMA queue.
b481de9c
ZY		 345 * @txq: Transmit queue to deallocate.
346 *
347 * Empty queue by removing and destroying all BD's.
6440adb5
CB		 348 * Free all buffers.
349 * 0-fill, but do not free "txq" descriptor structure.
b481de9c 350 */
bb8c093b 351void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c 352{
bb8c093b 353 struct iwl3945_queue *q = &txq->q;
b481de9c
ZY		 354 struct pci_dev *dev = priv->pci_dev;
355 int len;
356
357 if (q->n_bd == 0)
358 return;
359
360 /* first, empty all BD's */
fc4b6853 361 for (; q->write_ptr != q->read_ptr;
c54b679d 362 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
bb8c093b 363 iwl3945_hw_txq_free_tfd(priv, txq);
b481de9c 364
bb8c093b 365 len = sizeof(struct iwl3945_cmd) * q->n_window;
b481de9c
ZY		 366 if (q->id == IWL_CMD_QUEUE_NUM)
367 len += IWL_MAX_SCAN_SIZE;
368
6440adb5 369 /* De-alloc array of command/tx buffers */
b481de9c
ZY		 370 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
371
6440adb5 372 /* De-alloc circular buffer of TFDs */
b481de9c 373 if (txq->q.n_bd)
bb8c093b 374 pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
b481de9c
ZY		 375 txq->q.n_bd, txq->bd, txq->q.dma_addr);
376
6440adb5 377 /* De-alloc array of per-TFD driver data */
b481de9c
ZY		 378 if (txq->txb) {
379 kfree(txq->txb);
380 txq->txb = NULL;
381 }
382
6440adb5 383 /* 0-fill queue descriptor structure */
b481de9c
ZY		 384 memset(txq, 0, sizeof(*txq));
385}
386
bb8c093b 387const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
b481de9c
ZY		 388
389/*************** STATION TABLE MANAGEMENT ****
9fbab516 390 * mac80211 should be examined to determine if sta_info is duplicating
b481de9c
ZY		 391 * the functionality provided here
392 */
393
394/**************************************************************/
01ebd063 395#if 0 /* temporary disable till we add real remove station */
6440adb5
CB		 396/**
397 * iwl3945_remove_station - Remove driver's knowledge of station.
398 *
399 * NOTE: This does not remove station from device's station table.
400 */
bb8c093b 401static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
b481de9c
ZY		 402{
403 int index = IWL_INVALID_STATION;
404 int i;
405 unsigned long flags;
406
407 spin_lock_irqsave(&priv->sta_lock, flags);
408
409 if (is_ap)
410 index = IWL_AP_ID;
411 else if (is_broadcast_ether_addr(addr))
412 index = priv->hw_setting.bcast_sta_id;
413 else
414 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
415 if (priv->stations[i].used &&
416 !compare_ether_addr(priv->stations[i].sta.sta.addr,
417 addr)) {
418 index = i;
419 break;
420 }
421
422 if (unlikely(index == IWL_INVALID_STATION))
423 goto out;
424
425 if (priv->stations[index].used) {
426 priv->stations[index].used = 0;
427 priv->num_stations--;
428 }
429
430 BUG_ON(priv->num_stations < 0);
431
432out:
433 spin_unlock_irqrestore(&priv->sta_lock, flags);
434 return 0;
435}
556f8db7 436#endif
6440adb5
CB		 437
438/**
439 * iwl3945_clear_stations_table - Clear the driver's station table
440 *
441 * NOTE: This does not clear or otherwise alter the device's station table.
442 */
bb8c093b 443static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
b481de9c
ZY		 444{
445 unsigned long flags;
446
447 spin_lock_irqsave(&priv->sta_lock, flags);
448
449 priv->num_stations = 0;
450 memset(priv->stations, 0, sizeof(priv->stations));
451
452 spin_unlock_irqrestore(&priv->sta_lock, flags);
453}
454
6440adb5
CB		 455/**
456 * iwl3945_add_station - Add station to station tables in driver and device
457 */
bb8c093b 458u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
b481de9c
ZY		 459{
460 int i;
461 int index = IWL_INVALID_STATION;
bb8c093b 462 struct iwl3945_station_entry *station;
b481de9c 463 unsigned long flags_spin;
0795af57 464 DECLARE_MAC_BUF(mac);
c14c521e 465 u8 rate;
b481de9c
ZY		 466
467 spin_lock_irqsave(&priv->sta_lock, flags_spin);
468 if (is_ap)
469 index = IWL_AP_ID;
470 else if (is_broadcast_ether_addr(addr))
471 index = priv->hw_setting.bcast_sta_id;
472 else
473 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
474 if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
475 addr)) {
476 index = i;
477 break;
478 }
479
480 if (!priv->stations[i].used &&
481 index == IWL_INVALID_STATION)
482 index = i;
483 }
484
01ebd063 485 /* These two conditions has the same outcome but keep them separate
b481de9c
ZY		 486 since they have different meaning */
487 if (unlikely(index == IWL_INVALID_STATION)) {
488 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
489 return index;
490 }
491
492 if (priv->stations[index].used &&
493 !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
494 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
495 return index;
496 }
497
0795af57 498 IWL_DEBUG_ASSOC("Add STA ID %d: %s\n", index, print_mac(mac, addr));
b481de9c
ZY		 499 station = &priv->stations[index];
500 station->used = 1;
501 priv->num_stations++;
502
6440adb5 503 /* Set up the REPLY_ADD_STA command to send to device */
bb8c093b 504 memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
b481de9c
ZY		 505 memcpy(station->sta.sta.addr, addr, ETH_ALEN);
506 station->sta.mode = 0;
507 station->sta.sta.sta_id = index;
508 station->sta.station_flags = 0;
509
8318d78a 510 if (priv->band == IEEE80211_BAND_5GHZ)
69946333
TW		 511 rate = IWL_RATE_6M_PLCP;
512 else
513 rate = IWL_RATE_1M_PLCP;
c14c521e
ZY		 514
515 /* Turn on both antennas for the station... */
516 station->sta.rate_n_flags =
bb8c093b 517 iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
c14c521e
ZY		 518 station->current_rate.rate_n_flags =
519 le16_to_cpu(station->sta.rate_n_flags);
520
b481de9c 521 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
6440adb5
CB		 522
523 /* Add station to device's station table */
bb8c093b 524 iwl3945_send_add_station(priv, &station->sta, flags);
b481de9c
ZY		 525 return index;
526
527}
528
529/*************** DRIVER STATUS FUNCTIONS *****/
530
bb8c093b 531static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
b481de9c
ZY		 532{
533 /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
534 * set but EXIT_PENDING is not */
535 return test_bit(STATUS_READY, &priv->status) &&
536 test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
537 !test_bit(STATUS_EXIT_PENDING, &priv->status);
538}
539
bb8c093b 540static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
b481de9c
ZY		 541{
542 return test_bit(STATUS_ALIVE, &priv->status);
543}
544
bb8c093b 545static inline int iwl3945_is_init(struct iwl3945_priv *priv)
b481de9c
ZY		 546{
547 return test_bit(STATUS_INIT, &priv->status);
548}
549
bb8c093b 550static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
b481de9c
ZY		 551{
552 return test_bit(STATUS_RF_KILL_HW, &priv->status) ||
553 test_bit(STATUS_RF_KILL_SW, &priv->status);
554}
555
bb8c093b 556static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
b481de9c
ZY		 557{
558
bb8c093b 559 if (iwl3945_is_rfkill(priv))
b481de9c
ZY		 560 return 0;
561
bb8c093b 562 return iwl3945_is_ready(priv);
b481de9c
ZY		 563}
564
565/*************** HOST COMMAND QUEUE FUNCTIONS *****/
566
567#define IWL_CMD(x) case x : return #x
568
569static const char *get_cmd_string(u8 cmd)
570{
571 switch (cmd) {
572 IWL_CMD(REPLY_ALIVE);
573 IWL_CMD(REPLY_ERROR);
574 IWL_CMD(REPLY_RXON);
575 IWL_CMD(REPLY_RXON_ASSOC);
576 IWL_CMD(REPLY_QOS_PARAM);
577 IWL_CMD(REPLY_RXON_TIMING);
578 IWL_CMD(REPLY_ADD_STA);
579 IWL_CMD(REPLY_REMOVE_STA);
580 IWL_CMD(REPLY_REMOVE_ALL_STA);
581 IWL_CMD(REPLY_3945_RX);
582 IWL_CMD(REPLY_TX);
583 IWL_CMD(REPLY_RATE_SCALE);
584 IWL_CMD(REPLY_LEDS_CMD);
585 IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
586 IWL_CMD(RADAR_NOTIFICATION);
587 IWL_CMD(REPLY_QUIET_CMD);
588 IWL_CMD(REPLY_CHANNEL_SWITCH);
589 IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
590 IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
591 IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
592 IWL_CMD(POWER_TABLE_CMD);
593 IWL_CMD(PM_SLEEP_NOTIFICATION);
594 IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
595 IWL_CMD(REPLY_SCAN_CMD);
596 IWL_CMD(REPLY_SCAN_ABORT_CMD);
597 IWL_CMD(SCAN_START_NOTIFICATION);
598 IWL_CMD(SCAN_RESULTS_NOTIFICATION);
599 IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
600 IWL_CMD(BEACON_NOTIFICATION);
601 IWL_CMD(REPLY_TX_BEACON);
602 IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
603 IWL_CMD(QUIET_NOTIFICATION);
604 IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
605 IWL_CMD(MEASURE_ABORT_NOTIFICATION);
606 IWL_CMD(REPLY_BT_CONFIG);
607 IWL_CMD(REPLY_STATISTICS_CMD);
608 IWL_CMD(STATISTICS_NOTIFICATION);
609 IWL_CMD(REPLY_CARD_STATE_CMD);
610 IWL_CMD(CARD_STATE_NOTIFICATION);
611 IWL_CMD(MISSED_BEACONS_NOTIFICATION);
612 default:
613 return "UNKNOWN";
614
615 }
616}
617
618#define HOST_COMPLETE_TIMEOUT (HZ / 2)
619
620/**
bb8c093b 621 * iwl3945_enqueue_hcmd - enqueue a uCode command
b481de9c
ZY		 622 * @priv: device private data point
623 * @cmd: a point to the ucode command structure
624 *
625 * The function returns < 0 values to indicate the operation is
626 * failed. On success, it turns the index (> 0) of command in the
627 * command queue.
628 */
bb8c093b 629static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c 630{
bb8c093b
CH		 631 struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
632 struct iwl3945_queue *q = &txq->q;
633 struct iwl3945_tfd_frame *tfd;
b481de9c 634 u32 *control_flags;
bb8c093b 635 struct iwl3945_cmd *out_cmd;
b481de9c
ZY		 636 u32 idx;
637 u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
638 dma_addr_t phys_addr;
639 int pad;
640 u16 count;
641 int ret;
642 unsigned long flags;
643
644 /* If any of the command structures end up being larger than
645 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
646 * we will need to increase the size of the TFD entries */
647 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
648 !(cmd->meta.flags & CMD_SIZE_HUGE));
649
c342a1b9
GG		 650
651 if (iwl3945_is_rfkill(priv)) {
652 IWL_DEBUG_INFO("Not sending command - RF KILL");
653 return -EIO;
654 }
655
bb8c093b 656 if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
b481de9c
ZY		 657 IWL_ERROR("No space for Tx\n");
658 return -ENOSPC;
659 }
660
661 spin_lock_irqsave(&priv->hcmd_lock, flags);
662
fc4b6853 663 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY		 664 memset(tfd, 0, sizeof(*tfd));
665
666 control_flags = (u32 *) tfd;
667
fc4b6853 668 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
b481de9c
ZY		 669 out_cmd = &txq->cmd[idx];
670
671 out_cmd->hdr.cmd = cmd->id;
672 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
673 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
674
675 /* At this point, the out_cmd now has all of the incoming cmd
676 * information */
677
678 out_cmd->hdr.flags = 0;
679 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
fc4b6853 680 INDEX_TO_SEQ(q->write_ptr));
b481de9c
ZY		 681 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
682 out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
683
684 phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
bb8c093b
CH		 685 offsetof(struct iwl3945_cmd, hdr);
686 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
b481de9c
ZY		 687
688 pad = U32_PAD(cmd->len);
689 count = TFD_CTL_COUNT_GET(*control_flags);
690 *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
691
692 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
693 "%d bytes at %d[%d]:%d\n",
694 get_cmd_string(out_cmd->hdr.cmd),
695 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
fc4b6853 696 fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
b481de9c
ZY		 697
698 txq->need_update = 1;
6440adb5
CB		 699
700 /* Increment and update queue's write index */
c54b679d 701 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
bb8c093b 702 ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 703
704 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
705 return ret ? ret : idx;
706}
707
bb8c093b 708static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c
ZY		 709{
710 int ret;
711
712 BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
713
714 /* An asynchronous command can not expect an SKB to be set. */
715 BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
716
717 /* An asynchronous command MUST have a callback. */
718 BUG_ON(!cmd->meta.u.callback);
719
720 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
721 return -EBUSY;
722
bb8c093b 723 ret = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c 724 if (ret < 0) {
bb8c093b 725 IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
b481de9c
ZY		 726 get_cmd_string(cmd->id), ret);
727 return ret;
728 }
729 return 0;
730}
731
bb8c093b 732static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c
ZY		 733{
734 int cmd_idx;
735 int ret;
b481de9c
ZY		 736
737 BUG_ON(cmd->meta.flags & CMD_ASYNC);
738
739 /* A synchronous command can not have a callback set. */
740 BUG_ON(cmd->meta.u.callback != NULL);
741
e5472978 742 if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) {
b481de9c
ZY		 743 IWL_ERROR("Error sending %s: Already sending a host command\n",
744 get_cmd_string(cmd->id));
e5472978
TW		 745 ret = -EBUSY;
746 goto out;
b481de9c
ZY		 747 }
748
749 set_bit(STATUS_HCMD_ACTIVE, &priv->status);
750
751 if (cmd->meta.flags & CMD_WANT_SKB)
752 cmd->meta.source = &cmd->meta;
753
bb8c093b 754 cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c
ZY		 755 if (cmd_idx < 0) {
756 ret = cmd_idx;
bb8c093b 757 IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
b481de9c
ZY		 758 get_cmd_string(cmd->id), ret);
759 goto out;
760 }
761
762 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
763 !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
764 HOST_COMPLETE_TIMEOUT);
765 if (!ret) {
766 if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
767 IWL_ERROR("Error sending %s: time out after %dms.\n",
768 get_cmd_string(cmd->id),
769 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
770
771 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
772 ret = -ETIMEDOUT;
773 goto cancel;
774 }
775 }
776
777 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
778 IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
779 get_cmd_string(cmd->id));
780 ret = -ECANCELED;
781 goto fail;
782 }
783 if (test_bit(STATUS_FW_ERROR, &priv->status)) {
784 IWL_DEBUG_INFO("Command %s failed: FW Error\n",
785 get_cmd_string(cmd->id));
786 ret = -EIO;
787 goto fail;
788 }
789 if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
790 IWL_ERROR("Error: Response NULL in '%s'\n",
791 get_cmd_string(cmd->id));
792 ret = -EIO;
793 goto out;
794 }
795
796 ret = 0;
797 goto out;
798
799cancel:
800 if (cmd->meta.flags & CMD_WANT_SKB) {
bb8c093b 801 struct iwl3945_cmd *qcmd;
b481de9c
ZY		 802
803 /* Cancel the CMD_WANT_SKB flag for the cmd in the
804 * TX cmd queue. Otherwise in case the cmd comes
805 * in later, it will possibly set an invalid
806 * address (cmd->meta.source). */
807 qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
808 qcmd->meta.flags &= ~CMD_WANT_SKB;
809 }
810fail:
811 if (cmd->meta.u.skb) {
812 dev_kfree_skb_any(cmd->meta.u.skb);
813 cmd->meta.u.skb = NULL;
814 }
815out:
e5472978 816 clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status);
b481de9c
ZY		 817 return ret;
818}
819
bb8c093b 820int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c 821{
b481de9c 822 if (cmd->meta.flags & CMD_ASYNC)
bb8c093b 823 return iwl3945_send_cmd_async(priv, cmd);
b481de9c 824
bb8c093b 825 return iwl3945_send_cmd_sync(priv, cmd);
b481de9c
ZY		 826}
827
bb8c093b 828int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
b481de9c 829{
bb8c093b 830 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 831 .id = id,
832 .len = len,
833 .data = data,
834 };
835
bb8c093b 836 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 837}
838
bb8c093b 839static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
b481de9c 840{
bb8c093b 841 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 842 .id = id,
843 .len = sizeof(val),
844 .data = &val,
845 };
846
bb8c093b 847 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 848}
849
bb8c093b 850int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
b481de9c 851{
bb8c093b 852 return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
b481de9c
ZY		 853}
854
b481de9c 855/**
bb8c093b 856 * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
8318d78a
JB		 857 * @band: 2.4 or 5 GHz band
858 * @channel: Any channel valid for the requested band
b481de9c 859
8318d78a 860 * In addition to setting the staging RXON, priv->band is also set.
b481de9c
ZY		 861 *
862 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
8318d78a 863 * in the staging RXON flag structure based on the band
b481de9c 864 */
8318d78a
JB		 865static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv,
866 enum ieee80211_band band,
867 u16 channel)
b481de9c 868{
8318d78a 869 if (!iwl3945_get_channel_info(priv, band, channel)) {
b481de9c 870 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
8318d78a 871 channel, band);
b481de9c
ZY		 872 return -EINVAL;
873 }
874
875 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
8318d78a 876 (priv->band == band))
b481de9c
ZY		 877 return 0;
878
879 priv->staging_rxon.channel = cpu_to_le16(channel);
8318d78a 880 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 881 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
882 else
883 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
884
8318d78a 885 priv->band = band;
b481de9c 886
8318d78a 887 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
b481de9c
ZY		 888
889 return 0;
890}
891
892/**
bb8c093b 893 * iwl3945_check_rxon_cmd - validate RXON structure is valid
b481de9c
ZY		 894 *
895 * NOTE: This is really only useful during development and can eventually
896 * be #ifdef'd out once the driver is stable and folks aren't actively
897 * making changes
898 */
bb8c093b 899static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon)
b481de9c
ZY		 900{
901 int error = 0;
902 int counter = 1;
903
904 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
905 error |= le32_to_cpu(rxon->flags &
906 (RXON_FLG_TGJ_NARROW_BAND_MSK |
907 RXON_FLG_RADAR_DETECT_MSK));
908 if (error)
909 IWL_WARNING("check 24G fields %d | %d\n",
910 counter++, error);
911 } else {
912 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
913 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
914 if (error)
915 IWL_WARNING("check 52 fields %d | %d\n",
916 counter++, error);
917 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
918 if (error)
919 IWL_WARNING("check 52 CCK %d | %d\n",
920 counter++, error);
921 }
922 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
923 if (error)
924 IWL_WARNING("check mac addr %d | %d\n", counter++, error);
925
926 /* make sure basic rates 6Mbps and 1Mbps are supported */
927 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
928 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
929 if (error)
930 IWL_WARNING("check basic rate %d | %d\n", counter++, error);
931
932 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
933 if (error)
934 IWL_WARNING("check assoc id %d | %d\n", counter++, error);
935
936 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
937 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
938 if (error)
939 IWL_WARNING("check CCK and short slot %d | %d\n",
940 counter++, error);
941
942 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
943 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
944 if (error)
945 IWL_WARNING("check CCK & auto detect %d | %d\n",
946 counter++, error);
947
948 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
949 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
950 if (error)
951 IWL_WARNING("check TGG and auto detect %d | %d\n",
952 counter++, error);
953
954 if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
955 error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
956 RXON_FLG_ANT_A_MSK)) == 0);
957 if (error)
958 IWL_WARNING("check antenna %d %d\n", counter++, error);
959
960 if (error)
961 IWL_WARNING("Tuning to channel %d\n",
962 le16_to_cpu(rxon->channel));
963
964 if (error) {
bb8c093b 965 IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
b481de9c
ZY		 966 return -1;
967 }
968 return 0;
969}
970
971/**
9fbab516 972 * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
01ebd063 973 * @priv: staging_rxon is compared to active_rxon
b481de9c 974 *
9fbab516
BC		 975 * If the RXON structure is changing enough to require a new tune,
976 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
977 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
b481de9c 978 */
bb8c093b 979static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
b481de9c
ZY		 980{
981
982 /* These items are only settable from the full RXON command */
983 if (!(priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ||
984 compare_ether_addr(priv->staging_rxon.bssid_addr,
985 priv->active_rxon.bssid_addr) ||
986 compare_ether_addr(priv->staging_rxon.node_addr,
987 priv->active_rxon.node_addr) ||
988 compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
989 priv->active_rxon.wlap_bssid_addr) ||
990 (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
991 (priv->staging_rxon.channel != priv->active_rxon.channel) ||
992 (priv->staging_rxon.air_propagation !=
993 priv->active_rxon.air_propagation) ||
994 (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
995 return 1;
996
997 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
998 * be updated with the RXON_ASSOC command -- however only some
999 * flag transitions are allowed using RXON_ASSOC */
1000
1001 /* Check if we are not switching bands */
1002 if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
1003 (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
1004 return 1;
1005
1006 /* Check if we are switching association toggle */
1007 if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
1008 (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
1009 return 1;
1010
1011 return 0;
1012}
1013
bb8c093b 1014static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
b481de9c
ZY		 1015{
1016 int rc = 0;
bb8c093b
CH		 1017 struct iwl3945_rx_packet *res = NULL;
1018 struct iwl3945_rxon_assoc_cmd rxon_assoc;
1019 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 1020 .id = REPLY_RXON_ASSOC,
1021 .len = sizeof(rxon_assoc),
1022 .meta.flags = CMD_WANT_SKB,
1023 .data = &rxon_assoc,
1024 };
bb8c093b
CH		 1025 const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
1026 const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
b481de9c
ZY		 1027
1028 if ((rxon1->flags == rxon2->flags) &&
1029 (rxon1->filter_flags == rxon2->filter_flags) &&
1030 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1031 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1032 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
1033 return 0;
1034 }
1035
1036 rxon_assoc.flags = priv->staging_rxon.flags;
1037 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1038 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1039 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1040 rxon_assoc.reserved = 0;
1041
bb8c093b 1042 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 1043 if (rc)
1044 return rc;
1045
bb8c093b 1046 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1047 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1048 IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
1049 rc = -EIO;
1050 }
1051
1052 priv->alloc_rxb_skb--;
1053 dev_kfree_skb_any(cmd.meta.u.skb);
1054
1055 return rc;
1056}
1057
1058/**
bb8c093b 1059 * iwl3945_commit_rxon - commit staging_rxon to hardware
b481de9c 1060 *
01ebd063 1061 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
ZY		 1062 * the active_rxon structure is updated with the new data. This
1063 * function correctly transitions out of the RXON_ASSOC_MSK state if
1064 * a HW tune is required based on the RXON structure changes.
1065 */
bb8c093b 1066static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
b481de9c
ZY		 1067{
1068 /* cast away the const for active_rxon in this function */
bb8c093b 1069 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
b481de9c 1070 int rc = 0;
0795af57 1071 DECLARE_MAC_BUF(mac);
b481de9c 1072
bb8c093b 1073 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 1074 return -1;
1075
1076 /* always get timestamp with Rx frame */
1077 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
1078
1079 /* select antenna */
1080 priv->staging_rxon.flags &=
1081 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1082 priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
1083
bb8c093b 1084 rc = iwl3945_check_rxon_cmd(&priv->staging_rxon);
b481de9c
ZY		 1085 if (rc) {
1086 IWL_ERROR("Invalid RXON configuration. Not committing.\n");
1087 return -EINVAL;
1088 }
1089
1090 /* If we don't need to send a full RXON, we can use
bb8c093b 1091 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 1092 * and other flags for the current radio configuration. */
bb8c093b
CH		 1093 if (!iwl3945_full_rxon_required(priv)) {
1094 rc = iwl3945_send_rxon_assoc(priv);
b481de9c
ZY		 1095 if (rc) {
1096 IWL_ERROR("Error setting RXON_ASSOC "
1097 "configuration (%d).\n", rc);
1098 return rc;
1099 }
1100
1101 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1102
1103 return 0;
1104 }
1105
1106 /* If we are currently associated and the new config requires
1107 * an RXON_ASSOC and the new config wants the associated mask enabled,
1108 * we must clear the associated from the active configuration
1109 * before we apply the new config */
bb8c093b 1110 if (iwl3945_is_associated(priv) &&
b481de9c
ZY		 1111 (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
1112 IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
1113 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1114
bb8c093b
CH		 1115 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
1116 sizeof(struct iwl3945_rxon_cmd),
b481de9c
ZY		 1117 &priv->active_rxon);
1118
1119 /* If the mask clearing failed then we set
1120 * active_rxon back to what it was previously */
1121 if (rc) {
1122 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1123 IWL_ERROR("Error clearing ASSOC_MSK on current "
1124 "configuration (%d).\n", rc);
1125 return rc;
1126 }
b481de9c
ZY		 1127 }
1128
1129 IWL_DEBUG_INFO("Sending RXON\n"
1130 "* with%s RXON_FILTER_ASSOC_MSK\n"
1131 "* channel = %d\n"
0795af57 1132 "* bssid = %s\n",
b481de9c
ZY		 1133 ((priv->staging_rxon.filter_flags &
1134 RXON_FILTER_ASSOC_MSK) ? "" : "out"),
1135 le16_to_cpu(priv->staging_rxon.channel),
0795af57 1136 print_mac(mac, priv->staging_rxon.bssid_addr));
b481de9c
ZY		 1137
1138 /* Apply the new configuration */
bb8c093b
CH		 1139 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
1140 sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
b481de9c
ZY		 1141 if (rc) {
1142 IWL_ERROR("Error setting new configuration (%d).\n", rc);
1143 return rc;
1144 }
1145
1146 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1147
bb8c093b 1148 iwl3945_clear_stations_table(priv);
556f8db7 1149
b481de9c
ZY		 1150 /* If we issue a new RXON command which required a tune then we must
1151 * send a new TXPOWER command or we won't be able to Tx any frames */
bb8c093b 1152 rc = iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 1153 if (rc) {
1154 IWL_ERROR("Error setting Tx power (%d).\n", rc);
1155 return rc;
1156 }
1157
1158 /* Add the broadcast address so we can send broadcast frames */
bb8c093b 1159 if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
b481de9c
ZY		 1160 IWL_INVALID_STATION) {
1161 IWL_ERROR("Error adding BROADCAST address for transmit.\n");
1162 return -EIO;
1163 }
1164
1165 /* If we have set the ASSOC_MSK and we are in BSS mode then
1166 * add the IWL_AP_ID to the station rate table */
bb8c093b 1167 if (iwl3945_is_associated(priv) &&
b481de9c 1168 (priv->iw_mode == IEEE80211_IF_TYPE_STA))
bb8c093b 1169 if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
b481de9c
ZY		 1170 == IWL_INVALID_STATION) {
1171 IWL_ERROR("Error adding AP address for transmit.\n");
1172 return -EIO;
1173 }
1174
8318d78a 1175 /* Init the hardware's rate fallback order based on the band */
b481de9c
ZY		 1176 rc = iwl3945_init_hw_rate_table(priv);
1177 if (rc) {
1178 IWL_ERROR("Error setting HW rate table: %02X\n", rc);
1179 return -EIO;
1180 }
1181
1182 return 0;
1183}
1184
bb8c093b 1185static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
b481de9c 1186{
bb8c093b 1187 struct iwl3945_bt_cmd bt_cmd = {
b481de9c
ZY		 1188 .flags = 3,
1189 .lead_time = 0xAA,
1190 .max_kill = 1,
1191 .kill_ack_mask = 0,
1192 .kill_cts_mask = 0,
1193 };
1194
bb8c093b
CH		 1195 return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1196 sizeof(struct iwl3945_bt_cmd), &bt_cmd);
b481de9c
ZY		 1197}
1198
bb8c093b 1199static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
b481de9c
ZY		 1200{
1201 int rc = 0;
bb8c093b
CH		 1202 struct iwl3945_rx_packet *res;
1203 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 1204 .id = REPLY_SCAN_ABORT_CMD,
1205 .meta.flags = CMD_WANT_SKB,
1206 };
1207
1208 /* If there isn't a scan actively going on in the hardware
1209 * then we are in between scan bands and not actually
1210 * actively scanning, so don't send the abort command */
1211 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
1212 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1213 return 0;
1214 }
1215
bb8c093b 1216 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 1217 if (rc) {
1218 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1219 return rc;
1220 }
1221
bb8c093b 1222 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1223 if (res->u.status != CAN_ABORT_STATUS) {
1224 /* The scan abort will return 1 for success or
1225 * 2 for "failure". A failure condition can be
1226 * due to simply not being in an active scan which
1227 * can occur if we send the scan abort before we
1228 * the microcode has notified us that a scan is
1229 * completed. */
1230 IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
1231 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1232 clear_bit(STATUS_SCAN_HW, &priv->status);
1233 }
1234
1235 dev_kfree_skb_any(cmd.meta.u.skb);
1236
1237 return rc;
1238}
1239
bb8c093b
CH		 1240static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
1241 struct iwl3945_cmd *cmd,
b481de9c
ZY		 1242 struct sk_buff *skb)
1243{
1244 return 1;
1245}
1246
1247/*
1248 * CARD_STATE_CMD
1249 *
9fbab516 1250 * Use: Sets the device's internal card state to enable, disable, or halt
b481de9c
ZY		 1251 *
1252 * When in the 'enable' state the card operates as normal.
1253 * When in the 'disable' state, the card enters into a low power mode.
1254 * When in the 'halt' state, the card is shut down and must be fully
1255 * restarted to come back on.
1256 */
bb8c093b 1257static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
b481de9c 1258{
bb8c093b 1259 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 1260 .id = REPLY_CARD_STATE_CMD,
1261 .len = sizeof(u32),
1262 .data = &flags,
1263 .meta.flags = meta_flag,
1264 };
1265
1266 if (meta_flag & CMD_ASYNC)
bb8c093b 1267 cmd.meta.u.callback = iwl3945_card_state_sync_callback;
b481de9c 1268
bb8c093b 1269 return iwl3945_send_cmd(priv, &cmd);
b481de9c
ZY		 1270}
1271
bb8c093b
CH		 1272static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
1273 struct iwl3945_cmd *cmd, struct sk_buff *skb)
b481de9c 1274{
bb8c093b 1275 struct iwl3945_rx_packet *res = NULL;
b481de9c
ZY		 1276
1277 if (!skb) {
1278 IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
1279 return 1;
1280 }
1281
bb8c093b 1282 res = (struct iwl3945_rx_packet *)skb->data;
b481de9c
ZY		 1283 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1284 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1285 res->hdr.flags);
1286 return 1;
1287 }
1288
1289 switch (res->u.add_sta.status) {
1290 case ADD_STA_SUCCESS_MSK:
1291 break;
1292 default:
1293 break;
1294 }
1295
1296 /* We didn't cache the SKB; let the caller free it */
1297 return 1;
1298}
1299
bb8c093b
CH		 1300int iwl3945_send_add_station(struct iwl3945_priv *priv,
1301 struct iwl3945_addsta_cmd *sta, u8 flags)
b481de9c 1302{
bb8c093b 1303 struct iwl3945_rx_packet *res = NULL;
b481de9c 1304 int rc = 0;
bb8c093b 1305 struct iwl3945_host_cmd cmd = {
b481de9c 1306 .id = REPLY_ADD_STA,
bb8c093b 1307 .len = sizeof(struct iwl3945_addsta_cmd),
b481de9c
ZY		 1308 .meta.flags = flags,
1309 .data = sta,
1310 };
1311
1312 if (flags & CMD_ASYNC)
bb8c093b 1313 cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
b481de9c
ZY		 1314 else
1315 cmd.meta.flags |= CMD_WANT_SKB;
1316
bb8c093b 1317 rc = iwl3945_send_cmd(priv, &cmd);
b481de9c
ZY		 1318
1319 if (rc || (flags & CMD_ASYNC))
1320 return rc;
1321
bb8c093b 1322 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1323 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1324 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1325 res->hdr.flags);
1326 rc = -EIO;
1327 }
1328
1329 if (rc == 0) {
1330 switch (res->u.add_sta.status) {
1331 case ADD_STA_SUCCESS_MSK:
1332 IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
1333 break;
1334 default:
1335 rc = -EIO;
1336 IWL_WARNING("REPLY_ADD_STA failed\n");
1337 break;
1338 }
1339 }
1340
1341 priv->alloc_rxb_skb--;
1342 dev_kfree_skb_any(cmd.meta.u.skb);
1343
1344 return rc;
1345}
1346
bb8c093b 1347static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
b481de9c
ZY		 1348 struct ieee80211_key_conf *keyconf,
1349 u8 sta_id)
1350{
1351 unsigned long flags;
1352 __le16 key_flags = 0;
1353
1354 switch (keyconf->alg) {
1355 case ALG_CCMP:
1356 key_flags |= STA_KEY_FLG_CCMP;
1357 key_flags |= cpu_to_le16(
1358 keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
1359 key_flags &= ~STA_KEY_FLG_INVALID;
1360 break;
1361 case ALG_TKIP:
1362 case ALG_WEP:
b481de9c
ZY		 1363 default:
1364 return -EINVAL;
1365 }
1366 spin_lock_irqsave(&priv->sta_lock, flags);
1367 priv->stations[sta_id].keyinfo.alg = keyconf->alg;
1368 priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
1369 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
1370 keyconf->keylen);
1371
1372 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
1373 keyconf->keylen);
1374 priv->stations[sta_id].sta.key.key_flags = key_flags;
1375 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1376 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1377
1378 spin_unlock_irqrestore(&priv->sta_lock, flags);
1379
1380 IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
bb8c093b 1381 iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY		 1382 return 0;
1383}
1384
bb8c093b 1385static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
b481de9c
ZY		 1386{
1387 unsigned long flags;
1388
1389 spin_lock_irqsave(&priv->sta_lock, flags);
bb8c093b
CH		 1390 memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
1391 memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl3945_keyinfo));
b481de9c
ZY		 1392 priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
1393 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1394 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1395 spin_unlock_irqrestore(&priv->sta_lock, flags);
1396
1397 IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
bb8c093b 1398 iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY		 1399 return 0;
1400}
1401
bb8c093b 1402static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
b481de9c
ZY		 1403{
1404 struct list_head *element;
1405
1406 IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
1407 priv->frames_count);
1408
1409 while (!list_empty(&priv->free_frames)) {
1410 element = priv->free_frames.next;
1411 list_del(element);
bb8c093b 1412 kfree(list_entry(element, struct iwl3945_frame, list));
b481de9c
ZY		 1413 priv->frames_count--;
1414 }
1415
1416 if (priv->frames_count) {
1417 IWL_WARNING("%d frames still in use. Did we lose one?\n",
1418 priv->frames_count);
1419 priv->frames_count = 0;
1420 }
1421}
1422
bb8c093b 1423static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
b481de9c 1424{
bb8c093b 1425 struct iwl3945_frame *frame;
b481de9c
ZY		 1426 struct list_head *element;
1427 if (list_empty(&priv->free_frames)) {
1428 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
1429 if (!frame) {
1430 IWL_ERROR("Could not allocate frame!\n");
1431 return NULL;
1432 }
1433
1434 priv->frames_count++;
1435 return frame;
1436 }
1437
1438 element = priv->free_frames.next;
1439 list_del(element);
bb8c093b 1440 return list_entry(element, struct iwl3945_frame, list);
b481de9c
ZY		 1441}
1442
bb8c093b 1443static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
b481de9c
ZY		 1444{
1445 memset(frame, 0, sizeof(*frame));
1446 list_add(&frame->list, &priv->free_frames);
1447}
1448
bb8c093b 1449unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
b481de9c
ZY		 1450 struct ieee80211_hdr *hdr,
1451 const u8 *dest, int left)
1452{
1453
bb8c093b 1454 if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
b481de9c
ZY		 1455 ((priv->iw_mode != IEEE80211_IF_TYPE_IBSS) &&
1456 (priv->iw_mode != IEEE80211_IF_TYPE_AP)))
1457 return 0;
1458
1459 if (priv->ibss_beacon->len > left)
1460 return 0;
1461
1462 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
1463
1464 return priv->ibss_beacon->len;
1465}
1466
bb8c093b 1467static u8 iwl3945_rate_get_lowest_plcp(int rate_mask)
b481de9c
ZY		 1468{
1469 u8 i;
1470
1471 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
bb8c093b 1472 i = iwl3945_rates[i].next_ieee) {
b481de9c 1473 if (rate_mask & (1 << i))
bb8c093b 1474 return iwl3945_rates[i].plcp;
b481de9c
ZY		 1475 }
1476
1477 return IWL_RATE_INVALID;
1478}
1479
bb8c093b 1480static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
b481de9c 1481{
bb8c093b 1482 struct iwl3945_frame *frame;
b481de9c
ZY		 1483 unsigned int frame_size;
1484 int rc;
1485 u8 rate;
1486
bb8c093b 1487 frame = iwl3945_get_free_frame(priv);
b481de9c
ZY		 1488
1489 if (!frame) {
1490 IWL_ERROR("Could not obtain free frame buffer for beacon "
1491 "command.\n");
1492 return -ENOMEM;
1493 }
1494
1495 if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) {
bb8c093b 1496 rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic &
b481de9c
ZY		 1497 0xFF0);
1498 if (rate == IWL_INVALID_RATE)
1499 rate = IWL_RATE_6M_PLCP;
1500 } else {
bb8c093b 1501 rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic & 0xF);
b481de9c
ZY		 1502 if (rate == IWL_INVALID_RATE)
1503 rate = IWL_RATE_1M_PLCP;
1504 }
1505
bb8c093b 1506 frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 1507
bb8c093b 1508 rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY		 1509 &frame->u.cmd[0]);
1510
bb8c093b 1511 iwl3945_free_frame(priv, frame);
b481de9c
ZY		 1512
1513 return rc;
1514}
1515
1516/******************************************************************************
1517 *
1518 * EEPROM related functions
1519 *
1520 ******************************************************************************/
1521
bb8c093b 1522static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
b481de9c
ZY		 1523{
1524 memcpy(mac, priv->eeprom.mac_address, 6);
1525}
1526
74a3a250
RC		 1527/*
1528 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
1529 * embedded controller) as EEPROM reader; each read is a series of pulses
1530 * to/from the EEPROM chip, not a single event, so even reads could conflict
1531 * if they weren't arbitrated by some ownership mechanism. Here, the driver
1532 * simply claims ownership, which should be safe when this function is called
1533 * (i.e. before loading uCode!).
1534 */
1535static inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv)
1536{
1537 _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
1538 return 0;
1539}
1540
b481de9c 1541/**
bb8c093b 1542 * iwl3945_eeprom_init - read EEPROM contents
b481de9c 1543 *
6440adb5 1544 * Load the EEPROM contents from adapter into priv->eeprom
b481de9c
ZY		 1545 *
1546 * NOTE: This routine uses the non-debug IO access functions.
1547 */
bb8c093b 1548int iwl3945_eeprom_init(struct iwl3945_priv *priv)
b481de9c 1549{
58ff6d4d 1550 u16 *e = (u16 *)&priv->eeprom;
bb8c093b 1551 u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
b481de9c
ZY		 1552 u32 r;
1553 int sz = sizeof(priv->eeprom);
1554 int rc;
1555 int i;
1556 u16 addr;
1557
1558 /* The EEPROM structure has several padding buffers within it
1559 * and when adding new EEPROM maps is subject to programmer errors
1560 * which may be very difficult to identify without explicitly
1561 * checking the resulting size of the eeprom map. */
1562 BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
1563
1564 if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
1565 IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp);
1566 return -ENOENT;
1567 }
1568
6440adb5 1569 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
bb8c093b 1570 rc = iwl3945_eeprom_acquire_semaphore(priv);
b481de9c 1571 if (rc < 0) {
91e17473 1572 IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
b481de9c
ZY		 1573 return -ENOENT;
1574 }
1575
1576 /* eeprom is an array of 16bit values */
1577 for (addr = 0; addr < sz; addr += sizeof(u16)) {
bb8c093b
CH		 1578 _iwl3945_write32(priv, CSR_EEPROM_REG, addr << 1);
1579 _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
b481de9c
ZY		 1580
1581 for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
1582 i += IWL_EEPROM_ACCESS_DELAY) {
bb8c093b 1583 r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
b481de9c
ZY		 1584 if (r & CSR_EEPROM_REG_READ_VALID_MSK)
1585 break;
1586 udelay(IWL_EEPROM_ACCESS_DELAY);
1587 }
1588
1589 if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) {
1590 IWL_ERROR("Time out reading EEPROM[%d]", addr);
1591 return -ETIMEDOUT;
1592 }
58ff6d4d 1593 e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
b481de9c
ZY		 1594 }
1595
1596 return 0;
1597}
1598
bb8c093b 1599static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
b481de9c
ZY		 1600{
1601 if (priv->hw_setting.shared_virt)
1602 pci_free_consistent(priv->pci_dev,
bb8c093b 1603 sizeof(struct iwl3945_shared),
b481de9c
ZY		 1604 priv->hw_setting.shared_virt,
1605 priv->hw_setting.shared_phys);
1606}
1607
1608/**
bb8c093b 1609 * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
b481de9c
ZY		 1610 *
1611 * return : set the bit for each supported rate insert in ie
1612 */
bb8c093b 1613static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
c7c46676 1614 u16 basic_rate, int *left)
b481de9c
ZY		 1615{
1616 u16 ret_rates = 0, bit;
1617 int i;
c7c46676
TW		 1618 u8 *cnt = ie;
1619 u8 *rates = ie + 1;
b481de9c
ZY		 1620
1621 for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
1622 if (bit & supported_rate) {
1623 ret_rates |= bit;
bb8c093b 1624 rates[*cnt] = iwl3945_rates[i].ieee |
c7c46676
TW		 1625 ((bit & basic_rate) ? 0x80 : 0x00);
1626 (*cnt)++;
1627 (*left)--;
1628 if ((*left <= 0) ||
1629 (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
b481de9c
ZY		 1630 break;
1631 }
1632 }
1633
1634 return ret_rates;
1635}
1636
1637/**
bb8c093b 1638 * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
b481de9c 1639 */
bb8c093b 1640static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
b481de9c
ZY		 1641 struct ieee80211_mgmt *frame,
1642 int left, int is_direct)
1643{
1644 int len = 0;
1645 u8 *pos = NULL;
c7c46676 1646 u16 active_rates, ret_rates, cck_rates;
b481de9c
ZY		 1647
1648 /* Make sure there is enough space for the probe request,
1649 * two mandatory IEs and the data */
1650 left -= 24;
1651 if (left < 0)
1652 return 0;
1653 len += 24;
1654
1655 frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
bb8c093b 1656 memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
b481de9c 1657 memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
bb8c093b 1658 memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
b481de9c
ZY		 1659 frame->seq_ctrl = 0;
1660
1661 /* fill in our indirect SSID IE */
1662 /* ...next IE... */
1663
1664 left -= 2;
1665 if (left < 0)
1666 return 0;
1667 len += 2;
1668 pos = &(frame->u.probe_req.variable[0]);
1669 *pos++ = WLAN_EID_SSID;
1670 *pos++ = 0;
1671
1672 /* fill in our direct SSID IE... */
1673 if (is_direct) {
1674 /* ...next IE... */
1675 left -= 2 + priv->essid_len;
1676 if (left < 0)
1677 return 0;
1678 /* ... fill it in... */
1679 *pos++ = WLAN_EID_SSID;
1680 *pos++ = priv->essid_len;
1681 memcpy(pos, priv->essid, priv->essid_len);
1682 pos += priv->essid_len;
1683 len += 2 + priv->essid_len;
1684 }
1685
1686 /* fill in supported rate */
1687 /* ...next IE... */
1688 left -= 2;
1689 if (left < 0)
1690 return 0;
c7c46676 1691
b481de9c
ZY		 1692 /* ... fill it in... */
1693 *pos++ = WLAN_EID_SUPP_RATES;
1694 *pos = 0;
c7c46676
TW		 1695
1696 priv->active_rate = priv->rates_mask;
1697 active_rates = priv->active_rate;
b481de9c
ZY		 1698 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1699
c7c46676 1700 cck_rates = IWL_CCK_RATES_MASK & active_rates;
bb8c093b 1701 ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
c7c46676
TW		 1702 priv->active_rate_basic, &left);
1703 active_rates &= ~ret_rates;
1704
bb8c093b 1705 ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676
TW		 1706 priv->active_rate_basic, &left);
1707 active_rates &= ~ret_rates;
1708
b481de9c
ZY		 1709 len += 2 + *pos;
1710 pos += (*pos) + 1;
c7c46676 1711 if (active_rates == 0)
b481de9c
ZY		 1712 goto fill_end;
1713
1714 /* fill in supported extended rate */
1715 /* ...next IE... */
1716 left -= 2;
1717 if (left < 0)
1718 return 0;
1719 /* ... fill it in... */
1720 *pos++ = WLAN_EID_EXT_SUPP_RATES;
1721 *pos = 0;
bb8c093b 1722 iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676 1723 priv->active_rate_basic, &left);
b481de9c
ZY		 1724 if (*pos > 0)
1725 len += 2 + *pos;
1726
1727 fill_end:
1728 return (u16)len;
1729}
1730
1731/*
1732 * QoS support
1733*/
bb8c093b
CH		 1734static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
1735 struct iwl3945_qosparam_cmd *qos)
b481de9c
ZY		 1736{
1737
bb8c093b
CH		 1738 return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
1739 sizeof(struct iwl3945_qosparam_cmd), qos);
b481de9c
ZY		 1740}
1741
bb8c093b 1742static void iwl3945_reset_qos(struct iwl3945_priv *priv)
b481de9c
ZY		 1743{
1744 u16 cw_min = 15;
1745 u16 cw_max = 1023;
1746 u8 aifs = 2;
1747 u8 is_legacy = 0;
1748 unsigned long flags;
1749 int i;
1750
1751 spin_lock_irqsave(&priv->lock, flags);
1752 priv->qos_data.qos_active = 0;
1753
1754 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
1755 if (priv->qos_data.qos_enable)
1756 priv->qos_data.qos_active = 1;
1757 if (!(priv->active_rate & 0xfff0)) {
1758 cw_min = 31;
1759 is_legacy = 1;
1760 }
1761 } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
1762 if (priv->qos_data.qos_enable)
1763 priv->qos_data.qos_active = 1;
1764 } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
1765 cw_min = 31;
1766 is_legacy = 1;
1767 }
1768
1769 if (priv->qos_data.qos_active)
1770 aifs = 3;
1771
1772 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
1773 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
1774 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
1775 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
1776 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
1777
1778 if (priv->qos_data.qos_active) {
1779 i = 1;
1780 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
1781 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
1782 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
1783 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
1784 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1785
1786 i = 2;
1787 priv->qos_data.def_qos_parm.ac[i].cw_min =
1788 cpu_to_le16((cw_min + 1) / 2 - 1);
1789 priv->qos_data.def_qos_parm.ac[i].cw_max =
1790 cpu_to_le16(cw_max);
1791 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1792 if (is_legacy)
1793 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1794 cpu_to_le16(6016);
1795 else
1796 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1797 cpu_to_le16(3008);
1798 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1799
1800 i = 3;
1801 priv->qos_data.def_qos_parm.ac[i].cw_min =
1802 cpu_to_le16((cw_min + 1) / 4 - 1);
1803 priv->qos_data.def_qos_parm.ac[i].cw_max =
1804 cpu_to_le16((cw_max + 1) / 2 - 1);
1805 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1806 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1807 if (is_legacy)
1808 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1809 cpu_to_le16(3264);
1810 else
1811 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1812 cpu_to_le16(1504);
1813 } else {
1814 for (i = 1; i < 4; i++) {
1815 priv->qos_data.def_qos_parm.ac[i].cw_min =
1816 cpu_to_le16(cw_min);
1817 priv->qos_data.def_qos_parm.ac[i].cw_max =
1818 cpu_to_le16(cw_max);
1819 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
1820 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
1821 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1822 }
1823 }
1824 IWL_DEBUG_QOS("set QoS to default \n");
1825
1826 spin_unlock_irqrestore(&priv->lock, flags);
1827}
1828
bb8c093b 1829static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
b481de9c
ZY		 1830{
1831 unsigned long flags;
1832
b481de9c
ZY		 1833 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1834 return;
1835
1836 if (!priv->qos_data.qos_enable)
1837 return;
1838
1839 spin_lock_irqsave(&priv->lock, flags);
1840 priv->qos_data.def_qos_parm.qos_flags = 0;
1841
1842 if (priv->qos_data.qos_cap.q_AP.queue_request &&
1843 !priv->qos_data.qos_cap.q_AP.txop_request)
1844 priv->qos_data.def_qos_parm.qos_flags |=
1845 QOS_PARAM_FLG_TXOP_TYPE_MSK;
1846
1847 if (priv->qos_data.qos_active)
1848 priv->qos_data.def_qos_parm.qos_flags |=
1849 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
1850
1851 spin_unlock_irqrestore(&priv->lock, flags);
1852
bb8c093b 1853 if (force || iwl3945_is_associated(priv)) {
b481de9c
ZY		 1854 IWL_DEBUG_QOS("send QoS cmd with Qos active %d \n",
1855 priv->qos_data.qos_active);
1856
bb8c093b 1857 iwl3945_send_qos_params_command(priv,
b481de9c
ZY		 1858 &(priv->qos_data.def_qos_parm));
1859 }
1860}
1861
b481de9c
ZY		 1862/*
1863 * Power management (not Tx power!) functions
1864 */
1865#define MSEC_TO_USEC 1024
1866
1867#define NOSLP __constant_cpu_to_le32(0)
1868#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK
1869#define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
1870#define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
1871 __constant_cpu_to_le32(X1), \
1872 __constant_cpu_to_le32(X2), \
1873 __constant_cpu_to_le32(X3), \
1874 __constant_cpu_to_le32(X4)}
1875
1876
1877/* default power management (not Tx power) table values */
1878/* for tim 0-10 */
bb8c093b 1879static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = {
b481de9c
ZY		 1880 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1881 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
1882 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
1883 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
1884 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
1885 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
1886};
1887
1888/* for tim > 10 */
bb8c093b 1889static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = {
b481de9c
ZY		 1890 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1891 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
1892 SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
1893 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
1894 SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
1895 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
1896 SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
1897 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
1898 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
1899 SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
1900};
1901
bb8c093b 1902int iwl3945_power_init_handle(struct iwl3945_priv *priv)
b481de9c
ZY		 1903{
1904 int rc = 0, i;
bb8c093b
CH		 1905 struct iwl3945_power_mgr *pow_data;
1906 int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC;
b481de9c
ZY		 1907 u16 pci_pm;
1908
1909 IWL_DEBUG_POWER("Initialize power \n");
1910
1911 pow_data = &(priv->power_data);
1912
1913 memset(pow_data, 0, sizeof(*pow_data));
1914
1915 pow_data->active_index = IWL_POWER_RANGE_0;
1916 pow_data->dtim_val = 0xffff;
1917
1918 memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
1919 memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
1920
1921 rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
1922 if (rc != 0)
1923 return 0;
1924 else {
bb8c093b 1925 struct iwl3945_powertable_cmd *cmd;
b481de9c
ZY		 1926
1927 IWL_DEBUG_POWER("adjust power command flags\n");
1928
1929 for (i = 0; i < IWL_POWER_AC; i++) {
1930 cmd = &pow_data->pwr_range_0[i].cmd;
1931
1932 if (pci_pm & 0x1)
1933 cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
1934 else
1935 cmd->flags |= IWL_POWER_PCI_PM_MSK;
1936 }
1937 }
1938 return rc;
1939}
1940
bb8c093b
CH		 1941static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
1942 struct iwl3945_powertable_cmd *cmd, u32 mode)
b481de9c
ZY		 1943{
1944 int rc = 0, i;
1945 u8 skip;
1946 u32 max_sleep = 0;
bb8c093b 1947 struct iwl3945_power_vec_entry *range;
b481de9c 1948 u8 period = 0;
bb8c093b 1949 struct iwl3945_power_mgr *pow_data;
b481de9c
ZY		 1950
1951 if (mode > IWL_POWER_INDEX_5) {
1952 IWL_DEBUG_POWER("Error invalid power mode \n");
1953 return -1;
1954 }
1955 pow_data = &(priv->power_data);
1956
1957 if (pow_data->active_index == IWL_POWER_RANGE_0)
1958 range = &pow_data->pwr_range_0[0];
1959 else
1960 range = &pow_data->pwr_range_1[1];
1961
bb8c093b 1962 memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
b481de9c
ZY		 1963
1964#ifdef IWL_MAC80211_DISABLE
1965 if (priv->assoc_network != NULL) {
1966 unsigned long flags;
1967
1968 period = priv->assoc_network->tim.tim_period;
1969 }
1970#endif /*IWL_MAC80211_DISABLE */
1971 skip = range[mode].no_dtim;
1972
1973 if (period == 0) {
1974 period = 1;
1975 skip = 0;
1976 }
1977
1978 if (skip == 0) {
1979 max_sleep = period;
1980 cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
1981 } else {
1982 __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
1983 max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
1984 cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
1985 }
1986
1987 for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
1988 if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
1989 cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
1990 }
1991
1992 IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
1993 IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
1994 IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
1995 IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
1996 le32_to_cpu(cmd->sleep_interval[0]),
1997 le32_to_cpu(cmd->sleep_interval[1]),
1998 le32_to_cpu(cmd->sleep_interval[2]),
1999 le32_to_cpu(cmd->sleep_interval[3]),
2000 le32_to_cpu(cmd->sleep_interval[4]));
2001
2002 return rc;
2003}
2004
bb8c093b 2005static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
b481de9c 2006{
9a62f73b 2007 u32 uninitialized_var(final_mode);
b481de9c 2008 int rc;
bb8c093b 2009 struct iwl3945_powertable_cmd cmd;
b481de9c
ZY		 2010
2011 /* If on battery, set to 3,
01ebd063 2012 * if plugged into AC power, set to CAM ("continuously aware mode"),
b481de9c
ZY		 2013 * else user level */
2014 switch (mode) {
2015 case IWL_POWER_BATTERY:
2016 final_mode = IWL_POWER_INDEX_3;
2017 break;
2018 case IWL_POWER_AC:
2019 final_mode = IWL_POWER_MODE_CAM;
2020 break;
2021 default:
2022 final_mode = mode;
2023 break;
2024 }
2025
bb8c093b 2026 iwl3945_update_power_cmd(priv, &cmd, final_mode);
b481de9c 2027
bb8c093b 2028 rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
b481de9c
ZY		 2029
2030 if (final_mode == IWL_POWER_MODE_CAM)
2031 clear_bit(STATUS_POWER_PMI, &priv->status);
2032 else
2033 set_bit(STATUS_POWER_PMI, &priv->status);
2034
2035 return rc;
2036}
2037
bb8c093b 2038int iwl3945_is_network_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
b481de9c
ZY		 2039{
2040 /* Filter incoming packets to determine if they are targeted toward
2041 * this network, discarding packets coming from ourselves */
2042 switch (priv->iw_mode) {
2043 case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */
2044 /* packets from our adapter are dropped (echo) */
2045 if (!compare_ether_addr(header->addr2, priv->mac_addr))
2046 return 0;
2047 /* {broad,multi}cast packets to our IBSS go through */
2048 if (is_multicast_ether_addr(header->addr1))
2049 return !compare_ether_addr(header->addr3, priv->bssid);
2050 /* packets to our adapter go through */
2051 return !compare_ether_addr(header->addr1, priv->mac_addr);
2052 case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */
2053 /* packets from our adapter are dropped (echo) */
2054 if (!compare_ether_addr(header->addr3, priv->mac_addr))
2055 return 0;
2056 /* {broad,multi}cast packets to our BSS go through */
2057 if (is_multicast_ether_addr(header->addr1))
2058 return !compare_ether_addr(header->addr2, priv->bssid);
2059 /* packets to our adapter go through */
2060 return !compare_ether_addr(header->addr1, priv->mac_addr);
69dc5d9d
TW		 2061 default:
2062 return 1;
b481de9c
ZY		 2063 }
2064
2065 return 1;
2066}
2067
b481de9c 2068/**
bb8c093b 2069 * iwl3945_scan_cancel - Cancel any currently executing HW scan
b481de9c
ZY		 2070 *
2071 * NOTE: priv->mutex is not required before calling this function
2072 */
bb8c093b 2073static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
b481de9c
ZY		 2074{
2075 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
2076 clear_bit(STATUS_SCANNING, &priv->status);
2077 return 0;
2078 }
2079
2080 if (test_bit(STATUS_SCANNING, &priv->status)) {
2081 if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2082 IWL_DEBUG_SCAN("Queuing scan abort.\n");
2083 set_bit(STATUS_SCAN_ABORTING, &priv->status);
2084 queue_work(priv->workqueue, &priv->abort_scan);
2085
2086 } else
2087 IWL_DEBUG_SCAN("Scan abort already in progress.\n");
2088
2089 return test_bit(STATUS_SCANNING, &priv->status);
2090 }
2091
2092 return 0;
2093}
2094
2095/**
bb8c093b 2096 * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
b481de9c
ZY		 2097 * @ms: amount of time to wait (in milliseconds) for scan to abort
2098 *
2099 * NOTE: priv->mutex must be held before calling this function
2100 */
bb8c093b 2101static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
b481de9c
ZY		 2102{
2103 unsigned long now = jiffies;
2104 int ret;
2105
bb8c093b 2106 ret = iwl3945_scan_cancel(priv);
b481de9c
ZY		 2107 if (ret && ms) {
2108 mutex_unlock(&priv->mutex);
2109 while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
2110 test_bit(STATUS_SCANNING, &priv->status))
2111 msleep(1);
2112 mutex_lock(&priv->mutex);
2113
2114 return test_bit(STATUS_SCANNING, &priv->status);
2115 }
2116
2117 return ret;
2118}
2119
bb8c093b 2120static void iwl3945_sequence_reset(struct iwl3945_priv *priv)
b481de9c
ZY		 2121{
2122 /* Reset ieee stats */
2123
2124 /* We don't reset the net_device_stats (ieee->stats) on
2125 * re-association */
2126
2127 priv->last_seq_num = -1;
2128 priv->last_frag_num = -1;
2129 priv->last_packet_time = 0;
2130
bb8c093b 2131 iwl3945_scan_cancel(priv);
b481de9c
ZY		 2132}
2133
2134#define MAX_UCODE_BEACON_INTERVAL 1024
2135#define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
2136
bb8c093b 2137static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
b481de9c
ZY		 2138{
2139 u16 new_val = 0;
2140 u16 beacon_factor = 0;
2141
2142 beacon_factor =
2143 (beacon_val + MAX_UCODE_BEACON_INTERVAL)
2144 / MAX_UCODE_BEACON_INTERVAL;
2145 new_val = beacon_val / beacon_factor;
2146
2147 return cpu_to_le16(new_val);
2148}
2149
bb8c093b 2150static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
b481de9c
ZY		 2151{
2152 u64 interval_tm_unit;
2153 u64 tsf, result;
2154 unsigned long flags;
2155 struct ieee80211_conf *conf = NULL;
2156 u16 beacon_int = 0;
2157
2158 conf = ieee80211_get_hw_conf(priv->hw);
2159
2160 spin_lock_irqsave(&priv->lock, flags);
2161 priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
2162 priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
2163
2164 priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
2165
2166 tsf = priv->timestamp1;
2167 tsf = ((tsf << 32) | priv->timestamp0);
2168
2169 beacon_int = priv->beacon_int;
2170 spin_unlock_irqrestore(&priv->lock, flags);
2171
2172 if (priv->iw_mode == IEEE80211_IF_TYPE_STA) {
2173 if (beacon_int == 0) {
2174 priv->rxon_timing.beacon_interval = cpu_to_le16(100);
2175 priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
2176 } else {
2177 priv->rxon_timing.beacon_interval =
2178 cpu_to_le16(beacon_int);
2179 priv->rxon_timing.beacon_interval =
bb8c093b 2180 iwl3945_adjust_beacon_interval(
b481de9c
ZY		 2181 le16_to_cpu(priv->rxon_timing.beacon_interval));
2182 }
2183
2184 priv->rxon_timing.atim_window = 0;
2185 } else {
2186 priv->rxon_timing.beacon_interval =
bb8c093b 2187 iwl3945_adjust_beacon_interval(conf->beacon_int);
b481de9c
ZY		 2188 /* TODO: we need to get atim_window from upper stack
2189 * for now we set to 0 */
2190 priv->rxon_timing.atim_window = 0;
2191 }
2192
2193 interval_tm_unit =
2194 (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
2195 result = do_div(tsf, interval_tm_unit);
2196 priv->rxon_timing.beacon_init_val =
2197 cpu_to_le32((u32) ((u64) interval_tm_unit - result));
2198
2199 IWL_DEBUG_ASSOC
2200 ("beacon interval %d beacon timer %d beacon tim %d\n",
2201 le16_to_cpu(priv->rxon_timing.beacon_interval),
2202 le32_to_cpu(priv->rxon_timing.beacon_init_val),
2203 le16_to_cpu(priv->rxon_timing.atim_window));
2204}
2205
bb8c093b 2206static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
b481de9c
ZY		 2207{
2208 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
2209 IWL_ERROR("APs don't scan.\n");
2210 return 0;
2211 }
2212
bb8c093b 2213 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 2214 IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
2215 return -EIO;
2216 }
2217
2218 if (test_bit(STATUS_SCANNING, &priv->status)) {
2219 IWL_DEBUG_SCAN("Scan already in progress.\n");
2220 return -EAGAIN;
2221 }
2222
2223 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2224 IWL_DEBUG_SCAN("Scan request while abort pending. "
2225 "Queuing.\n");
2226 return -EAGAIN;
2227 }
2228
2229 IWL_DEBUG_INFO("Starting scan...\n");
2230 priv->scan_bands = 2;
2231 set_bit(STATUS_SCANNING, &priv->status);
2232 priv->scan_start = jiffies;
2233 priv->scan_pass_start = priv->scan_start;
2234
2235 queue_work(priv->workqueue, &priv->request_scan);
2236
2237 return 0;
2238}
2239
bb8c093b 2240static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
b481de9c 2241{
bb8c093b 2242 struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
b481de9c
ZY		 2243
2244 if (hw_decrypt)
2245 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
2246 else
2247 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
2248
2249 return 0;
2250}
2251
8318d78a
JB		 2252static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv,
2253 enum ieee80211_band band)
b481de9c 2254{
8318d78a 2255 if (band == IEEE80211_BAND_5GHZ) {
b481de9c
ZY		 2256 priv->staging_rxon.flags &=
2257 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
2258 | RXON_FLG_CCK_MSK);
2259 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2260 } else {
bb8c093b 2261 /* Copied from iwl3945_bg_post_associate() */
b481de9c
ZY		 2262 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2263 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2264 else
2265 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2266
2267 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
2268 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2269
2270 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
2271 priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
2272 priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
2273 }
2274}
2275
2276/*
01ebd063 2277 * initialize rxon structure with default values from eeprom
b481de9c 2278 */
bb8c093b 2279static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv)
b481de9c 2280{
bb8c093b 2281 const struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 2282
2283 memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
2284
2285 switch (priv->iw_mode) {
2286 case IEEE80211_IF_TYPE_AP:
2287 priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
2288 break;
2289
2290 case IEEE80211_IF_TYPE_STA:
2291 priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
2292 priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
2293 break;
2294
2295 case IEEE80211_IF_TYPE_IBSS:
2296 priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
2297 priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
2298 priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
2299 RXON_FILTER_ACCEPT_GRP_MSK;
2300 break;
2301
2302 case IEEE80211_IF_TYPE_MNTR:
2303 priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
2304 priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
2305 RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
2306 break;
69dc5d9d
TW		 2307 default:
2308 IWL_ERROR("Unsupported interface type %d\n", priv->iw_mode);
2309 break;
b481de9c
ZY		 2310 }
2311
2312#if 0
2313 /* TODO: Figure out when short_preamble would be set and cache from
2314 * that */
2315 if (!hw_to_local(priv->hw)->short_preamble)
2316 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2317 else
2318 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2319#endif
2320
8318d78a 2321 ch_info = iwl3945_get_channel_info(priv, priv->band,
b481de9c
ZY		 2322 le16_to_cpu(priv->staging_rxon.channel));
2323
2324 if (!ch_info)
2325 ch_info = &priv->channel_info[0];
2326
2327 /*
2328 * in some case A channels are all non IBSS
2329 * in this case force B/G channel
2330 */
2331 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
2332 !(is_channel_ibss(ch_info)))
2333 ch_info = &priv->channel_info[0];
2334
2335 priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
2336 if (is_channel_a_band(ch_info))
8318d78a 2337 priv->band = IEEE80211_BAND_5GHZ;
b481de9c 2338 else
8318d78a 2339 priv->band = IEEE80211_BAND_2GHZ;
b481de9c 2340
8318d78a 2341 iwl3945_set_flags_for_phymode(priv, priv->band);
b481de9c
ZY		 2342
2343 priv->staging_rxon.ofdm_basic_rates =
2344 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2345 priv->staging_rxon.cck_basic_rates =
2346 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2347}
2348
bb8c093b 2349static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
b481de9c 2350{
b481de9c 2351 if (mode == IEEE80211_IF_TYPE_IBSS) {
bb8c093b 2352 const struct iwl3945_channel_info *ch_info;
b481de9c 2353
bb8c093b 2354 ch_info = iwl3945_get_channel_info(priv,
8318d78a 2355 priv->band,
b481de9c
ZY		 2356 le16_to_cpu(priv->staging_rxon.channel));
2357
2358 if (!ch_info || !is_channel_ibss(ch_info)) {
2359 IWL_ERROR("channel %d not IBSS channel\n",
2360 le16_to_cpu(priv->staging_rxon.channel));
2361 return -EINVAL;
2362 }
2363 }
2364
b481de9c
ZY		 2365 priv->iw_mode = mode;
2366
bb8c093b 2367 iwl3945_connection_init_rx_config(priv);
b481de9c
ZY		 2368 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2369
bb8c093b 2370 iwl3945_clear_stations_table(priv);
b481de9c 2371
fde3571f
MA		 2372 /* dont commit rxon if rf-kill is on*/
2373 if (!iwl3945_is_ready_rf(priv))
2374 return -EAGAIN;
2375
2376 cancel_delayed_work(&priv->scan_check);
2377 if (iwl3945_scan_cancel_timeout(priv, 100)) {
2378 IWL_WARNING("Aborted scan still in progress after 100ms\n");
2379 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
2380 return -EAGAIN;
2381 }
2382
bb8c093b 2383 iwl3945_commit_rxon(priv);
b481de9c
ZY		 2384
2385 return 0;
2386}
2387
bb8c093b 2388static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
b481de9c 2389 struct ieee80211_tx_control *ctl,
bb8c093b 2390 struct iwl3945_cmd *cmd,
b481de9c
ZY		 2391 struct sk_buff *skb_frag,
2392 int last_frag)
2393{
bb8c093b 2394 struct iwl3945_hw_key *keyinfo = &priv->stations[ctl->key_idx].keyinfo;
b481de9c
ZY		 2395
2396 switch (keyinfo->alg) {
2397 case ALG_CCMP:
2398 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
2399 memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
2400 IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
2401 break;
2402
2403 case ALG_TKIP:
2404#if 0
2405 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
2406
2407 if (last_frag)
2408 memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
2409 8);
2410 else
2411 memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
2412#endif
2413 break;
2414
2415 case ALG_WEP:
2416 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
2417 (ctl->key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
2418
2419 if (keyinfo->keylen == 13)
2420 cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
2421
2422 memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
2423
2424 IWL_DEBUG_TX("Configuring packet for WEP encryption "
2425 "with key %d\n", ctl->key_idx);
2426 break;
2427
b481de9c
ZY		 2428 default:
2429 printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
2430 break;
2431 }
2432}
2433
2434/*
2435 * handle build REPLY_TX command notification.
2436 */
bb8c093b
CH		 2437static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
2438 struct iwl3945_cmd *cmd,
b481de9c
ZY		 2439 struct ieee80211_tx_control *ctrl,
2440 struct ieee80211_hdr *hdr,
2441 int is_unicast, u8 std_id)
2442{
2443 __le16 *qc;
2444 u16 fc = le16_to_cpu(hdr->frame_control);
2445 __le32 tx_flags = cmd->cmd.tx.tx_flags;
2446
2447 cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2448 if (!(ctrl->flags & IEEE80211_TXCTL_NO_ACK)) {
2449 tx_flags |= TX_CMD_FLG_ACK_MSK;
2450 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
2451 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2452 if (ieee80211_is_probe_response(fc) &&
2453 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
2454 tx_flags |= TX_CMD_FLG_TSF_MSK;
2455 } else {
2456 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
2457 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2458 }
2459
2460 cmd->cmd.tx.sta_id = std_id;
2461 if (ieee80211_get_morefrag(hdr))
2462 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
2463
2464 qc = ieee80211_get_qos_ctrl(hdr);
2465 if (qc) {
2466 cmd->cmd.tx.tid_tspec = (u8) (le16_to_cpu(*qc) & 0xf);
2467 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
2468 } else
2469 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2470
2471 if (ctrl->flags & IEEE80211_TXCTL_USE_RTS_CTS) {
2472 tx_flags |= TX_CMD_FLG_RTS_MSK;
2473 tx_flags &= ~TX_CMD_FLG_CTS_MSK;
2474 } else if (ctrl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) {
2475 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2476 tx_flags |= TX_CMD_FLG_CTS_MSK;
2477 }
2478
2479 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
2480 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
2481
2482 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
2483 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) {
2484 if ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_REQ ||
2485 (fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_REASSOC_REQ)
bc434dd2 2486 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
b481de9c 2487 else
bc434dd2 2488 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
ab53d8af 2489 } else {
b481de9c 2490 cmd->cmd.tx.timeout.pm_frame_timeout = 0;
ab53d8af
MA		 2491#ifdef CONFIG_IWL3945_LEDS
2492 priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
2493#endif
2494 }
b481de9c
ZY		 2495
2496 cmd->cmd.tx.driver_txop = 0;
2497 cmd->cmd.tx.tx_flags = tx_flags;
2498 cmd->cmd.tx.next_frame_len = 0;
2499}
2500
6440adb5
CB		 2501/**
2502 * iwl3945_get_sta_id - Find station's index within station table
2503 */
bb8c093b 2504static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
b481de9c
ZY		 2505{
2506 int sta_id;
2507 u16 fc = le16_to_cpu(hdr->frame_control);
2508
6440adb5 2509 /* If this frame is broadcast or management, use broadcast station id */
b481de9c
ZY		 2510 if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
2511 is_multicast_ether_addr(hdr->addr1))
2512 return priv->hw_setting.bcast_sta_id;
2513
2514 switch (priv->iw_mode) {
2515
6440adb5
CB		 2516 /* If we are a client station in a BSS network, use the special
2517 * AP station entry (that's the only station we communicate with) */
b481de9c
ZY		 2518 case IEEE80211_IF_TYPE_STA:
2519 return IWL_AP_ID;
2520
2521 /* If we are an AP, then find the station, or use BCAST */
2522 case IEEE80211_IF_TYPE_AP:
bb8c093b 2523 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY		 2524 if (sta_id != IWL_INVALID_STATION)
2525 return sta_id;
2526 return priv->hw_setting.bcast_sta_id;
2527
6440adb5
CB		 2528 /* If this frame is going out to an IBSS network, find the station,
2529 * or create a new station table entry */
0795af57
JP		 2530 case IEEE80211_IF_TYPE_IBSS: {
2531 DECLARE_MAC_BUF(mac);
2532
6440adb5 2533 /* Create new station table entry */
bb8c093b 2534 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY		 2535 if (sta_id != IWL_INVALID_STATION)
2536 return sta_id;
2537
bb8c093b 2538 sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
b481de9c
ZY		 2539
2540 if (sta_id != IWL_INVALID_STATION)
2541 return sta_id;
2542
0795af57 2543 IWL_DEBUG_DROP("Station %s not in station map. "
b481de9c 2544 "Defaulting to broadcast...\n",
0795af57 2545 print_mac(mac, hdr->addr1));
bb8c093b 2546 iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
b481de9c 2547 return priv->hw_setting.bcast_sta_id;
0795af57 2548 }
b481de9c 2549 default:
01ebd063 2550 IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode);
b481de9c
ZY		 2551 return priv->hw_setting.bcast_sta_id;
2552 }
2553}
2554
2555/*
2556 * start REPLY_TX command process
2557 */
bb8c093b 2558static int iwl3945_tx_skb(struct iwl3945_priv *priv,
b481de9c
ZY		 2559 struct sk_buff *skb, struct ieee80211_tx_control *ctl)
2560{
2561 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
bb8c093b 2562 struct iwl3945_tfd_frame *tfd;
b481de9c
ZY		 2563 u32 *control_flags;
2564 int txq_id = ctl->queue;
bb8c093b
CH		 2565 struct iwl3945_tx_queue *txq = NULL;
2566 struct iwl3945_queue *q = NULL;
b481de9c
ZY		 2567 dma_addr_t phys_addr;
2568 dma_addr_t txcmd_phys;
bb8c093b 2569 struct iwl3945_cmd *out_cmd = NULL;
b481de9c
ZY		 2570 u16 len, idx, len_org;
2571 u8 id, hdr_len, unicast;
2572 u8 sta_id;
2573 u16 seq_number = 0;
2574 u16 fc;
2575 __le16 *qc;
2576 u8 wait_write_ptr = 0;
2577 unsigned long flags;
2578 int rc;
2579
2580 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2581 if (iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 2582 IWL_DEBUG_DROP("Dropping - RF KILL\n");
2583 goto drop_unlock;
2584 }
2585
32bfd35d
JB		 2586 if (!priv->vif) {
2587 IWL_DEBUG_DROP("Dropping - !priv->vif\n");
b481de9c
ZY		 2588 goto drop_unlock;
2589 }
2590
8318d78a 2591 if ((ctl->tx_rate->hw_value & 0xFF) == IWL_INVALID_RATE) {
b481de9c
ZY		 2592 IWL_ERROR("ERROR: No TX rate available.\n");
2593 goto drop_unlock;
2594 }
2595
2596 unicast = !is_multicast_ether_addr(hdr->addr1);
2597 id = 0;
2598
2599 fc = le16_to_cpu(hdr->frame_control);
2600
c8b0e6e1 2601#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 2602 if (ieee80211_is_auth(fc))
2603 IWL_DEBUG_TX("Sending AUTH frame\n");
2604 else if (ieee80211_is_assoc_request(fc))
2605 IWL_DEBUG_TX("Sending ASSOC frame\n");
2606 else if (ieee80211_is_reassoc_request(fc))
2607 IWL_DEBUG_TX("Sending REASSOC frame\n");
2608#endif
2609
7878a5a4 2610 /* drop all data frame if we are not associated */
a6477249
RC		 2611 if ((!iwl3945_is_associated(priv) ||
2612 ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && !priv->assoc_id)) &&
b481de9c 2613 ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA)) {
bb8c093b 2614 IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
b481de9c
ZY		 2615 goto drop_unlock;
2616 }
2617
2618 spin_unlock_irqrestore(&priv->lock, flags);
2619
2620 hdr_len = ieee80211_get_hdrlen(fc);
6440adb5
CB		 2621
2622 /* Find (or create) index into station table for destination station */
bb8c093b 2623 sta_id = iwl3945_get_sta_id(priv, hdr);
b481de9c 2624 if (sta_id == IWL_INVALID_STATION) {
0795af57
JP		 2625 DECLARE_MAC_BUF(mac);
2626
2627 IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
2628 print_mac(mac, hdr->addr1));
b481de9c
ZY		 2629 goto drop;
2630 }
2631
2632 IWL_DEBUG_RATE("station Id %d\n", sta_id);
2633
2634 qc = ieee80211_get_qos_ctrl(hdr);
2635 if (qc) {
2636 u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
2637 seq_number = priv->stations[sta_id].tid[tid].seq_number &
2638 IEEE80211_SCTL_SEQ;
2639 hdr->seq_ctrl = cpu_to_le16(seq_number) |
2640 (hdr->seq_ctrl &
2641 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
2642 seq_number += 0x10;
2643 }
6440adb5
CB		 2644
2645 /* Descriptor for chosen Tx queue */
b481de9c
ZY		 2646 txq = &priv->txq[txq_id];
2647 q = &txq->q;
2648
2649 spin_lock_irqsave(&priv->lock, flags);
2650
6440adb5 2651 /* Set up first empty TFD within this queue's circular TFD buffer */
fc4b6853 2652 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY		 2653 memset(tfd, 0, sizeof(*tfd));
2654 control_flags = (u32 *) tfd;
fc4b6853 2655 idx = get_cmd_index(q, q->write_ptr, 0);
b481de9c 2656
6440adb5 2657 /* Set up driver data for this TFD */
bb8c093b 2658 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
fc4b6853
TW		 2659 txq->txb[q->write_ptr].skb[0] = skb;
2660 memcpy(&(txq->txb[q->write_ptr].status.control),
b481de9c 2661 ctl, sizeof(struct ieee80211_tx_control));
6440adb5
CB		 2662
2663 /* Init first empty entry in queue's array of Tx/cmd buffers */
b481de9c
ZY		 2664 out_cmd = &txq->cmd[idx];
2665 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
2666 memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
6440adb5
CB		 2667
2668 /*
2669 * Set up the Tx-command (not MAC!) header.
2670 * Store the chosen Tx queue and TFD index within the sequence field;
2671 * after Tx, uCode's Tx response will return this value so driver can
2672 * locate the frame within the tx queue and do post-tx processing.
2673 */
b481de9c
ZY		 2674 out_cmd->hdr.cmd = REPLY_TX;
2675 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
fc4b6853 2676 INDEX_TO_SEQ(q->write_ptr)));
6440adb5
CB		 2677
2678 /* Copy MAC header from skb into command buffer */
b481de9c
ZY		 2679 memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
2680
6440adb5
CB		 2681 /*
2682 * Use the first empty entry in this queue's command buffer array
2683 * to contain the Tx command and MAC header concatenated together
2684 * (payload data will be in another buffer).
2685 * Size of this varies, due to varying MAC header length.
2686 * If end is not dword aligned, we'll have 2 extra bytes at the end
2687 * of the MAC header (device reads on dword boundaries).
2688 * We'll tell device about this padding later.
2689 */
b481de9c 2690 len = priv->hw_setting.tx_cmd_len +
bb8c093b 2691 sizeof(struct iwl3945_cmd_header) + hdr_len;
b481de9c
ZY		 2692
2693 len_org = len;
2694 len = (len + 3) & ~3;
2695
2696 if (len_org != len)
2697 len_org = 1;
2698 else
2699 len_org = 0;
2700
6440adb5
CB		 2701 /* Physical address of this Tx command's header (not MAC header!),
2702 * within command buffer array. */
bb8c093b
CH		 2703 txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
2704 offsetof(struct iwl3945_cmd, hdr);
b481de9c 2705
6440adb5
CB		 2706 /* Add buffer containing Tx command and MAC(!) header to TFD's
2707 * first entry */
bb8c093b 2708 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
b481de9c
ZY		 2709
2710 if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT))
bb8c093b 2711 iwl3945_build_tx_cmd_hwcrypto(priv, ctl, out_cmd, skb, 0);
b481de9c 2712
6440adb5
CB		 2713 /* Set up TFD's 2nd entry to point directly to remainder of skb,
2714 * if any (802.11 null frames have no payload). */
b481de9c
ZY		 2715 len = skb->len - hdr_len;
2716 if (len) {
2717 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
2718 len, PCI_DMA_TODEVICE);
bb8c093b 2719 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
b481de9c
ZY		 2720 }
2721
b481de9c 2722 if (!len)
6440adb5 2723 /* If there is no payload, then we use only one Tx buffer */
b481de9c
ZY		 2724 *control_flags = TFD_CTL_COUNT_SET(1);
2725 else
6440adb5
CB		 2726 /* Else use 2 buffers.
2727 * Tell 3945 about any padding after MAC header */
b481de9c
ZY		 2728 *control_flags = TFD_CTL_COUNT_SET(2) |
2729 TFD_CTL_PAD_SET(U32_PAD(len));
2730
6440adb5 2731 /* Total # bytes to be transmitted */
b481de9c
ZY		 2732 len = (u16)skb->len;
2733 out_cmd->cmd.tx.len = cpu_to_le16(len);
2734
2735 /* TODO need this for burst mode later on */
bb8c093b 2736 iwl3945_build_tx_cmd_basic(priv, out_cmd, ctl, hdr, unicast, sta_id);
b481de9c
ZY		 2737
2738 /* set is_hcca to 0; it probably will never be implemented */
bb8c093b 2739 iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, ctl, hdr, sta_id, 0);
b481de9c
ZY		 2740
2741 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
2742 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
2743
2744 if (!ieee80211_get_morefrag(hdr)) {
2745 txq->need_update = 1;
2746 if (qc) {
2747 u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
2748 priv->stations[sta_id].tid[tid].seq_number = seq_number;
2749 }
2750 } else {
2751 wait_write_ptr = 1;
2752 txq->need_update = 0;
2753 }
2754
bb8c093b 2755 iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
b481de9c
ZY		 2756 sizeof(out_cmd->cmd.tx));
2757
bb8c093b 2758 iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
b481de9c
ZY		 2759 ieee80211_get_hdrlen(fc));
2760
6440adb5 2761 /* Tell device the write index *just past* this latest filled TFD */
c54b679d 2762 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
bb8c093b 2763 rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 2764 spin_unlock_irqrestore(&priv->lock, flags);
2765
2766 if (rc)
2767 return rc;
2768
bb8c093b 2769 if ((iwl3945_queue_space(q) < q->high_mark)
b481de9c
ZY		 2770 && priv->mac80211_registered) {
2771 if (wait_write_ptr) {
2772 spin_lock_irqsave(&priv->lock, flags);
2773 txq->need_update = 1;
bb8c093b 2774 iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 2775 spin_unlock_irqrestore(&priv->lock, flags);
2776 }
2777
2778 ieee80211_stop_queue(priv->hw, ctl->queue);
2779 }
2780
2781 return 0;
2782
2783drop_unlock:
2784 spin_unlock_irqrestore(&priv->lock, flags);
2785drop:
2786 return -1;
2787}
2788
bb8c093b 2789static void iwl3945_set_rate(struct iwl3945_priv *priv)
b481de9c 2790{
8318d78a 2791 const struct ieee80211_supported_band *sband = NULL;
b481de9c
ZY		 2792 struct ieee80211_rate *rate;
2793 int i;
2794
8318d78a
JB		 2795 sband = iwl3945_get_band(priv, priv->band);
2796 if (!sband) {
c4ba9621
SA		 2797 IWL_ERROR("Failed to set rate: unable to get hw mode\n");
2798 return;
2799 }
b481de9c
ZY		 2800
2801 priv->active_rate = 0;
2802 priv->active_rate_basic = 0;
2803
8318d78a
JB		 2804 IWL_DEBUG_RATE("Setting rates for %s GHz\n",
2805 sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
2806
2807 for (i = 0; i < sband->n_bitrates; i++) {
2808 rate = &sband->bitrates[i];
2809 if ((rate->hw_value < IWL_RATE_COUNT) &&
2810 !(rate->flags & IEEE80211_CHAN_DISABLED)) {
2811 IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
2812 rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
2813 priv->active_rate |= (1 << rate->hw_value);
2814 }
b481de9c
ZY		 2815 }
2816
2817 IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
2818 priv->active_rate, priv->active_rate_basic);
2819
2820 /*
2821 * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
2822 * otherwise set it to the default of all CCK rates and 6, 12, 24 for
2823 * OFDM
2824 */
2825 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
2826 priv->staging_rxon.cck_basic_rates =
2827 ((priv->active_rate_basic &
2828 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
2829 else
2830 priv->staging_rxon.cck_basic_rates =
2831 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2832
2833 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
2834 priv->staging_rxon.ofdm_basic_rates =
2835 ((priv->active_rate_basic &
2836 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
2837 IWL_FIRST_OFDM_RATE) & 0xFF;
2838 else
2839 priv->staging_rxon.ofdm_basic_rates =
2840 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2841}
2842
bb8c093b 2843static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
b481de9c
ZY		 2844{
2845 unsigned long flags;
2846
2847 if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
2848 return;
2849
2850 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
2851 disable_radio ? "OFF" : "ON");
2852
2853 if (disable_radio) {
bb8c093b 2854 iwl3945_scan_cancel(priv);
b481de9c
ZY		 2855 /* FIXME: This is a workaround for AP */
2856 if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
2857 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2858 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 2859 CSR_UCODE_SW_BIT_RFKILL);
2860 spin_unlock_irqrestore(&priv->lock, flags);
bb8c093b 2861 iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
b481de9c
ZY		 2862 set_bit(STATUS_RF_KILL_SW, &priv->status);
2863 }
2864 return;
2865 }
2866
2867 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2868 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 2869
2870 clear_bit(STATUS_RF_KILL_SW, &priv->status);
2871 spin_unlock_irqrestore(&priv->lock, flags);
2872
2873 /* wake up ucode */
2874 msleep(10);
2875
2876 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH		 2877 iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
2878 if (!iwl3945_grab_nic_access(priv))
2879 iwl3945_release_nic_access(priv);
b481de9c
ZY		 2880 spin_unlock_irqrestore(&priv->lock, flags);
2881
2882 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
2883 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
2884 "disabled by HW switch\n");
2885 return;
2886 }
2887
2888 queue_work(priv->workqueue, &priv->restart);
2889 return;
2890}
2891
bb8c093b 2892void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
b481de9c
ZY		 2893 u32 decrypt_res, struct ieee80211_rx_status *stats)
2894{
2895 u16 fc =
2896 le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
2897
2898 if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
2899 return;
2900
2901 if (!(fc & IEEE80211_FCTL_PROTECTED))
2902 return;
2903
2904 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
2905 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2906 case RX_RES_STATUS_SEC_TYPE_TKIP:
2907 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2908 RX_RES_STATUS_BAD_ICV_MIC)
2909 stats->flag |= RX_FLAG_MMIC_ERROR;
2910 case RX_RES_STATUS_SEC_TYPE_WEP:
2911 case RX_RES_STATUS_SEC_TYPE_CCMP:
2912 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2913 RX_RES_STATUS_DECRYPT_OK) {
2914 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
2915 stats->flag |= RX_FLAG_DECRYPTED;
2916 }
2917 break;
2918
2919 default:
2920 break;
2921 }
2922}
2923
b481de9c
ZY		 2924#define IWL_PACKET_RETRY_TIME HZ
2925
bb8c093b 2926int iwl3945_is_duplicate_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
b481de9c
ZY		 2927{
2928 u16 sc = le16_to_cpu(header->seq_ctrl);
2929 u16 seq = (sc & IEEE80211_SCTL_SEQ) >> 4;
2930 u16 frag = sc & IEEE80211_SCTL_FRAG;
2931 u16 *last_seq, *last_frag;
2932 unsigned long *last_time;
2933
2934 switch (priv->iw_mode) {
2935 case IEEE80211_IF_TYPE_IBSS:{
2936 struct list_head *p;
bb8c093b 2937 struct iwl3945_ibss_seq *entry = NULL;
b481de9c
ZY		 2938 u8 *mac = header->addr2;
2939 int index = mac[5] & (IWL_IBSS_MAC_HASH_SIZE - 1);
2940
2941 __list_for_each(p, &priv->ibss_mac_hash[index]) {
bb8c093b 2942 entry = list_entry(p, struct iwl3945_ibss_seq, list);
b481de9c
ZY		 2943 if (!compare_ether_addr(entry->mac, mac))
2944 break;
2945 }
2946 if (p == &priv->ibss_mac_hash[index]) {
2947 entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
2948 if (!entry) {
bc434dd2 2949 IWL_ERROR("Cannot malloc new mac entry\n");
b481de9c
ZY		 2950 return 0;
2951 }
2952 memcpy(entry->mac, mac, ETH_ALEN);
2953 entry->seq_num = seq;
2954 entry->frag_num = frag;
2955 entry->packet_time = jiffies;
bc434dd2 2956 list_add(&entry->list, &priv->ibss_mac_hash[index]);
b481de9c
ZY		 2957 return 0;
2958 }
2959 last_seq = &entry->seq_num;
2960 last_frag = &entry->frag_num;
2961 last_time = &entry->packet_time;
2962 break;
2963 }
2964 case IEEE80211_IF_TYPE_STA:
2965 last_seq = &priv->last_seq_num;
2966 last_frag = &priv->last_frag_num;
2967 last_time = &priv->last_packet_time;
2968 break;
2969 default:
2970 return 0;
2971 }
2972 if ((*last_seq == seq) &&
2973 time_after(*last_time + IWL_PACKET_RETRY_TIME, jiffies)) {
2974 if (*last_frag == frag)
2975 goto drop;
2976 if (*last_frag + 1 != frag)
2977 /* out-of-order fragment */
2978 goto drop;
2979 } else
2980 *last_seq = seq;
2981
2982 *last_frag = frag;
2983 *last_time = jiffies;
2984 return 0;
2985
2986 drop:
2987 return 1;
2988}
2989
c8b0e6e1 2990#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 2991
2992#include "iwl-spectrum.h"
2993
2994#define BEACON_TIME_MASK_LOW 0x00FFFFFF
2995#define BEACON_TIME_MASK_HIGH 0xFF000000
2996#define TIME_UNIT 1024
2997
2998/*
2999 * extended beacon time format
3000 * time in usec will be changed into a 32-bit value in 8:24 format
3001 * the high 1 byte is the beacon counts
3002 * the lower 3 bytes is the time in usec within one beacon interval
3003 */
3004
bb8c093b 3005static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
b481de9c
ZY		 3006{
3007 u32 quot;
3008 u32 rem;
3009 u32 interval = beacon_interval * 1024;
3010
3011 if (!interval || !usec)
3012 return 0;
3013
3014 quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
3015 rem = (usec % interval) & BEACON_TIME_MASK_LOW;
3016
3017 return (quot << 24) + rem;
3018}
3019
3020/* base is usually what we get from ucode with each received frame,
3021 * the same as HW timer counter counting down
3022 */
3023
bb8c093b 3024static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
b481de9c
ZY		 3025{
3026 u32 base_low = base & BEACON_TIME_MASK_LOW;
3027 u32 addon_low = addon & BEACON_TIME_MASK_LOW;
3028 u32 interval = beacon_interval * TIME_UNIT;
3029 u32 res = (base & BEACON_TIME_MASK_HIGH) +
3030 (addon & BEACON_TIME_MASK_HIGH);
3031
3032 if (base_low > addon_low)
3033 res += base_low - addon_low;
3034 else if (base_low < addon_low) {
3035 res += interval + base_low - addon_low;
3036 res += (1 << 24);
3037 } else
3038 res += (1 << 24);
3039
3040 return cpu_to_le32(res);
3041}
3042
bb8c093b 3043static int iwl3945_get_measurement(struct iwl3945_priv *priv,
b481de9c
ZY		 3044 struct ieee80211_measurement_params *params,
3045 u8 type)
3046{
bb8c093b
CH		 3047 struct iwl3945_spectrum_cmd spectrum;
3048 struct iwl3945_rx_packet *res;
3049 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 3050 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
3051 .data = (void *)&spectrum,
3052 .meta.flags = CMD_WANT_SKB,
3053 };
3054 u32 add_time = le64_to_cpu(params->start_time);
3055 int rc;
3056 int spectrum_resp_status;
3057 int duration = le16_to_cpu(params->duration);
3058
bb8c093b 3059 if (iwl3945_is_associated(priv))
b481de9c 3060 add_time =
bb8c093b 3061 iwl3945_usecs_to_beacons(
b481de9c
ZY		 3062 le64_to_cpu(params->start_time) - priv->last_tsf,
3063 le16_to_cpu(priv->rxon_timing.beacon_interval));
3064
3065 memset(&spectrum, 0, sizeof(spectrum));
3066
3067 spectrum.channel_count = cpu_to_le16(1);
3068 spectrum.flags =
3069 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
3070 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
3071 cmd.len = sizeof(spectrum);
3072 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
3073
bb8c093b 3074 if (iwl3945_is_associated(priv))
b481de9c 3075 spectrum.start_time =
bb8c093b 3076 iwl3945_add_beacon_time(priv->last_beacon_time,
b481de9c
ZY		 3077 add_time,
3078 le16_to_cpu(priv->rxon_timing.beacon_interval));
3079 else
3080 spectrum.start_time = 0;
3081
3082 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
3083 spectrum.channels[0].channel = params->channel;
3084 spectrum.channels[0].type = type;
3085 if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
3086 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
3087 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
3088
bb8c093b 3089 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 3090 if (rc)
3091 return rc;
3092
bb8c093b 3093 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 3094 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
3095 IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
3096 rc = -EIO;
3097 }
3098
3099 spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
3100 switch (spectrum_resp_status) {
3101 case 0: /* Command will be handled */
3102 if (res->u.spectrum.id != 0xff) {
bc434dd2
IS		 3103 IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
3104 res->u.spectrum.id);
b481de9c
ZY		 3105 priv->measurement_status &= ~MEASUREMENT_READY;
3106 }
3107 priv->measurement_status |= MEASUREMENT_ACTIVE;
3108 rc = 0;
3109 break;
3110
3111 case 1: /* Command will not be handled */
3112 rc = -EAGAIN;
3113 break;
3114 }
3115
3116 dev_kfree_skb_any(cmd.meta.u.skb);
3117
3118 return rc;
3119}
3120#endif
3121
bb8c093b
CH		 3122static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
3123 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3124{
bb8c093b
CH		 3125 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3126 struct iwl3945_alive_resp *palive;
b481de9c
ZY		 3127 struct delayed_work *pwork;
3128
3129 palive = &pkt->u.alive_frame;
3130
3131 IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
3132 "0x%01X 0x%01X\n",
3133 palive->is_valid, palive->ver_type,
3134 palive->ver_subtype);
3135
3136 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
3137 IWL_DEBUG_INFO("Initialization Alive received.\n");
3138 memcpy(&priv->card_alive_init,
3139 &pkt->u.alive_frame,
bb8c093b 3140 sizeof(struct iwl3945_init_alive_resp));
b481de9c
ZY		 3141 pwork = &priv->init_alive_start;
3142 } else {
3143 IWL_DEBUG_INFO("Runtime Alive received.\n");
3144 memcpy(&priv->card_alive, &pkt->u.alive_frame,
bb8c093b 3145 sizeof(struct iwl3945_alive_resp));
b481de9c 3146 pwork = &priv->alive_start;
bb8c093b 3147 iwl3945_disable_events(priv);
b481de9c
ZY		 3148 }
3149
3150 /* We delay the ALIVE response by 5ms to
3151 * give the HW RF Kill time to activate... */
3152 if (palive->is_valid == UCODE_VALID_OK)
3153 queue_delayed_work(priv->workqueue, pwork,
3154 msecs_to_jiffies(5));
3155 else
3156 IWL_WARNING("uCode did not respond OK.\n");
3157}
3158
bb8c093b
CH		 3159static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
3160 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3161{
bb8c093b 3162 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3163
3164 IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
3165 return;
3166}
3167
bb8c093b
CH		 3168static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
3169 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3170{
bb8c093b 3171 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3172
3173 IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
3174 "seq 0x%04X ser 0x%08X\n",
3175 le32_to_cpu(pkt->u.err_resp.error_type),
3176 get_cmd_string(pkt->u.err_resp.cmd_id),
3177 pkt->u.err_resp.cmd_id,
3178 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
3179 le32_to_cpu(pkt->u.err_resp.error_info));
3180}
3181
3182#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
3183
bb8c093b 3184static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3185{
bb8c093b
CH		 3186 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3187 struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
3188 struct iwl3945_csa_notification *csa = &(pkt->u.csa_notif);
b481de9c
ZY		 3189 IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
3190 le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
3191 rxon->channel = csa->channel;
3192 priv->staging_rxon.channel = csa->channel;
3193}
3194
bb8c093b
CH		 3195static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
3196 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3197{
c8b0e6e1 3198#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
bb8c093b
CH		 3199 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3200 struct iwl3945_spectrum_notification *report = &(pkt->u.spectrum_notif);
b481de9c
ZY		 3201
3202 if (!report->state) {
3203 IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
3204 "Spectrum Measure Notification: Start\n");
3205 return;
3206 }
3207
3208 memcpy(&priv->measure_report, report, sizeof(*report));
3209 priv->measurement_status |= MEASUREMENT_READY;
3210#endif
3211}
3212
bb8c093b
CH		 3213static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
3214 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3215{
c8b0e6e1 3216#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3217 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3218 struct iwl3945_sleep_notification *sleep = &(pkt->u.sleep_notif);
b481de9c
ZY		 3219 IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
3220 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
3221#endif
3222}
3223
bb8c093b
CH		 3224static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
3225 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3226{
bb8c093b 3227 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3228 IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
3229 "notification for %s:\n",
3230 le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
bb8c093b 3231 iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
b481de9c
ZY		 3232}
3233
bb8c093b 3234static void iwl3945_bg_beacon_update(struct work_struct *work)
b481de9c 3235{
bb8c093b
CH		 3236 struct iwl3945_priv *priv =
3237 container_of(work, struct iwl3945_priv, beacon_update);
b481de9c
ZY		 3238 struct sk_buff *beacon;
3239
3240 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
32bfd35d 3241 beacon = ieee80211_beacon_get(priv->hw, priv->vif, NULL);
b481de9c
ZY		 3242
3243 if (!beacon) {
3244 IWL_ERROR("update beacon failed\n");
3245 return;
3246 }
3247
3248 mutex_lock(&priv->mutex);
3249 /* new beacon skb is allocated every time; dispose previous.*/
3250 if (priv->ibss_beacon)
3251 dev_kfree_skb(priv->ibss_beacon);
3252
3253 priv->ibss_beacon = beacon;
3254 mutex_unlock(&priv->mutex);
3255
bb8c093b 3256 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 3257}
3258
bb8c093b
CH		 3259static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
3260 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3261{
c8b0e6e1 3262#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3263 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3264 struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
b481de9c
ZY		 3265 u8 rate = beacon->beacon_notify_hdr.rate;
3266
3267 IWL_DEBUG_RX("beacon status %x retries %d iss %d "
3268 "tsf %d %d rate %d\n",
3269 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
3270 beacon->beacon_notify_hdr.failure_frame,
3271 le32_to_cpu(beacon->ibss_mgr_status),
3272 le32_to_cpu(beacon->high_tsf),
3273 le32_to_cpu(beacon->low_tsf), rate);
3274#endif
3275
3276 if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
3277 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
3278 queue_work(priv->workqueue, &priv->beacon_update);
3279}
3280
3281/* Service response to REPLY_SCAN_CMD (0x80) */
bb8c093b
CH		 3282static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
3283 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3284{
c8b0e6e1 3285#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3286 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3287 struct iwl3945_scanreq_notification *notif =
3288 (struct iwl3945_scanreq_notification *)pkt->u.raw;
b481de9c
ZY		 3289
3290 IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
3291#endif
3292}
3293
3294/* Service SCAN_START_NOTIFICATION (0x82) */
bb8c093b
CH		 3295static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
3296 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3297{
bb8c093b
CH		 3298 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3299 struct iwl3945_scanstart_notification *notif =
3300 (struct iwl3945_scanstart_notification *)pkt->u.raw;
b481de9c
ZY		 3301 priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
3302 IWL_DEBUG_SCAN("Scan start: "
3303 "%d [802.11%s] "
3304 "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
3305 notif->channel,
3306 notif->band ? "bg" : "a",
3307 notif->tsf_high,
3308 notif->tsf_low, notif->status, notif->beacon_timer);
3309}
3310
3311/* Service SCAN_RESULTS_NOTIFICATION (0x83) */
bb8c093b
CH		 3312static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
3313 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3314{
bb8c093b
CH		 3315 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3316 struct iwl3945_scanresults_notification *notif =
3317 (struct iwl3945_scanresults_notification *)pkt->u.raw;
b481de9c
ZY		 3318
3319 IWL_DEBUG_SCAN("Scan ch.res: "
3320 "%d [802.11%s] "
3321 "(TSF: 0x%08X:%08X) - %d "
3322 "elapsed=%lu usec (%dms since last)\n",
3323 notif->channel,
3324 notif->band ? "bg" : "a",
3325 le32_to_cpu(notif->tsf_high),
3326 le32_to_cpu(notif->tsf_low),
3327 le32_to_cpu(notif->statistics[0]),
3328 le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
3329 jiffies_to_msecs(elapsed_jiffies
3330 (priv->last_scan_jiffies, jiffies)));
3331
3332 priv->last_scan_jiffies = jiffies;
7878a5a4 3333 priv->next_scan_jiffies = 0;
b481de9c
ZY		 3334}
3335
3336/* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
bb8c093b
CH		 3337static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
3338 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3339{
bb8c093b
CH		 3340 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3341 struct iwl3945_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
b481de9c
ZY		 3342
3343 IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
3344 scan_notif->scanned_channels,
3345 scan_notif->tsf_low,
3346 scan_notif->tsf_high, scan_notif->status);
3347
3348 /* The HW is no longer scanning */
3349 clear_bit(STATUS_SCAN_HW, &priv->status);
3350
3351 /* The scan completion notification came in, so kill that timer... */
3352 cancel_delayed_work(&priv->scan_check);
3353
3354 IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
3355 (priv->scan_bands == 2) ? "2.4" : "5.2",
3356 jiffies_to_msecs(elapsed_jiffies
3357 (priv->scan_pass_start, jiffies)));
3358
3359 /* Remove this scanned band from the list
3360 * of pending bands to scan */
3361 priv->scan_bands--;
3362
3363 /* If a request to abort was given, or the scan did not succeed
3364 * then we reset the scan state machine and terminate,
3365 * re-queuing another scan if one has been requested */
3366 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
3367 IWL_DEBUG_INFO("Aborted scan completed.\n");
3368 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
3369 } else {
3370 /* If there are more bands on this scan pass reschedule */
3371 if (priv->scan_bands > 0)
3372 goto reschedule;
3373 }
3374
3375 priv->last_scan_jiffies = jiffies;
7878a5a4 3376 priv->next_scan_jiffies = 0;
b481de9c
ZY		 3377 IWL_DEBUG_INFO("Setting scan to off\n");
3378
3379 clear_bit(STATUS_SCANNING, &priv->status);
3380
3381 IWL_DEBUG_INFO("Scan took %dms\n",
3382 jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
3383
3384 queue_work(priv->workqueue, &priv->scan_completed);
3385
3386 return;
3387
3388reschedule:
3389 priv->scan_pass_start = jiffies;
3390 queue_work(priv->workqueue, &priv->request_scan);
3391}
3392
3393/* Handle notification from uCode that card's power state is changing
3394 * due to software, hardware, or critical temperature RFKILL */
bb8c093b
CH		 3395static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
3396 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3397{
bb8c093b 3398 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3399 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
3400 unsigned long status = priv->status;
3401
3402 IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
3403 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3404 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
3405
bb8c093b 3406 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 3407 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3408
3409 if (flags & HW_CARD_DISABLED)
3410 set_bit(STATUS_RF_KILL_HW, &priv->status);
3411 else
3412 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3413
3414
3415 if (flags & SW_CARD_DISABLED)
3416 set_bit(STATUS_RF_KILL_SW, &priv->status);
3417 else
3418 clear_bit(STATUS_RF_KILL_SW, &priv->status);
3419
bb8c093b 3420 iwl3945_scan_cancel(priv);
b481de9c
ZY		 3421
3422 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
3423 test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
3424 (test_bit(STATUS_RF_KILL_SW, &status) !=
3425 test_bit(STATUS_RF_KILL_SW, &priv->status)))
3426 queue_work(priv->workqueue, &priv->rf_kill);
3427 else
3428 wake_up_interruptible(&priv->wait_command_queue);
3429}
3430
3431/**
bb8c093b 3432 * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY		 3433 *
3434 * Setup the RX handlers for each of the reply types sent from the uCode
3435 * to the host.
3436 *
3437 * This function chains into the hardware specific files for them to setup
3438 * any hardware specific handlers as well.
3439 */
bb8c093b 3440static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
b481de9c 3441{
bb8c093b
CH		 3442 priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
3443 priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
3444 priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
3445 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
b481de9c 3446 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
bb8c093b
CH		 3447 iwl3945_rx_spectrum_measure_notif;
3448 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
b481de9c 3449 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
bb8c093b
CH		 3450 iwl3945_rx_pm_debug_statistics_notif;
3451 priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
b481de9c 3452
9fbab516
BC		 3453 /*
3454 * The same handler is used for both the REPLY to a discrete
3455 * statistics request from the host as well as for the periodic
3456 * statistics notifications (after received beacons) from the uCode.
b481de9c 3457 */
bb8c093b
CH		 3458 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
3459 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
b481de9c 3460
bb8c093b
CH		 3461 priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
3462 priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
b481de9c 3463 priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
bb8c093b 3464 iwl3945_rx_scan_results_notif;
b481de9c 3465 priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
bb8c093b
CH		 3466 iwl3945_rx_scan_complete_notif;
3467 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
b481de9c 3468
9fbab516 3469 /* Set up hardware specific Rx handlers */
bb8c093b 3470 iwl3945_hw_rx_handler_setup(priv);
b481de9c
ZY		 3471}
3472
91c066f2
TW		 3473/**
3474 * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries
3475 * When FW advances 'R' index, all entries between old and new 'R' index
3476 * need to be reclaimed.
3477 */
3478static void iwl3945_cmd_queue_reclaim(struct iwl3945_priv *priv,
3479 int txq_id, int index)
3480{
3481 struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
3482 struct iwl3945_queue *q = &txq->q;
3483 int nfreed = 0;
3484
3485 if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) {
3486 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
3487 "is out of range [0-%d] %d %d.\n", txq_id,
3488 index, q->n_bd, q->write_ptr, q->read_ptr);
3489 return;
3490 }
3491
3492 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
3493 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
3494 if (nfreed > 1) {
3495 IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
3496 q->write_ptr, q->read_ptr);
3497 queue_work(priv->workqueue, &priv->restart);
3498 break;
3499 }
3500 nfreed++;
3501 }
3502}
3503
3504
b481de9c 3505/**
bb8c093b 3506 * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
b481de9c
ZY		 3507 * @rxb: Rx buffer to reclaim
3508 *
3509 * If an Rx buffer has an async callback associated with it the callback
3510 * will be executed. The attached skb (if present) will only be freed
3511 * if the callback returns 1
3512 */
bb8c093b
CH		 3513static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
3514 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3515{
bb8c093b 3516 struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
b481de9c
ZY		 3517 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3518 int txq_id = SEQ_TO_QUEUE(sequence);
3519 int index = SEQ_TO_INDEX(sequence);
3520 int huge = sequence & SEQ_HUGE_FRAME;
3521 int cmd_index;
bb8c093b 3522 struct iwl3945_cmd *cmd;
b481de9c 3523
b481de9c
ZY		 3524 BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
3525
3526 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
3527 cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
3528
3529 /* Input error checking is done when commands are added to queue. */
3530 if (cmd->meta.flags & CMD_WANT_SKB) {
3531 cmd->meta.source->u.skb = rxb->skb;
3532 rxb->skb = NULL;
3533 } else if (cmd->meta.u.callback &&
3534 !cmd->meta.u.callback(priv, cmd, rxb->skb))
3535 rxb->skb = NULL;
3536
91c066f2 3537 iwl3945_cmd_queue_reclaim(priv, txq_id, index);
b481de9c
ZY		 3538
3539 if (!(cmd->meta.flags & CMD_ASYNC)) {
3540 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
3541 wake_up_interruptible(&priv->wait_command_queue);
3542 }
3543}
3544
3545/************************** RX-FUNCTIONS ****************************/
3546/*
3547 * Rx theory of operation
3548 *
3549 * The host allocates 32 DMA target addresses and passes the host address
3550 * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
3551 * 0 to 31
3552 *
3553 * Rx Queue Indexes
3554 * The host/firmware share two index registers for managing the Rx buffers.
3555 *
3556 * The READ index maps to the first position that the firmware may be writing
3557 * to -- the driver can read up to (but not including) this position and get
3558 * good data.
3559 * The READ index is managed by the firmware once the card is enabled.
3560 *
3561 * The WRITE index maps to the last position the driver has read from -- the
3562 * position preceding WRITE is the last slot the firmware can place a packet.
3563 *
3564 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
3565 * WRITE = READ.
3566 *
9fbab516 3567 * During initialization, the host sets up the READ queue position to the first
b481de9c
ZY		 3568 * INDEX position, and WRITE to the last (READ - 1 wrapped)
3569 *
9fbab516 3570 * When the firmware places a packet in a buffer, it will advance the READ index
b481de9c
ZY		 3571 * and fire the RX interrupt. The driver can then query the READ index and
3572 * process as many packets as possible, moving the WRITE index forward as it
3573 * resets the Rx queue buffers with new memory.
3574 *
3575 * The management in the driver is as follows:
3576 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
3577 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
01ebd063 3578 * to replenish the iwl->rxq->rx_free.
bb8c093b 3579 * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
b481de9c
ZY		 3580 * iwl->rxq is replenished and the READ INDEX is updated (updating the
3581 * 'processed' and 'read' driver indexes as well)
3582 * + A received packet is processed and handed to the kernel network stack,
3583 * detached from the iwl->rxq. The driver 'processed' index is updated.
3584 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
3585 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
3586 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
3587 * were enough free buffers and RX_STALLED is set it is cleared.
3588 *
3589 *
3590 * Driver sequence:
3591 *
9fbab516
BC		 3592 * iwl3945_rx_queue_alloc() Allocates rx_free
3593 * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
bb8c093b 3594 * iwl3945_rx_queue_restock
9fbab516 3595 * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
b481de9c
ZY		 3596 * queue, updates firmware pointers, and updates
3597 * the WRITE index. If insufficient rx_free buffers
bb8c093b 3598 * are available, schedules iwl3945_rx_replenish
b481de9c
ZY		 3599 *
3600 * -- enable interrupts --
9fbab516 3601 * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the
b481de9c
ZY		 3602 * READ INDEX, detaching the SKB from the pool.
3603 * Moves the packet buffer from queue to rx_used.
bb8c093b 3604 * Calls iwl3945_rx_queue_restock to refill any empty
b481de9c
ZY		 3605 * slots.
3606 * ...
3607 *
3608 */
3609
3610/**
bb8c093b 3611 * iwl3945_rx_queue_space - Return number of free slots available in queue.
b481de9c 3612 */
bb8c093b 3613static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
b481de9c
ZY		 3614{
3615 int s = q->read - q->write;
3616 if (s <= 0)
3617 s += RX_QUEUE_SIZE;
3618 /* keep some buffer to not confuse full and empty queue */
3619 s -= 2;
3620 if (s < 0)
3621 s = 0;
3622 return s;
3623}
3624
3625/**
bb8c093b 3626 * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
b481de9c 3627 */
bb8c093b 3628int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
b481de9c
ZY		 3629{
3630 u32 reg = 0;
3631 int rc = 0;
3632 unsigned long flags;
3633
3634 spin_lock_irqsave(&q->lock, flags);
3635
3636 if (q->need_update == 0)
3637 goto exit_unlock;
3638
6440adb5 3639 /* If power-saving is in use, make sure device is awake */
b481de9c 3640 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
bb8c093b 3641 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY		 3642
3643 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
bb8c093b 3644 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 3645 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3646 goto exit_unlock;
3647 }
3648
bb8c093b 3649 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 3650 if (rc)
3651 goto exit_unlock;
3652
6440adb5 3653 /* Device expects a multiple of 8 */
bb8c093b 3654 iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
b481de9c 3655 q->write & ~0x7);
bb8c093b 3656 iwl3945_release_nic_access(priv);
6440adb5
CB		 3657
3658 /* Else device is assumed to be awake */
b481de9c 3659 } else
6440adb5 3660 /* Device expects a multiple of 8 */
bb8c093b 3661 iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
b481de9c
ZY		 3662
3663
3664 q->need_update = 0;
3665
3666 exit_unlock:
3667 spin_unlock_irqrestore(&q->lock, flags);
3668 return rc;
3669}
3670
3671/**
9fbab516 3672 * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
b481de9c 3673 */
bb8c093b 3674static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
b481de9c
ZY		 3675 dma_addr_t dma_addr)
3676{
3677 return cpu_to_le32((u32)dma_addr);
3678}
3679
3680/**
bb8c093b 3681 * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
b481de9c 3682 *
9fbab516 3683 * If there are slots in the RX queue that need to be restocked,
b481de9c 3684 * and we have free pre-allocated buffers, fill the ranks as much
9fbab516 3685 * as we can, pulling from rx_free.
b481de9c
ZY		 3686 *
3687 * This moves the 'write' index forward to catch up with 'processed', and
3688 * also updates the memory address in the firmware to reference the new
3689 * target buffer.
3690 */
bb8c093b 3691static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
b481de9c 3692{
bb8c093b 3693 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 3694 struct list_head *element;
bb8c093b 3695 struct iwl3945_rx_mem_buffer *rxb;
b481de9c
ZY		 3696 unsigned long flags;
3697 int write, rc;
3698
3699 spin_lock_irqsave(&rxq->lock, flags);
3700 write = rxq->write & ~0x7;
bb8c093b 3701 while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
6440adb5 3702 /* Get next free Rx buffer, remove from free list */
b481de9c 3703 element = rxq->rx_free.next;
bb8c093b 3704 rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
b481de9c 3705 list_del(element);
6440adb5
CB		 3706
3707 /* Point to Rx buffer via next RBD in circular buffer */
bb8c093b 3708 rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
b481de9c
ZY		 3709 rxq->queue[rxq->write] = rxb;
3710 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
3711 rxq->free_count--;
3712 }
3713 spin_unlock_irqrestore(&rxq->lock, flags);
3714 /* If the pre-allocated buffer pool is dropping low, schedule to
3715 * refill it */
3716 if (rxq->free_count <= RX_LOW_WATERMARK)
3717 queue_work(priv->workqueue, &priv->rx_replenish);
3718
3719
6440adb5
CB		 3720 /* If we've added more space for the firmware to place data, tell it.
3721 * Increment device's write pointer in multiples of 8. */
b481de9c
ZY		 3722 if ((write != (rxq->write & ~0x7))
3723 || (abs(rxq->write - rxq->read) > 7)) {
3724 spin_lock_irqsave(&rxq->lock, flags);
3725 rxq->need_update = 1;
3726 spin_unlock_irqrestore(&rxq->lock, flags);
bb8c093b 3727 rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 3728 if (rc)
3729 return rc;
3730 }
3731
3732 return 0;
3733}
3734
3735/**
bb8c093b 3736 * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
b481de9c
ZY		 3737 *
3738 * When moving to rx_free an SKB is allocated for the slot.
3739 *
bb8c093b 3740 * Also restock the Rx queue via iwl3945_rx_queue_restock.
01ebd063 3741 * This is called as a scheduled work item (except for during initialization)
b481de9c 3742 */
5c0eef96 3743static void iwl3945_rx_allocate(struct iwl3945_priv *priv)
b481de9c 3744{
bb8c093b 3745 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 3746 struct list_head *element;
bb8c093b 3747 struct iwl3945_rx_mem_buffer *rxb;
b481de9c
ZY		 3748 unsigned long flags;
3749 spin_lock_irqsave(&rxq->lock, flags);
3750 while (!list_empty(&rxq->rx_used)) {
3751 element = rxq->rx_used.next;
bb8c093b 3752 rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
6440adb5
CB		 3753
3754 /* Alloc a new receive buffer */
b481de9c
ZY		 3755 rxb->skb =
3756 alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
3757 if (!rxb->skb) {
3758 if (net_ratelimit())
3759 printk(KERN_CRIT DRV_NAME
3760 ": Can not allocate SKB buffers\n");
3761 /* We don't reschedule replenish work here -- we will
3762 * call the restock method and if it still needs
3763 * more buffers it will schedule replenish */
3764 break;
3765 }
12342c47
ZY		 3766
3767 /* If radiotap head is required, reserve some headroom here.
3768 * The physical head count is a variable rx_stats->phy_count.
3769 * We reserve 4 bytes here. Plus these extra bytes, the
3770 * headroom of the physical head should be enough for the
3771 * radiotap head that iwl3945 supported. See iwl3945_rt.
3772 */
3773 skb_reserve(rxb->skb, 4);
3774
b481de9c
ZY		 3775 priv->alloc_rxb_skb++;
3776 list_del(element);
6440adb5
CB		 3777
3778 /* Get physical address of RB/SKB */
b481de9c
ZY		 3779 rxb->dma_addr =
3780 pci_map_single(priv->pci_dev, rxb->skb->data,
3781 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3782 list_add_tail(&rxb->list, &rxq->rx_free);
3783 rxq->free_count++;
3784 }
3785 spin_unlock_irqrestore(&rxq->lock, flags);
5c0eef96
MA		 3786}
3787
3788/*
3789 * this should be called while priv->lock is locked
3790 */
4fd1f841 3791static void __iwl3945_rx_replenish(void *data)
5c0eef96
MA		 3792{
3793 struct iwl3945_priv *priv = data;
3794
3795 iwl3945_rx_allocate(priv);
3796 iwl3945_rx_queue_restock(priv);
3797}
3798
3799
3800void iwl3945_rx_replenish(void *data)
3801{
3802 struct iwl3945_priv *priv = data;
3803 unsigned long flags;
3804
3805 iwl3945_rx_allocate(priv);
b481de9c
ZY		 3806
3807 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 3808 iwl3945_rx_queue_restock(priv);
b481de9c
ZY		 3809 spin_unlock_irqrestore(&priv->lock, flags);
3810}
3811
3812/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
9fbab516 3813 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
b481de9c
ZY		 3814 * This free routine walks the list of POOL entries and if SKB is set to
3815 * non NULL it is unmapped and freed
3816 */
bb8c093b 3817static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY		 3818{
3819 int i;
3820 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
3821 if (rxq->pool[i].skb != NULL) {
3822 pci_unmap_single(priv->pci_dev,
3823 rxq->pool[i].dma_addr,
3824 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3825 dev_kfree_skb(rxq->pool[i].skb);
3826 }
3827 }
3828
3829 pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
3830 rxq->dma_addr);
3831 rxq->bd = NULL;
3832}
3833
bb8c093b 3834int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
b481de9c 3835{
bb8c093b 3836 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 3837 struct pci_dev *dev = priv->pci_dev;
3838 int i;
3839
3840 spin_lock_init(&rxq->lock);
3841 INIT_LIST_HEAD(&rxq->rx_free);
3842 INIT_LIST_HEAD(&rxq->rx_used);
6440adb5
CB		 3843
3844 /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
b481de9c
ZY		 3845 rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
3846 if (!rxq->bd)
3847 return -ENOMEM;
6440adb5 3848
b481de9c
ZY		 3849 /* Fill the rx_used queue with _all_ of the Rx buffers */
3850 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
3851 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
6440adb5 3852
b481de9c
ZY		 3853 /* Set us so that we have processed and used all buffers, but have
3854 * not restocked the Rx queue with fresh buffers */
3855 rxq->read = rxq->write = 0;
3856 rxq->free_count = 0;
3857 rxq->need_update = 0;
3858 return 0;
3859}
3860
bb8c093b 3861void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY		 3862{
3863 unsigned long flags;
3864 int i;
3865 spin_lock_irqsave(&rxq->lock, flags);
3866 INIT_LIST_HEAD(&rxq->rx_free);
3867 INIT_LIST_HEAD(&rxq->rx_used);
3868 /* Fill the rx_used queue with _all_ of the Rx buffers */
3869 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
3870 /* In the reset function, these buffers may have been allocated
3871 * to an SKB, so we need to unmap and free potential storage */
3872 if (rxq->pool[i].skb != NULL) {
3873 pci_unmap_single(priv->pci_dev,
3874 rxq->pool[i].dma_addr,
3875 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3876 priv->alloc_rxb_skb--;
3877 dev_kfree_skb(rxq->pool[i].skb);
3878 rxq->pool[i].skb = NULL;
3879 }
3880 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
3881 }
3882
3883 /* Set us so that we have processed and used all buffers, but have
3884 * not restocked the Rx queue with fresh buffers */
3885 rxq->read = rxq->write = 0;
3886 rxq->free_count = 0;
3887 spin_unlock_irqrestore(&rxq->lock, flags);
3888}
3889
3890/* Convert linear signal-to-noise ratio into dB */
3891static u8 ratio2dB[100] = {
3892/* 0 1 2 3 4 5 6 7 8 9 */
3893 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
3894 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
3895 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
3896 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
3897 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
3898 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
3899 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
3900 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
3901 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
3902 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
3903};
3904
3905/* Calculates a relative dB value from a ratio of linear
3906 * (i.e. not dB) signal levels.
3907 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
bb8c093b 3908int iwl3945_calc_db_from_ratio(int sig_ratio)
b481de9c 3909{
221c80cf
AB		 3910 /* 1000:1 or higher just report as 60 dB */
3911 if (sig_ratio >= 1000)
b481de9c
ZY		 3912 return 60;
3913
221c80cf 3914 /* 100:1 or higher, divide by 10 and use table,
b481de9c 3915 * add 20 dB to make up for divide by 10 */
221c80cf 3916 if (sig_ratio >= 100)
b481de9c
ZY		 3917 return (20 + (int)ratio2dB[sig_ratio/10]);
3918
3919 /* We shouldn't see this */
3920 if (sig_ratio < 1)
3921 return 0;
3922
3923 /* Use table for ratios 1:1 - 99:1 */
3924 return (int)ratio2dB[sig_ratio];
3925}
3926
3927#define PERFECT_RSSI (-20) /* dBm */
3928#define WORST_RSSI (-95) /* dBm */
3929#define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
3930
3931/* Calculate an indication of rx signal quality (a percentage, not dBm!).
3932 * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
3933 * about formulas used below. */
bb8c093b 3934int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
b481de9c
ZY		 3935{
3936 int sig_qual;
3937 int degradation = PERFECT_RSSI - rssi_dbm;
3938
3939 /* If we get a noise measurement, use signal-to-noise ratio (SNR)
3940 * as indicator; formula is (signal dbm - noise dbm).
3941 * SNR at or above 40 is a great signal (100%).
3942 * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
3943 * Weakest usable signal is usually 10 - 15 dB SNR. */
3944 if (noise_dbm) {
3945 if (rssi_dbm - noise_dbm >= 40)
3946 return 100;
3947 else if (rssi_dbm < noise_dbm)
3948 return 0;
3949 sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
3950
3951 /* Else use just the signal level.
3952 * This formula is a least squares fit of data points collected and
3953 * compared with a reference system that had a percentage (%) display
3954 * for signal quality. */
3955 } else
3956 sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
3957 (15 * RSSI_RANGE + 62 * degradation)) /
3958 (RSSI_RANGE * RSSI_RANGE);
3959
3960 if (sig_qual > 100)
3961 sig_qual = 100;
3962 else if (sig_qual < 1)
3963 sig_qual = 0;
3964
3965 return sig_qual;
3966}
3967
3968/**
9fbab516 3969 * iwl3945_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY		 3970 *
3971 * Uses the priv->rx_handlers callback function array to invoke
3972 * the appropriate handlers, including command responses,
3973 * frame-received notifications, and other notifications.
3974 */
bb8c093b 3975static void iwl3945_rx_handle(struct iwl3945_priv *priv)
b481de9c 3976{
bb8c093b
CH		 3977 struct iwl3945_rx_mem_buffer *rxb;
3978 struct iwl3945_rx_packet *pkt;
3979 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 3980 u32 r, i;
3981 int reclaim;
3982 unsigned long flags;
5c0eef96 3983 u8 fill_rx = 0;
d68ab680 3984 u32 count = 8;
b481de9c 3985
6440adb5
CB		 3986 /* uCode's read index (stored in shared DRAM) indicates the last Rx
3987 * buffer that the driver may process (last buffer filled by ucode). */
bb8c093b 3988 r = iwl3945_hw_get_rx_read(priv);
b481de9c
ZY		 3989 i = rxq->read;
3990
5c0eef96
MA		 3991 if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
3992 fill_rx = 1;
b481de9c
ZY		 3993 /* Rx interrupt, but nothing sent from uCode */
3994 if (i == r)
3995 IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
3996
3997 while (i != r) {
3998 rxb = rxq->queue[i];
3999
9fbab516 4000 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY		 4001 * then a bug has been introduced in the queue refilling
4002 * routines -- catch it here */
4003 BUG_ON(rxb == NULL);
4004
4005 rxq->queue[i] = NULL;
4006
4007 pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
4008 IWL_RX_BUF_SIZE,
4009 PCI_DMA_FROMDEVICE);
bb8c093b 4010 pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
b481de9c
ZY		 4011
4012 /* Reclaim a command buffer only if this packet is a response
4013 * to a (driver-originated) command.
4014 * If the packet (e.g. Rx frame) originated from uCode,
4015 * there is no command buffer to reclaim.
4016 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
4017 * but apparently a few don't get set; catch them here. */
4018 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
4019 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
4020 (pkt->hdr.cmd != REPLY_TX);
4021
4022 /* Based on type of command response or notification,
4023 * handle those that need handling via function in
bb8c093b 4024 * rx_handlers table. See iwl3945_setup_rx_handlers() */
b481de9c
ZY		 4025 if (priv->rx_handlers[pkt->hdr.cmd]) {
4026 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
4027 "r = %d, i = %d, %s, 0x%02x\n", r, i,
4028 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
4029 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
4030 } else {
4031 /* No handling needed */
4032 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
4033 "r %d i %d No handler needed for %s, 0x%02x\n",
4034 r, i, get_cmd_string(pkt->hdr.cmd),
4035 pkt->hdr.cmd);
4036 }
4037
4038 if (reclaim) {
9fbab516
BC		 4039 /* Invoke any callbacks, transfer the skb to caller, and
4040 * fire off the (possibly) blocking iwl3945_send_cmd()
b481de9c
ZY		 4041 * as we reclaim the driver command queue */
4042 if (rxb && rxb->skb)
bb8c093b 4043 iwl3945_tx_cmd_complete(priv, rxb);
b481de9c
ZY		 4044 else
4045 IWL_WARNING("Claim null rxb?\n");
4046 }
4047
4048 /* For now we just don't re-use anything. We can tweak this
4049 * later to try and re-use notification packets and SKBs that
4050 * fail to Rx correctly */
4051 if (rxb->skb != NULL) {
4052 priv->alloc_rxb_skb--;
4053 dev_kfree_skb_any(rxb->skb);
4054 rxb->skb = NULL;
4055 }
4056
4057 pci_unmap_single(priv->pci_dev, rxb->dma_addr,
4058 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
4059 spin_lock_irqsave(&rxq->lock, flags);
4060 list_add_tail(&rxb->list, &priv->rxq.rx_used);
4061 spin_unlock_irqrestore(&rxq->lock, flags);
4062 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA		 4063 /* If there are a lot of unused frames,
4064 * restock the Rx queue so ucode won't assert. */
4065 if (fill_rx) {
4066 count++;
4067 if (count >= 8) {
4068 priv->rxq.read = i;
4069 __iwl3945_rx_replenish(priv);
4070 count = 0;
4071 }
4072 }
b481de9c
ZY		 4073 }
4074
4075 /* Backtrack one entry */
4076 priv->rxq.read = i;
bb8c093b 4077 iwl3945_rx_queue_restock(priv);
b481de9c
ZY		 4078}
4079
6440adb5
CB		 4080/**
4081 * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
4082 */
bb8c093b
CH		 4083static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
4084 struct iwl3945_tx_queue *txq)
b481de9c
ZY		 4085{
4086 u32 reg = 0;
4087 int rc = 0;
4088 int txq_id = txq->q.id;
4089
4090 if (txq->need_update == 0)
4091 return rc;
4092
4093 /* if we're trying to save power */
4094 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
4095 /* wake up nic if it's powered down ...
4096 * uCode will wake up, and interrupt us again, so next
4097 * time we'll skip this part. */
bb8c093b 4098 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY		 4099
4100 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
4101 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
bb8c093b 4102 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 4103 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
4104 return rc;
4105 }
4106
4107 /* restore this queue's parameters in nic hardware. */
bb8c093b 4108 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 4109 if (rc)
4110 return rc;
bb8c093b 4111 iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
fc4b6853 4112 txq->q.write_ptr | (txq_id << 8));
bb8c093b 4113 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4114
4115 /* else not in power-save mode, uCode will never sleep when we're
4116 * trying to tx (during RFKILL, we're not trying to tx). */
4117 } else
bb8c093b 4118 iwl3945_write32(priv, HBUS_TARG_WRPTR,
fc4b6853 4119 txq->q.write_ptr | (txq_id << 8));
b481de9c
ZY		 4120
4121 txq->need_update = 0;
4122
4123 return rc;
4124}
4125
c8b0e6e1 4126#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4127static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon)
b481de9c 4128{
0795af57
JP		 4129 DECLARE_MAC_BUF(mac);
4130
b481de9c 4131 IWL_DEBUG_RADIO("RX CONFIG:\n");
bb8c093b 4132 iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
b481de9c
ZY		 4133 IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
4134 IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
4135 IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
4136 le32_to_cpu(rxon->filter_flags));
4137 IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
4138 IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
4139 rxon->ofdm_basic_rates);
4140 IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
0795af57
JP		 4141 IWL_DEBUG_RADIO("u8[6] node_addr: %s\n",
4142 print_mac(mac, rxon->node_addr));
4143 IWL_DEBUG_RADIO("u8[6] bssid_addr: %s\n",
4144 print_mac(mac, rxon->bssid_addr));
b481de9c
ZY		 4145 IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
4146}
4147#endif
4148
bb8c093b 4149static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
b481de9c
ZY		 4150{
4151 IWL_DEBUG_ISR("Enabling interrupts\n");
4152 set_bit(STATUS_INT_ENABLED, &priv->status);
bb8c093b 4153 iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
b481de9c
ZY		 4154}
4155
0359facc
MA		 4156
4157/* call this function to flush any scheduled tasklet */
4158static inline void iwl_synchronize_irq(struct iwl3945_priv *priv)
4159{
4160 /* wait to make sure we flush pedding tasklet*/
4161 synchronize_irq(priv->pci_dev->irq);
4162 tasklet_kill(&priv->irq_tasklet);
4163}
4164
4165
bb8c093b 4166static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
b481de9c
ZY		 4167{
4168 clear_bit(STATUS_INT_ENABLED, &priv->status);
4169
4170 /* disable interrupts from uCode/NIC to host */
bb8c093b 4171 iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY		 4172
4173 /* acknowledge/clear/reset any interrupts still pending
4174 * from uCode or flow handler (Rx/Tx DMA) */
bb8c093b
CH		 4175 iwl3945_write32(priv, CSR_INT, 0xffffffff);
4176 iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
b481de9c
ZY		 4177 IWL_DEBUG_ISR("Disabled interrupts\n");
4178}
4179
4180static const char *desc_lookup(int i)
4181{
4182 switch (i) {
4183 case 1:
4184 return "FAIL";
4185 case 2:
4186 return "BAD_PARAM";
4187 case 3:
4188 return "BAD_CHECKSUM";
4189 case 4:
4190 return "NMI_INTERRUPT";
4191 case 5:
4192 return "SYSASSERT";
4193 case 6:
4194 return "FATAL_ERROR";
4195 }
4196
4197 return "UNKNOWN";
4198}
4199
4200#define ERROR_START_OFFSET (1 * sizeof(u32))
4201#define ERROR_ELEM_SIZE (7 * sizeof(u32))
4202
bb8c093b 4203static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
b481de9c
ZY		 4204{
4205 u32 i;
4206 u32 desc, time, count, base, data1;
4207 u32 blink1, blink2, ilink1, ilink2;
4208 int rc;
4209
4210 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
4211
bb8c093b 4212 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 4213 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
4214 return;
4215 }
4216
bb8c093b 4217 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 4218 if (rc) {
4219 IWL_WARNING("Can not read from adapter at this time.\n");
4220 return;
4221 }
4222
bb8c093b 4223 count = iwl3945_read_targ_mem(priv, base);
b481de9c
ZY		 4224
4225 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
4226 IWL_ERROR("Start IWL Error Log Dump:\n");
2acae16e 4227 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
b481de9c
ZY		 4228 }
4229
4230 IWL_ERROR("Desc Time asrtPC blink2 "
4231 "ilink1 nmiPC Line\n");
4232 for (i = ERROR_START_OFFSET;
4233 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
4234 i += ERROR_ELEM_SIZE) {
bb8c093b 4235 desc = iwl3945_read_targ_mem(priv, base + i);
b481de9c 4236 time =
bb8c093b 4237 iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
b481de9c 4238 blink1 =
bb8c093b 4239 iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
b481de9c 4240 blink2 =
bb8c093b 4241 iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
b481de9c 4242 ilink1 =
bb8c093b 4243 iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
b481de9c 4244 ilink2 =
bb8c093b 4245 iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
b481de9c 4246 data1 =
bb8c093b 4247 iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
b481de9c
ZY		 4248
4249 IWL_ERROR
4250 ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
4251 desc_lookup(desc), desc, time, blink1, blink2,
4252 ilink1, ilink2, data1);
4253 }
4254
bb8c093b 4255 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4256
4257}
4258
f58177b9 4259#define EVENT_START_OFFSET (6 * sizeof(u32))
b481de9c
ZY		 4260
4261/**
bb8c093b 4262 * iwl3945_print_event_log - Dump error event log to syslog
b481de9c 4263 *
bb8c093b 4264 * NOTE: Must be called with iwl3945_grab_nic_access() already obtained!
b481de9c 4265 */
bb8c093b 4266static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
b481de9c
ZY		 4267 u32 num_events, u32 mode)
4268{
4269 u32 i;
4270 u32 base; /* SRAM byte address of event log header */
4271 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
4272 u32 ptr; /* SRAM byte address of log data */
4273 u32 ev, time, data; /* event log data */
4274
4275 if (num_events == 0)
4276 return;
4277
4278 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
4279
4280 if (mode == 0)
4281 event_size = 2 * sizeof(u32);
4282 else
4283 event_size = 3 * sizeof(u32);
4284
4285 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
4286
4287 /* "time" is actually "data" for mode 0 (no timestamp).
4288 * place event id # at far right for easier visual parsing. */
4289 for (i = 0; i < num_events; i++) {
bb8c093b 4290 ev = iwl3945_read_targ_mem(priv, ptr);
b481de9c 4291 ptr += sizeof(u32);
bb8c093b 4292 time = iwl3945_read_targ_mem(priv, ptr);
b481de9c
ZY		 4293 ptr += sizeof(u32);
4294 if (mode == 0)
4295 IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
4296 else {
bb8c093b 4297 data = iwl3945_read_targ_mem(priv, ptr);
b481de9c
ZY		 4298 ptr += sizeof(u32);
4299 IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
4300 }
4301 }
4302}
4303
bb8c093b 4304static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
b481de9c
ZY		 4305{
4306 int rc;
4307 u32 base; /* SRAM byte address of event log header */
4308 u32 capacity; /* event log capacity in # entries */
4309 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
4310 u32 num_wraps; /* # times uCode wrapped to top of log */
4311 u32 next_entry; /* index of next entry to be written by uCode */
4312 u32 size; /* # entries that we'll print */
4313
4314 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 4315 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 4316 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
4317 return;
4318 }
4319
bb8c093b 4320 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 4321 if (rc) {
4322 IWL_WARNING("Can not read from adapter at this time.\n");
4323 return;
4324 }
4325
4326 /* event log header */
bb8c093b
CH		 4327 capacity = iwl3945_read_targ_mem(priv, base);
4328 mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
4329 num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
4330 next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
b481de9c
ZY		 4331
4332 size = num_wraps ? capacity : next_entry;
4333
4334 /* bail out if nothing in log */
4335 if (size == 0) {
583fab37 4336 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
bb8c093b 4337 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4338 return;
4339 }
4340
583fab37 4341 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
b481de9c
ZY		 4342 size, num_wraps);
4343
4344 /* if uCode has wrapped back to top of log, start at the oldest entry,
4345 * i.e the next one that uCode would fill. */
4346 if (num_wraps)
bb8c093b 4347 iwl3945_print_event_log(priv, next_entry,
b481de9c
ZY		 4348 capacity - next_entry, mode);
4349
4350 /* (then/else) start at top of log */
bb8c093b 4351 iwl3945_print_event_log(priv, 0, next_entry, mode);
b481de9c 4352
bb8c093b 4353 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4354}
4355
4356/**
bb8c093b 4357 * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
b481de9c 4358 */
bb8c093b 4359static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
b481de9c 4360{
bb8c093b 4361 /* Set the FW error flag -- cleared on iwl3945_down */
b481de9c
ZY		 4362 set_bit(STATUS_FW_ERROR, &priv->status);
4363
4364 /* Cancel currently queued command. */
4365 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
4366
c8b0e6e1 4367#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 4368 if (iwl3945_debug_level & IWL_DL_FW_ERRORS) {
4369 iwl3945_dump_nic_error_log(priv);
4370 iwl3945_dump_nic_event_log(priv);
4371 iwl3945_print_rx_config_cmd(&priv->staging_rxon);
b481de9c
ZY		 4372 }
4373#endif
4374
4375 wake_up_interruptible(&priv->wait_command_queue);
4376
4377 /* Keep the restart process from trying to send host
4378 * commands by clearing the INIT status bit */
4379 clear_bit(STATUS_READY, &priv->status);
4380
4381 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
4382 IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
4383 "Restarting adapter due to uCode error.\n");
4384
bb8c093b 4385 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 4386 memcpy(&priv->recovery_rxon, &priv->active_rxon,
4387 sizeof(priv->recovery_rxon));
4388 priv->error_recovering = 1;
4389 }
4390 queue_work(priv->workqueue, &priv->restart);
4391 }
4392}
4393
bb8c093b 4394static void iwl3945_error_recovery(struct iwl3945_priv *priv)
b481de9c
ZY		 4395{
4396 unsigned long flags;
4397
4398 memcpy(&priv->staging_rxon, &priv->recovery_rxon,
4399 sizeof(priv->staging_rxon));
4400 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 4401 iwl3945_commit_rxon(priv);
b481de9c 4402
bb8c093b 4403 iwl3945_add_station(priv, priv->bssid, 1, 0);
b481de9c
ZY		 4404
4405 spin_lock_irqsave(&priv->lock, flags);
4406 priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
4407 priv->error_recovering = 0;
4408 spin_unlock_irqrestore(&priv->lock, flags);
4409}
4410
bb8c093b 4411static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
b481de9c
ZY		 4412{
4413 u32 inta, handled = 0;
4414 u32 inta_fh;
4415 unsigned long flags;
c8b0e6e1 4416#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 4417 u32 inta_mask;
4418#endif
4419
4420 spin_lock_irqsave(&priv->lock, flags);
4421
4422 /* Ack/clear/reset pending uCode interrupts.
4423 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
4424 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
bb8c093b
CH		 4425 inta = iwl3945_read32(priv, CSR_INT);
4426 iwl3945_write32(priv, CSR_INT, inta);
b481de9c
ZY		 4427
4428 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
4429 * Any new interrupts that happen after this, either while we're
4430 * in this tasklet, or later, will show up in next ISR/tasklet. */
bb8c093b
CH		 4431 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
4432 iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 4433
c8b0e6e1 4434#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4435 if (iwl3945_debug_level & IWL_DL_ISR) {
9fbab516
BC		 4436 /* just for debug */
4437 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
b481de9c
ZY		 4438 IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4439 inta, inta_mask, inta_fh);
4440 }
4441#endif
4442
4443 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
4444 * atomic, make sure that inta covers all the interrupts that
4445 * we've discovered, even if FH interrupt came in just after
4446 * reading CSR_INT. */
6f83eaa1 4447 if (inta_fh & CSR39_FH_INT_RX_MASK)
b481de9c 4448 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 4449 if (inta_fh & CSR39_FH_INT_TX_MASK)
b481de9c
ZY		 4450 inta |= CSR_INT_BIT_FH_TX;
4451
4452 /* Now service all interrupt bits discovered above. */
4453 if (inta & CSR_INT_BIT_HW_ERR) {
4454 IWL_ERROR("Microcode HW error detected. Restarting.\n");
4455
4456 /* Tell the device to stop sending interrupts */
bb8c093b 4457 iwl3945_disable_interrupts(priv);
b481de9c 4458
bb8c093b 4459 iwl3945_irq_handle_error(priv);
b481de9c
ZY		 4460
4461 handled |= CSR_INT_BIT_HW_ERR;
4462
4463 spin_unlock_irqrestore(&priv->lock, flags);
4464
4465 return;
4466 }
4467
c8b0e6e1 4468#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4469 if (iwl3945_debug_level & (IWL_DL_ISR)) {
b481de9c 4470 /* NIC fires this, but we don't use it, redundant with WAKEUP */
25c03d8e
JP		 4471 if (inta & CSR_INT_BIT_SCD)
4472 IWL_DEBUG_ISR("Scheduler finished to transmit "
4473 "the frame/frames.\n");
b481de9c
ZY		 4474
4475 /* Alive notification via Rx interrupt will do the real work */
4476 if (inta & CSR_INT_BIT_ALIVE)
4477 IWL_DEBUG_ISR("Alive interrupt\n");
4478 }
4479#endif
4480 /* Safely ignore these bits for debug checks below */
25c03d8e 4481 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c
ZY		 4482
4483 /* HW RF KILL switch toggled (4965 only) */
4484 if (inta & CSR_INT_BIT_RF_KILL) {
4485 int hw_rf_kill = 0;
bb8c093b 4486 if (!(iwl3945_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY		 4487 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
4488 hw_rf_kill = 1;
4489
4490 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR,
4491 "RF_KILL bit toggled to %s.\n",
4492 hw_rf_kill ? "disable radio":"enable radio");
4493
4494 /* Queue restart only if RF_KILL switch was set to "kill"
4495 * when we loaded driver, and is now set to "enable".
4496 * After we're Alive, RF_KILL gets handled by
3230455d 4497 * iwl3945_rx_card_state_notif() */
53e49093
ZY		 4498 if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) {
4499 clear_bit(STATUS_RF_KILL_HW, &priv->status);
b481de9c 4500 queue_work(priv->workqueue, &priv->restart);
53e49093 4501 }
b481de9c
ZY		 4502
4503 handled |= CSR_INT_BIT_RF_KILL;
4504 }
4505
4506 /* Chip got too hot and stopped itself (4965 only) */
4507 if (inta & CSR_INT_BIT_CT_KILL) {
4508 IWL_ERROR("Microcode CT kill error detected.\n");
4509 handled |= CSR_INT_BIT_CT_KILL;
4510 }
4511
4512 /* Error detected by uCode */
4513 if (inta & CSR_INT_BIT_SW_ERR) {
4514 IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
4515 inta);
bb8c093b 4516 iwl3945_irq_handle_error(priv);
b481de9c
ZY		 4517 handled |= CSR_INT_BIT_SW_ERR;
4518 }
4519
4520 /* uCode wakes up after power-down sleep */
4521 if (inta & CSR_INT_BIT_WAKEUP) {
4522 IWL_DEBUG_ISR("Wakeup interrupt\n");
bb8c093b
CH		 4523 iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
4524 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
4525 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
4526 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
4527 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
4528 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
4529 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
b481de9c
ZY		 4530
4531 handled |= CSR_INT_BIT_WAKEUP;
4532 }
4533
4534 /* All uCode command responses, including Tx command responses,
4535 * Rx "responses" (frame-received notification), and other
4536 * notifications from uCode come through here*/
4537 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
bb8c093b 4538 iwl3945_rx_handle(priv);
b481de9c
ZY		 4539 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
4540 }
4541
4542 if (inta & CSR_INT_BIT_FH_TX) {
4543 IWL_DEBUG_ISR("Tx interrupt\n");
4544
bb8c093b
CH		 4545 iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
4546 if (!iwl3945_grab_nic_access(priv)) {
4547 iwl3945_write_direct32(priv,
b481de9c
ZY		 4548 FH_TCSR_CREDIT
4549 (ALM_FH_SRVC_CHNL), 0x0);
bb8c093b 4550 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4551 }
4552 handled |= CSR_INT_BIT_FH_TX;
4553 }
4554
4555 if (inta & ~handled)
4556 IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
4557
4558 if (inta & ~CSR_INI_SET_MASK) {
4559 IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
4560 inta & ~CSR_INI_SET_MASK);
4561 IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
4562 }
4563
4564 /* Re-enable all interrupts */
0359facc
MA		 4565 /* only Re-enable if disabled by irq */
4566 if (test_bit(STATUS_INT_ENABLED, &priv->status))
4567 iwl3945_enable_interrupts(priv);
b481de9c 4568
c8b0e6e1 4569#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 4570 if (iwl3945_debug_level & (IWL_DL_ISR)) {
4571 inta = iwl3945_read32(priv, CSR_INT);
4572 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
4573 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY		 4574 IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4575 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
4576 }
4577#endif
4578 spin_unlock_irqrestore(&priv->lock, flags);
4579}
4580
bb8c093b 4581static irqreturn_t iwl3945_isr(int irq, void *data)
b481de9c 4582{
bb8c093b 4583 struct iwl3945_priv *priv = data;
b481de9c
ZY		 4584 u32 inta, inta_mask;
4585 u32 inta_fh;
4586 if (!priv)
4587 return IRQ_NONE;
4588
4589 spin_lock(&priv->lock);
4590
4591 /* Disable (but don't clear!) interrupts here to avoid
4592 * back-to-back ISRs and sporadic interrupts from our NIC.
4593 * If we have something to service, the tasklet will re-enable ints.
4594 * If we *don't* have something, we'll re-enable before leaving here. */
bb8c093b
CH		 4595 inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */
4596 iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY		 4597
4598 /* Discover which interrupts are active/pending */
bb8c093b
CH		 4599 inta = iwl3945_read32(priv, CSR_INT);
4600 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY		 4601
4602 /* Ignore interrupt if there's nothing in NIC to service.
4603 * This may be due to IRQ shared with another device,
4604 * or due to sporadic interrupts thrown from our NIC. */
4605 if (!inta && !inta_fh) {
4606 IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
4607 goto none;
4608 }
4609
4610 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
4611 /* Hardware disappeared */
4612 IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta);
cb4da1a3 4613 goto unplugged;
b481de9c
ZY		 4614 }
4615
4616 IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4617 inta, inta_mask, inta_fh);
4618
25c03d8e
JP		 4619 inta &= ~CSR_INT_BIT_SCD;
4620
bb8c093b 4621 /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
25c03d8e
JP		 4622 if (likely(inta || inta_fh))
4623 tasklet_schedule(&priv->irq_tasklet);
cb4da1a3 4624unplugged:
b481de9c
ZY		 4625 spin_unlock(&priv->lock);
4626
4627 return IRQ_HANDLED;
4628
4629 none:
4630 /* re-enable interrupts here since we don't have anything to service. */
0359facc
MA		 4631 /* only Re-enable if disabled by irq */
4632 if (test_bit(STATUS_INT_ENABLED, &priv->status))
4633 iwl3945_enable_interrupts(priv);
b481de9c
ZY		 4634 spin_unlock(&priv->lock);
4635 return IRQ_NONE;
4636}
4637
4638/************************** EEPROM BANDS ****************************
4639 *
bb8c093b 4640 * The iwl3945_eeprom_band definitions below provide the mapping from the
b481de9c
ZY		 4641 * EEPROM contents to the specific channel number supported for each
4642 * band.
4643 *
bb8c093b 4644 * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3
b481de9c
ZY		 4645 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
4646 * The specific geography and calibration information for that channel
4647 * is contained in the eeprom map itself.
4648 *
4649 * During init, we copy the eeprom information and channel map
4650 * information into priv->channel_info_24/52 and priv->channel_map_24/52
4651 *
4652 * channel_map_24/52 provides the index in the channel_info array for a
4653 * given channel. We have to have two separate maps as there is channel
4654 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
4655 * band_2
4656 *
4657 * A value of 0xff stored in the channel_map indicates that the channel
4658 * is not supported by the hardware at all.
4659 *
4660 * A value of 0xfe in the channel_map indicates that the channel is not
4661 * valid for Tx with the current hardware. This means that
4662 * while the system can tune and receive on a given channel, it may not
4663 * be able to associate or transmit any frames on that
4664 * channel. There is no corresponding channel information for that
4665 * entry.
4666 *
4667 *********************************************************************/
4668
4669/* 2.4 GHz */
bb8c093b 4670static const u8 iwl3945_eeprom_band_1[14] = {
b481de9c
ZY		 4671 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
4672};
4673
4674/* 5.2 GHz bands */
9fbab516 4675static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
b481de9c
ZY		 4676 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
4677};
4678
9fbab516 4679static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
b481de9c
ZY		 4680 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
4681};
4682
bb8c093b 4683static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
b481de9c
ZY		 4684 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
4685};
4686
bb8c093b 4687static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
b481de9c
ZY		 4688 145, 149, 153, 157, 161, 165
4689};
4690
bb8c093b 4691static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
b481de9c 4692 int *eeprom_ch_count,
bb8c093b 4693 const struct iwl3945_eeprom_channel
b481de9c
ZY		 4694 **eeprom_ch_info,
4695 const u8 **eeprom_ch_index)
4696{
4697 switch (band) {
4698 case 1: /* 2.4GHz band */
bb8c093b 4699 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
b481de9c 4700 *eeprom_ch_info = priv->eeprom.band_1_channels;
bb8c093b 4701 *eeprom_ch_index = iwl3945_eeprom_band_1;
b481de9c 4702 break;
9fbab516 4703 case 2: /* 4.9GHz band */
bb8c093b 4704 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
b481de9c 4705 *eeprom_ch_info = priv->eeprom.band_2_channels;
bb8c093b 4706 *eeprom_ch_index = iwl3945_eeprom_band_2;
b481de9c
ZY		 4707 break;
4708 case 3: /* 5.2GHz band */
bb8c093b 4709 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
b481de9c 4710 *eeprom_ch_info = priv->eeprom.band_3_channels;
bb8c093b 4711 *eeprom_ch_index = iwl3945_eeprom_band_3;
b481de9c 4712 break;
9fbab516 4713 case 4: /* 5.5GHz band */
bb8c093b 4714 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
b481de9c 4715 *eeprom_ch_info = priv->eeprom.band_4_channels;
bb8c093b 4716 *eeprom_ch_index = iwl3945_eeprom_band_4;
b481de9c 4717 break;
9fbab516 4718 case 5: /* 5.7GHz band */
bb8c093b 4719 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
b481de9c 4720 *eeprom_ch_info = priv->eeprom.band_5_channels;
bb8c093b 4721 *eeprom_ch_index = iwl3945_eeprom_band_5;
b481de9c
ZY		 4722 break;
4723 default:
4724 BUG();
4725 return;
4726 }
4727}
4728
6440adb5
CB		 4729/**
4730 * iwl3945_get_channel_info - Find driver's private channel info
4731 *
4732 * Based on band and channel number.
4733 */
bb8c093b 4734const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv,
8318d78a 4735 enum ieee80211_band band, u16 channel)
b481de9c
ZY		 4736{
4737 int i;
4738
8318d78a
JB		 4739 switch (band) {
4740 case IEEE80211_BAND_5GHZ:
b481de9c
ZY		 4741 for (i = 14; i < priv->channel_count; i++) {
4742 if (priv->channel_info[i].channel == channel)
4743 return &priv->channel_info[i];
4744 }
4745 break;
4746
8318d78a 4747 case IEEE80211_BAND_2GHZ:
b481de9c
ZY		 4748 if (channel >= 1 && channel <= 14)
4749 return &priv->channel_info[channel - 1];
4750 break;
8318d78a
JB		 4751 case IEEE80211_NUM_BANDS:
4752 WARN_ON(1);
b481de9c
ZY		 4753 }
4754
4755 return NULL;
4756}
4757
4758#define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
4759 ? # x " " : "")
4760
6440adb5
CB		 4761/**
4762 * iwl3945_init_channel_map - Set up driver's info for all possible channels
4763 */
bb8c093b 4764static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
b481de9c
ZY		 4765{
4766 int eeprom_ch_count = 0;
4767 const u8 *eeprom_ch_index = NULL;
bb8c093b 4768 const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL;
b481de9c 4769 int band, ch;
bb8c093b 4770 struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 4771
4772 if (priv->channel_count) {
4773 IWL_DEBUG_INFO("Channel map already initialized.\n");
4774 return 0;
4775 }
4776
4777 if (priv->eeprom.version < 0x2f) {
4778 IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
4779 priv->eeprom.version);
4780 return -EINVAL;
4781 }
4782
4783 IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
4784
4785 priv->channel_count =
bb8c093b
CH		 4786 ARRAY_SIZE(iwl3945_eeprom_band_1) +
4787 ARRAY_SIZE(iwl3945_eeprom_band_2) +
4788 ARRAY_SIZE(iwl3945_eeprom_band_3) +
4789 ARRAY_SIZE(iwl3945_eeprom_band_4) +
4790 ARRAY_SIZE(iwl3945_eeprom_band_5);
b481de9c
ZY		 4791
4792 IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
4793
bb8c093b 4794 priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) *
b481de9c
ZY		 4795 priv->channel_count, GFP_KERNEL);
4796 if (!priv->channel_info) {
4797 IWL_ERROR("Could not allocate channel_info\n");
4798 priv->channel_count = 0;
4799 return -ENOMEM;
4800 }
4801
4802 ch_info = priv->channel_info;
4803
4804 /* Loop through the 5 EEPROM bands adding them in order to the
4805 * channel map we maintain (that contains additional information than
4806 * what just in the EEPROM) */
4807 for (band = 1; band <= 5; band++) {
4808
bb8c093b 4809 iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
b481de9c
ZY		 4810 &eeprom_ch_info, &eeprom_ch_index);
4811
4812 /* Loop through each band adding each of the channels */
4813 for (ch = 0; ch < eeprom_ch_count; ch++) {
4814 ch_info->channel = eeprom_ch_index[ch];
8318d78a
JB		 4815 ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
4816 IEEE80211_BAND_5GHZ;
b481de9c
ZY		 4817
4818 /* permanently store EEPROM's channel regulatory flags
4819 * and max power in channel info database. */
4820 ch_info->eeprom = eeprom_ch_info[ch];
4821
4822 /* Copy the run-time flags so they are there even on
4823 * invalid channels */
4824 ch_info->flags = eeprom_ch_info[ch].flags;
4825
4826 if (!(is_channel_valid(ch_info))) {
4827 IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
4828 "No traffic\n",
4829 ch_info->channel,
4830 ch_info->flags,
4831 is_channel_a_band(ch_info) ?
4832 "5.2" : "2.4");
4833 ch_info++;
4834 continue;
4835 }
4836
4837 /* Initialize regulatory-based run-time data */
4838 ch_info->max_power_avg = ch_info->curr_txpow =
4839 eeprom_ch_info[ch].max_power_avg;
4840 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
4841 ch_info->min_power = 0;
4842
8211ef78 4843 IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s%s(0x%02x"
b481de9c
ZY		 4844 " %ddBm): Ad-Hoc %ssupported\n",
4845 ch_info->channel,
4846 is_channel_a_band(ch_info) ?
4847 "5.2" : "2.4",
8211ef78 4848 CHECK_AND_PRINT(VALID),
b481de9c
ZY		 4849 CHECK_AND_PRINT(IBSS),
4850 CHECK_AND_PRINT(ACTIVE),
4851 CHECK_AND_PRINT(RADAR),
4852 CHECK_AND_PRINT(WIDE),
4853 CHECK_AND_PRINT(NARROW),
4854 CHECK_AND_PRINT(DFS),
4855 eeprom_ch_info[ch].flags,
4856 eeprom_ch_info[ch].max_power_avg,
4857 ((eeprom_ch_info[ch].
4858 flags & EEPROM_CHANNEL_IBSS)
4859 && !(eeprom_ch_info[ch].
4860 flags & EEPROM_CHANNEL_RADAR))
4861 ? "" : "not ");
4862
4863 /* Set the user_txpower_limit to the highest power
4864 * supported by any channel */
4865 if (eeprom_ch_info[ch].max_power_avg >
4866 priv->user_txpower_limit)
4867 priv->user_txpower_limit =
4868 eeprom_ch_info[ch].max_power_avg;
4869
4870 ch_info++;
4871 }
4872 }
4873
6440adb5 4874 /* Set up txpower settings in driver for all channels */
b481de9c
ZY		 4875 if (iwl3945_txpower_set_from_eeprom(priv))
4876 return -EIO;
4877
4878 return 0;
4879}
4880
849e0dce
RC		 4881/*
4882 * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
4883 */
4884static void iwl3945_free_channel_map(struct iwl3945_priv *priv)
4885{
4886 kfree(priv->channel_info);
4887 priv->channel_count = 0;
4888}
4889
b481de9c
ZY		 4890/* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
4891 * sending probe req. This should be set long enough to hear probe responses
4892 * from more than one AP. */
4893#define IWL_ACTIVE_DWELL_TIME_24 (20) /* all times in msec */
4894#define IWL_ACTIVE_DWELL_TIME_52 (10)
4895
4896/* For faster active scanning, scan will move to the next channel if fewer than
4897 * PLCP_QUIET_THRESH packets are heard on this channel within
4898 * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
4899 * time if it's a quiet channel (nothing responded to our probe, and there's
4900 * no other traffic).
4901 * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
4902#define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
4903#define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(5) /* msec */
4904
4905/* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
4906 * Must be set longer than active dwell time.
4907 * For the most reliable scan, set > AP beacon interval (typically 100msec). */
4908#define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
4909#define IWL_PASSIVE_DWELL_TIME_52 (10)
4910#define IWL_PASSIVE_DWELL_BASE (100)
4911#define IWL_CHANNEL_TUNE_TIME 5
4912
8318d78a
JB		 4913static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv,
4914 enum ieee80211_band band)
b481de9c 4915{
8318d78a 4916 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 4917 return IWL_ACTIVE_DWELL_TIME_52;
4918 else
4919 return IWL_ACTIVE_DWELL_TIME_24;
4920}
4921
8318d78a
JB		 4922static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv,
4923 enum ieee80211_band band)
b481de9c 4924{
8318d78a
JB		 4925 u16 active = iwl3945_get_active_dwell_time(priv, band);
4926 u16 passive = (band == IEEE80211_BAND_2GHZ) ?
b481de9c
ZY		 4927 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
4928 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
4929
bb8c093b 4930 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 4931 /* If we're associated, we clamp the maximum passive
4932 * dwell time to be 98% of the beacon interval (minus
4933 * 2 * channel tune time) */
4934 passive = priv->beacon_int;
4935 if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
4936 passive = IWL_PASSIVE_DWELL_BASE;
4937 passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
4938 }
4939
4940 if (passive <= active)
4941 passive = active + 1;
4942
4943 return passive;
4944}
4945
8318d78a
JB		 4946static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv,
4947 enum ieee80211_band band,
b481de9c 4948 u8 is_active, u8 direct_mask,
bb8c093b 4949 struct iwl3945_scan_channel *scan_ch)
b481de9c
ZY		 4950{
4951 const struct ieee80211_channel *channels = NULL;
8318d78a 4952 const struct ieee80211_supported_band *sband;
bb8c093b 4953 const struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 4954 u16 passive_dwell = 0;
4955 u16 active_dwell = 0;
4956 int added, i;
4957
8318d78a
JB		 4958 sband = iwl3945_get_band(priv, band);
4959 if (!sband)
b481de9c
ZY		 4960 return 0;
4961
8318d78a 4962 channels = sband->channels;
b481de9c 4963
8318d78a
JB		 4964 active_dwell = iwl3945_get_active_dwell_time(priv, band);
4965 passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
b481de9c 4966
8318d78a
JB		 4967 for (i = 0, added = 0; i < sband->n_channels; i++) {
4968 if (channels[i].hw_value ==
b481de9c 4969 le16_to_cpu(priv->active_rxon.channel)) {
bb8c093b 4970 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 4971 IWL_DEBUG_SCAN
4972 ("Skipping current channel %d\n",
4973 le16_to_cpu(priv->active_rxon.channel));
4974 continue;
4975 }
4976 } else if (priv->only_active_channel)
4977 continue;
4978
8318d78a 4979 scan_ch->channel = channels[i].hw_value;
b481de9c 4980
8318d78a 4981 ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
b481de9c
ZY		 4982 if (!is_channel_valid(ch_info)) {
4983 IWL_DEBUG_SCAN("Channel %d is INVALID for this SKU.\n",
4984 scan_ch->channel);
4985 continue;
4986 }
4987
4988 if (!is_active || is_channel_passive(ch_info) ||
8318d78a 4989 (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN))
b481de9c
ZY		 4990 scan_ch->type = 0; /* passive */
4991 else
4992 scan_ch->type = 1; /* active */
4993
4994 if (scan_ch->type & 1)
4995 scan_ch->type |= (direct_mask << 1);
4996
4997 if (is_channel_narrow(ch_info))
4998 scan_ch->type |= (1 << 7);
4999
5000 scan_ch->active_dwell = cpu_to_le16(active_dwell);
5001 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
5002
9fbab516 5003 /* Set txpower levels to defaults */
b481de9c
ZY		 5004 scan_ch->tpc.dsp_atten = 110;
5005 /* scan_pwr_info->tpc.dsp_atten; */
5006
5007 /*scan_pwr_info->tpc.tx_gain; */
8318d78a 5008 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 5009 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
5010 else {
5011 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
5012 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
9fbab516 5013 * power level:
8a1b0245 5014 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
b481de9c
ZY		 5015 */
5016 }
5017
5018 IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
5019 scan_ch->channel,
5020 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
5021 (scan_ch->type & 1) ?
5022 active_dwell : passive_dwell);
5023
5024 scan_ch++;
5025 added++;
5026 }
5027
5028 IWL_DEBUG_SCAN("total channels to scan %d \n", added);
5029 return added;
5030}
5031
bb8c093b 5032static void iwl3945_init_hw_rates(struct iwl3945_priv *priv,
b481de9c
ZY		 5033 struct ieee80211_rate *rates)
5034{
5035 int i;
5036
5037 for (i = 0; i < IWL_RATE_COUNT; i++) {
8318d78a
JB		 5038 rates[i].bitrate = iwl3945_rates[i].ieee * 5;
5039 rates[i].hw_value = i; /* Rate scaling will work on indexes */
5040 rates[i].hw_value_short = i;
5041 rates[i].flags = 0;
5042 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
b481de9c 5043 /*
8318d78a 5044 * If CCK != 1M then set short preamble rate flag.
b481de9c 5045 */
bb8c093b 5046 rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
8318d78a 5047 0 : IEEE80211_RATE_SHORT_PREAMBLE;
b481de9c 5048 }
b481de9c
ZY		 5049 }
5050}
5051
5052/**
bb8c093b 5053 * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
b481de9c 5054 */
bb8c093b 5055static int iwl3945_init_geos(struct iwl3945_priv *priv)
b481de9c 5056{
bb8c093b 5057 struct iwl3945_channel_info *ch;
8211ef78 5058 struct ieee80211_supported_band *sband;
b481de9c
ZY		 5059 struct ieee80211_channel *channels;
5060 struct ieee80211_channel *geo_ch;
5061 struct ieee80211_rate *rates;
5062 int i = 0;
b481de9c 5063
8318d78a
JB		 5064 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
5065 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
b481de9c
ZY		 5066 IWL_DEBUG_INFO("Geography modes already initialized.\n");
5067 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
5068 return 0;
5069 }
5070
b481de9c
ZY		 5071 channels = kzalloc(sizeof(struct ieee80211_channel) *
5072 priv->channel_count, GFP_KERNEL);
8318d78a 5073 if (!channels)
b481de9c 5074 return -ENOMEM;
b481de9c 5075
8211ef78 5076 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
b481de9c
ZY		 5077 GFP_KERNEL);
5078 if (!rates) {
b481de9c
ZY		 5079 kfree(channels);
5080 return -ENOMEM;
5081 }
5082
b481de9c 5083 /* 5.2GHz channels start after the 2.4GHz channels */
8211ef78
TW		 5084 sband = &priv->bands[IEEE80211_BAND_5GHZ];
5085 sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
5086 /* just OFDM */
5087 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
5088 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
5089
5090 sband = &priv->bands[IEEE80211_BAND_2GHZ];
5091 sband->channels = channels;
5092 /* OFDM & CCK */
5093 sband->bitrates = rates;
5094 sband->n_bitrates = IWL_RATE_COUNT;
b481de9c
ZY		 5095
5096 priv->ieee_channels = channels;
5097 priv->ieee_rates = rates;
5098
bb8c093b 5099 iwl3945_init_hw_rates(priv, rates);
b481de9c 5100
8211ef78 5101 for (i = 0; i < priv->channel_count; i++) {
b481de9c
ZY		 5102 ch = &priv->channel_info[i];
5103
8211ef78
TW		 5104 /* FIXME: might be removed if scan is OK*/
5105 if (!is_channel_valid(ch))
b481de9c 5106 continue;
b481de9c
ZY		 5107
5108 if (is_channel_a_band(ch))
8211ef78 5109 sband = &priv->bands[IEEE80211_BAND_5GHZ];
8318d78a 5110 else
8211ef78 5111 sband = &priv->bands[IEEE80211_BAND_2GHZ];
b481de9c 5112
8211ef78
TW		 5113 geo_ch = &sband->channels[sband->n_channels++];
5114
5115 geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
8318d78a
JB		 5116 geo_ch->max_power = ch->max_power_avg;
5117 geo_ch->max_antenna_gain = 0xff;
7b72304d 5118 geo_ch->hw_value = ch->channel;
b481de9c
ZY		 5119
5120 if (is_channel_valid(ch)) {
8318d78a
JB		 5121 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
5122 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
b481de9c 5123
8318d78a
JB		 5124 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
5125 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
b481de9c
ZY		 5126
5127 if (ch->flags & EEPROM_CHANNEL_RADAR)
8318d78a 5128 geo_ch->flags |= IEEE80211_CHAN_RADAR;
b481de9c
ZY		 5129
5130 if (ch->max_power_avg > priv->max_channel_txpower_limit)
5131 priv->max_channel_txpower_limit =
5132 ch->max_power_avg;
8211ef78 5133 } else {
8318d78a 5134 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
8211ef78
TW		 5135 }
5136
5137 /* Save flags for reg domain usage */
5138 geo_ch->orig_flags = geo_ch->flags;
5139
5140 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
5141 ch->channel, geo_ch->center_freq,
5142 is_channel_a_band(ch) ? "5.2" : "2.4",
5143 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
5144 "restricted" : "valid",
5145 geo_ch->flags);
b481de9c
ZY		 5146 }
5147
82b9a121
TW		 5148 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
5149 priv->cfg->sku & IWL_SKU_A) {
b481de9c
ZY		 5150 printk(KERN_INFO DRV_NAME
5151 ": Incorrectly detected BG card as ABG. Please send "
5152 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
5153 priv->pci_dev->device, priv->pci_dev->subsystem_device);
82b9a121 5154 priv->cfg->sku &= ~IWL_SKU_A;
b481de9c
ZY		 5155 }
5156
5157 printk(KERN_INFO DRV_NAME
5158 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
8318d78a
JB		 5159 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
5160 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
b481de9c 5161
e0e0a67e
JL		 5162 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
5163 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
5164 &priv->bands[IEEE80211_BAND_2GHZ];
5165 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
5166 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
5167 &priv->bands[IEEE80211_BAND_5GHZ];
b481de9c 5168
b481de9c
ZY		 5169 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
5170
5171 return 0;
5172}
5173
849e0dce
RC		 5174/*
5175 * iwl3945_free_geos - undo allocations in iwl3945_init_geos
5176 */
5177static void iwl3945_free_geos(struct iwl3945_priv *priv)
5178{
849e0dce
RC		 5179 kfree(priv->ieee_channels);
5180 kfree(priv->ieee_rates);
5181 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
5182}
5183
b481de9c
ZY		 5184/******************************************************************************
5185 *
5186 * uCode download functions
5187 *
5188 ******************************************************************************/
5189
bb8c093b 5190static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv)
b481de9c 5191{
98c92211
TW		 5192 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
5193 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
5194 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
5195 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
5196 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
5197 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY		 5198}
5199
5200/**
bb8c093b 5201 * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
b481de9c
ZY		 5202 * looking at all data.
5203 */
bb8c093b 5204static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 * image, u32 len)
b481de9c
ZY		 5205{
5206 u32 val;
5207 u32 save_len = len;
5208 int rc = 0;
5209 u32 errcnt;
5210
5211 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5212
bb8c093b 5213 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5214 if (rc)
5215 return rc;
5216
bb8c093b 5217 iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
b481de9c
ZY		 5218
5219 errcnt = 0;
5220 for (; len > 0; len -= sizeof(u32), image++) {
5221 /* read data comes through single port, auto-incr addr */
5222 /* NOTE: Use the debugless read so we don't flood kernel log
5223 * if IWL_DL_IO is set */
bb8c093b 5224 val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY		 5225 if (val != le32_to_cpu(*image)) {
5226 IWL_ERROR("uCode INST section is invalid at "
5227 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5228 save_len - len, val, le32_to_cpu(*image));
5229 rc = -EIO;
5230 errcnt++;
5231 if (errcnt >= 20)
5232 break;
5233 }
5234 }
5235
bb8c093b 5236 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5237
5238 if (!errcnt)
bc434dd2 5239 IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
b481de9c
ZY		 5240
5241 return rc;
5242}
5243
5244
5245/**
bb8c093b 5246 * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
b481de9c
ZY		 5247 * using sample data 100 bytes apart. If these sample points are good,
5248 * it's a pretty good bet that everything between them is good, too.
5249 */
bb8c093b 5250static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len)
b481de9c
ZY		 5251{
5252 u32 val;
5253 int rc = 0;
5254 u32 errcnt = 0;
5255 u32 i;
5256
5257 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5258
bb8c093b 5259 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5260 if (rc)
5261 return rc;
5262
5263 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
5264 /* read data comes through single port, auto-incr addr */
5265 /* NOTE: Use the debugless read so we don't flood kernel log
5266 * if IWL_DL_IO is set */
bb8c093b 5267 iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
b481de9c 5268 i + RTC_INST_LOWER_BOUND);
bb8c093b 5269 val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY		 5270 if (val != le32_to_cpu(*image)) {
5271#if 0 /* Enable this if you want to see details */
5272 IWL_ERROR("uCode INST section is invalid at "
5273 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5274 i, val, *image);
5275#endif
5276 rc = -EIO;
5277 errcnt++;
5278 if (errcnt >= 3)
5279 break;
5280 }
5281 }
5282
bb8c093b 5283 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5284
5285 return rc;
5286}
5287
5288
5289/**
bb8c093b 5290 * iwl3945_verify_ucode - determine which instruction image is in SRAM,
b481de9c
ZY		 5291 * and verify its contents
5292 */
bb8c093b 5293static int iwl3945_verify_ucode(struct iwl3945_priv *priv)
b481de9c
ZY		 5294{
5295 __le32 *image;
5296 u32 len;
5297 int rc = 0;
5298
5299 /* Try bootstrap */
5300 image = (__le32 *)priv->ucode_boot.v_addr;
5301 len = priv->ucode_boot.len;
bb8c093b 5302 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5303 if (rc == 0) {
5304 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
5305 return 0;
5306 }
5307
5308 /* Try initialize */
5309 image = (__le32 *)priv->ucode_init.v_addr;
5310 len = priv->ucode_init.len;
bb8c093b 5311 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5312 if (rc == 0) {
5313 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
5314 return 0;
5315 }
5316
5317 /* Try runtime/protocol */
5318 image = (__le32 *)priv->ucode_code.v_addr;
5319 len = priv->ucode_code.len;
bb8c093b 5320 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5321 if (rc == 0) {
5322 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
5323 return 0;
5324 }
5325
5326 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
5327
9fbab516
BC		 5328 /* Since nothing seems to match, show first several data entries in
5329 * instruction SRAM, so maybe visual inspection will give a clue.
5330 * Selection of bootstrap image (vs. other images) is arbitrary. */
b481de9c
ZY		 5331 image = (__le32 *)priv->ucode_boot.v_addr;
5332 len = priv->ucode_boot.len;
bb8c093b 5333 rc = iwl3945_verify_inst_full(priv, image, len);
b481de9c
ZY		 5334
5335 return rc;
5336}
5337
5338
5339/* check contents of special bootstrap uCode SRAM */
bb8c093b 5340static int iwl3945_verify_bsm(struct iwl3945_priv *priv)
b481de9c
ZY		 5341{
5342 __le32 *image = priv->ucode_boot.v_addr;
5343 u32 len = priv->ucode_boot.len;
5344 u32 reg;
5345 u32 val;
5346
5347 IWL_DEBUG_INFO("Begin verify bsm\n");
5348
5349 /* verify BSM SRAM contents */
bb8c093b 5350 val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG);
b481de9c
ZY		 5351 for (reg = BSM_SRAM_LOWER_BOUND;
5352 reg < BSM_SRAM_LOWER_BOUND + len;
5353 reg += sizeof(u32), image ++) {
bb8c093b 5354 val = iwl3945_read_prph(priv, reg);
b481de9c
ZY		 5355 if (val != le32_to_cpu(*image)) {
5356 IWL_ERROR("BSM uCode verification failed at "
5357 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
5358 BSM_SRAM_LOWER_BOUND,
5359 reg - BSM_SRAM_LOWER_BOUND, len,
5360 val, le32_to_cpu(*image));
5361 return -EIO;
5362 }
5363 }
5364
5365 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
5366
5367 return 0;
5368}
5369
5370/**
bb8c093b 5371 * iwl3945_load_bsm - Load bootstrap instructions
b481de9c
ZY		 5372 *
5373 * BSM operation:
5374 *
5375 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
5376 * in special SRAM that does not power down during RFKILL. When powering back
5377 * up after power-saving sleeps (or during initial uCode load), the BSM loads
5378 * the bootstrap program into the on-board processor, and starts it.
5379 *
5380 * The bootstrap program loads (via DMA) instructions and data for a new
5381 * program from host DRAM locations indicated by the host driver in the
5382 * BSM_DRAM_* registers. Once the new program is loaded, it starts
5383 * automatically.
5384 *
5385 * When initializing the NIC, the host driver points the BSM to the
5386 * "initialize" uCode image. This uCode sets up some internal data, then
5387 * notifies host via "initialize alive" that it is complete.
5388 *
5389 * The host then replaces the BSM_DRAM_* pointer values to point to the
5390 * normal runtime uCode instructions and a backup uCode data cache buffer
5391 * (filled initially with starting data values for the on-board processor),
5392 * then triggers the "initialize" uCode to load and launch the runtime uCode,
5393 * which begins normal operation.
5394 *
5395 * When doing a power-save shutdown, runtime uCode saves data SRAM into
5396 * the backup data cache in DRAM before SRAM is powered down.
5397 *
5398 * When powering back up, the BSM loads the bootstrap program. This reloads
5399 * the runtime uCode instructions and the backup data cache into SRAM,
5400 * and re-launches the runtime uCode from where it left off.
5401 */
bb8c093b 5402static int iwl3945_load_bsm(struct iwl3945_priv *priv)
b481de9c
ZY		 5403{
5404 __le32 *image = priv->ucode_boot.v_addr;
5405 u32 len = priv->ucode_boot.len;
5406 dma_addr_t pinst;
5407 dma_addr_t pdata;
5408 u32 inst_len;
5409 u32 data_len;
5410 int rc;
5411 int i;
5412 u32 done;
5413 u32 reg_offset;
5414
5415 IWL_DEBUG_INFO("Begin load bsm\n");
5416
5417 /* make sure bootstrap program is no larger than BSM's SRAM size */
5418 if (len > IWL_MAX_BSM_SIZE)
5419 return -EINVAL;
5420
5421 /* Tell bootstrap uCode where to find the "Initialize" uCode
9fbab516 5422 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
bb8c093b 5423 * NOTE: iwl3945_initialize_alive_start() will replace these values,
b481de9c
ZY		 5424 * after the "initialize" uCode has run, to point to
5425 * runtime/protocol instructions and backup data cache. */
5426 pinst = priv->ucode_init.p_addr;
5427 pdata = priv->ucode_init_data.p_addr;
5428 inst_len = priv->ucode_init.len;
5429 data_len = priv->ucode_init_data.len;
5430
bb8c093b 5431 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5432 if (rc)
5433 return rc;
5434
bb8c093b
CH		 5435 iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5436 iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5437 iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
5438 iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
b481de9c
ZY		 5439
5440 /* Fill BSM memory with bootstrap instructions */
5441 for (reg_offset = BSM_SRAM_LOWER_BOUND;
5442 reg_offset < BSM_SRAM_LOWER_BOUND + len;
5443 reg_offset += sizeof(u32), image++)
bb8c093b 5444 _iwl3945_write_prph(priv, reg_offset,
b481de9c
ZY		 5445 le32_to_cpu(*image));
5446
bb8c093b 5447 rc = iwl3945_verify_bsm(priv);
b481de9c 5448 if (rc) {
bb8c093b 5449 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5450 return rc;
5451 }
5452
5453 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
bb8c093b
CH		 5454 iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
5455 iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG,
b481de9c 5456 RTC_INST_LOWER_BOUND);
bb8c093b 5457 iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
b481de9c
ZY		 5458
5459 /* Load bootstrap code into instruction SRAM now,
5460 * to prepare to load "initialize" uCode */
bb8c093b 5461 iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY		 5462 BSM_WR_CTRL_REG_BIT_START);
5463
5464 /* Wait for load of bootstrap uCode to finish */
5465 for (i = 0; i < 100; i++) {
bb8c093b 5466 done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG);
b481de9c
ZY		 5467 if (!(done & BSM_WR_CTRL_REG_BIT_START))
5468 break;
5469 udelay(10);
5470 }
5471 if (i < 100)
5472 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
5473 else {
5474 IWL_ERROR("BSM write did not complete!\n");
5475 return -EIO;
5476 }
5477
5478 /* Enable future boot loads whenever power management unit triggers it
5479 * (e.g. when powering back up after power-save shutdown) */
bb8c093b 5480 iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY		 5481 BSM_WR_CTRL_REG_BIT_START_EN);
5482
bb8c093b 5483 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5484
5485 return 0;
5486}
5487
bb8c093b 5488static void iwl3945_nic_start(struct iwl3945_priv *priv)
b481de9c
ZY		 5489{
5490 /* Remove all resets to allow NIC to operate */
bb8c093b 5491 iwl3945_write32(priv, CSR_RESET, 0);
b481de9c
ZY		 5492}
5493
5494/**
bb8c093b 5495 * iwl3945_read_ucode - Read uCode images from disk file.
b481de9c
ZY		 5496 *
5497 * Copy into buffers for card to fetch via bus-mastering
5498 */
bb8c093b 5499static int iwl3945_read_ucode(struct iwl3945_priv *priv)
b481de9c 5500{
bb8c093b 5501 struct iwl3945_ucode *ucode;
90e759d1 5502 int ret = 0;
b481de9c
ZY		 5503 const struct firmware *ucode_raw;
5504 /* firmware file name contains uCode/driver compatibility version */
4bf775cd 5505 const char *name = priv->cfg->fw_name;
b481de9c
ZY		 5506 u8 *src;
5507 size_t len;
5508 u32 ver, inst_size, data_size, init_size, init_data_size, boot_size;
5509
5510 /* Ask kernel firmware_class module to get the boot firmware off disk.
5511 * request_firmware() is synchronous, file is in memory on return. */
90e759d1
TW		 5512 ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev);
5513 if (ret < 0) {
5514 IWL_ERROR("%s firmware file req failed: Reason %d\n",
5515 name, ret);
b481de9c
ZY		 5516 goto error;
5517 }
5518
5519 IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
5520 name, ucode_raw->size);
5521
5522 /* Make sure that we got at least our header! */
5523 if (ucode_raw->size < sizeof(*ucode)) {
5524 IWL_ERROR("File size way too small!\n");
90e759d1 5525 ret = -EINVAL;
b481de9c
ZY		 5526 goto err_release;
5527 }
5528
5529 /* Data from ucode file: header followed by uCode images */
5530 ucode = (void *)ucode_raw->data;
5531
5532 ver = le32_to_cpu(ucode->ver);
5533 inst_size = le32_to_cpu(ucode->inst_size);
5534 data_size = le32_to_cpu(ucode->data_size);
5535 init_size = le32_to_cpu(ucode->init_size);
5536 init_data_size = le32_to_cpu(ucode->init_data_size);
5537 boot_size = le32_to_cpu(ucode->boot_size);
5538
5539 IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver);
bc434dd2
IS		 5540 IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
5541 IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
5542 IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
5543 IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
5544 IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
b481de9c
ZY		 5545
5546 /* Verify size of file vs. image size info in file's header */
5547 if (ucode_raw->size < sizeof(*ucode) +
5548 inst_size + data_size + init_size +
5549 init_data_size + boot_size) {
5550
5551 IWL_DEBUG_INFO("uCode file size %d too small\n",
5552 (int)ucode_raw->size);
90e759d1 5553 ret = -EINVAL;
b481de9c
ZY		 5554 goto err_release;
5555 }
5556
5557 /* Verify that uCode images will fit in card's SRAM */
5558 if (inst_size > IWL_MAX_INST_SIZE) {
90e759d1
TW		 5559 IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
5560 inst_size);
5561 ret = -EINVAL;
b481de9c
ZY		 5562 goto err_release;
5563 }
5564
5565 if (data_size > IWL_MAX_DATA_SIZE) {
90e759d1
TW		 5566 IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
5567 data_size);
5568 ret = -EINVAL;
b481de9c
ZY		 5569 goto err_release;
5570 }
5571 if (init_size > IWL_MAX_INST_SIZE) {
90e759d1
TW		 5572 IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
5573 init_size);
5574 ret = -EINVAL;
b481de9c
ZY		 5575 goto err_release;
5576 }
5577 if (init_data_size > IWL_MAX_DATA_SIZE) {
90e759d1
TW		 5578 IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
5579 init_data_size);
5580 ret = -EINVAL;
b481de9c
ZY		 5581 goto err_release;
5582 }
5583 if (boot_size > IWL_MAX_BSM_SIZE) {
90e759d1
TW		 5584 IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
5585 boot_size);
5586 ret = -EINVAL;
b481de9c
ZY		 5587 goto err_release;
5588 }
5589
5590 /* Allocate ucode buffers for card's bus-master loading ... */
5591
5592 /* Runtime instructions and 2 copies of data:
5593 * 1) unmodified from disk
5594 * 2) backup cache for save/restore during power-downs */
5595 priv->ucode_code.len = inst_size;
98c92211 5596 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY		 5597
5598 priv->ucode_data.len = data_size;
98c92211 5599 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY		 5600
5601 priv->ucode_data_backup.len = data_size;
98c92211 5602 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 5603
90e759d1
TW		 5604 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
5605 !priv->ucode_data_backup.v_addr)
5606 goto err_pci_alloc;
b481de9c
ZY		 5607
5608 /* Initialization instructions and data */
90e759d1
TW		 5609 if (init_size && init_data_size) {
5610 priv->ucode_init.len = init_size;
98c92211 5611 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW		 5612
5613 priv->ucode_init_data.len = init_data_size;
98c92211 5614 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW		 5615
5616 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
5617 goto err_pci_alloc;
5618 }
b481de9c
ZY		 5619
5620 /* Bootstrap (instructions only, no data) */
90e759d1
TW		 5621 if (boot_size) {
5622 priv->ucode_boot.len = boot_size;
98c92211 5623 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 5624
90e759d1
TW		 5625 if (!priv->ucode_boot.v_addr)
5626 goto err_pci_alloc;
5627 }
b481de9c
ZY		 5628
5629 /* Copy images into buffers for card's bus-master reads ... */
5630
5631 /* Runtime instructions (first block of data in file) */
5632 src = &ucode->data[0];
5633 len = priv->ucode_code.len;
90e759d1 5634 IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c
ZY		 5635 memcpy(priv->ucode_code.v_addr, src, len);
5636 IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
5637 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
5638
5639 /* Runtime data (2nd block)
bb8c093b 5640 * NOTE: Copy into backup buffer will be done in iwl3945_up() */
b481de9c
ZY		 5641 src = &ucode->data[inst_size];
5642 len = priv->ucode_data.len;
90e759d1 5643 IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY		 5644 memcpy(priv->ucode_data.v_addr, src, len);
5645 memcpy(priv->ucode_data_backup.v_addr, src, len);
5646
5647 /* Initialization instructions (3rd block) */
5648 if (init_size) {
5649 src = &ucode->data[inst_size + data_size];
5650 len = priv->ucode_init.len;
90e759d1
TW		 5651 IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
5652 len);
b481de9c
ZY		 5653 memcpy(priv->ucode_init.v_addr, src, len);
5654 }
5655
5656 /* Initialization data (4th block) */
5657 if (init_data_size) {
5658 src = &ucode->data[inst_size + data_size + init_size];
5659 len = priv->ucode_init_data.len;
5660 IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
5661 (int)len);
5662 memcpy(priv->ucode_init_data.v_addr, src, len);
5663 }
5664
5665 /* Bootstrap instructions (5th block) */
5666 src = &ucode->data[inst_size + data_size + init_size + init_data_size];
5667 len = priv->ucode_boot.len;
5668 IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
5669 (int)len);
5670 memcpy(priv->ucode_boot.v_addr, src, len);
5671
5672 /* We have our copies now, allow OS release its copies */
5673 release_firmware(ucode_raw);
5674 return 0;
5675
5676 err_pci_alloc:
5677 IWL_ERROR("failed to allocate pci memory\n");
90e759d1 5678 ret = -ENOMEM;
bb8c093b 5679 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY		 5680
5681 err_release:
5682 release_firmware(ucode_raw);
5683
5684 error:
90e759d1 5685 return ret;
b481de9c
ZY		 5686}
5687
5688
5689/**
bb8c093b 5690 * iwl3945_set_ucode_ptrs - Set uCode address location
b481de9c
ZY		 5691 *
5692 * Tell initialization uCode where to find runtime uCode.
5693 *
5694 * BSM registers initially contain pointers to initialization uCode.
5695 * We need to replace them to load runtime uCode inst and data,
5696 * and to save runtime data when powering down.
5697 */
bb8c093b 5698static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv)
b481de9c
ZY		 5699{
5700 dma_addr_t pinst;
5701 dma_addr_t pdata;
5702 int rc = 0;
5703 unsigned long flags;
5704
5705 /* bits 31:0 for 3945 */
5706 pinst = priv->ucode_code.p_addr;
5707 pdata = priv->ucode_data_backup.p_addr;
5708
5709 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5710 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5711 if (rc) {
5712 spin_unlock_irqrestore(&priv->lock, flags);
5713 return rc;
5714 }
5715
5716 /* Tell bootstrap uCode where to find image to load */
bb8c093b
CH		 5717 iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5718 iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5719 iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
b481de9c
ZY		 5720 priv->ucode_data.len);
5721
5722 /* Inst bytecount must be last to set up, bit 31 signals uCode
5723 * that all new ptr/size info is in place */
bb8c093b 5724 iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
b481de9c
ZY		 5725 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
5726
bb8c093b 5727 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5728
5729 spin_unlock_irqrestore(&priv->lock, flags);
5730
5731 IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
5732
5733 return rc;
5734}
5735
5736/**
bb8c093b 5737 * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
b481de9c
ZY		 5738 *
5739 * Called after REPLY_ALIVE notification received from "initialize" uCode.
5740 *
b481de9c 5741 * Tell "initialize" uCode to go ahead and load the runtime uCode.
9fbab516 5742 */
bb8c093b 5743static void iwl3945_init_alive_start(struct iwl3945_priv *priv)
b481de9c
ZY		 5744{
5745 /* Check alive response for "valid" sign from uCode */
5746 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
5747 /* We had an error bringing up the hardware, so take it
5748 * all the way back down so we can try again */
5749 IWL_DEBUG_INFO("Initialize Alive failed.\n");
5750 goto restart;
5751 }
5752
5753 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
5754 * This is a paranoid check, because we would not have gotten the
5755 * "initialize" alive if code weren't properly loaded. */
bb8c093b 5756 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY		 5757 /* Runtime instruction load was bad;
5758 * take it all the way back down so we can try again */
5759 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
5760 goto restart;
5761 }
5762
5763 /* Send pointers to protocol/runtime uCode image ... init code will
5764 * load and launch runtime uCode, which will send us another "Alive"
5765 * notification. */
5766 IWL_DEBUG_INFO("Initialization Alive received.\n");
bb8c093b 5767 if (iwl3945_set_ucode_ptrs(priv)) {
b481de9c
ZY		 5768 /* Runtime instruction load won't happen;
5769 * take it all the way back down so we can try again */
5770 IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
5771 goto restart;
5772 }
5773 return;
5774
5775 restart:
5776 queue_work(priv->workqueue, &priv->restart);
5777}
5778
5779
5780/**
bb8c093b 5781 * iwl3945_alive_start - called after REPLY_ALIVE notification received
b481de9c 5782 * from protocol/runtime uCode (initialization uCode's
bb8c093b 5783 * Alive gets handled by iwl3945_init_alive_start()).
b481de9c 5784 */
bb8c093b 5785static void iwl3945_alive_start(struct iwl3945_priv *priv)
b481de9c
ZY		 5786{
5787 int rc = 0;
5788 int thermal_spin = 0;
5789 u32 rfkill;
5790
5791 IWL_DEBUG_INFO("Runtime Alive received.\n");
5792
5793 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
5794 /* We had an error bringing up the hardware, so take it
5795 * all the way back down so we can try again */
5796 IWL_DEBUG_INFO("Alive failed.\n");
5797 goto restart;
5798 }
5799
5800 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
5801 * This is a paranoid check, because we would not have gotten the
5802 * "runtime" alive if code weren't properly loaded. */
bb8c093b 5803 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY		 5804 /* Runtime instruction load was bad;
5805 * take it all the way back down so we can try again */
5806 IWL_DEBUG_INFO("Bad runtime uCode load.\n");
5807 goto restart;
5808 }
5809
bb8c093b 5810 iwl3945_clear_stations_table(priv);
b481de9c 5811
bb8c093b 5812 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5813 if (rc) {
5814 IWL_WARNING("Can not read rfkill status from adapter\n");
5815 return;
5816 }
5817
bb8c093b 5818 rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG);
b481de9c 5819 IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
bb8c093b 5820 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5821
5822 if (rfkill & 0x1) {
5823 clear_bit(STATUS_RF_KILL_HW, &priv->status);
5824 /* if rfkill is not on, then wait for thermal
5825 * sensor in adapter to kick in */
bb8c093b 5826 while (iwl3945_hw_get_temperature(priv) == 0) {
b481de9c
ZY		 5827 thermal_spin++;
5828 udelay(10);
5829 }
5830
5831 if (thermal_spin)
5832 IWL_DEBUG_INFO("Thermal calibration took %dus\n",
5833 thermal_spin * 10);
5834 } else
5835 set_bit(STATUS_RF_KILL_HW, &priv->status);
5836
9fbab516 5837 /* After the ALIVE response, we can send commands to 3945 uCode */
b481de9c
ZY		 5838 set_bit(STATUS_ALIVE, &priv->status);
5839
5840 /* Clear out the uCode error bit if it is set */
5841 clear_bit(STATUS_FW_ERROR, &priv->status);
5842
bb8c093b 5843 if (iwl3945_is_rfkill(priv))
b481de9c
ZY		 5844 return;
5845
5a66926a 5846 ieee80211_start_queues(priv->hw);
b481de9c
ZY		 5847
5848 priv->active_rate = priv->rates_mask;
5849 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
5850
bb8c093b 5851 iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
b481de9c 5852
bb8c093b
CH		 5853 if (iwl3945_is_associated(priv)) {
5854 struct iwl3945_rxon_cmd *active_rxon =
5855 (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
b481de9c
ZY		 5856
5857 memcpy(&priv->staging_rxon, &priv->active_rxon,
5858 sizeof(priv->staging_rxon));
5859 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5860 } else {
5861 /* Initialize our rx_config data */
bb8c093b 5862 iwl3945_connection_init_rx_config(priv);
b481de9c
ZY		 5863 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
5864 }
5865
9fbab516 5866 /* Configure Bluetooth device coexistence support */
bb8c093b 5867 iwl3945_send_bt_config(priv);
b481de9c
ZY		 5868
5869 /* Configure the adapter for unassociated operation */
bb8c093b 5870 iwl3945_commit_rxon(priv);
b481de9c
ZY		 5871
5872 /* At this point, the NIC is initialized and operational */
5873 priv->notif_missed_beacons = 0;
b481de9c
ZY		 5874
5875 iwl3945_reg_txpower_periodic(priv);
5876
5877 IWL_DEBUG_INFO("ALIVE processing complete.\n");
a9f46786 5878 set_bit(STATUS_READY, &priv->status);
5a66926a 5879 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 5880
ab53d8af
MA		 5881 iwl3945_led_register(priv);
5882
b481de9c 5883 if (priv->error_recovering)
bb8c093b 5884 iwl3945_error_recovery(priv);
b481de9c
ZY		 5885
5886 return;
5887
5888 restart:
5889 queue_work(priv->workqueue, &priv->restart);
5890}
5891
bb8c093b 5892static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv);
b481de9c 5893
bb8c093b 5894static void __iwl3945_down(struct iwl3945_priv *priv)
b481de9c
ZY		 5895{
5896 unsigned long flags;
5897 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
5898 struct ieee80211_conf *conf = NULL;
5899
5900 IWL_DEBUG_INFO(DRV_NAME " is going down\n");
5901
5902 conf = ieee80211_get_hw_conf(priv->hw);
5903
5904 if (!exit_pending)
5905 set_bit(STATUS_EXIT_PENDING, &priv->status);
5906
ab53d8af 5907 iwl3945_led_unregister(priv);
bb8c093b 5908 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 5909
5910 /* Unblock any waiting calls */
5911 wake_up_interruptible_all(&priv->wait_command_queue);
5912
b481de9c
ZY		 5913 /* Wipe out the EXIT_PENDING status bit if we are not actually
5914 * exiting the module */
5915 if (!exit_pending)
5916 clear_bit(STATUS_EXIT_PENDING, &priv->status);
5917
5918 /* stop and reset the on-board processor */
bb8c093b 5919 iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY		 5920
5921 /* tell the device to stop sending interrupts */
0359facc 5922 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5923 iwl3945_disable_interrupts(priv);
0359facc
MA		 5924 spin_unlock_irqrestore(&priv->lock, flags);
5925 iwl_synchronize_irq(priv);
b481de9c
ZY		 5926
5927 if (priv->mac80211_registered)
5928 ieee80211_stop_queues(priv->hw);
5929
bb8c093b 5930 /* If we have not previously called iwl3945_init() then
b481de9c 5931 * clear all bits but the RF Kill and SUSPEND bits and return */
bb8c093b 5932 if (!iwl3945_is_init(priv)) {
b481de9c
ZY		 5933 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
5934 STATUS_RF_KILL_HW |
5935 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
5936 STATUS_RF_KILL_SW |
9788864e
RC		 5937 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
5938 STATUS_GEO_CONFIGURED |
b481de9c
ZY		 5939 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
5940 STATUS_IN_SUSPEND;
5941 goto exit;
5942 }
5943
5944 /* ...otherwise clear out all the status bits but the RF Kill and
5945 * SUSPEND bits and continue taking the NIC down. */
5946 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
5947 STATUS_RF_KILL_HW |
5948 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
5949 STATUS_RF_KILL_SW |
9788864e
RC		 5950 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
5951 STATUS_GEO_CONFIGURED |
b481de9c
ZY		 5952 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
5953 STATUS_IN_SUSPEND |
5954 test_bit(STATUS_FW_ERROR, &priv->status) <<
5955 STATUS_FW_ERROR;
5956
5957 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5958 iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY		 5959 spin_unlock_irqrestore(&priv->lock, flags);
5960
bb8c093b
CH		 5961 iwl3945_hw_txq_ctx_stop(priv);
5962 iwl3945_hw_rxq_stop(priv);
b481de9c
ZY		 5963
5964 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH		 5965 if (!iwl3945_grab_nic_access(priv)) {
5966 iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
b481de9c 5967 APMG_CLK_VAL_DMA_CLK_RQT);
bb8c093b 5968 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5969 }
5970 spin_unlock_irqrestore(&priv->lock, flags);
5971
5972 udelay(5);
5973
bb8c093b
CH		 5974 iwl3945_hw_nic_stop_master(priv);
5975 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
5976 iwl3945_hw_nic_reset(priv);
b481de9c
ZY		 5977
5978 exit:
bb8c093b 5979 memset(&priv->card_alive, 0, sizeof(struct iwl3945_alive_resp));
b481de9c
ZY		 5980
5981 if (priv->ibss_beacon)
5982 dev_kfree_skb(priv->ibss_beacon);
5983 priv->ibss_beacon = NULL;
5984
5985 /* clear out any free frames */
bb8c093b 5986 iwl3945_clear_free_frames(priv);
b481de9c
ZY		 5987}
5988
bb8c093b 5989static void iwl3945_down(struct iwl3945_priv *priv)
b481de9c
ZY		 5990{
5991 mutex_lock(&priv->mutex);
bb8c093b 5992 __iwl3945_down(priv);
b481de9c 5993 mutex_unlock(&priv->mutex);
b24d22b1 5994
bb8c093b 5995 iwl3945_cancel_deferred_work(priv);
b481de9c
ZY		 5996}
5997
5998#define MAX_HW_RESTARTS 5
5999
bb8c093b 6000static int __iwl3945_up(struct iwl3945_priv *priv)
b481de9c
ZY		 6001{
6002 int rc, i;
6003
6004 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
6005 IWL_WARNING("Exit pending; will not bring the NIC up\n");
6006 return -EIO;
6007 }
6008
6009 if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
6010 IWL_WARNING("Radio disabled by SW RF kill (module "
6011 "parameter)\n");
e655b9f0
ZY		 6012 return -ENODEV;
6013 }
6014
e903fbd4
RC		 6015 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
6016 IWL_ERROR("ucode not available for device bringup\n");
6017 return -EIO;
6018 }
6019
e655b9f0
ZY		 6020 /* If platform's RF_KILL switch is NOT set to KILL */
6021 if (iwl3945_read32(priv, CSR_GP_CNTRL) &
6022 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
6023 clear_bit(STATUS_RF_KILL_HW, &priv->status);
6024 else {
6025 set_bit(STATUS_RF_KILL_HW, &priv->status);
6026 if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
6027 IWL_WARNING("Radio disabled by HW RF Kill switch\n");
6028 return -ENODEV;
6029 }
b481de9c
ZY		 6030 }
6031
bb8c093b 6032 iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 6033
bb8c093b 6034 rc = iwl3945_hw_nic_init(priv);
b481de9c
ZY		 6035 if (rc) {
6036 IWL_ERROR("Unable to int nic\n");
6037 return rc;
6038 }
6039
6040 /* make sure rfkill handshake bits are cleared */
bb8c093b
CH		 6041 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
6042 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 6043 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
6044
6045 /* clear (again), then enable host interrupts */
bb8c093b
CH		 6046 iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
6047 iwl3945_enable_interrupts(priv);
b481de9c
ZY		 6048
6049 /* really make sure rfkill handshake bits are cleared */
bb8c093b
CH		 6050 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
6051 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 6052
6053 /* Copy original ucode data image from disk into backup cache.
6054 * This will be used to initialize the on-board processor's
6055 * data SRAM for a clean start when the runtime program first loads. */
6056 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 6057 priv->ucode_data.len);
b481de9c 6058
e655b9f0
ZY		 6059 /* We return success when we resume from suspend and rf_kill is on. */
6060 if (test_bit(STATUS_RF_KILL_HW, &priv->status))
6061 return 0;
6062
b481de9c
ZY		 6063 for (i = 0; i < MAX_HW_RESTARTS; i++) {
6064
bb8c093b 6065 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 6066
6067 /* load bootstrap state machine,
6068 * load bootstrap program into processor's memory,
6069 * prepare to load the "initialize" uCode */
bb8c093b 6070 rc = iwl3945_load_bsm(priv);
b481de9c
ZY		 6071
6072 if (rc) {
6073 IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
6074 continue;
6075 }
6076
6077 /* start card; "initialize" will load runtime ucode */
bb8c093b 6078 iwl3945_nic_start(priv);
b481de9c 6079
b481de9c
ZY		 6080 IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
6081
6082 return 0;
6083 }
6084
6085 set_bit(STATUS_EXIT_PENDING, &priv->status);
bb8c093b 6086 __iwl3945_down(priv);
b481de9c
ZY		 6087
6088 /* tried to restart and config the device for as long as our
6089 * patience could withstand */
6090 IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
6091 return -EIO;
6092}
6093
6094
6095/*****************************************************************************
6096 *
6097 * Workqueue callbacks
6098 *
6099 *****************************************************************************/
6100
bb8c093b 6101static void iwl3945_bg_init_alive_start(struct work_struct *data)
b481de9c 6102{
bb8c093b
CH		 6103 struct iwl3945_priv *priv =
6104 container_of(data, struct iwl3945_priv, init_alive_start.work);
b481de9c
ZY		 6105
6106 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6107 return;
6108
6109 mutex_lock(&priv->mutex);
bb8c093b 6110 iwl3945_init_alive_start(priv);
b481de9c
ZY		 6111 mutex_unlock(&priv->mutex);
6112}
6113
bb8c093b 6114static void iwl3945_bg_alive_start(struct work_struct *data)
b481de9c 6115{
bb8c093b
CH		 6116 struct iwl3945_priv *priv =
6117 container_of(data, struct iwl3945_priv, alive_start.work);
b481de9c
ZY		 6118
6119 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6120 return;
6121
6122 mutex_lock(&priv->mutex);
bb8c093b 6123 iwl3945_alive_start(priv);
b481de9c
ZY		 6124 mutex_unlock(&priv->mutex);
6125}
6126
bb8c093b 6127static void iwl3945_bg_rf_kill(struct work_struct *work)
b481de9c 6128{
bb8c093b 6129 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill);
b481de9c
ZY		 6130
6131 wake_up_interruptible(&priv->wait_command_queue);
6132
6133 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6134 return;
6135
6136 mutex_lock(&priv->mutex);
6137
bb8c093b 6138 if (!iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 6139 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
6140 "HW and/or SW RF Kill no longer active, restarting "
6141 "device\n");
6142 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
6143 queue_work(priv->workqueue, &priv->restart);
6144 } else {
6145
6146 if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
6147 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
6148 "disabled by SW switch\n");
6149 else
6150 IWL_WARNING("Radio Frequency Kill Switch is On:\n"
6151 "Kill switch must be turned off for "
6152 "wireless networking to work.\n");
6153 }
6154 mutex_unlock(&priv->mutex);
6155}
6156
6157#define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
6158
bb8c093b 6159static void iwl3945_bg_scan_check(struct work_struct *data)
b481de9c 6160{
bb8c093b
CH		 6161 struct iwl3945_priv *priv =
6162 container_of(data, struct iwl3945_priv, scan_check.work);
b481de9c
ZY		 6163
6164 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6165 return;
6166
6167 mutex_lock(&priv->mutex);
6168 if (test_bit(STATUS_SCANNING, &priv->status) ||
6169 test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6170 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
6171 "Scan completion watchdog resetting adapter (%dms)\n",
6172 jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
15e869d8 6173
b481de9c 6174 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
bb8c093b 6175 iwl3945_send_scan_abort(priv);
b481de9c
ZY		 6176 }
6177 mutex_unlock(&priv->mutex);
6178}
6179
bb8c093b 6180static void iwl3945_bg_request_scan(struct work_struct *data)
b481de9c 6181{
bb8c093b
CH		 6182 struct iwl3945_priv *priv =
6183 container_of(data, struct iwl3945_priv, request_scan);
6184 struct iwl3945_host_cmd cmd = {
b481de9c 6185 .id = REPLY_SCAN_CMD,
bb8c093b 6186 .len = sizeof(struct iwl3945_scan_cmd),
b481de9c
ZY		 6187 .meta.flags = CMD_SIZE_HUGE,
6188 };
6189 int rc = 0;
bb8c093b 6190 struct iwl3945_scan_cmd *scan;
b481de9c
ZY		 6191 struct ieee80211_conf *conf = NULL;
6192 u8 direct_mask;
8318d78a 6193 enum ieee80211_band band;
b481de9c
ZY		 6194
6195 conf = ieee80211_get_hw_conf(priv->hw);
6196
6197 mutex_lock(&priv->mutex);
6198
bb8c093b 6199 if (!iwl3945_is_ready(priv)) {
b481de9c
ZY		 6200 IWL_WARNING("request scan called when driver not ready.\n");
6201 goto done;
6202 }
6203
6204 /* Make sure the scan wasn't cancelled before this queued work
6205 * was given the chance to run... */
6206 if (!test_bit(STATUS_SCANNING, &priv->status))
6207 goto done;
6208
6209 /* This should never be called or scheduled if there is currently
6210 * a scan active in the hardware. */
6211 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
6212 IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
6213 "Ignoring second request.\n");
6214 rc = -EIO;
6215 goto done;
6216 }
6217
6218 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
6219 IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
6220 goto done;
6221 }
6222
6223 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6224 IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
6225 goto done;
6226 }
6227
bb8c093b 6228 if (iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 6229 IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
6230 goto done;
6231 }
6232
6233 if (!test_bit(STATUS_READY, &priv->status)) {
6234 IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
6235 goto done;
6236 }
6237
6238 if (!priv->scan_bands) {
6239 IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
6240 goto done;
6241 }
6242
6243 if (!priv->scan) {
bb8c093b 6244 priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
b481de9c
ZY		 6245 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
6246 if (!priv->scan) {
6247 rc = -ENOMEM;
6248 goto done;
6249 }
6250 }
6251 scan = priv->scan;
bb8c093b 6252 memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
b481de9c
ZY		 6253
6254 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
6255 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
6256
bb8c093b 6257 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 6258 u16 interval = 0;
6259 u32 extra;
6260 u32 suspend_time = 100;
6261 u32 scan_suspend_time = 100;
6262 unsigned long flags;
6263
6264 IWL_DEBUG_INFO("Scanning while associated...\n");
6265
6266 spin_lock_irqsave(&priv->lock, flags);
6267 interval = priv->beacon_int;
6268 spin_unlock_irqrestore(&priv->lock, flags);
6269
6270 scan->suspend_time = 0;
15e869d8 6271 scan->max_out_time = cpu_to_le32(200 * 1024);
b481de9c
ZY		 6272 if (!interval)
6273 interval = suspend_time;
6274 /*
6275 * suspend time format:
6276 * 0-19: beacon interval in usec (time before exec.)
6277 * 20-23: 0
6278 * 24-31: number of beacons (suspend between channels)
6279 */
6280
6281 extra = (suspend_time / interval) << 24;
6282 scan_suspend_time = 0xFF0FFFFF &
6283 (extra | ((suspend_time % interval) * 1024));
6284
6285 scan->suspend_time = cpu_to_le32(scan_suspend_time);
6286 IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
6287 scan_suspend_time, interval);
6288 }
6289
6290 /* We should add the ability for user to lock to PASSIVE ONLY */
6291 if (priv->one_direct_scan) {
6292 IWL_DEBUG_SCAN
6293 ("Kicking off one direct scan for '%s'\n",
bb8c093b 6294 iwl3945_escape_essid(priv->direct_ssid,
b481de9c
ZY		 6295 priv->direct_ssid_len));
6296 scan->direct_scan[0].id = WLAN_EID_SSID;
6297 scan->direct_scan[0].len = priv->direct_ssid_len;
6298 memcpy(scan->direct_scan[0].ssid,
6299 priv->direct_ssid, priv->direct_ssid_len);
6300 direct_mask = 1;
bb8c093b 6301 } else if (!iwl3945_is_associated(priv) && priv->essid_len) {
b481de9c
ZY		 6302 scan->direct_scan[0].id = WLAN_EID_SSID;
6303 scan->direct_scan[0].len = priv->essid_len;
6304 memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len);
6305 direct_mask = 1;
6306 } else
6307 direct_mask = 0;
6308
6309 /* We don't build a direct scan probe request; the uCode will do
6310 * that based on the direct_mask added to each channel entry */
6311 scan->tx_cmd.len = cpu_to_le16(
bb8c093b 6312 iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
18904f58 6313 IWL_MAX_SCAN_SIZE - sizeof(*scan), 0));
b481de9c
ZY		 6314 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
6315 scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
6316 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
6317
6318 /* flags + rate selection */
6319
6320 switch (priv->scan_bands) {
6321 case 2:
6322 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
6323 scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
6324 scan->good_CRC_th = 0;
8318d78a 6325 band = IEEE80211_BAND_2GHZ;
b481de9c
ZY		 6326 break;
6327
6328 case 1:
6329 scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
6330 scan->good_CRC_th = IWL_GOOD_CRC_TH;
8318d78a 6331 band = IEEE80211_BAND_5GHZ;
b481de9c
ZY		 6332 break;
6333
6334 default:
6335 IWL_WARNING("Invalid scan band count\n");
6336 goto done;
6337 }
6338
6339 /* select Rx antennas */
6340 scan->flags |= iwl3945_get_antenna_flags(priv);
6341
6342 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR)
6343 scan->filter_flags = RXON_FILTER_PROMISC_MSK;
6344
26c0f03f 6345 if (direct_mask) {
b481de9c
ZY		 6346 IWL_DEBUG_SCAN
6347 ("Initiating direct scan for %s.\n",
bb8c093b 6348 iwl3945_escape_essid(priv->essid, priv->essid_len));
26c0f03f
RC		 6349 scan->channel_count =
6350 iwl3945_get_channels_for_scan(
6351 priv, band, 1, /* active */
6352 direct_mask,
6353 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
6354 } else {
b481de9c 6355 IWL_DEBUG_SCAN("Initiating indirect scan.\n");
26c0f03f
RC		 6356 scan->channel_count =
6357 iwl3945_get_channels_for_scan(
6358 priv, band, 0, /* passive */
6359 direct_mask,
6360 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
6361 }
b481de9c
ZY		 6362
6363 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
bb8c093b 6364 scan->channel_count * sizeof(struct iwl3945_scan_channel);
b481de9c
ZY		 6365 cmd.data = scan;
6366 scan->len = cpu_to_le16(cmd.len);
6367
6368 set_bit(STATUS_SCAN_HW, &priv->status);
bb8c093b 6369 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 6370 if (rc)
6371 goto done;
6372
6373 queue_delayed_work(priv->workqueue, &priv->scan_check,
6374 IWL_SCAN_CHECK_WATCHDOG);
6375
6376 mutex_unlock(&priv->mutex);
6377 return;
6378
6379 done:
01ebd063 6380 /* inform mac80211 scan aborted */
b481de9c
ZY		 6381 queue_work(priv->workqueue, &priv->scan_completed);
6382 mutex_unlock(&priv->mutex);
6383}
6384
bb8c093b 6385static void iwl3945_bg_up(struct work_struct *data)
b481de9c 6386{
bb8c093b 6387 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up);
b481de9c
ZY		 6388
6389 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6390 return;
6391
6392 mutex_lock(&priv->mutex);
bb8c093b 6393 __iwl3945_up(priv);
b481de9c
ZY		 6394 mutex_unlock(&priv->mutex);
6395}
6396
bb8c093b 6397static void iwl3945_bg_restart(struct work_struct *data)
b481de9c 6398{
bb8c093b 6399 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart);
b481de9c
ZY		 6400
6401 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6402 return;
6403
bb8c093b 6404 iwl3945_down(priv);
b481de9c
ZY		 6405 queue_work(priv->workqueue, &priv->up);
6406}
6407
bb8c093b 6408static void iwl3945_bg_rx_replenish(struct work_struct *data)
b481de9c 6409{
bb8c093b
CH		 6410 struct iwl3945_priv *priv =
6411 container_of(data, struct iwl3945_priv, rx_replenish);
b481de9c
ZY		 6412
6413 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6414 return;
6415
6416 mutex_lock(&priv->mutex);
bb8c093b 6417 iwl3945_rx_replenish(priv);
b481de9c
ZY		 6418 mutex_unlock(&priv->mutex);
6419}
6420
7878a5a4
MA		 6421#define IWL_DELAY_NEXT_SCAN (HZ*2)
6422
bb8c093b 6423static void iwl3945_bg_post_associate(struct work_struct *data)
b481de9c 6424{
bb8c093b 6425 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv,
b481de9c
ZY		 6426 post_associate.work);
6427
6428 int rc = 0;
6429 struct ieee80211_conf *conf = NULL;
0795af57 6430 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 6431
6432 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
6433 IWL_ERROR("%s Should not be called in AP mode\n", __FUNCTION__);
6434 return;
6435 }
6436
6437
0795af57
JP		 6438 IWL_DEBUG_ASSOC("Associated as %d to: %s\n",
6439 priv->assoc_id,
6440 print_mac(mac, priv->active_rxon.bssid_addr));
b481de9c
ZY		 6441
6442 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6443 return;
6444
6445 mutex_lock(&priv->mutex);
6446
32bfd35d 6447 if (!priv->vif || !priv->is_open) {
6ef89d0a
MA		 6448 mutex_unlock(&priv->mutex);
6449 return;
6450 }
bb8c093b 6451 iwl3945_scan_cancel_timeout(priv, 200);
15e869d8 6452
b481de9c
ZY		 6453 conf = ieee80211_get_hw_conf(priv->hw);
6454
6455 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6456 iwl3945_commit_rxon(priv);
b481de9c 6457
bb8c093b
CH		 6458 memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
6459 iwl3945_setup_rxon_timing(priv);
6460 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY		 6461 sizeof(priv->rxon_timing), &priv->rxon_timing);
6462 if (rc)
6463 IWL_WARNING("REPLY_RXON_TIMING failed - "
6464 "Attempting to continue.\n");
6465
6466 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
6467
6468 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
6469
6470 IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
6471 priv->assoc_id, priv->beacon_int);
6472
6473 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
6474 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
6475 else
6476 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
6477
6478 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
6479 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
6480 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
6481 else
6482 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
6483
6484 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
6485 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
6486
6487 }
6488
bb8c093b 6489 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6490
6491 switch (priv->iw_mode) {
6492 case IEEE80211_IF_TYPE_STA:
bb8c093b 6493 iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
b481de9c
ZY		 6494 break;
6495
6496 case IEEE80211_IF_TYPE_IBSS:
6497
6498 /* clear out the station table */
bb8c093b 6499 iwl3945_clear_stations_table(priv);
b481de9c 6500
bb8c093b
CH		 6501 iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
6502 iwl3945_add_station(priv, priv->bssid, 0, 0);
b481de9c 6503 iwl3945_sync_sta(priv, IWL_STA_ID,
8318d78a 6504 (priv->band == IEEE80211_BAND_5GHZ) ?
b481de9c
ZY		 6505 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
6506 CMD_ASYNC);
bb8c093b
CH		 6507 iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
6508 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 6509
6510 break;
6511
6512 default:
6513 IWL_ERROR("%s Should not be called in %d mode\n",
bc434dd2 6514 __FUNCTION__, priv->iw_mode);
b481de9c
ZY		 6515 break;
6516 }
6517
bb8c093b 6518 iwl3945_sequence_reset(priv);
b481de9c 6519
bb8c093b 6520 iwl3945_activate_qos(priv, 0);
292ae174 6521
7878a5a4
MA		 6522 /* we have just associated, don't start scan too early */
6523 priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
b481de9c
ZY		 6524 mutex_unlock(&priv->mutex);
6525}
6526
bb8c093b 6527static void iwl3945_bg_abort_scan(struct work_struct *work)
b481de9c 6528{
bb8c093b 6529 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan);
b481de9c 6530
bb8c093b 6531 if (!iwl3945_is_ready(priv))
b481de9c
ZY		 6532 return;
6533
6534 mutex_lock(&priv->mutex);
6535
6536 set_bit(STATUS_SCAN_ABORTING, &priv->status);
bb8c093b 6537 iwl3945_send_scan_abort(priv);
b481de9c
ZY		 6538
6539 mutex_unlock(&priv->mutex);
6540}
6541
76bb77e0
ZY		 6542static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf);
6543
bb8c093b 6544static void iwl3945_bg_scan_completed(struct work_struct *work)
b481de9c 6545{
bb8c093b
CH		 6546 struct iwl3945_priv *priv =
6547 container_of(work, struct iwl3945_priv, scan_completed);
b481de9c
ZY		 6548
6549 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
6550
6551 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6552 return;
6553
a0646470
ZY		 6554 if (test_bit(STATUS_CONF_PENDING, &priv->status))
6555 iwl3945_mac_config(priv->hw, ieee80211_get_hw_conf(priv->hw));
76bb77e0 6556
b481de9c
ZY		 6557 ieee80211_scan_completed(priv->hw);
6558
6559 /* Since setting the TXPOWER may have been deferred while
6560 * performing the scan, fire one off */
6561 mutex_lock(&priv->mutex);
bb8c093b 6562 iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 6563 mutex_unlock(&priv->mutex);
6564}
6565
6566/*****************************************************************************
6567 *
6568 * mac80211 entry point functions
6569 *
6570 *****************************************************************************/
6571
5a66926a
ZY		 6572#define UCODE_READY_TIMEOUT (2 * HZ)
6573
bb8c093b 6574static int iwl3945_mac_start(struct ieee80211_hw *hw)
b481de9c 6575{
bb8c093b 6576 struct iwl3945_priv *priv = hw->priv;
5a66926a 6577 int ret;
b481de9c
ZY		 6578
6579 IWL_DEBUG_MAC80211("enter\n");
6580
5a66926a
ZY		 6581 if (pci_enable_device(priv->pci_dev)) {
6582 IWL_ERROR("Fail to pci_enable_device\n");
6583 return -ENODEV;
6584 }
6585 pci_restore_state(priv->pci_dev);
6586 pci_enable_msi(priv->pci_dev);
6587
6588 ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
6589 DRV_NAME, priv);
6590 if (ret) {
6591 IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq);
6592 goto out_disable_msi;
6593 }
6594
b481de9c
ZY		 6595 /* we should be verifying the device is ready to be opened */
6596 mutex_lock(&priv->mutex);
6597
5a66926a
ZY		 6598 memset(&priv->staging_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
6599 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
6600 * ucode filename and max sizes are card-specific. */
6601
6602 if (!priv->ucode_code.len) {
6603 ret = iwl3945_read_ucode(priv);
6604 if (ret) {
6605 IWL_ERROR("Could not read microcode: %d\n", ret);
6606 mutex_unlock(&priv->mutex);
6607 goto out_release_irq;
6608 }
6609 }
b481de9c 6610
e655b9f0 6611 ret = __iwl3945_up(priv);
b481de9c
ZY		 6612
6613 mutex_unlock(&priv->mutex);
5a66926a 6614
e655b9f0
ZY		 6615 if (ret)
6616 goto out_release_irq;
6617
6618 IWL_DEBUG_INFO("Start UP work.\n");
6619
6620 if (test_bit(STATUS_IN_SUSPEND, &priv->status))
6621 return 0;
6622
5a66926a
ZY		 6623 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
6624 * mac80211 will not be run successfully. */
6625 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
6626 test_bit(STATUS_READY, &priv->status),
6627 UCODE_READY_TIMEOUT);
6628 if (!ret) {
6629 if (!test_bit(STATUS_READY, &priv->status)) {
6630 IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n",
6631 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6632 ret = -ETIMEDOUT;
6633 goto out_release_irq;
6634 }
6635 }
6636
e655b9f0 6637 priv->is_open = 1;
b481de9c
ZY		 6638 IWL_DEBUG_MAC80211("leave\n");
6639 return 0;
5a66926a
ZY		 6640
6641out_release_irq:
6642 free_irq(priv->pci_dev->irq, priv);
6643out_disable_msi:
6644 pci_disable_msi(priv->pci_dev);
e655b9f0
ZY		 6645 pci_disable_device(priv->pci_dev);
6646 priv->is_open = 0;
6647 IWL_DEBUG_MAC80211("leave - failed\n");
5a66926a 6648 return ret;
b481de9c
ZY		 6649}
6650
bb8c093b 6651static void iwl3945_mac_stop(struct ieee80211_hw *hw)
b481de9c 6652{
bb8c093b 6653 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6654
6655 IWL_DEBUG_MAC80211("enter\n");
6ef89d0a 6656
e655b9f0
ZY		 6657 if (!priv->is_open) {
6658 IWL_DEBUG_MAC80211("leave - skip\n");
6659 return;
6660 }
6661
b481de9c 6662 priv->is_open = 0;
5a66926a
ZY		 6663
6664 if (iwl3945_is_ready_rf(priv)) {
e655b9f0
ZY		 6665 /* stop mac, cancel any scan request and clear
6666 * RXON_FILTER_ASSOC_MSK BIT
6667 */
5a66926a
ZY		 6668 mutex_lock(&priv->mutex);
6669 iwl3945_scan_cancel_timeout(priv, 100);
6670 cancel_delayed_work(&priv->post_associate);
fde3571f 6671 mutex_unlock(&priv->mutex);
fde3571f
MA		 6672 }
6673
5a66926a
ZY		 6674 iwl3945_down(priv);
6675
6676 flush_workqueue(priv->workqueue);
6677 free_irq(priv->pci_dev->irq, priv);
6678 pci_disable_msi(priv->pci_dev);
6679 pci_save_state(priv->pci_dev);
6680 pci_disable_device(priv->pci_dev);
6ef89d0a 6681
b481de9c 6682 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 6683}
6684
bb8c093b 6685static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
b481de9c
ZY		 6686 struct ieee80211_tx_control *ctl)
6687{
bb8c093b 6688 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6689
6690 IWL_DEBUG_MAC80211("enter\n");
6691
6692 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
6693 IWL_DEBUG_MAC80211("leave - monitor\n");
6694 return -1;
6695 }
6696
6697 IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
8318d78a 6698 ctl->tx_rate->bitrate);
b481de9c 6699
bb8c093b 6700 if (iwl3945_tx_skb(priv, skb, ctl))
b481de9c
ZY		 6701 dev_kfree_skb_any(skb);
6702
6703 IWL_DEBUG_MAC80211("leave\n");
6704 return 0;
6705}
6706
bb8c093b 6707static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
b481de9c
ZY		 6708 struct ieee80211_if_init_conf *conf)
6709{
bb8c093b 6710 struct iwl3945_priv *priv = hw->priv;
b481de9c 6711 unsigned long flags;
0795af57 6712 DECLARE_MAC_BUF(mac);
b481de9c 6713
32bfd35d 6714 IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
b481de9c 6715
32bfd35d
JB		 6716 if (priv->vif) {
6717 IWL_DEBUG_MAC80211("leave - vif != NULL\n");
864792e3 6718 return -EOPNOTSUPP;
b481de9c
ZY		 6719 }
6720
6721 spin_lock_irqsave(&priv->lock, flags);
32bfd35d 6722 priv->vif = conf->vif;
b481de9c
ZY		 6723
6724 spin_unlock_irqrestore(&priv->lock, flags);
6725
6726 mutex_lock(&priv->mutex);
864792e3
TW		 6727
6728 if (conf->mac_addr) {
6729 IWL_DEBUG_MAC80211("Set: %s\n", print_mac(mac, conf->mac_addr));
6730 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
6731 }
6732
5a66926a
ZY		 6733 if (iwl3945_is_ready(priv))
6734 iwl3945_set_mode(priv, conf->type);
b481de9c 6735
b481de9c
ZY		 6736 mutex_unlock(&priv->mutex);
6737
5a66926a 6738 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 6739 return 0;
6740}
6741
6742/**
bb8c093b 6743 * iwl3945_mac_config - mac80211 config callback
b481de9c
ZY		 6744 *
6745 * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
6746 * be set inappropriately and the driver currently sets the hardware up to
6747 * use it whenever needed.
6748 */
bb8c093b 6749static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
b481de9c 6750{
bb8c093b
CH		 6751 struct iwl3945_priv *priv = hw->priv;
6752 const struct iwl3945_channel_info *ch_info;
b481de9c 6753 unsigned long flags;
76bb77e0 6754 int ret = 0;
b481de9c
ZY		 6755
6756 mutex_lock(&priv->mutex);
8318d78a 6757 IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
b481de9c 6758
12342c47
ZY		 6759 priv->add_radiotap = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
6760
bb8c093b 6761 if (!iwl3945_is_ready(priv)) {
b481de9c 6762 IWL_DEBUG_MAC80211("leave - not ready\n");
76bb77e0
ZY		 6763 ret = -EIO;
6764 goto out;
b481de9c
ZY		 6765 }
6766
bb8c093b 6767 if (unlikely(!iwl3945_param_disable_hw_scan &&
b481de9c 6768 test_bit(STATUS_SCANNING, &priv->status))) {
a0646470
ZY		 6769 IWL_DEBUG_MAC80211("leave - scanning\n");
6770 set_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 6771 mutex_unlock(&priv->mutex);
a0646470 6772 return 0;
b481de9c
ZY		 6773 }
6774
6775 spin_lock_irqsave(&priv->lock, flags);
6776
8318d78a
JB		 6777 ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
6778 conf->channel->hw_value);
b481de9c
ZY		 6779 if (!is_channel_valid(ch_info)) {
6780 IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this SKU.\n",
8318d78a 6781 conf->channel->hw_value, conf->channel->band);
b481de9c
ZY		 6782 IWL_DEBUG_MAC80211("leave - invalid channel\n");
6783 spin_unlock_irqrestore(&priv->lock, flags);
76bb77e0
ZY		 6784 ret = -EINVAL;
6785 goto out;
b481de9c
ZY		 6786 }
6787
8318d78a 6788 iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
b481de9c 6789
8318d78a 6790 iwl3945_set_flags_for_phymode(priv, conf->channel->band);
b481de9c
ZY		 6791
6792 /* The list of supported rates and rate mask can be different
6793 * for each phymode; since the phymode may have changed, reset
6794 * the rate mask to what mac80211 lists */
bb8c093b 6795 iwl3945_set_rate(priv);
b481de9c
ZY		 6796
6797 spin_unlock_irqrestore(&priv->lock, flags);
6798
6799#ifdef IEEE80211_CONF_CHANNEL_SWITCH
6800 if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
bb8c093b 6801 iwl3945_hw_channel_switch(priv, conf->channel);
76bb77e0 6802 goto out;
b481de9c
ZY		 6803 }
6804#endif
6805
bb8c093b 6806 iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
b481de9c
ZY		 6807
6808 if (!conf->radio_enabled) {
6809 IWL_DEBUG_MAC80211("leave - radio disabled\n");
76bb77e0 6810 goto out;
b481de9c
ZY		 6811 }
6812
bb8c093b 6813 if (iwl3945_is_rfkill(priv)) {
b481de9c 6814 IWL_DEBUG_MAC80211("leave - RF kill\n");
76bb77e0
ZY		 6815 ret = -EIO;
6816 goto out;
b481de9c
ZY		 6817 }
6818
bb8c093b 6819 iwl3945_set_rate(priv);
b481de9c
ZY		 6820
6821 if (memcmp(&priv->active_rxon,
6822 &priv->staging_rxon, sizeof(priv->staging_rxon)))
bb8c093b 6823 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6824 else
6825 IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
6826
6827 IWL_DEBUG_MAC80211("leave\n");
6828
76bb77e0 6829out:
a0646470 6830 clear_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 6831 mutex_unlock(&priv->mutex);
76bb77e0 6832 return ret;
b481de9c
ZY		 6833}
6834
bb8c093b 6835static void iwl3945_config_ap(struct iwl3945_priv *priv)
b481de9c
ZY		 6836{
6837 int rc = 0;
6838
d986bcd1 6839 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY		 6840 return;
6841
6842 /* The following should be done only at AP bring up */
6843 if ((priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) == 0) {
6844
6845 /* RXON - unassoc (to set timing command) */
6846 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6847 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6848
6849 /* RXON Timing */
bb8c093b
CH		 6850 memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
6851 iwl3945_setup_rxon_timing(priv);
6852 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY		 6853 sizeof(priv->rxon_timing), &priv->rxon_timing);
6854 if (rc)
6855 IWL_WARNING("REPLY_RXON_TIMING failed - "
6856 "Attempting to continue.\n");
6857
6858 /* FIXME: what should be the assoc_id for AP? */
6859 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
6860 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
6861 priv->staging_rxon.flags |=
6862 RXON_FLG_SHORT_PREAMBLE_MSK;
6863 else
6864 priv->staging_rxon.flags &=
6865 ~RXON_FLG_SHORT_PREAMBLE_MSK;
6866
6867 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
6868 if (priv->assoc_capability &
6869 WLAN_CAPABILITY_SHORT_SLOT_TIME)
6870 priv->staging_rxon.flags |=
6871 RXON_FLG_SHORT_SLOT_MSK;
6872 else
6873 priv->staging_rxon.flags &=
6874 ~RXON_FLG_SHORT_SLOT_MSK;
6875
6876 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
6877 priv->staging_rxon.flags &=
6878 ~RXON_FLG_SHORT_SLOT_MSK;
6879 }
6880 /* restore RXON assoc */
6881 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
bb8c093b
CH		 6882 iwl3945_commit_rxon(priv);
6883 iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
556f8db7 6884 }
bb8c093b 6885 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 6886
6887 /* FIXME - we need to add code here to detect a totally new
6888 * configuration, reset the AP, unassoc, rxon timing, assoc,
6889 * clear sta table, add BCAST sta... */
6890}
6891
32bfd35d
JB		 6892static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
6893 struct ieee80211_vif *vif,
b481de9c
ZY		 6894 struct ieee80211_if_conf *conf)
6895{
bb8c093b 6896 struct iwl3945_priv *priv = hw->priv;
0795af57 6897 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 6898 unsigned long flags;
6899 int rc;
6900
6901 if (conf == NULL)
6902 return -EIO;
6903
b716bb91
EG		 6904 if (priv->vif != vif) {
6905 IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
6906 mutex_unlock(&priv->mutex);
6907 return 0;
6908 }
6909
4150c572
JB		 6910 /* XXX: this MUST use conf->mac_addr */
6911
b481de9c
ZY		 6912 if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
6913 (!conf->beacon || !conf->ssid_len)) {
6914 IWL_DEBUG_MAC80211
6915 ("Leaving in AP mode because HostAPD is not ready.\n");
6916 return 0;
6917 }
6918
5a66926a
ZY		 6919 if (!iwl3945_is_alive(priv))
6920 return -EAGAIN;
6921
b481de9c
ZY		 6922 mutex_lock(&priv->mutex);
6923
b481de9c 6924 if (conf->bssid)
0795af57
JP		 6925 IWL_DEBUG_MAC80211("bssid: %s\n",
6926 print_mac(mac, conf->bssid));
b481de9c 6927
4150c572
JB		 6928/*
6929 * very dubious code was here; the probe filtering flag is never set:
6930 *
b481de9c
ZY		 6931 if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
6932 !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
4150c572 6933 */
b481de9c
ZY		 6934
6935 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
6936 if (!conf->bssid) {
6937 conf->bssid = priv->mac_addr;
6938 memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
0795af57
JP		 6939 IWL_DEBUG_MAC80211("bssid was set to: %s\n",
6940 print_mac(mac, conf->bssid));
b481de9c
ZY		 6941 }
6942 if (priv->ibss_beacon)
6943 dev_kfree_skb(priv->ibss_beacon);
6944
6945 priv->ibss_beacon = conf->beacon;
6946 }
6947
fde3571f
MA		 6948 if (iwl3945_is_rfkill(priv))
6949 goto done;
6950
b481de9c
ZY		 6951 if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
6952 !is_multicast_ether_addr(conf->bssid)) {
6953 /* If there is currently a HW scan going on in the background
6954 * then we need to cancel it else the RXON below will fail. */
bb8c093b 6955 if (iwl3945_scan_cancel_timeout(priv, 100)) {
b481de9c
ZY		 6956 IWL_WARNING("Aborted scan still in progress "
6957 "after 100ms\n");
6958 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
6959 mutex_unlock(&priv->mutex);
6960 return -EAGAIN;
6961 }
6962 memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
6963
6964 /* TODO: Audit driver for usage of these members and see
6965 * if mac80211 deprecates them (priv->bssid looks like it
6966 * shouldn't be there, but I haven't scanned the IBSS code
6967 * to verify) - jpk */
6968 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
6969
6970 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
bb8c093b 6971 iwl3945_config_ap(priv);
b481de9c 6972 else {
bb8c093b 6973 rc = iwl3945_commit_rxon(priv);
b481de9c 6974 if ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && rc)
bb8c093b 6975 iwl3945_add_station(priv,
556f8db7 6976 priv->active_rxon.bssid_addr, 1, 0);
b481de9c
ZY		 6977 }
6978
6979 } else {
bb8c093b 6980 iwl3945_scan_cancel_timeout(priv, 100);
b481de9c 6981 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6982 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6983 }
6984
fde3571f 6985 done:
b481de9c
ZY		 6986 spin_lock_irqsave(&priv->lock, flags);
6987 if (!conf->ssid_len)
6988 memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
6989 else
6990 memcpy(priv->essid, conf->ssid, conf->ssid_len);
6991
6992 priv->essid_len = conf->ssid_len;
6993 spin_unlock_irqrestore(&priv->lock, flags);
6994
6995 IWL_DEBUG_MAC80211("leave\n");
6996 mutex_unlock(&priv->mutex);
6997
6998 return 0;
6999}
7000
bb8c093b 7001static void iwl3945_configure_filter(struct ieee80211_hw *hw,
4150c572
JB		 7002 unsigned int changed_flags,
7003 unsigned int *total_flags,
7004 int mc_count, struct dev_addr_list *mc_list)
7005{
7006 /*
7007 * XXX: dummy
bb8c093b 7008 * see also iwl3945_connection_init_rx_config
4150c572
JB		 7009 */
7010 *total_flags = 0;
7011}
7012
bb8c093b 7013static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
b481de9c
ZY		 7014 struct ieee80211_if_init_conf *conf)
7015{
bb8c093b 7016 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7017
7018 IWL_DEBUG_MAC80211("enter\n");
7019
7020 mutex_lock(&priv->mutex);
6ef89d0a 7021
fde3571f
MA		 7022 if (iwl3945_is_ready_rf(priv)) {
7023 iwl3945_scan_cancel_timeout(priv, 100);
7024 cancel_delayed_work(&priv->post_associate);
7025 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
7026 iwl3945_commit_rxon(priv);
7027 }
32bfd35d
JB		 7028 if (priv->vif == conf->vif) {
7029 priv->vif = NULL;
b481de9c
ZY		 7030 memset(priv->bssid, 0, ETH_ALEN);
7031 memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
7032 priv->essid_len = 0;
7033 }
7034 mutex_unlock(&priv->mutex);
7035
7036 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 7037}
7038
bb8c093b 7039static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
b481de9c
ZY		 7040{
7041 int rc = 0;
7042 unsigned long flags;
bb8c093b 7043 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7044
7045 IWL_DEBUG_MAC80211("enter\n");
7046
15e869d8 7047 mutex_lock(&priv->mutex);
b481de9c
ZY		 7048 spin_lock_irqsave(&priv->lock, flags);
7049
bb8c093b 7050 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7051 rc = -EIO;
7052 IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
7053 goto out_unlock;
7054 }
7055
7056 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { /* APs don't scan */
7057 rc = -EIO;
7058 IWL_ERROR("ERROR: APs don't scan\n");
7059 goto out_unlock;
7060 }
7061
7878a5a4
MA		 7062 /* we don't schedule scan within next_scan_jiffies period */
7063 if (priv->next_scan_jiffies &&
7064 time_after(priv->next_scan_jiffies, jiffies)) {
7065 rc = -EAGAIN;
7066 goto out_unlock;
7067 }
b481de9c 7068 /* if we just finished scan ask for delay */
7878a5a4
MA		 7069 if (priv->last_scan_jiffies && time_after(priv->last_scan_jiffies +
7070 IWL_DELAY_NEXT_SCAN, jiffies)) {
b481de9c
ZY		 7071 rc = -EAGAIN;
7072 goto out_unlock;
7073 }
7074 if (len) {
7878a5a4 7075 IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
bb8c093b 7076 iwl3945_escape_essid(ssid, len), (int)len);
b481de9c
ZY		 7077
7078 priv->one_direct_scan = 1;
7079 priv->direct_ssid_len = (u8)
7080 min((u8) len, (u8) IW_ESSID_MAX_SIZE);
7081 memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
6ef89d0a
MA		 7082 } else
7083 priv->one_direct_scan = 0;
b481de9c 7084
bb8c093b 7085 rc = iwl3945_scan_initiate(priv);
b481de9c
ZY		 7086
7087 IWL_DEBUG_MAC80211("leave\n");
7088
7089out_unlock:
7090 spin_unlock_irqrestore(&priv->lock, flags);
15e869d8 7091 mutex_unlock(&priv->mutex);
b481de9c
ZY		 7092
7093 return rc;
7094}
7095
bb8c093b 7096static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
b481de9c
ZY		 7097 const u8 *local_addr, const u8 *addr,
7098 struct ieee80211_key_conf *key)
7099{
bb8c093b 7100 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7101 int rc = 0;
7102 u8 sta_id;
7103
7104 IWL_DEBUG_MAC80211("enter\n");
7105
bb8c093b 7106 if (!iwl3945_param_hwcrypto) {
b481de9c
ZY		 7107 IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
7108 return -EOPNOTSUPP;
7109 }
7110
7111 if (is_zero_ether_addr(addr))
7112 /* only support pairwise keys */
7113 return -EOPNOTSUPP;
7114
bb8c093b 7115 sta_id = iwl3945_hw_find_station(priv, addr);
b481de9c 7116 if (sta_id == IWL_INVALID_STATION) {
0795af57
JP		 7117 DECLARE_MAC_BUF(mac);
7118
7119 IWL_DEBUG_MAC80211("leave - %s not in station map.\n",
7120 print_mac(mac, addr));
b481de9c
ZY		 7121 return -EINVAL;
7122 }
7123
7124 mutex_lock(&priv->mutex);
7125
bb8c093b 7126 iwl3945_scan_cancel_timeout(priv, 100);
15e869d8 7127
b481de9c
ZY		 7128 switch (cmd) {
7129 case SET_KEY:
bb8c093b 7130 rc = iwl3945_update_sta_key_info(priv, key, sta_id);
b481de9c 7131 if (!rc) {
bb8c093b
CH		 7132 iwl3945_set_rxon_hwcrypto(priv, 1);
7133 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7134 key->hw_key_idx = sta_id;
7135 IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
7136 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
7137 }
7138 break;
7139 case DISABLE_KEY:
bb8c093b 7140 rc = iwl3945_clear_sta_key_info(priv, sta_id);
b481de9c 7141 if (!rc) {
bb8c093b
CH		 7142 iwl3945_set_rxon_hwcrypto(priv, 0);
7143 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7144 IWL_DEBUG_MAC80211("disable hwcrypto key\n");
7145 }
7146 break;
7147 default:
7148 rc = -EINVAL;
7149 }
7150
7151 IWL_DEBUG_MAC80211("leave\n");
7152 mutex_unlock(&priv->mutex);
7153
7154 return rc;
7155}
7156
bb8c093b 7157static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, int queue,
b481de9c
ZY		 7158 const struct ieee80211_tx_queue_params *params)
7159{
bb8c093b 7160 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7161 unsigned long flags;
7162 int q;
b481de9c
ZY		 7163
7164 IWL_DEBUG_MAC80211("enter\n");
7165
bb8c093b 7166 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7167 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7168 return -EIO;
7169 }
7170
7171 if (queue >= AC_NUM) {
7172 IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
7173 return 0;
7174 }
7175
b481de9c
ZY		 7176 if (!priv->qos_data.qos_enable) {
7177 priv->qos_data.qos_active = 0;
7178 IWL_DEBUG_MAC80211("leave - qos not enabled\n");
7179 return 0;
7180 }
7181 q = AC_NUM - 1 - queue;
7182
7183 spin_lock_irqsave(&priv->lock, flags);
7184
7185 priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
7186 priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
7187 priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
7188 priv->qos_data.def_qos_parm.ac[q].edca_txop =
3330d7be 7189 cpu_to_le16((params->txop * 32));
b481de9c
ZY		 7190
7191 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
7192 priv->qos_data.qos_active = 1;
7193
7194 spin_unlock_irqrestore(&priv->lock, flags);
7195
7196 mutex_lock(&priv->mutex);
7197 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
bb8c093b
CH		 7198 iwl3945_activate_qos(priv, 1);
7199 else if (priv->assoc_id && iwl3945_is_associated(priv))
7200 iwl3945_activate_qos(priv, 0);
b481de9c
ZY		 7201
7202 mutex_unlock(&priv->mutex);
7203
b481de9c
ZY		 7204 IWL_DEBUG_MAC80211("leave\n");
7205 return 0;
7206}
7207
bb8c093b 7208static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
b481de9c
ZY		 7209 struct ieee80211_tx_queue_stats *stats)
7210{
bb8c093b 7211 struct iwl3945_priv *priv = hw->priv;
b481de9c 7212 int i, avail;
bb8c093b
CH		 7213 struct iwl3945_tx_queue *txq;
7214 struct iwl3945_queue *q;
b481de9c
ZY		 7215 unsigned long flags;
7216
7217 IWL_DEBUG_MAC80211("enter\n");
7218
bb8c093b 7219 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7220 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7221 return -EIO;
7222 }
7223
7224 spin_lock_irqsave(&priv->lock, flags);
7225
7226 for (i = 0; i < AC_NUM; i++) {
7227 txq = &priv->txq[i];
7228 q = &txq->q;
bb8c093b 7229 avail = iwl3945_queue_space(q);
b481de9c
ZY		 7230
7231 stats->data[i].len = q->n_window - avail;
7232 stats->data[i].limit = q->n_window - q->high_mark;
7233 stats->data[i].count = q->n_window;
7234
7235 }
7236 spin_unlock_irqrestore(&priv->lock, flags);
7237
7238 IWL_DEBUG_MAC80211("leave\n");
7239
7240 return 0;
7241}
7242
bb8c093b 7243static int iwl3945_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY		 7244 struct ieee80211_low_level_stats *stats)
7245{
7246 IWL_DEBUG_MAC80211("enter\n");
7247 IWL_DEBUG_MAC80211("leave\n");
7248
7249 return 0;
7250}
7251
bb8c093b 7252static u64 iwl3945_mac_get_tsf(struct ieee80211_hw *hw)
b481de9c
ZY		 7253{
7254 IWL_DEBUG_MAC80211("enter\n");
7255 IWL_DEBUG_MAC80211("leave\n");
7256
7257 return 0;
7258}
7259
bb8c093b 7260static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
b481de9c 7261{
bb8c093b 7262 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7263 unsigned long flags;
7264
7265 mutex_lock(&priv->mutex);
7266 IWL_DEBUG_MAC80211("enter\n");
7267
bb8c093b 7268 iwl3945_reset_qos(priv);
292ae174 7269
b481de9c
ZY		 7270 cancel_delayed_work(&priv->post_associate);
7271
7272 spin_lock_irqsave(&priv->lock, flags);
7273 priv->assoc_id = 0;
7274 priv->assoc_capability = 0;
7275 priv->call_post_assoc_from_beacon = 0;
7276
7277 /* new association get rid of ibss beacon skb */
7278 if (priv->ibss_beacon)
7279 dev_kfree_skb(priv->ibss_beacon);
7280
7281 priv->ibss_beacon = NULL;
7282
7283 priv->beacon_int = priv->hw->conf.beacon_int;
7284 priv->timestamp1 = 0;
7285 priv->timestamp0 = 0;
7286 if ((priv->iw_mode == IEEE80211_IF_TYPE_STA))
7287 priv->beacon_int = 0;
7288
7289 spin_unlock_irqrestore(&priv->lock, flags);
7290
fde3571f
MA		 7291 if (!iwl3945_is_ready_rf(priv)) {
7292 IWL_DEBUG_MAC80211("leave - not ready\n");
7293 mutex_unlock(&priv->mutex);
7294 return;
7295 }
7296
15e869d8
MA		 7297 /* we are restarting association process
7298 * clear RXON_FILTER_ASSOC_MSK bit
7299 */
7300 if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
bb8c093b 7301 iwl3945_scan_cancel_timeout(priv, 100);
15e869d8 7302 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 7303 iwl3945_commit_rxon(priv);
15e869d8
MA		 7304 }
7305
b481de9c
ZY		 7306 /* Per mac80211.h: This is only used in IBSS mode... */
7307 if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
15e869d8 7308
b481de9c
ZY		 7309 IWL_DEBUG_MAC80211("leave - not in IBSS\n");
7310 mutex_unlock(&priv->mutex);
7311 return;
b481de9c
ZY		 7312 }
7313
7314 priv->only_active_channel = 0;
7315
bb8c093b 7316 iwl3945_set_rate(priv);
b481de9c
ZY		 7317
7318 mutex_unlock(&priv->mutex);
7319
7320 IWL_DEBUG_MAC80211("leave\n");
7321
7322}
7323
bb8c093b 7324static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
b481de9c
ZY		 7325 struct ieee80211_tx_control *control)
7326{
bb8c093b 7327 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7328 unsigned long flags;
7329
7330 mutex_lock(&priv->mutex);
7331 IWL_DEBUG_MAC80211("enter\n");
7332
bb8c093b 7333 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7334 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7335 mutex_unlock(&priv->mutex);
7336 return -EIO;
7337 }
7338
7339 if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
7340 IWL_DEBUG_MAC80211("leave - not IBSS\n");
7341 mutex_unlock(&priv->mutex);
7342 return -EIO;
7343 }
7344
7345 spin_lock_irqsave(&priv->lock, flags);
7346
7347 if (priv->ibss_beacon)
7348 dev_kfree_skb(priv->ibss_beacon);
7349
7350 priv->ibss_beacon = skb;
7351
7352 priv->assoc_id = 0;
7353
7354 IWL_DEBUG_MAC80211("leave\n");
7355 spin_unlock_irqrestore(&priv->lock, flags);
7356
bb8c093b 7357 iwl3945_reset_qos(priv);
b481de9c
ZY		 7358
7359 queue_work(priv->workqueue, &priv->post_associate.work);
7360
7361 mutex_unlock(&priv->mutex);
7362
7363 return 0;
7364}
7365
7366/*****************************************************************************
7367 *
7368 * sysfs attributes
7369 *
7370 *****************************************************************************/
7371
c8b0e6e1 7372#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 7373
7374/*
7375 * The following adds a new attribute to the sysfs representation
7376 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
7377 * used for controlling the debug level.
7378 *
7379 * See the level definitions in iwl for details.
7380 */
7381
7382static ssize_t show_debug_level(struct device_driver *d, char *buf)
7383{
bb8c093b 7384 return sprintf(buf, "0x%08X\n", iwl3945_debug_level);
b481de9c
ZY		 7385}
7386static ssize_t store_debug_level(struct device_driver *d,
7387 const char *buf, size_t count)
7388{
7389 char *p = (char *)buf;
7390 u32 val;
7391
7392 val = simple_strtoul(p, &p, 0);
7393 if (p == buf)
7394 printk(KERN_INFO DRV_NAME
7395 ": %s is not in hex or decimal form.\n", buf);
7396 else
bb8c093b 7397 iwl3945_debug_level = val;
b481de9c
ZY		 7398
7399 return strnlen(buf, count);
7400}
7401
7402static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
7403 show_debug_level, store_debug_level);
7404
c8b0e6e1 7405#endif /* CONFIG_IWL3945_DEBUG */
b481de9c
ZY		 7406
7407static ssize_t show_rf_kill(struct device *d,
7408 struct device_attribute *attr, char *buf)
7409{
7410 /*
7411 * 0 - RF kill not enabled
7412 * 1 - SW based RF kill active (sysfs)
7413 * 2 - HW based RF kill active
7414 * 3 - Both HW and SW based RF kill active
7415 */
bb8c093b 7416 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7417 int val = (test_bit(STATUS_RF_KILL_SW, &priv->status) ? 0x1 : 0x0) |
7418 (test_bit(STATUS_RF_KILL_HW, &priv->status) ? 0x2 : 0x0);
7419
7420 return sprintf(buf, "%i\n", val);
7421}
7422
7423static ssize_t store_rf_kill(struct device *d,
7424 struct device_attribute *attr,
7425 const char *buf, size_t count)
7426{
bb8c093b 7427 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7428
7429 mutex_lock(&priv->mutex);
bb8c093b 7430 iwl3945_radio_kill_sw(priv, buf[0] == '1');
b481de9c
ZY		 7431 mutex_unlock(&priv->mutex);
7432
7433 return count;
7434}
7435
7436static DEVICE_ATTR(rf_kill, S_IWUSR | S_IRUGO, show_rf_kill, store_rf_kill);
7437
7438static ssize_t show_temperature(struct device *d,
7439 struct device_attribute *attr, char *buf)
7440{
bb8c093b 7441 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c 7442
bb8c093b 7443 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7444 return -EAGAIN;
7445
bb8c093b 7446 return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
b481de9c
ZY		 7447}
7448
7449static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
7450
7451static ssize_t show_rs_window(struct device *d,
7452 struct device_attribute *attr,
7453 char *buf)
7454{
bb8c093b
CH		 7455 struct iwl3945_priv *priv = d->driver_data;
7456 return iwl3945_fill_rs_info(priv->hw, buf, IWL_AP_ID);
b481de9c
ZY		 7457}
7458static DEVICE_ATTR(rs_window, S_IRUGO, show_rs_window, NULL);
7459
7460static ssize_t show_tx_power(struct device *d,
7461 struct device_attribute *attr, char *buf)
7462{
bb8c093b 7463 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7464 return sprintf(buf, "%d\n", priv->user_txpower_limit);
7465}
7466
7467static ssize_t store_tx_power(struct device *d,
7468 struct device_attribute *attr,
7469 const char *buf, size_t count)
7470{
bb8c093b 7471 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7472 char *p = (char *)buf;
7473 u32 val;
7474
7475 val = simple_strtoul(p, &p, 10);
7476 if (p == buf)
7477 printk(KERN_INFO DRV_NAME
7478 ": %s is not in decimal form.\n", buf);
7479 else
bb8c093b 7480 iwl3945_hw_reg_set_txpower(priv, val);
b481de9c
ZY		 7481
7482 return count;
7483}
7484
7485static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
7486
7487static ssize_t show_flags(struct device *d,
7488 struct device_attribute *attr, char *buf)
7489{
bb8c093b 7490 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7491
7492 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
7493}
7494
7495static ssize_t store_flags(struct device *d,
7496 struct device_attribute *attr,
7497 const char *buf, size_t count)
7498{
bb8c093b 7499 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7500 u32 flags = simple_strtoul(buf, NULL, 0);
7501
7502 mutex_lock(&priv->mutex);
7503 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
7504 /* Cancel any currently running scans... */
bb8c093b 7505 if (iwl3945_scan_cancel_timeout(priv, 100))
b481de9c
ZY		 7506 IWL_WARNING("Could not cancel scan.\n");
7507 else {
7508 IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
7509 flags);
7510 priv->staging_rxon.flags = cpu_to_le32(flags);
bb8c093b 7511 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7512 }
7513 }
7514 mutex_unlock(&priv->mutex);
7515
7516 return count;
7517}
7518
7519static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
7520
7521static ssize_t show_filter_flags(struct device *d,
7522 struct device_attribute *attr, char *buf)
7523{
bb8c093b 7524 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7525
7526 return sprintf(buf, "0x%04X\n",
7527 le32_to_cpu(priv->active_rxon.filter_flags));
7528}
7529
7530static ssize_t store_filter_flags(struct device *d,
7531 struct device_attribute *attr,
7532 const char *buf, size_t count)
7533{
bb8c093b 7534 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7535 u32 filter_flags = simple_strtoul(buf, NULL, 0);
7536
7537 mutex_lock(&priv->mutex);
7538 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
7539 /* Cancel any currently running scans... */
bb8c093b 7540 if (iwl3945_scan_cancel_timeout(priv, 100))
b481de9c
ZY		 7541 IWL_WARNING("Could not cancel scan.\n");
7542 else {
7543 IWL_DEBUG_INFO("Committing rxon.filter_flags = "
7544 "0x%04X\n", filter_flags);
7545 priv->staging_rxon.filter_flags =
7546 cpu_to_le32(filter_flags);
bb8c093b 7547 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7548 }
7549 }
7550 mutex_unlock(&priv->mutex);
7551
7552 return count;
7553}
7554
7555static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
7556 store_filter_flags);
7557
c8b0e6e1 7558#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 7559
7560static ssize_t show_measurement(struct device *d,
7561 struct device_attribute *attr, char *buf)
7562{
bb8c093b
CH		 7563 struct iwl3945_priv *priv = dev_get_drvdata(d);
7564 struct iwl3945_spectrum_notification measure_report;
b481de9c
ZY		 7565 u32 size = sizeof(measure_report), len = 0, ofs = 0;
7566 u8 *data = (u8 *) & measure_report;
7567 unsigned long flags;
7568
7569 spin_lock_irqsave(&priv->lock, flags);
7570 if (!(priv->measurement_status & MEASUREMENT_READY)) {
7571 spin_unlock_irqrestore(&priv->lock, flags);
7572 return 0;
7573 }
7574 memcpy(&measure_report, &priv->measure_report, size);
7575 priv->measurement_status = 0;
7576 spin_unlock_irqrestore(&priv->lock, flags);
7577
7578 while (size && (PAGE_SIZE - len)) {
7579 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
7580 PAGE_SIZE - len, 1);
7581 len = strlen(buf);
7582 if (PAGE_SIZE - len)
7583 buf[len++] = '\n';
7584
7585 ofs += 16;
7586 size -= min(size, 16U);
7587 }
7588
7589 return len;
7590}
7591
7592static ssize_t store_measurement(struct device *d,
7593 struct device_attribute *attr,
7594 const char *buf, size_t count)
7595{
bb8c093b 7596 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7597 struct ieee80211_measurement_params params = {
7598 .channel = le16_to_cpu(priv->active_rxon.channel),
7599 .start_time = cpu_to_le64(priv->last_tsf),
7600 .duration = cpu_to_le16(1),
7601 };
7602 u8 type = IWL_MEASURE_BASIC;
7603 u8 buffer[32];
7604 u8 channel;
7605
7606 if (count) {
7607 char *p = buffer;
7608 strncpy(buffer, buf, min(sizeof(buffer), count));
7609 channel = simple_strtoul(p, NULL, 0);
7610 if (channel)
7611 params.channel = channel;
7612
7613 p = buffer;
7614 while (*p && *p != ' ')
7615 p++;
7616 if (*p)
7617 type = simple_strtoul(p + 1, NULL, 0);
7618 }
7619
7620 IWL_DEBUG_INFO("Invoking measurement of type %d on "
7621 "channel %d (for '%s')\n", type, params.channel, buf);
bb8c093b 7622 iwl3945_get_measurement(priv, &params, type);
b481de9c
ZY		 7623
7624 return count;
7625}
7626
7627static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
7628 show_measurement, store_measurement);
c8b0e6e1 7629#endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
b481de9c 7630
b481de9c
ZY		 7631static ssize_t store_retry_rate(struct device *d,
7632 struct device_attribute *attr,
7633 const char *buf, size_t count)
7634{
bb8c093b 7635 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7636
7637 priv->retry_rate = simple_strtoul(buf, NULL, 0);
7638 if (priv->retry_rate <= 0)
7639 priv->retry_rate = 1;
7640
7641 return count;
7642}
7643
7644static ssize_t show_retry_rate(struct device *d,
7645 struct device_attribute *attr, char *buf)
7646{
bb8c093b 7647 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7648 return sprintf(buf, "%d", priv->retry_rate);
7649}
7650
7651static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
7652 store_retry_rate);
7653
7654static ssize_t store_power_level(struct device *d,
7655 struct device_attribute *attr,
7656 const char *buf, size_t count)
7657{
bb8c093b 7658 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7659 int rc;
7660 int mode;
7661
7662 mode = simple_strtoul(buf, NULL, 0);
7663 mutex_lock(&priv->mutex);
7664
bb8c093b 7665 if (!iwl3945_is_ready(priv)) {
b481de9c
ZY		 7666 rc = -EAGAIN;
7667 goto out;
7668 }
7669
7670 if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
7671 mode = IWL_POWER_AC;
7672 else
7673 mode |= IWL_POWER_ENABLED;
7674
7675 if (mode != priv->power_mode) {
bb8c093b 7676 rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
b481de9c
ZY		 7677 if (rc) {
7678 IWL_DEBUG_MAC80211("failed setting power mode.\n");
7679 goto out;
7680 }
7681 priv->power_mode = mode;
7682 }
7683
7684 rc = count;
7685
7686 out:
7687 mutex_unlock(&priv->mutex);
7688 return rc;
7689}
7690
7691#define MAX_WX_STRING 80
7692
7693/* Values are in microsecond */
7694static const s32 timeout_duration[] = {
7695 350000,
7696 250000,
7697 75000,
7698 37000,
7699 25000,
7700};
7701static const s32 period_duration[] = {
7702 400000,
7703 700000,
7704 1000000,
7705 1000000,
7706 1000000
7707};
7708
7709static ssize_t show_power_level(struct device *d,
7710 struct device_attribute *attr, char *buf)
7711{
bb8c093b 7712 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7713 int level = IWL_POWER_LEVEL(priv->power_mode);
7714 char *p = buf;
7715
7716 p += sprintf(p, "%d ", level);
7717 switch (level) {
7718 case IWL_POWER_MODE_CAM:
7719 case IWL_POWER_AC:
7720 p += sprintf(p, "(AC)");
7721 break;
7722 case IWL_POWER_BATTERY:
7723 p += sprintf(p, "(BATTERY)");
7724 break;
7725 default:
7726 p += sprintf(p,
7727 "(Timeout %dms, Period %dms)",
7728 timeout_duration[level - 1] / 1000,
7729 period_duration[level - 1] / 1000);
7730 }
7731
7732 if (!(priv->power_mode & IWL_POWER_ENABLED))
7733 p += sprintf(p, " OFF\n");
7734 else
7735 p += sprintf(p, " \n");
7736
7737 return (p - buf + 1);
7738
7739}
7740
7741static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
7742 store_power_level);
7743
7744static ssize_t show_channels(struct device *d,
7745 struct device_attribute *attr, char *buf)
7746{
8318d78a
JB		 7747 /* all this shit doesn't belong into sysfs anyway */
7748 return 0;
b481de9c
ZY		 7749}
7750
7751static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
7752
7753static ssize_t show_statistics(struct device *d,
7754 struct device_attribute *attr, char *buf)
7755{
bb8c093b
CH		 7756 struct iwl3945_priv *priv = dev_get_drvdata(d);
7757 u32 size = sizeof(struct iwl3945_notif_statistics);
b481de9c
ZY		 7758 u32 len = 0, ofs = 0;
7759 u8 *data = (u8 *) & priv->statistics;
7760 int rc = 0;
7761
bb8c093b 7762 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7763 return -EAGAIN;
7764
7765 mutex_lock(&priv->mutex);
bb8c093b 7766 rc = iwl3945_send_statistics_request(priv);
b481de9c
ZY		 7767 mutex_unlock(&priv->mutex);
7768
7769 if (rc) {
7770 len = sprintf(buf,
7771 "Error sending statistics request: 0x%08X\n", rc);
7772 return len;
7773 }
7774
7775 while (size && (PAGE_SIZE - len)) {
7776 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
7777 PAGE_SIZE - len, 1);
7778 len = strlen(buf);
7779 if (PAGE_SIZE - len)
7780 buf[len++] = '\n';
7781
7782 ofs += 16;
7783 size -= min(size, 16U);
7784 }
7785
7786 return len;
7787}
7788
7789static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
7790
7791static ssize_t show_antenna(struct device *d,
7792 struct device_attribute *attr, char *buf)
7793{
bb8c093b 7794 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c 7795
bb8c093b 7796 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7797 return -EAGAIN;
7798
7799 return sprintf(buf, "%d\n", priv->antenna);
7800}
7801
7802static ssize_t store_antenna(struct device *d,
7803 struct device_attribute *attr,
7804 const char *buf, size_t count)
7805{
7806 int ant;
bb8c093b 7807 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7808
7809 if (count == 0)
7810 return 0;
7811
7812 if (sscanf(buf, "%1i", &ant) != 1) {
7813 IWL_DEBUG_INFO("not in hex or decimal form.\n");
7814 return count;
7815 }
7816
7817 if ((ant >= 0) && (ant <= 2)) {
7818 IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
bb8c093b 7819 priv->antenna = (enum iwl3945_antenna)ant;
b481de9c
ZY		 7820 } else
7821 IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
7822
7823
7824 return count;
7825}
7826
7827static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
7828
7829static ssize_t show_status(struct device *d,
7830 struct device_attribute *attr, char *buf)
7831{
bb8c093b
CH		 7832 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
7833 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7834 return -EAGAIN;
7835 return sprintf(buf, "0x%08x\n", (int)priv->status);
7836}
7837
7838static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
7839
7840static ssize_t dump_error_log(struct device *d,
7841 struct device_attribute *attr,
7842 const char *buf, size_t count)
7843{
7844 char *p = (char *)buf;
7845
7846 if (p[0] == '1')
bb8c093b 7847 iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data);
b481de9c
ZY		 7848
7849 return strnlen(buf, count);
7850}
7851
7852static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
7853
7854static ssize_t dump_event_log(struct device *d,
7855 struct device_attribute *attr,
7856 const char *buf, size_t count)
7857{
7858 char *p = (char *)buf;
7859
7860 if (p[0] == '1')
bb8c093b 7861 iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data);
b481de9c
ZY		 7862
7863 return strnlen(buf, count);
7864}
7865
7866static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
7867
7868/*****************************************************************************
7869 *
7870 * driver setup and teardown
7871 *
7872 *****************************************************************************/
7873
bb8c093b 7874static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv)
b481de9c
ZY		 7875{
7876 priv->workqueue = create_workqueue(DRV_NAME);
7877
7878 init_waitqueue_head(&priv->wait_command_queue);
7879
bb8c093b
CH		 7880 INIT_WORK(&priv->up, iwl3945_bg_up);
7881 INIT_WORK(&priv->restart, iwl3945_bg_restart);
7882 INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
7883 INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
7884 INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
7885 INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
7886 INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
7887 INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
7888 INIT_DELAYED_WORK(&priv->post_associate, iwl3945_bg_post_associate);
7889 INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
7890 INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
7891 INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
7892
7893 iwl3945_hw_setup_deferred_work(priv);
b481de9c
ZY		 7894
7895 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
bb8c093b 7896 iwl3945_irq_tasklet, (unsigned long)priv);
b481de9c
ZY		 7897}
7898
bb8c093b 7899static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv)
b481de9c 7900{
bb8c093b 7901 iwl3945_hw_cancel_deferred_work(priv);
b481de9c 7902
e47eb6ad 7903 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY		 7904 cancel_delayed_work(&priv->scan_check);
7905 cancel_delayed_work(&priv->alive_start);
7906 cancel_delayed_work(&priv->post_associate);
7907 cancel_work_sync(&priv->beacon_update);
7908}
7909
bb8c093b 7910static struct attribute *iwl3945_sysfs_entries[] = {
b481de9c
ZY		 7911 &dev_attr_antenna.attr,
7912 &dev_attr_channels.attr,
7913 &dev_attr_dump_errors.attr,
7914 &dev_attr_dump_events.attr,
7915 &dev_attr_flags.attr,
7916 &dev_attr_filter_flags.attr,
c8b0e6e1 7917#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 7918 &dev_attr_measurement.attr,
7919#endif
7920 &dev_attr_power_level.attr,
b481de9c
ZY		 7921 &dev_attr_retry_rate.attr,
7922 &dev_attr_rf_kill.attr,
7923 &dev_attr_rs_window.attr,
7924 &dev_attr_statistics.attr,
7925 &dev_attr_status.attr,
7926 &dev_attr_temperature.attr,
b481de9c
ZY		 7927 &dev_attr_tx_power.attr,
7928
7929 NULL
7930};
7931
bb8c093b 7932static struct attribute_group iwl3945_attribute_group = {
b481de9c 7933 .name = NULL, /* put in device directory */
bb8c093b 7934 .attrs = iwl3945_sysfs_entries,
b481de9c
ZY		 7935};
7936
bb8c093b
CH		 7937static struct ieee80211_ops iwl3945_hw_ops = {
7938 .tx = iwl3945_mac_tx,
7939 .start = iwl3945_mac_start,
7940 .stop = iwl3945_mac_stop,
7941 .add_interface = iwl3945_mac_add_interface,
7942 .remove_interface = iwl3945_mac_remove_interface,
7943 .config = iwl3945_mac_config,
7944 .config_interface = iwl3945_mac_config_interface,
7945 .configure_filter = iwl3945_configure_filter,
7946 .set_key = iwl3945_mac_set_key,
7947 .get_stats = iwl3945_mac_get_stats,
7948 .get_tx_stats = iwl3945_mac_get_tx_stats,
7949 .conf_tx = iwl3945_mac_conf_tx,
7950 .get_tsf = iwl3945_mac_get_tsf,
7951 .reset_tsf = iwl3945_mac_reset_tsf,
7952 .beacon_update = iwl3945_mac_beacon_update,
7953 .hw_scan = iwl3945_mac_hw_scan
b481de9c
ZY		 7954};
7955
bb8c093b 7956static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY		 7957{
7958 int err = 0;
bb8c093b 7959 struct iwl3945_priv *priv;
b481de9c 7960 struct ieee80211_hw *hw;
82b9a121 7961 struct iwl_3945_cfg *cfg = (struct iwl_3945_cfg *)(ent->driver_data);
b481de9c 7962 int i;
0359facc 7963 unsigned long flags;
5a66926a 7964 DECLARE_MAC_BUF(mac);
b481de9c 7965
6440adb5
CB		 7966 /* Disabling hardware scan means that mac80211 will perform scans
7967 * "the hard way", rather than using device's scan. */
bb8c093b 7968 if (iwl3945_param_disable_hw_scan) {
b481de9c 7969 IWL_DEBUG_INFO("Disabling hw_scan\n");
bb8c093b 7970 iwl3945_hw_ops.hw_scan = NULL;
b481de9c
ZY		 7971 }
7972
bb8c093b
CH		 7973 if ((iwl3945_param_queues_num > IWL_MAX_NUM_QUEUES) ||
7974 (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) {
b481de9c
ZY		 7975 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
7976 IWL_MIN_NUM_QUEUES, IWL_MAX_NUM_QUEUES);
7977 err = -EINVAL;
7978 goto out;
7979 }
7980
7981 /* mac80211 allocates memory for this device instance, including
7982 * space for this driver's private structure */
bb8c093b 7983 hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops);
b481de9c
ZY		 7984 if (hw == NULL) {
7985 IWL_ERROR("Can not allocate network device\n");
7986 err = -ENOMEM;
7987 goto out;
7988 }
7989 SET_IEEE80211_DEV(hw, &pdev->dev);
7990
f51359a8
JB		 7991 hw->rate_control_algorithm = "iwl-3945-rs";
7992
b481de9c
ZY		 7993 IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
7994 priv = hw->priv;
7995 priv->hw = hw;
7996
7997 priv->pci_dev = pdev;
82b9a121 7998 priv->cfg = cfg;
6440adb5
CB		 7999
8000 /* Select antenna (may be helpful if only one antenna is connected) */
bb8c093b 8001 priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna;
c8b0e6e1 8002#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8003 iwl3945_debug_level = iwl3945_param_debug;
b481de9c
ZY		 8004 atomic_set(&priv->restrict_refcnt, 0);
8005#endif
8006 priv->retry_rate = 1;
8007
8008 priv->ibss_beacon = NULL;
8009
8010 /* Tell mac80211 and its clients (e.g. Wireless Extensions)
8011 * the range of signal quality values that we'll provide.
8012 * Negative values for level/noise indicate that we'll provide dBm.
8013 * For WE, at least, non-0 values here *enable* display of values
8014 * in app (iwconfig). */
8015 hw->max_rssi = -20; /* signal level, negative indicates dBm */
8016 hw->max_noise = -20; /* noise level, negative indicates dBm */
8017 hw->max_signal = 100; /* link quality indication (%) */
8018
8019 /* Tell mac80211 our Tx characteristics */
8020 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE;
8021
6440adb5 8022 /* 4 EDCA QOS priorities */
b481de9c
ZY		 8023 hw->queues = 4;
8024
8025 spin_lock_init(&priv->lock);
8026 spin_lock_init(&priv->power_data.lock);
8027 spin_lock_init(&priv->sta_lock);
8028 spin_lock_init(&priv->hcmd_lock);
8029
8030 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
8031 INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
8032
8033 INIT_LIST_HEAD(&priv->free_frames);
8034
8035 mutex_init(&priv->mutex);
8036 if (pci_enable_device(pdev)) {
8037 err = -ENODEV;
8038 goto out_ieee80211_free_hw;
8039 }
8040
8041 pci_set_master(pdev);
8042
6440adb5 8043 /* Clear the driver's (not device's) station table */
bb8c093b 8044 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 8045
8046 priv->data_retry_limit = -1;
8047 priv->ieee_channels = NULL;
8048 priv->ieee_rates = NULL;
8318d78a 8049 priv->band = IEEE80211_BAND_2GHZ;
b481de9c
ZY		 8050
8051 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
8052 if (!err)
8053 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
8054 if (err) {
8055 printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
8056 goto out_pci_disable_device;
8057 }
8058
8059 pci_set_drvdata(pdev, priv);
8060 err = pci_request_regions(pdev, DRV_NAME);
8061 if (err)
8062 goto out_pci_disable_device;
6440adb5 8063
b481de9c
ZY		 8064 /* We disable the RETRY_TIMEOUT register (0x41) to keep
8065 * PCI Tx retries from interfering with C3 CPU state */
8066 pci_write_config_byte(pdev, 0x41, 0x00);
6440adb5 8067
b481de9c
ZY		 8068 priv->hw_base = pci_iomap(pdev, 0, 0);
8069 if (!priv->hw_base) {
8070 err = -ENODEV;
8071 goto out_pci_release_regions;
8072 }
8073
8074 IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
8075 (unsigned long long) pci_resource_len(pdev, 0));
8076 IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
8077
8078 /* Initialize module parameter values here */
8079
6440adb5 8080 /* Disable radio (SW RF KILL) via parameter when loading driver */
bb8c093b 8081 if (iwl3945_param_disable) {
b481de9c
ZY		 8082 set_bit(STATUS_RF_KILL_SW, &priv->status);
8083 IWL_DEBUG_INFO("Radio disabled.\n");
8084 }
8085
8086 priv->iw_mode = IEEE80211_IF_TYPE_STA;
8087
b481de9c 8088 printk(KERN_INFO DRV_NAME
82b9a121 8089 ": Detected Intel Wireless WiFi Link %s\n", priv->cfg->name);
b481de9c
ZY		 8090
8091 /* Device-specific setup */
bb8c093b 8092 if (iwl3945_hw_set_hw_setting(priv)) {
b481de9c 8093 IWL_ERROR("failed to set hw settings\n");
b481de9c
ZY		 8094 goto out_iounmap;
8095 }
8096
bb8c093b 8097 if (iwl3945_param_qos_enable)
b481de9c
ZY		 8098 priv->qos_data.qos_enable = 1;
8099
bb8c093b 8100 iwl3945_reset_qos(priv);
b481de9c
ZY		 8101
8102 priv->qos_data.qos_active = 0;
8103 priv->qos_data.qos_cap.val = 0;
b481de9c 8104
8318d78a 8105 iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
bb8c093b
CH		 8106 iwl3945_setup_deferred_work(priv);
8107 iwl3945_setup_rx_handlers(priv);
b481de9c
ZY		 8108
8109 priv->rates_mask = IWL_RATES_MASK;
8110 /* If power management is turned on, default to AC mode */
8111 priv->power_mode = IWL_POWER_AC;
8112 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
8113
0359facc 8114 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 8115 iwl3945_disable_interrupts(priv);
0359facc 8116 spin_unlock_irqrestore(&priv->lock, flags);
49df2b33 8117
bb8c093b 8118 err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c
ZY		 8119 if (err) {
8120 IWL_ERROR("failed to create sysfs device attributes\n");
b481de9c
ZY		 8121 goto out_release_irq;
8122 }
8123
5a66926a
ZY		 8124 /* nic init */
8125 iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
8126 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
8127
8128 iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
8129 err = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
8130 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
8131 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
8132 if (err < 0) {
8133 IWL_DEBUG_INFO("Failed to init the card\n");
8134 goto out_remove_sysfs;
8135 }
8136 /* Read the EEPROM */
8137 err = iwl3945_eeprom_init(priv);
b481de9c 8138 if (err) {
5a66926a
ZY		 8139 IWL_ERROR("Unable to init EEPROM\n");
8140 goto out_remove_sysfs;
b481de9c 8141 }
5a66926a
ZY		 8142 /* MAC Address location in EEPROM same for 3945/4965 */
8143 get_eeprom_mac(priv, priv->mac_addr);
8144 IWL_DEBUG_INFO("MAC address: %s\n", print_mac(mac, priv->mac_addr));
8145 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
b481de9c 8146
849e0dce
RC		 8147 err = iwl3945_init_channel_map(priv);
8148 if (err) {
8149 IWL_ERROR("initializing regulatory failed: %d\n", err);
8150 goto out_remove_sysfs;
8151 }
8152
8153 err = iwl3945_init_geos(priv);
8154 if (err) {
8155 IWL_ERROR("initializing geos failed: %d\n", err);
8156 goto out_free_channel_map;
8157 }
849e0dce 8158
5a66926a
ZY		 8159 err = ieee80211_register_hw(priv->hw);
8160 if (err) {
8161 IWL_ERROR("Failed to register network device (error %d)\n", err);
849e0dce 8162 goto out_free_geos;
5a66926a 8163 }
b481de9c 8164
5a66926a
ZY		 8165 priv->hw->conf.beacon_int = 100;
8166 priv->mac80211_registered = 1;
8167 pci_save_state(pdev);
8168 pci_disable_device(pdev);
b481de9c
ZY		 8169
8170 return 0;
8171
849e0dce
RC		 8172 out_free_geos:
8173 iwl3945_free_geos(priv);
8174 out_free_channel_map:
8175 iwl3945_free_channel_map(priv);
5a66926a 8176 out_remove_sysfs:
bb8c093b 8177 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c
ZY		 8178
8179 out_release_irq:
b481de9c
ZY		 8180 destroy_workqueue(priv->workqueue);
8181 priv->workqueue = NULL;
bb8c093b 8182 iwl3945_unset_hw_setting(priv);
b481de9c
ZY		 8183
8184 out_iounmap:
8185 pci_iounmap(pdev, priv->hw_base);
8186 out_pci_release_regions:
8187 pci_release_regions(pdev);
8188 out_pci_disable_device:
8189 pci_disable_device(pdev);
8190 pci_set_drvdata(pdev, NULL);
8191 out_ieee80211_free_hw:
8192 ieee80211_free_hw(priv->hw);
8193 out:
8194 return err;
8195}
8196
c83dbf68 8197static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
b481de9c 8198{
bb8c093b 8199 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c
ZY		 8200 struct list_head *p, *q;
8201 int i;
0359facc 8202 unsigned long flags;
b481de9c
ZY		 8203
8204 if (!priv)
8205 return;
8206
8207 IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
8208
b481de9c 8209 set_bit(STATUS_EXIT_PENDING, &priv->status);
b24d22b1 8210
bb8c093b 8211 iwl3945_down(priv);
b481de9c 8212
0359facc
MA		 8213 /* make sure we flush any pending irq or
8214 * tasklet for the driver
8215 */
8216 spin_lock_irqsave(&priv->lock, flags);
8217 iwl3945_disable_interrupts(priv);
8218 spin_unlock_irqrestore(&priv->lock, flags);
8219
8220 iwl_synchronize_irq(priv);
8221
b481de9c
ZY		 8222 /* Free MAC hash list for ADHOC */
8223 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) {
8224 list_for_each_safe(p, q, &priv->ibss_mac_hash[i]) {
8225 list_del(p);
bb8c093b 8226 kfree(list_entry(p, struct iwl3945_ibss_seq, list));
b481de9c
ZY		 8227 }
8228 }
8229
bb8c093b 8230 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 8231
bb8c093b 8232 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY		 8233
8234 if (priv->rxq.bd)
bb8c093b
CH		 8235 iwl3945_rx_queue_free(priv, &priv->rxq);
8236 iwl3945_hw_txq_ctx_free(priv);
b481de9c 8237
bb8c093b
CH		 8238 iwl3945_unset_hw_setting(priv);
8239 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 8240
8241 if (priv->mac80211_registered) {
8242 ieee80211_unregister_hw(priv->hw);
b481de9c
ZY		 8243 }
8244
6ef89d0a
MA		 8245 /*netif_stop_queue(dev); */
8246 flush_workqueue(priv->workqueue);
8247
bb8c093b 8248 /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
b481de9c
ZY		 8249 * priv->workqueue... so we can't take down the workqueue
8250 * until now... */
8251 destroy_workqueue(priv->workqueue);
8252 priv->workqueue = NULL;
8253
b481de9c
ZY		 8254 pci_iounmap(pdev, priv->hw_base);
8255 pci_release_regions(pdev);
8256 pci_disable_device(pdev);
8257 pci_set_drvdata(pdev, NULL);
8258
849e0dce
RC		 8259 iwl3945_free_channel_map(priv);
8260 iwl3945_free_geos(priv);
b481de9c
ZY		 8261
8262 if (priv->ibss_beacon)
8263 dev_kfree_skb(priv->ibss_beacon);
8264
8265 ieee80211_free_hw(priv->hw);
8266}
8267
8268#ifdef CONFIG_PM
8269
bb8c093b 8270static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
b481de9c 8271{
bb8c093b 8272 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c 8273
e655b9f0
ZY		 8274 if (priv->is_open) {
8275 set_bit(STATUS_IN_SUSPEND, &priv->status);
8276 iwl3945_mac_stop(priv->hw);
8277 priv->is_open = 1;
8278 }
b481de9c 8279
b481de9c
ZY		 8280 pci_set_power_state(pdev, PCI_D3hot);
8281
b481de9c
ZY		 8282 return 0;
8283}
8284
bb8c093b 8285static int iwl3945_pci_resume(struct pci_dev *pdev)
b481de9c 8286{
bb8c093b 8287 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c 8288
b481de9c 8289 pci_set_power_state(pdev, PCI_D0);
b481de9c 8290
e655b9f0
ZY		 8291 if (priv->is_open)
8292 iwl3945_mac_start(priv->hw);
b481de9c 8293
e655b9f0 8294 clear_bit(STATUS_IN_SUSPEND, &priv->status);
b481de9c
ZY		 8295 return 0;
8296}
8297
8298#endif /* CONFIG_PM */
8299
8300/*****************************************************************************
8301 *
8302 * driver and module entry point
8303 *
8304 *****************************************************************************/
8305
bb8c093b 8306static struct pci_driver iwl3945_driver = {
b481de9c 8307 .name = DRV_NAME,
bb8c093b
CH		 8308 .id_table = iwl3945_hw_card_ids,
8309 .probe = iwl3945_pci_probe,
8310 .remove = __devexit_p(iwl3945_pci_remove),
b481de9c 8311#ifdef CONFIG_PM
bb8c093b
CH		 8312 .suspend = iwl3945_pci_suspend,
8313 .resume = iwl3945_pci_resume,
b481de9c
ZY		 8314#endif
8315};
8316
bb8c093b 8317static int __init iwl3945_init(void)
b481de9c
ZY		 8318{
8319
8320 int ret;
8321 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
8322 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2
RC		 8323
8324 ret = iwl3945_rate_control_register();
8325 if (ret) {
8326 IWL_ERROR("Unable to register rate control algorithm: %d\n", ret);
8327 return ret;
8328 }
8329
bb8c093b 8330 ret = pci_register_driver(&iwl3945_driver);
b481de9c
ZY		 8331 if (ret) {
8332 IWL_ERROR("Unable to initialize PCI module\n");
897e1cf2 8333 goto error_register;
b481de9c 8334 }
c8b0e6e1 8335#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8336 ret = driver_create_file(&iwl3945_driver.driver, &driver_attr_debug_level);
b481de9c
ZY		 8337 if (ret) {
8338 IWL_ERROR("Unable to create driver sysfs file\n");
897e1cf2 8339 goto error_debug;
b481de9c
ZY		 8340 }
8341#endif
8342
8343 return ret;
897e1cf2
RC		 8344
8345#ifdef CONFIG_IWL3945_DEBUG
8346error_debug:
8347 pci_unregister_driver(&iwl3945_driver);
8348#endif
8349error_register:
8350 iwl3945_rate_control_unregister();
8351 return ret;
b481de9c
ZY		 8352}
8353
bb8c093b 8354static void __exit iwl3945_exit(void)
b481de9c 8355{
c8b0e6e1 8356#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8357 driver_remove_file(&iwl3945_driver.driver, &driver_attr_debug_level);
b481de9c 8358#endif
bb8c093b 8359 pci_unregister_driver(&iwl3945_driver);
897e1cf2 8360 iwl3945_rate_control_unregister();
b481de9c
ZY		 8361}
8362
bb8c093b 8363module_param_named(antenna, iwl3945_param_antenna, int, 0444);
b481de9c 8364MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
bb8c093b 8365module_param_named(disable, iwl3945_param_disable, int, 0444);
b481de9c 8366MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
bb8c093b 8367module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444);
b481de9c
ZY		 8368MODULE_PARM_DESC(hwcrypto,
8369 "using hardware crypto engine (default 0 [software])\n");
bb8c093b 8370module_param_named(debug, iwl3945_param_debug, int, 0444);
b481de9c 8371MODULE_PARM_DESC(debug, "debug output mask");
bb8c093b 8372module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444);
b481de9c
ZY		 8373MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
8374
bb8c093b 8375module_param_named(queues_num, iwl3945_param_queues_num, int, 0444);
b481de9c
ZY		 8376MODULE_PARM_DESC(queues_num, "number of hw queues.");
8377
8378/* QoS */
bb8c093b 8379module_param_named(qos_enable, iwl3945_param_qos_enable, int, 0444);
b481de9c
ZY		 8380MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
8381
bb8c093b
CH		 8382module_exit(iwl3945_exit);
8383module_init(iwl3945_init);
Linux kernel - Deliverables
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