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mac80211: insert AP sta entry after filling it
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl3945-base.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
b481de9c
ZY		 30#include <linux/kernel.h>
31#include <linux/module.h>
b481de9c
ZY		 32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
36#include <linux/skbuff.h>
37#include <linux/netdevice.h>
38#include <linux/wireless.h>
39#include <linux/firmware.h>
b481de9c
ZY		 40#include <linux/etherdevice.h>
41#include <linux/if_arp.h>
42
43#include <net/ieee80211_radiotap.h>
44#include <net/mac80211.h>
45
46#include <asm/div64.h>
47
82b9a121 48#include "iwl-3945-core.h"
b481de9c
ZY		 49#include "iwl-3945.h"
50#include "iwl-helpers.h"
51
c8b0e6e1 52#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 53u32 iwl3945_debug_level;
b481de9c
ZY		 54#endif
55
bb8c093b
CH		 56static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
57 struct iwl3945_tx_queue *txq);
416e1438 58
b481de9c
ZY		 59/******************************************************************************
60 *
61 * module boiler plate
62 *
63 ******************************************************************************/
64
65/* module parameters */
6440adb5
CB		 66static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */
67static int iwl3945_param_debug; /* def: 0 = minimal debug log messages */
68static int iwl3945_param_disable; /* def: 0 = enable radio */
9fbab516 69static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */
6440adb5
CB		 70int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */
71static int iwl3945_param_qos_enable = 1; /* def: 1 = use quality of service */
dfe7d458 72int iwl3945_param_queues_num = IWL39_MAX_NUM_QUEUES; /* def: 8 Tx queues */
b481de9c
ZY		 73
74/*
75 * module name, copyright, version, etc.
76 * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
77 */
78
79#define DRV_DESCRIPTION \
80"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
81
c8b0e6e1 82#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 83#define VD "d"
84#else
85#define VD
86#endif
87
c8b0e6e1 88#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 89#define VS "s"
90#else
91#define VS
92#endif
93
b9e0b449 94#define IWLWIFI_VERSION "1.2.26k" VD VS
eb7ae89c 95#define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation"
b481de9c
ZY		 96#define DRV_VERSION IWLWIFI_VERSION
97
b481de9c
ZY		 98
99MODULE_DESCRIPTION(DRV_DESCRIPTION);
100MODULE_VERSION(DRV_VERSION);
101MODULE_AUTHOR(DRV_COPYRIGHT);
102MODULE_LICENSE("GPL");
103
8318d78a
JB		 104static const struct ieee80211_supported_band *iwl3945_get_band(
105 struct iwl3945_priv *priv, enum ieee80211_band band)
b481de9c 106{
8318d78a 107 return priv->hw->wiphy->bands[band];
b481de9c
ZY		 108}
109
bb8c093b 110static int iwl3945_is_empty_essid(const char *essid, int essid_len)
b481de9c
ZY		 111{
112 /* Single white space is for Linksys APs */
113 if (essid_len == 1 && essid[0] == ' ')
114 return 1;
115
116 /* Otherwise, if the entire essid is 0, we assume it is hidden */
117 while (essid_len) {
118 essid_len--;
119 if (essid[essid_len] != '\0')
120 return 0;
121 }
122
123 return 1;
124}
125
bb8c093b 126static const char *iwl3945_escape_essid(const char *essid, u8 essid_len)
b481de9c
ZY		 127{
128 static char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
129 const char *s = essid;
130 char *d = escaped;
131
bb8c093b 132 if (iwl3945_is_empty_essid(essid, essid_len)) {
b481de9c
ZY		 133 memcpy(escaped, "<hidden>", sizeof("<hidden>"));
134 return escaped;
135 }
136
137 essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE);
138 while (essid_len--) {
139 if (*s == '\0') {
140 *d++ = '\\';
141 *d++ = '0';
142 s++;
143 } else
144 *d++ = *s++;
145 }
146 *d = '\0';
147 return escaped;
148}
149
b481de9c
ZY		 150/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
151 * DMA services
152 *
153 * Theory of operation
154 *
6440adb5
CB		 155 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
156 * of buffer descriptors, each of which points to one or more data buffers for
157 * the device to read from or fill. Driver and device exchange status of each
158 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
159 * entries in each circular buffer, to protect against confusing empty and full
160 * queue states.
161 *
162 * The device reads or writes the data in the queues via the device's several
163 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
b481de9c
ZY		 164 *
165 * For Tx queue, there are low mark and high mark limits. If, after queuing
166 * the packet for Tx, free space become < low mark, Tx queue stopped. When
167 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
168 * Tx queue resumed.
169 *
6440adb5
CB		 170 * The 3945 operates with six queues: One receive queue, one transmit queue
171 * (#4) for sending commands to the device firmware, and four transmit queues
172 * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
b481de9c
ZY		 173 ***************************************************/
174
c54b679d 175int iwl3945_queue_space(const struct iwl3945_queue *q)
b481de9c 176{
fc4b6853 177 int s = q->read_ptr - q->write_ptr;
b481de9c 178
fc4b6853 179 if (q->read_ptr > q->write_ptr)
b481de9c
ZY		 180 s -= q->n_bd;
181
182 if (s <= 0)
183 s += q->n_window;
184 /* keep some reserve to not confuse empty and full situations */
185 s -= 2;
186 if (s < 0)
187 s = 0;
188 return s;
189}
190
c54b679d 191int iwl3945_x2_queue_used(const struct iwl3945_queue *q, int i)
b481de9c 192{
fc4b6853
TW		 193 return q->write_ptr > q->read_ptr ?
194 (i >= q->read_ptr && i < q->write_ptr) :
195 !(i < q->read_ptr && i >= q->write_ptr);
b481de9c
ZY		 196}
197
c54b679d 198
bb8c093b 199static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge)
b481de9c 200{
6440adb5 201 /* This is for scan command, the big buffer at end of command array */
b481de9c 202 if (is_huge)
6440adb5 203 return q->n_window; /* must be power of 2 */
b481de9c 204
6440adb5 205 /* Otherwise, use normal size buffers */
b481de9c
ZY		 206 return index & (q->n_window - 1);
207}
208
6440adb5
CB		 209/**
210 * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
211 */
bb8c093b 212static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q,
b481de9c
ZY		 213 int count, int slots_num, u32 id)
214{
215 q->n_bd = count;
216 q->n_window = slots_num;
217 q->id = id;
218
c54b679d
TW		 219 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
220 * and iwl_queue_dec_wrap are broken. */
b481de9c
ZY		 221 BUG_ON(!is_power_of_2(count));
222
223 /* slots_num must be power-of-two size, otherwise
224 * get_cmd_index is broken. */
225 BUG_ON(!is_power_of_2(slots_num));
226
227 q->low_mark = q->n_window / 4;
228 if (q->low_mark < 4)
229 q->low_mark = 4;
230
231 q->high_mark = q->n_window / 8;
232 if (q->high_mark < 2)
233 q->high_mark = 2;
234
fc4b6853 235 q->write_ptr = q->read_ptr = 0;
b481de9c
ZY		 236
237 return 0;
238}
239
6440adb5
CB		 240/**
241 * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
242 */
bb8c093b
CH		 243static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
244 struct iwl3945_tx_queue *txq, u32 id)
b481de9c
ZY		 245{
246 struct pci_dev *dev = priv->pci_dev;
247
6440adb5
CB		 248 /* Driver private data, only for Tx (not command) queues,
249 * not shared with device. */
b481de9c
ZY		 250 if (id != IWL_CMD_QUEUE_NUM) {
251 txq->txb = kmalloc(sizeof(txq->txb[0]) *
252 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
253 if (!txq->txb) {
01ebd063 254 IWL_ERROR("kmalloc for auxiliary BD "
b481de9c
ZY		 255 "structures failed\n");
256 goto error;
257 }
258 } else
259 txq->txb = NULL;
260
6440adb5
CB		 261 /* Circular buffer of transmit frame descriptors (TFDs),
262 * shared with device */
b481de9c
ZY		 263 txq->bd = pci_alloc_consistent(dev,
264 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
265 &txq->q.dma_addr);
266
267 if (!txq->bd) {
268 IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
269 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
270 goto error;
271 }
272 txq->q.id = id;
273
274 return 0;
275
276 error:
3ac7f146
TW		 277 kfree(txq->txb);
278 txq->txb = NULL;
b481de9c
ZY		 279
280 return -ENOMEM;
281}
282
6440adb5
CB		 283/**
284 * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
285 */
bb8c093b
CH		 286int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
287 struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
b481de9c
ZY		 288{
289 struct pci_dev *dev = priv->pci_dev;
290 int len;
291 int rc = 0;
292
6440adb5
CB		 293 /*
294 * Alloc buffer array for commands (Tx or other types of commands).
295 * For the command queue (#4), allocate command space + one big
296 * command for scan, since scan command is very huge; the system will
297 * not have two scans at the same time, so only one is needed.
298 * For data Tx queues (all other queues), no super-size command
299 * space is needed.
300 */
bb8c093b 301 len = sizeof(struct iwl3945_cmd) * slots_num;
b481de9c
ZY		 302 if (txq_id == IWL_CMD_QUEUE_NUM)
303 len += IWL_MAX_SCAN_SIZE;
304 txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
305 if (!txq->cmd)
306 return -ENOMEM;
307
6440adb5 308 /* Alloc driver data array and TFD circular buffer */
bb8c093b 309 rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
b481de9c
ZY		 310 if (rc) {
311 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
312
313 return -ENOMEM;
314 }
315 txq->need_update = 0;
316
317 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
c54b679d 318 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
b481de9c 319 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
6440adb5
CB		 320
321 /* Initialize queue high/low-water, head/tail indexes */
bb8c093b 322 iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
b481de9c 323
6440adb5 324 /* Tell device where to find queue, enable DMA channel. */
bb8c093b 325 iwl3945_hw_tx_queue_init(priv, txq);
b481de9c
ZY		 326
327 return 0;
328}
329
330/**
bb8c093b 331 * iwl3945_tx_queue_free - Deallocate DMA queue.
b481de9c
ZY		 332 * @txq: Transmit queue to deallocate.
333 *
334 * Empty queue by removing and destroying all BD's.
6440adb5
CB		 335 * Free all buffers.
336 * 0-fill, but do not free "txq" descriptor structure.
b481de9c 337 */
bb8c093b 338void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c 339{
bb8c093b 340 struct iwl3945_queue *q = &txq->q;
b481de9c
ZY		 341 struct pci_dev *dev = priv->pci_dev;
342 int len;
343
344 if (q->n_bd == 0)
345 return;
346
347 /* first, empty all BD's */
fc4b6853 348 for (; q->write_ptr != q->read_ptr;
c54b679d 349 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
bb8c093b 350 iwl3945_hw_txq_free_tfd(priv, txq);
b481de9c 351
bb8c093b 352 len = sizeof(struct iwl3945_cmd) * q->n_window;
b481de9c
ZY		 353 if (q->id == IWL_CMD_QUEUE_NUM)
354 len += IWL_MAX_SCAN_SIZE;
355
6440adb5 356 /* De-alloc array of command/tx buffers */
b481de9c
ZY		 357 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
358
6440adb5 359 /* De-alloc circular buffer of TFDs */
b481de9c 360 if (txq->q.n_bd)
bb8c093b 361 pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
b481de9c
ZY		 362 txq->q.n_bd, txq->bd, txq->q.dma_addr);
363
6440adb5 364 /* De-alloc array of per-TFD driver data */
3ac7f146
TW		 365 kfree(txq->txb);
366 txq->txb = NULL;
b481de9c 367
6440adb5 368 /* 0-fill queue descriptor structure */
b481de9c
ZY		 369 memset(txq, 0, sizeof(*txq));
370}
371
bb8c093b 372const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
b481de9c
ZY		 373
374/*************** STATION TABLE MANAGEMENT ****
9fbab516 375 * mac80211 should be examined to determine if sta_info is duplicating
b481de9c
ZY		 376 * the functionality provided here
377 */
378
379/**************************************************************/
01ebd063 380#if 0 /* temporary disable till we add real remove station */
6440adb5
CB		 381/**
382 * iwl3945_remove_station - Remove driver's knowledge of station.
383 *
384 * NOTE: This does not remove station from device's station table.
385 */
bb8c093b 386static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
b481de9c
ZY		 387{
388 int index = IWL_INVALID_STATION;
389 int i;
390 unsigned long flags;
391
392 spin_lock_irqsave(&priv->sta_lock, flags);
393
394 if (is_ap)
395 index = IWL_AP_ID;
396 else if (is_broadcast_ether_addr(addr))
397 index = priv->hw_setting.bcast_sta_id;
398 else
399 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
400 if (priv->stations[i].used &&
401 !compare_ether_addr(priv->stations[i].sta.sta.addr,
402 addr)) {
403 index = i;
404 break;
405 }
406
407 if (unlikely(index == IWL_INVALID_STATION))
408 goto out;
409
410 if (priv->stations[index].used) {
411 priv->stations[index].used = 0;
412 priv->num_stations--;
413 }
414
415 BUG_ON(priv->num_stations < 0);
416
417out:
418 spin_unlock_irqrestore(&priv->sta_lock, flags);
419 return 0;
420}
556f8db7 421#endif
6440adb5
CB		 422
423/**
424 * iwl3945_clear_stations_table - Clear the driver's station table
425 *
426 * NOTE: This does not clear or otherwise alter the device's station table.
427 */
bb8c093b 428static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
b481de9c
ZY		 429{
430 unsigned long flags;
431
432 spin_lock_irqsave(&priv->sta_lock, flags);
433
434 priv->num_stations = 0;
435 memset(priv->stations, 0, sizeof(priv->stations));
436
437 spin_unlock_irqrestore(&priv->sta_lock, flags);
438}
439
6440adb5
CB		 440/**
441 * iwl3945_add_station - Add station to station tables in driver and device
442 */
bb8c093b 443u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
b481de9c
ZY		 444{
445 int i;
446 int index = IWL_INVALID_STATION;
bb8c093b 447 struct iwl3945_station_entry *station;
b481de9c 448 unsigned long flags_spin;
c14c521e 449 u8 rate;
b481de9c
ZY		 450
451 spin_lock_irqsave(&priv->sta_lock, flags_spin);
452 if (is_ap)
453 index = IWL_AP_ID;
454 else if (is_broadcast_ether_addr(addr))
455 index = priv->hw_setting.bcast_sta_id;
456 else
457 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
458 if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
459 addr)) {
460 index = i;
461 break;
462 }
463
464 if (!priv->stations[i].used &&
465 index == IWL_INVALID_STATION)
466 index = i;
467 }
468
01ebd063 469 /* These two conditions has the same outcome but keep them separate
b481de9c
ZY		 470 since they have different meaning */
471 if (unlikely(index == IWL_INVALID_STATION)) {
472 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
473 return index;
474 }
475
476 if (priv->stations[index].used &&
477 !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
478 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
479 return index;
480 }
481
e174961c 482 IWL_DEBUG_ASSOC("Add STA ID %d: %pM\n", index, addr);
b481de9c
ZY		 483 station = &priv->stations[index];
484 station->used = 1;
485 priv->num_stations++;
486
6440adb5 487 /* Set up the REPLY_ADD_STA command to send to device */
bb8c093b 488 memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
b481de9c
ZY		 489 memcpy(station->sta.sta.addr, addr, ETH_ALEN);
490 station->sta.mode = 0;
491 station->sta.sta.sta_id = index;
492 station->sta.station_flags = 0;
493
8318d78a 494 if (priv->band == IEEE80211_BAND_5GHZ)
69946333
TW		 495 rate = IWL_RATE_6M_PLCP;
496 else
497 rate = IWL_RATE_1M_PLCP;
c14c521e
ZY		 498
499 /* Turn on both antennas for the station... */
500 station->sta.rate_n_flags =
bb8c093b 501 iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
c14c521e
ZY		 502 station->current_rate.rate_n_flags =
503 le16_to_cpu(station->sta.rate_n_flags);
504
b481de9c 505 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
6440adb5
CB		 506
507 /* Add station to device's station table */
bb8c093b 508 iwl3945_send_add_station(priv, &station->sta, flags);
b481de9c
ZY		 509 return index;
510
511}
512
513/*************** DRIVER STATUS FUNCTIONS *****/
514
bb8c093b 515static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
b481de9c
ZY		 516{
517 /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
518 * set but EXIT_PENDING is not */
519 return test_bit(STATUS_READY, &priv->status) &&
520 test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
521 !test_bit(STATUS_EXIT_PENDING, &priv->status);
522}
523
bb8c093b 524static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
b481de9c
ZY		 525{
526 return test_bit(STATUS_ALIVE, &priv->status);
527}
528
bb8c093b 529static inline int iwl3945_is_init(struct iwl3945_priv *priv)
b481de9c
ZY		 530{
531 return test_bit(STATUS_INIT, &priv->status);
532}
533
80fcc9e2
AG		 534static inline int iwl3945_is_rfkill_sw(struct iwl3945_priv *priv)
535{
536 return test_bit(STATUS_RF_KILL_SW, &priv->status);
537}
538
539static inline int iwl3945_is_rfkill_hw(struct iwl3945_priv *priv)
540{
541 return test_bit(STATUS_RF_KILL_HW, &priv->status);
542}
543
bb8c093b 544static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
b481de9c 545{
80fcc9e2
AG		 546 return iwl3945_is_rfkill_hw(priv) ||
547 iwl3945_is_rfkill_sw(priv);
b481de9c
ZY		 548}
549
bb8c093b 550static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
b481de9c
ZY		 551{
552
bb8c093b 553 if (iwl3945_is_rfkill(priv))
b481de9c
ZY		 554 return 0;
555
bb8c093b 556 return iwl3945_is_ready(priv);
b481de9c
ZY		 557}
558
559/*************** HOST COMMAND QUEUE FUNCTIONS *****/
560
561#define IWL_CMD(x) case x : return #x
562
563static const char *get_cmd_string(u8 cmd)
564{
565 switch (cmd) {
566 IWL_CMD(REPLY_ALIVE);
567 IWL_CMD(REPLY_ERROR);
568 IWL_CMD(REPLY_RXON);
569 IWL_CMD(REPLY_RXON_ASSOC);
570 IWL_CMD(REPLY_QOS_PARAM);
571 IWL_CMD(REPLY_RXON_TIMING);
572 IWL_CMD(REPLY_ADD_STA);
573 IWL_CMD(REPLY_REMOVE_STA);
574 IWL_CMD(REPLY_REMOVE_ALL_STA);
575 IWL_CMD(REPLY_3945_RX);
576 IWL_CMD(REPLY_TX);
577 IWL_CMD(REPLY_RATE_SCALE);
578 IWL_CMD(REPLY_LEDS_CMD);
579 IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
580 IWL_CMD(RADAR_NOTIFICATION);
581 IWL_CMD(REPLY_QUIET_CMD);
582 IWL_CMD(REPLY_CHANNEL_SWITCH);
583 IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
584 IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
585 IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
586 IWL_CMD(POWER_TABLE_CMD);
587 IWL_CMD(PM_SLEEP_NOTIFICATION);
588 IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
589 IWL_CMD(REPLY_SCAN_CMD);
590 IWL_CMD(REPLY_SCAN_ABORT_CMD);
591 IWL_CMD(SCAN_START_NOTIFICATION);
592 IWL_CMD(SCAN_RESULTS_NOTIFICATION);
593 IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
594 IWL_CMD(BEACON_NOTIFICATION);
595 IWL_CMD(REPLY_TX_BEACON);
596 IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
597 IWL_CMD(QUIET_NOTIFICATION);
598 IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
599 IWL_CMD(MEASURE_ABORT_NOTIFICATION);
600 IWL_CMD(REPLY_BT_CONFIG);
601 IWL_CMD(REPLY_STATISTICS_CMD);
602 IWL_CMD(STATISTICS_NOTIFICATION);
603 IWL_CMD(REPLY_CARD_STATE_CMD);
604 IWL_CMD(CARD_STATE_NOTIFICATION);
605 IWL_CMD(MISSED_BEACONS_NOTIFICATION);
606 default:
607 return "UNKNOWN";
608
609 }
610}
611
612#define HOST_COMPLETE_TIMEOUT (HZ / 2)
613
614/**
bb8c093b 615 * iwl3945_enqueue_hcmd - enqueue a uCode command
b481de9c
ZY		 616 * @priv: device private data point
617 * @cmd: a point to the ucode command structure
618 *
619 * The function returns < 0 values to indicate the operation is
620 * failed. On success, it turns the index (> 0) of command in the
621 * command queue.
622 */
bb8c093b 623static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c 624{
bb8c093b
CH		 625 struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
626 struct iwl3945_queue *q = &txq->q;
627 struct iwl3945_tfd_frame *tfd;
b481de9c 628 u32 *control_flags;
bb8c093b 629 struct iwl3945_cmd *out_cmd;
b481de9c
ZY		 630 u32 idx;
631 u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
632 dma_addr_t phys_addr;
633 int pad;
634 u16 count;
635 int ret;
636 unsigned long flags;
637
638 /* If any of the command structures end up being larger than
639 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
640 * we will need to increase the size of the TFD entries */
641 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
642 !(cmd->meta.flags & CMD_SIZE_HUGE));
643
c342a1b9
GG		 644
645 if (iwl3945_is_rfkill(priv)) {
646 IWL_DEBUG_INFO("Not sending command - RF KILL");
647 return -EIO;
648 }
649
bb8c093b 650 if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
b481de9c
ZY		 651 IWL_ERROR("No space for Tx\n");
652 return -ENOSPC;
653 }
654
655 spin_lock_irqsave(&priv->hcmd_lock, flags);
656
fc4b6853 657 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY		 658 memset(tfd, 0, sizeof(*tfd));
659
660 control_flags = (u32 *) tfd;
661
fc4b6853 662 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
b481de9c
ZY		 663 out_cmd = &txq->cmd[idx];
664
665 out_cmd->hdr.cmd = cmd->id;
666 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
667 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
668
669 /* At this point, the out_cmd now has all of the incoming cmd
670 * information */
671
672 out_cmd->hdr.flags = 0;
673 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
fc4b6853 674 INDEX_TO_SEQ(q->write_ptr));
b481de9c
ZY		 675 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
676 out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
677
678 phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
bb8c093b
CH		 679 offsetof(struct iwl3945_cmd, hdr);
680 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
b481de9c
ZY		 681
682 pad = U32_PAD(cmd->len);
683 count = TFD_CTL_COUNT_GET(*control_flags);
684 *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
685
686 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
687 "%d bytes at %d[%d]:%d\n",
688 get_cmd_string(out_cmd->hdr.cmd),
689 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
fc4b6853 690 fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
b481de9c
ZY		 691
692 txq->need_update = 1;
6440adb5
CB		 693
694 /* Increment and update queue's write index */
c54b679d 695 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
bb8c093b 696 ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 697
698 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
699 return ret ? ret : idx;
700}
701
bb8c093b 702static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c
ZY		 703{
704 int ret;
705
706 BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
707
708 /* An asynchronous command can not expect an SKB to be set. */
709 BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
710
711 /* An asynchronous command MUST have a callback. */
712 BUG_ON(!cmd->meta.u.callback);
713
714 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
715 return -EBUSY;
716
bb8c093b 717 ret = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c 718 if (ret < 0) {
bb8c093b 719 IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
b481de9c
ZY		 720 get_cmd_string(cmd->id), ret);
721 return ret;
722 }
723 return 0;
724}
725
bb8c093b 726static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c
ZY		 727{
728 int cmd_idx;
729 int ret;
b481de9c
ZY		 730
731 BUG_ON(cmd->meta.flags & CMD_ASYNC);
732
733 /* A synchronous command can not have a callback set. */
734 BUG_ON(cmd->meta.u.callback != NULL);
735
e5472978 736 if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) {
b481de9c
ZY		 737 IWL_ERROR("Error sending %s: Already sending a host command\n",
738 get_cmd_string(cmd->id));
e5472978
TW		 739 ret = -EBUSY;
740 goto out;
b481de9c
ZY		 741 }
742
743 set_bit(STATUS_HCMD_ACTIVE, &priv->status);
744
745 if (cmd->meta.flags & CMD_WANT_SKB)
746 cmd->meta.source = &cmd->meta;
747
bb8c093b 748 cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c
ZY		 749 if (cmd_idx < 0) {
750 ret = cmd_idx;
bb8c093b 751 IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
b481de9c
ZY		 752 get_cmd_string(cmd->id), ret);
753 goto out;
754 }
755
756 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
757 !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
758 HOST_COMPLETE_TIMEOUT);
759 if (!ret) {
760 if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
761 IWL_ERROR("Error sending %s: time out after %dms.\n",
762 get_cmd_string(cmd->id),
763 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
764
765 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
766 ret = -ETIMEDOUT;
767 goto cancel;
768 }
769 }
770
771 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
772 IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
773 get_cmd_string(cmd->id));
774 ret = -ECANCELED;
775 goto fail;
776 }
777 if (test_bit(STATUS_FW_ERROR, &priv->status)) {
778 IWL_DEBUG_INFO("Command %s failed: FW Error\n",
779 get_cmd_string(cmd->id));
780 ret = -EIO;
781 goto fail;
782 }
783 if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
784 IWL_ERROR("Error: Response NULL in '%s'\n",
785 get_cmd_string(cmd->id));
786 ret = -EIO;
787 goto out;
788 }
789
790 ret = 0;
791 goto out;
792
793cancel:
794 if (cmd->meta.flags & CMD_WANT_SKB) {
bb8c093b 795 struct iwl3945_cmd *qcmd;
b481de9c
ZY		 796
797 /* Cancel the CMD_WANT_SKB flag for the cmd in the
798 * TX cmd queue. Otherwise in case the cmd comes
799 * in later, it will possibly set an invalid
800 * address (cmd->meta.source). */
801 qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
802 qcmd->meta.flags &= ~CMD_WANT_SKB;
803 }
804fail:
805 if (cmd->meta.u.skb) {
806 dev_kfree_skb_any(cmd->meta.u.skb);
807 cmd->meta.u.skb = NULL;
808 }
809out:
e5472978 810 clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status);
b481de9c
ZY		 811 return ret;
812}
813
bb8c093b 814int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c 815{
b481de9c 816 if (cmd->meta.flags & CMD_ASYNC)
bb8c093b 817 return iwl3945_send_cmd_async(priv, cmd);
b481de9c 818
bb8c093b 819 return iwl3945_send_cmd_sync(priv, cmd);
b481de9c
ZY		 820}
821
bb8c093b 822int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
b481de9c 823{
bb8c093b 824 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 825 .id = id,
826 .len = len,
827 .data = data,
828 };
829
bb8c093b 830 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 831}
832
bb8c093b 833static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
b481de9c 834{
bb8c093b 835 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 836 .id = id,
837 .len = sizeof(val),
838 .data = &val,
839 };
840
bb8c093b 841 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 842}
843
bb8c093b 844int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
b481de9c 845{
bb8c093b 846 return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
b481de9c
ZY		 847}
848
b481de9c 849/**
bb8c093b 850 * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
8318d78a
JB		 851 * @band: 2.4 or 5 GHz band
852 * @channel: Any channel valid for the requested band
b481de9c 853
8318d78a 854 * In addition to setting the staging RXON, priv->band is also set.
b481de9c
ZY		 855 *
856 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
8318d78a 857 * in the staging RXON flag structure based on the band
b481de9c 858 */
8318d78a
JB		 859static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv,
860 enum ieee80211_band band,
861 u16 channel)
b481de9c 862{
8318d78a 863 if (!iwl3945_get_channel_info(priv, band, channel)) {
b481de9c 864 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
8318d78a 865 channel, band);
b481de9c
ZY		 866 return -EINVAL;
867 }
868
869 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
8318d78a 870 (priv->band == band))
b481de9c
ZY		 871 return 0;
872
873 priv->staging_rxon.channel = cpu_to_le16(channel);
8318d78a 874 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 875 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
876 else
877 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
878
8318d78a 879 priv->band = band;
b481de9c 880
8318d78a 881 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
b481de9c
ZY		 882
883 return 0;
884}
885
886/**
bb8c093b 887 * iwl3945_check_rxon_cmd - validate RXON structure is valid
b481de9c
ZY		 888 *
889 * NOTE: This is really only useful during development and can eventually
890 * be #ifdef'd out once the driver is stable and folks aren't actively
891 * making changes
892 */
bb8c093b 893static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon)
b481de9c
ZY		 894{
895 int error = 0;
896 int counter = 1;
897
898 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
899 error |= le32_to_cpu(rxon->flags &
900 (RXON_FLG_TGJ_NARROW_BAND_MSK |
901 RXON_FLG_RADAR_DETECT_MSK));
902 if (error)
903 IWL_WARNING("check 24G fields %d | %d\n",
904 counter++, error);
905 } else {
906 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
907 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
908 if (error)
909 IWL_WARNING("check 52 fields %d | %d\n",
910 counter++, error);
911 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
912 if (error)
913 IWL_WARNING("check 52 CCK %d | %d\n",
914 counter++, error);
915 }
916 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
917 if (error)
918 IWL_WARNING("check mac addr %d | %d\n", counter++, error);
919
920 /* make sure basic rates 6Mbps and 1Mbps are supported */
921 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
922 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
923 if (error)
924 IWL_WARNING("check basic rate %d | %d\n", counter++, error);
925
926 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
927 if (error)
928 IWL_WARNING("check assoc id %d | %d\n", counter++, error);
929
930 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
931 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
932 if (error)
933 IWL_WARNING("check CCK and short slot %d | %d\n",
934 counter++, error);
935
936 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
937 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
938 if (error)
939 IWL_WARNING("check CCK & auto detect %d | %d\n",
940 counter++, error);
941
942 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
943 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
944 if (error)
945 IWL_WARNING("check TGG and auto detect %d | %d\n",
946 counter++, error);
947
948 if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
949 error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
950 RXON_FLG_ANT_A_MSK)) == 0);
951 if (error)
952 IWL_WARNING("check antenna %d %d\n", counter++, error);
953
954 if (error)
955 IWL_WARNING("Tuning to channel %d\n",
956 le16_to_cpu(rxon->channel));
957
958 if (error) {
bb8c093b 959 IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
b481de9c
ZY		 960 return -1;
961 }
962 return 0;
963}
964
965/**
9fbab516 966 * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
01ebd063 967 * @priv: staging_rxon is compared to active_rxon
b481de9c 968 *
9fbab516
BC		 969 * If the RXON structure is changing enough to require a new tune,
970 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
971 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
b481de9c 972 */
bb8c093b 973static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
b481de9c
ZY		 974{
975
976 /* These items are only settable from the full RXON command */
5d1e2325 977 if (!(iwl3945_is_associated(priv)) ||
b481de9c
ZY		 978 compare_ether_addr(priv->staging_rxon.bssid_addr,
979 priv->active_rxon.bssid_addr) ||
980 compare_ether_addr(priv->staging_rxon.node_addr,
981 priv->active_rxon.node_addr) ||
982 compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
983 priv->active_rxon.wlap_bssid_addr) ||
984 (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
985 (priv->staging_rxon.channel != priv->active_rxon.channel) ||
986 (priv->staging_rxon.air_propagation !=
987 priv->active_rxon.air_propagation) ||
988 (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
989 return 1;
990
991 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
992 * be updated with the RXON_ASSOC command -- however only some
993 * flag transitions are allowed using RXON_ASSOC */
994
995 /* Check if we are not switching bands */
996 if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
997 (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
998 return 1;
999
1000 /* Check if we are switching association toggle */
1001 if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
1002 (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
1003 return 1;
1004
1005 return 0;
1006}
1007
bb8c093b 1008static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
b481de9c
ZY		 1009{
1010 int rc = 0;
bb8c093b
CH		 1011 struct iwl3945_rx_packet *res = NULL;
1012 struct iwl3945_rxon_assoc_cmd rxon_assoc;
1013 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 1014 .id = REPLY_RXON_ASSOC,
1015 .len = sizeof(rxon_assoc),
1016 .meta.flags = CMD_WANT_SKB,
1017 .data = &rxon_assoc,
1018 };
bb8c093b
CH		 1019 const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
1020 const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
b481de9c
ZY		 1021
1022 if ((rxon1->flags == rxon2->flags) &&
1023 (rxon1->filter_flags == rxon2->filter_flags) &&
1024 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1025 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1026 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
1027 return 0;
1028 }
1029
1030 rxon_assoc.flags = priv->staging_rxon.flags;
1031 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1032 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1033 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1034 rxon_assoc.reserved = 0;
1035
bb8c093b 1036 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 1037 if (rc)
1038 return rc;
1039
bb8c093b 1040 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1041 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1042 IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
1043 rc = -EIO;
1044 }
1045
1046 priv->alloc_rxb_skb--;
1047 dev_kfree_skb_any(cmd.meta.u.skb);
1048
1049 return rc;
1050}
1051
1052/**
bb8c093b 1053 * iwl3945_commit_rxon - commit staging_rxon to hardware
b481de9c 1054 *
01ebd063 1055 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
ZY		 1056 * the active_rxon structure is updated with the new data. This
1057 * function correctly transitions out of the RXON_ASSOC_MSK state if
1058 * a HW tune is required based on the RXON structure changes.
1059 */
bb8c093b 1060static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
b481de9c
ZY		 1061{
1062 /* cast away the const for active_rxon in this function */
bb8c093b 1063 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
b481de9c
ZY		 1064 int rc = 0;
1065
bb8c093b 1066 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 1067 return -1;
1068
1069 /* always get timestamp with Rx frame */
1070 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
1071
1072 /* select antenna */
1073 priv->staging_rxon.flags &=
1074 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1075 priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
1076
bb8c093b 1077 rc = iwl3945_check_rxon_cmd(&priv->staging_rxon);
b481de9c
ZY		 1078 if (rc) {
1079 IWL_ERROR("Invalid RXON configuration. Not committing.\n");
1080 return -EINVAL;
1081 }
1082
1083 /* If we don't need to send a full RXON, we can use
bb8c093b 1084 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 1085 * and other flags for the current radio configuration. */
bb8c093b
CH		 1086 if (!iwl3945_full_rxon_required(priv)) {
1087 rc = iwl3945_send_rxon_assoc(priv);
b481de9c
ZY		 1088 if (rc) {
1089 IWL_ERROR("Error setting RXON_ASSOC "
1090 "configuration (%d).\n", rc);
1091 return rc;
1092 }
1093
1094 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1095
1096 return 0;
1097 }
1098
1099 /* If we are currently associated and the new config requires
1100 * an RXON_ASSOC and the new config wants the associated mask enabled,
1101 * we must clear the associated from the active configuration
1102 * before we apply the new config */
bb8c093b 1103 if (iwl3945_is_associated(priv) &&
b481de9c
ZY		 1104 (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
1105 IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
1106 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1107
bb8c093b
CH		 1108 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
1109 sizeof(struct iwl3945_rxon_cmd),
b481de9c
ZY		 1110 &priv->active_rxon);
1111
1112 /* If the mask clearing failed then we set
1113 * active_rxon back to what it was previously */
1114 if (rc) {
1115 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1116 IWL_ERROR("Error clearing ASSOC_MSK on current "
1117 "configuration (%d).\n", rc);
1118 return rc;
1119 }
b481de9c
ZY		 1120 }
1121
1122 IWL_DEBUG_INFO("Sending RXON\n"
1123 "* with%s RXON_FILTER_ASSOC_MSK\n"
1124 "* channel = %d\n"
e174961c 1125 "* bssid = %pM\n",
b481de9c
ZY		 1126 ((priv->staging_rxon.filter_flags &
1127 RXON_FILTER_ASSOC_MSK) ? "" : "out"),
1128 le16_to_cpu(priv->staging_rxon.channel),
e174961c 1129 priv->staging_rxon.bssid_addr);
b481de9c
ZY		 1130
1131 /* Apply the new configuration */
bb8c093b
CH		 1132 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
1133 sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
b481de9c
ZY		 1134 if (rc) {
1135 IWL_ERROR("Error setting new configuration (%d).\n", rc);
1136 return rc;
1137 }
1138
1139 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1140
bb8c093b 1141 iwl3945_clear_stations_table(priv);
556f8db7 1142
b481de9c
ZY		 1143 /* If we issue a new RXON command which required a tune then we must
1144 * send a new TXPOWER command or we won't be able to Tx any frames */
bb8c093b 1145 rc = iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 1146 if (rc) {
1147 IWL_ERROR("Error setting Tx power (%d).\n", rc);
1148 return rc;
1149 }
1150
1151 /* Add the broadcast address so we can send broadcast frames */
bb8c093b 1152 if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
b481de9c
ZY		 1153 IWL_INVALID_STATION) {
1154 IWL_ERROR("Error adding BROADCAST address for transmit.\n");
1155 return -EIO;
1156 }
1157
1158 /* If we have set the ASSOC_MSK and we are in BSS mode then
1159 * add the IWL_AP_ID to the station rate table */
bb8c093b 1160 if (iwl3945_is_associated(priv) &&
05c914fe 1161 (priv->iw_mode == NL80211_IFTYPE_STATION))
bb8c093b 1162 if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
b481de9c
ZY		 1163 == IWL_INVALID_STATION) {
1164 IWL_ERROR("Error adding AP address for transmit.\n");
1165 return -EIO;
1166 }
1167
8318d78a 1168 /* Init the hardware's rate fallback order based on the band */
b481de9c
ZY		 1169 rc = iwl3945_init_hw_rate_table(priv);
1170 if (rc) {
1171 IWL_ERROR("Error setting HW rate table: %02X\n", rc);
1172 return -EIO;
1173 }
1174
1175 return 0;
1176}
1177
bb8c093b 1178static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
b481de9c 1179{
bb8c093b 1180 struct iwl3945_bt_cmd bt_cmd = {
b481de9c
ZY		 1181 .flags = 3,
1182 .lead_time = 0xAA,
1183 .max_kill = 1,
1184 .kill_ack_mask = 0,
1185 .kill_cts_mask = 0,
1186 };
1187
bb8c093b
CH		 1188 return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1189 sizeof(struct iwl3945_bt_cmd), &bt_cmd);
b481de9c
ZY		 1190}
1191
bb8c093b 1192static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
b481de9c
ZY		 1193{
1194 int rc = 0;
bb8c093b
CH		 1195 struct iwl3945_rx_packet *res;
1196 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 1197 .id = REPLY_SCAN_ABORT_CMD,
1198 .meta.flags = CMD_WANT_SKB,
1199 };
1200
1201 /* If there isn't a scan actively going on in the hardware
1202 * then we are in between scan bands and not actually
1203 * actively scanning, so don't send the abort command */
1204 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
1205 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1206 return 0;
1207 }
1208
bb8c093b 1209 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 1210 if (rc) {
1211 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1212 return rc;
1213 }
1214
bb8c093b 1215 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1216 if (res->u.status != CAN_ABORT_STATUS) {
1217 /* The scan abort will return 1 for success or
1218 * 2 for "failure". A failure condition can be
1219 * due to simply not being in an active scan which
1220 * can occur if we send the scan abort before we
1221 * the microcode has notified us that a scan is
1222 * completed. */
1223 IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
1224 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1225 clear_bit(STATUS_SCAN_HW, &priv->status);
1226 }
1227
1228 dev_kfree_skb_any(cmd.meta.u.skb);
1229
1230 return rc;
1231}
1232
bb8c093b
CH		 1233static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
1234 struct iwl3945_cmd *cmd,
b481de9c
ZY		 1235 struct sk_buff *skb)
1236{
1237 return 1;
1238}
1239
1240/*
1241 * CARD_STATE_CMD
1242 *
9fbab516 1243 * Use: Sets the device's internal card state to enable, disable, or halt
b481de9c
ZY		 1244 *
1245 * When in the 'enable' state the card operates as normal.
1246 * When in the 'disable' state, the card enters into a low power mode.
1247 * When in the 'halt' state, the card is shut down and must be fully
1248 * restarted to come back on.
1249 */
bb8c093b 1250static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
b481de9c 1251{
bb8c093b 1252 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 1253 .id = REPLY_CARD_STATE_CMD,
1254 .len = sizeof(u32),
1255 .data = &flags,
1256 .meta.flags = meta_flag,
1257 };
1258
1259 if (meta_flag & CMD_ASYNC)
bb8c093b 1260 cmd.meta.u.callback = iwl3945_card_state_sync_callback;
b481de9c 1261
bb8c093b 1262 return iwl3945_send_cmd(priv, &cmd);
b481de9c
ZY		 1263}
1264
bb8c093b
CH		 1265static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
1266 struct iwl3945_cmd *cmd, struct sk_buff *skb)
b481de9c 1267{
bb8c093b 1268 struct iwl3945_rx_packet *res = NULL;
b481de9c
ZY		 1269
1270 if (!skb) {
1271 IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
1272 return 1;
1273 }
1274
bb8c093b 1275 res = (struct iwl3945_rx_packet *)skb->data;
b481de9c
ZY		 1276 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1277 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1278 res->hdr.flags);
1279 return 1;
1280 }
1281
1282 switch (res->u.add_sta.status) {
1283 case ADD_STA_SUCCESS_MSK:
1284 break;
1285 default:
1286 break;
1287 }
1288
1289 /* We didn't cache the SKB; let the caller free it */
1290 return 1;
1291}
1292
bb8c093b
CH		 1293int iwl3945_send_add_station(struct iwl3945_priv *priv,
1294 struct iwl3945_addsta_cmd *sta, u8 flags)
b481de9c 1295{
bb8c093b 1296 struct iwl3945_rx_packet *res = NULL;
b481de9c 1297 int rc = 0;
bb8c093b 1298 struct iwl3945_host_cmd cmd = {
b481de9c 1299 .id = REPLY_ADD_STA,
bb8c093b 1300 .len = sizeof(struct iwl3945_addsta_cmd),
b481de9c
ZY		 1301 .meta.flags = flags,
1302 .data = sta,
1303 };
1304
1305 if (flags & CMD_ASYNC)
bb8c093b 1306 cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
b481de9c
ZY		 1307 else
1308 cmd.meta.flags |= CMD_WANT_SKB;
1309
bb8c093b 1310 rc = iwl3945_send_cmd(priv, &cmd);
b481de9c
ZY		 1311
1312 if (rc || (flags & CMD_ASYNC))
1313 return rc;
1314
bb8c093b 1315 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1316 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1317 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1318 res->hdr.flags);
1319 rc = -EIO;
1320 }
1321
1322 if (rc == 0) {
1323 switch (res->u.add_sta.status) {
1324 case ADD_STA_SUCCESS_MSK:
1325 IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
1326 break;
1327 default:
1328 rc = -EIO;
1329 IWL_WARNING("REPLY_ADD_STA failed\n");
1330 break;
1331 }
1332 }
1333
1334 priv->alloc_rxb_skb--;
1335 dev_kfree_skb_any(cmd.meta.u.skb);
1336
1337 return rc;
1338}
1339
bb8c093b 1340static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
b481de9c
ZY		 1341 struct ieee80211_key_conf *keyconf,
1342 u8 sta_id)
1343{
1344 unsigned long flags;
1345 __le16 key_flags = 0;
1346
1347 switch (keyconf->alg) {
1348 case ALG_CCMP:
1349 key_flags |= STA_KEY_FLG_CCMP;
1350 key_flags |= cpu_to_le16(
1351 keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
1352 key_flags &= ~STA_KEY_FLG_INVALID;
1353 break;
1354 case ALG_TKIP:
1355 case ALG_WEP:
b481de9c
ZY		 1356 default:
1357 return -EINVAL;
1358 }
1359 spin_lock_irqsave(&priv->sta_lock, flags);
1360 priv->stations[sta_id].keyinfo.alg = keyconf->alg;
1361 priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
1362 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
1363 keyconf->keylen);
1364
1365 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
1366 keyconf->keylen);
1367 priv->stations[sta_id].sta.key.key_flags = key_flags;
1368 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1369 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1370
1371 spin_unlock_irqrestore(&priv->sta_lock, flags);
1372
1373 IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
bb8c093b 1374 iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY		 1375 return 0;
1376}
1377
bb8c093b 1378static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
b481de9c
ZY		 1379{
1380 unsigned long flags;
1381
1382 spin_lock_irqsave(&priv->sta_lock, flags);
bb8c093b
CH		 1383 memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
1384 memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl3945_keyinfo));
b481de9c
ZY		 1385 priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
1386 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1387 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1388 spin_unlock_irqrestore(&priv->sta_lock, flags);
1389
1390 IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
bb8c093b 1391 iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY		 1392 return 0;
1393}
1394
bb8c093b 1395static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
b481de9c
ZY		 1396{
1397 struct list_head *element;
1398
1399 IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
1400 priv->frames_count);
1401
1402 while (!list_empty(&priv->free_frames)) {
1403 element = priv->free_frames.next;
1404 list_del(element);
bb8c093b 1405 kfree(list_entry(element, struct iwl3945_frame, list));
b481de9c
ZY		 1406 priv->frames_count--;
1407 }
1408
1409 if (priv->frames_count) {
1410 IWL_WARNING("%d frames still in use. Did we lose one?\n",
1411 priv->frames_count);
1412 priv->frames_count = 0;
1413 }
1414}
1415
bb8c093b 1416static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
b481de9c 1417{
bb8c093b 1418 struct iwl3945_frame *frame;
b481de9c
ZY		 1419 struct list_head *element;
1420 if (list_empty(&priv->free_frames)) {
1421 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
1422 if (!frame) {
1423 IWL_ERROR("Could not allocate frame!\n");
1424 return NULL;
1425 }
1426
1427 priv->frames_count++;
1428 return frame;
1429 }
1430
1431 element = priv->free_frames.next;
1432 list_del(element);
bb8c093b 1433 return list_entry(element, struct iwl3945_frame, list);
b481de9c
ZY		 1434}
1435
bb8c093b 1436static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
b481de9c
ZY		 1437{
1438 memset(frame, 0, sizeof(*frame));
1439 list_add(&frame->list, &priv->free_frames);
1440}
1441
bb8c093b 1442unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
b481de9c
ZY		 1443 struct ieee80211_hdr *hdr,
1444 const u8 *dest, int left)
1445{
1446
bb8c093b 1447 if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB		 1448 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
1449 (priv->iw_mode != NL80211_IFTYPE_AP)))
b481de9c
ZY		 1450 return 0;
1451
1452 if (priv->ibss_beacon->len > left)
1453 return 0;
1454
1455 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
1456
1457 return priv->ibss_beacon->len;
1458}
1459
bb8c093b 1460static u8 iwl3945_rate_get_lowest_plcp(int rate_mask)
b481de9c
ZY		 1461{
1462 u8 i;
1463
1464 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
bb8c093b 1465 i = iwl3945_rates[i].next_ieee) {
b481de9c 1466 if (rate_mask & (1 << i))
bb8c093b 1467 return iwl3945_rates[i].plcp;
b481de9c
ZY		 1468 }
1469
1470 return IWL_RATE_INVALID;
1471}
1472
bb8c093b 1473static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
b481de9c 1474{
bb8c093b 1475 struct iwl3945_frame *frame;
b481de9c
ZY		 1476 unsigned int frame_size;
1477 int rc;
1478 u8 rate;
1479
bb8c093b 1480 frame = iwl3945_get_free_frame(priv);
b481de9c
ZY		 1481
1482 if (!frame) {
1483 IWL_ERROR("Could not obtain free frame buffer for beacon "
1484 "command.\n");
1485 return -ENOMEM;
1486 }
1487
1488 if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) {
bb8c093b 1489 rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic &
b481de9c
ZY		 1490 0xFF0);
1491 if (rate == IWL_INVALID_RATE)
1492 rate = IWL_RATE_6M_PLCP;
1493 } else {
bb8c093b 1494 rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic & 0xF);
b481de9c
ZY		 1495 if (rate == IWL_INVALID_RATE)
1496 rate = IWL_RATE_1M_PLCP;
1497 }
1498
bb8c093b 1499 frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 1500
bb8c093b 1501 rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY		 1502 &frame->u.cmd[0]);
1503
bb8c093b 1504 iwl3945_free_frame(priv, frame);
b481de9c
ZY		 1505
1506 return rc;
1507}
1508
1509/******************************************************************************
1510 *
1511 * EEPROM related functions
1512 *
1513 ******************************************************************************/
1514
bb8c093b 1515static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
b481de9c
ZY		 1516{
1517 memcpy(mac, priv->eeprom.mac_address, 6);
1518}
1519
74a3a250
RC		 1520/*
1521 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
1522 * embedded controller) as EEPROM reader; each read is a series of pulses
1523 * to/from the EEPROM chip, not a single event, so even reads could conflict
1524 * if they weren't arbitrated by some ownership mechanism. Here, the driver
1525 * simply claims ownership, which should be safe when this function is called
1526 * (i.e. before loading uCode!).
1527 */
1528static inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv)
1529{
1530 _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
1531 return 0;
1532}
1533
b481de9c 1534/**
bb8c093b 1535 * iwl3945_eeprom_init - read EEPROM contents
b481de9c 1536 *
6440adb5 1537 * Load the EEPROM contents from adapter into priv->eeprom
b481de9c
ZY		 1538 *
1539 * NOTE: This routine uses the non-debug IO access functions.
1540 */
bb8c093b 1541int iwl3945_eeprom_init(struct iwl3945_priv *priv)
b481de9c 1542{
58ff6d4d 1543 u16 *e = (u16 *)&priv->eeprom;
bb8c093b 1544 u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
b481de9c
ZY		 1545 u32 r;
1546 int sz = sizeof(priv->eeprom);
1547 int rc;
1548 int i;
1549 u16 addr;
1550
1551 /* The EEPROM structure has several padding buffers within it
1552 * and when adding new EEPROM maps is subject to programmer errors
1553 * which may be very difficult to identify without explicitly
1554 * checking the resulting size of the eeprom map. */
1555 BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
1556
1557 if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
6f147926 1558 IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x\n", gp);
b481de9c
ZY		 1559 return -ENOENT;
1560 }
1561
6440adb5 1562 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
bb8c093b 1563 rc = iwl3945_eeprom_acquire_semaphore(priv);
b481de9c 1564 if (rc < 0) {
91e17473 1565 IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
b481de9c
ZY		 1566 return -ENOENT;
1567 }
1568
1569 /* eeprom is an array of 16bit values */
1570 for (addr = 0; addr < sz; addr += sizeof(u16)) {
bb8c093b
CH		 1571 _iwl3945_write32(priv, CSR_EEPROM_REG, addr << 1);
1572 _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
b481de9c
ZY		 1573
1574 for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
1575 i += IWL_EEPROM_ACCESS_DELAY) {
bb8c093b 1576 r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
b481de9c
ZY		 1577 if (r & CSR_EEPROM_REG_READ_VALID_MSK)
1578 break;
1579 udelay(IWL_EEPROM_ACCESS_DELAY);
1580 }
1581
1582 if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) {
6f147926 1583 IWL_ERROR("Time out reading EEPROM[%d]\n", addr);
b481de9c
ZY		 1584 return -ETIMEDOUT;
1585 }
58ff6d4d 1586 e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
b481de9c
ZY		 1587 }
1588
1589 return 0;
1590}
1591
bb8c093b 1592static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
b481de9c
ZY		 1593{
1594 if (priv->hw_setting.shared_virt)
1595 pci_free_consistent(priv->pci_dev,
bb8c093b 1596 sizeof(struct iwl3945_shared),
b481de9c
ZY		 1597 priv->hw_setting.shared_virt,
1598 priv->hw_setting.shared_phys);
1599}
1600
1601/**
bb8c093b 1602 * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
b481de9c
ZY		 1603 *
1604 * return : set the bit for each supported rate insert in ie
1605 */
bb8c093b 1606static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
c7c46676 1607 u16 basic_rate, int *left)
b481de9c
ZY		 1608{
1609 u16 ret_rates = 0, bit;
1610 int i;
c7c46676
TW		 1611 u8 *cnt = ie;
1612 u8 *rates = ie + 1;
b481de9c
ZY		 1613
1614 for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
1615 if (bit & supported_rate) {
1616 ret_rates |= bit;
bb8c093b 1617 rates[*cnt] = iwl3945_rates[i].ieee |
c7c46676
TW		 1618 ((bit & basic_rate) ? 0x80 : 0x00);
1619 (*cnt)++;
1620 (*left)--;
1621 if ((*left <= 0) ||
1622 (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
b481de9c
ZY		 1623 break;
1624 }
1625 }
1626
1627 return ret_rates;
1628}
1629
1630/**
bb8c093b 1631 * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
b481de9c 1632 */
bb8c093b 1633static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
b481de9c
ZY		 1634 struct ieee80211_mgmt *frame,
1635 int left, int is_direct)
1636{
1637 int len = 0;
1638 u8 *pos = NULL;
c7c46676 1639 u16 active_rates, ret_rates, cck_rates;
b481de9c
ZY		 1640
1641 /* Make sure there is enough space for the probe request,
1642 * two mandatory IEs and the data */
1643 left -= 24;
1644 if (left < 0)
1645 return 0;
1646 len += 24;
1647
1648 frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
bb8c093b 1649 memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
b481de9c 1650 memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
bb8c093b 1651 memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
b481de9c
ZY		 1652 frame->seq_ctrl = 0;
1653
1654 /* fill in our indirect SSID IE */
1655 /* ...next IE... */
1656
1657 left -= 2;
1658 if (left < 0)
1659 return 0;
1660 len += 2;
1661 pos = &(frame->u.probe_req.variable[0]);
1662 *pos++ = WLAN_EID_SSID;
1663 *pos++ = 0;
1664
1665 /* fill in our direct SSID IE... */
1666 if (is_direct) {
1667 /* ...next IE... */
1668 left -= 2 + priv->essid_len;
1669 if (left < 0)
1670 return 0;
1671 /* ... fill it in... */
1672 *pos++ = WLAN_EID_SSID;
1673 *pos++ = priv->essid_len;
1674 memcpy(pos, priv->essid, priv->essid_len);
1675 pos += priv->essid_len;
1676 len += 2 + priv->essid_len;
1677 }
1678
1679 /* fill in supported rate */
1680 /* ...next IE... */
1681 left -= 2;
1682 if (left < 0)
1683 return 0;
c7c46676 1684
b481de9c
ZY		 1685 /* ... fill it in... */
1686 *pos++ = WLAN_EID_SUPP_RATES;
1687 *pos = 0;
c7c46676
TW		 1688
1689 priv->active_rate = priv->rates_mask;
1690 active_rates = priv->active_rate;
b481de9c
ZY		 1691 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1692
c7c46676 1693 cck_rates = IWL_CCK_RATES_MASK & active_rates;
bb8c093b 1694 ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
c7c46676
TW		 1695 priv->active_rate_basic, &left);
1696 active_rates &= ~ret_rates;
1697
bb8c093b 1698 ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676
TW		 1699 priv->active_rate_basic, &left);
1700 active_rates &= ~ret_rates;
1701
b481de9c
ZY		 1702 len += 2 + *pos;
1703 pos += (*pos) + 1;
c7c46676 1704 if (active_rates == 0)
b481de9c
ZY		 1705 goto fill_end;
1706
1707 /* fill in supported extended rate */
1708 /* ...next IE... */
1709 left -= 2;
1710 if (left < 0)
1711 return 0;
1712 /* ... fill it in... */
1713 *pos++ = WLAN_EID_EXT_SUPP_RATES;
1714 *pos = 0;
bb8c093b 1715 iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676 1716 priv->active_rate_basic, &left);
b481de9c
ZY		 1717 if (*pos > 0)
1718 len += 2 + *pos;
1719
1720 fill_end:
1721 return (u16)len;
1722}
1723
1724/*
1725 * QoS support
1726*/
bb8c093b
CH		 1727static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
1728 struct iwl3945_qosparam_cmd *qos)
b481de9c
ZY		 1729{
1730
bb8c093b
CH		 1731 return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
1732 sizeof(struct iwl3945_qosparam_cmd), qos);
b481de9c
ZY		 1733}
1734
bb8c093b 1735static void iwl3945_reset_qos(struct iwl3945_priv *priv)
b481de9c
ZY		 1736{
1737 u16 cw_min = 15;
1738 u16 cw_max = 1023;
1739 u8 aifs = 2;
1740 u8 is_legacy = 0;
1741 unsigned long flags;
1742 int i;
1743
1744 spin_lock_irqsave(&priv->lock, flags);
1745 priv->qos_data.qos_active = 0;
1746
05c914fe 1747 if (priv->iw_mode == NL80211_IFTYPE_ADHOC) {
b481de9c
ZY		 1748 if (priv->qos_data.qos_enable)
1749 priv->qos_data.qos_active = 1;
1750 if (!(priv->active_rate & 0xfff0)) {
1751 cw_min = 31;
1752 is_legacy = 1;
1753 }
05c914fe 1754 } else if (priv->iw_mode == NL80211_IFTYPE_AP) {
b481de9c
ZY		 1755 if (priv->qos_data.qos_enable)
1756 priv->qos_data.qos_active = 1;
1757 } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
1758 cw_min = 31;
1759 is_legacy = 1;
1760 }
1761
1762 if (priv->qos_data.qos_active)
1763 aifs = 3;
1764
1765 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
1766 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
1767 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
1768 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
1769 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
1770
1771 if (priv->qos_data.qos_active) {
1772 i = 1;
1773 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
1774 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
1775 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
1776 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
1777 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1778
1779 i = 2;
1780 priv->qos_data.def_qos_parm.ac[i].cw_min =
1781 cpu_to_le16((cw_min + 1) / 2 - 1);
1782 priv->qos_data.def_qos_parm.ac[i].cw_max =
1783 cpu_to_le16(cw_max);
1784 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1785 if (is_legacy)
1786 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1787 cpu_to_le16(6016);
1788 else
1789 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1790 cpu_to_le16(3008);
1791 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1792
1793 i = 3;
1794 priv->qos_data.def_qos_parm.ac[i].cw_min =
1795 cpu_to_le16((cw_min + 1) / 4 - 1);
1796 priv->qos_data.def_qos_parm.ac[i].cw_max =
1797 cpu_to_le16((cw_max + 1) / 2 - 1);
1798 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1799 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1800 if (is_legacy)
1801 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1802 cpu_to_le16(3264);
1803 else
1804 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1805 cpu_to_le16(1504);
1806 } else {
1807 for (i = 1; i < 4; i++) {
1808 priv->qos_data.def_qos_parm.ac[i].cw_min =
1809 cpu_to_le16(cw_min);
1810 priv->qos_data.def_qos_parm.ac[i].cw_max =
1811 cpu_to_le16(cw_max);
1812 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
1813 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
1814 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1815 }
1816 }
1817 IWL_DEBUG_QOS("set QoS to default \n");
1818
1819 spin_unlock_irqrestore(&priv->lock, flags);
1820}
1821
bb8c093b 1822static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
b481de9c
ZY		 1823{
1824 unsigned long flags;
1825
b481de9c
ZY		 1826 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1827 return;
1828
1829 if (!priv->qos_data.qos_enable)
1830 return;
1831
1832 spin_lock_irqsave(&priv->lock, flags);
1833 priv->qos_data.def_qos_parm.qos_flags = 0;
1834
1835 if (priv->qos_data.qos_cap.q_AP.queue_request &&
1836 !priv->qos_data.qos_cap.q_AP.txop_request)
1837 priv->qos_data.def_qos_parm.qos_flags |=
1838 QOS_PARAM_FLG_TXOP_TYPE_MSK;
1839
1840 if (priv->qos_data.qos_active)
1841 priv->qos_data.def_qos_parm.qos_flags |=
1842 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
1843
1844 spin_unlock_irqrestore(&priv->lock, flags);
1845
bb8c093b 1846 if (force || iwl3945_is_associated(priv)) {
b481de9c
ZY		 1847 IWL_DEBUG_QOS("send QoS cmd with Qos active %d \n",
1848 priv->qos_data.qos_active);
1849
bb8c093b 1850 iwl3945_send_qos_params_command(priv,
b481de9c
ZY		 1851 &(priv->qos_data.def_qos_parm));
1852 }
1853}
1854
b481de9c
ZY		 1855/*
1856 * Power management (not Tx power!) functions
1857 */
1858#define MSEC_TO_USEC 1024
1859
1860#define NOSLP __constant_cpu_to_le32(0)
1861#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK
1862#define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
1863#define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
1864 __constant_cpu_to_le32(X1), \
1865 __constant_cpu_to_le32(X2), \
1866 __constant_cpu_to_le32(X3), \
1867 __constant_cpu_to_le32(X4)}
1868
1869
1870/* default power management (not Tx power) table values */
1871/* for tim 0-10 */
bb8c093b 1872static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = {
b481de9c
ZY		 1873 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1874 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
1875 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
1876 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
1877 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
1878 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
1879};
1880
1881/* for tim > 10 */
bb8c093b 1882static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = {
b481de9c
ZY		 1883 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1884 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
1885 SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
1886 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
1887 SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
1888 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
1889 SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
1890 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
1891 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
1892 SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
1893};
1894
bb8c093b 1895int iwl3945_power_init_handle(struct iwl3945_priv *priv)
b481de9c
ZY		 1896{
1897 int rc = 0, i;
bb8c093b
CH		 1898 struct iwl3945_power_mgr *pow_data;
1899 int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC;
b481de9c
ZY		 1900 u16 pci_pm;
1901
1902 IWL_DEBUG_POWER("Initialize power \n");
1903
1904 pow_data = &(priv->power_data);
1905
1906 memset(pow_data, 0, sizeof(*pow_data));
1907
1908 pow_data->active_index = IWL_POWER_RANGE_0;
1909 pow_data->dtim_val = 0xffff;
1910
1911 memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
1912 memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
1913
1914 rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
1915 if (rc != 0)
1916 return 0;
1917 else {
bb8c093b 1918 struct iwl3945_powertable_cmd *cmd;
b481de9c
ZY		 1919
1920 IWL_DEBUG_POWER("adjust power command flags\n");
1921
1922 for (i = 0; i < IWL_POWER_AC; i++) {
1923 cmd = &pow_data->pwr_range_0[i].cmd;
1924
1925 if (pci_pm & 0x1)
1926 cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
1927 else
1928 cmd->flags |= IWL_POWER_PCI_PM_MSK;
1929 }
1930 }
1931 return rc;
1932}
1933
bb8c093b
CH		 1934static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
1935 struct iwl3945_powertable_cmd *cmd, u32 mode)
b481de9c
ZY		 1936{
1937 int rc = 0, i;
1938 u8 skip;
1939 u32 max_sleep = 0;
bb8c093b 1940 struct iwl3945_power_vec_entry *range;
b481de9c 1941 u8 period = 0;
bb8c093b 1942 struct iwl3945_power_mgr *pow_data;
b481de9c
ZY		 1943
1944 if (mode > IWL_POWER_INDEX_5) {
1945 IWL_DEBUG_POWER("Error invalid power mode \n");
1946 return -1;
1947 }
1948 pow_data = &(priv->power_data);
1949
1950 if (pow_data->active_index == IWL_POWER_RANGE_0)
1951 range = &pow_data->pwr_range_0[0];
1952 else
1953 range = &pow_data->pwr_range_1[1];
1954
bb8c093b 1955 memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
b481de9c
ZY		 1956
1957#ifdef IWL_MAC80211_DISABLE
1958 if (priv->assoc_network != NULL) {
1959 unsigned long flags;
1960
1961 period = priv->assoc_network->tim.tim_period;
1962 }
1963#endif /*IWL_MAC80211_DISABLE */
1964 skip = range[mode].no_dtim;
1965
1966 if (period == 0) {
1967 period = 1;
1968 skip = 0;
1969 }
1970
1971 if (skip == 0) {
1972 max_sleep = period;
1973 cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
1974 } else {
1975 __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
1976 max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
1977 cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
1978 }
1979
1980 for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
1981 if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
1982 cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
1983 }
1984
1985 IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
1986 IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
1987 IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
1988 IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
1989 le32_to_cpu(cmd->sleep_interval[0]),
1990 le32_to_cpu(cmd->sleep_interval[1]),
1991 le32_to_cpu(cmd->sleep_interval[2]),
1992 le32_to_cpu(cmd->sleep_interval[3]),
1993 le32_to_cpu(cmd->sleep_interval[4]));
1994
1995 return rc;
1996}
1997
bb8c093b 1998static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
b481de9c 1999{
9a62f73b 2000 u32 uninitialized_var(final_mode);
b481de9c 2001 int rc;
bb8c093b 2002 struct iwl3945_powertable_cmd cmd;
b481de9c
ZY		 2003
2004 /* If on battery, set to 3,
01ebd063 2005 * if plugged into AC power, set to CAM ("continuously aware mode"),
b481de9c
ZY		 2006 * else user level */
2007 switch (mode) {
2008 case IWL_POWER_BATTERY:
2009 final_mode = IWL_POWER_INDEX_3;
2010 break;
2011 case IWL_POWER_AC:
2012 final_mode = IWL_POWER_MODE_CAM;
2013 break;
2014 default:
2015 final_mode = mode;
2016 break;
2017 }
2018
bb8c093b 2019 iwl3945_update_power_cmd(priv, &cmd, final_mode);
b481de9c 2020
bb8c093b 2021 rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
b481de9c
ZY		 2022
2023 if (final_mode == IWL_POWER_MODE_CAM)
2024 clear_bit(STATUS_POWER_PMI, &priv->status);
2025 else
2026 set_bit(STATUS_POWER_PMI, &priv->status);
2027
2028 return rc;
2029}
2030
b481de9c 2031/**
bb8c093b 2032 * iwl3945_scan_cancel - Cancel any currently executing HW scan
b481de9c
ZY		 2033 *
2034 * NOTE: priv->mutex is not required before calling this function
2035 */
bb8c093b 2036static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
b481de9c
ZY		 2037{
2038 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
2039 clear_bit(STATUS_SCANNING, &priv->status);
2040 return 0;
2041 }
2042
2043 if (test_bit(STATUS_SCANNING, &priv->status)) {
2044 if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2045 IWL_DEBUG_SCAN("Queuing scan abort.\n");
2046 set_bit(STATUS_SCAN_ABORTING, &priv->status);
2047 queue_work(priv->workqueue, &priv->abort_scan);
2048
2049 } else
2050 IWL_DEBUG_SCAN("Scan abort already in progress.\n");
2051
2052 return test_bit(STATUS_SCANNING, &priv->status);
2053 }
2054
2055 return 0;
2056}
2057
2058/**
bb8c093b 2059 * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
b481de9c
ZY		 2060 * @ms: amount of time to wait (in milliseconds) for scan to abort
2061 *
2062 * NOTE: priv->mutex must be held before calling this function
2063 */
bb8c093b 2064static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
b481de9c
ZY		 2065{
2066 unsigned long now = jiffies;
2067 int ret;
2068
bb8c093b 2069 ret = iwl3945_scan_cancel(priv);
b481de9c
ZY		 2070 if (ret && ms) {
2071 mutex_unlock(&priv->mutex);
2072 while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
2073 test_bit(STATUS_SCANNING, &priv->status))
2074 msleep(1);
2075 mutex_lock(&priv->mutex);
2076
2077 return test_bit(STATUS_SCANNING, &priv->status);
2078 }
2079
2080 return ret;
2081}
2082
b481de9c
ZY		 2083#define MAX_UCODE_BEACON_INTERVAL 1024
2084#define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
2085
bb8c093b 2086static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
b481de9c
ZY		 2087{
2088 u16 new_val = 0;
2089 u16 beacon_factor = 0;
2090
2091 beacon_factor =
2092 (beacon_val + MAX_UCODE_BEACON_INTERVAL)
2093 / MAX_UCODE_BEACON_INTERVAL;
2094 new_val = beacon_val / beacon_factor;
2095
2096 return cpu_to_le16(new_val);
2097}
2098
bb8c093b 2099static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
b481de9c
ZY		 2100{
2101 u64 interval_tm_unit;
2102 u64 tsf, result;
2103 unsigned long flags;
2104 struct ieee80211_conf *conf = NULL;
2105 u16 beacon_int = 0;
2106
2107 conf = ieee80211_get_hw_conf(priv->hw);
2108
2109 spin_lock_irqsave(&priv->lock, flags);
2110 priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
2111 priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
2112
2113 priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
2114
2115 tsf = priv->timestamp1;
2116 tsf = ((tsf << 32) | priv->timestamp0);
2117
2118 beacon_int = priv->beacon_int;
2119 spin_unlock_irqrestore(&priv->lock, flags);
2120
05c914fe 2121 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
b481de9c
ZY		 2122 if (beacon_int == 0) {
2123 priv->rxon_timing.beacon_interval = cpu_to_le16(100);
2124 priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
2125 } else {
2126 priv->rxon_timing.beacon_interval =
2127 cpu_to_le16(beacon_int);
2128 priv->rxon_timing.beacon_interval =
bb8c093b 2129 iwl3945_adjust_beacon_interval(
b481de9c
ZY		 2130 le16_to_cpu(priv->rxon_timing.beacon_interval));
2131 }
2132
2133 priv->rxon_timing.atim_window = 0;
2134 } else {
2135 priv->rxon_timing.beacon_interval =
bb8c093b 2136 iwl3945_adjust_beacon_interval(conf->beacon_int);
b481de9c
ZY		 2137 /* TODO: we need to get atim_window from upper stack
2138 * for now we set to 0 */
2139 priv->rxon_timing.atim_window = 0;
2140 }
2141
2142 interval_tm_unit =
2143 (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
2144 result = do_div(tsf, interval_tm_unit);
2145 priv->rxon_timing.beacon_init_val =
2146 cpu_to_le32((u32) ((u64) interval_tm_unit - result));
2147
2148 IWL_DEBUG_ASSOC
2149 ("beacon interval %d beacon timer %d beacon tim %d\n",
2150 le16_to_cpu(priv->rxon_timing.beacon_interval),
2151 le32_to_cpu(priv->rxon_timing.beacon_init_val),
2152 le16_to_cpu(priv->rxon_timing.atim_window));
2153}
2154
bb8c093b 2155static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
b481de9c 2156{
05c914fe 2157 if (priv->iw_mode == NL80211_IFTYPE_AP) {
b481de9c
ZY		 2158 IWL_ERROR("APs don't scan.\n");
2159 return 0;
2160 }
2161
bb8c093b 2162 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 2163 IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
2164 return -EIO;
2165 }
2166
2167 if (test_bit(STATUS_SCANNING, &priv->status)) {
2168 IWL_DEBUG_SCAN("Scan already in progress.\n");
2169 return -EAGAIN;
2170 }
2171
2172 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2173 IWL_DEBUG_SCAN("Scan request while abort pending. "
2174 "Queuing.\n");
2175 return -EAGAIN;
2176 }
2177
2178 IWL_DEBUG_INFO("Starting scan...\n");
66b5004d
RR		 2179 if (priv->cfg->sku & IWL_SKU_G)
2180 priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ);
2181 if (priv->cfg->sku & IWL_SKU_A)
2182 priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ);
b481de9c
ZY		 2183 set_bit(STATUS_SCANNING, &priv->status);
2184 priv->scan_start = jiffies;
2185 priv->scan_pass_start = priv->scan_start;
2186
2187 queue_work(priv->workqueue, &priv->request_scan);
2188
2189 return 0;
2190}
2191
bb8c093b 2192static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
b481de9c 2193{
bb8c093b 2194 struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
b481de9c
ZY		 2195
2196 if (hw_decrypt)
2197 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
2198 else
2199 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
2200
2201 return 0;
2202}
2203
8318d78a
JB		 2204static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv,
2205 enum ieee80211_band band)
b481de9c 2206{
8318d78a 2207 if (band == IEEE80211_BAND_5GHZ) {
b481de9c
ZY		 2208 priv->staging_rxon.flags &=
2209 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
2210 | RXON_FLG_CCK_MSK);
2211 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2212 } else {
bb8c093b 2213 /* Copied from iwl3945_bg_post_associate() */
b481de9c
ZY		 2214 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2215 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2216 else
2217 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2218
05c914fe 2219 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY		 2220 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2221
2222 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
2223 priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
2224 priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
2225 }
2226}
2227
2228/*
01ebd063 2229 * initialize rxon structure with default values from eeprom
b481de9c 2230 */
bb8c093b 2231static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv)
b481de9c 2232{
bb8c093b 2233 const struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 2234
2235 memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
2236
2237 switch (priv->iw_mode) {
05c914fe 2238 case NL80211_IFTYPE_AP:
b481de9c
ZY		 2239 priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
2240 break;
2241
05c914fe 2242 case NL80211_IFTYPE_STATION:
b481de9c
ZY		 2243 priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
2244 priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
2245 break;
2246
05c914fe 2247 case NL80211_IFTYPE_ADHOC:
b481de9c
ZY		 2248 priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
2249 priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
2250 priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
2251 RXON_FILTER_ACCEPT_GRP_MSK;
2252 break;
2253
05c914fe 2254 case NL80211_IFTYPE_MONITOR:
b481de9c
ZY		 2255 priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
2256 priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
2257 RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
2258 break;
69dc5d9d
TW		 2259 default:
2260 IWL_ERROR("Unsupported interface type %d\n", priv->iw_mode);
2261 break;
b481de9c
ZY		 2262 }
2263
2264#if 0
2265 /* TODO: Figure out when short_preamble would be set and cache from
2266 * that */
2267 if (!hw_to_local(priv->hw)->short_preamble)
2268 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2269 else
2270 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2271#endif
2272
8318d78a 2273 ch_info = iwl3945_get_channel_info(priv, priv->band,
25b3f57c 2274 le16_to_cpu(priv->active_rxon.channel));
b481de9c
ZY		 2275
2276 if (!ch_info)
2277 ch_info = &priv->channel_info[0];
2278
2279 /*
2280 * in some case A channels are all non IBSS
2281 * in this case force B/G channel
2282 */
05c914fe 2283 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) &&
b481de9c
ZY		 2284 !(is_channel_ibss(ch_info)))
2285 ch_info = &priv->channel_info[0];
2286
2287 priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
2288 if (is_channel_a_band(ch_info))
8318d78a 2289 priv->band = IEEE80211_BAND_5GHZ;
b481de9c 2290 else
8318d78a 2291 priv->band = IEEE80211_BAND_2GHZ;
b481de9c 2292
8318d78a 2293 iwl3945_set_flags_for_phymode(priv, priv->band);
b481de9c
ZY		 2294
2295 priv->staging_rxon.ofdm_basic_rates =
2296 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2297 priv->staging_rxon.cck_basic_rates =
2298 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2299}
2300
bb8c093b 2301static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
b481de9c 2302{
05c914fe 2303 if (mode == NL80211_IFTYPE_ADHOC) {
bb8c093b 2304 const struct iwl3945_channel_info *ch_info;
b481de9c 2305
bb8c093b 2306 ch_info = iwl3945_get_channel_info(priv,
8318d78a 2307 priv->band,
b481de9c
ZY		 2308 le16_to_cpu(priv->staging_rxon.channel));
2309
2310 if (!ch_info || !is_channel_ibss(ch_info)) {
2311 IWL_ERROR("channel %d not IBSS channel\n",
2312 le16_to_cpu(priv->staging_rxon.channel));
2313 return -EINVAL;
2314 }
2315 }
2316
b481de9c
ZY		 2317 priv->iw_mode = mode;
2318
bb8c093b 2319 iwl3945_connection_init_rx_config(priv);
b481de9c
ZY		 2320 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2321
bb8c093b 2322 iwl3945_clear_stations_table(priv);
b481de9c 2323
fde3571f
MA		 2324 /* dont commit rxon if rf-kill is on*/
2325 if (!iwl3945_is_ready_rf(priv))
2326 return -EAGAIN;
2327
2328 cancel_delayed_work(&priv->scan_check);
2329 if (iwl3945_scan_cancel_timeout(priv, 100)) {
2330 IWL_WARNING("Aborted scan still in progress after 100ms\n");
2331 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
2332 return -EAGAIN;
2333 }
2334
bb8c093b 2335 iwl3945_commit_rxon(priv);
b481de9c
ZY		 2336
2337 return 0;
2338}
2339
bb8c093b 2340static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
e039fa4a 2341 struct ieee80211_tx_info *info,
bb8c093b 2342 struct iwl3945_cmd *cmd,
b481de9c
ZY		 2343 struct sk_buff *skb_frag,
2344 int last_frag)
2345{
1c014420 2346 struct iwl3945_hw_key *keyinfo =
e039fa4a 2347 &priv->stations[info->control.hw_key->hw_key_idx].keyinfo;
b481de9c
ZY		 2348
2349 switch (keyinfo->alg) {
2350 case ALG_CCMP:
2351 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
2352 memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
2353 IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
2354 break;
2355
2356 case ALG_TKIP:
2357#if 0
2358 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
2359
2360 if (last_frag)
2361 memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
2362 8);
2363 else
2364 memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
2365#endif
2366 break;
2367
2368 case ALG_WEP:
2369 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
e039fa4a 2370 (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
b481de9c
ZY		 2371
2372 if (keyinfo->keylen == 13)
2373 cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
2374
2375 memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
2376
2377 IWL_DEBUG_TX("Configuring packet for WEP encryption "
e039fa4a 2378 "with key %d\n", info->control.hw_key->hw_key_idx);
b481de9c
ZY		 2379 break;
2380
b481de9c
ZY		 2381 default:
2382 printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
2383 break;
2384 }
2385}
2386
2387/*
2388 * handle build REPLY_TX command notification.
2389 */
bb8c093b
CH		 2390static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
2391 struct iwl3945_cmd *cmd,
e039fa4a 2392 struct ieee80211_tx_info *info,
b481de9c
ZY		 2393 struct ieee80211_hdr *hdr,
2394 int is_unicast, u8 std_id)
2395{
fd7c8a40 2396 __le16 fc = hdr->frame_control;
b481de9c 2397 __le32 tx_flags = cmd->cmd.tx.tx_flags;
e6a9854b 2398 u8 rc_flags = info->control.rates[0].flags;
b481de9c
ZY		 2399
2400 cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e039fa4a 2401 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
b481de9c 2402 tx_flags |= TX_CMD_FLG_ACK_MSK;
fd7c8a40 2403 if (ieee80211_is_mgmt(fc))
b481de9c 2404 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
fd7c8a40 2405 if (ieee80211_is_probe_resp(fc) &&
b481de9c
ZY		 2406 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
2407 tx_flags |= TX_CMD_FLG_TSF_MSK;
2408 } else {
2409 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
2410 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2411 }
2412
2413 cmd->cmd.tx.sta_id = std_id;
8b7b1e05 2414 if (ieee80211_has_morefrags(fc))
b481de9c
ZY		 2415 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
2416
fd7c8a40
HH		 2417 if (ieee80211_is_data_qos(fc)) {
2418 u8 *qc = ieee80211_get_qos_ctl(hdr);
54dbb525 2419 cmd->cmd.tx.tid_tspec = qc[0] & 0xf;
b481de9c 2420 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 2421 } else {
b481de9c 2422 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 2423 }
b481de9c 2424
e6a9854b 2425 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
b481de9c
ZY		 2426 tx_flags |= TX_CMD_FLG_RTS_MSK;
2427 tx_flags &= ~TX_CMD_FLG_CTS_MSK;
e6a9854b 2428 } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
b481de9c
ZY		 2429 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2430 tx_flags |= TX_CMD_FLG_CTS_MSK;
2431 }
2432
2433 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
2434 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
2435
2436 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
fd7c8a40
HH		 2437 if (ieee80211_is_mgmt(fc)) {
2438 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
bc434dd2 2439 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
b481de9c 2440 else
bc434dd2 2441 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
ab53d8af 2442 } else {
b481de9c 2443 cmd->cmd.tx.timeout.pm_frame_timeout = 0;
ab53d8af
MA		 2444#ifdef CONFIG_IWL3945_LEDS
2445 priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
2446#endif
2447 }
b481de9c
ZY		 2448
2449 cmd->cmd.tx.driver_txop = 0;
2450 cmd->cmd.tx.tx_flags = tx_flags;
2451 cmd->cmd.tx.next_frame_len = 0;
2452}
2453
6440adb5
CB		 2454/**
2455 * iwl3945_get_sta_id - Find station's index within station table
2456 */
bb8c093b 2457static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
b481de9c
ZY		 2458{
2459 int sta_id;
2460 u16 fc = le16_to_cpu(hdr->frame_control);
2461
6440adb5 2462 /* If this frame is broadcast or management, use broadcast station id */
b481de9c
ZY		 2463 if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
2464 is_multicast_ether_addr(hdr->addr1))
2465 return priv->hw_setting.bcast_sta_id;
2466
2467 switch (priv->iw_mode) {
2468
6440adb5
CB		 2469 /* If we are a client station in a BSS network, use the special
2470 * AP station entry (that's the only station we communicate with) */
05c914fe 2471 case NL80211_IFTYPE_STATION:
b481de9c
ZY		 2472 return IWL_AP_ID;
2473
2474 /* If we are an AP, then find the station, or use BCAST */
05c914fe 2475 case NL80211_IFTYPE_AP:
bb8c093b 2476 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY		 2477 if (sta_id != IWL_INVALID_STATION)
2478 return sta_id;
2479 return priv->hw_setting.bcast_sta_id;
2480
6440adb5
CB		 2481 /* If this frame is going out to an IBSS network, find the station,
2482 * or create a new station table entry */
05c914fe 2483 case NL80211_IFTYPE_ADHOC: {
6440adb5 2484 /* Create new station table entry */
bb8c093b 2485 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY		 2486 if (sta_id != IWL_INVALID_STATION)
2487 return sta_id;
2488
bb8c093b 2489 sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
b481de9c
ZY		 2490
2491 if (sta_id != IWL_INVALID_STATION)
2492 return sta_id;
2493
e174961c 2494 IWL_DEBUG_DROP("Station %pM not in station map. "
b481de9c 2495 "Defaulting to broadcast...\n",
e174961c 2496 hdr->addr1);
bb8c093b 2497 iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
b481de9c 2498 return priv->hw_setting.bcast_sta_id;
0795af57 2499 }
914233d6
SG		 2500 /* If we are in monitor mode, use BCAST. This is required for
2501 * packet injection. */
05c914fe 2502 case NL80211_IFTYPE_MONITOR:
914233d6
SG		 2503 return priv->hw_setting.bcast_sta_id;
2504
b481de9c 2505 default:
6f147926 2506 IWL_WARNING("Unknown mode of operation: %d\n", priv->iw_mode);
b481de9c
ZY		 2507 return priv->hw_setting.bcast_sta_id;
2508 }
2509}
2510
2511/*
2512 * start REPLY_TX command process
2513 */
e039fa4a 2514static int iwl3945_tx_skb(struct iwl3945_priv *priv, struct sk_buff *skb)
b481de9c
ZY		 2515{
2516 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
e039fa4a 2517 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bb8c093b 2518 struct iwl3945_tfd_frame *tfd;
b481de9c 2519 u32 *control_flags;
e2530083 2520 int txq_id = skb_get_queue_mapping(skb);
bb8c093b
CH		 2521 struct iwl3945_tx_queue *txq = NULL;
2522 struct iwl3945_queue *q = NULL;
b481de9c
ZY		 2523 dma_addr_t phys_addr;
2524 dma_addr_t txcmd_phys;
bb8c093b 2525 struct iwl3945_cmd *out_cmd = NULL;
54dbb525
TW		 2526 u16 len, idx, len_org, hdr_len;
2527 u8 id;
2528 u8 unicast;
b481de9c 2529 u8 sta_id;
54dbb525 2530 u8 tid = 0;
b481de9c 2531 u16 seq_number = 0;
fd7c8a40 2532 __le16 fc;
b481de9c 2533 u8 wait_write_ptr = 0;
54dbb525 2534 u8 *qc = NULL;
b481de9c
ZY		 2535 unsigned long flags;
2536 int rc;
2537
2538 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2539 if (iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 2540 IWL_DEBUG_DROP("Dropping - RF KILL\n");
2541 goto drop_unlock;
2542 }
2543
e039fa4a 2544 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
b481de9c
ZY		 2545 IWL_ERROR("ERROR: No TX rate available.\n");
2546 goto drop_unlock;
2547 }
2548
2549 unicast = !is_multicast_ether_addr(hdr->addr1);
2550 id = 0;
2551
fd7c8a40 2552 fc = hdr->frame_control;
b481de9c 2553
c8b0e6e1 2554#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 2555 if (ieee80211_is_auth(fc))
2556 IWL_DEBUG_TX("Sending AUTH frame\n");
fd7c8a40 2557 else if (ieee80211_is_assoc_req(fc))
b481de9c 2558 IWL_DEBUG_TX("Sending ASSOC frame\n");
fd7c8a40 2559 else if (ieee80211_is_reassoc_req(fc))
b481de9c
ZY		 2560 IWL_DEBUG_TX("Sending REASSOC frame\n");
2561#endif
2562
7878a5a4 2563 /* drop all data frame if we are not associated */
914233d6 2564 if (ieee80211_is_data(fc) &&
05c914fe 2565 (priv->iw_mode != NL80211_IFTYPE_MONITOR) && /* packet injection */
914233d6 2566 (!iwl3945_is_associated(priv) ||
05c914fe 2567 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
bb8c093b 2568 IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
b481de9c
ZY		 2569 goto drop_unlock;
2570 }
2571
2572 spin_unlock_irqrestore(&priv->lock, flags);
2573
7294ec95 2574 hdr_len = ieee80211_hdrlen(fc);
6440adb5
CB		 2575
2576 /* Find (or create) index into station table for destination station */
bb8c093b 2577 sta_id = iwl3945_get_sta_id(priv, hdr);
b481de9c 2578 if (sta_id == IWL_INVALID_STATION) {
e174961c
JB		 2579 IWL_DEBUG_DROP("Dropping - INVALID STATION: %pM\n",
2580 hdr->addr1);
b481de9c
ZY		 2581 goto drop;
2582 }
2583
2584 IWL_DEBUG_RATE("station Id %d\n", sta_id);
2585
fd7c8a40
HH		 2586 if (ieee80211_is_data_qos(fc)) {
2587 qc = ieee80211_get_qos_ctl(hdr);
7294ec95 2588 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
b481de9c
ZY		 2589 seq_number = priv->stations[sta_id].tid[tid].seq_number &
2590 IEEE80211_SCTL_SEQ;
2591 hdr->seq_ctrl = cpu_to_le16(seq_number) |
2592 (hdr->seq_ctrl &
2593 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
2594 seq_number += 0x10;
2595 }
6440adb5
CB		 2596
2597 /* Descriptor for chosen Tx queue */
b481de9c
ZY		 2598 txq = &priv->txq[txq_id];
2599 q = &txq->q;
2600
2601 spin_lock_irqsave(&priv->lock, flags);
2602
6440adb5 2603 /* Set up first empty TFD within this queue's circular TFD buffer */
fc4b6853 2604 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY		 2605 memset(tfd, 0, sizeof(*tfd));
2606 control_flags = (u32 *) tfd;
fc4b6853 2607 idx = get_cmd_index(q, q->write_ptr, 0);
b481de9c 2608
6440adb5 2609 /* Set up driver data for this TFD */
bb8c093b 2610 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
fc4b6853 2611 txq->txb[q->write_ptr].skb[0] = skb;
6440adb5
CB		 2612
2613 /* Init first empty entry in queue's array of Tx/cmd buffers */
b481de9c
ZY		 2614 out_cmd = &txq->cmd[idx];
2615 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
2616 memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
6440adb5
CB		 2617
2618 /*
2619 * Set up the Tx-command (not MAC!) header.
2620 * Store the chosen Tx queue and TFD index within the sequence field;
2621 * after Tx, uCode's Tx response will return this value so driver can
2622 * locate the frame within the tx queue and do post-tx processing.
2623 */
b481de9c
ZY		 2624 out_cmd->hdr.cmd = REPLY_TX;
2625 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
fc4b6853 2626 INDEX_TO_SEQ(q->write_ptr)));
6440adb5
CB		 2627
2628 /* Copy MAC header from skb into command buffer */
b481de9c
ZY		 2629 memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
2630
6440adb5
CB		 2631 /*
2632 * Use the first empty entry in this queue's command buffer array
2633 * to contain the Tx command and MAC header concatenated together
2634 * (payload data will be in another buffer).
2635 * Size of this varies, due to varying MAC header length.
2636 * If end is not dword aligned, we'll have 2 extra bytes at the end
2637 * of the MAC header (device reads on dword boundaries).
2638 * We'll tell device about this padding later.
2639 */
b481de9c 2640 len = priv->hw_setting.tx_cmd_len +
bb8c093b 2641 sizeof(struct iwl3945_cmd_header) + hdr_len;
b481de9c
ZY		 2642
2643 len_org = len;
2644 len = (len + 3) & ~3;
2645
2646 if (len_org != len)
2647 len_org = 1;
2648 else
2649 len_org = 0;
2650
6440adb5
CB		 2651 /* Physical address of this Tx command's header (not MAC header!),
2652 * within command buffer array. */
bb8c093b
CH		 2653 txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
2654 offsetof(struct iwl3945_cmd, hdr);
b481de9c 2655
6440adb5
CB		 2656 /* Add buffer containing Tx command and MAC(!) header to TFD's
2657 * first entry */
bb8c093b 2658 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
b481de9c 2659
d0f09804 2660 if (info->control.hw_key)
e039fa4a 2661 iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0);
b481de9c 2662
6440adb5
CB		 2663 /* Set up TFD's 2nd entry to point directly to remainder of skb,
2664 * if any (802.11 null frames have no payload). */
b481de9c
ZY		 2665 len = skb->len - hdr_len;
2666 if (len) {
2667 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
2668 len, PCI_DMA_TODEVICE);
bb8c093b 2669 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
b481de9c
ZY		 2670 }
2671
b481de9c 2672 if (!len)
6440adb5 2673 /* If there is no payload, then we use only one Tx buffer */
b481de9c
ZY		 2674 *control_flags = TFD_CTL_COUNT_SET(1);
2675 else
6440adb5
CB		 2676 /* Else use 2 buffers.
2677 * Tell 3945 about any padding after MAC header */
b481de9c
ZY		 2678 *control_flags = TFD_CTL_COUNT_SET(2) |
2679 TFD_CTL_PAD_SET(U32_PAD(len));
2680
6440adb5 2681 /* Total # bytes to be transmitted */
b481de9c
ZY		 2682 len = (u16)skb->len;
2683 out_cmd->cmd.tx.len = cpu_to_le16(len);
2684
2685 /* TODO need this for burst mode later on */
e039fa4a 2686 iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, unicast, sta_id);
b481de9c
ZY		 2687
2688 /* set is_hcca to 0; it probably will never be implemented */
e039fa4a 2689 iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
b481de9c
ZY		 2690
2691 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
2692 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
2693
8b7b1e05 2694 if (!ieee80211_has_morefrags(hdr->frame_control)) {
b481de9c 2695 txq->need_update = 1;
3ac7f146 2696 if (qc)
b481de9c 2697 priv->stations[sta_id].tid[tid].seq_number = seq_number;
b481de9c
ZY		 2698 } else {
2699 wait_write_ptr = 1;
2700 txq->need_update = 0;
2701 }
2702
bb8c093b 2703 iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
b481de9c
ZY		 2704 sizeof(out_cmd->cmd.tx));
2705
bb8c093b 2706 iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
7294ec95 2707 ieee80211_hdrlen(fc));
b481de9c 2708
6440adb5 2709 /* Tell device the write index *just past* this latest filled TFD */
c54b679d 2710 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
bb8c093b 2711 rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 2712 spin_unlock_irqrestore(&priv->lock, flags);
2713
2714 if (rc)
2715 return rc;
2716
bb8c093b 2717 if ((iwl3945_queue_space(q) < q->high_mark)
b481de9c
ZY		 2718 && priv->mac80211_registered) {
2719 if (wait_write_ptr) {
2720 spin_lock_irqsave(&priv->lock, flags);
2721 txq->need_update = 1;
bb8c093b 2722 iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 2723 spin_unlock_irqrestore(&priv->lock, flags);
2724 }
2725
e2530083 2726 ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
b481de9c
ZY		 2727 }
2728
2729 return 0;
2730
2731drop_unlock:
2732 spin_unlock_irqrestore(&priv->lock, flags);
2733drop:
2734 return -1;
2735}
2736
bb8c093b 2737static void iwl3945_set_rate(struct iwl3945_priv *priv)
b481de9c 2738{
8318d78a 2739 const struct ieee80211_supported_band *sband = NULL;
b481de9c
ZY		 2740 struct ieee80211_rate *rate;
2741 int i;
2742
8318d78a
JB		 2743 sband = iwl3945_get_band(priv, priv->band);
2744 if (!sband) {
c4ba9621
SA		 2745 IWL_ERROR("Failed to set rate: unable to get hw mode\n");
2746 return;
2747 }
b481de9c
ZY		 2748
2749 priv->active_rate = 0;
2750 priv->active_rate_basic = 0;
2751
8318d78a
JB		 2752 IWL_DEBUG_RATE("Setting rates for %s GHz\n",
2753 sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
2754
2755 for (i = 0; i < sband->n_bitrates; i++) {
2756 rate = &sband->bitrates[i];
2757 if ((rate->hw_value < IWL_RATE_COUNT) &&
2758 !(rate->flags & IEEE80211_CHAN_DISABLED)) {
2759 IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
2760 rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
2761 priv->active_rate |= (1 << rate->hw_value);
2762 }
b481de9c
ZY		 2763 }
2764
2765 IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
2766 priv->active_rate, priv->active_rate_basic);
2767
2768 /*
2769 * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
2770 * otherwise set it to the default of all CCK rates and 6, 12, 24 for
2771 * OFDM
2772 */
2773 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
2774 priv->staging_rxon.cck_basic_rates =
2775 ((priv->active_rate_basic &
2776 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
2777 else
2778 priv->staging_rxon.cck_basic_rates =
2779 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2780
2781 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
2782 priv->staging_rxon.ofdm_basic_rates =
2783 ((priv->active_rate_basic &
2784 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
2785 IWL_FIRST_OFDM_RATE) & 0xFF;
2786 else
2787 priv->staging_rxon.ofdm_basic_rates =
2788 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2789}
2790
bb8c093b 2791static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
b481de9c
ZY		 2792{
2793 unsigned long flags;
2794
2795 if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
2796 return;
2797
2798 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
2799 disable_radio ? "OFF" : "ON");
2800
2801 if (disable_radio) {
bb8c093b 2802 iwl3945_scan_cancel(priv);
b481de9c 2803 /* FIXME: This is a workaround for AP */
05c914fe 2804 if (priv->iw_mode != NL80211_IFTYPE_AP) {
b481de9c 2805 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2806 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 2807 CSR_UCODE_SW_BIT_RFKILL);
2808 spin_unlock_irqrestore(&priv->lock, flags);
bb8c093b 2809 iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
b481de9c
ZY		 2810 set_bit(STATUS_RF_KILL_SW, &priv->status);
2811 }
2812 return;
2813 }
2814
2815 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2816 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 2817
2818 clear_bit(STATUS_RF_KILL_SW, &priv->status);
2819 spin_unlock_irqrestore(&priv->lock, flags);
2820
2821 /* wake up ucode */
2822 msleep(10);
2823
2824 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH		 2825 iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
2826 if (!iwl3945_grab_nic_access(priv))
2827 iwl3945_release_nic_access(priv);
b481de9c
ZY		 2828 spin_unlock_irqrestore(&priv->lock, flags);
2829
2830 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
2831 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
2832 "disabled by HW switch\n");
2833 return;
2834 }
2835
808e72a0
ZY		 2836 if (priv->is_open)
2837 queue_work(priv->workqueue, &priv->restart);
b481de9c
ZY		 2838 return;
2839}
2840
bb8c093b 2841void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
b481de9c
ZY		 2842 u32 decrypt_res, struct ieee80211_rx_status *stats)
2843{
2844 u16 fc =
2845 le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
2846
2847 if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
2848 return;
2849
2850 if (!(fc & IEEE80211_FCTL_PROTECTED))
2851 return;
2852
2853 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
2854 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2855 case RX_RES_STATUS_SEC_TYPE_TKIP:
2856 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2857 RX_RES_STATUS_BAD_ICV_MIC)
2858 stats->flag |= RX_FLAG_MMIC_ERROR;
2859 case RX_RES_STATUS_SEC_TYPE_WEP:
2860 case RX_RES_STATUS_SEC_TYPE_CCMP:
2861 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2862 RX_RES_STATUS_DECRYPT_OK) {
2863 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
2864 stats->flag |= RX_FLAG_DECRYPTED;
2865 }
2866 break;
2867
2868 default:
2869 break;
2870 }
2871}
2872
c8b0e6e1 2873#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 2874
2875#include "iwl-spectrum.h"
2876
2877#define BEACON_TIME_MASK_LOW 0x00FFFFFF
2878#define BEACON_TIME_MASK_HIGH 0xFF000000
2879#define TIME_UNIT 1024
2880
2881/*
2882 * extended beacon time format
2883 * time in usec will be changed into a 32-bit value in 8:24 format
2884 * the high 1 byte is the beacon counts
2885 * the lower 3 bytes is the time in usec within one beacon interval
2886 */
2887
bb8c093b 2888static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
b481de9c
ZY		 2889{
2890 u32 quot;
2891 u32 rem;
2892 u32 interval = beacon_interval * 1024;
2893
2894 if (!interval || !usec)
2895 return 0;
2896
2897 quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
2898 rem = (usec % interval) & BEACON_TIME_MASK_LOW;
2899
2900 return (quot << 24) + rem;
2901}
2902
2903/* base is usually what we get from ucode with each received frame,
2904 * the same as HW timer counter counting down
2905 */
2906
bb8c093b 2907static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
b481de9c
ZY		 2908{
2909 u32 base_low = base & BEACON_TIME_MASK_LOW;
2910 u32 addon_low = addon & BEACON_TIME_MASK_LOW;
2911 u32 interval = beacon_interval * TIME_UNIT;
2912 u32 res = (base & BEACON_TIME_MASK_HIGH) +
2913 (addon & BEACON_TIME_MASK_HIGH);
2914
2915 if (base_low > addon_low)
2916 res += base_low - addon_low;
2917 else if (base_low < addon_low) {
2918 res += interval + base_low - addon_low;
2919 res += (1 << 24);
2920 } else
2921 res += (1 << 24);
2922
2923 return cpu_to_le32(res);
2924}
2925
bb8c093b 2926static int iwl3945_get_measurement(struct iwl3945_priv *priv,
b481de9c
ZY		 2927 struct ieee80211_measurement_params *params,
2928 u8 type)
2929{
bb8c093b
CH		 2930 struct iwl3945_spectrum_cmd spectrum;
2931 struct iwl3945_rx_packet *res;
2932 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 2933 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
2934 .data = (void *)&spectrum,
2935 .meta.flags = CMD_WANT_SKB,
2936 };
2937 u32 add_time = le64_to_cpu(params->start_time);
2938 int rc;
2939 int spectrum_resp_status;
2940 int duration = le16_to_cpu(params->duration);
2941
bb8c093b 2942 if (iwl3945_is_associated(priv))
b481de9c 2943 add_time =
bb8c093b 2944 iwl3945_usecs_to_beacons(
b481de9c
ZY		 2945 le64_to_cpu(params->start_time) - priv->last_tsf,
2946 le16_to_cpu(priv->rxon_timing.beacon_interval));
2947
2948 memset(&spectrum, 0, sizeof(spectrum));
2949
2950 spectrum.channel_count = cpu_to_le16(1);
2951 spectrum.flags =
2952 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
2953 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
2954 cmd.len = sizeof(spectrum);
2955 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
2956
bb8c093b 2957 if (iwl3945_is_associated(priv))
b481de9c 2958 spectrum.start_time =
bb8c093b 2959 iwl3945_add_beacon_time(priv->last_beacon_time,
b481de9c
ZY		 2960 add_time,
2961 le16_to_cpu(priv->rxon_timing.beacon_interval));
2962 else
2963 spectrum.start_time = 0;
2964
2965 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
2966 spectrum.channels[0].channel = params->channel;
2967 spectrum.channels[0].type = type;
2968 if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
2969 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
2970 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
2971
bb8c093b 2972 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 2973 if (rc)
2974 return rc;
2975
bb8c093b 2976 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 2977 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
2978 IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
2979 rc = -EIO;
2980 }
2981
2982 spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
2983 switch (spectrum_resp_status) {
2984 case 0: /* Command will be handled */
2985 if (res->u.spectrum.id != 0xff) {
bc434dd2
IS		 2986 IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
2987 res->u.spectrum.id);
b481de9c
ZY		 2988 priv->measurement_status &= ~MEASUREMENT_READY;
2989 }
2990 priv->measurement_status |= MEASUREMENT_ACTIVE;
2991 rc = 0;
2992 break;
2993
2994 case 1: /* Command will not be handled */
2995 rc = -EAGAIN;
2996 break;
2997 }
2998
2999 dev_kfree_skb_any(cmd.meta.u.skb);
3000
3001 return rc;
3002}
3003#endif
3004
bb8c093b
CH		 3005static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
3006 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3007{
bb8c093b
CH		 3008 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3009 struct iwl3945_alive_resp *palive;
b481de9c
ZY		 3010 struct delayed_work *pwork;
3011
3012 palive = &pkt->u.alive_frame;
3013
3014 IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
3015 "0x%01X 0x%01X\n",
3016 palive->is_valid, palive->ver_type,
3017 palive->ver_subtype);
3018
3019 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
3020 IWL_DEBUG_INFO("Initialization Alive received.\n");
3021 memcpy(&priv->card_alive_init,
3022 &pkt->u.alive_frame,
bb8c093b 3023 sizeof(struct iwl3945_init_alive_resp));
b481de9c
ZY		 3024 pwork = &priv->init_alive_start;
3025 } else {
3026 IWL_DEBUG_INFO("Runtime Alive received.\n");
3027 memcpy(&priv->card_alive, &pkt->u.alive_frame,
bb8c093b 3028 sizeof(struct iwl3945_alive_resp));
b481de9c 3029 pwork = &priv->alive_start;
bb8c093b 3030 iwl3945_disable_events(priv);
b481de9c
ZY		 3031 }
3032
3033 /* We delay the ALIVE response by 5ms to
3034 * give the HW RF Kill time to activate... */
3035 if (palive->is_valid == UCODE_VALID_OK)
3036 queue_delayed_work(priv->workqueue, pwork,
3037 msecs_to_jiffies(5));
3038 else
3039 IWL_WARNING("uCode did not respond OK.\n");
3040}
3041
bb8c093b
CH		 3042static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
3043 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3044{
bb8c093b 3045 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3046
3047 IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
3048 return;
3049}
3050
bb8c093b
CH		 3051static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
3052 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3053{
bb8c093b 3054 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3055
3056 IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
3057 "seq 0x%04X ser 0x%08X\n",
3058 le32_to_cpu(pkt->u.err_resp.error_type),
3059 get_cmd_string(pkt->u.err_resp.cmd_id),
3060 pkt->u.err_resp.cmd_id,
3061 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
3062 le32_to_cpu(pkt->u.err_resp.error_info));
3063}
3064
3065#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
3066
bb8c093b 3067static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3068{
bb8c093b
CH		 3069 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3070 struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
3071 struct iwl3945_csa_notification *csa = &(pkt->u.csa_notif);
b481de9c
ZY		 3072 IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
3073 le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
3074 rxon->channel = csa->channel;
3075 priv->staging_rxon.channel = csa->channel;
3076}
3077
bb8c093b
CH		 3078static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
3079 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3080{
c8b0e6e1 3081#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
bb8c093b
CH		 3082 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3083 struct iwl3945_spectrum_notification *report = &(pkt->u.spectrum_notif);
b481de9c
ZY		 3084
3085 if (!report->state) {
3086 IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
3087 "Spectrum Measure Notification: Start\n");
3088 return;
3089 }
3090
3091 memcpy(&priv->measure_report, report, sizeof(*report));
3092 priv->measurement_status |= MEASUREMENT_READY;
3093#endif
3094}
3095
bb8c093b
CH		 3096static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
3097 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3098{
c8b0e6e1 3099#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3100 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3101 struct iwl3945_sleep_notification *sleep = &(pkt->u.sleep_notif);
b481de9c
ZY		 3102 IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
3103 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
3104#endif
3105}
3106
bb8c093b
CH		 3107static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
3108 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3109{
bb8c093b 3110 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3111 IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
3112 "notification for %s:\n",
3113 le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
bb8c093b 3114 iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
b481de9c
ZY		 3115}
3116
bb8c093b 3117static void iwl3945_bg_beacon_update(struct work_struct *work)
b481de9c 3118{
bb8c093b
CH		 3119 struct iwl3945_priv *priv =
3120 container_of(work, struct iwl3945_priv, beacon_update);
b481de9c
ZY		 3121 struct sk_buff *beacon;
3122
3123 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 3124 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY		 3125
3126 if (!beacon) {
3127 IWL_ERROR("update beacon failed\n");
3128 return;
3129 }
3130
3131 mutex_lock(&priv->mutex);
3132 /* new beacon skb is allocated every time; dispose previous.*/
3133 if (priv->ibss_beacon)
3134 dev_kfree_skb(priv->ibss_beacon);
3135
3136 priv->ibss_beacon = beacon;
3137 mutex_unlock(&priv->mutex);
3138
bb8c093b 3139 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 3140}
3141
bb8c093b
CH		 3142static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
3143 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3144{
c8b0e6e1 3145#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3146 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3147 struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
b481de9c
ZY		 3148 u8 rate = beacon->beacon_notify_hdr.rate;
3149
3150 IWL_DEBUG_RX("beacon status %x retries %d iss %d "
3151 "tsf %d %d rate %d\n",
3152 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
3153 beacon->beacon_notify_hdr.failure_frame,
3154 le32_to_cpu(beacon->ibss_mgr_status),
3155 le32_to_cpu(beacon->high_tsf),
3156 le32_to_cpu(beacon->low_tsf), rate);
3157#endif
3158
05c914fe 3159 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY		 3160 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
3161 queue_work(priv->workqueue, &priv->beacon_update);
3162}
3163
3164/* Service response to REPLY_SCAN_CMD (0x80) */
bb8c093b
CH		 3165static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
3166 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3167{
c8b0e6e1 3168#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3169 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3170 struct iwl3945_scanreq_notification *notif =
3171 (struct iwl3945_scanreq_notification *)pkt->u.raw;
b481de9c
ZY		 3172
3173 IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
3174#endif
3175}
3176
3177/* Service SCAN_START_NOTIFICATION (0x82) */
bb8c093b
CH		 3178static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
3179 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3180{
bb8c093b
CH		 3181 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3182 struct iwl3945_scanstart_notification *notif =
3183 (struct iwl3945_scanstart_notification *)pkt->u.raw;
b481de9c
ZY		 3184 priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
3185 IWL_DEBUG_SCAN("Scan start: "
3186 "%d [802.11%s] "
3187 "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
3188 notif->channel,
3189 notif->band ? "bg" : "a",
3190 notif->tsf_high,
3191 notif->tsf_low, notif->status, notif->beacon_timer);
3192}
3193
3194/* Service SCAN_RESULTS_NOTIFICATION (0x83) */
bb8c093b
CH		 3195static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
3196 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3197{
bb8c093b
CH		 3198 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3199 struct iwl3945_scanresults_notification *notif =
3200 (struct iwl3945_scanresults_notification *)pkt->u.raw;
b481de9c
ZY		 3201
3202 IWL_DEBUG_SCAN("Scan ch.res: "
3203 "%d [802.11%s] "
3204 "(TSF: 0x%08X:%08X) - %d "
3205 "elapsed=%lu usec (%dms since last)\n",
3206 notif->channel,
3207 notif->band ? "bg" : "a",
3208 le32_to_cpu(notif->tsf_high),
3209 le32_to_cpu(notif->tsf_low),
3210 le32_to_cpu(notif->statistics[0]),
3211 le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
3212 jiffies_to_msecs(elapsed_jiffies
3213 (priv->last_scan_jiffies, jiffies)));
3214
3215 priv->last_scan_jiffies = jiffies;
7878a5a4 3216 priv->next_scan_jiffies = 0;
b481de9c
ZY		 3217}
3218
3219/* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
bb8c093b
CH		 3220static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
3221 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3222{
bb8c093b
CH		 3223 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3224 struct iwl3945_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
b481de9c
ZY		 3225
3226 IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
3227 scan_notif->scanned_channels,
3228 scan_notif->tsf_low,
3229 scan_notif->tsf_high, scan_notif->status);
3230
3231 /* The HW is no longer scanning */
3232 clear_bit(STATUS_SCAN_HW, &priv->status);
3233
3234 /* The scan completion notification came in, so kill that timer... */
3235 cancel_delayed_work(&priv->scan_check);
3236
3237 IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
66b5004d
RR		 3238 (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ?
3239 "2.4" : "5.2",
b481de9c
ZY		 3240 jiffies_to_msecs(elapsed_jiffies
3241 (priv->scan_pass_start, jiffies)));
3242
66b5004d
RR		 3243 /* Remove this scanned band from the list of pending
3244 * bands to scan, band G precedes A in order of scanning
3245 * as seen in iwl3945_bg_request_scan */
3246 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ))
3247 priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ);
3248 else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ))
3249 priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ);
b481de9c
ZY		 3250
3251 /* If a request to abort was given, or the scan did not succeed
3252 * then we reset the scan state machine and terminate,
3253 * re-queuing another scan if one has been requested */
3254 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
3255 IWL_DEBUG_INFO("Aborted scan completed.\n");
3256 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
3257 } else {
3258 /* If there are more bands on this scan pass reschedule */
3259 if (priv->scan_bands > 0)
3260 goto reschedule;
3261 }
3262
3263 priv->last_scan_jiffies = jiffies;
7878a5a4 3264 priv->next_scan_jiffies = 0;
b481de9c
ZY		 3265 IWL_DEBUG_INFO("Setting scan to off\n");
3266
3267 clear_bit(STATUS_SCANNING, &priv->status);
3268
3269 IWL_DEBUG_INFO("Scan took %dms\n",
3270 jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
3271
3272 queue_work(priv->workqueue, &priv->scan_completed);
3273
3274 return;
3275
3276reschedule:
3277 priv->scan_pass_start = jiffies;
3278 queue_work(priv->workqueue, &priv->request_scan);
3279}
3280
3281/* Handle notification from uCode that card's power state is changing
3282 * due to software, hardware, or critical temperature RFKILL */
bb8c093b
CH		 3283static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
3284 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3285{
bb8c093b 3286 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3287 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
3288 unsigned long status = priv->status;
3289
3290 IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
3291 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3292 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
3293
bb8c093b 3294 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 3295 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3296
3297 if (flags & HW_CARD_DISABLED)
3298 set_bit(STATUS_RF_KILL_HW, &priv->status);
3299 else
3300 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3301
3302
3303 if (flags & SW_CARD_DISABLED)
3304 set_bit(STATUS_RF_KILL_SW, &priv->status);
3305 else
3306 clear_bit(STATUS_RF_KILL_SW, &priv->status);
3307
bb8c093b 3308 iwl3945_scan_cancel(priv);
b481de9c
ZY		 3309
3310 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
3311 test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
3312 (test_bit(STATUS_RF_KILL_SW, &status) !=
3313 test_bit(STATUS_RF_KILL_SW, &priv->status)))
3314 queue_work(priv->workqueue, &priv->rf_kill);
3315 else
3316 wake_up_interruptible(&priv->wait_command_queue);
3317}
3318
3319/**
bb8c093b 3320 * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY		 3321 *
3322 * Setup the RX handlers for each of the reply types sent from the uCode
3323 * to the host.
3324 *
3325 * This function chains into the hardware specific files for them to setup
3326 * any hardware specific handlers as well.
3327 */
bb8c093b 3328static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
b481de9c 3329{
bb8c093b
CH		 3330 priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
3331 priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
3332 priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
3333 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
b481de9c 3334 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
bb8c093b
CH		 3335 iwl3945_rx_spectrum_measure_notif;
3336 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
b481de9c 3337 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
bb8c093b
CH		 3338 iwl3945_rx_pm_debug_statistics_notif;
3339 priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
b481de9c 3340
9fbab516
BC		 3341 /*
3342 * The same handler is used for both the REPLY to a discrete
3343 * statistics request from the host as well as for the periodic
3344 * statistics notifications (after received beacons) from the uCode.
b481de9c 3345 */
bb8c093b
CH		 3346 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
3347 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
b481de9c 3348
bb8c093b
CH		 3349 priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
3350 priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
b481de9c 3351 priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
bb8c093b 3352 iwl3945_rx_scan_results_notif;
b481de9c 3353 priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
bb8c093b
CH		 3354 iwl3945_rx_scan_complete_notif;
3355 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
b481de9c 3356
9fbab516 3357 /* Set up hardware specific Rx handlers */
bb8c093b 3358 iwl3945_hw_rx_handler_setup(priv);
b481de9c
ZY		 3359}
3360
91c066f2
TW		 3361/**
3362 * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries
3363 * When FW advances 'R' index, all entries between old and new 'R' index
3364 * need to be reclaimed.
3365 */
3366static void iwl3945_cmd_queue_reclaim(struct iwl3945_priv *priv,
3367 int txq_id, int index)
3368{
3369 struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
3370 struct iwl3945_queue *q = &txq->q;
3371 int nfreed = 0;
3372
3373 if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) {
3374 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
3375 "is out of range [0-%d] %d %d.\n", txq_id,
3376 index, q->n_bd, q->write_ptr, q->read_ptr);
3377 return;
3378 }
3379
3380 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
3381 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
3382 if (nfreed > 1) {
3383 IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
3384 q->write_ptr, q->read_ptr);
3385 queue_work(priv->workqueue, &priv->restart);
3386 break;
3387 }
3388 nfreed++;
3389 }
3390}
3391
3392
b481de9c 3393/**
bb8c093b 3394 * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
b481de9c
ZY		 3395 * @rxb: Rx buffer to reclaim
3396 *
3397 * If an Rx buffer has an async callback associated with it the callback
3398 * will be executed. The attached skb (if present) will only be freed
3399 * if the callback returns 1
3400 */
bb8c093b
CH		 3401static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
3402 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3403{
bb8c093b 3404 struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
b481de9c
ZY		 3405 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3406 int txq_id = SEQ_TO_QUEUE(sequence);
3407 int index = SEQ_TO_INDEX(sequence);
3408 int huge = sequence & SEQ_HUGE_FRAME;
3409 int cmd_index;
bb8c093b 3410 struct iwl3945_cmd *cmd;
b481de9c 3411
b481de9c
ZY		 3412 BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
3413
3414 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
3415 cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
3416
3417 /* Input error checking is done when commands are added to queue. */
3418 if (cmd->meta.flags & CMD_WANT_SKB) {
3419 cmd->meta.source->u.skb = rxb->skb;
3420 rxb->skb = NULL;
3421 } else if (cmd->meta.u.callback &&
3422 !cmd->meta.u.callback(priv, cmd, rxb->skb))
3423 rxb->skb = NULL;
3424
91c066f2 3425 iwl3945_cmd_queue_reclaim(priv, txq_id, index);
b481de9c
ZY		 3426
3427 if (!(cmd->meta.flags & CMD_ASYNC)) {
3428 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
3429 wake_up_interruptible(&priv->wait_command_queue);
3430 }
3431}
3432
3433/************************** RX-FUNCTIONS ****************************/
3434/*
3435 * Rx theory of operation
3436 *
3437 * The host allocates 32 DMA target addresses and passes the host address
3438 * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
3439 * 0 to 31
3440 *
3441 * Rx Queue Indexes
3442 * The host/firmware share two index registers for managing the Rx buffers.
3443 *
3444 * The READ index maps to the first position that the firmware may be writing
3445 * to -- the driver can read up to (but not including) this position and get
3446 * good data.
3447 * The READ index is managed by the firmware once the card is enabled.
3448 *
3449 * The WRITE index maps to the last position the driver has read from -- the
3450 * position preceding WRITE is the last slot the firmware can place a packet.
3451 *
3452 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
3453 * WRITE = READ.
3454 *
9fbab516 3455 * During initialization, the host sets up the READ queue position to the first
b481de9c
ZY		 3456 * INDEX position, and WRITE to the last (READ - 1 wrapped)
3457 *
9fbab516 3458 * When the firmware places a packet in a buffer, it will advance the READ index
b481de9c
ZY		 3459 * and fire the RX interrupt. The driver can then query the READ index and
3460 * process as many packets as possible, moving the WRITE index forward as it
3461 * resets the Rx queue buffers with new memory.
3462 *
3463 * The management in the driver is as follows:
3464 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
3465 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
01ebd063 3466 * to replenish the iwl->rxq->rx_free.
bb8c093b 3467 * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
b481de9c
ZY		 3468 * iwl->rxq is replenished and the READ INDEX is updated (updating the
3469 * 'processed' and 'read' driver indexes as well)
3470 * + A received packet is processed and handed to the kernel network stack,
3471 * detached from the iwl->rxq. The driver 'processed' index is updated.
3472 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
3473 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
3474 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
3475 * were enough free buffers and RX_STALLED is set it is cleared.
3476 *
3477 *
3478 * Driver sequence:
3479 *
9fbab516
BC		 3480 * iwl3945_rx_queue_alloc() Allocates rx_free
3481 * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
bb8c093b 3482 * iwl3945_rx_queue_restock
9fbab516 3483 * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
b481de9c
ZY		 3484 * queue, updates firmware pointers, and updates
3485 * the WRITE index. If insufficient rx_free buffers
bb8c093b 3486 * are available, schedules iwl3945_rx_replenish
b481de9c
ZY		 3487 *
3488 * -- enable interrupts --
9fbab516 3489 * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the
b481de9c
ZY		 3490 * READ INDEX, detaching the SKB from the pool.
3491 * Moves the packet buffer from queue to rx_used.
bb8c093b 3492 * Calls iwl3945_rx_queue_restock to refill any empty
b481de9c
ZY		 3493 * slots.
3494 * ...
3495 *
3496 */
3497
3498/**
bb8c093b 3499 * iwl3945_rx_queue_space - Return number of free slots available in queue.
b481de9c 3500 */
bb8c093b 3501static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
b481de9c
ZY		 3502{
3503 int s = q->read - q->write;
3504 if (s <= 0)
3505 s += RX_QUEUE_SIZE;
3506 /* keep some buffer to not confuse full and empty queue */
3507 s -= 2;
3508 if (s < 0)
3509 s = 0;
3510 return s;
3511}
3512
3513/**
bb8c093b 3514 * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
b481de9c 3515 */
bb8c093b 3516int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
b481de9c
ZY		 3517{
3518 u32 reg = 0;
3519 int rc = 0;
3520 unsigned long flags;
3521
3522 spin_lock_irqsave(&q->lock, flags);
3523
3524 if (q->need_update == 0)
3525 goto exit_unlock;
3526
6440adb5 3527 /* If power-saving is in use, make sure device is awake */
b481de9c 3528 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
bb8c093b 3529 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY		 3530
3531 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
bb8c093b 3532 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 3533 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3534 goto exit_unlock;
3535 }
3536
bb8c093b 3537 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 3538 if (rc)
3539 goto exit_unlock;
3540
6440adb5 3541 /* Device expects a multiple of 8 */
bb8c093b 3542 iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
b481de9c 3543 q->write & ~0x7);
bb8c093b 3544 iwl3945_release_nic_access(priv);
6440adb5
CB		 3545
3546 /* Else device is assumed to be awake */
b481de9c 3547 } else
6440adb5 3548 /* Device expects a multiple of 8 */
bb8c093b 3549 iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
b481de9c
ZY		 3550
3551
3552 q->need_update = 0;
3553
3554 exit_unlock:
3555 spin_unlock_irqrestore(&q->lock, flags);
3556 return rc;
3557}
3558
3559/**
9fbab516 3560 * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
b481de9c 3561 */
bb8c093b 3562static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
b481de9c
ZY		 3563 dma_addr_t dma_addr)
3564{
3565 return cpu_to_le32((u32)dma_addr);
3566}
3567
3568/**
bb8c093b 3569 * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
b481de9c 3570 *
9fbab516 3571 * If there are slots in the RX queue that need to be restocked,
b481de9c 3572 * and we have free pre-allocated buffers, fill the ranks as much
9fbab516 3573 * as we can, pulling from rx_free.
b481de9c
ZY		 3574 *
3575 * This moves the 'write' index forward to catch up with 'processed', and
3576 * also updates the memory address in the firmware to reference the new
3577 * target buffer.
3578 */
bb8c093b 3579static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
b481de9c 3580{
bb8c093b 3581 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 3582 struct list_head *element;
bb8c093b 3583 struct iwl3945_rx_mem_buffer *rxb;
b481de9c
ZY		 3584 unsigned long flags;
3585 int write, rc;
3586
3587 spin_lock_irqsave(&rxq->lock, flags);
3588 write = rxq->write & ~0x7;
bb8c093b 3589 while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
6440adb5 3590 /* Get next free Rx buffer, remove from free list */
b481de9c 3591 element = rxq->rx_free.next;
bb8c093b 3592 rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
b481de9c 3593 list_del(element);
6440adb5
CB		 3594
3595 /* Point to Rx buffer via next RBD in circular buffer */
bb8c093b 3596 rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
b481de9c
ZY		 3597 rxq->queue[rxq->write] = rxb;
3598 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
3599 rxq->free_count--;
3600 }
3601 spin_unlock_irqrestore(&rxq->lock, flags);
3602 /* If the pre-allocated buffer pool is dropping low, schedule to
3603 * refill it */
3604 if (rxq->free_count <= RX_LOW_WATERMARK)
3605 queue_work(priv->workqueue, &priv->rx_replenish);
3606
3607
6440adb5
CB		 3608 /* If we've added more space for the firmware to place data, tell it.
3609 * Increment device's write pointer in multiples of 8. */
b481de9c
ZY		 3610 if ((write != (rxq->write & ~0x7))
3611 || (abs(rxq->write - rxq->read) > 7)) {
3612 spin_lock_irqsave(&rxq->lock, flags);
3613 rxq->need_update = 1;
3614 spin_unlock_irqrestore(&rxq->lock, flags);
bb8c093b 3615 rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 3616 if (rc)
3617 return rc;
3618 }
3619
3620 return 0;
3621}
3622
3623/**
bb8c093b 3624 * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
b481de9c
ZY		 3625 *
3626 * When moving to rx_free an SKB is allocated for the slot.
3627 *
bb8c093b 3628 * Also restock the Rx queue via iwl3945_rx_queue_restock.
01ebd063 3629 * This is called as a scheduled work item (except for during initialization)
b481de9c 3630 */
5c0eef96 3631static void iwl3945_rx_allocate(struct iwl3945_priv *priv)
b481de9c 3632{
bb8c093b 3633 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 3634 struct list_head *element;
bb8c093b 3635 struct iwl3945_rx_mem_buffer *rxb;
b481de9c
ZY		 3636 unsigned long flags;
3637 spin_lock_irqsave(&rxq->lock, flags);
3638 while (!list_empty(&rxq->rx_used)) {
3639 element = rxq->rx_used.next;
bb8c093b 3640 rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
6440adb5
CB		 3641
3642 /* Alloc a new receive buffer */
b481de9c
ZY		 3643 rxb->skb =
3644 alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
3645 if (!rxb->skb) {
3646 if (net_ratelimit())
3647 printk(KERN_CRIT DRV_NAME
3648 ": Can not allocate SKB buffers\n");
3649 /* We don't reschedule replenish work here -- we will
3650 * call the restock method and if it still needs
3651 * more buffers it will schedule replenish */
3652 break;
3653 }
12342c47
ZY		 3654
3655 /* If radiotap head is required, reserve some headroom here.
3656 * The physical head count is a variable rx_stats->phy_count.
3657 * We reserve 4 bytes here. Plus these extra bytes, the
3658 * headroom of the physical head should be enough for the
3659 * radiotap head that iwl3945 supported. See iwl3945_rt.
3660 */
3661 skb_reserve(rxb->skb, 4);
3662
b481de9c
ZY		 3663 priv->alloc_rxb_skb++;
3664 list_del(element);
6440adb5
CB		 3665
3666 /* Get physical address of RB/SKB */
b481de9c
ZY		 3667 rxb->dma_addr =
3668 pci_map_single(priv->pci_dev, rxb->skb->data,
3669 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3670 list_add_tail(&rxb->list, &rxq->rx_free);
3671 rxq->free_count++;
3672 }
3673 spin_unlock_irqrestore(&rxq->lock, flags);
5c0eef96
MA		 3674}
3675
3676/*
3677 * this should be called while priv->lock is locked
3678 */
4fd1f841 3679static void __iwl3945_rx_replenish(void *data)
5c0eef96
MA		 3680{
3681 struct iwl3945_priv *priv = data;
3682
3683 iwl3945_rx_allocate(priv);
3684 iwl3945_rx_queue_restock(priv);
3685}
3686
3687
3688void iwl3945_rx_replenish(void *data)
3689{
3690 struct iwl3945_priv *priv = data;
3691 unsigned long flags;
3692
3693 iwl3945_rx_allocate(priv);
b481de9c
ZY		 3694
3695 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 3696 iwl3945_rx_queue_restock(priv);
b481de9c
ZY		 3697 spin_unlock_irqrestore(&priv->lock, flags);
3698}
3699
3700/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
9fbab516 3701 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
b481de9c
ZY		 3702 * This free routine walks the list of POOL entries and if SKB is set to
3703 * non NULL it is unmapped and freed
3704 */
bb8c093b 3705static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY		 3706{
3707 int i;
3708 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
3709 if (rxq->pool[i].skb != NULL) {
3710 pci_unmap_single(priv->pci_dev,
3711 rxq->pool[i].dma_addr,
3712 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3713 dev_kfree_skb(rxq->pool[i].skb);
3714 }
3715 }
3716
3717 pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
3718 rxq->dma_addr);
3719 rxq->bd = NULL;
3720}
3721
bb8c093b 3722int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
b481de9c 3723{
bb8c093b 3724 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 3725 struct pci_dev *dev = priv->pci_dev;
3726 int i;
3727
3728 spin_lock_init(&rxq->lock);
3729 INIT_LIST_HEAD(&rxq->rx_free);
3730 INIT_LIST_HEAD(&rxq->rx_used);
6440adb5
CB		 3731
3732 /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
b481de9c
ZY		 3733 rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
3734 if (!rxq->bd)
3735 return -ENOMEM;
6440adb5 3736
b481de9c
ZY		 3737 /* Fill the rx_used queue with _all_ of the Rx buffers */
3738 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
3739 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
6440adb5 3740
b481de9c
ZY		 3741 /* Set us so that we have processed and used all buffers, but have
3742 * not restocked the Rx queue with fresh buffers */
3743 rxq->read = rxq->write = 0;
3744 rxq->free_count = 0;
3745 rxq->need_update = 0;
3746 return 0;
3747}
3748
bb8c093b 3749void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY		 3750{
3751 unsigned long flags;
3752 int i;
3753 spin_lock_irqsave(&rxq->lock, flags);
3754 INIT_LIST_HEAD(&rxq->rx_free);
3755 INIT_LIST_HEAD(&rxq->rx_used);
3756 /* Fill the rx_used queue with _all_ of the Rx buffers */
3757 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
3758 /* In the reset function, these buffers may have been allocated
3759 * to an SKB, so we need to unmap and free potential storage */
3760 if (rxq->pool[i].skb != NULL) {
3761 pci_unmap_single(priv->pci_dev,
3762 rxq->pool[i].dma_addr,
3763 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3764 priv->alloc_rxb_skb--;
3765 dev_kfree_skb(rxq->pool[i].skb);
3766 rxq->pool[i].skb = NULL;
3767 }
3768 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
3769 }
3770
3771 /* Set us so that we have processed and used all buffers, but have
3772 * not restocked the Rx queue with fresh buffers */
3773 rxq->read = rxq->write = 0;
3774 rxq->free_count = 0;
3775 spin_unlock_irqrestore(&rxq->lock, flags);
3776}
3777
3778/* Convert linear signal-to-noise ratio into dB */
3779static u8 ratio2dB[100] = {
3780/* 0 1 2 3 4 5 6 7 8 9 */
3781 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
3782 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
3783 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
3784 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
3785 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
3786 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
3787 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
3788 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
3789 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
3790 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
3791};
3792
3793/* Calculates a relative dB value from a ratio of linear
3794 * (i.e. not dB) signal levels.
3795 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
bb8c093b 3796int iwl3945_calc_db_from_ratio(int sig_ratio)
b481de9c 3797{
221c80cf
AB		 3798 /* 1000:1 or higher just report as 60 dB */
3799 if (sig_ratio >= 1000)
b481de9c
ZY		 3800 return 60;
3801
221c80cf 3802 /* 100:1 or higher, divide by 10 and use table,
b481de9c 3803 * add 20 dB to make up for divide by 10 */
221c80cf 3804 if (sig_ratio >= 100)
3ac7f146 3805 return 20 + (int)ratio2dB[sig_ratio/10];
b481de9c
ZY		 3806
3807 /* We shouldn't see this */
3808 if (sig_ratio < 1)
3809 return 0;
3810
3811 /* Use table for ratios 1:1 - 99:1 */
3812 return (int)ratio2dB[sig_ratio];
3813}
3814
3815#define PERFECT_RSSI (-20) /* dBm */
3816#define WORST_RSSI (-95) /* dBm */
3817#define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
3818
3819/* Calculate an indication of rx signal quality (a percentage, not dBm!).
3820 * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
3821 * about formulas used below. */
bb8c093b 3822int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
b481de9c
ZY		 3823{
3824 int sig_qual;
3825 int degradation = PERFECT_RSSI - rssi_dbm;
3826
3827 /* If we get a noise measurement, use signal-to-noise ratio (SNR)
3828 * as indicator; formula is (signal dbm - noise dbm).
3829 * SNR at or above 40 is a great signal (100%).
3830 * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
3831 * Weakest usable signal is usually 10 - 15 dB SNR. */
3832 if (noise_dbm) {
3833 if (rssi_dbm - noise_dbm >= 40)
3834 return 100;
3835 else if (rssi_dbm < noise_dbm)
3836 return 0;
3837 sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
3838
3839 /* Else use just the signal level.
3840 * This formula is a least squares fit of data points collected and
3841 * compared with a reference system that had a percentage (%) display
3842 * for signal quality. */
3843 } else
3844 sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
3845 (15 * RSSI_RANGE + 62 * degradation)) /
3846 (RSSI_RANGE * RSSI_RANGE);
3847
3848 if (sig_qual > 100)
3849 sig_qual = 100;
3850 else if (sig_qual < 1)
3851 sig_qual = 0;
3852
3853 return sig_qual;
3854}
3855
3856/**
9fbab516 3857 * iwl3945_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY		 3858 *
3859 * Uses the priv->rx_handlers callback function array to invoke
3860 * the appropriate handlers, including command responses,
3861 * frame-received notifications, and other notifications.
3862 */
bb8c093b 3863static void iwl3945_rx_handle(struct iwl3945_priv *priv)
b481de9c 3864{
bb8c093b
CH		 3865 struct iwl3945_rx_mem_buffer *rxb;
3866 struct iwl3945_rx_packet *pkt;
3867 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 3868 u32 r, i;
3869 int reclaim;
3870 unsigned long flags;
5c0eef96 3871 u8 fill_rx = 0;
d68ab680 3872 u32 count = 8;
b481de9c 3873
6440adb5
CB		 3874 /* uCode's read index (stored in shared DRAM) indicates the last Rx
3875 * buffer that the driver may process (last buffer filled by ucode). */
bb8c093b 3876 r = iwl3945_hw_get_rx_read(priv);
b481de9c
ZY		 3877 i = rxq->read;
3878
5c0eef96
MA		 3879 if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
3880 fill_rx = 1;
b481de9c
ZY		 3881 /* Rx interrupt, but nothing sent from uCode */
3882 if (i == r)
3883 IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
3884
3885 while (i != r) {
3886 rxb = rxq->queue[i];
3887
9fbab516 3888 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY		 3889 * then a bug has been introduced in the queue refilling
3890 * routines -- catch it here */
3891 BUG_ON(rxb == NULL);
3892
3893 rxq->queue[i] = NULL;
3894
3895 pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
3896 IWL_RX_BUF_SIZE,
3897 PCI_DMA_FROMDEVICE);
bb8c093b 3898 pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
b481de9c
ZY		 3899
3900 /* Reclaim a command buffer only if this packet is a response
3901 * to a (driver-originated) command.
3902 * If the packet (e.g. Rx frame) originated from uCode,
3903 * there is no command buffer to reclaim.
3904 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
3905 * but apparently a few don't get set; catch them here. */
3906 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
3907 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
3908 (pkt->hdr.cmd != REPLY_TX);
3909
3910 /* Based on type of command response or notification,
3911 * handle those that need handling via function in
bb8c093b 3912 * rx_handlers table. See iwl3945_setup_rx_handlers() */
b481de9c
ZY		 3913 if (priv->rx_handlers[pkt->hdr.cmd]) {
3914 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
3915 "r = %d, i = %d, %s, 0x%02x\n", r, i,
3916 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
3917 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
3918 } else {
3919 /* No handling needed */
3920 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
3921 "r %d i %d No handler needed for %s, 0x%02x\n",
3922 r, i, get_cmd_string(pkt->hdr.cmd),
3923 pkt->hdr.cmd);
3924 }
3925
3926 if (reclaim) {
9fbab516
BC		 3927 /* Invoke any callbacks, transfer the skb to caller, and
3928 * fire off the (possibly) blocking iwl3945_send_cmd()
b481de9c
ZY		 3929 * as we reclaim the driver command queue */
3930 if (rxb && rxb->skb)
bb8c093b 3931 iwl3945_tx_cmd_complete(priv, rxb);
b481de9c
ZY		 3932 else
3933 IWL_WARNING("Claim null rxb?\n");
3934 }
3935
3936 /* For now we just don't re-use anything. We can tweak this
3937 * later to try and re-use notification packets and SKBs that
3938 * fail to Rx correctly */
3939 if (rxb->skb != NULL) {
3940 priv->alloc_rxb_skb--;
3941 dev_kfree_skb_any(rxb->skb);
3942 rxb->skb = NULL;
3943 }
3944
3945 pci_unmap_single(priv->pci_dev, rxb->dma_addr,
3946 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3947 spin_lock_irqsave(&rxq->lock, flags);
3948 list_add_tail(&rxb->list, &priv->rxq.rx_used);
3949 spin_unlock_irqrestore(&rxq->lock, flags);
3950 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA		 3951 /* If there are a lot of unused frames,
3952 * restock the Rx queue so ucode won't assert. */
3953 if (fill_rx) {
3954 count++;
3955 if (count >= 8) {
3956 priv->rxq.read = i;
3957 __iwl3945_rx_replenish(priv);
3958 count = 0;
3959 }
3960 }
b481de9c
ZY		 3961 }
3962
3963 /* Backtrack one entry */
3964 priv->rxq.read = i;
bb8c093b 3965 iwl3945_rx_queue_restock(priv);
b481de9c
ZY		 3966}
3967
6440adb5
CB		 3968/**
3969 * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
3970 */
bb8c093b
CH		 3971static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
3972 struct iwl3945_tx_queue *txq)
b481de9c
ZY		 3973{
3974 u32 reg = 0;
3975 int rc = 0;
3976 int txq_id = txq->q.id;
3977
3978 if (txq->need_update == 0)
3979 return rc;
3980
3981 /* if we're trying to save power */
3982 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
3983 /* wake up nic if it's powered down ...
3984 * uCode will wake up, and interrupt us again, so next
3985 * time we'll skip this part. */
bb8c093b 3986 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY		 3987
3988 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
3989 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
bb8c093b 3990 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 3991 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3992 return rc;
3993 }
3994
3995 /* restore this queue's parameters in nic hardware. */
bb8c093b 3996 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 3997 if (rc)
3998 return rc;
bb8c093b 3999 iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
fc4b6853 4000 txq->q.write_ptr | (txq_id << 8));
bb8c093b 4001 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4002
4003 /* else not in power-save mode, uCode will never sleep when we're
4004 * trying to tx (during RFKILL, we're not trying to tx). */
4005 } else
bb8c093b 4006 iwl3945_write32(priv, HBUS_TARG_WRPTR,
fc4b6853 4007 txq->q.write_ptr | (txq_id << 8));
b481de9c
ZY		 4008
4009 txq->need_update = 0;
4010
4011 return rc;
4012}
4013
c8b0e6e1 4014#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4015static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon)
b481de9c
ZY		 4016{
4017 IWL_DEBUG_RADIO("RX CONFIG:\n");
bb8c093b 4018 iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
b481de9c
ZY		 4019 IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
4020 IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
4021 IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
4022 le32_to_cpu(rxon->filter_flags));
4023 IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
4024 IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
4025 rxon->ofdm_basic_rates);
4026 IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
e174961c
JB		 4027 IWL_DEBUG_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
4028 IWL_DEBUG_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
b481de9c
ZY		 4029 IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
4030}
4031#endif
4032
bb8c093b 4033static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
b481de9c
ZY		 4034{
4035 IWL_DEBUG_ISR("Enabling interrupts\n");
4036 set_bit(STATUS_INT_ENABLED, &priv->status);
bb8c093b 4037 iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
b481de9c
ZY		 4038}
4039
0359facc
MA		 4040
4041/* call this function to flush any scheduled tasklet */
4042static inline void iwl_synchronize_irq(struct iwl3945_priv *priv)
4043{
4044 /* wait to make sure we flush pedding tasklet*/
4045 synchronize_irq(priv->pci_dev->irq);
4046 tasklet_kill(&priv->irq_tasklet);
4047}
4048
4049
bb8c093b 4050static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
b481de9c
ZY		 4051{
4052 clear_bit(STATUS_INT_ENABLED, &priv->status);
4053
4054 /* disable interrupts from uCode/NIC to host */
bb8c093b 4055 iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY		 4056
4057 /* acknowledge/clear/reset any interrupts still pending
4058 * from uCode or flow handler (Rx/Tx DMA) */
bb8c093b
CH		 4059 iwl3945_write32(priv, CSR_INT, 0xffffffff);
4060 iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
b481de9c
ZY		 4061 IWL_DEBUG_ISR("Disabled interrupts\n");
4062}
4063
4064static const char *desc_lookup(int i)
4065{
4066 switch (i) {
4067 case 1:
4068 return "FAIL";
4069 case 2:
4070 return "BAD_PARAM";
4071 case 3:
4072 return "BAD_CHECKSUM";
4073 case 4:
4074 return "NMI_INTERRUPT";
4075 case 5:
4076 return "SYSASSERT";
4077 case 6:
4078 return "FATAL_ERROR";
4079 }
4080
4081 return "UNKNOWN";
4082}
4083
4084#define ERROR_START_OFFSET (1 * sizeof(u32))
4085#define ERROR_ELEM_SIZE (7 * sizeof(u32))
4086
bb8c093b 4087static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
b481de9c
ZY		 4088{
4089 u32 i;
4090 u32 desc, time, count, base, data1;
4091 u32 blink1, blink2, ilink1, ilink2;
4092 int rc;
4093
4094 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
4095
bb8c093b 4096 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 4097 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
4098 return;
4099 }
4100
bb8c093b 4101 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 4102 if (rc) {
4103 IWL_WARNING("Can not read from adapter at this time.\n");
4104 return;
4105 }
4106
bb8c093b 4107 count = iwl3945_read_targ_mem(priv, base);
b481de9c
ZY		 4108
4109 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
4110 IWL_ERROR("Start IWL Error Log Dump:\n");
2acae16e 4111 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
b481de9c
ZY		 4112 }
4113
4114 IWL_ERROR("Desc Time asrtPC blink2 "
4115 "ilink1 nmiPC Line\n");
4116 for (i = ERROR_START_OFFSET;
4117 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
4118 i += ERROR_ELEM_SIZE) {
bb8c093b 4119 desc = iwl3945_read_targ_mem(priv, base + i);
b481de9c 4120 time =
bb8c093b 4121 iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
b481de9c 4122 blink1 =
bb8c093b 4123 iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
b481de9c 4124 blink2 =
bb8c093b 4125 iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
b481de9c 4126 ilink1 =
bb8c093b 4127 iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
b481de9c 4128 ilink2 =
bb8c093b 4129 iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
b481de9c 4130 data1 =
bb8c093b 4131 iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
b481de9c
ZY		 4132
4133 IWL_ERROR
4134 ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
4135 desc_lookup(desc), desc, time, blink1, blink2,
4136 ilink1, ilink2, data1);
4137 }
4138
bb8c093b 4139 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4140
4141}
4142
f58177b9 4143#define EVENT_START_OFFSET (6 * sizeof(u32))
b481de9c
ZY		 4144
4145/**
bb8c093b 4146 * iwl3945_print_event_log - Dump error event log to syslog
b481de9c 4147 *
bb8c093b 4148 * NOTE: Must be called with iwl3945_grab_nic_access() already obtained!
b481de9c 4149 */
bb8c093b 4150static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
b481de9c
ZY		 4151 u32 num_events, u32 mode)
4152{
4153 u32 i;
4154 u32 base; /* SRAM byte address of event log header */
4155 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
4156 u32 ptr; /* SRAM byte address of log data */
4157 u32 ev, time, data; /* event log data */
4158
4159 if (num_events == 0)
4160 return;
4161
4162 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
4163
4164 if (mode == 0)
4165 event_size = 2 * sizeof(u32);
4166 else
4167 event_size = 3 * sizeof(u32);
4168
4169 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
4170
4171 /* "time" is actually "data" for mode 0 (no timestamp).
4172 * place event id # at far right for easier visual parsing. */
4173 for (i = 0; i < num_events; i++) {
bb8c093b 4174 ev = iwl3945_read_targ_mem(priv, ptr);
b481de9c 4175 ptr += sizeof(u32);
bb8c093b 4176 time = iwl3945_read_targ_mem(priv, ptr);
b481de9c
ZY		 4177 ptr += sizeof(u32);
4178 if (mode == 0)
4179 IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
4180 else {
bb8c093b 4181 data = iwl3945_read_targ_mem(priv, ptr);
b481de9c
ZY		 4182 ptr += sizeof(u32);
4183 IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
4184 }
4185 }
4186}
4187
bb8c093b 4188static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
b481de9c
ZY		 4189{
4190 int rc;
4191 u32 base; /* SRAM byte address of event log header */
4192 u32 capacity; /* event log capacity in # entries */
4193 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
4194 u32 num_wraps; /* # times uCode wrapped to top of log */
4195 u32 next_entry; /* index of next entry to be written by uCode */
4196 u32 size; /* # entries that we'll print */
4197
4198 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 4199 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 4200 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
4201 return;
4202 }
4203
bb8c093b 4204 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 4205 if (rc) {
4206 IWL_WARNING("Can not read from adapter at this time.\n");
4207 return;
4208 }
4209
4210 /* event log header */
bb8c093b
CH		 4211 capacity = iwl3945_read_targ_mem(priv, base);
4212 mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
4213 num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
4214 next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
b481de9c
ZY		 4215
4216 size = num_wraps ? capacity : next_entry;
4217
4218 /* bail out if nothing in log */
4219 if (size == 0) {
583fab37 4220 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
bb8c093b 4221 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4222 return;
4223 }
4224
583fab37 4225 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
b481de9c
ZY		 4226 size, num_wraps);
4227
4228 /* if uCode has wrapped back to top of log, start at the oldest entry,
4229 * i.e the next one that uCode would fill. */
4230 if (num_wraps)
bb8c093b 4231 iwl3945_print_event_log(priv, next_entry,
b481de9c
ZY		 4232 capacity - next_entry, mode);
4233
4234 /* (then/else) start at top of log */
bb8c093b 4235 iwl3945_print_event_log(priv, 0, next_entry, mode);
b481de9c 4236
bb8c093b 4237 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4238}
4239
4240/**
bb8c093b 4241 * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
b481de9c 4242 */
bb8c093b 4243static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
b481de9c 4244{
bb8c093b 4245 /* Set the FW error flag -- cleared on iwl3945_down */
b481de9c
ZY		 4246 set_bit(STATUS_FW_ERROR, &priv->status);
4247
4248 /* Cancel currently queued command. */
4249 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
4250
c8b0e6e1 4251#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 4252 if (iwl3945_debug_level & IWL_DL_FW_ERRORS) {
4253 iwl3945_dump_nic_error_log(priv);
4254 iwl3945_dump_nic_event_log(priv);
4255 iwl3945_print_rx_config_cmd(&priv->staging_rxon);
b481de9c
ZY		 4256 }
4257#endif
4258
4259 wake_up_interruptible(&priv->wait_command_queue);
4260
4261 /* Keep the restart process from trying to send host
4262 * commands by clearing the INIT status bit */
4263 clear_bit(STATUS_READY, &priv->status);
4264
4265 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
4266 IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
4267 "Restarting adapter due to uCode error.\n");
4268
bb8c093b 4269 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 4270 memcpy(&priv->recovery_rxon, &priv->active_rxon,
4271 sizeof(priv->recovery_rxon));
4272 priv->error_recovering = 1;
4273 }
4274 queue_work(priv->workqueue, &priv->restart);
4275 }
4276}
4277
bb8c093b 4278static void iwl3945_error_recovery(struct iwl3945_priv *priv)
b481de9c
ZY		 4279{
4280 unsigned long flags;
4281
4282 memcpy(&priv->staging_rxon, &priv->recovery_rxon,
4283 sizeof(priv->staging_rxon));
4284 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 4285 iwl3945_commit_rxon(priv);
b481de9c 4286
bb8c093b 4287 iwl3945_add_station(priv, priv->bssid, 1, 0);
b481de9c
ZY		 4288
4289 spin_lock_irqsave(&priv->lock, flags);
4290 priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
4291 priv->error_recovering = 0;
4292 spin_unlock_irqrestore(&priv->lock, flags);
4293}
4294
bb8c093b 4295static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
b481de9c
ZY		 4296{
4297 u32 inta, handled = 0;
4298 u32 inta_fh;
4299 unsigned long flags;
c8b0e6e1 4300#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 4301 u32 inta_mask;
4302#endif
4303
4304 spin_lock_irqsave(&priv->lock, flags);
4305
4306 /* Ack/clear/reset pending uCode interrupts.
4307 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
4308 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
bb8c093b
CH		 4309 inta = iwl3945_read32(priv, CSR_INT);
4310 iwl3945_write32(priv, CSR_INT, inta);
b481de9c
ZY		 4311
4312 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
4313 * Any new interrupts that happen after this, either while we're
4314 * in this tasklet, or later, will show up in next ISR/tasklet. */
bb8c093b
CH		 4315 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
4316 iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 4317
c8b0e6e1 4318#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4319 if (iwl3945_debug_level & IWL_DL_ISR) {
9fbab516
BC		 4320 /* just for debug */
4321 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
b481de9c
ZY		 4322 IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4323 inta, inta_mask, inta_fh);
4324 }
4325#endif
4326
4327 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
4328 * atomic, make sure that inta covers all the interrupts that
4329 * we've discovered, even if FH interrupt came in just after
4330 * reading CSR_INT. */
6f83eaa1 4331 if (inta_fh & CSR39_FH_INT_RX_MASK)
b481de9c 4332 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 4333 if (inta_fh & CSR39_FH_INT_TX_MASK)
b481de9c
ZY		 4334 inta |= CSR_INT_BIT_FH_TX;
4335
4336 /* Now service all interrupt bits discovered above. */
4337 if (inta & CSR_INT_BIT_HW_ERR) {
4338 IWL_ERROR("Microcode HW error detected. Restarting.\n");
4339
4340 /* Tell the device to stop sending interrupts */
bb8c093b 4341 iwl3945_disable_interrupts(priv);
b481de9c 4342
bb8c093b 4343 iwl3945_irq_handle_error(priv);
b481de9c
ZY		 4344
4345 handled |= CSR_INT_BIT_HW_ERR;
4346
4347 spin_unlock_irqrestore(&priv->lock, flags);
4348
4349 return;
4350 }
4351
c8b0e6e1 4352#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4353 if (iwl3945_debug_level & (IWL_DL_ISR)) {
b481de9c 4354 /* NIC fires this, but we don't use it, redundant with WAKEUP */
25c03d8e
JP		 4355 if (inta & CSR_INT_BIT_SCD)
4356 IWL_DEBUG_ISR("Scheduler finished to transmit "
4357 "the frame/frames.\n");
b481de9c
ZY		 4358
4359 /* Alive notification via Rx interrupt will do the real work */
4360 if (inta & CSR_INT_BIT_ALIVE)
4361 IWL_DEBUG_ISR("Alive interrupt\n");
4362 }
4363#endif
4364 /* Safely ignore these bits for debug checks below */
25c03d8e 4365 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c
ZY		 4366
4367 /* HW RF KILL switch toggled (4965 only) */
4368 if (inta & CSR_INT_BIT_RF_KILL) {
4369 int hw_rf_kill = 0;
bb8c093b 4370 if (!(iwl3945_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY		 4371 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
4372 hw_rf_kill = 1;
4373
4374 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR,
4375 "RF_KILL bit toggled to %s.\n",
4376 hw_rf_kill ? "disable radio":"enable radio");
4377
4378 /* Queue restart only if RF_KILL switch was set to "kill"
4379 * when we loaded driver, and is now set to "enable".
4380 * After we're Alive, RF_KILL gets handled by
3230455d 4381 * iwl3945_rx_card_state_notif() */
53e49093
ZY		 4382 if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) {
4383 clear_bit(STATUS_RF_KILL_HW, &priv->status);
b481de9c 4384 queue_work(priv->workqueue, &priv->restart);
53e49093 4385 }
b481de9c
ZY		 4386
4387 handled |= CSR_INT_BIT_RF_KILL;
4388 }
4389
4390 /* Chip got too hot and stopped itself (4965 only) */
4391 if (inta & CSR_INT_BIT_CT_KILL) {
4392 IWL_ERROR("Microcode CT kill error detected.\n");
4393 handled |= CSR_INT_BIT_CT_KILL;
4394 }
4395
4396 /* Error detected by uCode */
4397 if (inta & CSR_INT_BIT_SW_ERR) {
4398 IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
4399 inta);
bb8c093b 4400 iwl3945_irq_handle_error(priv);
b481de9c
ZY		 4401 handled |= CSR_INT_BIT_SW_ERR;
4402 }
4403
4404 /* uCode wakes up after power-down sleep */
4405 if (inta & CSR_INT_BIT_WAKEUP) {
4406 IWL_DEBUG_ISR("Wakeup interrupt\n");
bb8c093b
CH		 4407 iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
4408 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
4409 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
4410 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
4411 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
4412 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
4413 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
b481de9c
ZY		 4414
4415 handled |= CSR_INT_BIT_WAKEUP;
4416 }
4417
4418 /* All uCode command responses, including Tx command responses,
4419 * Rx "responses" (frame-received notification), and other
4420 * notifications from uCode come through here*/
4421 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
bb8c093b 4422 iwl3945_rx_handle(priv);
b481de9c
ZY		 4423 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
4424 }
4425
4426 if (inta & CSR_INT_BIT_FH_TX) {
4427 IWL_DEBUG_ISR("Tx interrupt\n");
4428
bb8c093b
CH		 4429 iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
4430 if (!iwl3945_grab_nic_access(priv)) {
4431 iwl3945_write_direct32(priv,
b481de9c
ZY		 4432 FH_TCSR_CREDIT
4433 (ALM_FH_SRVC_CHNL), 0x0);
bb8c093b 4434 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4435 }
4436 handled |= CSR_INT_BIT_FH_TX;
4437 }
4438
4439 if (inta & ~handled)
4440 IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
4441
4442 if (inta & ~CSR_INI_SET_MASK) {
4443 IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
4444 inta & ~CSR_INI_SET_MASK);
4445 IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
4446 }
4447
4448 /* Re-enable all interrupts */
0359facc
MA		 4449 /* only Re-enable if disabled by irq */
4450 if (test_bit(STATUS_INT_ENABLED, &priv->status))
4451 iwl3945_enable_interrupts(priv);
b481de9c 4452
c8b0e6e1 4453#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 4454 if (iwl3945_debug_level & (IWL_DL_ISR)) {
4455 inta = iwl3945_read32(priv, CSR_INT);
4456 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
4457 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY		 4458 IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4459 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
4460 }
4461#endif
4462 spin_unlock_irqrestore(&priv->lock, flags);
4463}
4464
bb8c093b 4465static irqreturn_t iwl3945_isr(int irq, void *data)
b481de9c 4466{
bb8c093b 4467 struct iwl3945_priv *priv = data;
b481de9c
ZY		 4468 u32 inta, inta_mask;
4469 u32 inta_fh;
4470 if (!priv)
4471 return IRQ_NONE;
4472
4473 spin_lock(&priv->lock);
4474
4475 /* Disable (but don't clear!) interrupts here to avoid
4476 * back-to-back ISRs and sporadic interrupts from our NIC.
4477 * If we have something to service, the tasklet will re-enable ints.
4478 * If we *don't* have something, we'll re-enable before leaving here. */
bb8c093b
CH		 4479 inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */
4480 iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY		 4481
4482 /* Discover which interrupts are active/pending */
bb8c093b
CH		 4483 inta = iwl3945_read32(priv, CSR_INT);
4484 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY		 4485
4486 /* Ignore interrupt if there's nothing in NIC to service.
4487 * This may be due to IRQ shared with another device,
4488 * or due to sporadic interrupts thrown from our NIC. */
4489 if (!inta && !inta_fh) {
4490 IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
4491 goto none;
4492 }
4493
4494 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
4495 /* Hardware disappeared */
4496 IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta);
cb4da1a3 4497 goto unplugged;
b481de9c
ZY		 4498 }
4499
4500 IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4501 inta, inta_mask, inta_fh);
4502
25c03d8e
JP		 4503 inta &= ~CSR_INT_BIT_SCD;
4504
bb8c093b 4505 /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
25c03d8e
JP		 4506 if (likely(inta || inta_fh))
4507 tasklet_schedule(&priv->irq_tasklet);
cb4da1a3 4508unplugged:
b481de9c
ZY		 4509 spin_unlock(&priv->lock);
4510
4511 return IRQ_HANDLED;
4512
4513 none:
4514 /* re-enable interrupts here since we don't have anything to service. */
0359facc
MA		 4515 /* only Re-enable if disabled by irq */
4516 if (test_bit(STATUS_INT_ENABLED, &priv->status))
4517 iwl3945_enable_interrupts(priv);
b481de9c
ZY		 4518 spin_unlock(&priv->lock);
4519 return IRQ_NONE;
4520}
4521
4522/************************** EEPROM BANDS ****************************
4523 *
bb8c093b 4524 * The iwl3945_eeprom_band definitions below provide the mapping from the
b481de9c
ZY		 4525 * EEPROM contents to the specific channel number supported for each
4526 * band.
4527 *
bb8c093b 4528 * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3
b481de9c
ZY		 4529 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
4530 * The specific geography and calibration information for that channel
4531 * is contained in the eeprom map itself.
4532 *
4533 * During init, we copy the eeprom information and channel map
4534 * information into priv->channel_info_24/52 and priv->channel_map_24/52
4535 *
4536 * channel_map_24/52 provides the index in the channel_info array for a
4537 * given channel. We have to have two separate maps as there is channel
4538 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
4539 * band_2
4540 *
4541 * A value of 0xff stored in the channel_map indicates that the channel
4542 * is not supported by the hardware at all.
4543 *
4544 * A value of 0xfe in the channel_map indicates that the channel is not
4545 * valid for Tx with the current hardware. This means that
4546 * while the system can tune and receive on a given channel, it may not
4547 * be able to associate or transmit any frames on that
4548 * channel. There is no corresponding channel information for that
4549 * entry.
4550 *
4551 *********************************************************************/
4552
4553/* 2.4 GHz */
bb8c093b 4554static const u8 iwl3945_eeprom_band_1[14] = {
b481de9c
ZY		 4555 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
4556};
4557
4558/* 5.2 GHz bands */
9fbab516 4559static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
b481de9c
ZY		 4560 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
4561};
4562
9fbab516 4563static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
b481de9c
ZY		 4564 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
4565};
4566
bb8c093b 4567static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
b481de9c
ZY		 4568 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
4569};
4570
bb8c093b 4571static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
b481de9c
ZY		 4572 145, 149, 153, 157, 161, 165
4573};
4574
bb8c093b 4575static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
b481de9c 4576 int *eeprom_ch_count,
bb8c093b 4577 const struct iwl3945_eeprom_channel
b481de9c
ZY		 4578 **eeprom_ch_info,
4579 const u8 **eeprom_ch_index)
4580{
4581 switch (band) {
4582 case 1: /* 2.4GHz band */
bb8c093b 4583 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
b481de9c 4584 *eeprom_ch_info = priv->eeprom.band_1_channels;
bb8c093b 4585 *eeprom_ch_index = iwl3945_eeprom_band_1;
b481de9c 4586 break;
9fbab516 4587 case 2: /* 4.9GHz band */
bb8c093b 4588 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
b481de9c 4589 *eeprom_ch_info = priv->eeprom.band_2_channels;
bb8c093b 4590 *eeprom_ch_index = iwl3945_eeprom_band_2;
b481de9c
ZY		 4591 break;
4592 case 3: /* 5.2GHz band */
bb8c093b 4593 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
b481de9c 4594 *eeprom_ch_info = priv->eeprom.band_3_channels;
bb8c093b 4595 *eeprom_ch_index = iwl3945_eeprom_band_3;
b481de9c 4596 break;
9fbab516 4597 case 4: /* 5.5GHz band */
bb8c093b 4598 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
b481de9c 4599 *eeprom_ch_info = priv->eeprom.band_4_channels;
bb8c093b 4600 *eeprom_ch_index = iwl3945_eeprom_band_4;
b481de9c 4601 break;
9fbab516 4602 case 5: /* 5.7GHz band */
bb8c093b 4603 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
b481de9c 4604 *eeprom_ch_info = priv->eeprom.band_5_channels;
bb8c093b 4605 *eeprom_ch_index = iwl3945_eeprom_band_5;
b481de9c
ZY		 4606 break;
4607 default:
4608 BUG();
4609 return;
4610 }
4611}
4612
6440adb5
CB		 4613/**
4614 * iwl3945_get_channel_info - Find driver's private channel info
4615 *
4616 * Based on band and channel number.
4617 */
bb8c093b 4618const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv,
8318d78a 4619 enum ieee80211_band band, u16 channel)
b481de9c
ZY		 4620{
4621 int i;
4622
8318d78a
JB		 4623 switch (band) {
4624 case IEEE80211_BAND_5GHZ:
b481de9c
ZY		 4625 for (i = 14; i < priv->channel_count; i++) {
4626 if (priv->channel_info[i].channel == channel)
4627 return &priv->channel_info[i];
4628 }
4629 break;
4630
8318d78a 4631 case IEEE80211_BAND_2GHZ:
b481de9c
ZY		 4632 if (channel >= 1 && channel <= 14)
4633 return &priv->channel_info[channel - 1];
4634 break;
8318d78a
JB		 4635 case IEEE80211_NUM_BANDS:
4636 WARN_ON(1);
b481de9c
ZY		 4637 }
4638
4639 return NULL;
4640}
4641
4642#define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
4643 ? # x " " : "")
4644
6440adb5
CB		 4645/**
4646 * iwl3945_init_channel_map - Set up driver's info for all possible channels
4647 */
bb8c093b 4648static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
b481de9c
ZY		 4649{
4650 int eeprom_ch_count = 0;
4651 const u8 *eeprom_ch_index = NULL;
bb8c093b 4652 const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL;
b481de9c 4653 int band, ch;
bb8c093b 4654 struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 4655
4656 if (priv->channel_count) {
4657 IWL_DEBUG_INFO("Channel map already initialized.\n");
4658 return 0;
4659 }
4660
4661 if (priv->eeprom.version < 0x2f) {
4662 IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
4663 priv->eeprom.version);
4664 return -EINVAL;
4665 }
4666
4667 IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
4668
4669 priv->channel_count =
bb8c093b
CH		 4670 ARRAY_SIZE(iwl3945_eeprom_band_1) +
4671 ARRAY_SIZE(iwl3945_eeprom_band_2) +
4672 ARRAY_SIZE(iwl3945_eeprom_band_3) +
4673 ARRAY_SIZE(iwl3945_eeprom_band_4) +
4674 ARRAY_SIZE(iwl3945_eeprom_band_5);
b481de9c
ZY		 4675
4676 IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
4677
bb8c093b 4678 priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) *
b481de9c
ZY		 4679 priv->channel_count, GFP_KERNEL);
4680 if (!priv->channel_info) {
4681 IWL_ERROR("Could not allocate channel_info\n");
4682 priv->channel_count = 0;
4683 return -ENOMEM;
4684 }
4685
4686 ch_info = priv->channel_info;
4687
4688 /* Loop through the 5 EEPROM bands adding them in order to the
4689 * channel map we maintain (that contains additional information than
4690 * what just in the EEPROM) */
4691 for (band = 1; band <= 5; band++) {
4692
bb8c093b 4693 iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
b481de9c
ZY		 4694 &eeprom_ch_info, &eeprom_ch_index);
4695
4696 /* Loop through each band adding each of the channels */
4697 for (ch = 0; ch < eeprom_ch_count; ch++) {
4698 ch_info->channel = eeprom_ch_index[ch];
8318d78a
JB		 4699 ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
4700 IEEE80211_BAND_5GHZ;
b481de9c
ZY		 4701
4702 /* permanently store EEPROM's channel regulatory flags
4703 * and max power in channel info database. */
4704 ch_info->eeprom = eeprom_ch_info[ch];
4705
4706 /* Copy the run-time flags so they are there even on
4707 * invalid channels */
4708 ch_info->flags = eeprom_ch_info[ch].flags;
4709
4710 if (!(is_channel_valid(ch_info))) {
4711 IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
4712 "No traffic\n",
4713 ch_info->channel,
4714 ch_info->flags,
4715 is_channel_a_band(ch_info) ?
4716 "5.2" : "2.4");
4717 ch_info++;
4718 continue;
4719 }
4720
4721 /* Initialize regulatory-based run-time data */
4722 ch_info->max_power_avg = ch_info->curr_txpow =
4723 eeprom_ch_info[ch].max_power_avg;
4724 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
4725 ch_info->min_power = 0;
4726
fe7c4040 4727 IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
b481de9c
ZY		 4728 " %ddBm): Ad-Hoc %ssupported\n",
4729 ch_info->channel,
4730 is_channel_a_band(ch_info) ?
4731 "5.2" : "2.4",
8211ef78 4732 CHECK_AND_PRINT(VALID),
b481de9c
ZY		 4733 CHECK_AND_PRINT(IBSS),
4734 CHECK_AND_PRINT(ACTIVE),
4735 CHECK_AND_PRINT(RADAR),
4736 CHECK_AND_PRINT(WIDE),
b481de9c
ZY		 4737 CHECK_AND_PRINT(DFS),
4738 eeprom_ch_info[ch].flags,
4739 eeprom_ch_info[ch].max_power_avg,
4740 ((eeprom_ch_info[ch].
4741 flags & EEPROM_CHANNEL_IBSS)
4742 && !(eeprom_ch_info[ch].
4743 flags & EEPROM_CHANNEL_RADAR))
4744 ? "" : "not ");
4745
4746 /* Set the user_txpower_limit to the highest power
4747 * supported by any channel */
4748 if (eeprom_ch_info[ch].max_power_avg >
4749 priv->user_txpower_limit)
4750 priv->user_txpower_limit =
4751 eeprom_ch_info[ch].max_power_avg;
4752
4753 ch_info++;
4754 }
4755 }
4756
6440adb5 4757 /* Set up txpower settings in driver for all channels */
b481de9c
ZY		 4758 if (iwl3945_txpower_set_from_eeprom(priv))
4759 return -EIO;
4760
4761 return 0;
4762}
4763
849e0dce
RC		 4764/*
4765 * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
4766 */
4767static void iwl3945_free_channel_map(struct iwl3945_priv *priv)
4768{
4769 kfree(priv->channel_info);
4770 priv->channel_count = 0;
4771}
4772
b481de9c
ZY		 4773/* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
4774 * sending probe req. This should be set long enough to hear probe responses
4775 * from more than one AP. */
f9340520
AK		 4776#define IWL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
4777#define IWL_ACTIVE_DWELL_TIME_52 (20)
4778
4779#define IWL_ACTIVE_DWELL_FACTOR_24GHZ (3)
4780#define IWL_ACTIVE_DWELL_FACTOR_52GHZ (2)
b481de9c
ZY		 4781
4782/* For faster active scanning, scan will move to the next channel if fewer than
4783 * PLCP_QUIET_THRESH packets are heard on this channel within
4784 * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
4785 * time if it's a quiet channel (nothing responded to our probe, and there's
4786 * no other traffic).
4787 * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
4788#define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
f9340520 4789#define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(10) /* msec */
b481de9c
ZY		 4790
4791/* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
4792 * Must be set longer than active dwell time.
4793 * For the most reliable scan, set > AP beacon interval (typically 100msec). */
4794#define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
4795#define IWL_PASSIVE_DWELL_TIME_52 (10)
4796#define IWL_PASSIVE_DWELL_BASE (100)
4797#define IWL_CHANNEL_TUNE_TIME 5
4798
f9340520
AK		 4799#define IWL_SCAN_PROBE_MASK(n) cpu_to_le32((BIT(n) | (BIT(n) - BIT(1))))
4800
8318d78a 4801static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv,
f9340520
AK		 4802 enum ieee80211_band band,
4803 u8 n_probes)
b481de9c 4804{
8318d78a 4805 if (band == IEEE80211_BAND_5GHZ)
f9340520
AK		 4806 return IWL_ACTIVE_DWELL_TIME_52 +
4807 IWL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
b481de9c 4808 else
f9340520
AK		 4809 return IWL_ACTIVE_DWELL_TIME_24 +
4810 IWL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
b481de9c
ZY		 4811}
4812
8318d78a
JB		 4813static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv,
4814 enum ieee80211_band band)
b481de9c 4815{
8318d78a 4816 u16 passive = (band == IEEE80211_BAND_2GHZ) ?
b481de9c
ZY		 4817 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
4818 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
4819
bb8c093b 4820 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 4821 /* If we're associated, we clamp the maximum passive
4822 * dwell time to be 98% of the beacon interval (minus
4823 * 2 * channel tune time) */
4824 passive = priv->beacon_int;
4825 if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
4826 passive = IWL_PASSIVE_DWELL_BASE;
4827 passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
4828 }
4829
b481de9c
ZY		 4830 return passive;
4831}
4832
8318d78a
JB		 4833static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv,
4834 enum ieee80211_band band,
f9340520 4835 u8 is_active, u8 n_probes,
bb8c093b 4836 struct iwl3945_scan_channel *scan_ch)
b481de9c
ZY		 4837{
4838 const struct ieee80211_channel *channels = NULL;
8318d78a 4839 const struct ieee80211_supported_band *sband;
bb8c093b 4840 const struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 4841 u16 passive_dwell = 0;
4842 u16 active_dwell = 0;
4843 int added, i;
4844
8318d78a
JB		 4845 sband = iwl3945_get_band(priv, band);
4846 if (!sband)
b481de9c
ZY		 4847 return 0;
4848
8318d78a 4849 channels = sband->channels;
b481de9c 4850
f9340520 4851 active_dwell = iwl3945_get_active_dwell_time(priv, band, n_probes);
8318d78a 4852 passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
b481de9c 4853
8f4807a1
AK		 4854 if (passive_dwell <= active_dwell)
4855 passive_dwell = active_dwell + 1;
4856
8318d78a 4857 for (i = 0, added = 0; i < sband->n_channels; i++) {
182e2e66
JB		 4858 if (channels[i].flags & IEEE80211_CHAN_DISABLED)
4859 continue;
4860
8318d78a 4861 scan_ch->channel = channels[i].hw_value;
b481de9c 4862
8318d78a 4863 ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
b481de9c 4864 if (!is_channel_valid(ch_info)) {
66b5004d 4865 IWL_DEBUG_SCAN("Channel %d is INVALID for this band.\n",
b481de9c
ZY		 4866 scan_ch->channel);
4867 continue;
4868 }
4869
4870 if (!is_active || is_channel_passive(ch_info) ||
8318d78a 4871 (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN))
b481de9c
ZY		 4872 scan_ch->type = 0; /* passive */
4873 else
4874 scan_ch->type = 1; /* active */
4875
f9340520
AK		 4876 if ((scan_ch->type & 1) && n_probes)
4877 scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
b481de9c 4878
b481de9c
ZY		 4879 scan_ch->active_dwell = cpu_to_le16(active_dwell);
4880 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
4881
9fbab516 4882 /* Set txpower levels to defaults */
b481de9c
ZY		 4883 scan_ch->tpc.dsp_atten = 110;
4884 /* scan_pwr_info->tpc.dsp_atten; */
4885
4886 /*scan_pwr_info->tpc.tx_gain; */
8318d78a 4887 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 4888 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
4889 else {
4890 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
4891 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
9fbab516 4892 * power level:
8a1b0245 4893 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
b481de9c
ZY		 4894 */
4895 }
4896
4897 IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
4898 scan_ch->channel,
4899 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
4900 (scan_ch->type & 1) ?
4901 active_dwell : passive_dwell);
4902
4903 scan_ch++;
4904 added++;
4905 }
4906
4907 IWL_DEBUG_SCAN("total channels to scan %d \n", added);
4908 return added;
4909}
4910
bb8c093b 4911static void iwl3945_init_hw_rates(struct iwl3945_priv *priv,
b481de9c
ZY		 4912 struct ieee80211_rate *rates)
4913{
4914 int i;
4915
4916 for (i = 0; i < IWL_RATE_COUNT; i++) {
8318d78a
JB		 4917 rates[i].bitrate = iwl3945_rates[i].ieee * 5;
4918 rates[i].hw_value = i; /* Rate scaling will work on indexes */
4919 rates[i].hw_value_short = i;
4920 rates[i].flags = 0;
4921 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
b481de9c 4922 /*
8318d78a 4923 * If CCK != 1M then set short preamble rate flag.
b481de9c 4924 */
bb8c093b 4925 rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
8318d78a 4926 0 : IEEE80211_RATE_SHORT_PREAMBLE;
b481de9c 4927 }
b481de9c
ZY		 4928 }
4929}
4930
4931/**
bb8c093b 4932 * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
b481de9c 4933 */
bb8c093b 4934static int iwl3945_init_geos(struct iwl3945_priv *priv)
b481de9c 4935{
bb8c093b 4936 struct iwl3945_channel_info *ch;
8211ef78 4937 struct ieee80211_supported_band *sband;
b481de9c
ZY		 4938 struct ieee80211_channel *channels;
4939 struct ieee80211_channel *geo_ch;
4940 struct ieee80211_rate *rates;
4941 int i = 0;
b481de9c 4942
8318d78a
JB		 4943 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
4944 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
b481de9c
ZY		 4945 IWL_DEBUG_INFO("Geography modes already initialized.\n");
4946 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
4947 return 0;
4948 }
4949
b481de9c
ZY		 4950 channels = kzalloc(sizeof(struct ieee80211_channel) *
4951 priv->channel_count, GFP_KERNEL);
8318d78a 4952 if (!channels)
b481de9c 4953 return -ENOMEM;
b481de9c 4954
8211ef78 4955 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
b481de9c
ZY		 4956 GFP_KERNEL);
4957 if (!rates) {
b481de9c
ZY		 4958 kfree(channels);
4959 return -ENOMEM;
4960 }
4961
b481de9c 4962 /* 5.2GHz channels start after the 2.4GHz channels */
8211ef78
TW		 4963 sband = &priv->bands[IEEE80211_BAND_5GHZ];
4964 sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
4965 /* just OFDM */
4966 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
4967 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
4968
4969 sband = &priv->bands[IEEE80211_BAND_2GHZ];
4970 sband->channels = channels;
4971 /* OFDM & CCK */
4972 sband->bitrates = rates;
4973 sband->n_bitrates = IWL_RATE_COUNT;
b481de9c
ZY		 4974
4975 priv->ieee_channels = channels;
4976 priv->ieee_rates = rates;
4977
bb8c093b 4978 iwl3945_init_hw_rates(priv, rates);
b481de9c 4979
8211ef78 4980 for (i = 0; i < priv->channel_count; i++) {
b481de9c
ZY		 4981 ch = &priv->channel_info[i];
4982
8211ef78
TW		 4983 /* FIXME: might be removed if scan is OK*/
4984 if (!is_channel_valid(ch))
b481de9c 4985 continue;
b481de9c
ZY		 4986
4987 if (is_channel_a_band(ch))
8211ef78 4988 sband = &priv->bands[IEEE80211_BAND_5GHZ];
8318d78a 4989 else
8211ef78 4990 sband = &priv->bands[IEEE80211_BAND_2GHZ];
b481de9c 4991
8211ef78
TW		 4992 geo_ch = &sband->channels[sband->n_channels++];
4993
4994 geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
8318d78a
JB		 4995 geo_ch->max_power = ch->max_power_avg;
4996 geo_ch->max_antenna_gain = 0xff;
7b72304d 4997 geo_ch->hw_value = ch->channel;
b481de9c
ZY		 4998
4999 if (is_channel_valid(ch)) {
8318d78a
JB		 5000 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
5001 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
b481de9c 5002
8318d78a
JB		 5003 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
5004 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
b481de9c
ZY		 5005
5006 if (ch->flags & EEPROM_CHANNEL_RADAR)
8318d78a 5007 geo_ch->flags |= IEEE80211_CHAN_RADAR;
b481de9c
ZY		 5008
5009 if (ch->max_power_avg > priv->max_channel_txpower_limit)
5010 priv->max_channel_txpower_limit =
5011 ch->max_power_avg;
8211ef78 5012 } else {
8318d78a 5013 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
8211ef78
TW		 5014 }
5015
5016 /* Save flags for reg domain usage */
5017 geo_ch->orig_flags = geo_ch->flags;
5018
5019 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
5020 ch->channel, geo_ch->center_freq,
5021 is_channel_a_band(ch) ? "5.2" : "2.4",
5022 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
5023 "restricted" : "valid",
5024 geo_ch->flags);
b481de9c
ZY		 5025 }
5026
82b9a121
TW		 5027 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
5028 priv->cfg->sku & IWL_SKU_A) {
b481de9c
ZY		 5029 printk(KERN_INFO DRV_NAME
5030 ": Incorrectly detected BG card as ABG. Please send "
5031 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
5032 priv->pci_dev->device, priv->pci_dev->subsystem_device);
82b9a121 5033 priv->cfg->sku &= ~IWL_SKU_A;
b481de9c
ZY		 5034 }
5035
5036 printk(KERN_INFO DRV_NAME
5037 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
8318d78a
JB		 5038 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
5039 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
b481de9c 5040
e0e0a67e
JL		 5041 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
5042 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
5043 &priv->bands[IEEE80211_BAND_2GHZ];
5044 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
5045 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
5046 &priv->bands[IEEE80211_BAND_5GHZ];
b481de9c 5047
b481de9c
ZY		 5048 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
5049
5050 return 0;
5051}
5052
849e0dce
RC		 5053/*
5054 * iwl3945_free_geos - undo allocations in iwl3945_init_geos
5055 */
5056static void iwl3945_free_geos(struct iwl3945_priv *priv)
5057{
849e0dce
RC		 5058 kfree(priv->ieee_channels);
5059 kfree(priv->ieee_rates);
5060 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
5061}
5062
b481de9c
ZY		 5063/******************************************************************************
5064 *
5065 * uCode download functions
5066 *
5067 ******************************************************************************/
5068
bb8c093b 5069static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv)
b481de9c 5070{
98c92211
TW		 5071 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
5072 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
5073 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
5074 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
5075 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
5076 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY		 5077}
5078
5079/**
bb8c093b 5080 * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
b481de9c
ZY		 5081 * looking at all data.
5082 */
3ac7f146 5083static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 *image, u32 len)
b481de9c
ZY		 5084{
5085 u32 val;
5086 u32 save_len = len;
5087 int rc = 0;
5088 u32 errcnt;
5089
5090 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5091
bb8c093b 5092 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5093 if (rc)
5094 return rc;
5095
bb8c093b 5096 iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
b481de9c
ZY		 5097
5098 errcnt = 0;
5099 for (; len > 0; len -= sizeof(u32), image++) {
5100 /* read data comes through single port, auto-incr addr */
5101 /* NOTE: Use the debugless read so we don't flood kernel log
5102 * if IWL_DL_IO is set */
bb8c093b 5103 val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY		 5104 if (val != le32_to_cpu(*image)) {
5105 IWL_ERROR("uCode INST section is invalid at "
5106 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5107 save_len - len, val, le32_to_cpu(*image));
5108 rc = -EIO;
5109 errcnt++;
5110 if (errcnt >= 20)
5111 break;
5112 }
5113 }
5114
bb8c093b 5115 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5116
5117 if (!errcnt)
bc434dd2 5118 IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
b481de9c
ZY		 5119
5120 return rc;
5121}
5122
5123
5124/**
bb8c093b 5125 * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
b481de9c
ZY		 5126 * using sample data 100 bytes apart. If these sample points are good,
5127 * it's a pretty good bet that everything between them is good, too.
5128 */
bb8c093b 5129static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len)
b481de9c
ZY		 5130{
5131 u32 val;
5132 int rc = 0;
5133 u32 errcnt = 0;
5134 u32 i;
5135
5136 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5137
bb8c093b 5138 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5139 if (rc)
5140 return rc;
5141
5142 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
5143 /* read data comes through single port, auto-incr addr */
5144 /* NOTE: Use the debugless read so we don't flood kernel log
5145 * if IWL_DL_IO is set */
bb8c093b 5146 iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
b481de9c 5147 i + RTC_INST_LOWER_BOUND);
bb8c093b 5148 val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY		 5149 if (val != le32_to_cpu(*image)) {
5150#if 0 /* Enable this if you want to see details */
5151 IWL_ERROR("uCode INST section is invalid at "
5152 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5153 i, val, *image);
5154#endif
5155 rc = -EIO;
5156 errcnt++;
5157 if (errcnt >= 3)
5158 break;
5159 }
5160 }
5161
bb8c093b 5162 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5163
5164 return rc;
5165}
5166
5167
5168/**
bb8c093b 5169 * iwl3945_verify_ucode - determine which instruction image is in SRAM,
b481de9c
ZY		 5170 * and verify its contents
5171 */
bb8c093b 5172static int iwl3945_verify_ucode(struct iwl3945_priv *priv)
b481de9c
ZY		 5173{
5174 __le32 *image;
5175 u32 len;
5176 int rc = 0;
5177
5178 /* Try bootstrap */
5179 image = (__le32 *)priv->ucode_boot.v_addr;
5180 len = priv->ucode_boot.len;
bb8c093b 5181 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5182 if (rc == 0) {
5183 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
5184 return 0;
5185 }
5186
5187 /* Try initialize */
5188 image = (__le32 *)priv->ucode_init.v_addr;
5189 len = priv->ucode_init.len;
bb8c093b 5190 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5191 if (rc == 0) {
5192 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
5193 return 0;
5194 }
5195
5196 /* Try runtime/protocol */
5197 image = (__le32 *)priv->ucode_code.v_addr;
5198 len = priv->ucode_code.len;
bb8c093b 5199 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5200 if (rc == 0) {
5201 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
5202 return 0;
5203 }
5204
5205 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
5206
9fbab516
BC		 5207 /* Since nothing seems to match, show first several data entries in
5208 * instruction SRAM, so maybe visual inspection will give a clue.
5209 * Selection of bootstrap image (vs. other images) is arbitrary. */
b481de9c
ZY		 5210 image = (__le32 *)priv->ucode_boot.v_addr;
5211 len = priv->ucode_boot.len;
bb8c093b 5212 rc = iwl3945_verify_inst_full(priv, image, len);
b481de9c
ZY		 5213
5214 return rc;
5215}
5216
5217
5218/* check contents of special bootstrap uCode SRAM */
bb8c093b 5219static int iwl3945_verify_bsm(struct iwl3945_priv *priv)
b481de9c
ZY		 5220{
5221 __le32 *image = priv->ucode_boot.v_addr;
5222 u32 len = priv->ucode_boot.len;
5223 u32 reg;
5224 u32 val;
5225
5226 IWL_DEBUG_INFO("Begin verify bsm\n");
5227
5228 /* verify BSM SRAM contents */
bb8c093b 5229 val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG);
b481de9c
ZY		 5230 for (reg = BSM_SRAM_LOWER_BOUND;
5231 reg < BSM_SRAM_LOWER_BOUND + len;
3ac7f146 5232 reg += sizeof(u32), image++) {
bb8c093b 5233 val = iwl3945_read_prph(priv, reg);
b481de9c
ZY		 5234 if (val != le32_to_cpu(*image)) {
5235 IWL_ERROR("BSM uCode verification failed at "
5236 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
5237 BSM_SRAM_LOWER_BOUND,
5238 reg - BSM_SRAM_LOWER_BOUND, len,
5239 val, le32_to_cpu(*image));
5240 return -EIO;
5241 }
5242 }
5243
5244 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
5245
5246 return 0;
5247}
5248
5249/**
bb8c093b 5250 * iwl3945_load_bsm - Load bootstrap instructions
b481de9c
ZY		 5251 *
5252 * BSM operation:
5253 *
5254 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
5255 * in special SRAM that does not power down during RFKILL. When powering back
5256 * up after power-saving sleeps (or during initial uCode load), the BSM loads
5257 * the bootstrap program into the on-board processor, and starts it.
5258 *
5259 * The bootstrap program loads (via DMA) instructions and data for a new
5260 * program from host DRAM locations indicated by the host driver in the
5261 * BSM_DRAM_* registers. Once the new program is loaded, it starts
5262 * automatically.
5263 *
5264 * When initializing the NIC, the host driver points the BSM to the
5265 * "initialize" uCode image. This uCode sets up some internal data, then
5266 * notifies host via "initialize alive" that it is complete.
5267 *
5268 * The host then replaces the BSM_DRAM_* pointer values to point to the
5269 * normal runtime uCode instructions and a backup uCode data cache buffer
5270 * (filled initially with starting data values for the on-board processor),
5271 * then triggers the "initialize" uCode to load and launch the runtime uCode,
5272 * which begins normal operation.
5273 *
5274 * When doing a power-save shutdown, runtime uCode saves data SRAM into
5275 * the backup data cache in DRAM before SRAM is powered down.
5276 *
5277 * When powering back up, the BSM loads the bootstrap program. This reloads
5278 * the runtime uCode instructions and the backup data cache into SRAM,
5279 * and re-launches the runtime uCode from where it left off.
5280 */
bb8c093b 5281static int iwl3945_load_bsm(struct iwl3945_priv *priv)
b481de9c
ZY		 5282{
5283 __le32 *image = priv->ucode_boot.v_addr;
5284 u32 len = priv->ucode_boot.len;
5285 dma_addr_t pinst;
5286 dma_addr_t pdata;
5287 u32 inst_len;
5288 u32 data_len;
5289 int rc;
5290 int i;
5291 u32 done;
5292 u32 reg_offset;
5293
5294 IWL_DEBUG_INFO("Begin load bsm\n");
5295
5296 /* make sure bootstrap program is no larger than BSM's SRAM size */
5297 if (len > IWL_MAX_BSM_SIZE)
5298 return -EINVAL;
5299
5300 /* Tell bootstrap uCode where to find the "Initialize" uCode
9fbab516 5301 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
bb8c093b 5302 * NOTE: iwl3945_initialize_alive_start() will replace these values,
b481de9c
ZY		 5303 * after the "initialize" uCode has run, to point to
5304 * runtime/protocol instructions and backup data cache. */
5305 pinst = priv->ucode_init.p_addr;
5306 pdata = priv->ucode_init_data.p_addr;
5307 inst_len = priv->ucode_init.len;
5308 data_len = priv->ucode_init_data.len;
5309
bb8c093b 5310 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5311 if (rc)
5312 return rc;
5313
bb8c093b
CH		 5314 iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5315 iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5316 iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
5317 iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
b481de9c
ZY		 5318
5319 /* Fill BSM memory with bootstrap instructions */
5320 for (reg_offset = BSM_SRAM_LOWER_BOUND;
5321 reg_offset < BSM_SRAM_LOWER_BOUND + len;
5322 reg_offset += sizeof(u32), image++)
bb8c093b 5323 _iwl3945_write_prph(priv, reg_offset,
b481de9c
ZY		 5324 le32_to_cpu(*image));
5325
bb8c093b 5326 rc = iwl3945_verify_bsm(priv);
b481de9c 5327 if (rc) {
bb8c093b 5328 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5329 return rc;
5330 }
5331
5332 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
bb8c093b
CH		 5333 iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
5334 iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG,
b481de9c 5335 RTC_INST_LOWER_BOUND);
bb8c093b 5336 iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
b481de9c
ZY		 5337
5338 /* Load bootstrap code into instruction SRAM now,
5339 * to prepare to load "initialize" uCode */
bb8c093b 5340 iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY		 5341 BSM_WR_CTRL_REG_BIT_START);
5342
5343 /* Wait for load of bootstrap uCode to finish */
5344 for (i = 0; i < 100; i++) {
bb8c093b 5345 done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG);
b481de9c
ZY		 5346 if (!(done & BSM_WR_CTRL_REG_BIT_START))
5347 break;
5348 udelay(10);
5349 }
5350 if (i < 100)
5351 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
5352 else {
5353 IWL_ERROR("BSM write did not complete!\n");
5354 return -EIO;
5355 }
5356
5357 /* Enable future boot loads whenever power management unit triggers it
5358 * (e.g. when powering back up after power-save shutdown) */
bb8c093b 5359 iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY		 5360 BSM_WR_CTRL_REG_BIT_START_EN);
5361
bb8c093b 5362 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5363
5364 return 0;
5365}
5366
bb8c093b 5367static void iwl3945_nic_start(struct iwl3945_priv *priv)
b481de9c
ZY		 5368{
5369 /* Remove all resets to allow NIC to operate */
bb8c093b 5370 iwl3945_write32(priv, CSR_RESET, 0);
b481de9c
ZY		 5371}
5372
5373/**
bb8c093b 5374 * iwl3945_read_ucode - Read uCode images from disk file.
b481de9c
ZY		 5375 *
5376 * Copy into buffers for card to fetch via bus-mastering
5377 */
bb8c093b 5378static int iwl3945_read_ucode(struct iwl3945_priv *priv)
b481de9c 5379{
bb8c093b 5380 struct iwl3945_ucode *ucode;
90e759d1 5381 int ret = 0;
b481de9c
ZY		 5382 const struct firmware *ucode_raw;
5383 /* firmware file name contains uCode/driver compatibility version */
4bf775cd 5384 const char *name = priv->cfg->fw_name;
b481de9c
ZY		 5385 u8 *src;
5386 size_t len;
5387 u32 ver, inst_size, data_size, init_size, init_data_size, boot_size;
5388
5389 /* Ask kernel firmware_class module to get the boot firmware off disk.
5390 * request_firmware() is synchronous, file is in memory on return. */
90e759d1
TW		 5391 ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev);
5392 if (ret < 0) {
5393 IWL_ERROR("%s firmware file req failed: Reason %d\n",
5394 name, ret);
b481de9c
ZY		 5395 goto error;
5396 }
5397
5398 IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
5399 name, ucode_raw->size);
5400
5401 /* Make sure that we got at least our header! */
5402 if (ucode_raw->size < sizeof(*ucode)) {
5403 IWL_ERROR("File size way too small!\n");
90e759d1 5404 ret = -EINVAL;
b481de9c
ZY		 5405 goto err_release;
5406 }
5407
5408 /* Data from ucode file: header followed by uCode images */
5409 ucode = (void *)ucode_raw->data;
5410
5411 ver = le32_to_cpu(ucode->ver);
5412 inst_size = le32_to_cpu(ucode->inst_size);
5413 data_size = le32_to_cpu(ucode->data_size);
5414 init_size = le32_to_cpu(ucode->init_size);
5415 init_data_size = le32_to_cpu(ucode->init_data_size);
5416 boot_size = le32_to_cpu(ucode->boot_size);
5417
5418 IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver);
bc434dd2
IS		 5419 IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
5420 IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
5421 IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
5422 IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
5423 IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
b481de9c
ZY		 5424
5425 /* Verify size of file vs. image size info in file's header */
5426 if (ucode_raw->size < sizeof(*ucode) +
5427 inst_size + data_size + init_size +
5428 init_data_size + boot_size) {
5429
5430 IWL_DEBUG_INFO("uCode file size %d too small\n",
5431 (int)ucode_raw->size);
90e759d1 5432 ret = -EINVAL;
b481de9c
ZY		 5433 goto err_release;
5434 }
5435
5436 /* Verify that uCode images will fit in card's SRAM */
5437 if (inst_size > IWL_MAX_INST_SIZE) {
90e759d1
TW		 5438 IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
5439 inst_size);
5440 ret = -EINVAL;
b481de9c
ZY		 5441 goto err_release;
5442 }
5443
5444 if (data_size > IWL_MAX_DATA_SIZE) {
90e759d1
TW		 5445 IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
5446 data_size);
5447 ret = -EINVAL;
b481de9c
ZY		 5448 goto err_release;
5449 }
5450 if (init_size > IWL_MAX_INST_SIZE) {
90e759d1
TW		 5451 IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
5452 init_size);
5453 ret = -EINVAL;
b481de9c
ZY		 5454 goto err_release;
5455 }
5456 if (init_data_size > IWL_MAX_DATA_SIZE) {
90e759d1
TW		 5457 IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
5458 init_data_size);
5459 ret = -EINVAL;
b481de9c
ZY		 5460 goto err_release;
5461 }
5462 if (boot_size > IWL_MAX_BSM_SIZE) {
90e759d1
TW		 5463 IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
5464 boot_size);
5465 ret = -EINVAL;
b481de9c
ZY		 5466 goto err_release;
5467 }
5468
5469 /* Allocate ucode buffers for card's bus-master loading ... */
5470
5471 /* Runtime instructions and 2 copies of data:
5472 * 1) unmodified from disk
5473 * 2) backup cache for save/restore during power-downs */
5474 priv->ucode_code.len = inst_size;
98c92211 5475 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY		 5476
5477 priv->ucode_data.len = data_size;
98c92211 5478 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY		 5479
5480 priv->ucode_data_backup.len = data_size;
98c92211 5481 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 5482
90e759d1
TW		 5483 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
5484 !priv->ucode_data_backup.v_addr)
5485 goto err_pci_alloc;
b481de9c
ZY		 5486
5487 /* Initialization instructions and data */
90e759d1
TW		 5488 if (init_size && init_data_size) {
5489 priv->ucode_init.len = init_size;
98c92211 5490 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW		 5491
5492 priv->ucode_init_data.len = init_data_size;
98c92211 5493 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW		 5494
5495 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
5496 goto err_pci_alloc;
5497 }
b481de9c
ZY		 5498
5499 /* Bootstrap (instructions only, no data) */
90e759d1
TW		 5500 if (boot_size) {
5501 priv->ucode_boot.len = boot_size;
98c92211 5502 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 5503
90e759d1
TW		 5504 if (!priv->ucode_boot.v_addr)
5505 goto err_pci_alloc;
5506 }
b481de9c
ZY		 5507
5508 /* Copy images into buffers for card's bus-master reads ... */
5509
5510 /* Runtime instructions (first block of data in file) */
5511 src = &ucode->data[0];
5512 len = priv->ucode_code.len;
90e759d1 5513 IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c
ZY		 5514 memcpy(priv->ucode_code.v_addr, src, len);
5515 IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
5516 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
5517
5518 /* Runtime data (2nd block)
bb8c093b 5519 * NOTE: Copy into backup buffer will be done in iwl3945_up() */
b481de9c
ZY		 5520 src = &ucode->data[inst_size];
5521 len = priv->ucode_data.len;
90e759d1 5522 IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY		 5523 memcpy(priv->ucode_data.v_addr, src, len);
5524 memcpy(priv->ucode_data_backup.v_addr, src, len);
5525
5526 /* Initialization instructions (3rd block) */
5527 if (init_size) {
5528 src = &ucode->data[inst_size + data_size];
5529 len = priv->ucode_init.len;
90e759d1
TW		 5530 IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
5531 len);
b481de9c
ZY		 5532 memcpy(priv->ucode_init.v_addr, src, len);
5533 }
5534
5535 /* Initialization data (4th block) */
5536 if (init_data_size) {
5537 src = &ucode->data[inst_size + data_size + init_size];
5538 len = priv->ucode_init_data.len;
5539 IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
5540 (int)len);
5541 memcpy(priv->ucode_init_data.v_addr, src, len);
5542 }
5543
5544 /* Bootstrap instructions (5th block) */
5545 src = &ucode->data[inst_size + data_size + init_size + init_data_size];
5546 len = priv->ucode_boot.len;
5547 IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
5548 (int)len);
5549 memcpy(priv->ucode_boot.v_addr, src, len);
5550
5551 /* We have our copies now, allow OS release its copies */
5552 release_firmware(ucode_raw);
5553 return 0;
5554
5555 err_pci_alloc:
5556 IWL_ERROR("failed to allocate pci memory\n");
90e759d1 5557 ret = -ENOMEM;
bb8c093b 5558 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY		 5559
5560 err_release:
5561 release_firmware(ucode_raw);
5562
5563 error:
90e759d1 5564 return ret;
b481de9c
ZY		 5565}
5566
5567
5568/**
bb8c093b 5569 * iwl3945_set_ucode_ptrs - Set uCode address location
b481de9c
ZY		 5570 *
5571 * Tell initialization uCode where to find runtime uCode.
5572 *
5573 * BSM registers initially contain pointers to initialization uCode.
5574 * We need to replace them to load runtime uCode inst and data,
5575 * and to save runtime data when powering down.
5576 */
bb8c093b 5577static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv)
b481de9c
ZY		 5578{
5579 dma_addr_t pinst;
5580 dma_addr_t pdata;
5581 int rc = 0;
5582 unsigned long flags;
5583
5584 /* bits 31:0 for 3945 */
5585 pinst = priv->ucode_code.p_addr;
5586 pdata = priv->ucode_data_backup.p_addr;
5587
5588 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5589 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5590 if (rc) {
5591 spin_unlock_irqrestore(&priv->lock, flags);
5592 return rc;
5593 }
5594
5595 /* Tell bootstrap uCode where to find image to load */
bb8c093b
CH		 5596 iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5597 iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5598 iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
b481de9c
ZY		 5599 priv->ucode_data.len);
5600
5601 /* Inst bytecount must be last to set up, bit 31 signals uCode
5602 * that all new ptr/size info is in place */
bb8c093b 5603 iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
b481de9c
ZY		 5604 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
5605
bb8c093b 5606 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5607
5608 spin_unlock_irqrestore(&priv->lock, flags);
5609
5610 IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
5611
5612 return rc;
5613}
5614
5615/**
bb8c093b 5616 * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
b481de9c
ZY		 5617 *
5618 * Called after REPLY_ALIVE notification received from "initialize" uCode.
5619 *
b481de9c 5620 * Tell "initialize" uCode to go ahead and load the runtime uCode.
9fbab516 5621 */
bb8c093b 5622static void iwl3945_init_alive_start(struct iwl3945_priv *priv)
b481de9c
ZY		 5623{
5624 /* Check alive response for "valid" sign from uCode */
5625 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
5626 /* We had an error bringing up the hardware, so take it
5627 * all the way back down so we can try again */
5628 IWL_DEBUG_INFO("Initialize Alive failed.\n");
5629 goto restart;
5630 }
5631
5632 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
5633 * This is a paranoid check, because we would not have gotten the
5634 * "initialize" alive if code weren't properly loaded. */
bb8c093b 5635 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY		 5636 /* Runtime instruction load was bad;
5637 * take it all the way back down so we can try again */
5638 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
5639 goto restart;
5640 }
5641
5642 /* Send pointers to protocol/runtime uCode image ... init code will
5643 * load and launch runtime uCode, which will send us another "Alive"
5644 * notification. */
5645 IWL_DEBUG_INFO("Initialization Alive received.\n");
bb8c093b 5646 if (iwl3945_set_ucode_ptrs(priv)) {
b481de9c
ZY		 5647 /* Runtime instruction load won't happen;
5648 * take it all the way back down so we can try again */
5649 IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
5650 goto restart;
5651 }
5652 return;
5653
5654 restart:
5655 queue_work(priv->workqueue, &priv->restart);
5656}
5657
5658
5659/**
bb8c093b 5660 * iwl3945_alive_start - called after REPLY_ALIVE notification received
b481de9c 5661 * from protocol/runtime uCode (initialization uCode's
bb8c093b 5662 * Alive gets handled by iwl3945_init_alive_start()).
b481de9c 5663 */
bb8c093b 5664static void iwl3945_alive_start(struct iwl3945_priv *priv)
b481de9c
ZY		 5665{
5666 int rc = 0;
5667 int thermal_spin = 0;
5668 u32 rfkill;
5669
5670 IWL_DEBUG_INFO("Runtime Alive received.\n");
5671
5672 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
5673 /* We had an error bringing up the hardware, so take it
5674 * all the way back down so we can try again */
5675 IWL_DEBUG_INFO("Alive failed.\n");
5676 goto restart;
5677 }
5678
5679 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
5680 * This is a paranoid check, because we would not have gotten the
5681 * "runtime" alive if code weren't properly loaded. */
bb8c093b 5682 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY		 5683 /* Runtime instruction load was bad;
5684 * take it all the way back down so we can try again */
5685 IWL_DEBUG_INFO("Bad runtime uCode load.\n");
5686 goto restart;
5687 }
5688
bb8c093b 5689 iwl3945_clear_stations_table(priv);
b481de9c 5690
bb8c093b 5691 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5692 if (rc) {
5693 IWL_WARNING("Can not read rfkill status from adapter\n");
5694 return;
5695 }
5696
bb8c093b 5697 rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG);
b481de9c 5698 IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
bb8c093b 5699 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5700
5701 if (rfkill & 0x1) {
5702 clear_bit(STATUS_RF_KILL_HW, &priv->status);
5703 /* if rfkill is not on, then wait for thermal
5704 * sensor in adapter to kick in */
bb8c093b 5705 while (iwl3945_hw_get_temperature(priv) == 0) {
b481de9c
ZY		 5706 thermal_spin++;
5707 udelay(10);
5708 }
5709
5710 if (thermal_spin)
5711 IWL_DEBUG_INFO("Thermal calibration took %dus\n",
5712 thermal_spin * 10);
5713 } else
5714 set_bit(STATUS_RF_KILL_HW, &priv->status);
5715
9fbab516 5716 /* After the ALIVE response, we can send commands to 3945 uCode */
b481de9c
ZY		 5717 set_bit(STATUS_ALIVE, &priv->status);
5718
5719 /* Clear out the uCode error bit if it is set */
5720 clear_bit(STATUS_FW_ERROR, &priv->status);
5721
bb8c093b 5722 if (iwl3945_is_rfkill(priv))
b481de9c
ZY		 5723 return;
5724
36d6825b 5725 ieee80211_wake_queues(priv->hw);
b481de9c
ZY		 5726
5727 priv->active_rate = priv->rates_mask;
5728 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
5729
bb8c093b 5730 iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
b481de9c 5731
bb8c093b
CH		 5732 if (iwl3945_is_associated(priv)) {
5733 struct iwl3945_rxon_cmd *active_rxon =
5734 (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
b481de9c
ZY		 5735
5736 memcpy(&priv->staging_rxon, &priv->active_rxon,
5737 sizeof(priv->staging_rxon));
5738 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5739 } else {
5740 /* Initialize our rx_config data */
bb8c093b 5741 iwl3945_connection_init_rx_config(priv);
b481de9c
ZY		 5742 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
5743 }
5744
9fbab516 5745 /* Configure Bluetooth device coexistence support */
bb8c093b 5746 iwl3945_send_bt_config(priv);
b481de9c
ZY		 5747
5748 /* Configure the adapter for unassociated operation */
bb8c093b 5749 iwl3945_commit_rxon(priv);
b481de9c 5750
b481de9c
ZY		 5751 iwl3945_reg_txpower_periodic(priv);
5752
fe00b5a5
RC		 5753 iwl3945_led_register(priv);
5754
b481de9c 5755 IWL_DEBUG_INFO("ALIVE processing complete.\n");
a9f46786 5756 set_bit(STATUS_READY, &priv->status);
5a66926a 5757 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY		 5758
5759 if (priv->error_recovering)
bb8c093b 5760 iwl3945_error_recovery(priv);
b481de9c 5761
84363e6e 5762 ieee80211_notify_mac(priv->hw, IEEE80211_NOTIFY_RE_ASSOC);
b481de9c
ZY		 5763 return;
5764
5765 restart:
5766 queue_work(priv->workqueue, &priv->restart);
5767}
5768
bb8c093b 5769static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv);
b481de9c 5770
bb8c093b 5771static void __iwl3945_down(struct iwl3945_priv *priv)
b481de9c
ZY		 5772{
5773 unsigned long flags;
5774 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
5775 struct ieee80211_conf *conf = NULL;
5776
5777 IWL_DEBUG_INFO(DRV_NAME " is going down\n");
5778
5779 conf = ieee80211_get_hw_conf(priv->hw);
5780
5781 if (!exit_pending)
5782 set_bit(STATUS_EXIT_PENDING, &priv->status);
5783
ab53d8af 5784 iwl3945_led_unregister(priv);
bb8c093b 5785 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 5786
5787 /* Unblock any waiting calls */
5788 wake_up_interruptible_all(&priv->wait_command_queue);
5789
b481de9c
ZY		 5790 /* Wipe out the EXIT_PENDING status bit if we are not actually
5791 * exiting the module */
5792 if (!exit_pending)
5793 clear_bit(STATUS_EXIT_PENDING, &priv->status);
5794
5795 /* stop and reset the on-board processor */
bb8c093b 5796 iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY		 5797
5798 /* tell the device to stop sending interrupts */
0359facc 5799 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5800 iwl3945_disable_interrupts(priv);
0359facc
MA		 5801 spin_unlock_irqrestore(&priv->lock, flags);
5802 iwl_synchronize_irq(priv);
b481de9c
ZY		 5803
5804 if (priv->mac80211_registered)
5805 ieee80211_stop_queues(priv->hw);
5806
bb8c093b 5807 /* If we have not previously called iwl3945_init() then
b481de9c 5808 * clear all bits but the RF Kill and SUSPEND bits and return */
bb8c093b 5809 if (!iwl3945_is_init(priv)) {
b481de9c
ZY		 5810 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
5811 STATUS_RF_KILL_HW |
5812 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
5813 STATUS_RF_KILL_SW |
9788864e
RC		 5814 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
5815 STATUS_GEO_CONFIGURED |
b481de9c 5816 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
ebef2008
AK		 5817 STATUS_IN_SUSPEND |
5818 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
5819 STATUS_EXIT_PENDING;
b481de9c
ZY		 5820 goto exit;
5821 }
5822
5823 /* ...otherwise clear out all the status bits but the RF Kill and
5824 * SUSPEND bits and continue taking the NIC down. */
5825 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
5826 STATUS_RF_KILL_HW |
5827 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
5828 STATUS_RF_KILL_SW |
9788864e
RC		 5829 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
5830 STATUS_GEO_CONFIGURED |
b481de9c
ZY		 5831 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
5832 STATUS_IN_SUSPEND |
5833 test_bit(STATUS_FW_ERROR, &priv->status) <<
ebef2008
AK		 5834 STATUS_FW_ERROR |
5835 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
5836 STATUS_EXIT_PENDING;
b481de9c
ZY		 5837
5838 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5839 iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY		 5840 spin_unlock_irqrestore(&priv->lock, flags);
5841
bb8c093b
CH		 5842 iwl3945_hw_txq_ctx_stop(priv);
5843 iwl3945_hw_rxq_stop(priv);
b481de9c
ZY		 5844
5845 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH		 5846 if (!iwl3945_grab_nic_access(priv)) {
5847 iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
b481de9c 5848 APMG_CLK_VAL_DMA_CLK_RQT);
bb8c093b 5849 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5850 }
5851 spin_unlock_irqrestore(&priv->lock, flags);
5852
5853 udelay(5);
5854
bb8c093b
CH		 5855 iwl3945_hw_nic_stop_master(priv);
5856 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
5857 iwl3945_hw_nic_reset(priv);
b481de9c
ZY		 5858
5859 exit:
bb8c093b 5860 memset(&priv->card_alive, 0, sizeof(struct iwl3945_alive_resp));
b481de9c
ZY		 5861
5862 if (priv->ibss_beacon)
5863 dev_kfree_skb(priv->ibss_beacon);
5864 priv->ibss_beacon = NULL;
5865
5866 /* clear out any free frames */
bb8c093b 5867 iwl3945_clear_free_frames(priv);
b481de9c
ZY		 5868}
5869
bb8c093b 5870static void iwl3945_down(struct iwl3945_priv *priv)
b481de9c
ZY		 5871{
5872 mutex_lock(&priv->mutex);
bb8c093b 5873 __iwl3945_down(priv);
b481de9c 5874 mutex_unlock(&priv->mutex);
b24d22b1 5875
bb8c093b 5876 iwl3945_cancel_deferred_work(priv);
b481de9c
ZY		 5877}
5878
5879#define MAX_HW_RESTARTS 5
5880
bb8c093b 5881static int __iwl3945_up(struct iwl3945_priv *priv)
b481de9c
ZY		 5882{
5883 int rc, i;
5884
5885 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
5886 IWL_WARNING("Exit pending; will not bring the NIC up\n");
5887 return -EIO;
5888 }
5889
5890 if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
5891 IWL_WARNING("Radio disabled by SW RF kill (module "
5892 "parameter)\n");
e655b9f0
ZY		 5893 return -ENODEV;
5894 }
5895
e903fbd4
RC		 5896 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
5897 IWL_ERROR("ucode not available for device bringup\n");
5898 return -EIO;
5899 }
5900
e655b9f0
ZY		 5901 /* If platform's RF_KILL switch is NOT set to KILL */
5902 if (iwl3945_read32(priv, CSR_GP_CNTRL) &
5903 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
5904 clear_bit(STATUS_RF_KILL_HW, &priv->status);
5905 else {
5906 set_bit(STATUS_RF_KILL_HW, &priv->status);
5907 if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
5908 IWL_WARNING("Radio disabled by HW RF Kill switch\n");
5909 return -ENODEV;
5910 }
b481de9c 5911 }
80fcc9e2 5912
bb8c093b 5913 iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 5914
bb8c093b 5915 rc = iwl3945_hw_nic_init(priv);
b481de9c
ZY		 5916 if (rc) {
5917 IWL_ERROR("Unable to int nic\n");
5918 return rc;
5919 }
5920
5921 /* make sure rfkill handshake bits are cleared */
bb8c093b
CH		 5922 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5923 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 5924 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
5925
5926 /* clear (again), then enable host interrupts */
bb8c093b
CH		 5927 iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
5928 iwl3945_enable_interrupts(priv);
b481de9c
ZY		 5929
5930 /* really make sure rfkill handshake bits are cleared */
bb8c093b
CH		 5931 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5932 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 5933
5934 /* Copy original ucode data image from disk into backup cache.
5935 * This will be used to initialize the on-board processor's
5936 * data SRAM for a clean start when the runtime program first loads. */
5937 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 5938 priv->ucode_data.len);
b481de9c 5939
e655b9f0
ZY		 5940 /* We return success when we resume from suspend and rf_kill is on. */
5941 if (test_bit(STATUS_RF_KILL_HW, &priv->status))
5942 return 0;
5943
b481de9c
ZY		 5944 for (i = 0; i < MAX_HW_RESTARTS; i++) {
5945
bb8c093b 5946 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 5947
5948 /* load bootstrap state machine,
5949 * load bootstrap program into processor's memory,
5950 * prepare to load the "initialize" uCode */
bb8c093b 5951 rc = iwl3945_load_bsm(priv);
b481de9c
ZY		 5952
5953 if (rc) {
5954 IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
5955 continue;
5956 }
5957
5958 /* start card; "initialize" will load runtime ucode */
bb8c093b 5959 iwl3945_nic_start(priv);
b481de9c 5960
b481de9c
ZY		 5961 IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
5962
5963 return 0;
5964 }
5965
5966 set_bit(STATUS_EXIT_PENDING, &priv->status);
bb8c093b 5967 __iwl3945_down(priv);
ebef2008 5968 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY		 5969
5970 /* tried to restart and config the device for as long as our
5971 * patience could withstand */
5972 IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
5973 return -EIO;
5974}
5975
5976
5977/*****************************************************************************
5978 *
5979 * Workqueue callbacks
5980 *
5981 *****************************************************************************/
5982
bb8c093b 5983static void iwl3945_bg_init_alive_start(struct work_struct *data)
b481de9c 5984{
bb8c093b
CH		 5985 struct iwl3945_priv *priv =
5986 container_of(data, struct iwl3945_priv, init_alive_start.work);
b481de9c
ZY		 5987
5988 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5989 return;
5990
5991 mutex_lock(&priv->mutex);
bb8c093b 5992 iwl3945_init_alive_start(priv);
b481de9c
ZY		 5993 mutex_unlock(&priv->mutex);
5994}
5995
bb8c093b 5996static void iwl3945_bg_alive_start(struct work_struct *data)
b481de9c 5997{
bb8c093b
CH		 5998 struct iwl3945_priv *priv =
5999 container_of(data, struct iwl3945_priv, alive_start.work);
b481de9c
ZY		 6000
6001 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6002 return;
6003
6004 mutex_lock(&priv->mutex);
bb8c093b 6005 iwl3945_alive_start(priv);
b481de9c
ZY		 6006 mutex_unlock(&priv->mutex);
6007}
6008
bb8c093b 6009static void iwl3945_bg_rf_kill(struct work_struct *work)
b481de9c 6010{
bb8c093b 6011 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill);
b481de9c
ZY		 6012
6013 wake_up_interruptible(&priv->wait_command_queue);
6014
6015 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6016 return;
6017
6018 mutex_lock(&priv->mutex);
6019
bb8c093b 6020 if (!iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 6021 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
6022 "HW and/or SW RF Kill no longer active, restarting "
6023 "device\n");
6024 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
6025 queue_work(priv->workqueue, &priv->restart);
6026 } else {
6027
6028 if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
6029 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
6030 "disabled by SW switch\n");
6031 else
6032 IWL_WARNING("Radio Frequency Kill Switch is On:\n"
6033 "Kill switch must be turned off for "
6034 "wireless networking to work.\n");
6035 }
ebef2008 6036
b481de9c 6037 mutex_unlock(&priv->mutex);
80fcc9e2 6038 iwl3945_rfkill_set_hw_state(priv);
b481de9c
ZY		 6039}
6040
5ec03976
AK		 6041static void iwl3945_bg_set_monitor(struct work_struct *work)
6042{
6043 struct iwl3945_priv *priv = container_of(work,
6044 struct iwl3945_priv, set_monitor);
6045
6046 IWL_DEBUG(IWL_DL_STATE, "setting monitor mode\n");
6047
6048 mutex_lock(&priv->mutex);
6049
6050 if (!iwl3945_is_ready(priv))
6051 IWL_DEBUG(IWL_DL_STATE, "leave - not ready\n");
6052 else
05c914fe 6053 if (iwl3945_set_mode(priv, NL80211_IFTYPE_MONITOR) != 0)
5ec03976
AK		 6054 IWL_ERROR("iwl3945_set_mode() failed\n");
6055
6056 mutex_unlock(&priv->mutex);
6057}
6058
b481de9c
ZY		 6059#define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
6060
bb8c093b 6061static void iwl3945_bg_scan_check(struct work_struct *data)
b481de9c 6062{
bb8c093b
CH		 6063 struct iwl3945_priv *priv =
6064 container_of(data, struct iwl3945_priv, scan_check.work);
b481de9c
ZY		 6065
6066 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6067 return;
6068
6069 mutex_lock(&priv->mutex);
6070 if (test_bit(STATUS_SCANNING, &priv->status) ||
6071 test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6072 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
6073 "Scan completion watchdog resetting adapter (%dms)\n",
6074 jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
15e869d8 6075
b481de9c 6076 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
bb8c093b 6077 iwl3945_send_scan_abort(priv);
b481de9c
ZY		 6078 }
6079 mutex_unlock(&priv->mutex);
6080}
6081
bb8c093b 6082static void iwl3945_bg_request_scan(struct work_struct *data)
b481de9c 6083{
bb8c093b
CH		 6084 struct iwl3945_priv *priv =
6085 container_of(data, struct iwl3945_priv, request_scan);
6086 struct iwl3945_host_cmd cmd = {
b481de9c 6087 .id = REPLY_SCAN_CMD,
bb8c093b 6088 .len = sizeof(struct iwl3945_scan_cmd),
b481de9c
ZY		 6089 .meta.flags = CMD_SIZE_HUGE,
6090 };
6091 int rc = 0;
bb8c093b 6092 struct iwl3945_scan_cmd *scan;
b481de9c 6093 struct ieee80211_conf *conf = NULL;
f9340520 6094 u8 n_probes = 2;
8318d78a 6095 enum ieee80211_band band;
b481de9c
ZY		 6096
6097 conf = ieee80211_get_hw_conf(priv->hw);
6098
6099 mutex_lock(&priv->mutex);
6100
bb8c093b 6101 if (!iwl3945_is_ready(priv)) {
b481de9c
ZY		 6102 IWL_WARNING("request scan called when driver not ready.\n");
6103 goto done;
6104 }
6105
6106 /* Make sure the scan wasn't cancelled before this queued work
6107 * was given the chance to run... */
6108 if (!test_bit(STATUS_SCANNING, &priv->status))
6109 goto done;
6110
6111 /* This should never be called or scheduled if there is currently
6112 * a scan active in the hardware. */
6113 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
6114 IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
6115 "Ignoring second request.\n");
6116 rc = -EIO;
6117 goto done;
6118 }
6119
6120 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
6121 IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
6122 goto done;
6123 }
6124
6125 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6126 IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
6127 goto done;
6128 }
6129
bb8c093b 6130 if (iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 6131 IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
6132 goto done;
6133 }
6134
6135 if (!test_bit(STATUS_READY, &priv->status)) {
6136 IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
6137 goto done;
6138 }
6139
6140 if (!priv->scan_bands) {
6141 IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
6142 goto done;
6143 }
6144
6145 if (!priv->scan) {
bb8c093b 6146 priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
b481de9c
ZY		 6147 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
6148 if (!priv->scan) {
6149 rc = -ENOMEM;
6150 goto done;
6151 }
6152 }
6153 scan = priv->scan;
bb8c093b 6154 memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
b481de9c
ZY		 6155
6156 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
6157 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
6158
bb8c093b 6159 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 6160 u16 interval = 0;
6161 u32 extra;
6162 u32 suspend_time = 100;
6163 u32 scan_suspend_time = 100;
6164 unsigned long flags;
6165
6166 IWL_DEBUG_INFO("Scanning while associated...\n");
6167
6168 spin_lock_irqsave(&priv->lock, flags);
6169 interval = priv->beacon_int;
6170 spin_unlock_irqrestore(&priv->lock, flags);
6171
6172 scan->suspend_time = 0;
15e869d8 6173 scan->max_out_time = cpu_to_le32(200 * 1024);
b481de9c
ZY		 6174 if (!interval)
6175 interval = suspend_time;
6176 /*
6177 * suspend time format:
6178 * 0-19: beacon interval in usec (time before exec.)
6179 * 20-23: 0
6180 * 24-31: number of beacons (suspend between channels)
6181 */
6182
6183 extra = (suspend_time / interval) << 24;
6184 scan_suspend_time = 0xFF0FFFFF &
6185 (extra | ((suspend_time % interval) * 1024));
6186
6187 scan->suspend_time = cpu_to_le32(scan_suspend_time);
6188 IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
6189 scan_suspend_time, interval);
6190 }
6191
6192 /* We should add the ability for user to lock to PASSIVE ONLY */
6193 if (priv->one_direct_scan) {
6194 IWL_DEBUG_SCAN
6195 ("Kicking off one direct scan for '%s'\n",
bb8c093b 6196 iwl3945_escape_essid(priv->direct_ssid,
b481de9c
ZY		 6197 priv->direct_ssid_len));
6198 scan->direct_scan[0].id = WLAN_EID_SSID;
6199 scan->direct_scan[0].len = priv->direct_ssid_len;
6200 memcpy(scan->direct_scan[0].ssid,
6201 priv->direct_ssid, priv->direct_ssid_len);
f9340520 6202 n_probes++;
bb8c093b 6203 } else if (!iwl3945_is_associated(priv) && priv->essid_len) {
786b4557
BM		 6204 IWL_DEBUG_SCAN
6205 ("Kicking off one direct scan for '%s' when not associated\n",
6206 iwl3945_escape_essid(priv->essid, priv->essid_len));
b481de9c
ZY		 6207 scan->direct_scan[0].id = WLAN_EID_SSID;
6208 scan->direct_scan[0].len = priv->essid_len;
6209 memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len);
f9340520
AK		 6210 n_probes++;
6211 } else
786b4557 6212 IWL_DEBUG_SCAN("Kicking off one indirect scan.\n");
b481de9c
ZY		 6213
6214 /* We don't build a direct scan probe request; the uCode will do
6215 * that based on the direct_mask added to each channel entry */
6216 scan->tx_cmd.len = cpu_to_le16(
bb8c093b 6217 iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
18904f58 6218 IWL_MAX_SCAN_SIZE - sizeof(*scan), 0));
b481de9c
ZY		 6219 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
6220 scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
6221 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
6222
6223 /* flags + rate selection */
6224
66b5004d 6225 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
b481de9c
ZY		 6226 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
6227 scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
6228 scan->good_CRC_th = 0;
8318d78a 6229 band = IEEE80211_BAND_2GHZ;
66b5004d 6230 } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
b481de9c
ZY		 6231 scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
6232 scan->good_CRC_th = IWL_GOOD_CRC_TH;
8318d78a 6233 band = IEEE80211_BAND_5GHZ;
66b5004d 6234 } else {
b481de9c
ZY		 6235 IWL_WARNING("Invalid scan band count\n");
6236 goto done;
6237 }
6238
6239 /* select Rx antennas */
6240 scan->flags |= iwl3945_get_antenna_flags(priv);
6241
05c914fe 6242 if (priv->iw_mode == NL80211_IFTYPE_MONITOR)
b481de9c
ZY		 6243 scan->filter_flags = RXON_FILTER_PROMISC_MSK;
6244
f9340520
AK		 6245 scan->channel_count =
6246 iwl3945_get_channels_for_scan(priv, band, 1, /* active */
6247 n_probes,
6248 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
b481de9c
ZY		 6249
6250 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
bb8c093b 6251 scan->channel_count * sizeof(struct iwl3945_scan_channel);
b481de9c
ZY		 6252 cmd.data = scan;
6253 scan->len = cpu_to_le16(cmd.len);
6254
6255 set_bit(STATUS_SCAN_HW, &priv->status);
bb8c093b 6256 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 6257 if (rc)
6258 goto done;
6259
6260 queue_delayed_work(priv->workqueue, &priv->scan_check,
6261 IWL_SCAN_CHECK_WATCHDOG);
6262
6263 mutex_unlock(&priv->mutex);
6264 return;
6265
6266 done:
01ebd063 6267 /* inform mac80211 scan aborted */
b481de9c
ZY		 6268 queue_work(priv->workqueue, &priv->scan_completed);
6269 mutex_unlock(&priv->mutex);
6270}
6271
bb8c093b 6272static void iwl3945_bg_up(struct work_struct *data)
b481de9c 6273{
bb8c093b 6274 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up);
b481de9c
ZY		 6275
6276 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6277 return;
6278
6279 mutex_lock(&priv->mutex);
bb8c093b 6280 __iwl3945_up(priv);
b481de9c 6281 mutex_unlock(&priv->mutex);
80fcc9e2 6282 iwl3945_rfkill_set_hw_state(priv);
b481de9c
ZY		 6283}
6284
bb8c093b 6285static void iwl3945_bg_restart(struct work_struct *data)
b481de9c 6286{
bb8c093b 6287 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart);
b481de9c
ZY		 6288
6289 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6290 return;
6291
bb8c093b 6292 iwl3945_down(priv);
b481de9c
ZY		 6293 queue_work(priv->workqueue, &priv->up);
6294}
6295
bb8c093b 6296static void iwl3945_bg_rx_replenish(struct work_struct *data)
b481de9c 6297{
bb8c093b
CH		 6298 struct iwl3945_priv *priv =
6299 container_of(data, struct iwl3945_priv, rx_replenish);
b481de9c
ZY		 6300
6301 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6302 return;
6303
6304 mutex_lock(&priv->mutex);
bb8c093b 6305 iwl3945_rx_replenish(priv);
b481de9c
ZY		 6306 mutex_unlock(&priv->mutex);
6307}
6308
7878a5a4
MA		 6309#define IWL_DELAY_NEXT_SCAN (HZ*2)
6310
cd56d331 6311static void iwl3945_post_associate(struct iwl3945_priv *priv)
b481de9c 6312{
b481de9c
ZY		 6313 int rc = 0;
6314 struct ieee80211_conf *conf = NULL;
6315
05c914fe 6316 if (priv->iw_mode == NL80211_IFTYPE_AP) {
3ac7f146 6317 IWL_ERROR("%s Should not be called in AP mode\n", __func__);
b481de9c
ZY		 6318 return;
6319 }
6320
6321
e174961c
JB		 6322 IWL_DEBUG_ASSOC("Associated as %d to: %pM\n",
6323 priv->assoc_id, priv->active_rxon.bssid_addr);
b481de9c
ZY		 6324
6325 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6326 return;
6327
322a9811 6328 if (!priv->vif || !priv->is_open)
6ef89d0a 6329 return;
322a9811 6330
bb8c093b 6331 iwl3945_scan_cancel_timeout(priv, 200);
15e869d8 6332
b481de9c
ZY		 6333 conf = ieee80211_get_hw_conf(priv->hw);
6334
6335 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6336 iwl3945_commit_rxon(priv);
b481de9c 6337
bb8c093b
CH		 6338 memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
6339 iwl3945_setup_rxon_timing(priv);
6340 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY		 6341 sizeof(priv->rxon_timing), &priv->rxon_timing);
6342 if (rc)
6343 IWL_WARNING("REPLY_RXON_TIMING failed - "
6344 "Attempting to continue.\n");
6345
6346 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
6347
6348 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
6349
6350 IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
6351 priv->assoc_id, priv->beacon_int);
6352
6353 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
6354 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
6355 else
6356 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
6357
6358 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
6359 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
6360 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
6361 else
6362 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
6363
05c914fe 6364 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY		 6365 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
6366
6367 }
6368
bb8c093b 6369 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6370
6371 switch (priv->iw_mode) {
05c914fe 6372 case NL80211_IFTYPE_STATION:
bb8c093b 6373 iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
b481de9c
ZY		 6374 break;
6375
05c914fe 6376 case NL80211_IFTYPE_ADHOC:
b481de9c
ZY		 6377
6378 /* clear out the station table */
bb8c093b 6379 iwl3945_clear_stations_table(priv);
b481de9c 6380
bb8c093b
CH		 6381 iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
6382 iwl3945_add_station(priv, priv->bssid, 0, 0);
b481de9c 6383 iwl3945_sync_sta(priv, IWL_STA_ID,
8318d78a 6384 (priv->band == IEEE80211_BAND_5GHZ) ?
b481de9c
ZY		 6385 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
6386 CMD_ASYNC);
bb8c093b
CH		 6387 iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
6388 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 6389
6390 break;
6391
6392 default:
6393 IWL_ERROR("%s Should not be called in %d mode\n",
3ac7f146 6394 __func__, priv->iw_mode);
b481de9c
ZY		 6395 break;
6396 }
6397
bb8c093b 6398 iwl3945_activate_qos(priv, 0);
292ae174 6399
7878a5a4
MA		 6400 /* we have just associated, don't start scan too early */
6401 priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
cd56d331
AK		 6402}
6403
bb8c093b 6404static void iwl3945_bg_abort_scan(struct work_struct *work)
b481de9c 6405{
bb8c093b 6406 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan);
b481de9c 6407
bb8c093b 6408 if (!iwl3945_is_ready(priv))
b481de9c
ZY		 6409 return;
6410
6411 mutex_lock(&priv->mutex);
6412
6413 set_bit(STATUS_SCAN_ABORTING, &priv->status);
bb8c093b 6414 iwl3945_send_scan_abort(priv);
b481de9c
ZY		 6415
6416 mutex_unlock(&priv->mutex);
6417}
6418
e8975581 6419static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed);
76bb77e0 6420
bb8c093b 6421static void iwl3945_bg_scan_completed(struct work_struct *work)
b481de9c 6422{
bb8c093b
CH		 6423 struct iwl3945_priv *priv =
6424 container_of(work, struct iwl3945_priv, scan_completed);
b481de9c
ZY		 6425
6426 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
6427
6428 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6429 return;
6430
a0646470 6431 if (test_bit(STATUS_CONF_PENDING, &priv->status))
e8975581 6432 iwl3945_mac_config(priv->hw, 0);
76bb77e0 6433
b481de9c
ZY		 6434 ieee80211_scan_completed(priv->hw);
6435
6436 /* Since setting the TXPOWER may have been deferred while
6437 * performing the scan, fire one off */
6438 mutex_lock(&priv->mutex);
bb8c093b 6439 iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 6440 mutex_unlock(&priv->mutex);
6441}
6442
6443/*****************************************************************************
6444 *
6445 * mac80211 entry point functions
6446 *
6447 *****************************************************************************/
6448
5a66926a
ZY		 6449#define UCODE_READY_TIMEOUT (2 * HZ)
6450
bb8c093b 6451static int iwl3945_mac_start(struct ieee80211_hw *hw)
b481de9c 6452{
bb8c093b 6453 struct iwl3945_priv *priv = hw->priv;
5a66926a 6454 int ret;
b481de9c
ZY		 6455
6456 IWL_DEBUG_MAC80211("enter\n");
6457
5a66926a
ZY		 6458 if (pci_enable_device(priv->pci_dev)) {
6459 IWL_ERROR("Fail to pci_enable_device\n");
6460 return -ENODEV;
6461 }
6462 pci_restore_state(priv->pci_dev);
6463 pci_enable_msi(priv->pci_dev);
6464
6465 ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
6466 DRV_NAME, priv);
6467 if (ret) {
6468 IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq);
6469 goto out_disable_msi;
6470 }
6471
b481de9c
ZY		 6472 /* we should be verifying the device is ready to be opened */
6473 mutex_lock(&priv->mutex);
6474
5a66926a
ZY		 6475 memset(&priv->staging_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
6476 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
6477 * ucode filename and max sizes are card-specific. */
6478
6479 if (!priv->ucode_code.len) {
6480 ret = iwl3945_read_ucode(priv);
6481 if (ret) {
6482 IWL_ERROR("Could not read microcode: %d\n", ret);
6483 mutex_unlock(&priv->mutex);
6484 goto out_release_irq;
6485 }
6486 }
b481de9c 6487
e655b9f0 6488 ret = __iwl3945_up(priv);
b481de9c
ZY		 6489
6490 mutex_unlock(&priv->mutex);
5a66926a 6491
80fcc9e2
AG		 6492 iwl3945_rfkill_set_hw_state(priv);
6493
e655b9f0
ZY		 6494 if (ret)
6495 goto out_release_irq;
6496
6497 IWL_DEBUG_INFO("Start UP work.\n");
6498
6499 if (test_bit(STATUS_IN_SUSPEND, &priv->status))
6500 return 0;
6501
5a66926a
ZY		 6502 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
6503 * mac80211 will not be run successfully. */
6504 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
6505 test_bit(STATUS_READY, &priv->status),
6506 UCODE_READY_TIMEOUT);
6507 if (!ret) {
6508 if (!test_bit(STATUS_READY, &priv->status)) {
6509 IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n",
6510 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6511 ret = -ETIMEDOUT;
6512 goto out_release_irq;
6513 }
6514 }
6515
e655b9f0 6516 priv->is_open = 1;
b481de9c
ZY		 6517 IWL_DEBUG_MAC80211("leave\n");
6518 return 0;
5a66926a
ZY		 6519
6520out_release_irq:
6521 free_irq(priv->pci_dev->irq, priv);
6522out_disable_msi:
6523 pci_disable_msi(priv->pci_dev);
e655b9f0
ZY		 6524 pci_disable_device(priv->pci_dev);
6525 priv->is_open = 0;
6526 IWL_DEBUG_MAC80211("leave - failed\n");
5a66926a 6527 return ret;
b481de9c
ZY		 6528}
6529
bb8c093b 6530static void iwl3945_mac_stop(struct ieee80211_hw *hw)
b481de9c 6531{
bb8c093b 6532 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6533
6534 IWL_DEBUG_MAC80211("enter\n");
6ef89d0a 6535
e655b9f0
ZY		 6536 if (!priv->is_open) {
6537 IWL_DEBUG_MAC80211("leave - skip\n");
6538 return;
6539 }
6540
b481de9c 6541 priv->is_open = 0;
5a66926a
ZY		 6542
6543 if (iwl3945_is_ready_rf(priv)) {
e655b9f0
ZY		 6544 /* stop mac, cancel any scan request and clear
6545 * RXON_FILTER_ASSOC_MSK BIT
6546 */
5a66926a
ZY		 6547 mutex_lock(&priv->mutex);
6548 iwl3945_scan_cancel_timeout(priv, 100);
fde3571f 6549 mutex_unlock(&priv->mutex);
fde3571f
MA		 6550 }
6551
5a66926a
ZY		 6552 iwl3945_down(priv);
6553
6554 flush_workqueue(priv->workqueue);
6555 free_irq(priv->pci_dev->irq, priv);
6556 pci_disable_msi(priv->pci_dev);
6557 pci_save_state(priv->pci_dev);
6558 pci_disable_device(priv->pci_dev);
6ef89d0a 6559
b481de9c 6560 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 6561}
6562
e039fa4a 6563static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 6564{
bb8c093b 6565 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6566
6567 IWL_DEBUG_MAC80211("enter\n");
6568
b481de9c 6569 IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 6570 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 6571
e039fa4a 6572 if (iwl3945_tx_skb(priv, skb))
b481de9c
ZY		 6573 dev_kfree_skb_any(skb);
6574
6575 IWL_DEBUG_MAC80211("leave\n");
6576 return 0;
6577}
6578
bb8c093b 6579static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
b481de9c
ZY		 6580 struct ieee80211_if_init_conf *conf)
6581{
bb8c093b 6582 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6583 unsigned long flags;
6584
32bfd35d 6585 IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
b481de9c 6586
32bfd35d
JB		 6587 if (priv->vif) {
6588 IWL_DEBUG_MAC80211("leave - vif != NULL\n");
864792e3 6589 return -EOPNOTSUPP;
b481de9c
ZY		 6590 }
6591
6592 spin_lock_irqsave(&priv->lock, flags);
32bfd35d 6593 priv->vif = conf->vif;
b481de9c
ZY		 6594
6595 spin_unlock_irqrestore(&priv->lock, flags);
6596
6597 mutex_lock(&priv->mutex);
864792e3
TW		 6598
6599 if (conf->mac_addr) {
e174961c 6600 IWL_DEBUG_MAC80211("Set: %pM\n", conf->mac_addr);
864792e3
TW		 6601 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
6602 }
6603
5a66926a
ZY		 6604 if (iwl3945_is_ready(priv))
6605 iwl3945_set_mode(priv, conf->type);
b481de9c 6606
b481de9c
ZY		 6607 mutex_unlock(&priv->mutex);
6608
5a66926a 6609 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 6610 return 0;
6611}
6612
6613/**
bb8c093b 6614 * iwl3945_mac_config - mac80211 config callback
b481de9c
ZY		 6615 *
6616 * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
6617 * be set inappropriately and the driver currently sets the hardware up to
6618 * use it whenever needed.
6619 */
e8975581 6620static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed)
b481de9c 6621{
bb8c093b
CH		 6622 struct iwl3945_priv *priv = hw->priv;
6623 const struct iwl3945_channel_info *ch_info;
e8975581 6624 struct ieee80211_conf *conf = &hw->conf;
b481de9c 6625 unsigned long flags;
76bb77e0 6626 int ret = 0;
b481de9c
ZY		 6627
6628 mutex_lock(&priv->mutex);
8318d78a 6629 IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
b481de9c 6630
bb8c093b 6631 if (!iwl3945_is_ready(priv)) {
b481de9c 6632 IWL_DEBUG_MAC80211("leave - not ready\n");
76bb77e0
ZY		 6633 ret = -EIO;
6634 goto out;
b481de9c
ZY		 6635 }
6636
bb8c093b 6637 if (unlikely(!iwl3945_param_disable_hw_scan &&
b481de9c 6638 test_bit(STATUS_SCANNING, &priv->status))) {
a0646470
ZY		 6639 IWL_DEBUG_MAC80211("leave - scanning\n");
6640 set_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 6641 mutex_unlock(&priv->mutex);
a0646470 6642 return 0;
b481de9c
ZY		 6643 }
6644
6645 spin_lock_irqsave(&priv->lock, flags);
6646
8318d78a
JB		 6647 ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
6648 conf->channel->hw_value);
b481de9c 6649 if (!is_channel_valid(ch_info)) {
66b5004d 6650 IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this band.\n",
8318d78a 6651 conf->channel->hw_value, conf->channel->band);
b481de9c
ZY		 6652 IWL_DEBUG_MAC80211("leave - invalid channel\n");
6653 spin_unlock_irqrestore(&priv->lock, flags);
76bb77e0
ZY		 6654 ret = -EINVAL;
6655 goto out;
b481de9c
ZY		 6656 }
6657
8318d78a 6658 iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
b481de9c 6659
8318d78a 6660 iwl3945_set_flags_for_phymode(priv, conf->channel->band);
b481de9c
ZY		 6661
6662 /* The list of supported rates and rate mask can be different
6663 * for each phymode; since the phymode may have changed, reset
6664 * the rate mask to what mac80211 lists */
bb8c093b 6665 iwl3945_set_rate(priv);
b481de9c
ZY		 6666
6667 spin_unlock_irqrestore(&priv->lock, flags);
6668
6669#ifdef IEEE80211_CONF_CHANNEL_SWITCH
6670 if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
bb8c093b 6671 iwl3945_hw_channel_switch(priv, conf->channel);
76bb77e0 6672 goto out;
b481de9c
ZY		 6673 }
6674#endif
6675
bb8c093b 6676 iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
b481de9c
ZY		 6677
6678 if (!conf->radio_enabled) {
6679 IWL_DEBUG_MAC80211("leave - radio disabled\n");
76bb77e0 6680 goto out;
b481de9c
ZY		 6681 }
6682
bb8c093b 6683 if (iwl3945_is_rfkill(priv)) {
b481de9c 6684 IWL_DEBUG_MAC80211("leave - RF kill\n");
76bb77e0
ZY		 6685 ret = -EIO;
6686 goto out;
b481de9c
ZY		 6687 }
6688
bb8c093b 6689 iwl3945_set_rate(priv);
b481de9c
ZY		 6690
6691 if (memcmp(&priv->active_rxon,
6692 &priv->staging_rxon, sizeof(priv->staging_rxon)))
bb8c093b 6693 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6694 else
6695 IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
6696
6697 IWL_DEBUG_MAC80211("leave\n");
6698
76bb77e0 6699out:
a0646470 6700 clear_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 6701 mutex_unlock(&priv->mutex);
76bb77e0 6702 return ret;
b481de9c
ZY		 6703}
6704
bb8c093b 6705static void iwl3945_config_ap(struct iwl3945_priv *priv)
b481de9c
ZY		 6706{
6707 int rc = 0;
6708
d986bcd1 6709 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY		 6710 return;
6711
6712 /* The following should be done only at AP bring up */
5d1e2325 6713 if (!(iwl3945_is_associated(priv))) {
b481de9c
ZY		 6714
6715 /* RXON - unassoc (to set timing command) */
6716 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6717 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6718
6719 /* RXON Timing */
bb8c093b
CH		 6720 memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
6721 iwl3945_setup_rxon_timing(priv);
6722 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY		 6723 sizeof(priv->rxon_timing), &priv->rxon_timing);
6724 if (rc)
6725 IWL_WARNING("REPLY_RXON_TIMING failed - "
6726 "Attempting to continue.\n");
6727
6728 /* FIXME: what should be the assoc_id for AP? */
6729 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
6730 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
6731 priv->staging_rxon.flags |=
6732 RXON_FLG_SHORT_PREAMBLE_MSK;
6733 else
6734 priv->staging_rxon.flags &=
6735 ~RXON_FLG_SHORT_PREAMBLE_MSK;
6736
6737 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
6738 if (priv->assoc_capability &
6739 WLAN_CAPABILITY_SHORT_SLOT_TIME)
6740 priv->staging_rxon.flags |=
6741 RXON_FLG_SHORT_SLOT_MSK;
6742 else
6743 priv->staging_rxon.flags &=
6744 ~RXON_FLG_SHORT_SLOT_MSK;
6745
05c914fe 6746 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY		 6747 priv->staging_rxon.flags &=
6748 ~RXON_FLG_SHORT_SLOT_MSK;
6749 }
6750 /* restore RXON assoc */
6751 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
bb8c093b
CH		 6752 iwl3945_commit_rxon(priv);
6753 iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
556f8db7 6754 }
bb8c093b 6755 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 6756
6757 /* FIXME - we need to add code here to detect a totally new
6758 * configuration, reset the AP, unassoc, rxon timing, assoc,
6759 * clear sta table, add BCAST sta... */
6760}
6761
9d139c81
JB		 6762/* temporary */
6763static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb);
6764
32bfd35d
JB		 6765static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
6766 struct ieee80211_vif *vif,
b481de9c
ZY		 6767 struct ieee80211_if_conf *conf)
6768{
bb8c093b 6769 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6770 unsigned long flags;
6771 int rc;
6772
6773 if (conf == NULL)
6774 return -EIO;
6775
b716bb91
EG		 6776 if (priv->vif != vif) {
6777 IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
b716bb91
EG		 6778 return 0;
6779 }
6780
9d139c81 6781 /* handle this temporarily here */
05c914fe 6782 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
9d139c81
JB		 6783 conf->changed & IEEE80211_IFCC_BEACON) {
6784 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
6785 if (!beacon)
6786 return -ENOMEM;
6787 rc = iwl3945_mac_beacon_update(hw, beacon);
6788 if (rc)
6789 return rc;
6790 }
6791
4150c572
JB		 6792 /* XXX: this MUST use conf->mac_addr */
6793
05c914fe 6794 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
9d139c81 6795 (!conf->ssid_len)) {
b481de9c
ZY		 6796 IWL_DEBUG_MAC80211
6797 ("Leaving in AP mode because HostAPD is not ready.\n");
6798 return 0;
6799 }
6800
5a66926a
ZY		 6801 if (!iwl3945_is_alive(priv))
6802 return -EAGAIN;
6803
b481de9c
ZY		 6804 mutex_lock(&priv->mutex);
6805
b481de9c 6806 if (conf->bssid)
e174961c 6807 IWL_DEBUG_MAC80211("bssid: %pM\n", conf->bssid);
b481de9c 6808
4150c572
JB		 6809/*
6810 * very dubious code was here; the probe filtering flag is never set:
6811 *
b481de9c
ZY		 6812 if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
6813 !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
4150c572 6814 */
b481de9c 6815
05c914fe 6816 if (priv->iw_mode == NL80211_IFTYPE_AP) {
b481de9c
ZY		 6817 if (!conf->bssid) {
6818 conf->bssid = priv->mac_addr;
6819 memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
e174961c
JB		 6820 IWL_DEBUG_MAC80211("bssid was set to: %pM\n",
6821 conf->bssid);
b481de9c
ZY		 6822 }
6823 if (priv->ibss_beacon)
6824 dev_kfree_skb(priv->ibss_beacon);
6825
9d139c81 6826 priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
b481de9c
ZY		 6827 }
6828
fde3571f
MA		 6829 if (iwl3945_is_rfkill(priv))
6830 goto done;
6831
b481de9c
ZY		 6832 if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
6833 !is_multicast_ether_addr(conf->bssid)) {
6834 /* If there is currently a HW scan going on in the background
6835 * then we need to cancel it else the RXON below will fail. */
bb8c093b 6836 if (iwl3945_scan_cancel_timeout(priv, 100)) {
b481de9c
ZY		 6837 IWL_WARNING("Aborted scan still in progress "
6838 "after 100ms\n");
6839 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
6840 mutex_unlock(&priv->mutex);
6841 return -EAGAIN;
6842 }
6843 memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
6844
6845 /* TODO: Audit driver for usage of these members and see
6846 * if mac80211 deprecates them (priv->bssid looks like it
6847 * shouldn't be there, but I haven't scanned the IBSS code
6848 * to verify) - jpk */
6849 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
6850
05c914fe 6851 if (priv->iw_mode == NL80211_IFTYPE_AP)
bb8c093b 6852 iwl3945_config_ap(priv);
b481de9c 6853 else {
bb8c093b 6854 rc = iwl3945_commit_rxon(priv);
05c914fe 6855 if ((priv->iw_mode == NL80211_IFTYPE_STATION) && rc)
bb8c093b 6856 iwl3945_add_station(priv,
556f8db7 6857 priv->active_rxon.bssid_addr, 1, 0);
b481de9c
ZY		 6858 }
6859
6860 } else {
bb8c093b 6861 iwl3945_scan_cancel_timeout(priv, 100);
b481de9c 6862 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6863 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6864 }
6865
fde3571f 6866 done:
b481de9c
ZY		 6867 spin_lock_irqsave(&priv->lock, flags);
6868 if (!conf->ssid_len)
6869 memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
6870 else
6871 memcpy(priv->essid, conf->ssid, conf->ssid_len);
6872
6873 priv->essid_len = conf->ssid_len;
6874 spin_unlock_irqrestore(&priv->lock, flags);
6875
6876 IWL_DEBUG_MAC80211("leave\n");
6877 mutex_unlock(&priv->mutex);
6878
6879 return 0;
6880}
6881
bb8c093b 6882static void iwl3945_configure_filter(struct ieee80211_hw *hw,
4150c572
JB		 6883 unsigned int changed_flags,
6884 unsigned int *total_flags,
6885 int mc_count, struct dev_addr_list *mc_list)
6886{
5ec03976 6887 struct iwl3945_priv *priv = hw->priv;
25b3f57c
RF		 6888
6889 if (changed_flags & (*total_flags) & FIF_OTHER_BSS) {
6890 IWL_DEBUG_MAC80211("Enter: type %d (0x%x, 0x%x)\n",
05c914fe 6891 NL80211_IFTYPE_MONITOR,
25b3f57c
RF		 6892 changed_flags, *total_flags);
6893 /* queue work 'cuz mac80211 is holding a lock which
6894 * prevents us from issuing (synchronous) f/w cmds */
6895 queue_work(priv->workqueue, &priv->set_monitor);
5ec03976 6896 }
25b3f57c
RF		 6897 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI |
6898 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
4150c572
JB		 6899}
6900
bb8c093b 6901static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
b481de9c
ZY		 6902 struct ieee80211_if_init_conf *conf)
6903{
bb8c093b 6904 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6905
6906 IWL_DEBUG_MAC80211("enter\n");
6907
6908 mutex_lock(&priv->mutex);
6ef89d0a 6909
fde3571f
MA		 6910 if (iwl3945_is_ready_rf(priv)) {
6911 iwl3945_scan_cancel_timeout(priv, 100);
fde3571f
MA		 6912 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
6913 iwl3945_commit_rxon(priv);
6914 }
32bfd35d
JB		 6915 if (priv->vif == conf->vif) {
6916 priv->vif = NULL;
b481de9c
ZY		 6917 memset(priv->bssid, 0, ETH_ALEN);
6918 memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
6919 priv->essid_len = 0;
6920 }
6921 mutex_unlock(&priv->mutex);
6922
6923 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 6924}
6925
cd56d331
AK		 6926#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
6927
6928static void iwl3945_bss_info_changed(struct ieee80211_hw *hw,
6929 struct ieee80211_vif *vif,
6930 struct ieee80211_bss_conf *bss_conf,
6931 u32 changes)
6932{
6933 struct iwl3945_priv *priv = hw->priv;
6934
6935 IWL_DEBUG_MAC80211("changes = 0x%X\n", changes);
6936
6937 if (changes & BSS_CHANGED_ERP_PREAMBLE) {
6938 IWL_DEBUG_MAC80211("ERP_PREAMBLE %d\n",
6939 bss_conf->use_short_preamble);
6940 if (bss_conf->use_short_preamble)
6941 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
6942 else
6943 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
6944 }
6945
6946 if (changes & BSS_CHANGED_ERP_CTS_PROT) {
6947 IWL_DEBUG_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
6948 if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
6949 priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
6950 else
6951 priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
6952 }
6953
6954 if (changes & BSS_CHANGED_ASSOC) {
6955 IWL_DEBUG_MAC80211("ASSOC %d\n", bss_conf->assoc);
6956 /* This should never happen as this function should
6957 * never be called from interrupt context. */
6958 if (WARN_ON_ONCE(in_interrupt()))
6959 return;
6960 if (bss_conf->assoc) {
6961 priv->assoc_id = bss_conf->aid;
6962 priv->beacon_int = bss_conf->beacon_int;
6963 priv->timestamp0 = bss_conf->timestamp & 0xFFFFFFFF;
6964 priv->timestamp1 = (bss_conf->timestamp >> 32) &
6965 0xFFFFFFFF;
6966 priv->assoc_capability = bss_conf->assoc_capability;
6967 priv->next_scan_jiffies = jiffies +
6968 IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
6969 mutex_lock(&priv->mutex);
6970 iwl3945_post_associate(priv);
6971 mutex_unlock(&priv->mutex);
6972 } else {
6973 priv->assoc_id = 0;
6974 IWL_DEBUG_MAC80211("DISASSOC %d\n", bss_conf->assoc);
6975 }
6976 } else if (changes && iwl3945_is_associated(priv) && priv->assoc_id) {
6977 IWL_DEBUG_MAC80211("Associated Changes %d\n", changes);
6978 iwl3945_send_rxon_assoc(priv);
6979 }
6980
6981}
6982
bb8c093b 6983static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
b481de9c
ZY		 6984{
6985 int rc = 0;
6986 unsigned long flags;
bb8c093b 6987 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6988
6989 IWL_DEBUG_MAC80211("enter\n");
6990
15e869d8 6991 mutex_lock(&priv->mutex);
b481de9c
ZY		 6992 spin_lock_irqsave(&priv->lock, flags);
6993
bb8c093b 6994 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 6995 rc = -EIO;
6996 IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
6997 goto out_unlock;
6998 }
6999
05c914fe 7000 if (priv->iw_mode == NL80211_IFTYPE_AP) { /* APs don't scan */
b481de9c
ZY		 7001 rc = -EIO;
7002 IWL_ERROR("ERROR: APs don't scan\n");
7003 goto out_unlock;
7004 }
7005
7878a5a4
MA		 7006 /* we don't schedule scan within next_scan_jiffies period */
7007 if (priv->next_scan_jiffies &&
7008 time_after(priv->next_scan_jiffies, jiffies)) {
7009 rc = -EAGAIN;
7010 goto out_unlock;
7011 }
15dbf1b7
BM		 7012 /* if we just finished scan ask for delay for a broadcast scan */
7013 if ((len == 0) && priv->last_scan_jiffies &&
7014 time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN,
7015 jiffies)) {
b481de9c
ZY		 7016 rc = -EAGAIN;
7017 goto out_unlock;
7018 }
7019 if (len) {
7878a5a4 7020 IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
bb8c093b 7021 iwl3945_escape_essid(ssid, len), (int)len);
b481de9c
ZY		 7022
7023 priv->one_direct_scan = 1;
7024 priv->direct_ssid_len = (u8)
7025 min((u8) len, (u8) IW_ESSID_MAX_SIZE);
7026 memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
6ef89d0a
MA		 7027 } else
7028 priv->one_direct_scan = 0;
b481de9c 7029
bb8c093b 7030 rc = iwl3945_scan_initiate(priv);
b481de9c
ZY		 7031
7032 IWL_DEBUG_MAC80211("leave\n");
7033
7034out_unlock:
7035 spin_unlock_irqrestore(&priv->lock, flags);
15e869d8 7036 mutex_unlock(&priv->mutex);
b481de9c
ZY		 7037
7038 return rc;
7039}
7040
bb8c093b 7041static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
b481de9c
ZY		 7042 const u8 *local_addr, const u8 *addr,
7043 struct ieee80211_key_conf *key)
7044{
bb8c093b 7045 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7046 int rc = 0;
7047 u8 sta_id;
7048
7049 IWL_DEBUG_MAC80211("enter\n");
7050
bb8c093b 7051 if (!iwl3945_param_hwcrypto) {
b481de9c
ZY		 7052 IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
7053 return -EOPNOTSUPP;
7054 }
7055
7056 if (is_zero_ether_addr(addr))
7057 /* only support pairwise keys */
7058 return -EOPNOTSUPP;
7059
bb8c093b 7060 sta_id = iwl3945_hw_find_station(priv, addr);
b481de9c 7061 if (sta_id == IWL_INVALID_STATION) {
e174961c
JB		 7062 IWL_DEBUG_MAC80211("leave - %pM not in station map.\n",
7063 addr);
b481de9c
ZY		 7064 return -EINVAL;
7065 }
7066
7067 mutex_lock(&priv->mutex);
7068
bb8c093b 7069 iwl3945_scan_cancel_timeout(priv, 100);
15e869d8 7070
b481de9c
ZY		 7071 switch (cmd) {
7072 case SET_KEY:
bb8c093b 7073 rc = iwl3945_update_sta_key_info(priv, key, sta_id);
b481de9c 7074 if (!rc) {
bb8c093b
CH		 7075 iwl3945_set_rxon_hwcrypto(priv, 1);
7076 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7077 key->hw_key_idx = sta_id;
7078 IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
7079 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
7080 }
7081 break;
7082 case DISABLE_KEY:
bb8c093b 7083 rc = iwl3945_clear_sta_key_info(priv, sta_id);
b481de9c 7084 if (!rc) {
bb8c093b
CH		 7085 iwl3945_set_rxon_hwcrypto(priv, 0);
7086 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7087 IWL_DEBUG_MAC80211("disable hwcrypto key\n");
7088 }
7089 break;
7090 default:
7091 rc = -EINVAL;
7092 }
7093
7094 IWL_DEBUG_MAC80211("leave\n");
7095 mutex_unlock(&priv->mutex);
7096
7097 return rc;
7098}
7099
e100bb64 7100static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
b481de9c
ZY		 7101 const struct ieee80211_tx_queue_params *params)
7102{
bb8c093b 7103 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7104 unsigned long flags;
7105 int q;
b481de9c
ZY		 7106
7107 IWL_DEBUG_MAC80211("enter\n");
7108
bb8c093b 7109 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7110 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7111 return -EIO;
7112 }
7113
7114 if (queue >= AC_NUM) {
7115 IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
7116 return 0;
7117 }
7118
b481de9c
ZY		 7119 if (!priv->qos_data.qos_enable) {
7120 priv->qos_data.qos_active = 0;
7121 IWL_DEBUG_MAC80211("leave - qos not enabled\n");
7122 return 0;
7123 }
7124 q = AC_NUM - 1 - queue;
7125
7126 spin_lock_irqsave(&priv->lock, flags);
7127
7128 priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
7129 priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
7130 priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
7131 priv->qos_data.def_qos_parm.ac[q].edca_txop =
3330d7be 7132 cpu_to_le16((params->txop * 32));
b481de9c
ZY		 7133
7134 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
7135 priv->qos_data.qos_active = 1;
7136
7137 spin_unlock_irqrestore(&priv->lock, flags);
7138
7139 mutex_lock(&priv->mutex);
05c914fe 7140 if (priv->iw_mode == NL80211_IFTYPE_AP)
bb8c093b
CH		 7141 iwl3945_activate_qos(priv, 1);
7142 else if (priv->assoc_id && iwl3945_is_associated(priv))
7143 iwl3945_activate_qos(priv, 0);
b481de9c
ZY		 7144
7145 mutex_unlock(&priv->mutex);
7146
b481de9c
ZY		 7147 IWL_DEBUG_MAC80211("leave\n");
7148 return 0;
7149}
7150
bb8c093b 7151static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
b481de9c
ZY		 7152 struct ieee80211_tx_queue_stats *stats)
7153{
bb8c093b 7154 struct iwl3945_priv *priv = hw->priv;
b481de9c 7155 int i, avail;
bb8c093b
CH		 7156 struct iwl3945_tx_queue *txq;
7157 struct iwl3945_queue *q;
b481de9c
ZY		 7158 unsigned long flags;
7159
7160 IWL_DEBUG_MAC80211("enter\n");
7161
bb8c093b 7162 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7163 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7164 return -EIO;
7165 }
7166
7167 spin_lock_irqsave(&priv->lock, flags);
7168
7169 for (i = 0; i < AC_NUM; i++) {
7170 txq = &priv->txq[i];
7171 q = &txq->q;
bb8c093b 7172 avail = iwl3945_queue_space(q);
b481de9c 7173
57ffc589
JB		 7174 stats[i].len = q->n_window - avail;
7175 stats[i].limit = q->n_window - q->high_mark;
7176 stats[i].count = q->n_window;
b481de9c
ZY		 7177
7178 }
7179 spin_unlock_irqrestore(&priv->lock, flags);
7180
7181 IWL_DEBUG_MAC80211("leave\n");
7182
7183 return 0;
7184}
7185
bb8c093b 7186static int iwl3945_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY		 7187 struct ieee80211_low_level_stats *stats)
7188{
7189 IWL_DEBUG_MAC80211("enter\n");
7190 IWL_DEBUG_MAC80211("leave\n");
7191
7192 return 0;
7193}
7194
bb8c093b 7195static u64 iwl3945_mac_get_tsf(struct ieee80211_hw *hw)
b481de9c
ZY		 7196{
7197 IWL_DEBUG_MAC80211("enter\n");
7198 IWL_DEBUG_MAC80211("leave\n");
7199
7200 return 0;
7201}
7202
bb8c093b 7203static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
b481de9c 7204{
bb8c093b 7205 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7206 unsigned long flags;
7207
7208 mutex_lock(&priv->mutex);
7209 IWL_DEBUG_MAC80211("enter\n");
7210
bb8c093b 7211 iwl3945_reset_qos(priv);
292ae174 7212
b481de9c
ZY		 7213 spin_lock_irqsave(&priv->lock, flags);
7214 priv->assoc_id = 0;
7215 priv->assoc_capability = 0;
7216 priv->call_post_assoc_from_beacon = 0;
7217
7218 /* new association get rid of ibss beacon skb */
7219 if (priv->ibss_beacon)
7220 dev_kfree_skb(priv->ibss_beacon);
7221
7222 priv->ibss_beacon = NULL;
7223
7224 priv->beacon_int = priv->hw->conf.beacon_int;
7225 priv->timestamp1 = 0;
7226 priv->timestamp0 = 0;
05c914fe 7227 if ((priv->iw_mode == NL80211_IFTYPE_STATION))
b481de9c
ZY		 7228 priv->beacon_int = 0;
7229
7230 spin_unlock_irqrestore(&priv->lock, flags);
7231
fde3571f
MA		 7232 if (!iwl3945_is_ready_rf(priv)) {
7233 IWL_DEBUG_MAC80211("leave - not ready\n");
7234 mutex_unlock(&priv->mutex);
7235 return;
7236 }
7237
15e869d8
MA		 7238 /* we are restarting association process
7239 * clear RXON_FILTER_ASSOC_MSK bit
7240 */
05c914fe 7241 if (priv->iw_mode != NL80211_IFTYPE_AP) {
bb8c093b 7242 iwl3945_scan_cancel_timeout(priv, 100);
15e869d8 7243 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 7244 iwl3945_commit_rxon(priv);
15e869d8
MA		 7245 }
7246
b481de9c 7247 /* Per mac80211.h: This is only used in IBSS mode... */
05c914fe 7248 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
15e869d8 7249
b481de9c
ZY		 7250 IWL_DEBUG_MAC80211("leave - not in IBSS\n");
7251 mutex_unlock(&priv->mutex);
7252 return;
b481de9c
ZY		 7253 }
7254
bb8c093b 7255 iwl3945_set_rate(priv);
b481de9c
ZY		 7256
7257 mutex_unlock(&priv->mutex);
7258
7259 IWL_DEBUG_MAC80211("leave\n");
7260
7261}
7262
e039fa4a 7263static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 7264{
bb8c093b 7265 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7266 unsigned long flags;
7267
7268 mutex_lock(&priv->mutex);
7269 IWL_DEBUG_MAC80211("enter\n");
7270
bb8c093b 7271 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7272 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7273 mutex_unlock(&priv->mutex);
7274 return -EIO;
7275 }
7276
05c914fe 7277 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
b481de9c
ZY		 7278 IWL_DEBUG_MAC80211("leave - not IBSS\n");
7279 mutex_unlock(&priv->mutex);
7280 return -EIO;
7281 }
7282
7283 spin_lock_irqsave(&priv->lock, flags);
7284
7285 if (priv->ibss_beacon)
7286 dev_kfree_skb(priv->ibss_beacon);
7287
7288 priv->ibss_beacon = skb;
7289
7290 priv->assoc_id = 0;
7291
7292 IWL_DEBUG_MAC80211("leave\n");
7293 spin_unlock_irqrestore(&priv->lock, flags);
7294
bb8c093b 7295 iwl3945_reset_qos(priv);
b481de9c 7296
dc4b1e7d 7297 iwl3945_post_associate(priv);
b481de9c
ZY		 7298
7299 mutex_unlock(&priv->mutex);
7300
7301 return 0;
7302}
7303
7304/*****************************************************************************
7305 *
7306 * sysfs attributes
7307 *
7308 *****************************************************************************/
7309
c8b0e6e1 7310#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 7311
7312/*
7313 * The following adds a new attribute to the sysfs representation
7314 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
7315 * used for controlling the debug level.
7316 *
7317 * See the level definitions in iwl for details.
7318 */
7319
7320static ssize_t show_debug_level(struct device_driver *d, char *buf)
7321{
bb8c093b 7322 return sprintf(buf, "0x%08X\n", iwl3945_debug_level);
b481de9c
ZY		 7323}
7324static ssize_t store_debug_level(struct device_driver *d,
7325 const char *buf, size_t count)
7326{
7327 char *p = (char *)buf;
7328 u32 val;
7329
7330 val = simple_strtoul(p, &p, 0);
7331 if (p == buf)
7332 printk(KERN_INFO DRV_NAME
7333 ": %s is not in hex or decimal form.\n", buf);
7334 else
bb8c093b 7335 iwl3945_debug_level = val;
b481de9c
ZY		 7336
7337 return strnlen(buf, count);
7338}
7339
7340static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
7341 show_debug_level, store_debug_level);
7342
c8b0e6e1 7343#endif /* CONFIG_IWL3945_DEBUG */
b481de9c 7344
b481de9c
ZY		 7345static ssize_t show_temperature(struct device *d,
7346 struct device_attribute *attr, char *buf)
7347{
bb8c093b 7348 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c 7349
bb8c093b 7350 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7351 return -EAGAIN;
7352
bb8c093b 7353 return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
b481de9c
ZY		 7354}
7355
7356static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
7357
b481de9c
ZY		 7358static ssize_t show_tx_power(struct device *d,
7359 struct device_attribute *attr, char *buf)
7360{
bb8c093b 7361 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7362 return sprintf(buf, "%d\n", priv->user_txpower_limit);
7363}
7364
7365static ssize_t store_tx_power(struct device *d,
7366 struct device_attribute *attr,
7367 const char *buf, size_t count)
7368{
bb8c093b 7369 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7370 char *p = (char *)buf;
7371 u32 val;
7372
7373 val = simple_strtoul(p, &p, 10);
7374 if (p == buf)
7375 printk(KERN_INFO DRV_NAME
7376 ": %s is not in decimal form.\n", buf);
7377 else
bb8c093b 7378 iwl3945_hw_reg_set_txpower(priv, val);
b481de9c
ZY		 7379
7380 return count;
7381}
7382
7383static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
7384
7385static ssize_t show_flags(struct device *d,
7386 struct device_attribute *attr, char *buf)
7387{
bb8c093b 7388 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7389
7390 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
7391}
7392
7393static ssize_t store_flags(struct device *d,
7394 struct device_attribute *attr,
7395 const char *buf, size_t count)
7396{
bb8c093b 7397 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7398 u32 flags = simple_strtoul(buf, NULL, 0);
7399
7400 mutex_lock(&priv->mutex);
7401 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
7402 /* Cancel any currently running scans... */
bb8c093b 7403 if (iwl3945_scan_cancel_timeout(priv, 100))
b481de9c
ZY		 7404 IWL_WARNING("Could not cancel scan.\n");
7405 else {
7406 IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
7407 flags);
7408 priv->staging_rxon.flags = cpu_to_le32(flags);
bb8c093b 7409 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7410 }
7411 }
7412 mutex_unlock(&priv->mutex);
7413
7414 return count;
7415}
7416
7417static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
7418
7419static ssize_t show_filter_flags(struct device *d,
7420 struct device_attribute *attr, char *buf)
7421{
bb8c093b 7422 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7423
7424 return sprintf(buf, "0x%04X\n",
7425 le32_to_cpu(priv->active_rxon.filter_flags));
7426}
7427
7428static ssize_t store_filter_flags(struct device *d,
7429 struct device_attribute *attr,
7430 const char *buf, size_t count)
7431{
bb8c093b 7432 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7433 u32 filter_flags = simple_strtoul(buf, NULL, 0);
7434
7435 mutex_lock(&priv->mutex);
7436 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
7437 /* Cancel any currently running scans... */
bb8c093b 7438 if (iwl3945_scan_cancel_timeout(priv, 100))
b481de9c
ZY		 7439 IWL_WARNING("Could not cancel scan.\n");
7440 else {
7441 IWL_DEBUG_INFO("Committing rxon.filter_flags = "
7442 "0x%04X\n", filter_flags);
7443 priv->staging_rxon.filter_flags =
7444 cpu_to_le32(filter_flags);
bb8c093b 7445 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7446 }
7447 }
7448 mutex_unlock(&priv->mutex);
7449
7450 return count;
7451}
7452
7453static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
7454 store_filter_flags);
7455
c8b0e6e1 7456#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 7457
7458static ssize_t show_measurement(struct device *d,
7459 struct device_attribute *attr, char *buf)
7460{
bb8c093b
CH		 7461 struct iwl3945_priv *priv = dev_get_drvdata(d);
7462 struct iwl3945_spectrum_notification measure_report;
b481de9c 7463 u32 size = sizeof(measure_report), len = 0, ofs = 0;
3ac7f146 7464 u8 *data = (u8 *)&measure_report;
b481de9c
ZY		 7465 unsigned long flags;
7466
7467 spin_lock_irqsave(&priv->lock, flags);
7468 if (!(priv->measurement_status & MEASUREMENT_READY)) {
7469 spin_unlock_irqrestore(&priv->lock, flags);
7470 return 0;
7471 }
7472 memcpy(&measure_report, &priv->measure_report, size);
7473 priv->measurement_status = 0;
7474 spin_unlock_irqrestore(&priv->lock, flags);
7475
7476 while (size && (PAGE_SIZE - len)) {
7477 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
7478 PAGE_SIZE - len, 1);
7479 len = strlen(buf);
7480 if (PAGE_SIZE - len)
7481 buf[len++] = '\n';
7482
7483 ofs += 16;
7484 size -= min(size, 16U);
7485 }
7486
7487 return len;
7488}
7489
7490static ssize_t store_measurement(struct device *d,
7491 struct device_attribute *attr,
7492 const char *buf, size_t count)
7493{
bb8c093b 7494 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7495 struct ieee80211_measurement_params params = {
7496 .channel = le16_to_cpu(priv->active_rxon.channel),
7497 .start_time = cpu_to_le64(priv->last_tsf),
7498 .duration = cpu_to_le16(1),
7499 };
7500 u8 type = IWL_MEASURE_BASIC;
7501 u8 buffer[32];
7502 u8 channel;
7503
7504 if (count) {
7505 char *p = buffer;
7506 strncpy(buffer, buf, min(sizeof(buffer), count));
7507 channel = simple_strtoul(p, NULL, 0);
7508 if (channel)
7509 params.channel = channel;
7510
7511 p = buffer;
7512 while (*p && *p != ' ')
7513 p++;
7514 if (*p)
7515 type = simple_strtoul(p + 1, NULL, 0);
7516 }
7517
7518 IWL_DEBUG_INFO("Invoking measurement of type %d on "
7519 "channel %d (for '%s')\n", type, params.channel, buf);
bb8c093b 7520 iwl3945_get_measurement(priv, &params, type);
b481de9c
ZY		 7521
7522 return count;
7523}
7524
7525static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
7526 show_measurement, store_measurement);
c8b0e6e1 7527#endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
b481de9c 7528
b481de9c
ZY		 7529static ssize_t store_retry_rate(struct device *d,
7530 struct device_attribute *attr,
7531 const char *buf, size_t count)
7532{
bb8c093b 7533 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7534
7535 priv->retry_rate = simple_strtoul(buf, NULL, 0);
7536 if (priv->retry_rate <= 0)
7537 priv->retry_rate = 1;
7538
7539 return count;
7540}
7541
7542static ssize_t show_retry_rate(struct device *d,
7543 struct device_attribute *attr, char *buf)
7544{
bb8c093b 7545 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7546 return sprintf(buf, "%d", priv->retry_rate);
7547}
7548
7549static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
7550 store_retry_rate);
7551
7552static ssize_t store_power_level(struct device *d,
7553 struct device_attribute *attr,
7554 const char *buf, size_t count)
7555{
bb8c093b 7556 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7557 int rc;
7558 int mode;
7559
7560 mode = simple_strtoul(buf, NULL, 0);
7561 mutex_lock(&priv->mutex);
7562
bb8c093b 7563 if (!iwl3945_is_ready(priv)) {
b481de9c
ZY		 7564 rc = -EAGAIN;
7565 goto out;
7566 }
7567
7568 if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
7569 mode = IWL_POWER_AC;
7570 else
7571 mode |= IWL_POWER_ENABLED;
7572
7573 if (mode != priv->power_mode) {
bb8c093b 7574 rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
b481de9c
ZY		 7575 if (rc) {
7576 IWL_DEBUG_MAC80211("failed setting power mode.\n");
7577 goto out;
7578 }
7579 priv->power_mode = mode;
7580 }
7581
7582 rc = count;
7583
7584 out:
7585 mutex_unlock(&priv->mutex);
7586 return rc;
7587}
7588
7589#define MAX_WX_STRING 80
7590
7591/* Values are in microsecond */
7592static const s32 timeout_duration[] = {
7593 350000,
7594 250000,
7595 75000,
7596 37000,
7597 25000,
7598};
7599static const s32 period_duration[] = {
7600 400000,
7601 700000,
7602 1000000,
7603 1000000,
7604 1000000
7605};
7606
7607static ssize_t show_power_level(struct device *d,
7608 struct device_attribute *attr, char *buf)
7609{
bb8c093b 7610 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7611 int level = IWL_POWER_LEVEL(priv->power_mode);
7612 char *p = buf;
7613
7614 p += sprintf(p, "%d ", level);
7615 switch (level) {
7616 case IWL_POWER_MODE_CAM:
7617 case IWL_POWER_AC:
7618 p += sprintf(p, "(AC)");
7619 break;
7620 case IWL_POWER_BATTERY:
7621 p += sprintf(p, "(BATTERY)");
7622 break;
7623 default:
7624 p += sprintf(p,
7625 "(Timeout %dms, Period %dms)",
7626 timeout_duration[level - 1] / 1000,
7627 period_duration[level - 1] / 1000);
7628 }
7629
7630 if (!(priv->power_mode & IWL_POWER_ENABLED))
7631 p += sprintf(p, " OFF\n");
7632 else
7633 p += sprintf(p, " \n");
7634
3ac7f146 7635 return p - buf + 1;
b481de9c
ZY		 7636
7637}
7638
7639static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
7640 store_power_level);
7641
7642static ssize_t show_channels(struct device *d,
7643 struct device_attribute *attr, char *buf)
7644{
8318d78a
JB		 7645 /* all this shit doesn't belong into sysfs anyway */
7646 return 0;
b481de9c
ZY		 7647}
7648
7649static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
7650
7651static ssize_t show_statistics(struct device *d,
7652 struct device_attribute *attr, char *buf)
7653{
bb8c093b
CH		 7654 struct iwl3945_priv *priv = dev_get_drvdata(d);
7655 u32 size = sizeof(struct iwl3945_notif_statistics);
b481de9c 7656 u32 len = 0, ofs = 0;
3ac7f146 7657 u8 *data = (u8 *)&priv->statistics;
b481de9c
ZY		 7658 int rc = 0;
7659
bb8c093b 7660 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7661 return -EAGAIN;
7662
7663 mutex_lock(&priv->mutex);
bb8c093b 7664 rc = iwl3945_send_statistics_request(priv);
b481de9c
ZY		 7665 mutex_unlock(&priv->mutex);
7666
7667 if (rc) {
7668 len = sprintf(buf,
7669 "Error sending statistics request: 0x%08X\n", rc);
7670 return len;
7671 }
7672
7673 while (size && (PAGE_SIZE - len)) {
7674 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
7675 PAGE_SIZE - len, 1);
7676 len = strlen(buf);
7677 if (PAGE_SIZE - len)
7678 buf[len++] = '\n';
7679
7680 ofs += 16;
7681 size -= min(size, 16U);
7682 }
7683
7684 return len;
7685}
7686
7687static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
7688
7689static ssize_t show_antenna(struct device *d,
7690 struct device_attribute *attr, char *buf)
7691{
bb8c093b 7692 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c 7693
bb8c093b 7694 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7695 return -EAGAIN;
7696
7697 return sprintf(buf, "%d\n", priv->antenna);
7698}
7699
7700static ssize_t store_antenna(struct device *d,
7701 struct device_attribute *attr,
7702 const char *buf, size_t count)
7703{
7704 int ant;
bb8c093b 7705 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7706
7707 if (count == 0)
7708 return 0;
7709
7710 if (sscanf(buf, "%1i", &ant) != 1) {
7711 IWL_DEBUG_INFO("not in hex or decimal form.\n");
7712 return count;
7713 }
7714
7715 if ((ant >= 0) && (ant <= 2)) {
7716 IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
bb8c093b 7717 priv->antenna = (enum iwl3945_antenna)ant;
b481de9c
ZY		 7718 } else
7719 IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
7720
7721
7722 return count;
7723}
7724
7725static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
7726
7727static ssize_t show_status(struct device *d,
7728 struct device_attribute *attr, char *buf)
7729{
bb8c093b
CH		 7730 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
7731 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7732 return -EAGAIN;
7733 return sprintf(buf, "0x%08x\n", (int)priv->status);
7734}
7735
7736static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
7737
7738static ssize_t dump_error_log(struct device *d,
7739 struct device_attribute *attr,
7740 const char *buf, size_t count)
7741{
7742 char *p = (char *)buf;
7743
7744 if (p[0] == '1')
bb8c093b 7745 iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data);
b481de9c
ZY		 7746
7747 return strnlen(buf, count);
7748}
7749
7750static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
7751
7752static ssize_t dump_event_log(struct device *d,
7753 struct device_attribute *attr,
7754 const char *buf, size_t count)
7755{
7756 char *p = (char *)buf;
7757
7758 if (p[0] == '1')
bb8c093b 7759 iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data);
b481de9c
ZY		 7760
7761 return strnlen(buf, count);
7762}
7763
7764static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
7765
7766/*****************************************************************************
7767 *
7768 * driver setup and teardown
7769 *
7770 *****************************************************************************/
7771
bb8c093b 7772static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv)
b481de9c
ZY		 7773{
7774 priv->workqueue = create_workqueue(DRV_NAME);
7775
7776 init_waitqueue_head(&priv->wait_command_queue);
7777
bb8c093b
CH		 7778 INIT_WORK(&priv->up, iwl3945_bg_up);
7779 INIT_WORK(&priv->restart, iwl3945_bg_restart);
7780 INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
7781 INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
7782 INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
7783 INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
7784 INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
7785 INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
5ec03976 7786 INIT_WORK(&priv->set_monitor, iwl3945_bg_set_monitor);
bb8c093b
CH		 7787 INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
7788 INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
7789 INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
7790
7791 iwl3945_hw_setup_deferred_work(priv);
b481de9c
ZY		 7792
7793 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
bb8c093b 7794 iwl3945_irq_tasklet, (unsigned long)priv);
b481de9c
ZY		 7795}
7796
bb8c093b 7797static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv)
b481de9c 7798{
bb8c093b 7799 iwl3945_hw_cancel_deferred_work(priv);
b481de9c 7800
e47eb6ad 7801 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY		 7802 cancel_delayed_work(&priv->scan_check);
7803 cancel_delayed_work(&priv->alive_start);
b481de9c
ZY		 7804 cancel_work_sync(&priv->beacon_update);
7805}
7806
bb8c093b 7807static struct attribute *iwl3945_sysfs_entries[] = {
b481de9c
ZY		 7808 &dev_attr_antenna.attr,
7809 &dev_attr_channels.attr,
7810 &dev_attr_dump_errors.attr,
7811 &dev_attr_dump_events.attr,
7812 &dev_attr_flags.attr,
7813 &dev_attr_filter_flags.attr,
c8b0e6e1 7814#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 7815 &dev_attr_measurement.attr,
7816#endif
7817 &dev_attr_power_level.attr,
b481de9c 7818 &dev_attr_retry_rate.attr,
b481de9c
ZY		 7819 &dev_attr_statistics.attr,
7820 &dev_attr_status.attr,
7821 &dev_attr_temperature.attr,
b481de9c
ZY		 7822 &dev_attr_tx_power.attr,
7823
7824 NULL
7825};
7826
bb8c093b 7827static struct attribute_group iwl3945_attribute_group = {
b481de9c 7828 .name = NULL, /* put in device directory */
bb8c093b 7829 .attrs = iwl3945_sysfs_entries,
b481de9c
ZY		 7830};
7831
bb8c093b
CH		 7832static struct ieee80211_ops iwl3945_hw_ops = {
7833 .tx = iwl3945_mac_tx,
7834 .start = iwl3945_mac_start,
7835 .stop = iwl3945_mac_stop,
7836 .add_interface = iwl3945_mac_add_interface,
7837 .remove_interface = iwl3945_mac_remove_interface,
7838 .config = iwl3945_mac_config,
7839 .config_interface = iwl3945_mac_config_interface,
7840 .configure_filter = iwl3945_configure_filter,
7841 .set_key = iwl3945_mac_set_key,
7842 .get_stats = iwl3945_mac_get_stats,
7843 .get_tx_stats = iwl3945_mac_get_tx_stats,
7844 .conf_tx = iwl3945_mac_conf_tx,
7845 .get_tsf = iwl3945_mac_get_tsf,
7846 .reset_tsf = iwl3945_mac_reset_tsf,
cd56d331 7847 .bss_info_changed = iwl3945_bss_info_changed,
bb8c093b 7848 .hw_scan = iwl3945_mac_hw_scan
b481de9c
ZY		 7849};
7850
bb8c093b 7851static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY		 7852{
7853 int err = 0;
bb8c093b 7854 struct iwl3945_priv *priv;
b481de9c 7855 struct ieee80211_hw *hw;
82b9a121 7856 struct iwl_3945_cfg *cfg = (struct iwl_3945_cfg *)(ent->driver_data);
0359facc 7857 unsigned long flags;
b481de9c 7858
6440adb5
CB		 7859 /* Disabling hardware scan means that mac80211 will perform scans
7860 * "the hard way", rather than using device's scan. */
bb8c093b 7861 if (iwl3945_param_disable_hw_scan) {
b481de9c 7862 IWL_DEBUG_INFO("Disabling hw_scan\n");
bb8c093b 7863 iwl3945_hw_ops.hw_scan = NULL;
b481de9c
ZY		 7864 }
7865
dfe7d458 7866 if ((iwl3945_param_queues_num > IWL39_MAX_NUM_QUEUES) ||
bb8c093b 7867 (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) {
b481de9c 7868 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
dfe7d458 7869 IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES);
b481de9c
ZY		 7870 err = -EINVAL;
7871 goto out;
7872 }
7873
7874 /* mac80211 allocates memory for this device instance, including
7875 * space for this driver's private structure */
bb8c093b 7876 hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops);
b481de9c
ZY		 7877 if (hw == NULL) {
7878 IWL_ERROR("Can not allocate network device\n");
7879 err = -ENOMEM;
7880 goto out;
7881 }
7882 SET_IEEE80211_DEV(hw, &pdev->dev);
7883
f51359a8 7884 hw->rate_control_algorithm = "iwl-3945-rs";
4b7679a5 7885 hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
f51359a8 7886
b481de9c
ZY		 7887 IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
7888 priv = hw->priv;
7889 priv->hw = hw;
7890
7891 priv->pci_dev = pdev;
82b9a121 7892 priv->cfg = cfg;
6440adb5
CB		 7893
7894 /* Select antenna (may be helpful if only one antenna is connected) */
bb8c093b 7895 priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna;
c8b0e6e1 7896#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 7897 iwl3945_debug_level = iwl3945_param_debug;
b481de9c
ZY		 7898 atomic_set(&priv->restrict_refcnt, 0);
7899#endif
7900 priv->retry_rate = 1;
7901
7902 priv->ibss_beacon = NULL;
7903
566bfe5a 7904 /* Tell mac80211 our characteristics */
605a0bd6 7905 hw->flags = IEEE80211_HW_SIGNAL_DBM |
566bfe5a 7906 IEEE80211_HW_NOISE_DBM;
b481de9c 7907
f59ac048
LR		 7908 hw->wiphy->interface_modes =
7909 BIT(NL80211_IFTYPE_AP) |
7910 BIT(NL80211_IFTYPE_STATION) |
7911 BIT(NL80211_IFTYPE_ADHOC);
7912
6440adb5 7913 /* 4 EDCA QOS priorities */
b481de9c
ZY		 7914 hw->queues = 4;
7915
7916 spin_lock_init(&priv->lock);
7917 spin_lock_init(&priv->power_data.lock);
7918 spin_lock_init(&priv->sta_lock);
7919 spin_lock_init(&priv->hcmd_lock);
7920
b481de9c
ZY		 7921 INIT_LIST_HEAD(&priv->free_frames);
7922
7923 mutex_init(&priv->mutex);
7924 if (pci_enable_device(pdev)) {
7925 err = -ENODEV;
7926 goto out_ieee80211_free_hw;
7927 }
7928
7929 pci_set_master(pdev);
7930
6440adb5 7931 /* Clear the driver's (not device's) station table */
bb8c093b 7932 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 7933
7934 priv->data_retry_limit = -1;
7935 priv->ieee_channels = NULL;
7936 priv->ieee_rates = NULL;
8318d78a 7937 priv->band = IEEE80211_BAND_2GHZ;
b481de9c
ZY		 7938
7939 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
7940 if (!err)
7941 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
7942 if (err) {
7943 printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
7944 goto out_pci_disable_device;
7945 }
7946
7947 pci_set_drvdata(pdev, priv);
7948 err = pci_request_regions(pdev, DRV_NAME);
7949 if (err)
7950 goto out_pci_disable_device;
6440adb5 7951
b481de9c
ZY		 7952 /* We disable the RETRY_TIMEOUT register (0x41) to keep
7953 * PCI Tx retries from interfering with C3 CPU state */
7954 pci_write_config_byte(pdev, 0x41, 0x00);
6440adb5 7955
b481de9c
ZY		 7956 priv->hw_base = pci_iomap(pdev, 0, 0);
7957 if (!priv->hw_base) {
7958 err = -ENODEV;
7959 goto out_pci_release_regions;
7960 }
7961
7962 IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
7963 (unsigned long long) pci_resource_len(pdev, 0));
7964 IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
7965
7966 /* Initialize module parameter values here */
7967
6440adb5 7968 /* Disable radio (SW RF KILL) via parameter when loading driver */
bb8c093b 7969 if (iwl3945_param_disable) {
b481de9c
ZY		 7970 set_bit(STATUS_RF_KILL_SW, &priv->status);
7971 IWL_DEBUG_INFO("Radio disabled.\n");
7972 }
7973
05c914fe 7974 priv->iw_mode = NL80211_IFTYPE_STATION;
b481de9c 7975
b481de9c 7976 printk(KERN_INFO DRV_NAME
82b9a121 7977 ": Detected Intel Wireless WiFi Link %s\n", priv->cfg->name);
b481de9c
ZY		 7978
7979 /* Device-specific setup */
bb8c093b 7980 if (iwl3945_hw_set_hw_setting(priv)) {
b481de9c 7981 IWL_ERROR("failed to set hw settings\n");
b481de9c
ZY		 7982 goto out_iounmap;
7983 }
7984
bb8c093b 7985 if (iwl3945_param_qos_enable)
b481de9c
ZY		 7986 priv->qos_data.qos_enable = 1;
7987
bb8c093b 7988 iwl3945_reset_qos(priv);
b481de9c
ZY		 7989
7990 priv->qos_data.qos_active = 0;
7991 priv->qos_data.qos_cap.val = 0;
b481de9c 7992
8318d78a 7993 iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
bb8c093b
CH		 7994 iwl3945_setup_deferred_work(priv);
7995 iwl3945_setup_rx_handlers(priv);
b481de9c
ZY		 7996
7997 priv->rates_mask = IWL_RATES_MASK;
7998 /* If power management is turned on, default to AC mode */
7999 priv->power_mode = IWL_POWER_AC;
8000 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
8001
0359facc 8002 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 8003 iwl3945_disable_interrupts(priv);
0359facc 8004 spin_unlock_irqrestore(&priv->lock, flags);
49df2b33 8005
bb8c093b 8006 err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c
ZY		 8007 if (err) {
8008 IWL_ERROR("failed to create sysfs device attributes\n");
b481de9c
ZY		 8009 goto out_release_irq;
8010 }
8011
5a66926a
ZY		 8012 /* nic init */
8013 iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
3ac7f146
TW		 8014 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
8015
8016 iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
8017 err = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
8018 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
8019 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
8020 if (err < 0) {
8021 IWL_DEBUG_INFO("Failed to init the card\n");
5a66926a 8022 goto out_remove_sysfs;
3ac7f146 8023 }
5a66926a
ZY		 8024 /* Read the EEPROM */
8025 err = iwl3945_eeprom_init(priv);
b481de9c 8026 if (err) {
5a66926a
ZY		 8027 IWL_ERROR("Unable to init EEPROM\n");
8028 goto out_remove_sysfs;
b481de9c 8029 }
5a66926a
ZY		 8030 /* MAC Address location in EEPROM same for 3945/4965 */
8031 get_eeprom_mac(priv, priv->mac_addr);
e174961c 8032 IWL_DEBUG_INFO("MAC address: %pM\n", priv->mac_addr);
5a66926a 8033 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
b481de9c 8034
849e0dce
RC		 8035 err = iwl3945_init_channel_map(priv);
8036 if (err) {
8037 IWL_ERROR("initializing regulatory failed: %d\n", err);
8038 goto out_remove_sysfs;
8039 }
8040
8041 err = iwl3945_init_geos(priv);
8042 if (err) {
8043 IWL_ERROR("initializing geos failed: %d\n", err);
8044 goto out_free_channel_map;
8045 }
849e0dce 8046
5a66926a
ZY		 8047 err = ieee80211_register_hw(priv->hw);
8048 if (err) {
8049 IWL_ERROR("Failed to register network device (error %d)\n", err);
849e0dce 8050 goto out_free_geos;
5a66926a 8051 }
b481de9c 8052
5a66926a
ZY		 8053 priv->hw->conf.beacon_int = 100;
8054 priv->mac80211_registered = 1;
8055 pci_save_state(pdev);
8056 pci_disable_device(pdev);
b481de9c 8057
ebef2008
AK		 8058 err = iwl3945_rfkill_init(priv);
8059 if (err)
8060 IWL_ERROR("Unable to initialize RFKILL system. "
8061 "Ignoring error: %d\n", err);
8062
b481de9c
ZY		 8063 return 0;
8064
849e0dce
RC		 8065 out_free_geos:
8066 iwl3945_free_geos(priv);
8067 out_free_channel_map:
8068 iwl3945_free_channel_map(priv);
5a66926a 8069 out_remove_sysfs:
bb8c093b 8070 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c
ZY		 8071
8072 out_release_irq:
b481de9c
ZY		 8073 destroy_workqueue(priv->workqueue);
8074 priv->workqueue = NULL;
bb8c093b 8075 iwl3945_unset_hw_setting(priv);
b481de9c
ZY		 8076
8077 out_iounmap:
8078 pci_iounmap(pdev, priv->hw_base);
8079 out_pci_release_regions:
8080 pci_release_regions(pdev);
8081 out_pci_disable_device:
8082 pci_disable_device(pdev);
8083 pci_set_drvdata(pdev, NULL);
8084 out_ieee80211_free_hw:
8085 ieee80211_free_hw(priv->hw);
8086 out:
8087 return err;
8088}
8089
c83dbf68 8090static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
b481de9c 8091{
bb8c093b 8092 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
0359facc 8093 unsigned long flags;
b481de9c
ZY		 8094
8095 if (!priv)
8096 return;
8097
8098 IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
8099
b481de9c 8100 set_bit(STATUS_EXIT_PENDING, &priv->status);
b24d22b1 8101
bb8c093b 8102 iwl3945_down(priv);
b481de9c 8103
0359facc
MA		 8104 /* make sure we flush any pending irq or
8105 * tasklet for the driver
8106 */
8107 spin_lock_irqsave(&priv->lock, flags);
8108 iwl3945_disable_interrupts(priv);
8109 spin_unlock_irqrestore(&priv->lock, flags);
8110
8111 iwl_synchronize_irq(priv);
8112
bb8c093b 8113 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 8114
ebef2008 8115 iwl3945_rfkill_unregister(priv);
bb8c093b 8116 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY		 8117
8118 if (priv->rxq.bd)
bb8c093b
CH		 8119 iwl3945_rx_queue_free(priv, &priv->rxq);
8120 iwl3945_hw_txq_ctx_free(priv);
b481de9c 8121
bb8c093b
CH		 8122 iwl3945_unset_hw_setting(priv);
8123 iwl3945_clear_stations_table(priv);
b481de9c 8124
3ac7f146 8125 if (priv->mac80211_registered)
b481de9c 8126 ieee80211_unregister_hw(priv->hw);
b481de9c 8127
6ef89d0a
MA		 8128 /*netif_stop_queue(dev); */
8129 flush_workqueue(priv->workqueue);
8130
bb8c093b 8131 /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
b481de9c
ZY		 8132 * priv->workqueue... so we can't take down the workqueue
8133 * until now... */
8134 destroy_workqueue(priv->workqueue);
8135 priv->workqueue = NULL;
8136
b481de9c
ZY		 8137 pci_iounmap(pdev, priv->hw_base);
8138 pci_release_regions(pdev);
8139 pci_disable_device(pdev);
8140 pci_set_drvdata(pdev, NULL);
8141
849e0dce
RC		 8142 iwl3945_free_channel_map(priv);
8143 iwl3945_free_geos(priv);
261415f7 8144 kfree(priv->scan);
b481de9c
ZY		 8145 if (priv->ibss_beacon)
8146 dev_kfree_skb(priv->ibss_beacon);
8147
8148 ieee80211_free_hw(priv->hw);
8149}
8150
8151#ifdef CONFIG_PM
8152
bb8c093b 8153static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
b481de9c 8154{
bb8c093b 8155 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c 8156
e655b9f0
ZY		 8157 if (priv->is_open) {
8158 set_bit(STATUS_IN_SUSPEND, &priv->status);
8159 iwl3945_mac_stop(priv->hw);
8160 priv->is_open = 1;
8161 }
b481de9c 8162
b481de9c
ZY		 8163 pci_set_power_state(pdev, PCI_D3hot);
8164
b481de9c
ZY		 8165 return 0;
8166}
8167
bb8c093b 8168static int iwl3945_pci_resume(struct pci_dev *pdev)
b481de9c 8169{
bb8c093b 8170 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c 8171
b481de9c 8172 pci_set_power_state(pdev, PCI_D0);
b481de9c 8173
e655b9f0
ZY		 8174 if (priv->is_open)
8175 iwl3945_mac_start(priv->hw);
b481de9c 8176
e655b9f0 8177 clear_bit(STATUS_IN_SUSPEND, &priv->status);
b481de9c
ZY		 8178 return 0;
8179}
8180
8181#endif /* CONFIG_PM */
8182
ebef2008 8183/*************** RFKILL FUNCTIONS **********/
80fcc9e2 8184#ifdef CONFIG_IWL3945_RFKILL
ebef2008
AK		 8185/* software rf-kill from user */
8186static int iwl3945_rfkill_soft_rf_kill(void *data, enum rfkill_state state)
8187{
8188 struct iwl3945_priv *priv = data;
8189 int err = 0;
8190
80fcc9e2 8191 if (!priv->rfkill)
ebef2008
AK		 8192 return 0;
8193
8194 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
8195 return 0;
8196
8197 IWL_DEBUG_RF_KILL("we recieved soft RFKILL set to state %d\n", state);
8198 mutex_lock(&priv->mutex);
8199
8200 switch (state) {
acdfe9b4 8201 case RFKILL_STATE_UNBLOCKED:
80fcc9e2 8202 if (iwl3945_is_rfkill_hw(priv)) {
ebef2008 8203 err = -EBUSY;
80fcc9e2
AG		 8204 goto out_unlock;
8205 }
8206 iwl3945_radio_kill_sw(priv, 0);
ebef2008 8207 break;
acdfe9b4 8208 case RFKILL_STATE_SOFT_BLOCKED:
ebef2008 8209 iwl3945_radio_kill_sw(priv, 1);
ebef2008 8210 break;
acdfe9b4
ZY		 8211 default:
8212 IWL_WARNING("we recieved unexpected RFKILL state %d\n", state);
8213 break;
ebef2008 8214 }
80fcc9e2 8215out_unlock:
ebef2008
AK		 8216 mutex_unlock(&priv->mutex);
8217
8218 return err;
8219}
8220
8221int iwl3945_rfkill_init(struct iwl3945_priv *priv)
8222{
8223 struct device *device = wiphy_dev(priv->hw->wiphy);
8224 int ret = 0;
8225
8226 BUG_ON(device == NULL);
8227
8228 IWL_DEBUG_RF_KILL("Initializing RFKILL.\n");
80fcc9e2
AG		 8229 priv->rfkill = rfkill_allocate(device, RFKILL_TYPE_WLAN);
8230 if (!priv->rfkill) {
ebef2008
AK		 8231 IWL_ERROR("Unable to allocate rfkill device.\n");
8232 ret = -ENOMEM;
8233 goto error;
8234 }
8235
80fcc9e2
AG		 8236 priv->rfkill->name = priv->cfg->name;
8237 priv->rfkill->data = priv;
8238 priv->rfkill->state = RFKILL_STATE_UNBLOCKED;
8239 priv->rfkill->toggle_radio = iwl3945_rfkill_soft_rf_kill;
8240 priv->rfkill->user_claim_unsupported = 1;
ebef2008 8241
80fcc9e2
AG		 8242 priv->rfkill->dev.class->suspend = NULL;
8243 priv->rfkill->dev.class->resume = NULL;
ebef2008 8244
80fcc9e2 8245 ret = rfkill_register(priv->rfkill);
ebef2008
AK		 8246 if (ret) {
8247 IWL_ERROR("Unable to register rfkill: %d\n", ret);
80fcc9e2 8248 goto freed_rfkill;
ebef2008
AK		 8249 }
8250
8251 IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
8252 return ret;
8253
ebef2008 8254freed_rfkill:
80fcc9e2
AG		 8255 if (priv->rfkill != NULL)
8256 rfkill_free(priv->rfkill);
8257 priv->rfkill = NULL;
ebef2008
AK		 8258
8259error:
8260 IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
8261 return ret;
8262}
8263
8264void iwl3945_rfkill_unregister(struct iwl3945_priv *priv)
8265{
80fcc9e2
AG		 8266 if (priv->rfkill)
8267 rfkill_unregister(priv->rfkill);
ebef2008 8268
80fcc9e2 8269 priv->rfkill = NULL;
ebef2008
AK		 8270}
8271
8272/* set rf-kill to the right state. */
8273void iwl3945_rfkill_set_hw_state(struct iwl3945_priv *priv)
8274{
8275
80fcc9e2
AG		 8276 if (!priv->rfkill)
8277 return;
8278
8279 if (iwl3945_is_rfkill_hw(priv)) {
8280 rfkill_force_state(priv->rfkill, RFKILL_STATE_HARD_BLOCKED);
ebef2008 8281 return;
80fcc9e2 8282 }
ebef2008 8283
80fcc9e2
AG		 8284 if (!iwl3945_is_rfkill_sw(priv))
8285 rfkill_force_state(priv->rfkill, RFKILL_STATE_UNBLOCKED);
ebef2008 8286 else
80fcc9e2 8287 rfkill_force_state(priv->rfkill, RFKILL_STATE_SOFT_BLOCKED);
ebef2008
AK		 8288}
8289#endif
8290
b481de9c
ZY		 8291/*****************************************************************************
8292 *
8293 * driver and module entry point
8294 *
8295 *****************************************************************************/
8296
bb8c093b 8297static struct pci_driver iwl3945_driver = {
b481de9c 8298 .name = DRV_NAME,
bb8c093b
CH		 8299 .id_table = iwl3945_hw_card_ids,
8300 .probe = iwl3945_pci_probe,
8301 .remove = __devexit_p(iwl3945_pci_remove),
b481de9c 8302#ifdef CONFIG_PM
bb8c093b
CH		 8303 .suspend = iwl3945_pci_suspend,
8304 .resume = iwl3945_pci_resume,
b481de9c
ZY		 8305#endif
8306};
8307
bb8c093b 8308static int __init iwl3945_init(void)
b481de9c
ZY		 8309{
8310
8311 int ret;
8312 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
8313 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2
RC		 8314
8315 ret = iwl3945_rate_control_register();
8316 if (ret) {
8317 IWL_ERROR("Unable to register rate control algorithm: %d\n", ret);
8318 return ret;
8319 }
8320
bb8c093b 8321 ret = pci_register_driver(&iwl3945_driver);
b481de9c
ZY		 8322 if (ret) {
8323 IWL_ERROR("Unable to initialize PCI module\n");
897e1cf2 8324 goto error_register;
b481de9c 8325 }
c8b0e6e1 8326#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8327 ret = driver_create_file(&iwl3945_driver.driver, &driver_attr_debug_level);
b481de9c
ZY		 8328 if (ret) {
8329 IWL_ERROR("Unable to create driver sysfs file\n");
897e1cf2 8330 goto error_debug;
b481de9c
ZY		 8331 }
8332#endif
8333
8334 return ret;
897e1cf2
RC		 8335
8336#ifdef CONFIG_IWL3945_DEBUG
8337error_debug:
8338 pci_unregister_driver(&iwl3945_driver);
8339#endif
8340error_register:
8341 iwl3945_rate_control_unregister();
8342 return ret;
b481de9c
ZY		 8343}
8344
bb8c093b 8345static void __exit iwl3945_exit(void)
b481de9c 8346{
c8b0e6e1 8347#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8348 driver_remove_file(&iwl3945_driver.driver, &driver_attr_debug_level);
b481de9c 8349#endif
bb8c093b 8350 pci_unregister_driver(&iwl3945_driver);
897e1cf2 8351 iwl3945_rate_control_unregister();
b481de9c
ZY		 8352}
8353
25cb6cad
ZY		 8354MODULE_FIRMWARE("iwlwifi-3945" IWL3945_UCODE_API ".ucode");
8355
bb8c093b 8356module_param_named(antenna, iwl3945_param_antenna, int, 0444);
b481de9c 8357MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
bb8c093b 8358module_param_named(disable, iwl3945_param_disable, int, 0444);
b481de9c 8359MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
bb8c093b 8360module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444);
b481de9c
ZY		 8361MODULE_PARM_DESC(hwcrypto,
8362 "using hardware crypto engine (default 0 [software])\n");
bb8c093b 8363module_param_named(debug, iwl3945_param_debug, int, 0444);
b481de9c 8364MODULE_PARM_DESC(debug, "debug output mask");
bb8c093b 8365module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444);
b481de9c
ZY		 8366MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
8367
bb8c093b 8368module_param_named(queues_num, iwl3945_param_queues_num, int, 0444);
b481de9c
ZY		 8369MODULE_PARM_DESC(queues_num, "number of hw queues.");
8370
8371/* QoS */
bb8c093b 8372module_param_named(qos_enable, iwl3945_param_qos_enable, int, 0444);
b481de9c
ZY		 8373MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
8374
bb8c093b
CH		 8375module_exit(iwl3945_exit);
8376module_init(iwl3945_init);
Linux kernel - Deliverables
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