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Merge commit 'origin/master' into next
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl3945-base.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
b481de9c
ZY		 30#include <linux/kernel.h>
31#include <linux/module.h>
b481de9c
ZY		 32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
36#include <linux/skbuff.h>
37#include <linux/netdevice.h>
38#include <linux/wireless.h>
39#include <linux/firmware.h>
b481de9c
ZY		 40#include <linux/etherdevice.h>
41#include <linux/if_arp.h>
42
43#include <net/ieee80211_radiotap.h>
7e272fcf 44#include <net/lib80211.h>
b481de9c
ZY		 45#include <net/mac80211.h>
46
47#include <asm/div64.h>
48
82b9a121 49#include "iwl-3945-core.h"
b481de9c
ZY		 50#include "iwl-3945.h"
51#include "iwl-helpers.h"
52
c8b0e6e1 53#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 54u32 iwl3945_debug_level;
b481de9c
ZY		 55#endif
56
bb8c093b
CH		 57static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
58 struct iwl3945_tx_queue *txq);
416e1438 59
b481de9c
ZY		 60/******************************************************************************
61 *
62 * module boiler plate
63 *
64 ******************************************************************************/
65
66/* module parameters */
6440adb5 67static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */
95aa194a 68static u32 iwl3945_param_debug; /* def: 0 = minimal debug log messages */
6440adb5 69static int iwl3945_param_disable; /* def: 0 = enable radio */
9fbab516 70static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */
6440adb5 71int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */
dfe7d458 72int iwl3945_param_queues_num = IWL39_MAX_NUM_QUEUES; /* def: 8 Tx queues */
b481de9c
ZY		 73
74/*
75 * module name, copyright, version, etc.
76 * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
77 */
78
79#define DRV_DESCRIPTION \
80"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
81
c8b0e6e1 82#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 83#define VD "d"
84#else
85#define VD
86#endif
87
c8b0e6e1 88#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 89#define VS "s"
90#else
91#define VS
92#endif
93
b9e0b449 94#define IWLWIFI_VERSION "1.2.26k" VD VS
eb7ae89c 95#define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation"
a7b75207 96#define DRV_AUTHOR "<ilw@linux.intel.com>"
b481de9c
ZY		 97#define DRV_VERSION IWLWIFI_VERSION
98
b481de9c
ZY		 99
100MODULE_DESCRIPTION(DRV_DESCRIPTION);
101MODULE_VERSION(DRV_VERSION);
a7b75207 102MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c
ZY		 103MODULE_LICENSE("GPL");
104
8318d78a
JB		 105static const struct ieee80211_supported_band *iwl3945_get_band(
106 struct iwl3945_priv *priv, enum ieee80211_band band)
b481de9c 107{
8318d78a 108 return priv->hw->wiphy->bands[band];
b481de9c
ZY		 109}
110
b481de9c
ZY		 111/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
112 * DMA services
113 *
114 * Theory of operation
115 *
6440adb5
CB		 116 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
117 * of buffer descriptors, each of which points to one or more data buffers for
118 * the device to read from or fill. Driver and device exchange status of each
119 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
120 * entries in each circular buffer, to protect against confusing empty and full
121 * queue states.
122 *
123 * The device reads or writes the data in the queues via the device's several
124 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
b481de9c
ZY		 125 *
126 * For Tx queue, there are low mark and high mark limits. If, after queuing
127 * the packet for Tx, free space become < low mark, Tx queue stopped. When
128 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
129 * Tx queue resumed.
130 *
6440adb5
CB		 131 * The 3945 operates with six queues: One receive queue, one transmit queue
132 * (#4) for sending commands to the device firmware, and four transmit queues
133 * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
b481de9c
ZY		 134 ***************************************************/
135
c54b679d 136int iwl3945_queue_space(const struct iwl3945_queue *q)
b481de9c 137{
fc4b6853 138 int s = q->read_ptr - q->write_ptr;
b481de9c 139
fc4b6853 140 if (q->read_ptr > q->write_ptr)
b481de9c
ZY		 141 s -= q->n_bd;
142
143 if (s <= 0)
144 s += q->n_window;
145 /* keep some reserve to not confuse empty and full situations */
146 s -= 2;
147 if (s < 0)
148 s = 0;
149 return s;
150}
151
c54b679d 152int iwl3945_x2_queue_used(const struct iwl3945_queue *q, int i)
b481de9c 153{
fc4b6853
TW		 154 return q->write_ptr > q->read_ptr ?
155 (i >= q->read_ptr && i < q->write_ptr) :
156 !(i < q->read_ptr && i >= q->write_ptr);
b481de9c
ZY		 157}
158
c54b679d 159
bb8c093b 160static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge)
b481de9c 161{
6440adb5 162 /* This is for scan command, the big buffer at end of command array */
b481de9c 163 if (is_huge)
6440adb5 164 return q->n_window; /* must be power of 2 */
b481de9c 165
6440adb5 166 /* Otherwise, use normal size buffers */
b481de9c
ZY		 167 return index & (q->n_window - 1);
168}
169
6440adb5
CB		 170/**
171 * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
172 */
bb8c093b 173static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q,
b481de9c
ZY		 174 int count, int slots_num, u32 id)
175{
176 q->n_bd = count;
177 q->n_window = slots_num;
178 q->id = id;
179
c54b679d
TW		 180 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
181 * and iwl_queue_dec_wrap are broken. */
b481de9c
ZY		 182 BUG_ON(!is_power_of_2(count));
183
184 /* slots_num must be power-of-two size, otherwise
185 * get_cmd_index is broken. */
186 BUG_ON(!is_power_of_2(slots_num));
187
188 q->low_mark = q->n_window / 4;
189 if (q->low_mark < 4)
190 q->low_mark = 4;
191
192 q->high_mark = q->n_window / 8;
193 if (q->high_mark < 2)
194 q->high_mark = 2;
195
fc4b6853 196 q->write_ptr = q->read_ptr = 0;
b481de9c
ZY		 197
198 return 0;
199}
200
6440adb5
CB		 201/**
202 * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
203 */
bb8c093b
CH		 204static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
205 struct iwl3945_tx_queue *txq, u32 id)
b481de9c
ZY		 206{
207 struct pci_dev *dev = priv->pci_dev;
208
6440adb5
CB		 209 /* Driver private data, only for Tx (not command) queues,
210 * not shared with device. */
b481de9c
ZY		 211 if (id != IWL_CMD_QUEUE_NUM) {
212 txq->txb = kmalloc(sizeof(txq->txb[0]) *
213 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
214 if (!txq->txb) {
01ebd063 215 IWL_ERROR("kmalloc for auxiliary BD "
b481de9c
ZY		 216 "structures failed\n");
217 goto error;
218 }
219 } else
220 txq->txb = NULL;
221
6440adb5
CB		 222 /* Circular buffer of transmit frame descriptors (TFDs),
223 * shared with device */
b481de9c
ZY		 224 txq->bd = pci_alloc_consistent(dev,
225 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
226 &txq->q.dma_addr);
227
228 if (!txq->bd) {
229 IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
230 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
231 goto error;
232 }
233 txq->q.id = id;
234
235 return 0;
236
237 error:
3ac7f146
TW		 238 kfree(txq->txb);
239 txq->txb = NULL;
b481de9c
ZY		 240
241 return -ENOMEM;
242}
243
6440adb5
CB		 244/**
245 * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
246 */
bb8c093b
CH		 247int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
248 struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
b481de9c
ZY		 249{
250 struct pci_dev *dev = priv->pci_dev;
251 int len;
252 int rc = 0;
253
6440adb5
CB		 254 /*
255 * Alloc buffer array for commands (Tx or other types of commands).
256 * For the command queue (#4), allocate command space + one big
257 * command for scan, since scan command is very huge; the system will
258 * not have two scans at the same time, so only one is needed.
259 * For data Tx queues (all other queues), no super-size command
260 * space is needed.
261 */
bb8c093b 262 len = sizeof(struct iwl3945_cmd) * slots_num;
b481de9c
ZY		 263 if (txq_id == IWL_CMD_QUEUE_NUM)
264 len += IWL_MAX_SCAN_SIZE;
265 txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
266 if (!txq->cmd)
267 return -ENOMEM;
268
6440adb5 269 /* Alloc driver data array and TFD circular buffer */
bb8c093b 270 rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
b481de9c
ZY		 271 if (rc) {
272 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
273
274 return -ENOMEM;
275 }
276 txq->need_update = 0;
277
278 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
c54b679d 279 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
b481de9c 280 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
6440adb5
CB		 281
282 /* Initialize queue high/low-water, head/tail indexes */
bb8c093b 283 iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
b481de9c 284
6440adb5 285 /* Tell device where to find queue, enable DMA channel. */
bb8c093b 286 iwl3945_hw_tx_queue_init(priv, txq);
b481de9c
ZY		 287
288 return 0;
289}
290
291/**
bb8c093b 292 * iwl3945_tx_queue_free - Deallocate DMA queue.
b481de9c
ZY		 293 * @txq: Transmit queue to deallocate.
294 *
295 * Empty queue by removing and destroying all BD's.
6440adb5
CB		 296 * Free all buffers.
297 * 0-fill, but do not free "txq" descriptor structure.
b481de9c 298 */
bb8c093b 299void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c 300{
bb8c093b 301 struct iwl3945_queue *q = &txq->q;
b481de9c
ZY		 302 struct pci_dev *dev = priv->pci_dev;
303 int len;
304
305 if (q->n_bd == 0)
306 return;
307
308 /* first, empty all BD's */
fc4b6853 309 for (; q->write_ptr != q->read_ptr;
c54b679d 310 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
bb8c093b 311 iwl3945_hw_txq_free_tfd(priv, txq);
b481de9c 312
bb8c093b 313 len = sizeof(struct iwl3945_cmd) * q->n_window;
b481de9c
ZY		 314 if (q->id == IWL_CMD_QUEUE_NUM)
315 len += IWL_MAX_SCAN_SIZE;
316
6440adb5 317 /* De-alloc array of command/tx buffers */
b481de9c
ZY		 318 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
319
6440adb5 320 /* De-alloc circular buffer of TFDs */
b481de9c 321 if (txq->q.n_bd)
bb8c093b 322 pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
b481de9c
ZY		 323 txq->q.n_bd, txq->bd, txq->q.dma_addr);
324
6440adb5 325 /* De-alloc array of per-TFD driver data */
3ac7f146
TW		 326 kfree(txq->txb);
327 txq->txb = NULL;
b481de9c 328
6440adb5 329 /* 0-fill queue descriptor structure */
b481de9c
ZY		 330 memset(txq, 0, sizeof(*txq));
331}
332
bb8c093b 333const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
b481de9c
ZY		 334
335/*************** STATION TABLE MANAGEMENT ****
9fbab516 336 * mac80211 should be examined to determine if sta_info is duplicating
b481de9c
ZY		 337 * the functionality provided here
338 */
339
340/**************************************************************/
01ebd063 341#if 0 /* temporary disable till we add real remove station */
6440adb5
CB		 342/**
343 * iwl3945_remove_station - Remove driver's knowledge of station.
344 *
345 * NOTE: This does not remove station from device's station table.
346 */
bb8c093b 347static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
b481de9c
ZY		 348{
349 int index = IWL_INVALID_STATION;
350 int i;
351 unsigned long flags;
352
353 spin_lock_irqsave(&priv->sta_lock, flags);
354
355 if (is_ap)
356 index = IWL_AP_ID;
357 else if (is_broadcast_ether_addr(addr))
358 index = priv->hw_setting.bcast_sta_id;
359 else
360 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
361 if (priv->stations[i].used &&
362 !compare_ether_addr(priv->stations[i].sta.sta.addr,
363 addr)) {
364 index = i;
365 break;
366 }
367
368 if (unlikely(index == IWL_INVALID_STATION))
369 goto out;
370
371 if (priv->stations[index].used) {
372 priv->stations[index].used = 0;
373 priv->num_stations--;
374 }
375
376 BUG_ON(priv->num_stations < 0);
377
378out:
379 spin_unlock_irqrestore(&priv->sta_lock, flags);
380 return 0;
381}
556f8db7 382#endif
6440adb5
CB		 383
384/**
385 * iwl3945_clear_stations_table - Clear the driver's station table
386 *
387 * NOTE: This does not clear or otherwise alter the device's station table.
388 */
bb8c093b 389static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
b481de9c
ZY		 390{
391 unsigned long flags;
392
393 spin_lock_irqsave(&priv->sta_lock, flags);
394
395 priv->num_stations = 0;
396 memset(priv->stations, 0, sizeof(priv->stations));
397
398 spin_unlock_irqrestore(&priv->sta_lock, flags);
399}
400
6440adb5
CB		 401/**
402 * iwl3945_add_station - Add station to station tables in driver and device
403 */
bb8c093b 404u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
b481de9c
ZY		 405{
406 int i;
407 int index = IWL_INVALID_STATION;
bb8c093b 408 struct iwl3945_station_entry *station;
b481de9c 409 unsigned long flags_spin;
c14c521e 410 u8 rate;
b481de9c
ZY		 411
412 spin_lock_irqsave(&priv->sta_lock, flags_spin);
413 if (is_ap)
414 index = IWL_AP_ID;
415 else if (is_broadcast_ether_addr(addr))
416 index = priv->hw_setting.bcast_sta_id;
417 else
418 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
419 if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
420 addr)) {
421 index = i;
422 break;
423 }
424
425 if (!priv->stations[i].used &&
426 index == IWL_INVALID_STATION)
427 index = i;
428 }
429
01ebd063 430 /* These two conditions has the same outcome but keep them separate
b481de9c
ZY		 431 since they have different meaning */
432 if (unlikely(index == IWL_INVALID_STATION)) {
433 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
434 return index;
435 }
436
437 if (priv->stations[index].used &&
438 !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
439 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
440 return index;
441 }
442
e174961c 443 IWL_DEBUG_ASSOC("Add STA ID %d: %pM\n", index, addr);
b481de9c
ZY		 444 station = &priv->stations[index];
445 station->used = 1;
446 priv->num_stations++;
447
6440adb5 448 /* Set up the REPLY_ADD_STA command to send to device */
bb8c093b 449 memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
b481de9c
ZY		 450 memcpy(station->sta.sta.addr, addr, ETH_ALEN);
451 station->sta.mode = 0;
452 station->sta.sta.sta_id = index;
453 station->sta.station_flags = 0;
454
8318d78a 455 if (priv->band == IEEE80211_BAND_5GHZ)
69946333
TW		 456 rate = IWL_RATE_6M_PLCP;
457 else
458 rate = IWL_RATE_1M_PLCP;
c14c521e
ZY		 459
460 /* Turn on both antennas for the station... */
461 station->sta.rate_n_flags =
bb8c093b 462 iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
c14c521e
ZY		 463 station->current_rate.rate_n_flags =
464 le16_to_cpu(station->sta.rate_n_flags);
465
b481de9c 466 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
6440adb5
CB		 467
468 /* Add station to device's station table */
bb8c093b 469 iwl3945_send_add_station(priv, &station->sta, flags);
b481de9c
ZY		 470 return index;
471
472}
473
474/*************** DRIVER STATUS FUNCTIONS *****/
475
bb8c093b 476static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
b481de9c
ZY		 477{
478 /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
479 * set but EXIT_PENDING is not */
480 return test_bit(STATUS_READY, &priv->status) &&
481 test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
482 !test_bit(STATUS_EXIT_PENDING, &priv->status);
483}
484
bb8c093b 485static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
b481de9c
ZY		 486{
487 return test_bit(STATUS_ALIVE, &priv->status);
488}
489
bb8c093b 490static inline int iwl3945_is_init(struct iwl3945_priv *priv)
b481de9c
ZY		 491{
492 return test_bit(STATUS_INIT, &priv->status);
493}
494
80fcc9e2
AG		 495static inline int iwl3945_is_rfkill_sw(struct iwl3945_priv *priv)
496{
497 return test_bit(STATUS_RF_KILL_SW, &priv->status);
498}
499
500static inline int iwl3945_is_rfkill_hw(struct iwl3945_priv *priv)
501{
502 return test_bit(STATUS_RF_KILL_HW, &priv->status);
503}
504
bb8c093b 505static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
b481de9c 506{
80fcc9e2
AG		 507 return iwl3945_is_rfkill_hw(priv) ||
508 iwl3945_is_rfkill_sw(priv);
b481de9c
ZY		 509}
510
bb8c093b 511static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
b481de9c
ZY		 512{
513
bb8c093b 514 if (iwl3945_is_rfkill(priv))
b481de9c
ZY		 515 return 0;
516
bb8c093b 517 return iwl3945_is_ready(priv);
b481de9c
ZY		 518}
519
520/*************** HOST COMMAND QUEUE FUNCTIONS *****/
521
c3056065 522#define IWL_CMD(x) case x: return #x
b481de9c
ZY		 523
524static const char *get_cmd_string(u8 cmd)
525{
526 switch (cmd) {
527 IWL_CMD(REPLY_ALIVE);
528 IWL_CMD(REPLY_ERROR);
529 IWL_CMD(REPLY_RXON);
530 IWL_CMD(REPLY_RXON_ASSOC);
531 IWL_CMD(REPLY_QOS_PARAM);
532 IWL_CMD(REPLY_RXON_TIMING);
533 IWL_CMD(REPLY_ADD_STA);
534 IWL_CMD(REPLY_REMOVE_STA);
535 IWL_CMD(REPLY_REMOVE_ALL_STA);
536 IWL_CMD(REPLY_3945_RX);
537 IWL_CMD(REPLY_TX);
538 IWL_CMD(REPLY_RATE_SCALE);
539 IWL_CMD(REPLY_LEDS_CMD);
540 IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
541 IWL_CMD(RADAR_NOTIFICATION);
542 IWL_CMD(REPLY_QUIET_CMD);
543 IWL_CMD(REPLY_CHANNEL_SWITCH);
544 IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
545 IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
546 IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
547 IWL_CMD(POWER_TABLE_CMD);
548 IWL_CMD(PM_SLEEP_NOTIFICATION);
549 IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
550 IWL_CMD(REPLY_SCAN_CMD);
551 IWL_CMD(REPLY_SCAN_ABORT_CMD);
552 IWL_CMD(SCAN_START_NOTIFICATION);
553 IWL_CMD(SCAN_RESULTS_NOTIFICATION);
554 IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
555 IWL_CMD(BEACON_NOTIFICATION);
556 IWL_CMD(REPLY_TX_BEACON);
557 IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
558 IWL_CMD(QUIET_NOTIFICATION);
559 IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
560 IWL_CMD(MEASURE_ABORT_NOTIFICATION);
561 IWL_CMD(REPLY_BT_CONFIG);
562 IWL_CMD(REPLY_STATISTICS_CMD);
563 IWL_CMD(STATISTICS_NOTIFICATION);
564 IWL_CMD(REPLY_CARD_STATE_CMD);
565 IWL_CMD(CARD_STATE_NOTIFICATION);
566 IWL_CMD(MISSED_BEACONS_NOTIFICATION);
567 default:
568 return "UNKNOWN";
569
570 }
571}
572
573#define HOST_COMPLETE_TIMEOUT (HZ / 2)
574
575/**
bb8c093b 576 * iwl3945_enqueue_hcmd - enqueue a uCode command
b481de9c
ZY		 577 * @priv: device private data point
578 * @cmd: a point to the ucode command structure
579 *
580 * The function returns < 0 values to indicate the operation is
581 * failed. On success, it turns the index (> 0) of command in the
582 * command queue.
583 */
bb8c093b 584static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c 585{
bb8c093b
CH		 586 struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
587 struct iwl3945_queue *q = &txq->q;
588 struct iwl3945_tfd_frame *tfd;
b481de9c 589 u32 *control_flags;
bb8c093b 590 struct iwl3945_cmd *out_cmd;
b481de9c
ZY		 591 u32 idx;
592 u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
593 dma_addr_t phys_addr;
594 int pad;
595 u16 count;
596 int ret;
597 unsigned long flags;
598
599 /* If any of the command structures end up being larger than
600 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
601 * we will need to increase the size of the TFD entries */
602 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
603 !(cmd->meta.flags & CMD_SIZE_HUGE));
604
c342a1b9
GG		 605
606 if (iwl3945_is_rfkill(priv)) {
607 IWL_DEBUG_INFO("Not sending command - RF KILL");
608 return -EIO;
609 }
610
bb8c093b 611 if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
b481de9c
ZY		 612 IWL_ERROR("No space for Tx\n");
613 return -ENOSPC;
614 }
615
616 spin_lock_irqsave(&priv->hcmd_lock, flags);
617
fc4b6853 618 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY		 619 memset(tfd, 0, sizeof(*tfd));
620
621 control_flags = (u32 *) tfd;
622
fc4b6853 623 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
b481de9c
ZY		 624 out_cmd = &txq->cmd[idx];
625
626 out_cmd->hdr.cmd = cmd->id;
627 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
628 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
629
630 /* At this point, the out_cmd now has all of the incoming cmd
631 * information */
632
633 out_cmd->hdr.flags = 0;
634 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
fc4b6853 635 INDEX_TO_SEQ(q->write_ptr));
b481de9c
ZY		 636 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
637 out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
638
639 phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
bb8c093b
CH		 640 offsetof(struct iwl3945_cmd, hdr);
641 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
b481de9c
ZY		 642
643 pad = U32_PAD(cmd->len);
644 count = TFD_CTL_COUNT_GET(*control_flags);
645 *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
646
647 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
648 "%d bytes at %d[%d]:%d\n",
649 get_cmd_string(out_cmd->hdr.cmd),
650 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
fc4b6853 651 fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
b481de9c
ZY		 652
653 txq->need_update = 1;
6440adb5
CB		 654
655 /* Increment and update queue's write index */
c54b679d 656 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
bb8c093b 657 ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 658
659 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
660 return ret ? ret : idx;
661}
662
bb8c093b 663static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c
ZY		 664{
665 int ret;
666
667 BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
668
669 /* An asynchronous command can not expect an SKB to be set. */
670 BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
671
672 /* An asynchronous command MUST have a callback. */
673 BUG_ON(!cmd->meta.u.callback);
674
675 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
676 return -EBUSY;
677
bb8c093b 678 ret = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c 679 if (ret < 0) {
bb8c093b 680 IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
b481de9c
ZY		 681 get_cmd_string(cmd->id), ret);
682 return ret;
683 }
684 return 0;
685}
686
bb8c093b 687static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c
ZY		 688{
689 int cmd_idx;
690 int ret;
b481de9c
ZY		 691
692 BUG_ON(cmd->meta.flags & CMD_ASYNC);
693
694 /* A synchronous command can not have a callback set. */
695 BUG_ON(cmd->meta.u.callback != NULL);
696
e5472978 697 if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) {
b481de9c
ZY		 698 IWL_ERROR("Error sending %s: Already sending a host command\n",
699 get_cmd_string(cmd->id));
e5472978
TW		 700 ret = -EBUSY;
701 goto out;
b481de9c
ZY		 702 }
703
704 set_bit(STATUS_HCMD_ACTIVE, &priv->status);
705
706 if (cmd->meta.flags & CMD_WANT_SKB)
707 cmd->meta.source = &cmd->meta;
708
bb8c093b 709 cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c
ZY		 710 if (cmd_idx < 0) {
711 ret = cmd_idx;
bb8c093b 712 IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
b481de9c
ZY		 713 get_cmd_string(cmd->id), ret);
714 goto out;
715 }
716
717 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
718 !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
719 HOST_COMPLETE_TIMEOUT);
720 if (!ret) {
721 if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
722 IWL_ERROR("Error sending %s: time out after %dms.\n",
723 get_cmd_string(cmd->id),
724 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
725
726 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
727 ret = -ETIMEDOUT;
728 goto cancel;
729 }
730 }
731
732 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
733 IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
734 get_cmd_string(cmd->id));
735 ret = -ECANCELED;
736 goto fail;
737 }
738 if (test_bit(STATUS_FW_ERROR, &priv->status)) {
739 IWL_DEBUG_INFO("Command %s failed: FW Error\n",
740 get_cmd_string(cmd->id));
741 ret = -EIO;
742 goto fail;
743 }
744 if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
745 IWL_ERROR("Error: Response NULL in '%s'\n",
746 get_cmd_string(cmd->id));
747 ret = -EIO;
73e1a65d 748 goto cancel;
b481de9c
ZY		 749 }
750
751 ret = 0;
752 goto out;
753
754cancel:
755 if (cmd->meta.flags & CMD_WANT_SKB) {
bb8c093b 756 struct iwl3945_cmd *qcmd;
b481de9c
ZY		 757
758 /* Cancel the CMD_WANT_SKB flag for the cmd in the
759 * TX cmd queue. Otherwise in case the cmd comes
760 * in later, it will possibly set an invalid
761 * address (cmd->meta.source). */
762 qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
763 qcmd->meta.flags &= ~CMD_WANT_SKB;
764 }
765fail:
766 if (cmd->meta.u.skb) {
767 dev_kfree_skb_any(cmd->meta.u.skb);
768 cmd->meta.u.skb = NULL;
769 }
770out:
e5472978 771 clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status);
b481de9c
ZY		 772 return ret;
773}
774
bb8c093b 775int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c 776{
b481de9c 777 if (cmd->meta.flags & CMD_ASYNC)
bb8c093b 778 return iwl3945_send_cmd_async(priv, cmd);
b481de9c 779
bb8c093b 780 return iwl3945_send_cmd_sync(priv, cmd);
b481de9c
ZY		 781}
782
bb8c093b 783int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
b481de9c 784{
bb8c093b 785 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 786 .id = id,
787 .len = len,
788 .data = data,
789 };
790
bb8c093b 791 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 792}
793
bb8c093b 794static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
b481de9c 795{
bb8c093b 796 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 797 .id = id,
798 .len = sizeof(val),
799 .data = &val,
800 };
801
bb8c093b 802 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 803}
804
bb8c093b 805int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
b481de9c 806{
bb8c093b 807 return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
b481de9c
ZY		 808}
809
b481de9c 810/**
bb8c093b 811 * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
8318d78a
JB		 812 * @band: 2.4 or 5 GHz band
813 * @channel: Any channel valid for the requested band
b481de9c 814
8318d78a 815 * In addition to setting the staging RXON, priv->band is also set.
b481de9c
ZY		 816 *
817 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
8318d78a 818 * in the staging RXON flag structure based on the band
b481de9c 819 */
8318d78a
JB		 820static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv,
821 enum ieee80211_band band,
822 u16 channel)
b481de9c 823{
8318d78a 824 if (!iwl3945_get_channel_info(priv, band, channel)) {
b481de9c 825 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
8318d78a 826 channel, band);
b481de9c
ZY		 827 return -EINVAL;
828 }
829
830 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
8318d78a 831 (priv->band == band))
b481de9c
ZY		 832 return 0;
833
834 priv->staging_rxon.channel = cpu_to_le16(channel);
8318d78a 835 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 836 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
837 else
838 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
839
8318d78a 840 priv->band = band;
b481de9c 841
8318d78a 842 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
b481de9c
ZY		 843
844 return 0;
845}
846
847/**
bb8c093b 848 * iwl3945_check_rxon_cmd - validate RXON structure is valid
b481de9c
ZY		 849 *
850 * NOTE: This is really only useful during development and can eventually
851 * be #ifdef'd out once the driver is stable and folks aren't actively
852 * making changes
853 */
bb8c093b 854static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon)
b481de9c
ZY		 855{
856 int error = 0;
857 int counter = 1;
858
859 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
860 error |= le32_to_cpu(rxon->flags &
861 (RXON_FLG_TGJ_NARROW_BAND_MSK |
862 RXON_FLG_RADAR_DETECT_MSK));
863 if (error)
864 IWL_WARNING("check 24G fields %d | %d\n",
865 counter++, error);
866 } else {
867 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
868 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
869 if (error)
870 IWL_WARNING("check 52 fields %d | %d\n",
871 counter++, error);
872 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
873 if (error)
874 IWL_WARNING("check 52 CCK %d | %d\n",
875 counter++, error);
876 }
877 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
878 if (error)
879 IWL_WARNING("check mac addr %d | %d\n", counter++, error);
880
881 /* make sure basic rates 6Mbps and 1Mbps are supported */
882 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
883 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
884 if (error)
885 IWL_WARNING("check basic rate %d | %d\n", counter++, error);
886
887 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
888 if (error)
889 IWL_WARNING("check assoc id %d | %d\n", counter++, error);
890
891 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
892 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
893 if (error)
894 IWL_WARNING("check CCK and short slot %d | %d\n",
895 counter++, error);
896
897 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
898 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
899 if (error)
900 IWL_WARNING("check CCK & auto detect %d | %d\n",
901 counter++, error);
902
903 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
904 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
905 if (error)
906 IWL_WARNING("check TGG and auto detect %d | %d\n",
907 counter++, error);
908
909 if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
910 error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
911 RXON_FLG_ANT_A_MSK)) == 0);
912 if (error)
913 IWL_WARNING("check antenna %d %d\n", counter++, error);
914
915 if (error)
916 IWL_WARNING("Tuning to channel %d\n",
917 le16_to_cpu(rxon->channel));
918
919 if (error) {
bb8c093b 920 IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
b481de9c
ZY		 921 return -1;
922 }
923 return 0;
924}
925
926/**
9fbab516 927 * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
01ebd063 928 * @priv: staging_rxon is compared to active_rxon
b481de9c 929 *
9fbab516
BC		 930 * If the RXON structure is changing enough to require a new tune,
931 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
932 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
b481de9c 933 */
bb8c093b 934static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
b481de9c
ZY		 935{
936
937 /* These items are only settable from the full RXON command */
5d1e2325 938 if (!(iwl3945_is_associated(priv)) ||
b481de9c
ZY		 939 compare_ether_addr(priv->staging_rxon.bssid_addr,
940 priv->active_rxon.bssid_addr) ||
941 compare_ether_addr(priv->staging_rxon.node_addr,
942 priv->active_rxon.node_addr) ||
943 compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
944 priv->active_rxon.wlap_bssid_addr) ||
945 (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
946 (priv->staging_rxon.channel != priv->active_rxon.channel) ||
947 (priv->staging_rxon.air_propagation !=
948 priv->active_rxon.air_propagation) ||
949 (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
950 return 1;
951
952 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
953 * be updated with the RXON_ASSOC command -- however only some
954 * flag transitions are allowed using RXON_ASSOC */
955
956 /* Check if we are not switching bands */
957 if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
958 (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
959 return 1;
960
961 /* Check if we are switching association toggle */
962 if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
963 (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
964 return 1;
965
966 return 0;
967}
968
bb8c093b 969static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
b481de9c
ZY		 970{
971 int rc = 0;
bb8c093b
CH		 972 struct iwl3945_rx_packet *res = NULL;
973 struct iwl3945_rxon_assoc_cmd rxon_assoc;
974 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 975 .id = REPLY_RXON_ASSOC,
976 .len = sizeof(rxon_assoc),
977 .meta.flags = CMD_WANT_SKB,
978 .data = &rxon_assoc,
979 };
bb8c093b
CH		 980 const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
981 const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
b481de9c
ZY		 982
983 if ((rxon1->flags == rxon2->flags) &&
984 (rxon1->filter_flags == rxon2->filter_flags) &&
985 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
986 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
987 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
988 return 0;
989 }
990
991 rxon_assoc.flags = priv->staging_rxon.flags;
992 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
993 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
994 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
995 rxon_assoc.reserved = 0;
996
bb8c093b 997 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 998 if (rc)
999 return rc;
1000
bb8c093b 1001 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1002 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1003 IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
1004 rc = -EIO;
1005 }
1006
1007 priv->alloc_rxb_skb--;
1008 dev_kfree_skb_any(cmd.meta.u.skb);
1009
1010 return rc;
1011}
1012
1013/**
bb8c093b 1014 * iwl3945_commit_rxon - commit staging_rxon to hardware
b481de9c 1015 *
01ebd063 1016 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
ZY		 1017 * the active_rxon structure is updated with the new data. This
1018 * function correctly transitions out of the RXON_ASSOC_MSK state if
1019 * a HW tune is required based on the RXON structure changes.
1020 */
bb8c093b 1021static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
b481de9c
ZY		 1022{
1023 /* cast away the const for active_rxon in this function */
bb8c093b 1024 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
b481de9c
ZY		 1025 int rc = 0;
1026
bb8c093b 1027 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 1028 return -1;
1029
1030 /* always get timestamp with Rx frame */
1031 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
1032
1033 /* select antenna */
1034 priv->staging_rxon.flags &=
1035 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1036 priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
1037
bb8c093b 1038 rc = iwl3945_check_rxon_cmd(&priv->staging_rxon);
b481de9c
ZY		 1039 if (rc) {
1040 IWL_ERROR("Invalid RXON configuration. Not committing.\n");
1041 return -EINVAL;
1042 }
1043
1044 /* If we don't need to send a full RXON, we can use
bb8c093b 1045 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 1046 * and other flags for the current radio configuration. */
bb8c093b
CH		 1047 if (!iwl3945_full_rxon_required(priv)) {
1048 rc = iwl3945_send_rxon_assoc(priv);
b481de9c
ZY		 1049 if (rc) {
1050 IWL_ERROR("Error setting RXON_ASSOC "
1051 "configuration (%d).\n", rc);
1052 return rc;
1053 }
1054
1055 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1056
1057 return 0;
1058 }
1059
1060 /* If we are currently associated and the new config requires
1061 * an RXON_ASSOC and the new config wants the associated mask enabled,
1062 * we must clear the associated from the active configuration
1063 * before we apply the new config */
bb8c093b 1064 if (iwl3945_is_associated(priv) &&
b481de9c
ZY		 1065 (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
1066 IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
1067 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1068
bb8c093b
CH		 1069 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
1070 sizeof(struct iwl3945_rxon_cmd),
b481de9c
ZY		 1071 &priv->active_rxon);
1072
1073 /* If the mask clearing failed then we set
1074 * active_rxon back to what it was previously */
1075 if (rc) {
1076 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1077 IWL_ERROR("Error clearing ASSOC_MSK on current "
1078 "configuration (%d).\n", rc);
1079 return rc;
1080 }
b481de9c
ZY		 1081 }
1082
1083 IWL_DEBUG_INFO("Sending RXON\n"
1084 "* with%s RXON_FILTER_ASSOC_MSK\n"
1085 "* channel = %d\n"
e174961c 1086 "* bssid = %pM\n",
b481de9c
ZY		 1087 ((priv->staging_rxon.filter_flags &
1088 RXON_FILTER_ASSOC_MSK) ? "" : "out"),
1089 le16_to_cpu(priv->staging_rxon.channel),
e174961c 1090 priv->staging_rxon.bssid_addr);
b481de9c
ZY		 1091
1092 /* Apply the new configuration */
bb8c093b
CH		 1093 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
1094 sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
b481de9c
ZY		 1095 if (rc) {
1096 IWL_ERROR("Error setting new configuration (%d).\n", rc);
1097 return rc;
1098 }
1099
1100 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1101
bb8c093b 1102 iwl3945_clear_stations_table(priv);
556f8db7 1103
b481de9c
ZY		 1104 /* If we issue a new RXON command which required a tune then we must
1105 * send a new TXPOWER command or we won't be able to Tx any frames */
bb8c093b 1106 rc = iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 1107 if (rc) {
1108 IWL_ERROR("Error setting Tx power (%d).\n", rc);
1109 return rc;
1110 }
1111
1112 /* Add the broadcast address so we can send broadcast frames */
bb8c093b 1113 if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
b481de9c
ZY		 1114 IWL_INVALID_STATION) {
1115 IWL_ERROR("Error adding BROADCAST address for transmit.\n");
1116 return -EIO;
1117 }
1118
1119 /* If we have set the ASSOC_MSK and we are in BSS mode then
1120 * add the IWL_AP_ID to the station rate table */
bb8c093b 1121 if (iwl3945_is_associated(priv) &&
05c914fe 1122 (priv->iw_mode == NL80211_IFTYPE_STATION))
bb8c093b 1123 if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
b481de9c
ZY		 1124 == IWL_INVALID_STATION) {
1125 IWL_ERROR("Error adding AP address for transmit.\n");
1126 return -EIO;
1127 }
1128
8318d78a 1129 /* Init the hardware's rate fallback order based on the band */
b481de9c
ZY		 1130 rc = iwl3945_init_hw_rate_table(priv);
1131 if (rc) {
1132 IWL_ERROR("Error setting HW rate table: %02X\n", rc);
1133 return -EIO;
1134 }
1135
1136 return 0;
1137}
1138
bb8c093b 1139static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
b481de9c 1140{
bb8c093b 1141 struct iwl3945_bt_cmd bt_cmd = {
b481de9c
ZY		 1142 .flags = 3,
1143 .lead_time = 0xAA,
1144 .max_kill = 1,
1145 .kill_ack_mask = 0,
1146 .kill_cts_mask = 0,
1147 };
1148
bb8c093b
CH		 1149 return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1150 sizeof(struct iwl3945_bt_cmd), &bt_cmd);
b481de9c
ZY		 1151}
1152
bb8c093b 1153static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
b481de9c
ZY		 1154{
1155 int rc = 0;
bb8c093b
CH		 1156 struct iwl3945_rx_packet *res;
1157 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 1158 .id = REPLY_SCAN_ABORT_CMD,
1159 .meta.flags = CMD_WANT_SKB,
1160 };
1161
1162 /* If there isn't a scan actively going on in the hardware
1163 * then we are in between scan bands and not actually
1164 * actively scanning, so don't send the abort command */
1165 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
1166 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1167 return 0;
1168 }
1169
bb8c093b 1170 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 1171 if (rc) {
1172 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1173 return rc;
1174 }
1175
bb8c093b 1176 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1177 if (res->u.status != CAN_ABORT_STATUS) {
1178 /* The scan abort will return 1 for success or
1179 * 2 for "failure". A failure condition can be
1180 * due to simply not being in an active scan which
1181 * can occur if we send the scan abort before we
1182 * the microcode has notified us that a scan is
1183 * completed. */
1184 IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
1185 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1186 clear_bit(STATUS_SCAN_HW, &priv->status);
1187 }
1188
1189 dev_kfree_skb_any(cmd.meta.u.skb);
1190
1191 return rc;
1192}
1193
bb8c093b
CH		 1194static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
1195 struct iwl3945_cmd *cmd,
b481de9c
ZY		 1196 struct sk_buff *skb)
1197{
1198 return 1;
1199}
1200
1201/*
1202 * CARD_STATE_CMD
1203 *
9fbab516 1204 * Use: Sets the device's internal card state to enable, disable, or halt
b481de9c
ZY		 1205 *
1206 * When in the 'enable' state the card operates as normal.
1207 * When in the 'disable' state, the card enters into a low power mode.
1208 * When in the 'halt' state, the card is shut down and must be fully
1209 * restarted to come back on.
1210 */
bb8c093b 1211static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
b481de9c 1212{
bb8c093b 1213 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 1214 .id = REPLY_CARD_STATE_CMD,
1215 .len = sizeof(u32),
1216 .data = &flags,
1217 .meta.flags = meta_flag,
1218 };
1219
1220 if (meta_flag & CMD_ASYNC)
bb8c093b 1221 cmd.meta.u.callback = iwl3945_card_state_sync_callback;
b481de9c 1222
bb8c093b 1223 return iwl3945_send_cmd(priv, &cmd);
b481de9c
ZY		 1224}
1225
bb8c093b
CH		 1226static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
1227 struct iwl3945_cmd *cmd, struct sk_buff *skb)
b481de9c 1228{
bb8c093b 1229 struct iwl3945_rx_packet *res = NULL;
b481de9c
ZY		 1230
1231 if (!skb) {
1232 IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
1233 return 1;
1234 }
1235
bb8c093b 1236 res = (struct iwl3945_rx_packet *)skb->data;
b481de9c
ZY		 1237 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1238 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1239 res->hdr.flags);
1240 return 1;
1241 }
1242
1243 switch (res->u.add_sta.status) {
1244 case ADD_STA_SUCCESS_MSK:
1245 break;
1246 default:
1247 break;
1248 }
1249
1250 /* We didn't cache the SKB; let the caller free it */
1251 return 1;
1252}
1253
bb8c093b
CH		 1254int iwl3945_send_add_station(struct iwl3945_priv *priv,
1255 struct iwl3945_addsta_cmd *sta, u8 flags)
b481de9c 1256{
bb8c093b 1257 struct iwl3945_rx_packet *res = NULL;
b481de9c 1258 int rc = 0;
bb8c093b 1259 struct iwl3945_host_cmd cmd = {
b481de9c 1260 .id = REPLY_ADD_STA,
bb8c093b 1261 .len = sizeof(struct iwl3945_addsta_cmd),
b481de9c
ZY		 1262 .meta.flags = flags,
1263 .data = sta,
1264 };
1265
1266 if (flags & CMD_ASYNC)
bb8c093b 1267 cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
b481de9c
ZY		 1268 else
1269 cmd.meta.flags |= CMD_WANT_SKB;
1270
bb8c093b 1271 rc = iwl3945_send_cmd(priv, &cmd);
b481de9c
ZY		 1272
1273 if (rc || (flags & CMD_ASYNC))
1274 return rc;
1275
bb8c093b 1276 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1277 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1278 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1279 res->hdr.flags);
1280 rc = -EIO;
1281 }
1282
1283 if (rc == 0) {
1284 switch (res->u.add_sta.status) {
1285 case ADD_STA_SUCCESS_MSK:
1286 IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
1287 break;
1288 default:
1289 rc = -EIO;
1290 IWL_WARNING("REPLY_ADD_STA failed\n");
1291 break;
1292 }
1293 }
1294
1295 priv->alloc_rxb_skb--;
1296 dev_kfree_skb_any(cmd.meta.u.skb);
1297
1298 return rc;
1299}
1300
bb8c093b 1301static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
b481de9c
ZY		 1302 struct ieee80211_key_conf *keyconf,
1303 u8 sta_id)
1304{
1305 unsigned long flags;
1306 __le16 key_flags = 0;
1307
1308 switch (keyconf->alg) {
1309 case ALG_CCMP:
1310 key_flags |= STA_KEY_FLG_CCMP;
1311 key_flags |= cpu_to_le16(
1312 keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
1313 key_flags &= ~STA_KEY_FLG_INVALID;
1314 break;
1315 case ALG_TKIP:
1316 case ALG_WEP:
b481de9c
ZY		 1317 default:
1318 return -EINVAL;
1319 }
1320 spin_lock_irqsave(&priv->sta_lock, flags);
1321 priv->stations[sta_id].keyinfo.alg = keyconf->alg;
1322 priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
1323 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
1324 keyconf->keylen);
1325
1326 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
1327 keyconf->keylen);
1328 priv->stations[sta_id].sta.key.key_flags = key_flags;
1329 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1330 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1331
1332 spin_unlock_irqrestore(&priv->sta_lock, flags);
1333
1334 IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
bb8c093b 1335 iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY		 1336 return 0;
1337}
1338
bb8c093b 1339static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
b481de9c
ZY		 1340{
1341 unsigned long flags;
1342
1343 spin_lock_irqsave(&priv->sta_lock, flags);
bb8c093b
CH		 1344 memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
1345 memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl3945_keyinfo));
b481de9c
ZY		 1346 priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
1347 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1348 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1349 spin_unlock_irqrestore(&priv->sta_lock, flags);
1350
1351 IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
bb8c093b 1352 iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY		 1353 return 0;
1354}
1355
bb8c093b 1356static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
b481de9c
ZY		 1357{
1358 struct list_head *element;
1359
1360 IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
1361 priv->frames_count);
1362
1363 while (!list_empty(&priv->free_frames)) {
1364 element = priv->free_frames.next;
1365 list_del(element);
bb8c093b 1366 kfree(list_entry(element, struct iwl3945_frame, list));
b481de9c
ZY		 1367 priv->frames_count--;
1368 }
1369
1370 if (priv->frames_count) {
1371 IWL_WARNING("%d frames still in use. Did we lose one?\n",
1372 priv->frames_count);
1373 priv->frames_count = 0;
1374 }
1375}
1376
bb8c093b 1377static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
b481de9c 1378{
bb8c093b 1379 struct iwl3945_frame *frame;
b481de9c
ZY		 1380 struct list_head *element;
1381 if (list_empty(&priv->free_frames)) {
1382 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
1383 if (!frame) {
1384 IWL_ERROR("Could not allocate frame!\n");
1385 return NULL;
1386 }
1387
1388 priv->frames_count++;
1389 return frame;
1390 }
1391
1392 element = priv->free_frames.next;
1393 list_del(element);
bb8c093b 1394 return list_entry(element, struct iwl3945_frame, list);
b481de9c
ZY		 1395}
1396
bb8c093b 1397static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
b481de9c
ZY		 1398{
1399 memset(frame, 0, sizeof(*frame));
1400 list_add(&frame->list, &priv->free_frames);
1401}
1402
bb8c093b 1403unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
b481de9c 1404 struct ieee80211_hdr *hdr,
73ec1cc2 1405 int left)
b481de9c
ZY		 1406{
1407
bb8c093b 1408 if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB		 1409 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
1410 (priv->iw_mode != NL80211_IFTYPE_AP)))
b481de9c
ZY		 1411 return 0;
1412
1413 if (priv->ibss_beacon->len > left)
1414 return 0;
1415
1416 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
1417
1418 return priv->ibss_beacon->len;
1419}
1420
c24f0817 1421static u8 iwl3945_rate_get_lowest_plcp(struct iwl3945_priv *priv)
b481de9c
ZY		 1422{
1423 u8 i;
c24f0817
KA		 1424 int rate_mask;
1425
1426 /* Set rate mask*/
1427 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
dbce56a4 1428 rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
c24f0817 1429 else
dbce56a4 1430 rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
b481de9c
ZY		 1431
1432 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
bb8c093b 1433 i = iwl3945_rates[i].next_ieee) {
b481de9c 1434 if (rate_mask & (1 << i))
bb8c093b 1435 return iwl3945_rates[i].plcp;
b481de9c
ZY		 1436 }
1437
c24f0817
KA		 1438 /* No valid rate was found. Assign the lowest one */
1439 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
1440 return IWL_RATE_1M_PLCP;
1441 else
1442 return IWL_RATE_6M_PLCP;
b481de9c
ZY		 1443}
1444
bb8c093b 1445static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
b481de9c 1446{
bb8c093b 1447 struct iwl3945_frame *frame;
b481de9c
ZY		 1448 unsigned int frame_size;
1449 int rc;
1450 u8 rate;
1451
bb8c093b 1452 frame = iwl3945_get_free_frame(priv);
b481de9c
ZY		 1453
1454 if (!frame) {
1455 IWL_ERROR("Could not obtain free frame buffer for beacon "
1456 "command.\n");
1457 return -ENOMEM;
1458 }
1459
c24f0817 1460 rate = iwl3945_rate_get_lowest_plcp(priv);
b481de9c 1461
bb8c093b 1462 frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 1463
bb8c093b 1464 rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY		 1465 &frame->u.cmd[0]);
1466
bb8c093b 1467 iwl3945_free_frame(priv, frame);
b481de9c
ZY		 1468
1469 return rc;
1470}
1471
1472/******************************************************************************
1473 *
1474 * EEPROM related functions
1475 *
1476 ******************************************************************************/
1477
bb8c093b 1478static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
b481de9c
ZY		 1479{
1480 memcpy(mac, priv->eeprom.mac_address, 6);
1481}
1482
74a3a250
RC		 1483/*
1484 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
1485 * embedded controller) as EEPROM reader; each read is a series of pulses
1486 * to/from the EEPROM chip, not a single event, so even reads could conflict
1487 * if they weren't arbitrated by some ownership mechanism. Here, the driver
1488 * simply claims ownership, which should be safe when this function is called
1489 * (i.e. before loading uCode!).
1490 */
1491static inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv)
1492{
1493 _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
1494 return 0;
1495}
1496
b481de9c 1497/**
bb8c093b 1498 * iwl3945_eeprom_init - read EEPROM contents
b481de9c 1499 *
6440adb5 1500 * Load the EEPROM contents from adapter into priv->eeprom
b481de9c
ZY		 1501 *
1502 * NOTE: This routine uses the non-debug IO access functions.
1503 */
bb8c093b 1504int iwl3945_eeprom_init(struct iwl3945_priv *priv)
b481de9c 1505{
58ff6d4d 1506 u16 *e = (u16 *)&priv->eeprom;
bb8c093b 1507 u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
b481de9c 1508 int sz = sizeof(priv->eeprom);
3d5717ad 1509 int ret;
b481de9c
ZY		 1510 u16 addr;
1511
1512 /* The EEPROM structure has several padding buffers within it
1513 * and when adding new EEPROM maps is subject to programmer errors
1514 * which may be very difficult to identify without explicitly
1515 * checking the resulting size of the eeprom map. */
1516 BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
1517
1518 if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
6f147926 1519 IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x\n", gp);
b481de9c
ZY		 1520 return -ENOENT;
1521 }
1522
6440adb5 1523 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
3d5717ad
ZY		 1524 ret = iwl3945_eeprom_acquire_semaphore(priv);
1525 if (ret < 0) {
91e17473 1526 IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
b481de9c
ZY		 1527 return -ENOENT;
1528 }
1529
1530 /* eeprom is an array of 16bit values */
1531 for (addr = 0; addr < sz; addr += sizeof(u16)) {
3d5717ad 1532 u32 r;
b481de9c 1533
3d5717ad
ZY		 1534 _iwl3945_write32(priv, CSR_EEPROM_REG,
1535 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
1536 _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
1537 ret = iwl3945_poll_direct_bit(priv, CSR_EEPROM_REG,
1538 CSR_EEPROM_REG_READ_VALID_MSK,
1539 IWL_EEPROM_ACCESS_TIMEOUT);
1540 if (ret < 0) {
6f147926 1541 IWL_ERROR("Time out reading EEPROM[%d]\n", addr);
3d5717ad 1542 return ret;
b481de9c 1543 }
3d5717ad
ZY		 1544
1545 r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
58ff6d4d 1546 e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
b481de9c
ZY		 1547 }
1548
1549 return 0;
1550}
1551
bb8c093b 1552static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
b481de9c
ZY		 1553{
1554 if (priv->hw_setting.shared_virt)
1555 pci_free_consistent(priv->pci_dev,
bb8c093b 1556 sizeof(struct iwl3945_shared),
b481de9c
ZY		 1557 priv->hw_setting.shared_virt,
1558 priv->hw_setting.shared_phys);
1559}
1560
1561/**
bb8c093b 1562 * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
b481de9c
ZY		 1563 *
1564 * return : set the bit for each supported rate insert in ie
1565 */
bb8c093b 1566static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
c7c46676 1567 u16 basic_rate, int *left)
b481de9c
ZY		 1568{
1569 u16 ret_rates = 0, bit;
1570 int i;
c7c46676
TW		 1571 u8 *cnt = ie;
1572 u8 *rates = ie + 1;
b481de9c
ZY		 1573
1574 for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
1575 if (bit & supported_rate) {
1576 ret_rates |= bit;
bb8c093b 1577 rates[*cnt] = iwl3945_rates[i].ieee |
c7c46676
TW		 1578 ((bit & basic_rate) ? 0x80 : 0x00);
1579 (*cnt)++;
1580 (*left)--;
1581 if ((*left <= 0) ||
1582 (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
b481de9c
ZY		 1583 break;
1584 }
1585 }
1586
1587 return ret_rates;
1588}
1589
1590/**
bb8c093b 1591 * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
b481de9c 1592 */
bb8c093b 1593static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
b481de9c 1594 struct ieee80211_mgmt *frame,
430cfe95 1595 int left)
b481de9c
ZY		 1596{
1597 int len = 0;
1598 u8 *pos = NULL;
c7c46676 1599 u16 active_rates, ret_rates, cck_rates;
b481de9c
ZY		 1600
1601 /* Make sure there is enough space for the probe request,
1602 * two mandatory IEs and the data */
1603 left -= 24;
1604 if (left < 0)
1605 return 0;
1606 len += 24;
1607
1608 frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
bb8c093b 1609 memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
b481de9c 1610 memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
bb8c093b 1611 memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
b481de9c
ZY		 1612 frame->seq_ctrl = 0;
1613
1614 /* fill in our indirect SSID IE */
1615 /* ...next IE... */
1616
1617 left -= 2;
1618 if (left < 0)
1619 return 0;
1620 len += 2;
1621 pos = &(frame->u.probe_req.variable[0]);
1622 *pos++ = WLAN_EID_SSID;
1623 *pos++ = 0;
1624
b481de9c
ZY		 1625 /* fill in supported rate */
1626 /* ...next IE... */
1627 left -= 2;
1628 if (left < 0)
1629 return 0;
c7c46676 1630
b481de9c
ZY		 1631 /* ... fill it in... */
1632 *pos++ = WLAN_EID_SUPP_RATES;
1633 *pos = 0;
c7c46676
TW		 1634
1635 priv->active_rate = priv->rates_mask;
1636 active_rates = priv->active_rate;
b481de9c
ZY		 1637 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1638
c7c46676 1639 cck_rates = IWL_CCK_RATES_MASK & active_rates;
bb8c093b 1640 ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
c7c46676
TW		 1641 priv->active_rate_basic, &left);
1642 active_rates &= ~ret_rates;
1643
bb8c093b 1644 ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676
TW		 1645 priv->active_rate_basic, &left);
1646 active_rates &= ~ret_rates;
1647
b481de9c
ZY		 1648 len += 2 + *pos;
1649 pos += (*pos) + 1;
c7c46676 1650 if (active_rates == 0)
b481de9c
ZY		 1651 goto fill_end;
1652
1653 /* fill in supported extended rate */
1654 /* ...next IE... */
1655 left -= 2;
1656 if (left < 0)
1657 return 0;
1658 /* ... fill it in... */
1659 *pos++ = WLAN_EID_EXT_SUPP_RATES;
1660 *pos = 0;
bb8c093b 1661 iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676 1662 priv->active_rate_basic, &left);
b481de9c
ZY		 1663 if (*pos > 0)
1664 len += 2 + *pos;
1665
1666 fill_end:
1667 return (u16)len;
1668}
1669
1670/*
1671 * QoS support
1672*/
bb8c093b
CH		 1673static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
1674 struct iwl3945_qosparam_cmd *qos)
b481de9c
ZY		 1675{
1676
bb8c093b
CH		 1677 return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
1678 sizeof(struct iwl3945_qosparam_cmd), qos);
b481de9c
ZY		 1679}
1680
bb8c093b 1681static void iwl3945_reset_qos(struct iwl3945_priv *priv)
b481de9c
ZY		 1682{
1683 u16 cw_min = 15;
1684 u16 cw_max = 1023;
1685 u8 aifs = 2;
1686 u8 is_legacy = 0;
1687 unsigned long flags;
1688 int i;
1689
1690 spin_lock_irqsave(&priv->lock, flags);
1691 priv->qos_data.qos_active = 0;
1692
6d1ef1a3
WT		 1693 /* QoS always active in AP and ADHOC mode
1694 * In STA mode wait for association
1695 */
1696 if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
1697 priv->iw_mode == NL80211_IFTYPE_AP)
1698 priv->qos_data.qos_active = 1;
1699 else
1700 priv->qos_data.qos_active = 0;
1701
1702
1703 /* check for legacy mode */
1704 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC &&
1705 (priv->active_rate & IWL_OFDM_RATES_MASK) == 0) ||
1706 (priv->iw_mode == NL80211_IFTYPE_STATION &&
1707 (priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK) == 0)) {
b481de9c
ZY		 1708 cw_min = 31;
1709 is_legacy = 1;
1710 }
1711
1712 if (priv->qos_data.qos_active)
1713 aifs = 3;
1714
1715 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
1716 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
1717 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
1718 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
1719 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
1720
1721 if (priv->qos_data.qos_active) {
1722 i = 1;
1723 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
1724 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
1725 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
1726 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
1727 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1728
1729 i = 2;
1730 priv->qos_data.def_qos_parm.ac[i].cw_min =
1731 cpu_to_le16((cw_min + 1) / 2 - 1);
1732 priv->qos_data.def_qos_parm.ac[i].cw_max =
1733 cpu_to_le16(cw_max);
1734 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1735 if (is_legacy)
1736 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1737 cpu_to_le16(6016);
1738 else
1739 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1740 cpu_to_le16(3008);
1741 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1742
1743 i = 3;
1744 priv->qos_data.def_qos_parm.ac[i].cw_min =
1745 cpu_to_le16((cw_min + 1) / 4 - 1);
1746 priv->qos_data.def_qos_parm.ac[i].cw_max =
1747 cpu_to_le16((cw_max + 1) / 2 - 1);
1748 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1749 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1750 if (is_legacy)
1751 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1752 cpu_to_le16(3264);
1753 else
1754 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1755 cpu_to_le16(1504);
1756 } else {
1757 for (i = 1; i < 4; i++) {
1758 priv->qos_data.def_qos_parm.ac[i].cw_min =
1759 cpu_to_le16(cw_min);
1760 priv->qos_data.def_qos_parm.ac[i].cw_max =
1761 cpu_to_le16(cw_max);
1762 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
1763 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
1764 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1765 }
1766 }
1767 IWL_DEBUG_QOS("set QoS to default \n");
1768
1769 spin_unlock_irqrestore(&priv->lock, flags);
1770}
1771
bb8c093b 1772static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
b481de9c
ZY		 1773{
1774 unsigned long flags;
1775
b481de9c
ZY		 1776 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1777 return;
1778
b481de9c
ZY		 1779 spin_lock_irqsave(&priv->lock, flags);
1780 priv->qos_data.def_qos_parm.qos_flags = 0;
1781
1782 if (priv->qos_data.qos_cap.q_AP.queue_request &&
1783 !priv->qos_data.qos_cap.q_AP.txop_request)
1784 priv->qos_data.def_qos_parm.qos_flags |=
1785 QOS_PARAM_FLG_TXOP_TYPE_MSK;
1786
1787 if (priv->qos_data.qos_active)
1788 priv->qos_data.def_qos_parm.qos_flags |=
1789 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
1790
1791 spin_unlock_irqrestore(&priv->lock, flags);
1792
bb8c093b 1793 if (force || iwl3945_is_associated(priv)) {
a96a27f9 1794 IWL_DEBUG_QOS("send QoS cmd with QoS active %d \n",
b481de9c
ZY		 1795 priv->qos_data.qos_active);
1796
bb8c093b 1797 iwl3945_send_qos_params_command(priv,
b481de9c
ZY		 1798 &(priv->qos_data.def_qos_parm));
1799 }
1800}
1801
b481de9c
ZY		 1802/*
1803 * Power management (not Tx power!) functions
1804 */
1805#define MSEC_TO_USEC 1024
1806
1807#define NOSLP __constant_cpu_to_le32(0)
1808#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK
1809#define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
1810#define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
1811 __constant_cpu_to_le32(X1), \
1812 __constant_cpu_to_le32(X2), \
1813 __constant_cpu_to_le32(X3), \
1814 __constant_cpu_to_le32(X4)}
1815
1816
1817/* default power management (not Tx power) table values */
a96a27f9 1818/* for TIM 0-10 */
bb8c093b 1819static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = {
b481de9c
ZY		 1820 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1821 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
1822 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
1823 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
1824 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
1825 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
1826};
1827
a96a27f9 1828/* for TIM > 10 */
bb8c093b 1829static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = {
b481de9c
ZY		 1830 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1831 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
1832 SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
1833 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
1834 SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
1835 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
1836 SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
1837 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
1838 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
1839 SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
1840};
1841
bb8c093b 1842int iwl3945_power_init_handle(struct iwl3945_priv *priv)
b481de9c
ZY		 1843{
1844 int rc = 0, i;
bb8c093b
CH		 1845 struct iwl3945_power_mgr *pow_data;
1846 int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC;
b481de9c
ZY		 1847 u16 pci_pm;
1848
1849 IWL_DEBUG_POWER("Initialize power \n");
1850
1851 pow_data = &(priv->power_data);
1852
1853 memset(pow_data, 0, sizeof(*pow_data));
1854
1855 pow_data->active_index = IWL_POWER_RANGE_0;
1856 pow_data->dtim_val = 0xffff;
1857
1858 memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
1859 memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
1860
1861 rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
1862 if (rc != 0)
1863 return 0;
1864 else {
bb8c093b 1865 struct iwl3945_powertable_cmd *cmd;
b481de9c
ZY		 1866
1867 IWL_DEBUG_POWER("adjust power command flags\n");
1868
1869 for (i = 0; i < IWL_POWER_AC; i++) {
1870 cmd = &pow_data->pwr_range_0[i].cmd;
1871
1872 if (pci_pm & 0x1)
1873 cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
1874 else
1875 cmd->flags |= IWL_POWER_PCI_PM_MSK;
1876 }
1877 }
1878 return rc;
1879}
1880
bb8c093b
CH		 1881static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
1882 struct iwl3945_powertable_cmd *cmd, u32 mode)
b481de9c
ZY		 1883{
1884 int rc = 0, i;
1885 u8 skip;
1886 u32 max_sleep = 0;
bb8c093b 1887 struct iwl3945_power_vec_entry *range;
b481de9c 1888 u8 period = 0;
bb8c093b 1889 struct iwl3945_power_mgr *pow_data;
b481de9c
ZY		 1890
1891 if (mode > IWL_POWER_INDEX_5) {
1892 IWL_DEBUG_POWER("Error invalid power mode \n");
1893 return -1;
1894 }
1895 pow_data = &(priv->power_data);
1896
1897 if (pow_data->active_index == IWL_POWER_RANGE_0)
1898 range = &pow_data->pwr_range_0[0];
1899 else
1900 range = &pow_data->pwr_range_1[1];
1901
bb8c093b 1902 memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
b481de9c
ZY		 1903
1904#ifdef IWL_MAC80211_DISABLE
1905 if (priv->assoc_network != NULL) {
1906 unsigned long flags;
1907
1908 period = priv->assoc_network->tim.tim_period;
1909 }
1910#endif /*IWL_MAC80211_DISABLE */
1911 skip = range[mode].no_dtim;
1912
1913 if (period == 0) {
1914 period = 1;
1915 skip = 0;
1916 }
1917
1918 if (skip == 0) {
1919 max_sleep = period;
1920 cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
1921 } else {
1922 __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
1923 max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
1924 cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
1925 }
1926
1927 for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
1928 if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
1929 cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
1930 }
1931
1932 IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
1933 IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
1934 IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
1935 IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
1936 le32_to_cpu(cmd->sleep_interval[0]),
1937 le32_to_cpu(cmd->sleep_interval[1]),
1938 le32_to_cpu(cmd->sleep_interval[2]),
1939 le32_to_cpu(cmd->sleep_interval[3]),
1940 le32_to_cpu(cmd->sleep_interval[4]));
1941
1942 return rc;
1943}
1944
bb8c093b 1945static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
b481de9c 1946{
9a62f73b 1947 u32 uninitialized_var(final_mode);
b481de9c 1948 int rc;
bb8c093b 1949 struct iwl3945_powertable_cmd cmd;
b481de9c
ZY		 1950
1951 /* If on battery, set to 3,
01ebd063 1952 * if plugged into AC power, set to CAM ("continuously aware mode"),
b481de9c
ZY		 1953 * else user level */
1954 switch (mode) {
1955 case IWL_POWER_BATTERY:
1956 final_mode = IWL_POWER_INDEX_3;
1957 break;
1958 case IWL_POWER_AC:
1959 final_mode = IWL_POWER_MODE_CAM;
1960 break;
1961 default:
1962 final_mode = mode;
1963 break;
1964 }
1965
bb8c093b 1966 iwl3945_update_power_cmd(priv, &cmd, final_mode);
b481de9c 1967
bb8c093b 1968 rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
b481de9c
ZY		 1969
1970 if (final_mode == IWL_POWER_MODE_CAM)
1971 clear_bit(STATUS_POWER_PMI, &priv->status);
1972 else
1973 set_bit(STATUS_POWER_PMI, &priv->status);
1974
1975 return rc;
1976}
1977
b481de9c 1978/**
bb8c093b 1979 * iwl3945_scan_cancel - Cancel any currently executing HW scan
b481de9c
ZY		 1980 *
1981 * NOTE: priv->mutex is not required before calling this function
1982 */
bb8c093b 1983static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
b481de9c
ZY		 1984{
1985 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
1986 clear_bit(STATUS_SCANNING, &priv->status);
1987 return 0;
1988 }
1989
1990 if (test_bit(STATUS_SCANNING, &priv->status)) {
1991 if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
1992 IWL_DEBUG_SCAN("Queuing scan abort.\n");
1993 set_bit(STATUS_SCAN_ABORTING, &priv->status);
1994 queue_work(priv->workqueue, &priv->abort_scan);
1995
1996 } else
1997 IWL_DEBUG_SCAN("Scan abort already in progress.\n");
1998
1999 return test_bit(STATUS_SCANNING, &priv->status);
2000 }
2001
2002 return 0;
2003}
2004
2005/**
bb8c093b 2006 * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
b481de9c
ZY		 2007 * @ms: amount of time to wait (in milliseconds) for scan to abort
2008 *
2009 * NOTE: priv->mutex must be held before calling this function
2010 */
bb8c093b 2011static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
b481de9c
ZY		 2012{
2013 unsigned long now = jiffies;
2014 int ret;
2015
bb8c093b 2016 ret = iwl3945_scan_cancel(priv);
b481de9c
ZY		 2017 if (ret && ms) {
2018 mutex_unlock(&priv->mutex);
2019 while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
2020 test_bit(STATUS_SCANNING, &priv->status))
2021 msleep(1);
2022 mutex_lock(&priv->mutex);
2023
2024 return test_bit(STATUS_SCANNING, &priv->status);
2025 }
2026
2027 return ret;
2028}
2029
b481de9c
ZY		 2030#define MAX_UCODE_BEACON_INTERVAL 1024
2031#define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
2032
bb8c093b 2033static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
b481de9c
ZY		 2034{
2035 u16 new_val = 0;
2036 u16 beacon_factor = 0;
2037
2038 beacon_factor =
2039 (beacon_val + MAX_UCODE_BEACON_INTERVAL)
2040 / MAX_UCODE_BEACON_INTERVAL;
2041 new_val = beacon_val / beacon_factor;
2042
2043 return cpu_to_le16(new_val);
2044}
2045
bb8c093b 2046static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
b481de9c
ZY		 2047{
2048 u64 interval_tm_unit;
2049 u64 tsf, result;
2050 unsigned long flags;
2051 struct ieee80211_conf *conf = NULL;
2052 u16 beacon_int = 0;
2053
2054 conf = ieee80211_get_hw_conf(priv->hw);
2055
2056 spin_lock_irqsave(&priv->lock, flags);
2057 priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
2058 priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
2059
2060 priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
2061
2062 tsf = priv->timestamp1;
2063 tsf = ((tsf << 32) | priv->timestamp0);
2064
2065 beacon_int = priv->beacon_int;
2066 spin_unlock_irqrestore(&priv->lock, flags);
2067
05c914fe 2068 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
b481de9c
ZY		 2069 if (beacon_int == 0) {
2070 priv->rxon_timing.beacon_interval = cpu_to_le16(100);
2071 priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
2072 } else {
2073 priv->rxon_timing.beacon_interval =
2074 cpu_to_le16(beacon_int);
2075 priv->rxon_timing.beacon_interval =
bb8c093b 2076 iwl3945_adjust_beacon_interval(
b481de9c
ZY		 2077 le16_to_cpu(priv->rxon_timing.beacon_interval));
2078 }
2079
2080 priv->rxon_timing.atim_window = 0;
2081 } else {
2082 priv->rxon_timing.beacon_interval =
bb8c093b 2083 iwl3945_adjust_beacon_interval(conf->beacon_int);
b481de9c
ZY		 2084 /* TODO: we need to get atim_window from upper stack
2085 * for now we set to 0 */
2086 priv->rxon_timing.atim_window = 0;
2087 }
2088
2089 interval_tm_unit =
2090 (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
2091 result = do_div(tsf, interval_tm_unit);
2092 priv->rxon_timing.beacon_init_val =
2093 cpu_to_le32((u32) ((u64) interval_tm_unit - result));
2094
2095 IWL_DEBUG_ASSOC
2096 ("beacon interval %d beacon timer %d beacon tim %d\n",
2097 le16_to_cpu(priv->rxon_timing.beacon_interval),
2098 le32_to_cpu(priv->rxon_timing.beacon_init_val),
2099 le16_to_cpu(priv->rxon_timing.atim_window));
2100}
2101
bb8c093b 2102static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
b481de9c 2103{
bb8c093b 2104 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 2105 IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
2106 return -EIO;
2107 }
2108
2109 if (test_bit(STATUS_SCANNING, &priv->status)) {
2110 IWL_DEBUG_SCAN("Scan already in progress.\n");
2111 return -EAGAIN;
2112 }
2113
2114 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2115 IWL_DEBUG_SCAN("Scan request while abort pending. "
2116 "Queuing.\n");
2117 return -EAGAIN;
2118 }
2119
2120 IWL_DEBUG_INFO("Starting scan...\n");
66b5004d
RR		 2121 if (priv->cfg->sku & IWL_SKU_G)
2122 priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ);
2123 if (priv->cfg->sku & IWL_SKU_A)
2124 priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ);
b481de9c
ZY		 2125 set_bit(STATUS_SCANNING, &priv->status);
2126 priv->scan_start = jiffies;
2127 priv->scan_pass_start = priv->scan_start;
2128
2129 queue_work(priv->workqueue, &priv->request_scan);
2130
2131 return 0;
2132}
2133
bb8c093b 2134static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
b481de9c 2135{
bb8c093b 2136 struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
b481de9c
ZY		 2137
2138 if (hw_decrypt)
2139 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
2140 else
2141 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
2142
2143 return 0;
2144}
2145
8318d78a
JB		 2146static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv,
2147 enum ieee80211_band band)
b481de9c 2148{
8318d78a 2149 if (band == IEEE80211_BAND_5GHZ) {
b481de9c
ZY		 2150 priv->staging_rxon.flags &=
2151 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
2152 | RXON_FLG_CCK_MSK);
2153 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2154 } else {
bb8c093b 2155 /* Copied from iwl3945_bg_post_associate() */
b481de9c
ZY		 2156 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2157 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2158 else
2159 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2160
05c914fe 2161 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY		 2162 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2163
2164 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
2165 priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
2166 priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
2167 }
2168}
2169
2170/*
01ebd063 2171 * initialize rxon structure with default values from eeprom
b481de9c 2172 */
60294de3
ZY		 2173static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv,
2174 int mode)
b481de9c 2175{
bb8c093b 2176 const struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 2177
2178 memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
2179
60294de3 2180 switch (mode) {
05c914fe 2181 case NL80211_IFTYPE_AP:
b481de9c
ZY		 2182 priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
2183 break;
2184
05c914fe 2185 case NL80211_IFTYPE_STATION:
b481de9c
ZY		 2186 priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
2187 priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
2188 break;
2189
05c914fe 2190 case NL80211_IFTYPE_ADHOC:
b481de9c
ZY		 2191 priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
2192 priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
2193 priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
2194 RXON_FILTER_ACCEPT_GRP_MSK;
2195 break;
2196
05c914fe 2197 case NL80211_IFTYPE_MONITOR:
b481de9c
ZY		 2198 priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
2199 priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
2200 RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
2201 break;
69dc5d9d 2202 default:
60294de3 2203 IWL_ERROR("Unsupported interface type %d\n", mode);
69dc5d9d 2204 break;
b481de9c
ZY		 2205 }
2206
2207#if 0
2208 /* TODO: Figure out when short_preamble would be set and cache from
2209 * that */
2210 if (!hw_to_local(priv->hw)->short_preamble)
2211 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2212 else
2213 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2214#endif
2215
8318d78a 2216 ch_info = iwl3945_get_channel_info(priv, priv->band,
25b3f57c 2217 le16_to_cpu(priv->active_rxon.channel));
b481de9c
ZY		 2218
2219 if (!ch_info)
2220 ch_info = &priv->channel_info[0];
2221
2222 /*
2223 * in some case A channels are all non IBSS
2224 * in this case force B/G channel
2225 */
60294de3 2226 if ((mode == NL80211_IFTYPE_ADHOC) && !(is_channel_ibss(ch_info)))
b481de9c
ZY		 2227 ch_info = &priv->channel_info[0];
2228
2229 priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
2230 if (is_channel_a_band(ch_info))
8318d78a 2231 priv->band = IEEE80211_BAND_5GHZ;
b481de9c 2232 else
8318d78a 2233 priv->band = IEEE80211_BAND_2GHZ;
b481de9c 2234
8318d78a 2235 iwl3945_set_flags_for_phymode(priv, priv->band);
b481de9c
ZY		 2236
2237 priv->staging_rxon.ofdm_basic_rates =
2238 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2239 priv->staging_rxon.cck_basic_rates =
2240 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2241}
2242
bb8c093b 2243static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
b481de9c 2244{
05c914fe 2245 if (mode == NL80211_IFTYPE_ADHOC) {
bb8c093b 2246 const struct iwl3945_channel_info *ch_info;
b481de9c 2247
bb8c093b 2248 ch_info = iwl3945_get_channel_info(priv,
8318d78a 2249 priv->band,
b481de9c
ZY		 2250 le16_to_cpu(priv->staging_rxon.channel));
2251
2252 if (!ch_info || !is_channel_ibss(ch_info)) {
2253 IWL_ERROR("channel %d not IBSS channel\n",
2254 le16_to_cpu(priv->staging_rxon.channel));
2255 return -EINVAL;
2256 }
2257 }
2258
60294de3 2259 iwl3945_connection_init_rx_config(priv, mode);
b481de9c
ZY		 2260 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2261
bb8c093b 2262 iwl3945_clear_stations_table(priv);
b481de9c 2263
a96a27f9 2264 /* don't commit rxon if rf-kill is on*/
fde3571f
MA		 2265 if (!iwl3945_is_ready_rf(priv))
2266 return -EAGAIN;
2267
2268 cancel_delayed_work(&priv->scan_check);
2269 if (iwl3945_scan_cancel_timeout(priv, 100)) {
2270 IWL_WARNING("Aborted scan still in progress after 100ms\n");
2271 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
2272 return -EAGAIN;
2273 }
2274
bb8c093b 2275 iwl3945_commit_rxon(priv);
b481de9c
ZY		 2276
2277 return 0;
2278}
2279
bb8c093b 2280static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
e039fa4a 2281 struct ieee80211_tx_info *info,
bb8c093b 2282 struct iwl3945_cmd *cmd,
b481de9c
ZY		 2283 struct sk_buff *skb_frag,
2284 int last_frag)
2285{
1c014420 2286 struct iwl3945_hw_key *keyinfo =
e039fa4a 2287 &priv->stations[info->control.hw_key->hw_key_idx].keyinfo;
b481de9c
ZY		 2288
2289 switch (keyinfo->alg) {
2290 case ALG_CCMP:
2291 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
2292 memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
a96a27f9 2293 IWL_DEBUG_TX("tx_cmd with AES hwcrypto\n");
b481de9c
ZY		 2294 break;
2295
2296 case ALG_TKIP:
2297#if 0
2298 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
2299
2300 if (last_frag)
2301 memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
2302 8);
2303 else
2304 memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
2305#endif
2306 break;
2307
2308 case ALG_WEP:
2309 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
e039fa4a 2310 (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
b481de9c
ZY		 2311
2312 if (keyinfo->keylen == 13)
2313 cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
2314
2315 memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
2316
2317 IWL_DEBUG_TX("Configuring packet for WEP encryption "
e039fa4a 2318 "with key %d\n", info->control.hw_key->hw_key_idx);
b481de9c
ZY		 2319 break;
2320
b481de9c
ZY		 2321 default:
2322 printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
2323 break;
2324 }
2325}
2326
2327/*
2328 * handle build REPLY_TX command notification.
2329 */
bb8c093b
CH		 2330static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
2331 struct iwl3945_cmd *cmd,
e039fa4a 2332 struct ieee80211_tx_info *info,
b481de9c
ZY		 2333 struct ieee80211_hdr *hdr,
2334 int is_unicast, u8 std_id)
2335{
fd7c8a40 2336 __le16 fc = hdr->frame_control;
b481de9c 2337 __le32 tx_flags = cmd->cmd.tx.tx_flags;
e6a9854b 2338 u8 rc_flags = info->control.rates[0].flags;
b481de9c
ZY		 2339
2340 cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e039fa4a 2341 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
b481de9c 2342 tx_flags |= TX_CMD_FLG_ACK_MSK;
fd7c8a40 2343 if (ieee80211_is_mgmt(fc))
b481de9c 2344 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
fd7c8a40 2345 if (ieee80211_is_probe_resp(fc) &&
b481de9c
ZY		 2346 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
2347 tx_flags |= TX_CMD_FLG_TSF_MSK;
2348 } else {
2349 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
2350 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2351 }
2352
2353 cmd->cmd.tx.sta_id = std_id;
8b7b1e05 2354 if (ieee80211_has_morefrags(fc))
b481de9c
ZY		 2355 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
2356
fd7c8a40
HH		 2357 if (ieee80211_is_data_qos(fc)) {
2358 u8 *qc = ieee80211_get_qos_ctl(hdr);
54dbb525 2359 cmd->cmd.tx.tid_tspec = qc[0] & 0xf;
b481de9c 2360 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 2361 } else {
b481de9c 2362 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 2363 }
b481de9c 2364
e6a9854b 2365 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
b481de9c
ZY		 2366 tx_flags |= TX_CMD_FLG_RTS_MSK;
2367 tx_flags &= ~TX_CMD_FLG_CTS_MSK;
e6a9854b 2368 } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
b481de9c
ZY		 2369 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2370 tx_flags |= TX_CMD_FLG_CTS_MSK;
2371 }
2372
2373 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
2374 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
2375
2376 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
fd7c8a40
HH		 2377 if (ieee80211_is_mgmt(fc)) {
2378 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
bc434dd2 2379 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
b481de9c 2380 else
bc434dd2 2381 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
ab53d8af 2382 } else {
b481de9c 2383 cmd->cmd.tx.timeout.pm_frame_timeout = 0;
ab53d8af
MA		 2384#ifdef CONFIG_IWL3945_LEDS
2385 priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
2386#endif
2387 }
b481de9c
ZY		 2388
2389 cmd->cmd.tx.driver_txop = 0;
2390 cmd->cmd.tx.tx_flags = tx_flags;
2391 cmd->cmd.tx.next_frame_len = 0;
2392}
2393
6440adb5
CB		 2394/**
2395 * iwl3945_get_sta_id - Find station's index within station table
2396 */
bb8c093b 2397static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
b481de9c
ZY		 2398{
2399 int sta_id;
2400 u16 fc = le16_to_cpu(hdr->frame_control);
2401
6440adb5 2402 /* If this frame is broadcast or management, use broadcast station id */
b481de9c
ZY		 2403 if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
2404 is_multicast_ether_addr(hdr->addr1))
2405 return priv->hw_setting.bcast_sta_id;
2406
2407 switch (priv->iw_mode) {
2408
6440adb5
CB		 2409 /* If we are a client station in a BSS network, use the special
2410 * AP station entry (that's the only station we communicate with) */
05c914fe 2411 case NL80211_IFTYPE_STATION:
b481de9c
ZY		 2412 return IWL_AP_ID;
2413
2414 /* If we are an AP, then find the station, or use BCAST */
05c914fe 2415 case NL80211_IFTYPE_AP:
bb8c093b 2416 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY		 2417 if (sta_id != IWL_INVALID_STATION)
2418 return sta_id;
2419 return priv->hw_setting.bcast_sta_id;
2420
6440adb5
CB		 2421 /* If this frame is going out to an IBSS network, find the station,
2422 * or create a new station table entry */
05c914fe 2423 case NL80211_IFTYPE_ADHOC: {
6440adb5 2424 /* Create new station table entry */
bb8c093b 2425 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY		 2426 if (sta_id != IWL_INVALID_STATION)
2427 return sta_id;
2428
bb8c093b 2429 sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
b481de9c
ZY		 2430
2431 if (sta_id != IWL_INVALID_STATION)
2432 return sta_id;
2433
e174961c 2434 IWL_DEBUG_DROP("Station %pM not in station map. "
b481de9c 2435 "Defaulting to broadcast...\n",
e174961c 2436 hdr->addr1);
bb8c093b 2437 iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
b481de9c 2438 return priv->hw_setting.bcast_sta_id;
0795af57 2439 }
914233d6
SG		 2440 /* If we are in monitor mode, use BCAST. This is required for
2441 * packet injection. */
05c914fe 2442 case NL80211_IFTYPE_MONITOR:
914233d6
SG		 2443 return priv->hw_setting.bcast_sta_id;
2444
b481de9c 2445 default:
6f147926 2446 IWL_WARNING("Unknown mode of operation: %d\n", priv->iw_mode);
b481de9c
ZY		 2447 return priv->hw_setting.bcast_sta_id;
2448 }
2449}
2450
2451/*
2452 * start REPLY_TX command process
2453 */
e039fa4a 2454static int iwl3945_tx_skb(struct iwl3945_priv *priv, struct sk_buff *skb)
b481de9c
ZY		 2455{
2456 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
e039fa4a 2457 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bb8c093b 2458 struct iwl3945_tfd_frame *tfd;
b481de9c 2459 u32 *control_flags;
e2530083 2460 int txq_id = skb_get_queue_mapping(skb);
bb8c093b
CH		 2461 struct iwl3945_tx_queue *txq = NULL;
2462 struct iwl3945_queue *q = NULL;
b481de9c
ZY		 2463 dma_addr_t phys_addr;
2464 dma_addr_t txcmd_phys;
bb8c093b 2465 struct iwl3945_cmd *out_cmd = NULL;
54dbb525
TW		 2466 u16 len, idx, len_org, hdr_len;
2467 u8 id;
2468 u8 unicast;
b481de9c 2469 u8 sta_id;
54dbb525 2470 u8 tid = 0;
b481de9c 2471 u16 seq_number = 0;
fd7c8a40 2472 __le16 fc;
b481de9c 2473 u8 wait_write_ptr = 0;
54dbb525 2474 u8 *qc = NULL;
b481de9c
ZY		 2475 unsigned long flags;
2476 int rc;
2477
2478 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2479 if (iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 2480 IWL_DEBUG_DROP("Dropping - RF KILL\n");
2481 goto drop_unlock;
2482 }
2483
e039fa4a 2484 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
b481de9c
ZY		 2485 IWL_ERROR("ERROR: No TX rate available.\n");
2486 goto drop_unlock;
2487 }
2488
2489 unicast = !is_multicast_ether_addr(hdr->addr1);
2490 id = 0;
2491
fd7c8a40 2492 fc = hdr->frame_control;
b481de9c 2493
c8b0e6e1 2494#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 2495 if (ieee80211_is_auth(fc))
2496 IWL_DEBUG_TX("Sending AUTH frame\n");
fd7c8a40 2497 else if (ieee80211_is_assoc_req(fc))
b481de9c 2498 IWL_DEBUG_TX("Sending ASSOC frame\n");
fd7c8a40 2499 else if (ieee80211_is_reassoc_req(fc))
b481de9c
ZY		 2500 IWL_DEBUG_TX("Sending REASSOC frame\n");
2501#endif
2502
7878a5a4 2503 /* drop all data frame if we are not associated */
914233d6 2504 if (ieee80211_is_data(fc) &&
05c914fe 2505 (priv->iw_mode != NL80211_IFTYPE_MONITOR) && /* packet injection */
914233d6 2506 (!iwl3945_is_associated(priv) ||
05c914fe 2507 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
bb8c093b 2508 IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
b481de9c
ZY		 2509 goto drop_unlock;
2510 }
2511
2512 spin_unlock_irqrestore(&priv->lock, flags);
2513
7294ec95 2514 hdr_len = ieee80211_hdrlen(fc);
6440adb5
CB		 2515
2516 /* Find (or create) index into station table for destination station */
bb8c093b 2517 sta_id = iwl3945_get_sta_id(priv, hdr);
b481de9c 2518 if (sta_id == IWL_INVALID_STATION) {
e174961c
JB		 2519 IWL_DEBUG_DROP("Dropping - INVALID STATION: %pM\n",
2520 hdr->addr1);
b481de9c
ZY		 2521 goto drop;
2522 }
2523
2524 IWL_DEBUG_RATE("station Id %d\n", sta_id);
2525
fd7c8a40
HH		 2526 if (ieee80211_is_data_qos(fc)) {
2527 qc = ieee80211_get_qos_ctl(hdr);
7294ec95 2528 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
b481de9c
ZY		 2529 seq_number = priv->stations[sta_id].tid[tid].seq_number &
2530 IEEE80211_SCTL_SEQ;
2531 hdr->seq_ctrl = cpu_to_le16(seq_number) |
2532 (hdr->seq_ctrl &
2533 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
2534 seq_number += 0x10;
2535 }
6440adb5
CB		 2536
2537 /* Descriptor for chosen Tx queue */
b481de9c
ZY		 2538 txq = &priv->txq[txq_id];
2539 q = &txq->q;
2540
2541 spin_lock_irqsave(&priv->lock, flags);
2542
6440adb5 2543 /* Set up first empty TFD within this queue's circular TFD buffer */
fc4b6853 2544 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY		 2545 memset(tfd, 0, sizeof(*tfd));
2546 control_flags = (u32 *) tfd;
fc4b6853 2547 idx = get_cmd_index(q, q->write_ptr, 0);
b481de9c 2548
6440adb5 2549 /* Set up driver data for this TFD */
bb8c093b 2550 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
fc4b6853 2551 txq->txb[q->write_ptr].skb[0] = skb;
6440adb5
CB		 2552
2553 /* Init first empty entry in queue's array of Tx/cmd buffers */
b481de9c
ZY		 2554 out_cmd = &txq->cmd[idx];
2555 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
2556 memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
6440adb5
CB		 2557
2558 /*
2559 * Set up the Tx-command (not MAC!) header.
2560 * Store the chosen Tx queue and TFD index within the sequence field;
2561 * after Tx, uCode's Tx response will return this value so driver can
2562 * locate the frame within the tx queue and do post-tx processing.
2563 */
b481de9c
ZY		 2564 out_cmd->hdr.cmd = REPLY_TX;
2565 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
fc4b6853 2566 INDEX_TO_SEQ(q->write_ptr)));
6440adb5
CB		 2567
2568 /* Copy MAC header from skb into command buffer */
b481de9c
ZY		 2569 memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
2570
6440adb5
CB		 2571 /*
2572 * Use the first empty entry in this queue's command buffer array
2573 * to contain the Tx command and MAC header concatenated together
2574 * (payload data will be in another buffer).
2575 * Size of this varies, due to varying MAC header length.
2576 * If end is not dword aligned, we'll have 2 extra bytes at the end
2577 * of the MAC header (device reads on dword boundaries).
2578 * We'll tell device about this padding later.
2579 */
b481de9c 2580 len = priv->hw_setting.tx_cmd_len +
bb8c093b 2581 sizeof(struct iwl3945_cmd_header) + hdr_len;
b481de9c
ZY		 2582
2583 len_org = len;
2584 len = (len + 3) & ~3;
2585
2586 if (len_org != len)
2587 len_org = 1;
2588 else
2589 len_org = 0;
2590
6440adb5
CB		 2591 /* Physical address of this Tx command's header (not MAC header!),
2592 * within command buffer array. */
bb8c093b
CH		 2593 txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
2594 offsetof(struct iwl3945_cmd, hdr);
b481de9c 2595
6440adb5
CB		 2596 /* Add buffer containing Tx command and MAC(!) header to TFD's
2597 * first entry */
bb8c093b 2598 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
b481de9c 2599
d0f09804 2600 if (info->control.hw_key)
e039fa4a 2601 iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0);
b481de9c 2602
6440adb5
CB		 2603 /* Set up TFD's 2nd entry to point directly to remainder of skb,
2604 * if any (802.11 null frames have no payload). */
b481de9c
ZY		 2605 len = skb->len - hdr_len;
2606 if (len) {
2607 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
2608 len, PCI_DMA_TODEVICE);
bb8c093b 2609 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
b481de9c
ZY		 2610 }
2611
b481de9c 2612 if (!len)
6440adb5 2613 /* If there is no payload, then we use only one Tx buffer */
b481de9c
ZY		 2614 *control_flags = TFD_CTL_COUNT_SET(1);
2615 else
6440adb5
CB		 2616 /* Else use 2 buffers.
2617 * Tell 3945 about any padding after MAC header */
b481de9c
ZY		 2618 *control_flags = TFD_CTL_COUNT_SET(2) |
2619 TFD_CTL_PAD_SET(U32_PAD(len));
2620
6440adb5 2621 /* Total # bytes to be transmitted */
b481de9c
ZY		 2622 len = (u16)skb->len;
2623 out_cmd->cmd.tx.len = cpu_to_le16(len);
2624
2625 /* TODO need this for burst mode later on */
e039fa4a 2626 iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, unicast, sta_id);
b481de9c
ZY		 2627
2628 /* set is_hcca to 0; it probably will never be implemented */
e039fa4a 2629 iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
b481de9c
ZY		 2630
2631 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
2632 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
2633
8b7b1e05 2634 if (!ieee80211_has_morefrags(hdr->frame_control)) {
b481de9c 2635 txq->need_update = 1;
3ac7f146 2636 if (qc)
b481de9c 2637 priv->stations[sta_id].tid[tid].seq_number = seq_number;
b481de9c
ZY		 2638 } else {
2639 wait_write_ptr = 1;
2640 txq->need_update = 0;
2641 }
2642
bb8c093b 2643 iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
b481de9c
ZY		 2644 sizeof(out_cmd->cmd.tx));
2645
bb8c093b 2646 iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
7294ec95 2647 ieee80211_hdrlen(fc));
b481de9c 2648
6440adb5 2649 /* Tell device the write index *just past* this latest filled TFD */
c54b679d 2650 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
bb8c093b 2651 rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 2652 spin_unlock_irqrestore(&priv->lock, flags);
2653
2654 if (rc)
2655 return rc;
2656
bb8c093b 2657 if ((iwl3945_queue_space(q) < q->high_mark)
b481de9c
ZY		 2658 && priv->mac80211_registered) {
2659 if (wait_write_ptr) {
2660 spin_lock_irqsave(&priv->lock, flags);
2661 txq->need_update = 1;
bb8c093b 2662 iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 2663 spin_unlock_irqrestore(&priv->lock, flags);
2664 }
2665
e2530083 2666 ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
b481de9c
ZY		 2667 }
2668
2669 return 0;
2670
2671drop_unlock:
2672 spin_unlock_irqrestore(&priv->lock, flags);
2673drop:
2674 return -1;
2675}
2676
bb8c093b 2677static void iwl3945_set_rate(struct iwl3945_priv *priv)
b481de9c 2678{
8318d78a 2679 const struct ieee80211_supported_band *sband = NULL;
b481de9c
ZY		 2680 struct ieee80211_rate *rate;
2681 int i;
2682
8318d78a
JB		 2683 sband = iwl3945_get_band(priv, priv->band);
2684 if (!sband) {
c4ba9621
SA		 2685 IWL_ERROR("Failed to set rate: unable to get hw mode\n");
2686 return;
2687 }
b481de9c
ZY		 2688
2689 priv->active_rate = 0;
2690 priv->active_rate_basic = 0;
2691
8318d78a
JB		 2692 IWL_DEBUG_RATE("Setting rates for %s GHz\n",
2693 sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
2694
2695 for (i = 0; i < sband->n_bitrates; i++) {
2696 rate = &sband->bitrates[i];
2697 if ((rate->hw_value < IWL_RATE_COUNT) &&
2698 !(rate->flags & IEEE80211_CHAN_DISABLED)) {
2699 IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
2700 rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
2701 priv->active_rate |= (1 << rate->hw_value);
2702 }
b481de9c
ZY		 2703 }
2704
2705 IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
2706 priv->active_rate, priv->active_rate_basic);
2707
2708 /*
2709 * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
2710 * otherwise set it to the default of all CCK rates and 6, 12, 24 for
2711 * OFDM
2712 */
2713 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
2714 priv->staging_rxon.cck_basic_rates =
2715 ((priv->active_rate_basic &
2716 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
2717 else
2718 priv->staging_rxon.cck_basic_rates =
2719 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2720
2721 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
2722 priv->staging_rxon.ofdm_basic_rates =
2723 ((priv->active_rate_basic &
2724 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
2725 IWL_FIRST_OFDM_RATE) & 0xFF;
2726 else
2727 priv->staging_rxon.ofdm_basic_rates =
2728 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2729}
2730
bb8c093b 2731static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
b481de9c
ZY		 2732{
2733 unsigned long flags;
2734
2735 if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
2736 return;
2737
2738 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
2739 disable_radio ? "OFF" : "ON");
2740
2741 if (disable_radio) {
bb8c093b 2742 iwl3945_scan_cancel(priv);
b481de9c 2743 /* FIXME: This is a workaround for AP */
05c914fe 2744 if (priv->iw_mode != NL80211_IFTYPE_AP) {
b481de9c 2745 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2746 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 2747 CSR_UCODE_SW_BIT_RFKILL);
2748 spin_unlock_irqrestore(&priv->lock, flags);
bb8c093b 2749 iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
b481de9c
ZY		 2750 set_bit(STATUS_RF_KILL_SW, &priv->status);
2751 }
2752 return;
2753 }
2754
2755 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2756 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 2757
2758 clear_bit(STATUS_RF_KILL_SW, &priv->status);
2759 spin_unlock_irqrestore(&priv->lock, flags);
2760
2761 /* wake up ucode */
2762 msleep(10);
2763
2764 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH		 2765 iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
2766 if (!iwl3945_grab_nic_access(priv))
2767 iwl3945_release_nic_access(priv);
b481de9c
ZY		 2768 spin_unlock_irqrestore(&priv->lock, flags);
2769
2770 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
2771 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
2772 "disabled by HW switch\n");
2773 return;
2774 }
2775
808e72a0
ZY		 2776 if (priv->is_open)
2777 queue_work(priv->workqueue, &priv->restart);
b481de9c
ZY		 2778 return;
2779}
2780
bb8c093b 2781void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
b481de9c
ZY		 2782 u32 decrypt_res, struct ieee80211_rx_status *stats)
2783{
2784 u16 fc =
2785 le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
2786
2787 if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
2788 return;
2789
2790 if (!(fc & IEEE80211_FCTL_PROTECTED))
2791 return;
2792
2793 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
2794 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2795 case RX_RES_STATUS_SEC_TYPE_TKIP:
2796 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2797 RX_RES_STATUS_BAD_ICV_MIC)
2798 stats->flag |= RX_FLAG_MMIC_ERROR;
2799 case RX_RES_STATUS_SEC_TYPE_WEP:
2800 case RX_RES_STATUS_SEC_TYPE_CCMP:
2801 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2802 RX_RES_STATUS_DECRYPT_OK) {
2803 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
2804 stats->flag |= RX_FLAG_DECRYPTED;
2805 }
2806 break;
2807
2808 default:
2809 break;
2810 }
2811}
2812
c8b0e6e1 2813#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 2814
2815#include "iwl-spectrum.h"
2816
2817#define BEACON_TIME_MASK_LOW 0x00FFFFFF
2818#define BEACON_TIME_MASK_HIGH 0xFF000000
2819#define TIME_UNIT 1024
2820
2821/*
2822 * extended beacon time format
2823 * time in usec will be changed into a 32-bit value in 8:24 format
2824 * the high 1 byte is the beacon counts
2825 * the lower 3 bytes is the time in usec within one beacon interval
2826 */
2827
bb8c093b 2828static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
b481de9c
ZY		 2829{
2830 u32 quot;
2831 u32 rem;
2832 u32 interval = beacon_interval * 1024;
2833
2834 if (!interval || !usec)
2835 return 0;
2836
2837 quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
2838 rem = (usec % interval) & BEACON_TIME_MASK_LOW;
2839
2840 return (quot << 24) + rem;
2841}
2842
2843/* base is usually what we get from ucode with each received frame,
2844 * the same as HW timer counter counting down
2845 */
2846
bb8c093b 2847static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
b481de9c
ZY		 2848{
2849 u32 base_low = base & BEACON_TIME_MASK_LOW;
2850 u32 addon_low = addon & BEACON_TIME_MASK_LOW;
2851 u32 interval = beacon_interval * TIME_UNIT;
2852 u32 res = (base & BEACON_TIME_MASK_HIGH) +
2853 (addon & BEACON_TIME_MASK_HIGH);
2854
2855 if (base_low > addon_low)
2856 res += base_low - addon_low;
2857 else if (base_low < addon_low) {
2858 res += interval + base_low - addon_low;
2859 res += (1 << 24);
2860 } else
2861 res += (1 << 24);
2862
2863 return cpu_to_le32(res);
2864}
2865
bb8c093b 2866static int iwl3945_get_measurement(struct iwl3945_priv *priv,
b481de9c
ZY		 2867 struct ieee80211_measurement_params *params,
2868 u8 type)
2869{
bb8c093b
CH		 2870 struct iwl3945_spectrum_cmd spectrum;
2871 struct iwl3945_rx_packet *res;
2872 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 2873 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
2874 .data = (void *)&spectrum,
2875 .meta.flags = CMD_WANT_SKB,
2876 };
2877 u32 add_time = le64_to_cpu(params->start_time);
2878 int rc;
2879 int spectrum_resp_status;
2880 int duration = le16_to_cpu(params->duration);
2881
bb8c093b 2882 if (iwl3945_is_associated(priv))
b481de9c 2883 add_time =
bb8c093b 2884 iwl3945_usecs_to_beacons(
b481de9c
ZY		 2885 le64_to_cpu(params->start_time) - priv->last_tsf,
2886 le16_to_cpu(priv->rxon_timing.beacon_interval));
2887
2888 memset(&spectrum, 0, sizeof(spectrum));
2889
2890 spectrum.channel_count = cpu_to_le16(1);
2891 spectrum.flags =
2892 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
2893 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
2894 cmd.len = sizeof(spectrum);
2895 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
2896
bb8c093b 2897 if (iwl3945_is_associated(priv))
b481de9c 2898 spectrum.start_time =
bb8c093b 2899 iwl3945_add_beacon_time(priv->last_beacon_time,
b481de9c
ZY		 2900 add_time,
2901 le16_to_cpu(priv->rxon_timing.beacon_interval));
2902 else
2903 spectrum.start_time = 0;
2904
2905 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
2906 spectrum.channels[0].channel = params->channel;
2907 spectrum.channels[0].type = type;
2908 if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
2909 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
2910 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
2911
bb8c093b 2912 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 2913 if (rc)
2914 return rc;
2915
bb8c093b 2916 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 2917 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
2918 IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
2919 rc = -EIO;
2920 }
2921
2922 spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
2923 switch (spectrum_resp_status) {
2924 case 0: /* Command will be handled */
2925 if (res->u.spectrum.id != 0xff) {
bc434dd2
IS		 2926 IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
2927 res->u.spectrum.id);
b481de9c
ZY		 2928 priv->measurement_status &= ~MEASUREMENT_READY;
2929 }
2930 priv->measurement_status |= MEASUREMENT_ACTIVE;
2931 rc = 0;
2932 break;
2933
2934 case 1: /* Command will not be handled */
2935 rc = -EAGAIN;
2936 break;
2937 }
2938
2939 dev_kfree_skb_any(cmd.meta.u.skb);
2940
2941 return rc;
2942}
2943#endif
2944
bb8c093b
CH		 2945static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
2946 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 2947{
bb8c093b
CH		 2948 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
2949 struct iwl3945_alive_resp *palive;
b481de9c
ZY		 2950 struct delayed_work *pwork;
2951
2952 palive = &pkt->u.alive_frame;
2953
2954 IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
2955 "0x%01X 0x%01X\n",
2956 palive->is_valid, palive->ver_type,
2957 palive->ver_subtype);
2958
2959 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
2960 IWL_DEBUG_INFO("Initialization Alive received.\n");
2961 memcpy(&priv->card_alive_init,
2962 &pkt->u.alive_frame,
bb8c093b 2963 sizeof(struct iwl3945_init_alive_resp));
b481de9c
ZY		 2964 pwork = &priv->init_alive_start;
2965 } else {
2966 IWL_DEBUG_INFO("Runtime Alive received.\n");
2967 memcpy(&priv->card_alive, &pkt->u.alive_frame,
bb8c093b 2968 sizeof(struct iwl3945_alive_resp));
b481de9c 2969 pwork = &priv->alive_start;
bb8c093b 2970 iwl3945_disable_events(priv);
b481de9c
ZY		 2971 }
2972
2973 /* We delay the ALIVE response by 5ms to
2974 * give the HW RF Kill time to activate... */
2975 if (palive->is_valid == UCODE_VALID_OK)
2976 queue_delayed_work(priv->workqueue, pwork,
2977 msecs_to_jiffies(5));
2978 else
2979 IWL_WARNING("uCode did not respond OK.\n");
2980}
2981
bb8c093b
CH		 2982static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
2983 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 2984{
bb8c093b 2985 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 2986
2987 IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
2988 return;
2989}
2990
bb8c093b
CH		 2991static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
2992 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 2993{
bb8c093b 2994 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 2995
2996 IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
2997 "seq 0x%04X ser 0x%08X\n",
2998 le32_to_cpu(pkt->u.err_resp.error_type),
2999 get_cmd_string(pkt->u.err_resp.cmd_id),
3000 pkt->u.err_resp.cmd_id,
3001 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
3002 le32_to_cpu(pkt->u.err_resp.error_info));
3003}
3004
3005#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
3006
bb8c093b 3007static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3008{
bb8c093b
CH		 3009 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3010 struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
3011 struct iwl3945_csa_notification *csa = &(pkt->u.csa_notif);
b481de9c
ZY		 3012 IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
3013 le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
3014 rxon->channel = csa->channel;
3015 priv->staging_rxon.channel = csa->channel;
3016}
3017
bb8c093b
CH		 3018static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
3019 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3020{
c8b0e6e1 3021#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
bb8c093b
CH		 3022 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3023 struct iwl3945_spectrum_notification *report = &(pkt->u.spectrum_notif);
b481de9c
ZY		 3024
3025 if (!report->state) {
3026 IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
3027 "Spectrum Measure Notification: Start\n");
3028 return;
3029 }
3030
3031 memcpy(&priv->measure_report, report, sizeof(*report));
3032 priv->measurement_status |= MEASUREMENT_READY;
3033#endif
3034}
3035
bb8c093b
CH		 3036static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
3037 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3038{
c8b0e6e1 3039#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3040 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3041 struct iwl3945_sleep_notification *sleep = &(pkt->u.sleep_notif);
b481de9c
ZY		 3042 IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
3043 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
3044#endif
3045}
3046
bb8c093b
CH		 3047static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
3048 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3049{
bb8c093b 3050 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3051 IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
3052 "notification for %s:\n",
3053 le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
bb8c093b 3054 iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
b481de9c
ZY		 3055}
3056
bb8c093b 3057static void iwl3945_bg_beacon_update(struct work_struct *work)
b481de9c 3058{
bb8c093b
CH		 3059 struct iwl3945_priv *priv =
3060 container_of(work, struct iwl3945_priv, beacon_update);
b481de9c
ZY		 3061 struct sk_buff *beacon;
3062
3063 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 3064 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY		 3065
3066 if (!beacon) {
3067 IWL_ERROR("update beacon failed\n");
3068 return;
3069 }
3070
3071 mutex_lock(&priv->mutex);
3072 /* new beacon skb is allocated every time; dispose previous.*/
3073 if (priv->ibss_beacon)
3074 dev_kfree_skb(priv->ibss_beacon);
3075
3076 priv->ibss_beacon = beacon;
3077 mutex_unlock(&priv->mutex);
3078
bb8c093b 3079 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 3080}
3081
bb8c093b
CH		 3082static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
3083 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3084{
c8b0e6e1 3085#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3086 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3087 struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
b481de9c
ZY		 3088 u8 rate = beacon->beacon_notify_hdr.rate;
3089
3090 IWL_DEBUG_RX("beacon status %x retries %d iss %d "
3091 "tsf %d %d rate %d\n",
3092 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
3093 beacon->beacon_notify_hdr.failure_frame,
3094 le32_to_cpu(beacon->ibss_mgr_status),
3095 le32_to_cpu(beacon->high_tsf),
3096 le32_to_cpu(beacon->low_tsf), rate);
3097#endif
3098
05c914fe 3099 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY		 3100 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
3101 queue_work(priv->workqueue, &priv->beacon_update);
3102}
3103
3104/* Service response to REPLY_SCAN_CMD (0x80) */
bb8c093b
CH		 3105static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
3106 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3107{
c8b0e6e1 3108#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3109 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3110 struct iwl3945_scanreq_notification *notif =
3111 (struct iwl3945_scanreq_notification *)pkt->u.raw;
b481de9c
ZY		 3112
3113 IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
3114#endif
3115}
3116
3117/* Service SCAN_START_NOTIFICATION (0x82) */
bb8c093b
CH		 3118static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
3119 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3120{
bb8c093b
CH		 3121 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3122 struct iwl3945_scanstart_notification *notif =
3123 (struct iwl3945_scanstart_notification *)pkt->u.raw;
b481de9c
ZY		 3124 priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
3125 IWL_DEBUG_SCAN("Scan start: "
3126 "%d [802.11%s] "
3127 "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
3128 notif->channel,
3129 notif->band ? "bg" : "a",
3130 notif->tsf_high,
3131 notif->tsf_low, notif->status, notif->beacon_timer);
3132}
3133
3134/* Service SCAN_RESULTS_NOTIFICATION (0x83) */
bb8c093b
CH		 3135static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
3136 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3137{
bb8c093b
CH		 3138 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3139 struct iwl3945_scanresults_notification *notif =
3140 (struct iwl3945_scanresults_notification *)pkt->u.raw;
b481de9c
ZY		 3141
3142 IWL_DEBUG_SCAN("Scan ch.res: "
3143 "%d [802.11%s] "
3144 "(TSF: 0x%08X:%08X) - %d "
3145 "elapsed=%lu usec (%dms since last)\n",
3146 notif->channel,
3147 notif->band ? "bg" : "a",
3148 le32_to_cpu(notif->tsf_high),
3149 le32_to_cpu(notif->tsf_low),
3150 le32_to_cpu(notif->statistics[0]),
3151 le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
3152 jiffies_to_msecs(elapsed_jiffies
3153 (priv->last_scan_jiffies, jiffies)));
3154
3155 priv->last_scan_jiffies = jiffies;
7878a5a4 3156 priv->next_scan_jiffies = 0;
b481de9c
ZY		 3157}
3158
3159/* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
bb8c093b
CH		 3160static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
3161 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3162{
bb8c093b
CH		 3163 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3164 struct iwl3945_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
b481de9c
ZY		 3165
3166 IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
3167 scan_notif->scanned_channels,
3168 scan_notif->tsf_low,
3169 scan_notif->tsf_high, scan_notif->status);
3170
3171 /* The HW is no longer scanning */
3172 clear_bit(STATUS_SCAN_HW, &priv->status);
3173
3174 /* The scan completion notification came in, so kill that timer... */
3175 cancel_delayed_work(&priv->scan_check);
3176
3177 IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
66b5004d
RR		 3178 (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ?
3179 "2.4" : "5.2",
b481de9c
ZY		 3180 jiffies_to_msecs(elapsed_jiffies
3181 (priv->scan_pass_start, jiffies)));
3182
66b5004d
RR		 3183 /* Remove this scanned band from the list of pending
3184 * bands to scan, band G precedes A in order of scanning
3185 * as seen in iwl3945_bg_request_scan */
3186 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ))
3187 priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ);
3188 else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ))
3189 priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ);
b481de9c
ZY		 3190
3191 /* If a request to abort was given, or the scan did not succeed
3192 * then we reset the scan state machine and terminate,
3193 * re-queuing another scan if one has been requested */
3194 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
3195 IWL_DEBUG_INFO("Aborted scan completed.\n");
3196 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
3197 } else {
3198 /* If there are more bands on this scan pass reschedule */
3199 if (priv->scan_bands > 0)
3200 goto reschedule;
3201 }
3202
3203 priv->last_scan_jiffies = jiffies;
7878a5a4 3204 priv->next_scan_jiffies = 0;
b481de9c
ZY		 3205 IWL_DEBUG_INFO("Setting scan to off\n");
3206
3207 clear_bit(STATUS_SCANNING, &priv->status);
3208
3209 IWL_DEBUG_INFO("Scan took %dms\n",
3210 jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
3211
3212 queue_work(priv->workqueue, &priv->scan_completed);
3213
3214 return;
3215
3216reschedule:
3217 priv->scan_pass_start = jiffies;
3218 queue_work(priv->workqueue, &priv->request_scan);
3219}
3220
3221/* Handle notification from uCode that card's power state is changing
3222 * due to software, hardware, or critical temperature RFKILL */
bb8c093b
CH		 3223static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
3224 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3225{
bb8c093b 3226 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3227 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
3228 unsigned long status = priv->status;
3229
3230 IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
3231 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3232 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
3233
bb8c093b 3234 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 3235 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3236
3237 if (flags & HW_CARD_DISABLED)
3238 set_bit(STATUS_RF_KILL_HW, &priv->status);
3239 else
3240 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3241
3242
3243 if (flags & SW_CARD_DISABLED)
3244 set_bit(STATUS_RF_KILL_SW, &priv->status);
3245 else
3246 clear_bit(STATUS_RF_KILL_SW, &priv->status);
3247
bb8c093b 3248 iwl3945_scan_cancel(priv);
b481de9c
ZY		 3249
3250 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
3251 test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
3252 (test_bit(STATUS_RF_KILL_SW, &status) !=
3253 test_bit(STATUS_RF_KILL_SW, &priv->status)))
3254 queue_work(priv->workqueue, &priv->rf_kill);
3255 else
3256 wake_up_interruptible(&priv->wait_command_queue);
3257}
3258
3259/**
bb8c093b 3260 * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY		 3261 *
3262 * Setup the RX handlers for each of the reply types sent from the uCode
3263 * to the host.
3264 *
3265 * This function chains into the hardware specific files for them to setup
3266 * any hardware specific handlers as well.
3267 */
bb8c093b 3268static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
b481de9c 3269{
bb8c093b
CH		 3270 priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
3271 priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
3272 priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
3273 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
b481de9c 3274 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
bb8c093b
CH		 3275 iwl3945_rx_spectrum_measure_notif;
3276 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
b481de9c 3277 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
bb8c093b
CH		 3278 iwl3945_rx_pm_debug_statistics_notif;
3279 priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
b481de9c 3280
9fbab516
BC		 3281 /*
3282 * The same handler is used for both the REPLY to a discrete
3283 * statistics request from the host as well as for the periodic
3284 * statistics notifications (after received beacons) from the uCode.
b481de9c 3285 */
bb8c093b
CH		 3286 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
3287 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
b481de9c 3288
bb8c093b
CH		 3289 priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
3290 priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
b481de9c 3291 priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
bb8c093b 3292 iwl3945_rx_scan_results_notif;
b481de9c 3293 priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
bb8c093b
CH		 3294 iwl3945_rx_scan_complete_notif;
3295 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
b481de9c 3296
9fbab516 3297 /* Set up hardware specific Rx handlers */
bb8c093b 3298 iwl3945_hw_rx_handler_setup(priv);
b481de9c
ZY		 3299}
3300
91c066f2
TW		 3301/**
3302 * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries
3303 * When FW advances 'R' index, all entries between old and new 'R' index
3304 * need to be reclaimed.
3305 */
3306static void iwl3945_cmd_queue_reclaim(struct iwl3945_priv *priv,
3307 int txq_id, int index)
3308{
3309 struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
3310 struct iwl3945_queue *q = &txq->q;
3311 int nfreed = 0;
3312
3313 if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) {
3314 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
3315 "is out of range [0-%d] %d %d.\n", txq_id,
3316 index, q->n_bd, q->write_ptr, q->read_ptr);
3317 return;
3318 }
3319
3320 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
3321 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
3322 if (nfreed > 1) {
3323 IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
3324 q->write_ptr, q->read_ptr);
3325 queue_work(priv->workqueue, &priv->restart);
3326 break;
3327 }
3328 nfreed++;
3329 }
3330}
3331
3332
b481de9c 3333/**
bb8c093b 3334 * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
b481de9c
ZY		 3335 * @rxb: Rx buffer to reclaim
3336 *
3337 * If an Rx buffer has an async callback associated with it the callback
3338 * will be executed. The attached skb (if present) will only be freed
3339 * if the callback returns 1
3340 */
bb8c093b
CH		 3341static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
3342 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3343{
bb8c093b 3344 struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
b481de9c
ZY		 3345 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3346 int txq_id = SEQ_TO_QUEUE(sequence);
3347 int index = SEQ_TO_INDEX(sequence);
3348 int huge = sequence & SEQ_HUGE_FRAME;
3349 int cmd_index;
bb8c093b 3350 struct iwl3945_cmd *cmd;
b481de9c 3351
b481de9c
ZY		 3352 BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
3353
3354 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
3355 cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
3356
3357 /* Input error checking is done when commands are added to queue. */
3358 if (cmd->meta.flags & CMD_WANT_SKB) {
3359 cmd->meta.source->u.skb = rxb->skb;
3360 rxb->skb = NULL;
3361 } else if (cmd->meta.u.callback &&
3362 !cmd->meta.u.callback(priv, cmd, rxb->skb))
3363 rxb->skb = NULL;
3364
91c066f2 3365 iwl3945_cmd_queue_reclaim(priv, txq_id, index);
b481de9c
ZY		 3366
3367 if (!(cmd->meta.flags & CMD_ASYNC)) {
3368 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
3369 wake_up_interruptible(&priv->wait_command_queue);
3370 }
3371}
3372
3373/************************** RX-FUNCTIONS ****************************/
3374/*
3375 * Rx theory of operation
3376 *
3377 * The host allocates 32 DMA target addresses and passes the host address
3378 * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
3379 * 0 to 31
3380 *
3381 * Rx Queue Indexes
3382 * The host/firmware share two index registers for managing the Rx buffers.
3383 *
3384 * The READ index maps to the first position that the firmware may be writing
3385 * to -- the driver can read up to (but not including) this position and get
3386 * good data.
3387 * The READ index is managed by the firmware once the card is enabled.
3388 *
3389 * The WRITE index maps to the last position the driver has read from -- the
3390 * position preceding WRITE is the last slot the firmware can place a packet.
3391 *
3392 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
3393 * WRITE = READ.
3394 *
9fbab516 3395 * During initialization, the host sets up the READ queue position to the first
b481de9c
ZY		 3396 * INDEX position, and WRITE to the last (READ - 1 wrapped)
3397 *
9fbab516 3398 * When the firmware places a packet in a buffer, it will advance the READ index
b481de9c
ZY		 3399 * and fire the RX interrupt. The driver can then query the READ index and
3400 * process as many packets as possible, moving the WRITE index forward as it
3401 * resets the Rx queue buffers with new memory.
3402 *
3403 * The management in the driver is as follows:
3404 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
3405 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
01ebd063 3406 * to replenish the iwl->rxq->rx_free.
bb8c093b 3407 * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
b481de9c
ZY		 3408 * iwl->rxq is replenished and the READ INDEX is updated (updating the
3409 * 'processed' and 'read' driver indexes as well)
3410 * + A received packet is processed and handed to the kernel network stack,
3411 * detached from the iwl->rxq. The driver 'processed' index is updated.
3412 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
3413 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
3414 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
3415 * were enough free buffers and RX_STALLED is set it is cleared.
3416 *
3417 *
3418 * Driver sequence:
3419 *
9fbab516
BC		 3420 * iwl3945_rx_queue_alloc() Allocates rx_free
3421 * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
bb8c093b 3422 * iwl3945_rx_queue_restock
9fbab516 3423 * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
b481de9c
ZY		 3424 * queue, updates firmware pointers, and updates
3425 * the WRITE index. If insufficient rx_free buffers
bb8c093b 3426 * are available, schedules iwl3945_rx_replenish
b481de9c
ZY		 3427 *
3428 * -- enable interrupts --
9fbab516 3429 * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the
b481de9c
ZY		 3430 * READ INDEX, detaching the SKB from the pool.
3431 * Moves the packet buffer from queue to rx_used.
bb8c093b 3432 * Calls iwl3945_rx_queue_restock to refill any empty
b481de9c
ZY		 3433 * slots.
3434 * ...
3435 *
3436 */
3437
3438/**
bb8c093b 3439 * iwl3945_rx_queue_space - Return number of free slots available in queue.
b481de9c 3440 */
bb8c093b 3441static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
b481de9c
ZY		 3442{
3443 int s = q->read - q->write;
3444 if (s <= 0)
3445 s += RX_QUEUE_SIZE;
3446 /* keep some buffer to not confuse full and empty queue */
3447 s -= 2;
3448 if (s < 0)
3449 s = 0;
3450 return s;
3451}
3452
3453/**
bb8c093b 3454 * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
b481de9c 3455 */
bb8c093b 3456int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
b481de9c
ZY		 3457{
3458 u32 reg = 0;
3459 int rc = 0;
3460 unsigned long flags;
3461
3462 spin_lock_irqsave(&q->lock, flags);
3463
3464 if (q->need_update == 0)
3465 goto exit_unlock;
3466
6440adb5 3467 /* If power-saving is in use, make sure device is awake */
b481de9c 3468 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
bb8c093b 3469 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY		 3470
3471 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
bb8c093b 3472 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 3473 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3474 goto exit_unlock;
3475 }
3476
bb8c093b 3477 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 3478 if (rc)
3479 goto exit_unlock;
3480
6440adb5 3481 /* Device expects a multiple of 8 */
bb8c093b 3482 iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
b481de9c 3483 q->write & ~0x7);
bb8c093b 3484 iwl3945_release_nic_access(priv);
6440adb5
CB		 3485
3486 /* Else device is assumed to be awake */
b481de9c 3487 } else
6440adb5 3488 /* Device expects a multiple of 8 */
bb8c093b 3489 iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
b481de9c
ZY		 3490
3491
3492 q->need_update = 0;
3493
3494 exit_unlock:
3495 spin_unlock_irqrestore(&q->lock, flags);
3496 return rc;
3497}
3498
3499/**
9fbab516 3500 * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
b481de9c 3501 */
bb8c093b 3502static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
b481de9c
ZY		 3503 dma_addr_t dma_addr)
3504{
3505 return cpu_to_le32((u32)dma_addr);
3506}
3507
3508/**
bb8c093b 3509 * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
b481de9c 3510 *
9fbab516 3511 * If there are slots in the RX queue that need to be restocked,
b481de9c 3512 * and we have free pre-allocated buffers, fill the ranks as much
9fbab516 3513 * as we can, pulling from rx_free.
b481de9c
ZY		 3514 *
3515 * This moves the 'write' index forward to catch up with 'processed', and
3516 * also updates the memory address in the firmware to reference the new
3517 * target buffer.
3518 */
bb8c093b 3519static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
b481de9c 3520{
bb8c093b 3521 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 3522 struct list_head *element;
bb8c093b 3523 struct iwl3945_rx_mem_buffer *rxb;
b481de9c
ZY		 3524 unsigned long flags;
3525 int write, rc;
3526
3527 spin_lock_irqsave(&rxq->lock, flags);
3528 write = rxq->write & ~0x7;
bb8c093b 3529 while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
6440adb5 3530 /* Get next free Rx buffer, remove from free list */
b481de9c 3531 element = rxq->rx_free.next;
bb8c093b 3532 rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
b481de9c 3533 list_del(element);
6440adb5
CB		 3534
3535 /* Point to Rx buffer via next RBD in circular buffer */
bb8c093b 3536 rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
b481de9c
ZY		 3537 rxq->queue[rxq->write] = rxb;
3538 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
3539 rxq->free_count--;
3540 }
3541 spin_unlock_irqrestore(&rxq->lock, flags);
3542 /* If the pre-allocated buffer pool is dropping low, schedule to
3543 * refill it */
3544 if (rxq->free_count <= RX_LOW_WATERMARK)
3545 queue_work(priv->workqueue, &priv->rx_replenish);
3546
3547
6440adb5
CB		 3548 /* If we've added more space for the firmware to place data, tell it.
3549 * Increment device's write pointer in multiples of 8. */
b481de9c
ZY		 3550 if ((write != (rxq->write & ~0x7))
3551 || (abs(rxq->write - rxq->read) > 7)) {
3552 spin_lock_irqsave(&rxq->lock, flags);
3553 rxq->need_update = 1;
3554 spin_unlock_irqrestore(&rxq->lock, flags);
bb8c093b 3555 rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 3556 if (rc)
3557 return rc;
3558 }
3559
3560 return 0;
3561}
3562
3563/**
bb8c093b 3564 * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
b481de9c
ZY		 3565 *
3566 * When moving to rx_free an SKB is allocated for the slot.
3567 *
bb8c093b 3568 * Also restock the Rx queue via iwl3945_rx_queue_restock.
01ebd063 3569 * This is called as a scheduled work item (except for during initialization)
b481de9c 3570 */
5c0eef96 3571static void iwl3945_rx_allocate(struct iwl3945_priv *priv)
b481de9c 3572{
bb8c093b 3573 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 3574 struct list_head *element;
bb8c093b 3575 struct iwl3945_rx_mem_buffer *rxb;
b481de9c
ZY		 3576 unsigned long flags;
3577 spin_lock_irqsave(&rxq->lock, flags);
3578 while (!list_empty(&rxq->rx_used)) {
3579 element = rxq->rx_used.next;
bb8c093b 3580 rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
6440adb5
CB		 3581
3582 /* Alloc a new receive buffer */
b481de9c
ZY		 3583 rxb->skb =
3584 alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
3585 if (!rxb->skb) {
3586 if (net_ratelimit())
3587 printk(KERN_CRIT DRV_NAME
3588 ": Can not allocate SKB buffers\n");
3589 /* We don't reschedule replenish work here -- we will
3590 * call the restock method and if it still needs
3591 * more buffers it will schedule replenish */
3592 break;
3593 }
12342c47
ZY		 3594
3595 /* If radiotap head is required, reserve some headroom here.
3596 * The physical head count is a variable rx_stats->phy_count.
3597 * We reserve 4 bytes here. Plus these extra bytes, the
3598 * headroom of the physical head should be enough for the
3599 * radiotap head that iwl3945 supported. See iwl3945_rt.
3600 */
3601 skb_reserve(rxb->skb, 4);
3602
b481de9c
ZY		 3603 priv->alloc_rxb_skb++;
3604 list_del(element);
6440adb5
CB		 3605
3606 /* Get physical address of RB/SKB */
b481de9c
ZY		 3607 rxb->dma_addr =
3608 pci_map_single(priv->pci_dev, rxb->skb->data,
3609 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3610 list_add_tail(&rxb->list, &rxq->rx_free);
3611 rxq->free_count++;
3612 }
3613 spin_unlock_irqrestore(&rxq->lock, flags);
5c0eef96
MA		 3614}
3615
3616/*
3617 * this should be called while priv->lock is locked
3618 */
4fd1f841 3619static void __iwl3945_rx_replenish(void *data)
5c0eef96
MA		 3620{
3621 struct iwl3945_priv *priv = data;
3622
3623 iwl3945_rx_allocate(priv);
3624 iwl3945_rx_queue_restock(priv);
3625}
3626
3627
3628void iwl3945_rx_replenish(void *data)
3629{
3630 struct iwl3945_priv *priv = data;
3631 unsigned long flags;
3632
3633 iwl3945_rx_allocate(priv);
b481de9c
ZY		 3634
3635 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 3636 iwl3945_rx_queue_restock(priv);
b481de9c
ZY		 3637 spin_unlock_irqrestore(&priv->lock, flags);
3638}
3639
3640/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
9fbab516 3641 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
b481de9c
ZY		 3642 * This free routine walks the list of POOL entries and if SKB is set to
3643 * non NULL it is unmapped and freed
3644 */
bb8c093b 3645static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY		 3646{
3647 int i;
3648 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
3649 if (rxq->pool[i].skb != NULL) {
3650 pci_unmap_single(priv->pci_dev,
3651 rxq->pool[i].dma_addr,
3652 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3653 dev_kfree_skb(rxq->pool[i].skb);
3654 }
3655 }
3656
3657 pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
3658 rxq->dma_addr);
3659 rxq->bd = NULL;
3660}
3661
bb8c093b 3662int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
b481de9c 3663{
bb8c093b 3664 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 3665 struct pci_dev *dev = priv->pci_dev;
3666 int i;
3667
3668 spin_lock_init(&rxq->lock);
3669 INIT_LIST_HEAD(&rxq->rx_free);
3670 INIT_LIST_HEAD(&rxq->rx_used);
6440adb5
CB		 3671
3672 /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
b481de9c
ZY		 3673 rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
3674 if (!rxq->bd)
3675 return -ENOMEM;
6440adb5 3676
b481de9c
ZY		 3677 /* Fill the rx_used queue with _all_ of the Rx buffers */
3678 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
3679 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
6440adb5 3680
b481de9c
ZY		 3681 /* Set us so that we have processed and used all buffers, but have
3682 * not restocked the Rx queue with fresh buffers */
3683 rxq->read = rxq->write = 0;
3684 rxq->free_count = 0;
3685 rxq->need_update = 0;
3686 return 0;
3687}
3688
bb8c093b 3689void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY		 3690{
3691 unsigned long flags;
3692 int i;
3693 spin_lock_irqsave(&rxq->lock, flags);
3694 INIT_LIST_HEAD(&rxq->rx_free);
3695 INIT_LIST_HEAD(&rxq->rx_used);
3696 /* Fill the rx_used queue with _all_ of the Rx buffers */
3697 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
3698 /* In the reset function, these buffers may have been allocated
3699 * to an SKB, so we need to unmap and free potential storage */
3700 if (rxq->pool[i].skb != NULL) {
3701 pci_unmap_single(priv->pci_dev,
3702 rxq->pool[i].dma_addr,
3703 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3704 priv->alloc_rxb_skb--;
3705 dev_kfree_skb(rxq->pool[i].skb);
3706 rxq->pool[i].skb = NULL;
3707 }
3708 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
3709 }
3710
3711 /* Set us so that we have processed and used all buffers, but have
3712 * not restocked the Rx queue with fresh buffers */
3713 rxq->read = rxq->write = 0;
3714 rxq->free_count = 0;
3715 spin_unlock_irqrestore(&rxq->lock, flags);
3716}
3717
3718/* Convert linear signal-to-noise ratio into dB */
3719static u8 ratio2dB[100] = {
3720/* 0 1 2 3 4 5 6 7 8 9 */
3721 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
3722 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
3723 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
3724 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
3725 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
3726 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
3727 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
3728 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
3729 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
3730 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
3731};
3732
3733/* Calculates a relative dB value from a ratio of linear
3734 * (i.e. not dB) signal levels.
3735 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
bb8c093b 3736int iwl3945_calc_db_from_ratio(int sig_ratio)
b481de9c 3737{
221c80cf
AB		 3738 /* 1000:1 or higher just report as 60 dB */
3739 if (sig_ratio >= 1000)
b481de9c
ZY		 3740 return 60;
3741
221c80cf 3742 /* 100:1 or higher, divide by 10 and use table,
b481de9c 3743 * add 20 dB to make up for divide by 10 */
221c80cf 3744 if (sig_ratio >= 100)
3ac7f146 3745 return 20 + (int)ratio2dB[sig_ratio/10];
b481de9c
ZY		 3746
3747 /* We shouldn't see this */
3748 if (sig_ratio < 1)
3749 return 0;
3750
3751 /* Use table for ratios 1:1 - 99:1 */
3752 return (int)ratio2dB[sig_ratio];
3753}
3754
3755#define PERFECT_RSSI (-20) /* dBm */
3756#define WORST_RSSI (-95) /* dBm */
3757#define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
3758
3759/* Calculate an indication of rx signal quality (a percentage, not dBm!).
3760 * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
3761 * about formulas used below. */
bb8c093b 3762int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
b481de9c
ZY		 3763{
3764 int sig_qual;
3765 int degradation = PERFECT_RSSI - rssi_dbm;
3766
3767 /* If we get a noise measurement, use signal-to-noise ratio (SNR)
3768 * as indicator; formula is (signal dbm - noise dbm).
3769 * SNR at or above 40 is a great signal (100%).
3770 * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
3771 * Weakest usable signal is usually 10 - 15 dB SNR. */
3772 if (noise_dbm) {
3773 if (rssi_dbm - noise_dbm >= 40)
3774 return 100;
3775 else if (rssi_dbm < noise_dbm)
3776 return 0;
3777 sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
3778
3779 /* Else use just the signal level.
3780 * This formula is a least squares fit of data points collected and
3781 * compared with a reference system that had a percentage (%) display
3782 * for signal quality. */
3783 } else
3784 sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
3785 (15 * RSSI_RANGE + 62 * degradation)) /
3786 (RSSI_RANGE * RSSI_RANGE);
3787
3788 if (sig_qual > 100)
3789 sig_qual = 100;
3790 else if (sig_qual < 1)
3791 sig_qual = 0;
3792
3793 return sig_qual;
3794}
3795
3796/**
9fbab516 3797 * iwl3945_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY		 3798 *
3799 * Uses the priv->rx_handlers callback function array to invoke
3800 * the appropriate handlers, including command responses,
3801 * frame-received notifications, and other notifications.
3802 */
bb8c093b 3803static void iwl3945_rx_handle(struct iwl3945_priv *priv)
b481de9c 3804{
bb8c093b
CH		 3805 struct iwl3945_rx_mem_buffer *rxb;
3806 struct iwl3945_rx_packet *pkt;
3807 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 3808 u32 r, i;
3809 int reclaim;
3810 unsigned long flags;
5c0eef96 3811 u8 fill_rx = 0;
d68ab680 3812 u32 count = 8;
b481de9c 3813
6440adb5
CB		 3814 /* uCode's read index (stored in shared DRAM) indicates the last Rx
3815 * buffer that the driver may process (last buffer filled by ucode). */
bb8c093b 3816 r = iwl3945_hw_get_rx_read(priv);
b481de9c
ZY		 3817 i = rxq->read;
3818
5c0eef96
MA		 3819 if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
3820 fill_rx = 1;
b481de9c
ZY		 3821 /* Rx interrupt, but nothing sent from uCode */
3822 if (i == r)
3823 IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
3824
3825 while (i != r) {
3826 rxb = rxq->queue[i];
3827
9fbab516 3828 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY		 3829 * then a bug has been introduced in the queue refilling
3830 * routines -- catch it here */
3831 BUG_ON(rxb == NULL);
3832
3833 rxq->queue[i] = NULL;
3834
3835 pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
3836 IWL_RX_BUF_SIZE,
3837 PCI_DMA_FROMDEVICE);
bb8c093b 3838 pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
b481de9c
ZY		 3839
3840 /* Reclaim a command buffer only if this packet is a response
3841 * to a (driver-originated) command.
3842 * If the packet (e.g. Rx frame) originated from uCode,
3843 * there is no command buffer to reclaim.
3844 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
3845 * but apparently a few don't get set; catch them here. */
3846 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
3847 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
3848 (pkt->hdr.cmd != REPLY_TX);
3849
3850 /* Based on type of command response or notification,
3851 * handle those that need handling via function in
bb8c093b 3852 * rx_handlers table. See iwl3945_setup_rx_handlers() */
b481de9c
ZY		 3853 if (priv->rx_handlers[pkt->hdr.cmd]) {
3854 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
3855 "r = %d, i = %d, %s, 0x%02x\n", r, i,
3856 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
3857 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
3858 } else {
3859 /* No handling needed */
3860 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
3861 "r %d i %d No handler needed for %s, 0x%02x\n",
3862 r, i, get_cmd_string(pkt->hdr.cmd),
3863 pkt->hdr.cmd);
3864 }
3865
3866 if (reclaim) {
9fbab516
BC		 3867 /* Invoke any callbacks, transfer the skb to caller, and
3868 * fire off the (possibly) blocking iwl3945_send_cmd()
b481de9c
ZY		 3869 * as we reclaim the driver command queue */
3870 if (rxb && rxb->skb)
bb8c093b 3871 iwl3945_tx_cmd_complete(priv, rxb);
b481de9c
ZY		 3872 else
3873 IWL_WARNING("Claim null rxb?\n");
3874 }
3875
3876 /* For now we just don't re-use anything. We can tweak this
3877 * later to try and re-use notification packets and SKBs that
3878 * fail to Rx correctly */
3879 if (rxb->skb != NULL) {
3880 priv->alloc_rxb_skb--;
3881 dev_kfree_skb_any(rxb->skb);
3882 rxb->skb = NULL;
3883 }
3884
3885 pci_unmap_single(priv->pci_dev, rxb->dma_addr,
3886 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3887 spin_lock_irqsave(&rxq->lock, flags);
3888 list_add_tail(&rxb->list, &priv->rxq.rx_used);
3889 spin_unlock_irqrestore(&rxq->lock, flags);
3890 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA		 3891 /* If there are a lot of unused frames,
3892 * restock the Rx queue so ucode won't assert. */
3893 if (fill_rx) {
3894 count++;
3895 if (count >= 8) {
3896 priv->rxq.read = i;
3897 __iwl3945_rx_replenish(priv);
3898 count = 0;
3899 }
3900 }
b481de9c
ZY		 3901 }
3902
3903 /* Backtrack one entry */
3904 priv->rxq.read = i;
bb8c093b 3905 iwl3945_rx_queue_restock(priv);
b481de9c
ZY		 3906}
3907
6440adb5
CB		 3908/**
3909 * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
3910 */
bb8c093b
CH		 3911static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
3912 struct iwl3945_tx_queue *txq)
b481de9c
ZY		 3913{
3914 u32 reg = 0;
3915 int rc = 0;
3916 int txq_id = txq->q.id;
3917
3918 if (txq->need_update == 0)
3919 return rc;
3920
3921 /* if we're trying to save power */
3922 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
3923 /* wake up nic if it's powered down ...
3924 * uCode will wake up, and interrupt us again, so next
3925 * time we'll skip this part. */
bb8c093b 3926 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY		 3927
3928 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
3929 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
bb8c093b 3930 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 3931 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3932 return rc;
3933 }
3934
3935 /* restore this queue's parameters in nic hardware. */
bb8c093b 3936 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 3937 if (rc)
3938 return rc;
bb8c093b 3939 iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
fc4b6853 3940 txq->q.write_ptr | (txq_id << 8));
bb8c093b 3941 iwl3945_release_nic_access(priv);
b481de9c
ZY		 3942
3943 /* else not in power-save mode, uCode will never sleep when we're
3944 * trying to tx (during RFKILL, we're not trying to tx). */
3945 } else
bb8c093b 3946 iwl3945_write32(priv, HBUS_TARG_WRPTR,
fc4b6853 3947 txq->q.write_ptr | (txq_id << 8));
b481de9c
ZY		 3948
3949 txq->need_update = 0;
3950
3951 return rc;
3952}
3953
c8b0e6e1 3954#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 3955static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon)
b481de9c
ZY		 3956{
3957 IWL_DEBUG_RADIO("RX CONFIG:\n");
bb8c093b 3958 iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
b481de9c
ZY		 3959 IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
3960 IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
3961 IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
3962 le32_to_cpu(rxon->filter_flags));
3963 IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
3964 IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
3965 rxon->ofdm_basic_rates);
3966 IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
e174961c
JB		 3967 IWL_DEBUG_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
3968 IWL_DEBUG_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
b481de9c
ZY		 3969 IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
3970}
3971#endif
3972
bb8c093b 3973static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
b481de9c
ZY		 3974{
3975 IWL_DEBUG_ISR("Enabling interrupts\n");
3976 set_bit(STATUS_INT_ENABLED, &priv->status);
bb8c093b 3977 iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
b481de9c
ZY		 3978}
3979
0359facc
MA		 3980
3981/* call this function to flush any scheduled tasklet */
3982static inline void iwl_synchronize_irq(struct iwl3945_priv *priv)
3983{
a96a27f9 3984 /* wait to make sure we flush pending tasklet*/
0359facc
MA		 3985 synchronize_irq(priv->pci_dev->irq);
3986 tasklet_kill(&priv->irq_tasklet);
3987}
3988
3989
bb8c093b 3990static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
b481de9c
ZY		 3991{
3992 clear_bit(STATUS_INT_ENABLED, &priv->status);
3993
3994 /* disable interrupts from uCode/NIC to host */
bb8c093b 3995 iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY		 3996
3997 /* acknowledge/clear/reset any interrupts still pending
3998 * from uCode or flow handler (Rx/Tx DMA) */
bb8c093b
CH		 3999 iwl3945_write32(priv, CSR_INT, 0xffffffff);
4000 iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
b481de9c
ZY		 4001 IWL_DEBUG_ISR("Disabled interrupts\n");
4002}
4003
4004static const char *desc_lookup(int i)
4005{
4006 switch (i) {
4007 case 1:
4008 return "FAIL";
4009 case 2:
4010 return "BAD_PARAM";
4011 case 3:
4012 return "BAD_CHECKSUM";
4013 case 4:
4014 return "NMI_INTERRUPT";
4015 case 5:
4016 return "SYSASSERT";
4017 case 6:
4018 return "FATAL_ERROR";
4019 }
4020
4021 return "UNKNOWN";
4022}
4023
4024#define ERROR_START_OFFSET (1 * sizeof(u32))
4025#define ERROR_ELEM_SIZE (7 * sizeof(u32))
4026
bb8c093b 4027static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
b481de9c
ZY		 4028{
4029 u32 i;
4030 u32 desc, time, count, base, data1;
4031 u32 blink1, blink2, ilink1, ilink2;
4032 int rc;
4033
4034 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
4035
bb8c093b 4036 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 4037 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
4038 return;
4039 }
4040
bb8c093b 4041 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 4042 if (rc) {
4043 IWL_WARNING("Can not read from adapter at this time.\n");
4044 return;
4045 }
4046
bb8c093b 4047 count = iwl3945_read_targ_mem(priv, base);
b481de9c
ZY		 4048
4049 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
4050 IWL_ERROR("Start IWL Error Log Dump:\n");
2acae16e 4051 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
b481de9c
ZY		 4052 }
4053
4054 IWL_ERROR("Desc Time asrtPC blink2 "
4055 "ilink1 nmiPC Line\n");
4056 for (i = ERROR_START_OFFSET;
4057 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
4058 i += ERROR_ELEM_SIZE) {
bb8c093b 4059 desc = iwl3945_read_targ_mem(priv, base + i);
b481de9c 4060 time =
bb8c093b 4061 iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
b481de9c 4062 blink1 =
bb8c093b 4063 iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
b481de9c 4064 blink2 =
bb8c093b 4065 iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
b481de9c 4066 ilink1 =
bb8c093b 4067 iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
b481de9c 4068 ilink2 =
bb8c093b 4069 iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
b481de9c 4070 data1 =
bb8c093b 4071 iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
b481de9c
ZY		 4072
4073 IWL_ERROR
4074 ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
4075 desc_lookup(desc), desc, time, blink1, blink2,
4076 ilink1, ilink2, data1);
4077 }
4078
bb8c093b 4079 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4080
4081}
4082
f58177b9 4083#define EVENT_START_OFFSET (6 * sizeof(u32))
b481de9c
ZY		 4084
4085/**
bb8c093b 4086 * iwl3945_print_event_log - Dump error event log to syslog
b481de9c 4087 *
bb8c093b 4088 * NOTE: Must be called with iwl3945_grab_nic_access() already obtained!
b481de9c 4089 */
bb8c093b 4090static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
b481de9c
ZY		 4091 u32 num_events, u32 mode)
4092{
4093 u32 i;
4094 u32 base; /* SRAM byte address of event log header */
4095 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
4096 u32 ptr; /* SRAM byte address of log data */
4097 u32 ev, time, data; /* event log data */
4098
4099 if (num_events == 0)
4100 return;
4101
4102 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
4103
4104 if (mode == 0)
4105 event_size = 2 * sizeof(u32);
4106 else
4107 event_size = 3 * sizeof(u32);
4108
4109 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
4110
4111 /* "time" is actually "data" for mode 0 (no timestamp).
4112 * place event id # at far right for easier visual parsing. */
4113 for (i = 0; i < num_events; i++) {
bb8c093b 4114 ev = iwl3945_read_targ_mem(priv, ptr);
b481de9c 4115 ptr += sizeof(u32);
bb8c093b 4116 time = iwl3945_read_targ_mem(priv, ptr);
b481de9c
ZY		 4117 ptr += sizeof(u32);
4118 if (mode == 0)
4119 IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
4120 else {
bb8c093b 4121 data = iwl3945_read_targ_mem(priv, ptr);
b481de9c
ZY		 4122 ptr += sizeof(u32);
4123 IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
4124 }
4125 }
4126}
4127
bb8c093b 4128static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
b481de9c
ZY		 4129{
4130 int rc;
4131 u32 base; /* SRAM byte address of event log header */
4132 u32 capacity; /* event log capacity in # entries */
4133 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
4134 u32 num_wraps; /* # times uCode wrapped to top of log */
4135 u32 next_entry; /* index of next entry to be written by uCode */
4136 u32 size; /* # entries that we'll print */
4137
4138 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 4139 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 4140 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
4141 return;
4142 }
4143
bb8c093b 4144 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 4145 if (rc) {
4146 IWL_WARNING("Can not read from adapter at this time.\n");
4147 return;
4148 }
4149
4150 /* event log header */
bb8c093b
CH		 4151 capacity = iwl3945_read_targ_mem(priv, base);
4152 mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
4153 num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
4154 next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
b481de9c
ZY		 4155
4156 size = num_wraps ? capacity : next_entry;
4157
4158 /* bail out if nothing in log */
4159 if (size == 0) {
583fab37 4160 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
bb8c093b 4161 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4162 return;
4163 }
4164
583fab37 4165 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
b481de9c
ZY		 4166 size, num_wraps);
4167
4168 /* if uCode has wrapped back to top of log, start at the oldest entry,
4169 * i.e the next one that uCode would fill. */
4170 if (num_wraps)
bb8c093b 4171 iwl3945_print_event_log(priv, next_entry,
b481de9c
ZY		 4172 capacity - next_entry, mode);
4173
4174 /* (then/else) start at top of log */
bb8c093b 4175 iwl3945_print_event_log(priv, 0, next_entry, mode);
b481de9c 4176
bb8c093b 4177 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4178}
4179
4180/**
bb8c093b 4181 * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
b481de9c 4182 */
bb8c093b 4183static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
b481de9c 4184{
bb8c093b 4185 /* Set the FW error flag -- cleared on iwl3945_down */
b481de9c
ZY		 4186 set_bit(STATUS_FW_ERROR, &priv->status);
4187
4188 /* Cancel currently queued command. */
4189 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
4190
c8b0e6e1 4191#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 4192 if (iwl3945_debug_level & IWL_DL_FW_ERRORS) {
4193 iwl3945_dump_nic_error_log(priv);
4194 iwl3945_dump_nic_event_log(priv);
4195 iwl3945_print_rx_config_cmd(&priv->staging_rxon);
b481de9c
ZY		 4196 }
4197#endif
4198
4199 wake_up_interruptible(&priv->wait_command_queue);
4200
4201 /* Keep the restart process from trying to send host
4202 * commands by clearing the INIT status bit */
4203 clear_bit(STATUS_READY, &priv->status);
4204
4205 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
4206 IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
4207 "Restarting adapter due to uCode error.\n");
4208
bb8c093b 4209 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 4210 memcpy(&priv->recovery_rxon, &priv->active_rxon,
4211 sizeof(priv->recovery_rxon));
4212 priv->error_recovering = 1;
4213 }
4214 queue_work(priv->workqueue, &priv->restart);
4215 }
4216}
4217
bb8c093b 4218static void iwl3945_error_recovery(struct iwl3945_priv *priv)
b481de9c
ZY		 4219{
4220 unsigned long flags;
4221
4222 memcpy(&priv->staging_rxon, &priv->recovery_rxon,
4223 sizeof(priv->staging_rxon));
4224 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 4225 iwl3945_commit_rxon(priv);
b481de9c 4226
bb8c093b 4227 iwl3945_add_station(priv, priv->bssid, 1, 0);
b481de9c
ZY		 4228
4229 spin_lock_irqsave(&priv->lock, flags);
4230 priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
4231 priv->error_recovering = 0;
4232 spin_unlock_irqrestore(&priv->lock, flags);
4233}
4234
bb8c093b 4235static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
b481de9c
ZY		 4236{
4237 u32 inta, handled = 0;
4238 u32 inta_fh;
4239 unsigned long flags;
c8b0e6e1 4240#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 4241 u32 inta_mask;
4242#endif
4243
4244 spin_lock_irqsave(&priv->lock, flags);
4245
4246 /* Ack/clear/reset pending uCode interrupts.
4247 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
4248 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
bb8c093b
CH		 4249 inta = iwl3945_read32(priv, CSR_INT);
4250 iwl3945_write32(priv, CSR_INT, inta);
b481de9c
ZY		 4251
4252 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
4253 * Any new interrupts that happen after this, either while we're
4254 * in this tasklet, or later, will show up in next ISR/tasklet. */
bb8c093b
CH		 4255 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
4256 iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 4257
c8b0e6e1 4258#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4259 if (iwl3945_debug_level & IWL_DL_ISR) {
9fbab516
BC		 4260 /* just for debug */
4261 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
b481de9c
ZY		 4262 IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4263 inta, inta_mask, inta_fh);
4264 }
4265#endif
4266
4267 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
4268 * atomic, make sure that inta covers all the interrupts that
4269 * we've discovered, even if FH interrupt came in just after
4270 * reading CSR_INT. */
6f83eaa1 4271 if (inta_fh & CSR39_FH_INT_RX_MASK)
b481de9c 4272 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 4273 if (inta_fh & CSR39_FH_INT_TX_MASK)
b481de9c
ZY		 4274 inta |= CSR_INT_BIT_FH_TX;
4275
4276 /* Now service all interrupt bits discovered above. */
4277 if (inta & CSR_INT_BIT_HW_ERR) {
4278 IWL_ERROR("Microcode HW error detected. Restarting.\n");
4279
4280 /* Tell the device to stop sending interrupts */
bb8c093b 4281 iwl3945_disable_interrupts(priv);
b481de9c 4282
bb8c093b 4283 iwl3945_irq_handle_error(priv);
b481de9c
ZY		 4284
4285 handled |= CSR_INT_BIT_HW_ERR;
4286
4287 spin_unlock_irqrestore(&priv->lock, flags);
4288
4289 return;
4290 }
4291
c8b0e6e1 4292#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4293 if (iwl3945_debug_level & (IWL_DL_ISR)) {
b481de9c 4294 /* NIC fires this, but we don't use it, redundant with WAKEUP */
25c03d8e
JP		 4295 if (inta & CSR_INT_BIT_SCD)
4296 IWL_DEBUG_ISR("Scheduler finished to transmit "
4297 "the frame/frames.\n");
b481de9c
ZY		 4298
4299 /* Alive notification via Rx interrupt will do the real work */
4300 if (inta & CSR_INT_BIT_ALIVE)
4301 IWL_DEBUG_ISR("Alive interrupt\n");
4302 }
4303#endif
4304 /* Safely ignore these bits for debug checks below */
25c03d8e 4305 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 4306
b481de9c
ZY		 4307 /* Error detected by uCode */
4308 if (inta & CSR_INT_BIT_SW_ERR) {
4309 IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
4310 inta);
bb8c093b 4311 iwl3945_irq_handle_error(priv);
b481de9c
ZY		 4312 handled |= CSR_INT_BIT_SW_ERR;
4313 }
4314
4315 /* uCode wakes up after power-down sleep */
4316 if (inta & CSR_INT_BIT_WAKEUP) {
4317 IWL_DEBUG_ISR("Wakeup interrupt\n");
bb8c093b
CH		 4318 iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
4319 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
4320 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
4321 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
4322 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
4323 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
4324 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
b481de9c
ZY		 4325
4326 handled |= CSR_INT_BIT_WAKEUP;
4327 }
4328
4329 /* All uCode command responses, including Tx command responses,
4330 * Rx "responses" (frame-received notification), and other
4331 * notifications from uCode come through here*/
4332 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
bb8c093b 4333 iwl3945_rx_handle(priv);
b481de9c
ZY		 4334 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
4335 }
4336
4337 if (inta & CSR_INT_BIT_FH_TX) {
4338 IWL_DEBUG_ISR("Tx interrupt\n");
4339
bb8c093b
CH		 4340 iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
4341 if (!iwl3945_grab_nic_access(priv)) {
4342 iwl3945_write_direct32(priv,
b481de9c
ZY		 4343 FH_TCSR_CREDIT
4344 (ALM_FH_SRVC_CHNL), 0x0);
bb8c093b 4345 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4346 }
4347 handled |= CSR_INT_BIT_FH_TX;
4348 }
4349
4350 if (inta & ~handled)
4351 IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
4352
4353 if (inta & ~CSR_INI_SET_MASK) {
4354 IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
4355 inta & ~CSR_INI_SET_MASK);
4356 IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
4357 }
4358
4359 /* Re-enable all interrupts */
0359facc
MA		 4360 /* only Re-enable if disabled by irq */
4361 if (test_bit(STATUS_INT_ENABLED, &priv->status))
4362 iwl3945_enable_interrupts(priv);
b481de9c 4363
c8b0e6e1 4364#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 4365 if (iwl3945_debug_level & (IWL_DL_ISR)) {
4366 inta = iwl3945_read32(priv, CSR_INT);
4367 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
4368 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY		 4369 IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4370 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
4371 }
4372#endif
4373 spin_unlock_irqrestore(&priv->lock, flags);
4374}
4375
bb8c093b 4376static irqreturn_t iwl3945_isr(int irq, void *data)
b481de9c 4377{
bb8c093b 4378 struct iwl3945_priv *priv = data;
b481de9c
ZY		 4379 u32 inta, inta_mask;
4380 u32 inta_fh;
4381 if (!priv)
4382 return IRQ_NONE;
4383
4384 spin_lock(&priv->lock);
4385
4386 /* Disable (but don't clear!) interrupts here to avoid
4387 * back-to-back ISRs and sporadic interrupts from our NIC.
4388 * If we have something to service, the tasklet will re-enable ints.
4389 * If we *don't* have something, we'll re-enable before leaving here. */
bb8c093b
CH		 4390 inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */
4391 iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY		 4392
4393 /* Discover which interrupts are active/pending */
bb8c093b
CH		 4394 inta = iwl3945_read32(priv, CSR_INT);
4395 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY		 4396
4397 /* Ignore interrupt if there's nothing in NIC to service.
4398 * This may be due to IRQ shared with another device,
4399 * or due to sporadic interrupts thrown from our NIC. */
4400 if (!inta && !inta_fh) {
4401 IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
4402 goto none;
4403 }
4404
4405 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
4406 /* Hardware disappeared */
99df630c 4407 IWL_WARNING("HARDWARE GONE?? INTA == 0x%08x\n", inta);
cb4da1a3 4408 goto unplugged;
b481de9c
ZY		 4409 }
4410
4411 IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4412 inta, inta_mask, inta_fh);
4413
25c03d8e
JP		 4414 inta &= ~CSR_INT_BIT_SCD;
4415
bb8c093b 4416 /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
25c03d8e
JP		 4417 if (likely(inta || inta_fh))
4418 tasklet_schedule(&priv->irq_tasklet);
cb4da1a3 4419unplugged:
b481de9c
ZY		 4420 spin_unlock(&priv->lock);
4421
4422 return IRQ_HANDLED;
4423
4424 none:
4425 /* re-enable interrupts here since we don't have anything to service. */
0359facc
MA		 4426 /* only Re-enable if disabled by irq */
4427 if (test_bit(STATUS_INT_ENABLED, &priv->status))
4428 iwl3945_enable_interrupts(priv);
b481de9c
ZY		 4429 spin_unlock(&priv->lock);
4430 return IRQ_NONE;
4431}
4432
4433/************************** EEPROM BANDS ****************************
4434 *
bb8c093b 4435 * The iwl3945_eeprom_band definitions below provide the mapping from the
b481de9c
ZY		 4436 * EEPROM contents to the specific channel number supported for each
4437 * band.
4438 *
bb8c093b 4439 * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3
b481de9c
ZY		 4440 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
4441 * The specific geography and calibration information for that channel
4442 * is contained in the eeprom map itself.
4443 *
4444 * During init, we copy the eeprom information and channel map
4445 * information into priv->channel_info_24/52 and priv->channel_map_24/52
4446 *
4447 * channel_map_24/52 provides the index in the channel_info array for a
4448 * given channel. We have to have two separate maps as there is channel
4449 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
4450 * band_2
4451 *
4452 * A value of 0xff stored in the channel_map indicates that the channel
4453 * is not supported by the hardware at all.
4454 *
4455 * A value of 0xfe in the channel_map indicates that the channel is not
4456 * valid for Tx with the current hardware. This means that
4457 * while the system can tune and receive on a given channel, it may not
4458 * be able to associate or transmit any frames on that
4459 * channel. There is no corresponding channel information for that
4460 * entry.
4461 *
4462 *********************************************************************/
4463
4464/* 2.4 GHz */
bb8c093b 4465static const u8 iwl3945_eeprom_band_1[14] = {
b481de9c
ZY		 4466 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
4467};
4468
4469/* 5.2 GHz bands */
9fbab516 4470static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
b481de9c
ZY		 4471 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
4472};
4473
9fbab516 4474static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
b481de9c
ZY		 4475 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
4476};
4477
bb8c093b 4478static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
b481de9c
ZY		 4479 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
4480};
4481
bb8c093b 4482static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
b481de9c
ZY		 4483 145, 149, 153, 157, 161, 165
4484};
4485
bb8c093b 4486static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
b481de9c 4487 int *eeprom_ch_count,
bb8c093b 4488 const struct iwl3945_eeprom_channel
b481de9c
ZY		 4489 **eeprom_ch_info,
4490 const u8 **eeprom_ch_index)
4491{
4492 switch (band) {
4493 case 1: /* 2.4GHz band */
bb8c093b 4494 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
b481de9c 4495 *eeprom_ch_info = priv->eeprom.band_1_channels;
bb8c093b 4496 *eeprom_ch_index = iwl3945_eeprom_band_1;
b481de9c 4497 break;
9fbab516 4498 case 2: /* 4.9GHz band */
bb8c093b 4499 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
b481de9c 4500 *eeprom_ch_info = priv->eeprom.band_2_channels;
bb8c093b 4501 *eeprom_ch_index = iwl3945_eeprom_band_2;
b481de9c
ZY		 4502 break;
4503 case 3: /* 5.2GHz band */
bb8c093b 4504 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
b481de9c 4505 *eeprom_ch_info = priv->eeprom.band_3_channels;
bb8c093b 4506 *eeprom_ch_index = iwl3945_eeprom_band_3;
b481de9c 4507 break;
9fbab516 4508 case 4: /* 5.5GHz band */
bb8c093b 4509 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
b481de9c 4510 *eeprom_ch_info = priv->eeprom.band_4_channels;
bb8c093b 4511 *eeprom_ch_index = iwl3945_eeprom_band_4;
b481de9c 4512 break;
9fbab516 4513 case 5: /* 5.7GHz band */
bb8c093b 4514 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
b481de9c 4515 *eeprom_ch_info = priv->eeprom.band_5_channels;
bb8c093b 4516 *eeprom_ch_index = iwl3945_eeprom_band_5;
b481de9c
ZY		 4517 break;
4518 default:
4519 BUG();
4520 return;
4521 }
4522}
4523
6440adb5
CB		 4524/**
4525 * iwl3945_get_channel_info - Find driver's private channel info
4526 *
4527 * Based on band and channel number.
4528 */
bb8c093b 4529const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv,
8318d78a 4530 enum ieee80211_band band, u16 channel)
b481de9c
ZY		 4531{
4532 int i;
4533
8318d78a
JB		 4534 switch (band) {
4535 case IEEE80211_BAND_5GHZ:
b481de9c
ZY		 4536 for (i = 14; i < priv->channel_count; i++) {
4537 if (priv->channel_info[i].channel == channel)
4538 return &priv->channel_info[i];
4539 }
4540 break;
4541
8318d78a 4542 case IEEE80211_BAND_2GHZ:
b481de9c
ZY		 4543 if (channel >= 1 && channel <= 14)
4544 return &priv->channel_info[channel - 1];
4545 break;
8318d78a
JB		 4546 case IEEE80211_NUM_BANDS:
4547 WARN_ON(1);
b481de9c
ZY		 4548 }
4549
4550 return NULL;
4551}
4552
4553#define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
4554 ? # x " " : "")
4555
6440adb5
CB		 4556/**
4557 * iwl3945_init_channel_map - Set up driver's info for all possible channels
4558 */
bb8c093b 4559static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
b481de9c
ZY		 4560{
4561 int eeprom_ch_count = 0;
4562 const u8 *eeprom_ch_index = NULL;
bb8c093b 4563 const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL;
b481de9c 4564 int band, ch;
bb8c093b 4565 struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 4566
4567 if (priv->channel_count) {
4568 IWL_DEBUG_INFO("Channel map already initialized.\n");
4569 return 0;
4570 }
4571
4572 if (priv->eeprom.version < 0x2f) {
4573 IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
4574 priv->eeprom.version);
4575 return -EINVAL;
4576 }
4577
4578 IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
4579
4580 priv->channel_count =
bb8c093b
CH		 4581 ARRAY_SIZE(iwl3945_eeprom_band_1) +
4582 ARRAY_SIZE(iwl3945_eeprom_band_2) +
4583 ARRAY_SIZE(iwl3945_eeprom_band_3) +
4584 ARRAY_SIZE(iwl3945_eeprom_band_4) +
4585 ARRAY_SIZE(iwl3945_eeprom_band_5);
b481de9c
ZY		 4586
4587 IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
4588
bb8c093b 4589 priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) *
b481de9c
ZY		 4590 priv->channel_count, GFP_KERNEL);
4591 if (!priv->channel_info) {
4592 IWL_ERROR("Could not allocate channel_info\n");
4593 priv->channel_count = 0;
4594 return -ENOMEM;
4595 }
4596
4597 ch_info = priv->channel_info;
4598
4599 /* Loop through the 5 EEPROM bands adding them in order to the
4600 * channel map we maintain (that contains additional information than
4601 * what just in the EEPROM) */
4602 for (band = 1; band <= 5; band++) {
4603
bb8c093b 4604 iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
b481de9c
ZY		 4605 &eeprom_ch_info, &eeprom_ch_index);
4606
4607 /* Loop through each band adding each of the channels */
4608 for (ch = 0; ch < eeprom_ch_count; ch++) {
4609 ch_info->channel = eeprom_ch_index[ch];
8318d78a
JB		 4610 ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
4611 IEEE80211_BAND_5GHZ;
b481de9c
ZY		 4612
4613 /* permanently store EEPROM's channel regulatory flags
4614 * and max power in channel info database. */
4615 ch_info->eeprom = eeprom_ch_info[ch];
4616
4617 /* Copy the run-time flags so they are there even on
4618 * invalid channels */
4619 ch_info->flags = eeprom_ch_info[ch].flags;
4620
4621 if (!(is_channel_valid(ch_info))) {
4622 IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
4623 "No traffic\n",
4624 ch_info->channel,
4625 ch_info->flags,
4626 is_channel_a_band(ch_info) ?
4627 "5.2" : "2.4");
4628 ch_info++;
4629 continue;
4630 }
4631
4632 /* Initialize regulatory-based run-time data */
4633 ch_info->max_power_avg = ch_info->curr_txpow =
4634 eeprom_ch_info[ch].max_power_avg;
4635 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
4636 ch_info->min_power = 0;
4637
fe7c4040 4638 IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
b481de9c
ZY		 4639 " %ddBm): Ad-Hoc %ssupported\n",
4640 ch_info->channel,
4641 is_channel_a_band(ch_info) ?
4642 "5.2" : "2.4",
8211ef78 4643 CHECK_AND_PRINT(VALID),
b481de9c
ZY		 4644 CHECK_AND_PRINT(IBSS),
4645 CHECK_AND_PRINT(ACTIVE),
4646 CHECK_AND_PRINT(RADAR),
4647 CHECK_AND_PRINT(WIDE),
b481de9c
ZY		 4648 CHECK_AND_PRINT(DFS),
4649 eeprom_ch_info[ch].flags,
4650 eeprom_ch_info[ch].max_power_avg,
4651 ((eeprom_ch_info[ch].
4652 flags & EEPROM_CHANNEL_IBSS)
4653 && !(eeprom_ch_info[ch].
4654 flags & EEPROM_CHANNEL_RADAR))
4655 ? "" : "not ");
4656
4657 /* Set the user_txpower_limit to the highest power
4658 * supported by any channel */
4659 if (eeprom_ch_info[ch].max_power_avg >
4660 priv->user_txpower_limit)
4661 priv->user_txpower_limit =
4662 eeprom_ch_info[ch].max_power_avg;
4663
4664 ch_info++;
4665 }
4666 }
4667
6440adb5 4668 /* Set up txpower settings in driver for all channels */
b481de9c
ZY		 4669 if (iwl3945_txpower_set_from_eeprom(priv))
4670 return -EIO;
4671
4672 return 0;
4673}
4674
849e0dce
RC		 4675/*
4676 * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
4677 */
4678static void iwl3945_free_channel_map(struct iwl3945_priv *priv)
4679{
4680 kfree(priv->channel_info);
4681 priv->channel_count = 0;
4682}
4683
b481de9c
ZY		 4684/* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
4685 * sending probe req. This should be set long enough to hear probe responses
4686 * from more than one AP. */
f9340520
AK		 4687#define IWL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
4688#define IWL_ACTIVE_DWELL_TIME_52 (20)
4689
4690#define IWL_ACTIVE_DWELL_FACTOR_24GHZ (3)
4691#define IWL_ACTIVE_DWELL_FACTOR_52GHZ (2)
b481de9c
ZY		 4692
4693/* For faster active scanning, scan will move to the next channel if fewer than
4694 * PLCP_QUIET_THRESH packets are heard on this channel within
4695 * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
4696 * time if it's a quiet channel (nothing responded to our probe, and there's
4697 * no other traffic).
4698 * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
4699#define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
f9340520 4700#define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(10) /* msec */
b481de9c
ZY		 4701
4702/* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
4703 * Must be set longer than active dwell time.
4704 * For the most reliable scan, set > AP beacon interval (typically 100msec). */
4705#define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
4706#define IWL_PASSIVE_DWELL_TIME_52 (10)
4707#define IWL_PASSIVE_DWELL_BASE (100)
4708#define IWL_CHANNEL_TUNE_TIME 5
4709
e720ce9d 4710#define IWL_SCAN_PROBE_MASK(n) (BIT(n) | (BIT(n) - BIT(1)))
f9340520 4711
8318d78a 4712static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv,
f9340520
AK		 4713 enum ieee80211_band band,
4714 u8 n_probes)
b481de9c 4715{
8318d78a 4716 if (band == IEEE80211_BAND_5GHZ)
f9340520
AK		 4717 return IWL_ACTIVE_DWELL_TIME_52 +
4718 IWL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
b481de9c 4719 else
f9340520
AK		 4720 return IWL_ACTIVE_DWELL_TIME_24 +
4721 IWL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
b481de9c
ZY		 4722}
4723
8318d78a
JB		 4724static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv,
4725 enum ieee80211_band band)
b481de9c 4726{
8318d78a 4727 u16 passive = (band == IEEE80211_BAND_2GHZ) ?
b481de9c
ZY		 4728 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
4729 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
4730
bb8c093b 4731 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 4732 /* If we're associated, we clamp the maximum passive
4733 * dwell time to be 98% of the beacon interval (minus
4734 * 2 * channel tune time) */
4735 passive = priv->beacon_int;
4736 if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
4737 passive = IWL_PASSIVE_DWELL_BASE;
4738 passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
4739 }
4740
b481de9c
ZY		 4741 return passive;
4742}
4743
8318d78a
JB		 4744static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv,
4745 enum ieee80211_band band,
f9340520 4746 u8 is_active, u8 n_probes,
bb8c093b 4747 struct iwl3945_scan_channel *scan_ch)
b481de9c
ZY		 4748{
4749 const struct ieee80211_channel *channels = NULL;
8318d78a 4750 const struct ieee80211_supported_band *sband;
bb8c093b 4751 const struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 4752 u16 passive_dwell = 0;
4753 u16 active_dwell = 0;
4754 int added, i;
4755
8318d78a
JB		 4756 sband = iwl3945_get_band(priv, band);
4757 if (!sband)
b481de9c
ZY		 4758 return 0;
4759
8318d78a 4760 channels = sband->channels;
b481de9c 4761
f9340520 4762 active_dwell = iwl3945_get_active_dwell_time(priv, band, n_probes);
8318d78a 4763 passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
b481de9c 4764
8f4807a1
AK		 4765 if (passive_dwell <= active_dwell)
4766 passive_dwell = active_dwell + 1;
4767
8318d78a 4768 for (i = 0, added = 0; i < sband->n_channels; i++) {
182e2e66
JB		 4769 if (channels[i].flags & IEEE80211_CHAN_DISABLED)
4770 continue;
4771
8318d78a 4772 scan_ch->channel = channels[i].hw_value;
b481de9c 4773
8318d78a 4774 ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
b481de9c 4775 if (!is_channel_valid(ch_info)) {
66b5004d 4776 IWL_DEBUG_SCAN("Channel %d is INVALID for this band.\n",
b481de9c
ZY		 4777 scan_ch->channel);
4778 continue;
4779 }
4780
011a0330
AK		 4781 scan_ch->active_dwell = cpu_to_le16(active_dwell);
4782 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
4783 /* If passive , set up for auto-switch
4784 * and use long active_dwell time.
4785 */
b481de9c 4786 if (!is_active || is_channel_passive(ch_info) ||
011a0330 4787 (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
b481de9c 4788 scan_ch->type = 0; /* passive */
011a0330
AK		 4789 if (IWL_UCODE_API(priv->ucode_ver) == 1)
4790 scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
4791 } else {
b481de9c 4792 scan_ch->type = 1; /* active */
011a0330 4793 }
b481de9c 4794
011a0330
AK		 4795 /* Set direct probe bits. These may be used both for active
4796 * scan channels (probes gets sent right away),
4797 * or for passive channels (probes get se sent only after
4798 * hearing clear Rx packet).*/
4799 if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
4800 if (n_probes)
4801 scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
4802 } else {
4803 /* uCode v1 does not allow setting direct probe bits on
4804 * passive channel. */
4805 if ((scan_ch->type & 1) && n_probes)
4806 scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
4807 }
b481de9c 4808
9fbab516 4809 /* Set txpower levels to defaults */
b481de9c
ZY		 4810 scan_ch->tpc.dsp_atten = 110;
4811 /* scan_pwr_info->tpc.dsp_atten; */
4812
4813 /*scan_pwr_info->tpc.tx_gain; */
8318d78a 4814 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 4815 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
4816 else {
4817 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
4818 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
9fbab516 4819 * power level:
8a1b0245 4820 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
b481de9c
ZY		 4821 */
4822 }
4823
4824 IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
4825 scan_ch->channel,
4826 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
4827 (scan_ch->type & 1) ?
4828 active_dwell : passive_dwell);
4829
4830 scan_ch++;
4831 added++;
4832 }
4833
4834 IWL_DEBUG_SCAN("total channels to scan %d \n", added);
4835 return added;
4836}
4837
bb8c093b 4838static void iwl3945_init_hw_rates(struct iwl3945_priv *priv,
b481de9c
ZY		 4839 struct ieee80211_rate *rates)
4840{
4841 int i;
4842
4843 for (i = 0; i < IWL_RATE_COUNT; i++) {
8318d78a
JB		 4844 rates[i].bitrate = iwl3945_rates[i].ieee * 5;
4845 rates[i].hw_value = i; /* Rate scaling will work on indexes */
4846 rates[i].hw_value_short = i;
4847 rates[i].flags = 0;
4848 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
b481de9c 4849 /*
8318d78a 4850 * If CCK != 1M then set short preamble rate flag.
b481de9c 4851 */
bb8c093b 4852 rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
8318d78a 4853 0 : IEEE80211_RATE_SHORT_PREAMBLE;
b481de9c 4854 }
b481de9c
ZY		 4855 }
4856}
4857
4858/**
bb8c093b 4859 * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
b481de9c 4860 */
bb8c093b 4861static int iwl3945_init_geos(struct iwl3945_priv *priv)
b481de9c 4862{
bb8c093b 4863 struct iwl3945_channel_info *ch;
8211ef78 4864 struct ieee80211_supported_band *sband;
b481de9c
ZY		 4865 struct ieee80211_channel *channels;
4866 struct ieee80211_channel *geo_ch;
4867 struct ieee80211_rate *rates;
4868 int i = 0;
b481de9c 4869
8318d78a
JB		 4870 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
4871 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
b481de9c
ZY		 4872 IWL_DEBUG_INFO("Geography modes already initialized.\n");
4873 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
4874 return 0;
4875 }
4876
b481de9c
ZY		 4877 channels = kzalloc(sizeof(struct ieee80211_channel) *
4878 priv->channel_count, GFP_KERNEL);
8318d78a 4879 if (!channels)
b481de9c 4880 return -ENOMEM;
b481de9c 4881
8211ef78 4882 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
b481de9c
ZY		 4883 GFP_KERNEL);
4884 if (!rates) {
b481de9c
ZY		 4885 kfree(channels);
4886 return -ENOMEM;
4887 }
4888
b481de9c 4889 /* 5.2GHz channels start after the 2.4GHz channels */
8211ef78
TW		 4890 sband = &priv->bands[IEEE80211_BAND_5GHZ];
4891 sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
4892 /* just OFDM */
4893 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
4894 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
4895
4896 sband = &priv->bands[IEEE80211_BAND_2GHZ];
4897 sband->channels = channels;
4898 /* OFDM & CCK */
4899 sband->bitrates = rates;
4900 sband->n_bitrates = IWL_RATE_COUNT;
b481de9c
ZY		 4901
4902 priv->ieee_channels = channels;
4903 priv->ieee_rates = rates;
4904
bb8c093b 4905 iwl3945_init_hw_rates(priv, rates);
b481de9c 4906
8211ef78 4907 for (i = 0; i < priv->channel_count; i++) {
b481de9c
ZY		 4908 ch = &priv->channel_info[i];
4909
8211ef78
TW		 4910 /* FIXME: might be removed if scan is OK*/
4911 if (!is_channel_valid(ch))
b481de9c 4912 continue;
b481de9c
ZY		 4913
4914 if (is_channel_a_band(ch))
8211ef78 4915 sband = &priv->bands[IEEE80211_BAND_5GHZ];
8318d78a 4916 else
8211ef78 4917 sband = &priv->bands[IEEE80211_BAND_2GHZ];
b481de9c 4918
8211ef78
TW		 4919 geo_ch = &sband->channels[sband->n_channels++];
4920
4921 geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
8318d78a
JB		 4922 geo_ch->max_power = ch->max_power_avg;
4923 geo_ch->max_antenna_gain = 0xff;
7b72304d 4924 geo_ch->hw_value = ch->channel;
b481de9c
ZY		 4925
4926 if (is_channel_valid(ch)) {
8318d78a
JB		 4927 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
4928 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
b481de9c 4929
8318d78a
JB		 4930 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
4931 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
b481de9c
ZY		 4932
4933 if (ch->flags & EEPROM_CHANNEL_RADAR)
8318d78a 4934 geo_ch->flags |= IEEE80211_CHAN_RADAR;
b481de9c
ZY		 4935
4936 if (ch->max_power_avg > priv->max_channel_txpower_limit)
4937 priv->max_channel_txpower_limit =
4938 ch->max_power_avg;
8211ef78 4939 } else {
8318d78a 4940 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
8211ef78
TW		 4941 }
4942
4943 /* Save flags for reg domain usage */
4944 geo_ch->orig_flags = geo_ch->flags;
4945
4946 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
4947 ch->channel, geo_ch->center_freq,
4948 is_channel_a_band(ch) ? "5.2" : "2.4",
4949 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
4950 "restricted" : "valid",
4951 geo_ch->flags);
b481de9c
ZY		 4952 }
4953
82b9a121
TW		 4954 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
4955 priv->cfg->sku & IWL_SKU_A) {
b481de9c
ZY		 4956 printk(KERN_INFO DRV_NAME
4957 ": Incorrectly detected BG card as ABG. Please send "
4958 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
4959 priv->pci_dev->device, priv->pci_dev->subsystem_device);
82b9a121 4960 priv->cfg->sku &= ~IWL_SKU_A;
b481de9c
ZY		 4961 }
4962
4963 printk(KERN_INFO DRV_NAME
4964 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
8318d78a
JB		 4965 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
4966 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
b481de9c 4967
e0e0a67e
JL		 4968 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
4969 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
4970 &priv->bands[IEEE80211_BAND_2GHZ];
4971 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
4972 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
4973 &priv->bands[IEEE80211_BAND_5GHZ];
b481de9c 4974
b481de9c
ZY		 4975 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
4976
4977 return 0;
4978}
4979
849e0dce
RC		 4980/*
4981 * iwl3945_free_geos - undo allocations in iwl3945_init_geos
4982 */
4983static void iwl3945_free_geos(struct iwl3945_priv *priv)
4984{
849e0dce
RC		 4985 kfree(priv->ieee_channels);
4986 kfree(priv->ieee_rates);
4987 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
4988}
4989
b481de9c
ZY		 4990/******************************************************************************
4991 *
4992 * uCode download functions
4993 *
4994 ******************************************************************************/
4995
bb8c093b 4996static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv)
b481de9c 4997{
98c92211
TW		 4998 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
4999 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
5000 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
5001 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
5002 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
5003 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY		 5004}
5005
5006/**
bb8c093b 5007 * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
b481de9c
ZY		 5008 * looking at all data.
5009 */
3ac7f146 5010static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 *image, u32 len)
b481de9c
ZY		 5011{
5012 u32 val;
5013 u32 save_len = len;
5014 int rc = 0;
5015 u32 errcnt;
5016
5017 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5018
bb8c093b 5019 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5020 if (rc)
5021 return rc;
5022
bb8c093b 5023 iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
b481de9c
ZY		 5024
5025 errcnt = 0;
5026 for (; len > 0; len -= sizeof(u32), image++) {
5027 /* read data comes through single port, auto-incr addr */
5028 /* NOTE: Use the debugless read so we don't flood kernel log
5029 * if IWL_DL_IO is set */
bb8c093b 5030 val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY		 5031 if (val != le32_to_cpu(*image)) {
5032 IWL_ERROR("uCode INST section is invalid at "
5033 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5034 save_len - len, val, le32_to_cpu(*image));
5035 rc = -EIO;
5036 errcnt++;
5037 if (errcnt >= 20)
5038 break;
5039 }
5040 }
5041
bb8c093b 5042 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5043
5044 if (!errcnt)
bc434dd2 5045 IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
b481de9c
ZY		 5046
5047 return rc;
5048}
5049
5050
5051/**
bb8c093b 5052 * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
b481de9c
ZY		 5053 * using sample data 100 bytes apart. If these sample points are good,
5054 * it's a pretty good bet that everything between them is good, too.
5055 */
bb8c093b 5056static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len)
b481de9c
ZY		 5057{
5058 u32 val;
5059 int rc = 0;
5060 u32 errcnt = 0;
5061 u32 i;
5062
5063 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5064
bb8c093b 5065 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5066 if (rc)
5067 return rc;
5068
5069 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
5070 /* read data comes through single port, auto-incr addr */
5071 /* NOTE: Use the debugless read so we don't flood kernel log
5072 * if IWL_DL_IO is set */
bb8c093b 5073 iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
b481de9c 5074 i + RTC_INST_LOWER_BOUND);
bb8c093b 5075 val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY		 5076 if (val != le32_to_cpu(*image)) {
5077#if 0 /* Enable this if you want to see details */
5078 IWL_ERROR("uCode INST section is invalid at "
5079 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5080 i, val, *image);
5081#endif
5082 rc = -EIO;
5083 errcnt++;
5084 if (errcnt >= 3)
5085 break;
5086 }
5087 }
5088
bb8c093b 5089 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5090
5091 return rc;
5092}
5093
5094
5095/**
bb8c093b 5096 * iwl3945_verify_ucode - determine which instruction image is in SRAM,
b481de9c
ZY		 5097 * and verify its contents
5098 */
bb8c093b 5099static int iwl3945_verify_ucode(struct iwl3945_priv *priv)
b481de9c
ZY		 5100{
5101 __le32 *image;
5102 u32 len;
5103 int rc = 0;
5104
5105 /* Try bootstrap */
5106 image = (__le32 *)priv->ucode_boot.v_addr;
5107 len = priv->ucode_boot.len;
bb8c093b 5108 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5109 if (rc == 0) {
5110 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
5111 return 0;
5112 }
5113
5114 /* Try initialize */
5115 image = (__le32 *)priv->ucode_init.v_addr;
5116 len = priv->ucode_init.len;
bb8c093b 5117 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5118 if (rc == 0) {
5119 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
5120 return 0;
5121 }
5122
5123 /* Try runtime/protocol */
5124 image = (__le32 *)priv->ucode_code.v_addr;
5125 len = priv->ucode_code.len;
bb8c093b 5126 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5127 if (rc == 0) {
5128 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
5129 return 0;
5130 }
5131
5132 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
5133
9fbab516
BC		 5134 /* Since nothing seems to match, show first several data entries in
5135 * instruction SRAM, so maybe visual inspection will give a clue.
5136 * Selection of bootstrap image (vs. other images) is arbitrary. */
b481de9c
ZY		 5137 image = (__le32 *)priv->ucode_boot.v_addr;
5138 len = priv->ucode_boot.len;
bb8c093b 5139 rc = iwl3945_verify_inst_full(priv, image, len);
b481de9c
ZY		 5140
5141 return rc;
5142}
5143
5144
5145/* check contents of special bootstrap uCode SRAM */
bb8c093b 5146static int iwl3945_verify_bsm(struct iwl3945_priv *priv)
b481de9c
ZY		 5147{
5148 __le32 *image = priv->ucode_boot.v_addr;
5149 u32 len = priv->ucode_boot.len;
5150 u32 reg;
5151 u32 val;
5152
5153 IWL_DEBUG_INFO("Begin verify bsm\n");
5154
5155 /* verify BSM SRAM contents */
bb8c093b 5156 val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG);
b481de9c
ZY		 5157 for (reg = BSM_SRAM_LOWER_BOUND;
5158 reg < BSM_SRAM_LOWER_BOUND + len;
3ac7f146 5159 reg += sizeof(u32), image++) {
bb8c093b 5160 val = iwl3945_read_prph(priv, reg);
b481de9c
ZY		 5161 if (val != le32_to_cpu(*image)) {
5162 IWL_ERROR("BSM uCode verification failed at "
5163 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
5164 BSM_SRAM_LOWER_BOUND,
5165 reg - BSM_SRAM_LOWER_BOUND, len,
5166 val, le32_to_cpu(*image));
5167 return -EIO;
5168 }
5169 }
5170
5171 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
5172
5173 return 0;
5174}
5175
5176/**
bb8c093b 5177 * iwl3945_load_bsm - Load bootstrap instructions
b481de9c
ZY		 5178 *
5179 * BSM operation:
5180 *
5181 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
5182 * in special SRAM that does not power down during RFKILL. When powering back
5183 * up after power-saving sleeps (or during initial uCode load), the BSM loads
5184 * the bootstrap program into the on-board processor, and starts it.
5185 *
5186 * The bootstrap program loads (via DMA) instructions and data for a new
5187 * program from host DRAM locations indicated by the host driver in the
5188 * BSM_DRAM_* registers. Once the new program is loaded, it starts
5189 * automatically.
5190 *
5191 * When initializing the NIC, the host driver points the BSM to the
5192 * "initialize" uCode image. This uCode sets up some internal data, then
5193 * notifies host via "initialize alive" that it is complete.
5194 *
5195 * The host then replaces the BSM_DRAM_* pointer values to point to the
5196 * normal runtime uCode instructions and a backup uCode data cache buffer
5197 * (filled initially with starting data values for the on-board processor),
5198 * then triggers the "initialize" uCode to load and launch the runtime uCode,
5199 * which begins normal operation.
5200 *
5201 * When doing a power-save shutdown, runtime uCode saves data SRAM into
5202 * the backup data cache in DRAM before SRAM is powered down.
5203 *
5204 * When powering back up, the BSM loads the bootstrap program. This reloads
5205 * the runtime uCode instructions and the backup data cache into SRAM,
5206 * and re-launches the runtime uCode from where it left off.
5207 */
bb8c093b 5208static int iwl3945_load_bsm(struct iwl3945_priv *priv)
b481de9c
ZY		 5209{
5210 __le32 *image = priv->ucode_boot.v_addr;
5211 u32 len = priv->ucode_boot.len;
5212 dma_addr_t pinst;
5213 dma_addr_t pdata;
5214 u32 inst_len;
5215 u32 data_len;
5216 int rc;
5217 int i;
5218 u32 done;
5219 u32 reg_offset;
5220
5221 IWL_DEBUG_INFO("Begin load bsm\n");
5222
5223 /* make sure bootstrap program is no larger than BSM's SRAM size */
5224 if (len > IWL_MAX_BSM_SIZE)
5225 return -EINVAL;
5226
5227 /* Tell bootstrap uCode where to find the "Initialize" uCode
9fbab516 5228 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
bb8c093b 5229 * NOTE: iwl3945_initialize_alive_start() will replace these values,
b481de9c
ZY		 5230 * after the "initialize" uCode has run, to point to
5231 * runtime/protocol instructions and backup data cache. */
5232 pinst = priv->ucode_init.p_addr;
5233 pdata = priv->ucode_init_data.p_addr;
5234 inst_len = priv->ucode_init.len;
5235 data_len = priv->ucode_init_data.len;
5236
bb8c093b 5237 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5238 if (rc)
5239 return rc;
5240
bb8c093b
CH		 5241 iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5242 iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5243 iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
5244 iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
b481de9c
ZY		 5245
5246 /* Fill BSM memory with bootstrap instructions */
5247 for (reg_offset = BSM_SRAM_LOWER_BOUND;
5248 reg_offset < BSM_SRAM_LOWER_BOUND + len;
5249 reg_offset += sizeof(u32), image++)
bb8c093b 5250 _iwl3945_write_prph(priv, reg_offset,
b481de9c
ZY		 5251 le32_to_cpu(*image));
5252
bb8c093b 5253 rc = iwl3945_verify_bsm(priv);
b481de9c 5254 if (rc) {
bb8c093b 5255 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5256 return rc;
5257 }
5258
5259 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
bb8c093b
CH		 5260 iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
5261 iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG,
b481de9c 5262 RTC_INST_LOWER_BOUND);
bb8c093b 5263 iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
b481de9c
ZY		 5264
5265 /* Load bootstrap code into instruction SRAM now,
5266 * to prepare to load "initialize" uCode */
bb8c093b 5267 iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY		 5268 BSM_WR_CTRL_REG_BIT_START);
5269
5270 /* Wait for load of bootstrap uCode to finish */
5271 for (i = 0; i < 100; i++) {
bb8c093b 5272 done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG);
b481de9c
ZY		 5273 if (!(done & BSM_WR_CTRL_REG_BIT_START))
5274 break;
5275 udelay(10);
5276 }
5277 if (i < 100)
5278 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
5279 else {
5280 IWL_ERROR("BSM write did not complete!\n");
5281 return -EIO;
5282 }
5283
5284 /* Enable future boot loads whenever power management unit triggers it
5285 * (e.g. when powering back up after power-save shutdown) */
bb8c093b 5286 iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY		 5287 BSM_WR_CTRL_REG_BIT_START_EN);
5288
bb8c093b 5289 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5290
5291 return 0;
5292}
5293
bb8c093b 5294static void iwl3945_nic_start(struct iwl3945_priv *priv)
b481de9c
ZY		 5295{
5296 /* Remove all resets to allow NIC to operate */
bb8c093b 5297 iwl3945_write32(priv, CSR_RESET, 0);
b481de9c
ZY		 5298}
5299
5300/**
bb8c093b 5301 * iwl3945_read_ucode - Read uCode images from disk file.
b481de9c
ZY		 5302 *
5303 * Copy into buffers for card to fetch via bus-mastering
5304 */
bb8c093b 5305static int iwl3945_read_ucode(struct iwl3945_priv *priv)
b481de9c 5306{
bb8c093b 5307 struct iwl3945_ucode *ucode;
a0987a8d 5308 int ret = -EINVAL, index;
b481de9c
ZY		 5309 const struct firmware *ucode_raw;
5310 /* firmware file name contains uCode/driver compatibility version */
a0987a8d
RC		 5311 const char *name_pre = priv->cfg->fw_name_pre;
5312 const unsigned int api_max = priv->cfg->ucode_api_max;
5313 const unsigned int api_min = priv->cfg->ucode_api_min;
5314 char buf[25];
b481de9c
ZY		 5315 u8 *src;
5316 size_t len;
a0987a8d 5317 u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
b481de9c
ZY		 5318
5319 /* Ask kernel firmware_class module to get the boot firmware off disk.
5320 * request_firmware() is synchronous, file is in memory on return. */
a0987a8d
RC		 5321 for (index = api_max; index >= api_min; index--) {
5322 sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
5323 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
5324 if (ret < 0) {
5325 IWL_ERROR("%s firmware file req failed: Reason %d\n",
5326 buf, ret);
5327 if (ret == -ENOENT)
5328 continue;
5329 else
5330 goto error;
5331 } else {
5332 if (index < api_max)
5333 IWL_ERROR("Loaded firmware %s, which is deprecated. Please use API v%u instead.\n",
5334 buf, api_max);
5335 IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
5336 buf, ucode_raw->size);
5337 break;
5338 }
b481de9c
ZY		 5339 }
5340
a0987a8d
RC		 5341 if (ret < 0)
5342 goto error;
b481de9c
ZY		 5343
5344 /* Make sure that we got at least our header! */
5345 if (ucode_raw->size < sizeof(*ucode)) {
5346 IWL_ERROR("File size way too small!\n");
90e759d1 5347 ret = -EINVAL;
b481de9c
ZY		 5348 goto err_release;
5349 }
5350
5351 /* Data from ucode file: header followed by uCode images */
5352 ucode = (void *)ucode_raw->data;
5353
c02b3acd 5354 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 5355 api_ver = IWL_UCODE_API(priv->ucode_ver);
b481de9c
ZY		 5356 inst_size = le32_to_cpu(ucode->inst_size);
5357 data_size = le32_to_cpu(ucode->data_size);
5358 init_size = le32_to_cpu(ucode->init_size);
5359 init_data_size = le32_to_cpu(ucode->init_data_size);
5360 boot_size = le32_to_cpu(ucode->boot_size);
5361
a0987a8d
RC		 5362 /* api_ver should match the api version forming part of the
5363 * firmware filename ... but we don't check for that and only rely
5364 * on the API version read from firware header from here on forward */
5365
5366 if (api_ver < api_min || api_ver > api_max) {
5367 IWL_ERROR("Driver unable to support your firmware API. "
5368 "Driver supports v%u, firmware is v%u.\n",
5369 api_max, api_ver);
5370 priv->ucode_ver = 0;
5371 ret = -EINVAL;
5372 goto err_release;
5373 }
5374 if (api_ver != api_max)
5375 IWL_ERROR("Firmware has old API version. Expected %u, "
5376 "got %u. New firmware can be obtained "
5377 "from http://www.intellinuxwireless.org.\n",
5378 api_max, api_ver);
5379
5380 printk(KERN_INFO DRV_NAME " loaded firmware version %u.%u.%u.%u\n",
c02b3acd
CR		 5381 IWL_UCODE_MAJOR(priv->ucode_ver),
5382 IWL_UCODE_MINOR(priv->ucode_ver),
5383 IWL_UCODE_API(priv->ucode_ver),
5384 IWL_UCODE_SERIAL(priv->ucode_ver));
a0987a8d
RC		 5385 IWL_DEBUG_INFO("f/w package hdr ucode version raw = 0x%x\n",
5386 priv->ucode_ver);
bc434dd2
IS		 5387 IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
5388 IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
5389 IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
5390 IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
5391 IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
b481de9c 5392
a0987a8d 5393
b481de9c
ZY		 5394 /* Verify size of file vs. image size info in file's header */
5395 if (ucode_raw->size < sizeof(*ucode) +
5396 inst_size + data_size + init_size +
5397 init_data_size + boot_size) {
5398
5399 IWL_DEBUG_INFO("uCode file size %d too small\n",
5400 (int)ucode_raw->size);
90e759d1 5401 ret = -EINVAL;
b481de9c
ZY		 5402 goto err_release;
5403 }
5404
5405 /* Verify that uCode images will fit in card's SRAM */
5406 if (inst_size > IWL_MAX_INST_SIZE) {
90e759d1
TW		 5407 IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
5408 inst_size);
5409 ret = -EINVAL;
b481de9c
ZY		 5410 goto err_release;
5411 }
5412
5413 if (data_size > IWL_MAX_DATA_SIZE) {
90e759d1
TW		 5414 IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
5415 data_size);
5416 ret = -EINVAL;
b481de9c
ZY		 5417 goto err_release;
5418 }
5419 if (init_size > IWL_MAX_INST_SIZE) {
90e759d1
TW		 5420 IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
5421 init_size);
5422 ret = -EINVAL;
b481de9c
ZY		 5423 goto err_release;
5424 }
5425 if (init_data_size > IWL_MAX_DATA_SIZE) {
90e759d1
TW		 5426 IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
5427 init_data_size);
5428 ret = -EINVAL;
b481de9c
ZY		 5429 goto err_release;
5430 }
5431 if (boot_size > IWL_MAX_BSM_SIZE) {
90e759d1
TW		 5432 IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
5433 boot_size);
5434 ret = -EINVAL;
b481de9c
ZY		 5435 goto err_release;
5436 }
5437
5438 /* Allocate ucode buffers for card's bus-master loading ... */
5439
5440 /* Runtime instructions and 2 copies of data:
5441 * 1) unmodified from disk
5442 * 2) backup cache for save/restore during power-downs */
5443 priv->ucode_code.len = inst_size;
98c92211 5444 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY		 5445
5446 priv->ucode_data.len = data_size;
98c92211 5447 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY		 5448
5449 priv->ucode_data_backup.len = data_size;
98c92211 5450 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 5451
90e759d1
TW		 5452 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
5453 !priv->ucode_data_backup.v_addr)
5454 goto err_pci_alloc;
b481de9c
ZY		 5455
5456 /* Initialization instructions and data */
90e759d1
TW		 5457 if (init_size && init_data_size) {
5458 priv->ucode_init.len = init_size;
98c92211 5459 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW		 5460
5461 priv->ucode_init_data.len = init_data_size;
98c92211 5462 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW		 5463
5464 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
5465 goto err_pci_alloc;
5466 }
b481de9c
ZY		 5467
5468 /* Bootstrap (instructions only, no data) */
90e759d1
TW		 5469 if (boot_size) {
5470 priv->ucode_boot.len = boot_size;
98c92211 5471 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 5472
90e759d1
TW		 5473 if (!priv->ucode_boot.v_addr)
5474 goto err_pci_alloc;
5475 }
b481de9c
ZY		 5476
5477 /* Copy images into buffers for card's bus-master reads ... */
5478
5479 /* Runtime instructions (first block of data in file) */
5480 src = &ucode->data[0];
5481 len = priv->ucode_code.len;
90e759d1 5482 IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c
ZY		 5483 memcpy(priv->ucode_code.v_addr, src, len);
5484 IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
5485 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
5486
5487 /* Runtime data (2nd block)
bb8c093b 5488 * NOTE: Copy into backup buffer will be done in iwl3945_up() */
b481de9c
ZY		 5489 src = &ucode->data[inst_size];
5490 len = priv->ucode_data.len;
90e759d1 5491 IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY		 5492 memcpy(priv->ucode_data.v_addr, src, len);
5493 memcpy(priv->ucode_data_backup.v_addr, src, len);
5494
5495 /* Initialization instructions (3rd block) */
5496 if (init_size) {
5497 src = &ucode->data[inst_size + data_size];
5498 len = priv->ucode_init.len;
90e759d1
TW		 5499 IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
5500 len);
b481de9c
ZY		 5501 memcpy(priv->ucode_init.v_addr, src, len);
5502 }
5503
5504 /* Initialization data (4th block) */
5505 if (init_data_size) {
5506 src = &ucode->data[inst_size + data_size + init_size];
5507 len = priv->ucode_init_data.len;
5508 IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
5509 (int)len);
5510 memcpy(priv->ucode_init_data.v_addr, src, len);
5511 }
5512
5513 /* Bootstrap instructions (5th block) */
5514 src = &ucode->data[inst_size + data_size + init_size + init_data_size];
5515 len = priv->ucode_boot.len;
5516 IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
5517 (int)len);
5518 memcpy(priv->ucode_boot.v_addr, src, len);
5519
5520 /* We have our copies now, allow OS release its copies */
5521 release_firmware(ucode_raw);
5522 return 0;
5523
5524 err_pci_alloc:
5525 IWL_ERROR("failed to allocate pci memory\n");
90e759d1 5526 ret = -ENOMEM;
bb8c093b 5527 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY		 5528
5529 err_release:
5530 release_firmware(ucode_raw);
5531
5532 error:
90e759d1 5533 return ret;
b481de9c
ZY		 5534}
5535
5536
5537/**
bb8c093b 5538 * iwl3945_set_ucode_ptrs - Set uCode address location
b481de9c
ZY		 5539 *
5540 * Tell initialization uCode where to find runtime uCode.
5541 *
5542 * BSM registers initially contain pointers to initialization uCode.
5543 * We need to replace them to load runtime uCode inst and data,
5544 * and to save runtime data when powering down.
5545 */
bb8c093b 5546static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv)
b481de9c
ZY		 5547{
5548 dma_addr_t pinst;
5549 dma_addr_t pdata;
5550 int rc = 0;
5551 unsigned long flags;
5552
5553 /* bits 31:0 for 3945 */
5554 pinst = priv->ucode_code.p_addr;
5555 pdata = priv->ucode_data_backup.p_addr;
5556
5557 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5558 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5559 if (rc) {
5560 spin_unlock_irqrestore(&priv->lock, flags);
5561 return rc;
5562 }
5563
5564 /* Tell bootstrap uCode where to find image to load */
bb8c093b
CH		 5565 iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5566 iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5567 iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
b481de9c
ZY		 5568 priv->ucode_data.len);
5569
a96a27f9 5570 /* Inst byte count must be last to set up, bit 31 signals uCode
b481de9c 5571 * that all new ptr/size info is in place */
bb8c093b 5572 iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
b481de9c
ZY		 5573 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
5574
bb8c093b 5575 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5576
5577 spin_unlock_irqrestore(&priv->lock, flags);
5578
5579 IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
5580
5581 return rc;
5582}
5583
5584/**
bb8c093b 5585 * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
b481de9c
ZY		 5586 *
5587 * Called after REPLY_ALIVE notification received from "initialize" uCode.
5588 *
b481de9c 5589 * Tell "initialize" uCode to go ahead and load the runtime uCode.
9fbab516 5590 */
bb8c093b 5591static void iwl3945_init_alive_start(struct iwl3945_priv *priv)
b481de9c
ZY		 5592{
5593 /* Check alive response for "valid" sign from uCode */
5594 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
5595 /* We had an error bringing up the hardware, so take it
5596 * all the way back down so we can try again */
5597 IWL_DEBUG_INFO("Initialize Alive failed.\n");
5598 goto restart;
5599 }
5600
5601 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
5602 * This is a paranoid check, because we would not have gotten the
5603 * "initialize" alive if code weren't properly loaded. */
bb8c093b 5604 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY		 5605 /* Runtime instruction load was bad;
5606 * take it all the way back down so we can try again */
5607 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
5608 goto restart;
5609 }
5610
5611 /* Send pointers to protocol/runtime uCode image ... init code will
5612 * load and launch runtime uCode, which will send us another "Alive"
5613 * notification. */
5614 IWL_DEBUG_INFO("Initialization Alive received.\n");
bb8c093b 5615 if (iwl3945_set_ucode_ptrs(priv)) {
b481de9c
ZY		 5616 /* Runtime instruction load won't happen;
5617 * take it all the way back down so we can try again */
5618 IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
5619 goto restart;
5620 }
5621 return;
5622
5623 restart:
5624 queue_work(priv->workqueue, &priv->restart);
5625}
5626
5627
9bdf5eca
MA		 5628/* temporary */
5629static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw,
5630 struct sk_buff *skb);
5631
b481de9c 5632/**
bb8c093b 5633 * iwl3945_alive_start - called after REPLY_ALIVE notification received
b481de9c 5634 * from protocol/runtime uCode (initialization uCode's
bb8c093b 5635 * Alive gets handled by iwl3945_init_alive_start()).
b481de9c 5636 */
bb8c093b 5637static void iwl3945_alive_start(struct iwl3945_priv *priv)
b481de9c
ZY		 5638{
5639 int rc = 0;
5640 int thermal_spin = 0;
5641 u32 rfkill;
5642
5643 IWL_DEBUG_INFO("Runtime Alive received.\n");
5644
5645 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
5646 /* We had an error bringing up the hardware, so take it
5647 * all the way back down so we can try again */
5648 IWL_DEBUG_INFO("Alive failed.\n");
5649 goto restart;
5650 }
5651
5652 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
5653 * This is a paranoid check, because we would not have gotten the
5654 * "runtime" alive if code weren't properly loaded. */
bb8c093b 5655 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY		 5656 /* Runtime instruction load was bad;
5657 * take it all the way back down so we can try again */
5658 IWL_DEBUG_INFO("Bad runtime uCode load.\n");
5659 goto restart;
5660 }
5661
bb8c093b 5662 iwl3945_clear_stations_table(priv);
b481de9c 5663
bb8c093b 5664 rc = iwl3945_grab_nic_access(priv);
b481de9c 5665 if (rc) {
a96a27f9 5666 IWL_WARNING("Can not read RFKILL status from adapter\n");
b481de9c
ZY		 5667 return;
5668 }
5669
bb8c093b 5670 rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG);
b481de9c 5671 IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
bb8c093b 5672 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5673
5674 if (rfkill & 0x1) {
5675 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a96a27f9 5676 /* if RFKILL is not on, then wait for thermal
b481de9c 5677 * sensor in adapter to kick in */
bb8c093b 5678 while (iwl3945_hw_get_temperature(priv) == 0) {
b481de9c
ZY		 5679 thermal_spin++;
5680 udelay(10);
5681 }
5682
5683 if (thermal_spin)
5684 IWL_DEBUG_INFO("Thermal calibration took %dus\n",
5685 thermal_spin * 10);
5686 } else
5687 set_bit(STATUS_RF_KILL_HW, &priv->status);
5688
9fbab516 5689 /* After the ALIVE response, we can send commands to 3945 uCode */
b481de9c
ZY		 5690 set_bit(STATUS_ALIVE, &priv->status);
5691
5692 /* Clear out the uCode error bit if it is set */
5693 clear_bit(STATUS_FW_ERROR, &priv->status);
5694
bb8c093b 5695 if (iwl3945_is_rfkill(priv))
b481de9c
ZY		 5696 return;
5697
36d6825b 5698 ieee80211_wake_queues(priv->hw);
b481de9c
ZY		 5699
5700 priv->active_rate = priv->rates_mask;
5701 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
5702
bb8c093b 5703 iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
b481de9c 5704
bb8c093b
CH		 5705 if (iwl3945_is_associated(priv)) {
5706 struct iwl3945_rxon_cmd *active_rxon =
5707 (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
b481de9c
ZY		 5708
5709 memcpy(&priv->staging_rxon, &priv->active_rxon,
5710 sizeof(priv->staging_rxon));
5711 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5712 } else {
5713 /* Initialize our rx_config data */
60294de3 5714 iwl3945_connection_init_rx_config(priv, priv->iw_mode);
b481de9c
ZY		 5715 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
5716 }
5717
9fbab516 5718 /* Configure Bluetooth device coexistence support */
bb8c093b 5719 iwl3945_send_bt_config(priv);
b481de9c
ZY		 5720
5721 /* Configure the adapter for unassociated operation */
bb8c093b 5722 iwl3945_commit_rxon(priv);
b481de9c 5723
b481de9c
ZY		 5724 iwl3945_reg_txpower_periodic(priv);
5725
fe00b5a5
RC		 5726 iwl3945_led_register(priv);
5727
b481de9c 5728 IWL_DEBUG_INFO("ALIVE processing complete.\n");
a9f46786 5729 set_bit(STATUS_READY, &priv->status);
5a66926a 5730 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY		 5731
5732 if (priv->error_recovering)
bb8c093b 5733 iwl3945_error_recovery(priv);
b481de9c 5734
9bdf5eca
MA		 5735 /* reassociate for ADHOC mode */
5736 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
5737 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
5738 priv->vif);
5739 if (beacon)
5740 iwl3945_mac_beacon_update(priv->hw, beacon);
5741 }
5742
b481de9c
ZY		 5743 return;
5744
5745 restart:
5746 queue_work(priv->workqueue, &priv->restart);
5747}
5748
bb8c093b 5749static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv);
b481de9c 5750
bb8c093b 5751static void __iwl3945_down(struct iwl3945_priv *priv)
b481de9c
ZY		 5752{
5753 unsigned long flags;
5754 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
5755 struct ieee80211_conf *conf = NULL;
5756
5757 IWL_DEBUG_INFO(DRV_NAME " is going down\n");
5758
5759 conf = ieee80211_get_hw_conf(priv->hw);
5760
5761 if (!exit_pending)
5762 set_bit(STATUS_EXIT_PENDING, &priv->status);
5763
ab53d8af 5764 iwl3945_led_unregister(priv);
bb8c093b 5765 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 5766
5767 /* Unblock any waiting calls */
5768 wake_up_interruptible_all(&priv->wait_command_queue);
5769
b481de9c
ZY		 5770 /* Wipe out the EXIT_PENDING status bit if we are not actually
5771 * exiting the module */
5772 if (!exit_pending)
5773 clear_bit(STATUS_EXIT_PENDING, &priv->status);
5774
5775 /* stop and reset the on-board processor */
bb8c093b 5776 iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY		 5777
5778 /* tell the device to stop sending interrupts */
0359facc 5779 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5780 iwl3945_disable_interrupts(priv);
0359facc
MA		 5781 spin_unlock_irqrestore(&priv->lock, flags);
5782 iwl_synchronize_irq(priv);
b481de9c
ZY		 5783
5784 if (priv->mac80211_registered)
5785 ieee80211_stop_queues(priv->hw);
5786
bb8c093b 5787 /* If we have not previously called iwl3945_init() then
b481de9c 5788 * clear all bits but the RF Kill and SUSPEND bits and return */
bb8c093b 5789 if (!iwl3945_is_init(priv)) {
b481de9c
ZY		 5790 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
5791 STATUS_RF_KILL_HW |
5792 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
5793 STATUS_RF_KILL_SW |
9788864e
RC		 5794 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
5795 STATUS_GEO_CONFIGURED |
b481de9c 5796 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
ebef2008
AK		 5797 STATUS_IN_SUSPEND |
5798 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
5799 STATUS_EXIT_PENDING;
b481de9c
ZY		 5800 goto exit;
5801 }
5802
5803 /* ...otherwise clear out all the status bits but the RF Kill and
5804 * SUSPEND bits and continue taking the NIC down. */
5805 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
5806 STATUS_RF_KILL_HW |
5807 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
5808 STATUS_RF_KILL_SW |
9788864e
RC		 5809 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
5810 STATUS_GEO_CONFIGURED |
b481de9c
ZY		 5811 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
5812 STATUS_IN_SUSPEND |
5813 test_bit(STATUS_FW_ERROR, &priv->status) <<
ebef2008
AK		 5814 STATUS_FW_ERROR |
5815 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
5816 STATUS_EXIT_PENDING;
b481de9c
ZY		 5817
5818 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5819 iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY		 5820 spin_unlock_irqrestore(&priv->lock, flags);
5821
bb8c093b
CH		 5822 iwl3945_hw_txq_ctx_stop(priv);
5823 iwl3945_hw_rxq_stop(priv);
b481de9c
ZY		 5824
5825 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH		 5826 if (!iwl3945_grab_nic_access(priv)) {
5827 iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
b481de9c 5828 APMG_CLK_VAL_DMA_CLK_RQT);
bb8c093b 5829 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5830 }
5831 spin_unlock_irqrestore(&priv->lock, flags);
5832
5833 udelay(5);
5834
bb8c093b
CH		 5835 iwl3945_hw_nic_stop_master(priv);
5836 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
5837 iwl3945_hw_nic_reset(priv);
b481de9c
ZY		 5838
5839 exit:
bb8c093b 5840 memset(&priv->card_alive, 0, sizeof(struct iwl3945_alive_resp));
b481de9c
ZY		 5841
5842 if (priv->ibss_beacon)
5843 dev_kfree_skb(priv->ibss_beacon);
5844 priv->ibss_beacon = NULL;
5845
5846 /* clear out any free frames */
bb8c093b 5847 iwl3945_clear_free_frames(priv);
b481de9c
ZY		 5848}
5849
bb8c093b 5850static void iwl3945_down(struct iwl3945_priv *priv)
b481de9c
ZY		 5851{
5852 mutex_lock(&priv->mutex);
bb8c093b 5853 __iwl3945_down(priv);
b481de9c 5854 mutex_unlock(&priv->mutex);
b24d22b1 5855
bb8c093b 5856 iwl3945_cancel_deferred_work(priv);
b481de9c
ZY		 5857}
5858
5859#define MAX_HW_RESTARTS 5
5860
bb8c093b 5861static int __iwl3945_up(struct iwl3945_priv *priv)
b481de9c
ZY		 5862{
5863 int rc, i;
5864
5865 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
5866 IWL_WARNING("Exit pending; will not bring the NIC up\n");
5867 return -EIO;
5868 }
5869
5870 if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
5871 IWL_WARNING("Radio disabled by SW RF kill (module "
5872 "parameter)\n");
e655b9f0
ZY		 5873 return -ENODEV;
5874 }
5875
e903fbd4 5876 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
a96a27f9 5877 IWL_ERROR("ucode not available for device bring up\n");
e903fbd4
RC		 5878 return -EIO;
5879 }
5880
e655b9f0
ZY		 5881 /* If platform's RF_KILL switch is NOT set to KILL */
5882 if (iwl3945_read32(priv, CSR_GP_CNTRL) &
5883 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
5884 clear_bit(STATUS_RF_KILL_HW, &priv->status);
5885 else {
5886 set_bit(STATUS_RF_KILL_HW, &priv->status);
5887 if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
5888 IWL_WARNING("Radio disabled by HW RF Kill switch\n");
5889 return -ENODEV;
5890 }
b481de9c 5891 }
80fcc9e2 5892
bb8c093b 5893 iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 5894
bb8c093b 5895 rc = iwl3945_hw_nic_init(priv);
b481de9c
ZY		 5896 if (rc) {
5897 IWL_ERROR("Unable to int nic\n");
5898 return rc;
5899 }
5900
5901 /* make sure rfkill handshake bits are cleared */
bb8c093b
CH		 5902 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5903 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 5904 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
5905
5906 /* clear (again), then enable host interrupts */
bb8c093b
CH		 5907 iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
5908 iwl3945_enable_interrupts(priv);
b481de9c
ZY		 5909
5910 /* really make sure rfkill handshake bits are cleared */
bb8c093b
CH		 5911 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5912 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 5913
5914 /* Copy original ucode data image from disk into backup cache.
5915 * This will be used to initialize the on-board processor's
5916 * data SRAM for a clean start when the runtime program first loads. */
5917 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 5918 priv->ucode_data.len);
b481de9c 5919
e655b9f0
ZY		 5920 /* We return success when we resume from suspend and rf_kill is on. */
5921 if (test_bit(STATUS_RF_KILL_HW, &priv->status))
5922 return 0;
5923
b481de9c
ZY		 5924 for (i = 0; i < MAX_HW_RESTARTS; i++) {
5925
bb8c093b 5926 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 5927
5928 /* load bootstrap state machine,
5929 * load bootstrap program into processor's memory,
5930 * prepare to load the "initialize" uCode */
bb8c093b 5931 rc = iwl3945_load_bsm(priv);
b481de9c
ZY		 5932
5933 if (rc) {
5934 IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
5935 continue;
5936 }
5937
5938 /* start card; "initialize" will load runtime ucode */
bb8c093b 5939 iwl3945_nic_start(priv);
b481de9c 5940
b481de9c
ZY		 5941 IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
5942
5943 return 0;
5944 }
5945
5946 set_bit(STATUS_EXIT_PENDING, &priv->status);
bb8c093b 5947 __iwl3945_down(priv);
ebef2008 5948 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY		 5949
5950 /* tried to restart and config the device for as long as our
5951 * patience could withstand */
5952 IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
5953 return -EIO;
5954}
5955
5956
5957/*****************************************************************************
5958 *
5959 * Workqueue callbacks
5960 *
5961 *****************************************************************************/
5962
bb8c093b 5963static void iwl3945_bg_init_alive_start(struct work_struct *data)
b481de9c 5964{
bb8c093b
CH		 5965 struct iwl3945_priv *priv =
5966 container_of(data, struct iwl3945_priv, init_alive_start.work);
b481de9c
ZY		 5967
5968 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5969 return;
5970
5971 mutex_lock(&priv->mutex);
bb8c093b 5972 iwl3945_init_alive_start(priv);
b481de9c
ZY		 5973 mutex_unlock(&priv->mutex);
5974}
5975
bb8c093b 5976static void iwl3945_bg_alive_start(struct work_struct *data)
b481de9c 5977{
bb8c093b
CH		 5978 struct iwl3945_priv *priv =
5979 container_of(data, struct iwl3945_priv, alive_start.work);
b481de9c
ZY		 5980
5981 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5982 return;
5983
5984 mutex_lock(&priv->mutex);
bb8c093b 5985 iwl3945_alive_start(priv);
b481de9c
ZY		 5986 mutex_unlock(&priv->mutex);
5987}
5988
bb8c093b 5989static void iwl3945_bg_rf_kill(struct work_struct *work)
b481de9c 5990{
bb8c093b 5991 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill);
b481de9c
ZY		 5992
5993 wake_up_interruptible(&priv->wait_command_queue);
5994
5995 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5996 return;
5997
5998 mutex_lock(&priv->mutex);
5999
bb8c093b 6000 if (!iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 6001 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
6002 "HW and/or SW RF Kill no longer active, restarting "
6003 "device\n");
6004 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
6005 queue_work(priv->workqueue, &priv->restart);
6006 } else {
6007
6008 if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
6009 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
6010 "disabled by SW switch\n");
6011 else
6012 IWL_WARNING("Radio Frequency Kill Switch is On:\n"
6013 "Kill switch must be turned off for "
6014 "wireless networking to work.\n");
6015 }
ebef2008 6016
b481de9c 6017 mutex_unlock(&priv->mutex);
80fcc9e2 6018 iwl3945_rfkill_set_hw_state(priv);
b481de9c
ZY		 6019}
6020
6021#define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
6022
bb8c093b 6023static void iwl3945_bg_scan_check(struct work_struct *data)
b481de9c 6024{
bb8c093b
CH		 6025 struct iwl3945_priv *priv =
6026 container_of(data, struct iwl3945_priv, scan_check.work);
b481de9c
ZY		 6027
6028 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6029 return;
6030
6031 mutex_lock(&priv->mutex);
6032 if (test_bit(STATUS_SCANNING, &priv->status) ||
6033 test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6034 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
6035 "Scan completion watchdog resetting adapter (%dms)\n",
6036 jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
15e869d8 6037
b481de9c 6038 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
bb8c093b 6039 iwl3945_send_scan_abort(priv);
b481de9c
ZY		 6040 }
6041 mutex_unlock(&priv->mutex);
6042}
6043
bb8c093b 6044static void iwl3945_bg_request_scan(struct work_struct *data)
b481de9c 6045{
bb8c093b
CH		 6046 struct iwl3945_priv *priv =
6047 container_of(data, struct iwl3945_priv, request_scan);
6048 struct iwl3945_host_cmd cmd = {
b481de9c 6049 .id = REPLY_SCAN_CMD,
bb8c093b 6050 .len = sizeof(struct iwl3945_scan_cmd),
b481de9c
ZY		 6051 .meta.flags = CMD_SIZE_HUGE,
6052 };
6053 int rc = 0;
bb8c093b 6054 struct iwl3945_scan_cmd *scan;
b481de9c 6055 struct ieee80211_conf *conf = NULL;
f9340520 6056 u8 n_probes = 2;
8318d78a 6057 enum ieee80211_band band;
9387b7ca 6058 DECLARE_SSID_BUF(ssid);
b481de9c
ZY		 6059
6060 conf = ieee80211_get_hw_conf(priv->hw);
6061
6062 mutex_lock(&priv->mutex);
6063
bb8c093b 6064 if (!iwl3945_is_ready(priv)) {
b481de9c
ZY		 6065 IWL_WARNING("request scan called when driver not ready.\n");
6066 goto done;
6067 }
6068
a96a27f9 6069 /* Make sure the scan wasn't canceled before this queued work
b481de9c
ZY		 6070 * was given the chance to run... */
6071 if (!test_bit(STATUS_SCANNING, &priv->status))
6072 goto done;
6073
6074 /* This should never be called or scheduled if there is currently
6075 * a scan active in the hardware. */
6076 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
6077 IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
6078 "Ignoring second request.\n");
6079 rc = -EIO;
6080 goto done;
6081 }
6082
6083 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
6084 IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
6085 goto done;
6086 }
6087
6088 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6089 IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
6090 goto done;
6091 }
6092
bb8c093b 6093 if (iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 6094 IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
6095 goto done;
6096 }
6097
6098 if (!test_bit(STATUS_READY, &priv->status)) {
6099 IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
6100 goto done;
6101 }
6102
6103 if (!priv->scan_bands) {
6104 IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
6105 goto done;
6106 }
6107
6108 if (!priv->scan) {
bb8c093b 6109 priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
b481de9c
ZY		 6110 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
6111 if (!priv->scan) {
6112 rc = -ENOMEM;
6113 goto done;
6114 }
6115 }
6116 scan = priv->scan;
bb8c093b 6117 memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
b481de9c
ZY		 6118
6119 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
6120 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
6121
bb8c093b 6122 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 6123 u16 interval = 0;
6124 u32 extra;
6125 u32 suspend_time = 100;
6126 u32 scan_suspend_time = 100;
6127 unsigned long flags;
6128
6129 IWL_DEBUG_INFO("Scanning while associated...\n");
6130
6131 spin_lock_irqsave(&priv->lock, flags);
6132 interval = priv->beacon_int;
6133 spin_unlock_irqrestore(&priv->lock, flags);
6134
6135 scan->suspend_time = 0;
15e869d8 6136 scan->max_out_time = cpu_to_le32(200 * 1024);
b481de9c
ZY		 6137 if (!interval)
6138 interval = suspend_time;
6139 /*
6140 * suspend time format:
6141 * 0-19: beacon interval in usec (time before exec.)
6142 * 20-23: 0
6143 * 24-31: number of beacons (suspend between channels)
6144 */
6145
6146 extra = (suspend_time / interval) << 24;
6147 scan_suspend_time = 0xFF0FFFFF &
6148 (extra | ((suspend_time % interval) * 1024));
6149
6150 scan->suspend_time = cpu_to_le32(scan_suspend_time);
6151 IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
6152 scan_suspend_time, interval);
6153 }
6154
6155 /* We should add the ability for user to lock to PASSIVE ONLY */
6156 if (priv->one_direct_scan) {
6157 IWL_DEBUG_SCAN
6158 ("Kicking off one direct scan for '%s'\n",
9387b7ca
JL		 6159 print_ssid(ssid, priv->direct_ssid,
6160 priv->direct_ssid_len));
b481de9c
ZY		 6161 scan->direct_scan[0].id = WLAN_EID_SSID;
6162 scan->direct_scan[0].len = priv->direct_ssid_len;
6163 memcpy(scan->direct_scan[0].ssid,
6164 priv->direct_ssid, priv->direct_ssid_len);
f9340520 6165 n_probes++;
f9340520 6166 } else
786b4557 6167 IWL_DEBUG_SCAN("Kicking off one indirect scan.\n");
b481de9c
ZY		 6168
6169 /* We don't build a direct scan probe request; the uCode will do
6170 * that based on the direct_mask added to each channel entry */
6171 scan->tx_cmd.len = cpu_to_le16(
bb8c093b 6172 iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
430cfe95 6173 IWL_MAX_SCAN_SIZE - sizeof(*scan)));
b481de9c
ZY		 6174 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
6175 scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
6176 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
6177
6178 /* flags + rate selection */
6179
66b5004d 6180 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
b481de9c
ZY		 6181 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
6182 scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
6183 scan->good_CRC_th = 0;
8318d78a 6184 band = IEEE80211_BAND_2GHZ;
66b5004d 6185 } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
b481de9c
ZY		 6186 scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
6187 scan->good_CRC_th = IWL_GOOD_CRC_TH;
8318d78a 6188 band = IEEE80211_BAND_5GHZ;
66b5004d 6189 } else {
b481de9c
ZY		 6190 IWL_WARNING("Invalid scan band count\n");
6191 goto done;
6192 }
6193
6194 /* select Rx antennas */
6195 scan->flags |= iwl3945_get_antenna_flags(priv);
6196
05c914fe 6197 if (priv->iw_mode == NL80211_IFTYPE_MONITOR)
b481de9c
ZY		 6198 scan->filter_flags = RXON_FILTER_PROMISC_MSK;
6199
f9340520
AK		 6200 scan->channel_count =
6201 iwl3945_get_channels_for_scan(priv, band, 1, /* active */
6202 n_probes,
6203 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
b481de9c 6204
14b54336
RC		 6205 if (scan->channel_count == 0) {
6206 IWL_DEBUG_SCAN("channel count %d\n", scan->channel_count);
6207 goto done;
6208 }
6209
b481de9c 6210 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
bb8c093b 6211 scan->channel_count * sizeof(struct iwl3945_scan_channel);
b481de9c
ZY		 6212 cmd.data = scan;
6213 scan->len = cpu_to_le16(cmd.len);
6214
6215 set_bit(STATUS_SCAN_HW, &priv->status);
bb8c093b 6216 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 6217 if (rc)
6218 goto done;
6219
6220 queue_delayed_work(priv->workqueue, &priv->scan_check,
6221 IWL_SCAN_CHECK_WATCHDOG);
6222
6223 mutex_unlock(&priv->mutex);
6224 return;
6225
6226 done:
2420ebc1
MA		 6227 /* can not perform scan make sure we clear scanning
6228 * bits from status so next scan request can be performed.
6229 * if we dont clear scanning status bit here all next scan
6230 * will fail
6231 */
6232 clear_bit(STATUS_SCAN_HW, &priv->status);
6233 clear_bit(STATUS_SCANNING, &priv->status);
6234
01ebd063 6235 /* inform mac80211 scan aborted */
b481de9c
ZY		 6236 queue_work(priv->workqueue, &priv->scan_completed);
6237 mutex_unlock(&priv->mutex);
6238}
6239
bb8c093b 6240static void iwl3945_bg_up(struct work_struct *data)
b481de9c 6241{
bb8c093b 6242 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up);
b481de9c
ZY		 6243
6244 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6245 return;
6246
6247 mutex_lock(&priv->mutex);
bb8c093b 6248 __iwl3945_up(priv);
b481de9c 6249 mutex_unlock(&priv->mutex);
80fcc9e2 6250 iwl3945_rfkill_set_hw_state(priv);
b481de9c
ZY		 6251}
6252
bb8c093b 6253static void iwl3945_bg_restart(struct work_struct *data)
b481de9c 6254{
bb8c093b 6255 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart);
b481de9c
ZY		 6256
6257 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6258 return;
6259
bb8c093b 6260 iwl3945_down(priv);
b481de9c
ZY		 6261 queue_work(priv->workqueue, &priv->up);
6262}
6263
bb8c093b 6264static void iwl3945_bg_rx_replenish(struct work_struct *data)
b481de9c 6265{
bb8c093b
CH		 6266 struct iwl3945_priv *priv =
6267 container_of(data, struct iwl3945_priv, rx_replenish);
b481de9c
ZY		 6268
6269 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6270 return;
6271
6272 mutex_lock(&priv->mutex);
bb8c093b 6273 iwl3945_rx_replenish(priv);
b481de9c
ZY		 6274 mutex_unlock(&priv->mutex);
6275}
6276
7878a5a4
MA		 6277#define IWL_DELAY_NEXT_SCAN (HZ*2)
6278
cd56d331 6279static void iwl3945_post_associate(struct iwl3945_priv *priv)
b481de9c 6280{
b481de9c
ZY		 6281 int rc = 0;
6282 struct ieee80211_conf *conf = NULL;
6283
05c914fe 6284 if (priv->iw_mode == NL80211_IFTYPE_AP) {
3ac7f146 6285 IWL_ERROR("%s Should not be called in AP mode\n", __func__);
b481de9c
ZY		 6286 return;
6287 }
6288
6289
e174961c
JB		 6290 IWL_DEBUG_ASSOC("Associated as %d to: %pM\n",
6291 priv->assoc_id, priv->active_rxon.bssid_addr);
b481de9c
ZY		 6292
6293 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6294 return;
6295
322a9811 6296 if (!priv->vif || !priv->is_open)
6ef89d0a 6297 return;
322a9811 6298
bb8c093b 6299 iwl3945_scan_cancel_timeout(priv, 200);
15e869d8 6300
b481de9c
ZY		 6301 conf = ieee80211_get_hw_conf(priv->hw);
6302
6303 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6304 iwl3945_commit_rxon(priv);
b481de9c 6305
bb8c093b
CH		 6306 memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
6307 iwl3945_setup_rxon_timing(priv);
6308 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY		 6309 sizeof(priv->rxon_timing), &priv->rxon_timing);
6310 if (rc)
6311 IWL_WARNING("REPLY_RXON_TIMING failed - "
6312 "Attempting to continue.\n");
6313
6314 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
6315
6316 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
6317
6318 IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
6319 priv->assoc_id, priv->beacon_int);
6320
6321 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
6322 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
6323 else
6324 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
6325
6326 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
6327 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
6328 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
6329 else
6330 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
6331
05c914fe 6332 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY		 6333 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
6334
6335 }
6336
bb8c093b 6337 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6338
6339 switch (priv->iw_mode) {
05c914fe 6340 case NL80211_IFTYPE_STATION:
bb8c093b 6341 iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
b481de9c
ZY		 6342 break;
6343
05c914fe 6344 case NL80211_IFTYPE_ADHOC:
b481de9c 6345
ce546fd2 6346 priv->assoc_id = 1;
bb8c093b 6347 iwl3945_add_station(priv, priv->bssid, 0, 0);
b481de9c 6348 iwl3945_sync_sta(priv, IWL_STA_ID,
8318d78a 6349 (priv->band == IEEE80211_BAND_5GHZ) ?
b481de9c
ZY		 6350 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
6351 CMD_ASYNC);
bb8c093b
CH		 6352 iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
6353 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 6354
6355 break;
6356
6357 default:
6358 IWL_ERROR("%s Should not be called in %d mode\n",
3ac7f146 6359 __func__, priv->iw_mode);
b481de9c
ZY		 6360 break;
6361 }
6362
bb8c093b 6363 iwl3945_activate_qos(priv, 0);
292ae174 6364
7878a5a4
MA		 6365 /* we have just associated, don't start scan too early */
6366 priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
cd56d331
AK		 6367}
6368
bb8c093b 6369static void iwl3945_bg_abort_scan(struct work_struct *work)
b481de9c 6370{
bb8c093b 6371 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan);
b481de9c 6372
bb8c093b 6373 if (!iwl3945_is_ready(priv))
b481de9c
ZY		 6374 return;
6375
6376 mutex_lock(&priv->mutex);
6377
6378 set_bit(STATUS_SCAN_ABORTING, &priv->status);
bb8c093b 6379 iwl3945_send_scan_abort(priv);
b481de9c
ZY		 6380
6381 mutex_unlock(&priv->mutex);
6382}
6383
e8975581 6384static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed);
76bb77e0 6385
bb8c093b 6386static void iwl3945_bg_scan_completed(struct work_struct *work)
b481de9c 6387{
bb8c093b
CH		 6388 struct iwl3945_priv *priv =
6389 container_of(work, struct iwl3945_priv, scan_completed);
b481de9c
ZY		 6390
6391 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
6392
6393 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6394 return;
6395
a0646470 6396 if (test_bit(STATUS_CONF_PENDING, &priv->status))
e8975581 6397 iwl3945_mac_config(priv->hw, 0);
76bb77e0 6398
b481de9c
ZY		 6399 ieee80211_scan_completed(priv->hw);
6400
6401 /* Since setting the TXPOWER may have been deferred while
6402 * performing the scan, fire one off */
6403 mutex_lock(&priv->mutex);
bb8c093b 6404 iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 6405 mutex_unlock(&priv->mutex);
6406}
6407
6408/*****************************************************************************
6409 *
6410 * mac80211 entry point functions
6411 *
6412 *****************************************************************************/
6413
5a66926a
ZY		 6414#define UCODE_READY_TIMEOUT (2 * HZ)
6415
bb8c093b 6416static int iwl3945_mac_start(struct ieee80211_hw *hw)
b481de9c 6417{
bb8c093b 6418 struct iwl3945_priv *priv = hw->priv;
5a66926a 6419 int ret;
b481de9c
ZY		 6420
6421 IWL_DEBUG_MAC80211("enter\n");
6422
5a66926a
ZY		 6423 if (pci_enable_device(priv->pci_dev)) {
6424 IWL_ERROR("Fail to pci_enable_device\n");
6425 return -ENODEV;
6426 }
6427 pci_restore_state(priv->pci_dev);
6428 pci_enable_msi(priv->pci_dev);
6429
6430 ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
6431 DRV_NAME, priv);
6432 if (ret) {
6433 IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq);
6434 goto out_disable_msi;
6435 }
6436
b481de9c
ZY		 6437 /* we should be verifying the device is ready to be opened */
6438 mutex_lock(&priv->mutex);
6439
5a66926a
ZY		 6440 memset(&priv->staging_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
6441 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
6442 * ucode filename and max sizes are card-specific. */
6443
6444 if (!priv->ucode_code.len) {
6445 ret = iwl3945_read_ucode(priv);
6446 if (ret) {
6447 IWL_ERROR("Could not read microcode: %d\n", ret);
6448 mutex_unlock(&priv->mutex);
6449 goto out_release_irq;
6450 }
6451 }
b481de9c 6452
e655b9f0 6453 ret = __iwl3945_up(priv);
b481de9c
ZY		 6454
6455 mutex_unlock(&priv->mutex);
5a66926a 6456
80fcc9e2
AG		 6457 iwl3945_rfkill_set_hw_state(priv);
6458
e655b9f0
ZY		 6459 if (ret)
6460 goto out_release_irq;
6461
6462 IWL_DEBUG_INFO("Start UP work.\n");
6463
6464 if (test_bit(STATUS_IN_SUSPEND, &priv->status))
6465 return 0;
6466
5a66926a
ZY		 6467 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
6468 * mac80211 will not be run successfully. */
6469 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
6470 test_bit(STATUS_READY, &priv->status),
6471 UCODE_READY_TIMEOUT);
6472 if (!ret) {
6473 if (!test_bit(STATUS_READY, &priv->status)) {
6474 IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n",
6475 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6476 ret = -ETIMEDOUT;
6477 goto out_release_irq;
6478 }
6479 }
6480
e655b9f0 6481 priv->is_open = 1;
b481de9c
ZY		 6482 IWL_DEBUG_MAC80211("leave\n");
6483 return 0;
5a66926a
ZY		 6484
6485out_release_irq:
6486 free_irq(priv->pci_dev->irq, priv);
6487out_disable_msi:
6488 pci_disable_msi(priv->pci_dev);
e655b9f0
ZY		 6489 pci_disable_device(priv->pci_dev);
6490 priv->is_open = 0;
6491 IWL_DEBUG_MAC80211("leave - failed\n");
5a66926a 6492 return ret;
b481de9c
ZY		 6493}
6494
bb8c093b 6495static void iwl3945_mac_stop(struct ieee80211_hw *hw)
b481de9c 6496{
bb8c093b 6497 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6498
6499 IWL_DEBUG_MAC80211("enter\n");
6ef89d0a 6500
e655b9f0
ZY		 6501 if (!priv->is_open) {
6502 IWL_DEBUG_MAC80211("leave - skip\n");
6503 return;
6504 }
6505
b481de9c 6506 priv->is_open = 0;
5a66926a
ZY		 6507
6508 if (iwl3945_is_ready_rf(priv)) {
e655b9f0
ZY		 6509 /* stop mac, cancel any scan request and clear
6510 * RXON_FILTER_ASSOC_MSK BIT
6511 */
5a66926a
ZY		 6512 mutex_lock(&priv->mutex);
6513 iwl3945_scan_cancel_timeout(priv, 100);
fde3571f 6514 mutex_unlock(&priv->mutex);
fde3571f
MA		 6515 }
6516
5a66926a
ZY		 6517 iwl3945_down(priv);
6518
6519 flush_workqueue(priv->workqueue);
6520 free_irq(priv->pci_dev->irq, priv);
6521 pci_disable_msi(priv->pci_dev);
6522 pci_save_state(priv->pci_dev);
6523 pci_disable_device(priv->pci_dev);
6ef89d0a 6524
b481de9c 6525 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 6526}
6527
e039fa4a 6528static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 6529{
bb8c093b 6530 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6531
6532 IWL_DEBUG_MAC80211("enter\n");
6533
b481de9c 6534 IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 6535 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 6536
e039fa4a 6537 if (iwl3945_tx_skb(priv, skb))
b481de9c
ZY		 6538 dev_kfree_skb_any(skb);
6539
6540 IWL_DEBUG_MAC80211("leave\n");
637f8837 6541 return NETDEV_TX_OK;
b481de9c
ZY		 6542}
6543
bb8c093b 6544static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
b481de9c
ZY		 6545 struct ieee80211_if_init_conf *conf)
6546{
bb8c093b 6547 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6548 unsigned long flags;
6549
32bfd35d 6550 IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
b481de9c 6551
32bfd35d
JB		 6552 if (priv->vif) {
6553 IWL_DEBUG_MAC80211("leave - vif != NULL\n");
864792e3 6554 return -EOPNOTSUPP;
b481de9c
ZY		 6555 }
6556
6557 spin_lock_irqsave(&priv->lock, flags);
32bfd35d 6558 priv->vif = conf->vif;
60294de3 6559 priv->iw_mode = conf->type;
b481de9c
ZY		 6560
6561 spin_unlock_irqrestore(&priv->lock, flags);
6562
6563 mutex_lock(&priv->mutex);
864792e3
TW		 6564
6565 if (conf->mac_addr) {
e174961c 6566 IWL_DEBUG_MAC80211("Set: %pM\n", conf->mac_addr);
864792e3
TW		 6567 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
6568 }
6569
5a66926a
ZY		 6570 if (iwl3945_is_ready(priv))
6571 iwl3945_set_mode(priv, conf->type);
b481de9c 6572
b481de9c
ZY		 6573 mutex_unlock(&priv->mutex);
6574
5a66926a 6575 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 6576 return 0;
6577}
6578
6579/**
bb8c093b 6580 * iwl3945_mac_config - mac80211 config callback
b481de9c
ZY		 6581 *
6582 * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
6583 * be set inappropriately and the driver currently sets the hardware up to
6584 * use it whenever needed.
6585 */
e8975581 6586static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed)
b481de9c 6587{
bb8c093b
CH		 6588 struct iwl3945_priv *priv = hw->priv;
6589 const struct iwl3945_channel_info *ch_info;
e8975581 6590 struct ieee80211_conf *conf = &hw->conf;
b481de9c 6591 unsigned long flags;
76bb77e0 6592 int ret = 0;
b481de9c
ZY		 6593
6594 mutex_lock(&priv->mutex);
8318d78a 6595 IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
b481de9c 6596
bb8c093b 6597 if (!iwl3945_is_ready(priv)) {
b481de9c 6598 IWL_DEBUG_MAC80211("leave - not ready\n");
76bb77e0
ZY		 6599 ret = -EIO;
6600 goto out;
b481de9c
ZY		 6601 }
6602
bb8c093b 6603 if (unlikely(!iwl3945_param_disable_hw_scan &&
b481de9c 6604 test_bit(STATUS_SCANNING, &priv->status))) {
a0646470
ZY		 6605 IWL_DEBUG_MAC80211("leave - scanning\n");
6606 set_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 6607 mutex_unlock(&priv->mutex);
a0646470 6608 return 0;
b481de9c
ZY		 6609 }
6610
6611 spin_lock_irqsave(&priv->lock, flags);
6612
8318d78a
JB		 6613 ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
6614 conf->channel->hw_value);
b481de9c 6615 if (!is_channel_valid(ch_info)) {
66b5004d 6616 IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this band.\n",
8318d78a 6617 conf->channel->hw_value, conf->channel->band);
b481de9c
ZY		 6618 IWL_DEBUG_MAC80211("leave - invalid channel\n");
6619 spin_unlock_irqrestore(&priv->lock, flags);
76bb77e0
ZY		 6620 ret = -EINVAL;
6621 goto out;
b481de9c
ZY		 6622 }
6623
8318d78a 6624 iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
b481de9c 6625
8318d78a 6626 iwl3945_set_flags_for_phymode(priv, conf->channel->band);
b481de9c
ZY		 6627
6628 /* The list of supported rates and rate mask can be different
6629 * for each phymode; since the phymode may have changed, reset
6630 * the rate mask to what mac80211 lists */
bb8c093b 6631 iwl3945_set_rate(priv);
b481de9c
ZY		 6632
6633 spin_unlock_irqrestore(&priv->lock, flags);
6634
6635#ifdef IEEE80211_CONF_CHANNEL_SWITCH
6636 if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
bb8c093b 6637 iwl3945_hw_channel_switch(priv, conf->channel);
76bb77e0 6638 goto out;
b481de9c
ZY		 6639 }
6640#endif
6641
bb8c093b 6642 iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
b481de9c
ZY		 6643
6644 if (!conf->radio_enabled) {
6645 IWL_DEBUG_MAC80211("leave - radio disabled\n");
76bb77e0 6646 goto out;
b481de9c
ZY		 6647 }
6648
bb8c093b 6649 if (iwl3945_is_rfkill(priv)) {
b481de9c 6650 IWL_DEBUG_MAC80211("leave - RF kill\n");
76bb77e0
ZY		 6651 ret = -EIO;
6652 goto out;
b481de9c
ZY		 6653 }
6654
bb8c093b 6655 iwl3945_set_rate(priv);
b481de9c
ZY		 6656
6657 if (memcmp(&priv->active_rxon,
6658 &priv->staging_rxon, sizeof(priv->staging_rxon)))
bb8c093b 6659 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6660 else
6661 IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
6662
6663 IWL_DEBUG_MAC80211("leave\n");
6664
76bb77e0 6665out:
a0646470 6666 clear_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 6667 mutex_unlock(&priv->mutex);
76bb77e0 6668 return ret;
b481de9c
ZY		 6669}
6670
bb8c093b 6671static void iwl3945_config_ap(struct iwl3945_priv *priv)
b481de9c
ZY		 6672{
6673 int rc = 0;
6674
d986bcd1 6675 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY		 6676 return;
6677
6678 /* The following should be done only at AP bring up */
5d1e2325 6679 if (!(iwl3945_is_associated(priv))) {
b481de9c
ZY		 6680
6681 /* RXON - unassoc (to set timing command) */
6682 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6683 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6684
6685 /* RXON Timing */
bb8c093b
CH		 6686 memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
6687 iwl3945_setup_rxon_timing(priv);
6688 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY		 6689 sizeof(priv->rxon_timing), &priv->rxon_timing);
6690 if (rc)
6691 IWL_WARNING("REPLY_RXON_TIMING failed - "
6692 "Attempting to continue.\n");
6693
6694 /* FIXME: what should be the assoc_id for AP? */
6695 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
6696 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
6697 priv->staging_rxon.flags |=
6698 RXON_FLG_SHORT_PREAMBLE_MSK;
6699 else
6700 priv->staging_rxon.flags &=
6701 ~RXON_FLG_SHORT_PREAMBLE_MSK;
6702
6703 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
6704 if (priv->assoc_capability &
6705 WLAN_CAPABILITY_SHORT_SLOT_TIME)
6706 priv->staging_rxon.flags |=
6707 RXON_FLG_SHORT_SLOT_MSK;
6708 else
6709 priv->staging_rxon.flags &=
6710 ~RXON_FLG_SHORT_SLOT_MSK;
6711
05c914fe 6712 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY		 6713 priv->staging_rxon.flags &=
6714 ~RXON_FLG_SHORT_SLOT_MSK;
6715 }
6716 /* restore RXON assoc */
6717 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
bb8c093b
CH		 6718 iwl3945_commit_rxon(priv);
6719 iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
556f8db7 6720 }
bb8c093b 6721 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 6722
6723 /* FIXME - we need to add code here to detect a totally new
6724 * configuration, reset the AP, unassoc, rxon timing, assoc,
6725 * clear sta table, add BCAST sta... */
6726}
6727
32bfd35d
JB		 6728static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
6729 struct ieee80211_vif *vif,
b481de9c
ZY		 6730 struct ieee80211_if_conf *conf)
6731{
bb8c093b 6732 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6733 int rc;
6734
6735 if (conf == NULL)
6736 return -EIO;
6737
b716bb91
EG		 6738 if (priv->vif != vif) {
6739 IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
b716bb91
EG		 6740 return 0;
6741 }
6742
9d139c81 6743 /* handle this temporarily here */
05c914fe 6744 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
9d139c81
JB		 6745 conf->changed & IEEE80211_IFCC_BEACON) {
6746 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
6747 if (!beacon)
6748 return -ENOMEM;
9bdf5eca 6749 mutex_lock(&priv->mutex);
9d139c81 6750 rc = iwl3945_mac_beacon_update(hw, beacon);
9bdf5eca 6751 mutex_unlock(&priv->mutex);
9d139c81
JB		 6752 if (rc)
6753 return rc;
6754 }
6755
5a66926a
ZY		 6756 if (!iwl3945_is_alive(priv))
6757 return -EAGAIN;
6758
b481de9c
ZY		 6759 mutex_lock(&priv->mutex);
6760
b481de9c 6761 if (conf->bssid)
e174961c 6762 IWL_DEBUG_MAC80211("bssid: %pM\n", conf->bssid);
b481de9c 6763
4150c572
JB		 6764/*
6765 * very dubious code was here; the probe filtering flag is never set:
6766 *
b481de9c
ZY		 6767 if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
6768 !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
4150c572 6769 */
b481de9c 6770
05c914fe 6771 if (priv->iw_mode == NL80211_IFTYPE_AP) {
b481de9c
ZY		 6772 if (!conf->bssid) {
6773 conf->bssid = priv->mac_addr;
6774 memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
e174961c
JB		 6775 IWL_DEBUG_MAC80211("bssid was set to: %pM\n",
6776 conf->bssid);
b481de9c
ZY		 6777 }
6778 if (priv->ibss_beacon)
6779 dev_kfree_skb(priv->ibss_beacon);
6780
9d139c81 6781 priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
b481de9c
ZY		 6782 }
6783
fde3571f
MA		 6784 if (iwl3945_is_rfkill(priv))
6785 goto done;
6786
b481de9c
ZY		 6787 if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
6788 !is_multicast_ether_addr(conf->bssid)) {
6789 /* If there is currently a HW scan going on in the background
6790 * then we need to cancel it else the RXON below will fail. */
bb8c093b 6791 if (iwl3945_scan_cancel_timeout(priv, 100)) {
b481de9c
ZY		 6792 IWL_WARNING("Aborted scan still in progress "
6793 "after 100ms\n");
6794 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
6795 mutex_unlock(&priv->mutex);
6796 return -EAGAIN;
6797 }
6798 memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
6799
6800 /* TODO: Audit driver for usage of these members and see
6801 * if mac80211 deprecates them (priv->bssid looks like it
6802 * shouldn't be there, but I haven't scanned the IBSS code
6803 * to verify) - jpk */
6804 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
6805
05c914fe 6806 if (priv->iw_mode == NL80211_IFTYPE_AP)
bb8c093b 6807 iwl3945_config_ap(priv);
b481de9c 6808 else {
bb8c093b 6809 rc = iwl3945_commit_rxon(priv);
05c914fe 6810 if ((priv->iw_mode == NL80211_IFTYPE_STATION) && rc)
bb8c093b 6811 iwl3945_add_station(priv,
556f8db7 6812 priv->active_rxon.bssid_addr, 1, 0);
b481de9c
ZY		 6813 }
6814
6815 } else {
bb8c093b 6816 iwl3945_scan_cancel_timeout(priv, 100);
b481de9c 6817 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6818 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6819 }
6820
fde3571f 6821 done:
b481de9c
ZY		 6822 IWL_DEBUG_MAC80211("leave\n");
6823 mutex_unlock(&priv->mutex);
6824
6825 return 0;
6826}
6827
bb8c093b 6828static void iwl3945_configure_filter(struct ieee80211_hw *hw,
4150c572
JB		 6829 unsigned int changed_flags,
6830 unsigned int *total_flags,
6831 int mc_count, struct dev_addr_list *mc_list)
6832{
5ec03976 6833 struct iwl3945_priv *priv = hw->priv;
352bc8de 6834 __le32 *filter_flags = &priv->staging_rxon.filter_flags;
25b3f57c 6835
352bc8de
ZY		 6836 IWL_DEBUG_MAC80211("Enter: changed: 0x%x, total: 0x%x\n",
6837 changed_flags, *total_flags);
6838
6839 if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
6840 if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
6841 *filter_flags |= RXON_FILTER_PROMISC_MSK;
6842 else
6843 *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
6844 }
6845 if (changed_flags & FIF_ALLMULTI) {
6846 if (*total_flags & FIF_ALLMULTI)
6847 *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
6848 else
6849 *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
6850 }
6851 if (changed_flags & FIF_CONTROL) {
6852 if (*total_flags & FIF_CONTROL)
6853 *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
6854 else
6855 *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
5ec03976 6856 }
352bc8de
ZY		 6857 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
6858 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
6859 *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
6860 else
6861 *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
6862 }
6863
6864 /* We avoid iwl_commit_rxon here to commit the new filter flags
6865 * since mac80211 will call ieee80211_hw_config immediately.
6866 * (mc_list is not supported at this time). Otherwise, we need to
6867 * queue a background iwl_commit_rxon work.
6868 */
6869
6870 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
25b3f57c 6871 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
4150c572
JB		 6872}
6873
bb8c093b 6874static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
b481de9c
ZY		 6875 struct ieee80211_if_init_conf *conf)
6876{
bb8c093b 6877 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6878
6879 IWL_DEBUG_MAC80211("enter\n");
6880
6881 mutex_lock(&priv->mutex);
6ef89d0a 6882
fde3571f
MA		 6883 if (iwl3945_is_ready_rf(priv)) {
6884 iwl3945_scan_cancel_timeout(priv, 100);
fde3571f
MA		 6885 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
6886 iwl3945_commit_rxon(priv);
6887 }
32bfd35d
JB		 6888 if (priv->vif == conf->vif) {
6889 priv->vif = NULL;
b481de9c 6890 memset(priv->bssid, 0, ETH_ALEN);
b481de9c
ZY		 6891 }
6892 mutex_unlock(&priv->mutex);
6893
6894 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 6895}
6896
cd56d331
AK		 6897#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
6898
6899static void iwl3945_bss_info_changed(struct ieee80211_hw *hw,
6900 struct ieee80211_vif *vif,
6901 struct ieee80211_bss_conf *bss_conf,
6902 u32 changes)
6903{
6904 struct iwl3945_priv *priv = hw->priv;
6905
6906 IWL_DEBUG_MAC80211("changes = 0x%X\n", changes);
6907
6908 if (changes & BSS_CHANGED_ERP_PREAMBLE) {
6909 IWL_DEBUG_MAC80211("ERP_PREAMBLE %d\n",
6910 bss_conf->use_short_preamble);
6911 if (bss_conf->use_short_preamble)
6912 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
6913 else
6914 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
6915 }
6916
6917 if (changes & BSS_CHANGED_ERP_CTS_PROT) {
6918 IWL_DEBUG_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
6919 if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
6920 priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
6921 else
6922 priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
6923 }
6924
6925 if (changes & BSS_CHANGED_ASSOC) {
6926 IWL_DEBUG_MAC80211("ASSOC %d\n", bss_conf->assoc);
6927 /* This should never happen as this function should
6928 * never be called from interrupt context. */
6929 if (WARN_ON_ONCE(in_interrupt()))
6930 return;
6931 if (bss_conf->assoc) {
6932 priv->assoc_id = bss_conf->aid;
6933 priv->beacon_int = bss_conf->beacon_int;
6934 priv->timestamp0 = bss_conf->timestamp & 0xFFFFFFFF;
6935 priv->timestamp1 = (bss_conf->timestamp >> 32) &
6936 0xFFFFFFFF;
6937 priv->assoc_capability = bss_conf->assoc_capability;
6938 priv->next_scan_jiffies = jiffies +
6939 IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
6940 mutex_lock(&priv->mutex);
6941 iwl3945_post_associate(priv);
6942 mutex_unlock(&priv->mutex);
6943 } else {
6944 priv->assoc_id = 0;
6945 IWL_DEBUG_MAC80211("DISASSOC %d\n", bss_conf->assoc);
6946 }
6947 } else if (changes && iwl3945_is_associated(priv) && priv->assoc_id) {
6948 IWL_DEBUG_MAC80211("Associated Changes %d\n", changes);
6949 iwl3945_send_rxon_assoc(priv);
6950 }
6951
6952}
6953
bb8c093b 6954static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
b481de9c
ZY		 6955{
6956 int rc = 0;
6957 unsigned long flags;
bb8c093b 6958 struct iwl3945_priv *priv = hw->priv;
9387b7ca 6959 DECLARE_SSID_BUF(ssid_buf);
b481de9c
ZY		 6960
6961 IWL_DEBUG_MAC80211("enter\n");
6962
15e869d8 6963 mutex_lock(&priv->mutex);
b481de9c
ZY		 6964 spin_lock_irqsave(&priv->lock, flags);
6965
bb8c093b 6966 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 6967 rc = -EIO;
6968 IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
6969 goto out_unlock;
6970 }
6971
7878a5a4
MA		 6972 /* we don't schedule scan within next_scan_jiffies period */
6973 if (priv->next_scan_jiffies &&
6974 time_after(priv->next_scan_jiffies, jiffies)) {
6975 rc = -EAGAIN;
6976 goto out_unlock;
6977 }
15dbf1b7
BM		 6978 /* if we just finished scan ask for delay for a broadcast scan */
6979 if ((len == 0) && priv->last_scan_jiffies &&
6980 time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN,
6981 jiffies)) {
b481de9c
ZY		 6982 rc = -EAGAIN;
6983 goto out_unlock;
6984 }
6985 if (len) {
7878a5a4 6986 IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
9387b7ca 6987 print_ssid(ssid_buf, ssid, len), (int)len);
b481de9c
ZY		 6988
6989 priv->one_direct_scan = 1;
6990 priv->direct_ssid_len = (u8)
6991 min((u8) len, (u8) IW_ESSID_MAX_SIZE);
6992 memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
6ef89d0a
MA		 6993 } else
6994 priv->one_direct_scan = 0;
b481de9c 6995
bb8c093b 6996 rc = iwl3945_scan_initiate(priv);
b481de9c
ZY		 6997
6998 IWL_DEBUG_MAC80211("leave\n");
6999
7000out_unlock:
7001 spin_unlock_irqrestore(&priv->lock, flags);
15e869d8 7002 mutex_unlock(&priv->mutex);
b481de9c
ZY		 7003
7004 return rc;
7005}
7006
bb8c093b 7007static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
b481de9c
ZY		 7008 const u8 *local_addr, const u8 *addr,
7009 struct ieee80211_key_conf *key)
7010{
bb8c093b 7011 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7012 int rc = 0;
7013 u8 sta_id;
7014
7015 IWL_DEBUG_MAC80211("enter\n");
7016
bb8c093b 7017 if (!iwl3945_param_hwcrypto) {
b481de9c
ZY		 7018 IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
7019 return -EOPNOTSUPP;
7020 }
7021
7022 if (is_zero_ether_addr(addr))
7023 /* only support pairwise keys */
7024 return -EOPNOTSUPP;
7025
bb8c093b 7026 sta_id = iwl3945_hw_find_station(priv, addr);
b481de9c 7027 if (sta_id == IWL_INVALID_STATION) {
e174961c
JB		 7028 IWL_DEBUG_MAC80211("leave - %pM not in station map.\n",
7029 addr);
b481de9c
ZY		 7030 return -EINVAL;
7031 }
7032
7033 mutex_lock(&priv->mutex);
7034
bb8c093b 7035 iwl3945_scan_cancel_timeout(priv, 100);
15e869d8 7036
b481de9c
ZY		 7037 switch (cmd) {
7038 case SET_KEY:
bb8c093b 7039 rc = iwl3945_update_sta_key_info(priv, key, sta_id);
b481de9c 7040 if (!rc) {
bb8c093b
CH		 7041 iwl3945_set_rxon_hwcrypto(priv, 1);
7042 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7043 key->hw_key_idx = sta_id;
7044 IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
7045 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
7046 }
7047 break;
7048 case DISABLE_KEY:
bb8c093b 7049 rc = iwl3945_clear_sta_key_info(priv, sta_id);
b481de9c 7050 if (!rc) {
bb8c093b
CH		 7051 iwl3945_set_rxon_hwcrypto(priv, 0);
7052 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7053 IWL_DEBUG_MAC80211("disable hwcrypto key\n");
7054 }
7055 break;
7056 default:
7057 rc = -EINVAL;
7058 }
7059
7060 IWL_DEBUG_MAC80211("leave\n");
7061 mutex_unlock(&priv->mutex);
7062
7063 return rc;
7064}
7065
e100bb64 7066static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
b481de9c
ZY		 7067 const struct ieee80211_tx_queue_params *params)
7068{
bb8c093b 7069 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7070 unsigned long flags;
7071 int q;
b481de9c
ZY		 7072
7073 IWL_DEBUG_MAC80211("enter\n");
7074
bb8c093b 7075 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7076 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7077 return -EIO;
7078 }
7079
7080 if (queue >= AC_NUM) {
7081 IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
7082 return 0;
7083 }
7084
b481de9c
ZY		 7085 q = AC_NUM - 1 - queue;
7086
7087 spin_lock_irqsave(&priv->lock, flags);
7088
7089 priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
7090 priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
7091 priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
7092 priv->qos_data.def_qos_parm.ac[q].edca_txop =
3330d7be 7093 cpu_to_le16((params->txop * 32));
b481de9c
ZY		 7094
7095 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
7096 priv->qos_data.qos_active = 1;
7097
7098 spin_unlock_irqrestore(&priv->lock, flags);
7099
7100 mutex_lock(&priv->mutex);
05c914fe 7101 if (priv->iw_mode == NL80211_IFTYPE_AP)
bb8c093b
CH		 7102 iwl3945_activate_qos(priv, 1);
7103 else if (priv->assoc_id && iwl3945_is_associated(priv))
7104 iwl3945_activate_qos(priv, 0);
b481de9c
ZY		 7105
7106 mutex_unlock(&priv->mutex);
7107
b481de9c
ZY		 7108 IWL_DEBUG_MAC80211("leave\n");
7109 return 0;
7110}
7111
bb8c093b 7112static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
b481de9c
ZY		 7113 struct ieee80211_tx_queue_stats *stats)
7114{
bb8c093b 7115 struct iwl3945_priv *priv = hw->priv;
b481de9c 7116 int i, avail;
bb8c093b
CH		 7117 struct iwl3945_tx_queue *txq;
7118 struct iwl3945_queue *q;
b481de9c
ZY		 7119 unsigned long flags;
7120
7121 IWL_DEBUG_MAC80211("enter\n");
7122
bb8c093b 7123 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7124 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7125 return -EIO;
7126 }
7127
7128 spin_lock_irqsave(&priv->lock, flags);
7129
7130 for (i = 0; i < AC_NUM; i++) {
7131 txq = &priv->txq[i];
7132 q = &txq->q;
bb8c093b 7133 avail = iwl3945_queue_space(q);
b481de9c 7134
57ffc589
JB		 7135 stats[i].len = q->n_window - avail;
7136 stats[i].limit = q->n_window - q->high_mark;
7137 stats[i].count = q->n_window;
b481de9c
ZY		 7138
7139 }
7140 spin_unlock_irqrestore(&priv->lock, flags);
7141
7142 IWL_DEBUG_MAC80211("leave\n");
7143
7144 return 0;
7145}
7146
bb8c093b 7147static int iwl3945_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY		 7148 struct ieee80211_low_level_stats *stats)
7149{
7150 IWL_DEBUG_MAC80211("enter\n");
7151 IWL_DEBUG_MAC80211("leave\n");
7152
7153 return 0;
7154}
7155
bb8c093b 7156static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
b481de9c 7157{
bb8c093b 7158 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7159 unsigned long flags;
7160
7161 mutex_lock(&priv->mutex);
7162 IWL_DEBUG_MAC80211("enter\n");
7163
bb8c093b 7164 iwl3945_reset_qos(priv);
292ae174 7165
b481de9c
ZY		 7166 spin_lock_irqsave(&priv->lock, flags);
7167 priv->assoc_id = 0;
7168 priv->assoc_capability = 0;
7169 priv->call_post_assoc_from_beacon = 0;
7170
7171 /* new association get rid of ibss beacon skb */
7172 if (priv->ibss_beacon)
7173 dev_kfree_skb(priv->ibss_beacon);
7174
7175 priv->ibss_beacon = NULL;
7176
7177 priv->beacon_int = priv->hw->conf.beacon_int;
7178 priv->timestamp1 = 0;
7179 priv->timestamp0 = 0;
05c914fe 7180 if ((priv->iw_mode == NL80211_IFTYPE_STATION))
b481de9c
ZY		 7181 priv->beacon_int = 0;
7182
7183 spin_unlock_irqrestore(&priv->lock, flags);
7184
fde3571f
MA		 7185 if (!iwl3945_is_ready_rf(priv)) {
7186 IWL_DEBUG_MAC80211("leave - not ready\n");
7187 mutex_unlock(&priv->mutex);
7188 return;
7189 }
7190
15e869d8
MA		 7191 /* we are restarting association process
7192 * clear RXON_FILTER_ASSOC_MSK bit
7193 */
05c914fe 7194 if (priv->iw_mode != NL80211_IFTYPE_AP) {
bb8c093b 7195 iwl3945_scan_cancel_timeout(priv, 100);
15e869d8 7196 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 7197 iwl3945_commit_rxon(priv);
15e869d8
MA		 7198 }
7199
b481de9c 7200 /* Per mac80211.h: This is only used in IBSS mode... */
05c914fe 7201 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
15e869d8 7202
b481de9c
ZY		 7203 IWL_DEBUG_MAC80211("leave - not in IBSS\n");
7204 mutex_unlock(&priv->mutex);
7205 return;
b481de9c
ZY		 7206 }
7207
bb8c093b 7208 iwl3945_set_rate(priv);
b481de9c
ZY		 7209
7210 mutex_unlock(&priv->mutex);
7211
7212 IWL_DEBUG_MAC80211("leave\n");
7213
7214}
7215
e039fa4a 7216static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 7217{
bb8c093b 7218 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7219 unsigned long flags;
7220
b481de9c
ZY		 7221 IWL_DEBUG_MAC80211("enter\n");
7222
bb8c093b 7223 if (!iwl3945_is_ready_rf(priv)) {
b481de9c 7224 IWL_DEBUG_MAC80211("leave - RF not ready\n");
b481de9c
ZY		 7225 return -EIO;
7226 }
7227
05c914fe 7228 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
b481de9c 7229 IWL_DEBUG_MAC80211("leave - not IBSS\n");
b481de9c
ZY		 7230 return -EIO;
7231 }
7232
7233 spin_lock_irqsave(&priv->lock, flags);
7234
7235 if (priv->ibss_beacon)
7236 dev_kfree_skb(priv->ibss_beacon);
7237
7238 priv->ibss_beacon = skb;
7239
7240 priv->assoc_id = 0;
7241
7242 IWL_DEBUG_MAC80211("leave\n");
7243 spin_unlock_irqrestore(&priv->lock, flags);
7244
bb8c093b 7245 iwl3945_reset_qos(priv);
b481de9c 7246
dc4b1e7d 7247 iwl3945_post_associate(priv);
b481de9c 7248
b481de9c
ZY		 7249
7250 return 0;
7251}
7252
7253/*****************************************************************************
7254 *
7255 * sysfs attributes
7256 *
7257 *****************************************************************************/
7258
c8b0e6e1 7259#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 7260
7261/*
7262 * The following adds a new attribute to the sysfs representation
7263 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
7264 * used for controlling the debug level.
7265 *
7266 * See the level definitions in iwl for details.
7267 */
7268
7269static ssize_t show_debug_level(struct device_driver *d, char *buf)
7270{
bb8c093b 7271 return sprintf(buf, "0x%08X\n", iwl3945_debug_level);
b481de9c
ZY		 7272}
7273static ssize_t store_debug_level(struct device_driver *d,
7274 const char *buf, size_t count)
7275{
7276 char *p = (char *)buf;
7277 u32 val;
7278
7279 val = simple_strtoul(p, &p, 0);
7280 if (p == buf)
7281 printk(KERN_INFO DRV_NAME
7282 ": %s is not in hex or decimal form.\n", buf);
7283 else
bb8c093b 7284 iwl3945_debug_level = val;
b481de9c
ZY		 7285
7286 return strnlen(buf, count);
7287}
7288
7289static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
7290 show_debug_level, store_debug_level);
7291
c8b0e6e1 7292#endif /* CONFIG_IWL3945_DEBUG */
b481de9c 7293
b481de9c
ZY		 7294static ssize_t show_temperature(struct device *d,
7295 struct device_attribute *attr, char *buf)
7296{
bb8c093b 7297 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c 7298
bb8c093b 7299 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7300 return -EAGAIN;
7301
bb8c093b 7302 return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
b481de9c
ZY		 7303}
7304
7305static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
7306
b481de9c
ZY		 7307static ssize_t show_tx_power(struct device *d,
7308 struct device_attribute *attr, char *buf)
7309{
bb8c093b 7310 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7311 return sprintf(buf, "%d\n", priv->user_txpower_limit);
7312}
7313
7314static ssize_t store_tx_power(struct device *d,
7315 struct device_attribute *attr,
7316 const char *buf, size_t count)
7317{
bb8c093b 7318 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7319 char *p = (char *)buf;
7320 u32 val;
7321
7322 val = simple_strtoul(p, &p, 10);
7323 if (p == buf)
7324 printk(KERN_INFO DRV_NAME
7325 ": %s is not in decimal form.\n", buf);
7326 else
bb8c093b 7327 iwl3945_hw_reg_set_txpower(priv, val);
b481de9c
ZY		 7328
7329 return count;
7330}
7331
7332static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
7333
7334static ssize_t show_flags(struct device *d,
7335 struct device_attribute *attr, char *buf)
7336{
bb8c093b 7337 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7338
7339 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
7340}
7341
7342static ssize_t store_flags(struct device *d,
7343 struct device_attribute *attr,
7344 const char *buf, size_t count)
7345{
bb8c093b 7346 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7347 u32 flags = simple_strtoul(buf, NULL, 0);
7348
7349 mutex_lock(&priv->mutex);
7350 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
7351 /* Cancel any currently running scans... */
bb8c093b 7352 if (iwl3945_scan_cancel_timeout(priv, 100))
b481de9c
ZY		 7353 IWL_WARNING("Could not cancel scan.\n");
7354 else {
7355 IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
7356 flags);
7357 priv->staging_rxon.flags = cpu_to_le32(flags);
bb8c093b 7358 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7359 }
7360 }
7361 mutex_unlock(&priv->mutex);
7362
7363 return count;
7364}
7365
7366static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
7367
7368static ssize_t show_filter_flags(struct device *d,
7369 struct device_attribute *attr, char *buf)
7370{
bb8c093b 7371 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7372
7373 return sprintf(buf, "0x%04X\n",
7374 le32_to_cpu(priv->active_rxon.filter_flags));
7375}
7376
7377static ssize_t store_filter_flags(struct device *d,
7378 struct device_attribute *attr,
7379 const char *buf, size_t count)
7380{
bb8c093b 7381 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7382 u32 filter_flags = simple_strtoul(buf, NULL, 0);
7383
7384 mutex_lock(&priv->mutex);
7385 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
7386 /* Cancel any currently running scans... */
bb8c093b 7387 if (iwl3945_scan_cancel_timeout(priv, 100))
b481de9c
ZY		 7388 IWL_WARNING("Could not cancel scan.\n");
7389 else {
7390 IWL_DEBUG_INFO("Committing rxon.filter_flags = "
7391 "0x%04X\n", filter_flags);
7392 priv->staging_rxon.filter_flags =
7393 cpu_to_le32(filter_flags);
bb8c093b 7394 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7395 }
7396 }
7397 mutex_unlock(&priv->mutex);
7398
7399 return count;
7400}
7401
7402static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
7403 store_filter_flags);
7404
c8b0e6e1 7405#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 7406
7407static ssize_t show_measurement(struct device *d,
7408 struct device_attribute *attr, char *buf)
7409{
bb8c093b
CH		 7410 struct iwl3945_priv *priv = dev_get_drvdata(d);
7411 struct iwl3945_spectrum_notification measure_report;
b481de9c 7412 u32 size = sizeof(measure_report), len = 0, ofs = 0;
3ac7f146 7413 u8 *data = (u8 *)&measure_report;
b481de9c
ZY		 7414 unsigned long flags;
7415
7416 spin_lock_irqsave(&priv->lock, flags);
7417 if (!(priv->measurement_status & MEASUREMENT_READY)) {
7418 spin_unlock_irqrestore(&priv->lock, flags);
7419 return 0;
7420 }
7421 memcpy(&measure_report, &priv->measure_report, size);
7422 priv->measurement_status = 0;
7423 spin_unlock_irqrestore(&priv->lock, flags);
7424
7425 while (size && (PAGE_SIZE - len)) {
7426 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
7427 PAGE_SIZE - len, 1);
7428 len = strlen(buf);
7429 if (PAGE_SIZE - len)
7430 buf[len++] = '\n';
7431
7432 ofs += 16;
7433 size -= min(size, 16U);
7434 }
7435
7436 return len;
7437}
7438
7439static ssize_t store_measurement(struct device *d,
7440 struct device_attribute *attr,
7441 const char *buf, size_t count)
7442{
bb8c093b 7443 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7444 struct ieee80211_measurement_params params = {
7445 .channel = le16_to_cpu(priv->active_rxon.channel),
7446 .start_time = cpu_to_le64(priv->last_tsf),
7447 .duration = cpu_to_le16(1),
7448 };
7449 u8 type = IWL_MEASURE_BASIC;
7450 u8 buffer[32];
7451 u8 channel;
7452
7453 if (count) {
7454 char *p = buffer;
7455 strncpy(buffer, buf, min(sizeof(buffer), count));
7456 channel = simple_strtoul(p, NULL, 0);
7457 if (channel)
7458 params.channel = channel;
7459
7460 p = buffer;
7461 while (*p && *p != ' ')
7462 p++;
7463 if (*p)
7464 type = simple_strtoul(p + 1, NULL, 0);
7465 }
7466
7467 IWL_DEBUG_INFO("Invoking measurement of type %d on "
7468 "channel %d (for '%s')\n", type, params.channel, buf);
bb8c093b 7469 iwl3945_get_measurement(priv, &params, type);
b481de9c
ZY		 7470
7471 return count;
7472}
7473
7474static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
7475 show_measurement, store_measurement);
c8b0e6e1 7476#endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
b481de9c 7477
b481de9c
ZY		 7478static ssize_t store_retry_rate(struct device *d,
7479 struct device_attribute *attr,
7480 const char *buf, size_t count)
7481{
bb8c093b 7482 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7483
7484 priv->retry_rate = simple_strtoul(buf, NULL, 0);
7485 if (priv->retry_rate <= 0)
7486 priv->retry_rate = 1;
7487
7488 return count;
7489}
7490
7491static ssize_t show_retry_rate(struct device *d,
7492 struct device_attribute *attr, char *buf)
7493{
bb8c093b 7494 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7495 return sprintf(buf, "%d", priv->retry_rate);
7496}
7497
7498static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
7499 store_retry_rate);
7500
7501static ssize_t store_power_level(struct device *d,
7502 struct device_attribute *attr,
7503 const char *buf, size_t count)
7504{
bb8c093b 7505 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7506 int rc;
7507 int mode;
7508
7509 mode = simple_strtoul(buf, NULL, 0);
7510 mutex_lock(&priv->mutex);
7511
bb8c093b 7512 if (!iwl3945_is_ready(priv)) {
b481de9c
ZY		 7513 rc = -EAGAIN;
7514 goto out;
7515 }
7516
7517 if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
7518 mode = IWL_POWER_AC;
7519 else
7520 mode |= IWL_POWER_ENABLED;
7521
7522 if (mode != priv->power_mode) {
bb8c093b 7523 rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
b481de9c
ZY		 7524 if (rc) {
7525 IWL_DEBUG_MAC80211("failed setting power mode.\n");
7526 goto out;
7527 }
7528 priv->power_mode = mode;
7529 }
7530
7531 rc = count;
7532
7533 out:
7534 mutex_unlock(&priv->mutex);
7535 return rc;
7536}
7537
7538#define MAX_WX_STRING 80
7539
7540/* Values are in microsecond */
7541static const s32 timeout_duration[] = {
7542 350000,
7543 250000,
7544 75000,
7545 37000,
7546 25000,
7547};
7548static const s32 period_duration[] = {
7549 400000,
7550 700000,
7551 1000000,
7552 1000000,
7553 1000000
7554};
7555
7556static ssize_t show_power_level(struct device *d,
7557 struct device_attribute *attr, char *buf)
7558{
bb8c093b 7559 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7560 int level = IWL_POWER_LEVEL(priv->power_mode);
7561 char *p = buf;
7562
7563 p += sprintf(p, "%d ", level);
7564 switch (level) {
7565 case IWL_POWER_MODE_CAM:
7566 case IWL_POWER_AC:
7567 p += sprintf(p, "(AC)");
7568 break;
7569 case IWL_POWER_BATTERY:
7570 p += sprintf(p, "(BATTERY)");
7571 break;
7572 default:
7573 p += sprintf(p,
7574 "(Timeout %dms, Period %dms)",
7575 timeout_duration[level - 1] / 1000,
7576 period_duration[level - 1] / 1000);
7577 }
7578
7579 if (!(priv->power_mode & IWL_POWER_ENABLED))
7580 p += sprintf(p, " OFF\n");
7581 else
7582 p += sprintf(p, " \n");
7583
3ac7f146 7584 return p - buf + 1;
b481de9c
ZY		 7585
7586}
7587
7588static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
7589 store_power_level);
7590
7591static ssize_t show_channels(struct device *d,
7592 struct device_attribute *attr, char *buf)
7593{
8318d78a
JB		 7594 /* all this shit doesn't belong into sysfs anyway */
7595 return 0;
b481de9c
ZY		 7596}
7597
7598static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
7599
7600static ssize_t show_statistics(struct device *d,
7601 struct device_attribute *attr, char *buf)
7602{
bb8c093b
CH		 7603 struct iwl3945_priv *priv = dev_get_drvdata(d);
7604 u32 size = sizeof(struct iwl3945_notif_statistics);
b481de9c 7605 u32 len = 0, ofs = 0;
3ac7f146 7606 u8 *data = (u8 *)&priv->statistics;
b481de9c
ZY		 7607 int rc = 0;
7608
bb8c093b 7609 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7610 return -EAGAIN;
7611
7612 mutex_lock(&priv->mutex);
bb8c093b 7613 rc = iwl3945_send_statistics_request(priv);
b481de9c
ZY		 7614 mutex_unlock(&priv->mutex);
7615
7616 if (rc) {
7617 len = sprintf(buf,
7618 "Error sending statistics request: 0x%08X\n", rc);
7619 return len;
7620 }
7621
7622 while (size && (PAGE_SIZE - len)) {
7623 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
7624 PAGE_SIZE - len, 1);
7625 len = strlen(buf);
7626 if (PAGE_SIZE - len)
7627 buf[len++] = '\n';
7628
7629 ofs += 16;
7630 size -= min(size, 16U);
7631 }
7632
7633 return len;
7634}
7635
7636static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
7637
7638static ssize_t show_antenna(struct device *d,
7639 struct device_attribute *attr, char *buf)
7640{
bb8c093b 7641 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c 7642
bb8c093b 7643 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7644 return -EAGAIN;
7645
7646 return sprintf(buf, "%d\n", priv->antenna);
7647}
7648
7649static ssize_t store_antenna(struct device *d,
7650 struct device_attribute *attr,
7651 const char *buf, size_t count)
7652{
7653 int ant;
bb8c093b 7654 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7655
7656 if (count == 0)
7657 return 0;
7658
7659 if (sscanf(buf, "%1i", &ant) != 1) {
7660 IWL_DEBUG_INFO("not in hex or decimal form.\n");
7661 return count;
7662 }
7663
7664 if ((ant >= 0) && (ant <= 2)) {
7665 IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
bb8c093b 7666 priv->antenna = (enum iwl3945_antenna)ant;
b481de9c
ZY		 7667 } else
7668 IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
7669
7670
7671 return count;
7672}
7673
7674static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
7675
7676static ssize_t show_status(struct device *d,
7677 struct device_attribute *attr, char *buf)
7678{
bb8c093b
CH		 7679 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
7680 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7681 return -EAGAIN;
7682 return sprintf(buf, "0x%08x\n", (int)priv->status);
7683}
7684
7685static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
7686
7687static ssize_t dump_error_log(struct device *d,
7688 struct device_attribute *attr,
7689 const char *buf, size_t count)
7690{
7691 char *p = (char *)buf;
7692
7693 if (p[0] == '1')
bb8c093b 7694 iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data);
b481de9c
ZY		 7695
7696 return strnlen(buf, count);
7697}
7698
7699static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
7700
7701static ssize_t dump_event_log(struct device *d,
7702 struct device_attribute *attr,
7703 const char *buf, size_t count)
7704{
7705 char *p = (char *)buf;
7706
7707 if (p[0] == '1')
bb8c093b 7708 iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data);
b481de9c
ZY		 7709
7710 return strnlen(buf, count);
7711}
7712
7713static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
7714
7715/*****************************************************************************
7716 *
a96a27f9 7717 * driver setup and tear down
b481de9c
ZY		 7718 *
7719 *****************************************************************************/
7720
bb8c093b 7721static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv)
b481de9c
ZY		 7722{
7723 priv->workqueue = create_workqueue(DRV_NAME);
7724
7725 init_waitqueue_head(&priv->wait_command_queue);
7726
bb8c093b
CH		 7727 INIT_WORK(&priv->up, iwl3945_bg_up);
7728 INIT_WORK(&priv->restart, iwl3945_bg_restart);
7729 INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
7730 INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
7731 INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
7732 INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
7733 INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
7734 INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
bb8c093b
CH		 7735 INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
7736 INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
7737 INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
7738
7739 iwl3945_hw_setup_deferred_work(priv);
b481de9c
ZY		 7740
7741 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
bb8c093b 7742 iwl3945_irq_tasklet, (unsigned long)priv);
b481de9c
ZY		 7743}
7744
bb8c093b 7745static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv)
b481de9c 7746{
bb8c093b 7747 iwl3945_hw_cancel_deferred_work(priv);
b481de9c 7748
e47eb6ad 7749 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY		 7750 cancel_delayed_work(&priv->scan_check);
7751 cancel_delayed_work(&priv->alive_start);
b481de9c
ZY		 7752 cancel_work_sync(&priv->beacon_update);
7753}
7754
bb8c093b 7755static struct attribute *iwl3945_sysfs_entries[] = {
b481de9c
ZY		 7756 &dev_attr_antenna.attr,
7757 &dev_attr_channels.attr,
7758 &dev_attr_dump_errors.attr,
7759 &dev_attr_dump_events.attr,
7760 &dev_attr_flags.attr,
7761 &dev_attr_filter_flags.attr,
c8b0e6e1 7762#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 7763 &dev_attr_measurement.attr,
7764#endif
7765 &dev_attr_power_level.attr,
b481de9c 7766 &dev_attr_retry_rate.attr,
b481de9c
ZY		 7767 &dev_attr_statistics.attr,
7768 &dev_attr_status.attr,
7769 &dev_attr_temperature.attr,
b481de9c
ZY		 7770 &dev_attr_tx_power.attr,
7771
7772 NULL
7773};
7774
bb8c093b 7775static struct attribute_group iwl3945_attribute_group = {
b481de9c 7776 .name = NULL, /* put in device directory */
bb8c093b 7777 .attrs = iwl3945_sysfs_entries,
b481de9c
ZY		 7778};
7779
bb8c093b
CH		 7780static struct ieee80211_ops iwl3945_hw_ops = {
7781 .tx = iwl3945_mac_tx,
7782 .start = iwl3945_mac_start,
7783 .stop = iwl3945_mac_stop,
7784 .add_interface = iwl3945_mac_add_interface,
7785 .remove_interface = iwl3945_mac_remove_interface,
7786 .config = iwl3945_mac_config,
7787 .config_interface = iwl3945_mac_config_interface,
7788 .configure_filter = iwl3945_configure_filter,
7789 .set_key = iwl3945_mac_set_key,
7790 .get_stats = iwl3945_mac_get_stats,
7791 .get_tx_stats = iwl3945_mac_get_tx_stats,
7792 .conf_tx = iwl3945_mac_conf_tx,
bb8c093b 7793 .reset_tsf = iwl3945_mac_reset_tsf,
cd56d331 7794 .bss_info_changed = iwl3945_bss_info_changed,
bb8c093b 7795 .hw_scan = iwl3945_mac_hw_scan
b481de9c
ZY		 7796};
7797
bb8c093b 7798static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY		 7799{
7800 int err = 0;
bb8c093b 7801 struct iwl3945_priv *priv;
b481de9c 7802 struct ieee80211_hw *hw;
82b9a121 7803 struct iwl_3945_cfg *cfg = (struct iwl_3945_cfg *)(ent->driver_data);
0359facc 7804 unsigned long flags;
b481de9c 7805
cee53ddb
KA		 7806 /***********************
7807 * 1. Allocating HW data
7808 * ********************/
7809
6440adb5
CB		 7810 /* Disabling hardware scan means that mac80211 will perform scans
7811 * "the hard way", rather than using device's scan. */
bb8c093b 7812 if (iwl3945_param_disable_hw_scan) {
b481de9c 7813 IWL_DEBUG_INFO("Disabling hw_scan\n");
bb8c093b 7814 iwl3945_hw_ops.hw_scan = NULL;
b481de9c
ZY		 7815 }
7816
dfe7d458 7817 if ((iwl3945_param_queues_num > IWL39_MAX_NUM_QUEUES) ||
bb8c093b 7818 (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) {
b481de9c 7819 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
dfe7d458 7820 IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES);
b481de9c
ZY		 7821 err = -EINVAL;
7822 goto out;
7823 }
7824
7825 /* mac80211 allocates memory for this device instance, including
7826 * space for this driver's private structure */
bb8c093b 7827 hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops);
b481de9c
ZY		 7828 if (hw == NULL) {
7829 IWL_ERROR("Can not allocate network device\n");
7830 err = -ENOMEM;
7831 goto out;
7832 }
b481de9c 7833
cee53ddb 7834 SET_IEEE80211_DEV(hw, &pdev->dev);
f51359a8 7835
b481de9c
ZY		 7836 priv = hw->priv;
7837 priv->hw = hw;
b481de9c 7838 priv->pci_dev = pdev;
82b9a121 7839 priv->cfg = cfg;
6440adb5 7840
cee53ddb
KA		 7841 IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
7842 hw->rate_control_algorithm = "iwl-3945-rs";
7843 hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
7844
6440adb5 7845 /* Select antenna (may be helpful if only one antenna is connected) */
bb8c093b 7846 priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna;
c8b0e6e1 7847#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 7848 iwl3945_debug_level = iwl3945_param_debug;
b481de9c
ZY		 7849 atomic_set(&priv->restrict_refcnt, 0);
7850#endif
b481de9c 7851
566bfe5a 7852 /* Tell mac80211 our characteristics */
605a0bd6 7853 hw->flags = IEEE80211_HW_SIGNAL_DBM |
566bfe5a 7854 IEEE80211_HW_NOISE_DBM;
b481de9c 7855
f59ac048 7856 hw->wiphy->interface_modes =
f59ac048
LR		 7857 BIT(NL80211_IFTYPE_STATION) |
7858 BIT(NL80211_IFTYPE_ADHOC);
7859
ea4a82dc
LR		 7860 hw->wiphy->fw_handles_regulatory = true;
7861
6440adb5 7862 /* 4 EDCA QOS priorities */
b481de9c
ZY		 7863 hw->queues = 4;
7864
cee53ddb
KA		 7865 /***************************
7866 * 2. Initializing PCI bus
7867 * *************************/
b481de9c
ZY		 7868 if (pci_enable_device(pdev)) {
7869 err = -ENODEV;
7870 goto out_ieee80211_free_hw;
7871 }
7872
7873 pci_set_master(pdev);
7874
b481de9c
ZY		 7875 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
7876 if (!err)
7877 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
7878 if (err) {
7879 printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
7880 goto out_pci_disable_device;
7881 }
7882
7883 pci_set_drvdata(pdev, priv);
7884 err = pci_request_regions(pdev, DRV_NAME);
7885 if (err)
7886 goto out_pci_disable_device;
6440adb5 7887
cee53ddb
KA		 7888 /***********************
7889 * 3. Read REV Register
7890 * ********************/
b481de9c
ZY		 7891 priv->hw_base = pci_iomap(pdev, 0, 0);
7892 if (!priv->hw_base) {
7893 err = -ENODEV;
7894 goto out_pci_release_regions;
7895 }
7896
7897 IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
7898 (unsigned long long) pci_resource_len(pdev, 0));
7899 IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
7900
cee53ddb
KA		 7901 /* We disable the RETRY_TIMEOUT register (0x41) to keep
7902 * PCI Tx retries from interfering with C3 CPU state */
7903 pci_write_config_byte(pdev, 0x41, 0x00);
b481de9c 7904
cee53ddb
KA		 7905 /* nic init */
7906 iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
7907 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
b481de9c 7908
cee53ddb 7909 iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
73d7b5ac
ZY		 7910 err = iwl3945_poll_direct_bit(priv, CSR_GP_CNTRL,
7911 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
cee53ddb
KA		 7912 if (err < 0) {
7913 IWL_DEBUG_INFO("Failed to init the card\n");
623d563e 7914 goto out_iounmap;
cee53ddb 7915 }
b481de9c 7916
cee53ddb
KA		 7917 /***********************
7918 * 4. Read EEPROM
7919 * ********************/
7920 /* Read the EEPROM */
7921 err = iwl3945_eeprom_init(priv);
7922 if (err) {
7923 IWL_ERROR("Unable to init EEPROM\n");
623d563e 7924 goto out_iounmap;
cee53ddb
KA		 7925 }
7926 /* MAC Address location in EEPROM same for 3945/4965 */
7927 get_eeprom_mac(priv, priv->mac_addr);
7928 IWL_DEBUG_INFO("MAC address: %pM\n", priv->mac_addr);
7929 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
b481de9c 7930
cee53ddb
KA		 7931 /***********************
7932 * 5. Setup HW Constants
7933 * ********************/
b481de9c 7934 /* Device-specific setup */
bb8c093b 7935 if (iwl3945_hw_set_hw_setting(priv)) {
b481de9c 7936 IWL_ERROR("failed to set hw settings\n");
b481de9c
ZY		 7937 goto out_iounmap;
7938 }
7939
cee53ddb
KA		 7940 /***********************
7941 * 6. Setup priv
7942 * ********************/
7943 priv->retry_rate = 1;
7944 priv->ibss_beacon = NULL;
7945
7946 spin_lock_init(&priv->lock);
7947 spin_lock_init(&priv->power_data.lock);
7948 spin_lock_init(&priv->sta_lock);
7949 spin_lock_init(&priv->hcmd_lock);
7950
7951 INIT_LIST_HEAD(&priv->free_frames);
7952 mutex_init(&priv->mutex);
7953
7954 /* Clear the driver's (not device's) station table */
7955 iwl3945_clear_stations_table(priv);
7956
7957 priv->data_retry_limit = -1;
7958 priv->ieee_channels = NULL;
7959 priv->ieee_rates = NULL;
7960 priv->band = IEEE80211_BAND_2GHZ;
7961
7962 priv->iw_mode = NL80211_IFTYPE_STATION;
7963
bb8c093b 7964 iwl3945_reset_qos(priv);
b481de9c
ZY		 7965
7966 priv->qos_data.qos_active = 0;
7967 priv->qos_data.qos_cap.val = 0;
b481de9c 7968
b481de9c
ZY		 7969
7970 priv->rates_mask = IWL_RATES_MASK;
7971 /* If power management is turned on, default to AC mode */
7972 priv->power_mode = IWL_POWER_AC;
7973 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
7974
cee53ddb 7975 err = iwl3945_init_channel_map(priv);
b481de9c 7976 if (err) {
cee53ddb 7977 IWL_ERROR("initializing regulatory failed: %d\n", err);
623d563e 7978 goto out_unset_hw_setting;
b481de9c
ZY		 7979 }
7980
cee53ddb 7981 err = iwl3945_init_geos(priv);
b481de9c 7982 if (err) {
cee53ddb
KA		 7983 IWL_ERROR("initializing geos failed: %d\n", err);
7984 goto out_free_channel_map;
b481de9c
ZY		 7985 }
7986
cee53ddb
KA		 7987 printk(KERN_INFO DRV_NAME
7988 ": Detected Intel Wireless WiFi Link %s\n", priv->cfg->name);
7989
7990 /***********************************
7991 * 7. Initialize Module Parameters
7992 * **********************************/
7993
7994 /* Initialize module parameter values here */
7995 /* Disable radio (SW RF KILL) via parameter when loading driver */
7996 if (iwl3945_param_disable) {
7997 set_bit(STATUS_RF_KILL_SW, &priv->status);
7998 IWL_DEBUG_INFO("Radio disabled.\n");
849e0dce
RC		 7999 }
8000
cee53ddb
KA		 8001
8002 /***********************
8003 * 8. Setup Services
8004 * ********************/
8005
8006 spin_lock_irqsave(&priv->lock, flags);
8007 iwl3945_disable_interrupts(priv);
8008 spin_unlock_irqrestore(&priv->lock, flags);
8009
8010 err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
849e0dce 8011 if (err) {
cee53ddb
KA		 8012 IWL_ERROR("failed to create sysfs device attributes\n");
8013 goto out_free_geos;
849e0dce 8014 }
849e0dce 8015
cee53ddb
KA		 8016 iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
8017 iwl3945_setup_deferred_work(priv);
8018 iwl3945_setup_rx_handlers(priv);
8019
8020 /***********************
8021 * 9. Conclude
8022 * ********************/
8023 pci_save_state(pdev);
8024 pci_disable_device(pdev);
8025
8026 /*********************************
8027 * 10. Setup and Register mac80211
8028 * *******************************/
8029
5a66926a
ZY		 8030 err = ieee80211_register_hw(priv->hw);
8031 if (err) {
8032 IWL_ERROR("Failed to register network device (error %d)\n", err);
cee53ddb 8033 goto out_remove_sysfs;
5a66926a 8034 }
b481de9c 8035
5a66926a
ZY		 8036 priv->hw->conf.beacon_int = 100;
8037 priv->mac80211_registered = 1;
cee53ddb 8038
b481de9c 8039
ebef2008
AK		 8040 err = iwl3945_rfkill_init(priv);
8041 if (err)
8042 IWL_ERROR("Unable to initialize RFKILL system. "
8043 "Ignoring error: %d\n", err);
8044
b481de9c
ZY		 8045 return 0;
8046
cee53ddb 8047 out_remove_sysfs:
623d563e
RC		 8048 destroy_workqueue(priv->workqueue);
8049 priv->workqueue = NULL;
cee53ddb 8050 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
849e0dce
RC		 8051 out_free_geos:
8052 iwl3945_free_geos(priv);
8053 out_free_channel_map:
8054 iwl3945_free_channel_map(priv);
623d563e 8055 out_unset_hw_setting:
bb8c093b 8056 iwl3945_unset_hw_setting(priv);
b481de9c
ZY		 8057 out_iounmap:
8058 pci_iounmap(pdev, priv->hw_base);
8059 out_pci_release_regions:
8060 pci_release_regions(pdev);
8061 out_pci_disable_device:
b481de9c 8062 pci_set_drvdata(pdev, NULL);
623d563e 8063 pci_disable_device(pdev);
b481de9c
ZY		 8064 out_ieee80211_free_hw:
8065 ieee80211_free_hw(priv->hw);
8066 out:
8067 return err;
8068}
8069
c83dbf68 8070static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
b481de9c 8071{
bb8c093b 8072 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
0359facc 8073 unsigned long flags;
b481de9c
ZY		 8074
8075 if (!priv)
8076 return;
8077
8078 IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
8079
b481de9c 8080 set_bit(STATUS_EXIT_PENDING, &priv->status);
b24d22b1 8081
bb8c093b 8082 iwl3945_down(priv);
b481de9c 8083
0359facc
MA		 8084 /* make sure we flush any pending irq or
8085 * tasklet for the driver
8086 */
8087 spin_lock_irqsave(&priv->lock, flags);
8088 iwl3945_disable_interrupts(priv);
8089 spin_unlock_irqrestore(&priv->lock, flags);
8090
8091 iwl_synchronize_irq(priv);
8092
bb8c093b 8093 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 8094
ebef2008 8095 iwl3945_rfkill_unregister(priv);
bb8c093b 8096 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY		 8097
8098 if (priv->rxq.bd)
bb8c093b
CH		 8099 iwl3945_rx_queue_free(priv, &priv->rxq);
8100 iwl3945_hw_txq_ctx_free(priv);
b481de9c 8101
bb8c093b
CH		 8102 iwl3945_unset_hw_setting(priv);
8103 iwl3945_clear_stations_table(priv);
b481de9c 8104
3ac7f146 8105 if (priv->mac80211_registered)
b481de9c 8106 ieee80211_unregister_hw(priv->hw);
b481de9c 8107
6ef89d0a
MA		 8108 /*netif_stop_queue(dev); */
8109 flush_workqueue(priv->workqueue);
8110
bb8c093b 8111 /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
b481de9c
ZY		 8112 * priv->workqueue... so we can't take down the workqueue
8113 * until now... */
8114 destroy_workqueue(priv->workqueue);
8115 priv->workqueue = NULL;
8116
b481de9c
ZY		 8117 pci_iounmap(pdev, priv->hw_base);
8118 pci_release_regions(pdev);
8119 pci_disable_device(pdev);
8120 pci_set_drvdata(pdev, NULL);
8121
849e0dce
RC		 8122 iwl3945_free_channel_map(priv);
8123 iwl3945_free_geos(priv);
261415f7 8124 kfree(priv->scan);
b481de9c
ZY		 8125 if (priv->ibss_beacon)
8126 dev_kfree_skb(priv->ibss_beacon);
8127
8128 ieee80211_free_hw(priv->hw);
8129}
8130
8131#ifdef CONFIG_PM
8132
bb8c093b 8133static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
b481de9c 8134{
bb8c093b 8135 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c 8136
e655b9f0
ZY		 8137 if (priv->is_open) {
8138 set_bit(STATUS_IN_SUSPEND, &priv->status);
8139 iwl3945_mac_stop(priv->hw);
8140 priv->is_open = 1;
8141 }
b481de9c 8142
89c581b3
RC		 8143 /* pci driver assumes state will be saved in this function.
8144 * pci state is saved and device disabled when interface is
8145 * stopped, so at this time pci device will always be disabled -
8146 * whether interface was started or not. saving pci state now will
8147 * cause saved state be that of a disabled device, which will cause
8148 * problems during resume in that we will end up with a disabled device.
8149 *
8150 * indicate that the current saved state (from when interface was
8151 * stopped) is valid. if interface was never up at time of suspend
8152 * then the saved state will still be valid as it was saved during
8153 * .probe. */
8154 pdev->state_saved = true;
8155
b481de9c
ZY		 8156 pci_set_power_state(pdev, PCI_D3hot);
8157
b481de9c
ZY		 8158 return 0;
8159}
8160
bb8c093b 8161static int iwl3945_pci_resume(struct pci_dev *pdev)
b481de9c 8162{
bb8c093b 8163 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c 8164
b481de9c 8165 pci_set_power_state(pdev, PCI_D0);
b481de9c 8166
e655b9f0
ZY		 8167 if (priv->is_open)
8168 iwl3945_mac_start(priv->hw);
b481de9c 8169
e655b9f0 8170 clear_bit(STATUS_IN_SUSPEND, &priv->status);
b481de9c
ZY		 8171 return 0;
8172}
8173
8174#endif /* CONFIG_PM */
8175
ebef2008 8176/*************** RFKILL FUNCTIONS **********/
80fcc9e2 8177#ifdef CONFIG_IWL3945_RFKILL
ebef2008
AK		 8178/* software rf-kill from user */
8179static int iwl3945_rfkill_soft_rf_kill(void *data, enum rfkill_state state)
8180{
8181 struct iwl3945_priv *priv = data;
8182 int err = 0;
8183
80fcc9e2 8184 if (!priv->rfkill)
ebef2008
AK		 8185 return 0;
8186
8187 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
8188 return 0;
8189
a96a27f9 8190 IWL_DEBUG_RF_KILL("we received soft RFKILL set to state %d\n", state);
ebef2008
AK		 8191 mutex_lock(&priv->mutex);
8192
8193 switch (state) {
acdfe9b4 8194 case RFKILL_STATE_UNBLOCKED:
80fcc9e2 8195 if (iwl3945_is_rfkill_hw(priv)) {
ebef2008 8196 err = -EBUSY;
80fcc9e2
AG		 8197 goto out_unlock;
8198 }
8199 iwl3945_radio_kill_sw(priv, 0);
ebef2008 8200 break;
acdfe9b4 8201 case RFKILL_STATE_SOFT_BLOCKED:
ebef2008 8202 iwl3945_radio_kill_sw(priv, 1);
ebef2008 8203 break;
acdfe9b4 8204 default:
a96a27f9 8205 IWL_WARNING("we received unexpected RFKILL state %d\n", state);
acdfe9b4 8206 break;
ebef2008 8207 }
80fcc9e2 8208out_unlock:
ebef2008
AK		 8209 mutex_unlock(&priv->mutex);
8210
8211 return err;
8212}
8213
8214int iwl3945_rfkill_init(struct iwl3945_priv *priv)
8215{
8216 struct device *device = wiphy_dev(priv->hw->wiphy);
8217 int ret = 0;
8218
8219 BUG_ON(device == NULL);
8220
8221 IWL_DEBUG_RF_KILL("Initializing RFKILL.\n");
80fcc9e2
AG		 8222 priv->rfkill = rfkill_allocate(device, RFKILL_TYPE_WLAN);
8223 if (!priv->rfkill) {
ebef2008
AK		 8224 IWL_ERROR("Unable to allocate rfkill device.\n");
8225 ret = -ENOMEM;
8226 goto error;
8227 }
8228
80fcc9e2
AG		 8229 priv->rfkill->name = priv->cfg->name;
8230 priv->rfkill->data = priv;
8231 priv->rfkill->state = RFKILL_STATE_UNBLOCKED;
8232 priv->rfkill->toggle_radio = iwl3945_rfkill_soft_rf_kill;
8233 priv->rfkill->user_claim_unsupported = 1;
ebef2008 8234
80fcc9e2
AG		 8235 priv->rfkill->dev.class->suspend = NULL;
8236 priv->rfkill->dev.class->resume = NULL;
ebef2008 8237
80fcc9e2 8238 ret = rfkill_register(priv->rfkill);
ebef2008
AK		 8239 if (ret) {
8240 IWL_ERROR("Unable to register rfkill: %d\n", ret);
80fcc9e2 8241 goto freed_rfkill;
ebef2008
AK		 8242 }
8243
8244 IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
8245 return ret;
8246
ebef2008 8247freed_rfkill:
80fcc9e2
AG		 8248 if (priv->rfkill != NULL)
8249 rfkill_free(priv->rfkill);
8250 priv->rfkill = NULL;
ebef2008
AK		 8251
8252error:
8253 IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
8254 return ret;
8255}
8256
8257void iwl3945_rfkill_unregister(struct iwl3945_priv *priv)
8258{
80fcc9e2
AG		 8259 if (priv->rfkill)
8260 rfkill_unregister(priv->rfkill);
ebef2008 8261
80fcc9e2 8262 priv->rfkill = NULL;
ebef2008
AK		 8263}
8264
8265/* set rf-kill to the right state. */
8266void iwl3945_rfkill_set_hw_state(struct iwl3945_priv *priv)
8267{
8268
80fcc9e2
AG		 8269 if (!priv->rfkill)
8270 return;
8271
8272 if (iwl3945_is_rfkill_hw(priv)) {
8273 rfkill_force_state(priv->rfkill, RFKILL_STATE_HARD_BLOCKED);
ebef2008 8274 return;
80fcc9e2 8275 }
ebef2008 8276
80fcc9e2
AG		 8277 if (!iwl3945_is_rfkill_sw(priv))
8278 rfkill_force_state(priv->rfkill, RFKILL_STATE_UNBLOCKED);
ebef2008 8279 else
80fcc9e2 8280 rfkill_force_state(priv->rfkill, RFKILL_STATE_SOFT_BLOCKED);
ebef2008
AK		 8281}
8282#endif
8283
b481de9c
ZY		 8284/*****************************************************************************
8285 *
8286 * driver and module entry point
8287 *
8288 *****************************************************************************/
8289
bb8c093b 8290static struct pci_driver iwl3945_driver = {
b481de9c 8291 .name = DRV_NAME,
bb8c093b
CH		 8292 .id_table = iwl3945_hw_card_ids,
8293 .probe = iwl3945_pci_probe,
8294 .remove = __devexit_p(iwl3945_pci_remove),
b481de9c 8295#ifdef CONFIG_PM
bb8c093b
CH		 8296 .suspend = iwl3945_pci_suspend,
8297 .resume = iwl3945_pci_resume,
b481de9c
ZY		 8298#endif
8299};
8300
bb8c093b 8301static int __init iwl3945_init(void)
b481de9c
ZY		 8302{
8303
8304 int ret;
8305 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
8306 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2
RC		 8307
8308 ret = iwl3945_rate_control_register();
8309 if (ret) {
8310 IWL_ERROR("Unable to register rate control algorithm: %d\n", ret);
8311 return ret;
8312 }
8313
bb8c093b 8314 ret = pci_register_driver(&iwl3945_driver);
b481de9c
ZY		 8315 if (ret) {
8316 IWL_ERROR("Unable to initialize PCI module\n");
897e1cf2 8317 goto error_register;
b481de9c 8318 }
c8b0e6e1 8319#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8320 ret = driver_create_file(&iwl3945_driver.driver, &driver_attr_debug_level);
b481de9c
ZY		 8321 if (ret) {
8322 IWL_ERROR("Unable to create driver sysfs file\n");
897e1cf2 8323 goto error_debug;
b481de9c
ZY		 8324 }
8325#endif
8326
8327 return ret;
897e1cf2
RC		 8328
8329#ifdef CONFIG_IWL3945_DEBUG
8330error_debug:
8331 pci_unregister_driver(&iwl3945_driver);
8332#endif
8333error_register:
8334 iwl3945_rate_control_unregister();
8335 return ret;
b481de9c
ZY		 8336}
8337
bb8c093b 8338static void __exit iwl3945_exit(void)
b481de9c 8339{
c8b0e6e1 8340#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8341 driver_remove_file(&iwl3945_driver.driver, &driver_attr_debug_level);
b481de9c 8342#endif
bb8c093b 8343 pci_unregister_driver(&iwl3945_driver);
897e1cf2 8344 iwl3945_rate_control_unregister();
b481de9c
ZY		 8345}
8346
a0987a8d 8347MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
25cb6cad 8348
bb8c093b 8349module_param_named(antenna, iwl3945_param_antenna, int, 0444);
b481de9c 8350MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
bb8c093b 8351module_param_named(disable, iwl3945_param_disable, int, 0444);
b481de9c 8352MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
bb8c093b 8353module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444);
b481de9c
ZY		 8354MODULE_PARM_DESC(hwcrypto,
8355 "using hardware crypto engine (default 0 [software])\n");
95aa194a 8356module_param_named(debug, iwl3945_param_debug, uint, 0444);
b481de9c 8357MODULE_PARM_DESC(debug, "debug output mask");
bb8c093b 8358module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444);
b481de9c
ZY		 8359MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
8360
bb8c093b 8361module_param_named(queues_num, iwl3945_param_queues_num, int, 0444);
b481de9c
ZY		 8362MODULE_PARM_DESC(queues_num, "number of hw queues.");
8363
bb8c093b
CH		 8364module_exit(iwl3945_exit);
8365module_init(iwl3945_init);
Linux kernel - Deliverables
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