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mac80211: reorder some transmit handlers
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl3945-base.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
b481de9c
ZY		 30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/version.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/dma-mapping.h>
36#include <linux/delay.h>
37#include <linux/skbuff.h>
38#include <linux/netdevice.h>
39#include <linux/wireless.h>
40#include <linux/firmware.h>
b481de9c
ZY		 41#include <linux/etherdevice.h>
42#include <linux/if_arp.h>
43
44#include <net/ieee80211_radiotap.h>
45#include <net/mac80211.h>
46
47#include <asm/div64.h>
48
82b9a121 49#include "iwl-3945-core.h"
b481de9c
ZY		 50#include "iwl-3945.h"
51#include "iwl-helpers.h"
52
c8b0e6e1 53#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 54u32 iwl3945_debug_level;
b481de9c
ZY		 55#endif
56
bb8c093b
CH		 57static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
58 struct iwl3945_tx_queue *txq);
416e1438 59
b481de9c
ZY		 60/******************************************************************************
61 *
62 * module boiler plate
63 *
64 ******************************************************************************/
65
66/* module parameters */
6440adb5
CB		 67static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */
68static int iwl3945_param_debug; /* def: 0 = minimal debug log messages */
69static int iwl3945_param_disable; /* def: 0 = enable radio */
9fbab516 70static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */
6440adb5
CB		 71int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */
72static int iwl3945_param_qos_enable = 1; /* def: 1 = use quality of service */
dfe7d458 73int iwl3945_param_queues_num = IWL39_MAX_NUM_QUEUES; /* def: 8 Tx queues */
b481de9c
ZY		 74
75/*
76 * module name, copyright, version, etc.
77 * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
78 */
79
80#define DRV_DESCRIPTION \
81"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
82
c8b0e6e1 83#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 84#define VD "d"
85#else
86#define VD
87#endif
88
c8b0e6e1 89#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 90#define VS "s"
91#else
92#define VS
93#endif
94
b9e0b449 95#define IWLWIFI_VERSION "1.2.26k" VD VS
eb7ae89c 96#define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation"
b481de9c
ZY		 97#define DRV_VERSION IWLWIFI_VERSION
98
b481de9c
ZY		 99
100MODULE_DESCRIPTION(DRV_DESCRIPTION);
101MODULE_VERSION(DRV_VERSION);
102MODULE_AUTHOR(DRV_COPYRIGHT);
103MODULE_LICENSE("GPL");
104
8318d78a
JB		 105static const struct ieee80211_supported_band *iwl3945_get_band(
106 struct iwl3945_priv *priv, enum ieee80211_band band)
b481de9c 107{
8318d78a 108 return priv->hw->wiphy->bands[band];
b481de9c
ZY		 109}
110
bb8c093b 111static int iwl3945_is_empty_essid(const char *essid, int essid_len)
b481de9c
ZY		 112{
113 /* Single white space is for Linksys APs */
114 if (essid_len == 1 && essid[0] == ' ')
115 return 1;
116
117 /* Otherwise, if the entire essid is 0, we assume it is hidden */
118 while (essid_len) {
119 essid_len--;
120 if (essid[essid_len] != '\0')
121 return 0;
122 }
123
124 return 1;
125}
126
bb8c093b 127static const char *iwl3945_escape_essid(const char *essid, u8 essid_len)
b481de9c
ZY		 128{
129 static char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
130 const char *s = essid;
131 char *d = escaped;
132
bb8c093b 133 if (iwl3945_is_empty_essid(essid, essid_len)) {
b481de9c
ZY		 134 memcpy(escaped, "<hidden>", sizeof("<hidden>"));
135 return escaped;
136 }
137
138 essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE);
139 while (essid_len--) {
140 if (*s == '\0') {
141 *d++ = '\\';
142 *d++ = '0';
143 s++;
144 } else
145 *d++ = *s++;
146 }
147 *d = '\0';
148 return escaped;
149}
150
b481de9c
ZY		 151/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
152 * DMA services
153 *
154 * Theory of operation
155 *
6440adb5
CB		 156 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
157 * of buffer descriptors, each of which points to one or more data buffers for
158 * the device to read from or fill. Driver and device exchange status of each
159 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
160 * entries in each circular buffer, to protect against confusing empty and full
161 * queue states.
162 *
163 * The device reads or writes the data in the queues via the device's several
164 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
b481de9c
ZY		 165 *
166 * For Tx queue, there are low mark and high mark limits. If, after queuing
167 * the packet for Tx, free space become < low mark, Tx queue stopped. When
168 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
169 * Tx queue resumed.
170 *
6440adb5
CB		 171 * The 3945 operates with six queues: One receive queue, one transmit queue
172 * (#4) for sending commands to the device firmware, and four transmit queues
173 * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
b481de9c
ZY		 174 ***************************************************/
175
c54b679d 176int iwl3945_queue_space(const struct iwl3945_queue *q)
b481de9c 177{
fc4b6853 178 int s = q->read_ptr - q->write_ptr;
b481de9c 179
fc4b6853 180 if (q->read_ptr > q->write_ptr)
b481de9c
ZY		 181 s -= q->n_bd;
182
183 if (s <= 0)
184 s += q->n_window;
185 /* keep some reserve to not confuse empty and full situations */
186 s -= 2;
187 if (s < 0)
188 s = 0;
189 return s;
190}
191
c54b679d 192int iwl3945_x2_queue_used(const struct iwl3945_queue *q, int i)
b481de9c 193{
fc4b6853
TW		 194 return q->write_ptr > q->read_ptr ?
195 (i >= q->read_ptr && i < q->write_ptr) :
196 !(i < q->read_ptr && i >= q->write_ptr);
b481de9c
ZY		 197}
198
c54b679d 199
bb8c093b 200static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge)
b481de9c 201{
6440adb5 202 /* This is for scan command, the big buffer at end of command array */
b481de9c 203 if (is_huge)
6440adb5 204 return q->n_window; /* must be power of 2 */
b481de9c 205
6440adb5 206 /* Otherwise, use normal size buffers */
b481de9c
ZY		 207 return index & (q->n_window - 1);
208}
209
6440adb5
CB		 210/**
211 * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
212 */
bb8c093b 213static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q,
b481de9c
ZY		 214 int count, int slots_num, u32 id)
215{
216 q->n_bd = count;
217 q->n_window = slots_num;
218 q->id = id;
219
c54b679d
TW		 220 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
221 * and iwl_queue_dec_wrap are broken. */
b481de9c
ZY		 222 BUG_ON(!is_power_of_2(count));
223
224 /* slots_num must be power-of-two size, otherwise
225 * get_cmd_index is broken. */
226 BUG_ON(!is_power_of_2(slots_num));
227
228 q->low_mark = q->n_window / 4;
229 if (q->low_mark < 4)
230 q->low_mark = 4;
231
232 q->high_mark = q->n_window / 8;
233 if (q->high_mark < 2)
234 q->high_mark = 2;
235
fc4b6853 236 q->write_ptr = q->read_ptr = 0;
b481de9c
ZY		 237
238 return 0;
239}
240
6440adb5
CB		 241/**
242 * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
243 */
bb8c093b
CH		 244static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
245 struct iwl3945_tx_queue *txq, u32 id)
b481de9c
ZY		 246{
247 struct pci_dev *dev = priv->pci_dev;
248
6440adb5
CB		 249 /* Driver private data, only for Tx (not command) queues,
250 * not shared with device. */
b481de9c
ZY		 251 if (id != IWL_CMD_QUEUE_NUM) {
252 txq->txb = kmalloc(sizeof(txq->txb[0]) *
253 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
254 if (!txq->txb) {
01ebd063 255 IWL_ERROR("kmalloc for auxiliary BD "
b481de9c
ZY		 256 "structures failed\n");
257 goto error;
258 }
259 } else
260 txq->txb = NULL;
261
6440adb5
CB		 262 /* Circular buffer of transmit frame descriptors (TFDs),
263 * shared with device */
b481de9c
ZY		 264 txq->bd = pci_alloc_consistent(dev,
265 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
266 &txq->q.dma_addr);
267
268 if (!txq->bd) {
269 IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
270 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
271 goto error;
272 }
273 txq->q.id = id;
274
275 return 0;
276
277 error:
278 if (txq->txb) {
279 kfree(txq->txb);
280 txq->txb = NULL;
281 }
282
283 return -ENOMEM;
284}
285
6440adb5
CB		 286/**
287 * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
288 */
bb8c093b
CH		 289int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
290 struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
b481de9c
ZY		 291{
292 struct pci_dev *dev = priv->pci_dev;
293 int len;
294 int rc = 0;
295
6440adb5
CB		 296 /*
297 * Alloc buffer array for commands (Tx or other types of commands).
298 * For the command queue (#4), allocate command space + one big
299 * command for scan, since scan command is very huge; the system will
300 * not have two scans at the same time, so only one is needed.
301 * For data Tx queues (all other queues), no super-size command
302 * space is needed.
303 */
bb8c093b 304 len = sizeof(struct iwl3945_cmd) * slots_num;
b481de9c
ZY		 305 if (txq_id == IWL_CMD_QUEUE_NUM)
306 len += IWL_MAX_SCAN_SIZE;
307 txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
308 if (!txq->cmd)
309 return -ENOMEM;
310
6440adb5 311 /* Alloc driver data array and TFD circular buffer */
bb8c093b 312 rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
b481de9c
ZY		 313 if (rc) {
314 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
315
316 return -ENOMEM;
317 }
318 txq->need_update = 0;
319
320 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
c54b679d 321 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
b481de9c 322 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
6440adb5
CB		 323
324 /* Initialize queue high/low-water, head/tail indexes */
bb8c093b 325 iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
b481de9c 326
6440adb5 327 /* Tell device where to find queue, enable DMA channel. */
bb8c093b 328 iwl3945_hw_tx_queue_init(priv, txq);
b481de9c
ZY		 329
330 return 0;
331}
332
333/**
bb8c093b 334 * iwl3945_tx_queue_free - Deallocate DMA queue.
b481de9c
ZY		 335 * @txq: Transmit queue to deallocate.
336 *
337 * Empty queue by removing and destroying all BD's.
6440adb5
CB		 338 * Free all buffers.
339 * 0-fill, but do not free "txq" descriptor structure.
b481de9c 340 */
bb8c093b 341void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c 342{
bb8c093b 343 struct iwl3945_queue *q = &txq->q;
b481de9c
ZY		 344 struct pci_dev *dev = priv->pci_dev;
345 int len;
346
347 if (q->n_bd == 0)
348 return;
349
350 /* first, empty all BD's */
fc4b6853 351 for (; q->write_ptr != q->read_ptr;
c54b679d 352 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
bb8c093b 353 iwl3945_hw_txq_free_tfd(priv, txq);
b481de9c 354
bb8c093b 355 len = sizeof(struct iwl3945_cmd) * q->n_window;
b481de9c
ZY		 356 if (q->id == IWL_CMD_QUEUE_NUM)
357 len += IWL_MAX_SCAN_SIZE;
358
6440adb5 359 /* De-alloc array of command/tx buffers */
b481de9c
ZY		 360 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
361
6440adb5 362 /* De-alloc circular buffer of TFDs */
b481de9c 363 if (txq->q.n_bd)
bb8c093b 364 pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
b481de9c
ZY		 365 txq->q.n_bd, txq->bd, txq->q.dma_addr);
366
6440adb5 367 /* De-alloc array of per-TFD driver data */
b481de9c
ZY		 368 if (txq->txb) {
369 kfree(txq->txb);
370 txq->txb = NULL;
371 }
372
6440adb5 373 /* 0-fill queue descriptor structure */
b481de9c
ZY		 374 memset(txq, 0, sizeof(*txq));
375}
376
bb8c093b 377const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
b481de9c
ZY		 378
379/*************** STATION TABLE MANAGEMENT ****
9fbab516 380 * mac80211 should be examined to determine if sta_info is duplicating
b481de9c
ZY		 381 * the functionality provided here
382 */
383
384/**************************************************************/
01ebd063 385#if 0 /* temporary disable till we add real remove station */
6440adb5
CB		 386/**
387 * iwl3945_remove_station - Remove driver's knowledge of station.
388 *
389 * NOTE: This does not remove station from device's station table.
390 */
bb8c093b 391static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
b481de9c
ZY		 392{
393 int index = IWL_INVALID_STATION;
394 int i;
395 unsigned long flags;
396
397 spin_lock_irqsave(&priv->sta_lock, flags);
398
399 if (is_ap)
400 index = IWL_AP_ID;
401 else if (is_broadcast_ether_addr(addr))
402 index = priv->hw_setting.bcast_sta_id;
403 else
404 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
405 if (priv->stations[i].used &&
406 !compare_ether_addr(priv->stations[i].sta.sta.addr,
407 addr)) {
408 index = i;
409 break;
410 }
411
412 if (unlikely(index == IWL_INVALID_STATION))
413 goto out;
414
415 if (priv->stations[index].used) {
416 priv->stations[index].used = 0;
417 priv->num_stations--;
418 }
419
420 BUG_ON(priv->num_stations < 0);
421
422out:
423 spin_unlock_irqrestore(&priv->sta_lock, flags);
424 return 0;
425}
556f8db7 426#endif
6440adb5
CB		 427
428/**
429 * iwl3945_clear_stations_table - Clear the driver's station table
430 *
431 * NOTE: This does not clear or otherwise alter the device's station table.
432 */
bb8c093b 433static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
b481de9c
ZY		 434{
435 unsigned long flags;
436
437 spin_lock_irqsave(&priv->sta_lock, flags);
438
439 priv->num_stations = 0;
440 memset(priv->stations, 0, sizeof(priv->stations));
441
442 spin_unlock_irqrestore(&priv->sta_lock, flags);
443}
444
6440adb5
CB		 445/**
446 * iwl3945_add_station - Add station to station tables in driver and device
447 */
bb8c093b 448u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
b481de9c
ZY		 449{
450 int i;
451 int index = IWL_INVALID_STATION;
bb8c093b 452 struct iwl3945_station_entry *station;
b481de9c 453 unsigned long flags_spin;
0795af57 454 DECLARE_MAC_BUF(mac);
c14c521e 455 u8 rate;
b481de9c
ZY		 456
457 spin_lock_irqsave(&priv->sta_lock, flags_spin);
458 if (is_ap)
459 index = IWL_AP_ID;
460 else if (is_broadcast_ether_addr(addr))
461 index = priv->hw_setting.bcast_sta_id;
462 else
463 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
464 if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
465 addr)) {
466 index = i;
467 break;
468 }
469
470 if (!priv->stations[i].used &&
471 index == IWL_INVALID_STATION)
472 index = i;
473 }
474
01ebd063 475 /* These two conditions has the same outcome but keep them separate
b481de9c
ZY		 476 since they have different meaning */
477 if (unlikely(index == IWL_INVALID_STATION)) {
478 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
479 return index;
480 }
481
482 if (priv->stations[index].used &&
483 !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
484 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
485 return index;
486 }
487
0795af57 488 IWL_DEBUG_ASSOC("Add STA ID %d: %s\n", index, print_mac(mac, addr));
b481de9c
ZY		 489 station = &priv->stations[index];
490 station->used = 1;
491 priv->num_stations++;
492
6440adb5 493 /* Set up the REPLY_ADD_STA command to send to device */
bb8c093b 494 memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
b481de9c
ZY		 495 memcpy(station->sta.sta.addr, addr, ETH_ALEN);
496 station->sta.mode = 0;
497 station->sta.sta.sta_id = index;
498 station->sta.station_flags = 0;
499
8318d78a 500 if (priv->band == IEEE80211_BAND_5GHZ)
69946333
TW		 501 rate = IWL_RATE_6M_PLCP;
502 else
503 rate = IWL_RATE_1M_PLCP;
c14c521e
ZY		 504
505 /* Turn on both antennas for the station... */
506 station->sta.rate_n_flags =
bb8c093b 507 iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
c14c521e
ZY		 508 station->current_rate.rate_n_flags =
509 le16_to_cpu(station->sta.rate_n_flags);
510
b481de9c 511 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
6440adb5
CB		 512
513 /* Add station to device's station table */
bb8c093b 514 iwl3945_send_add_station(priv, &station->sta, flags);
b481de9c
ZY		 515 return index;
516
517}
518
519/*************** DRIVER STATUS FUNCTIONS *****/
520
bb8c093b 521static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
b481de9c
ZY		 522{
523 /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
524 * set but EXIT_PENDING is not */
525 return test_bit(STATUS_READY, &priv->status) &&
526 test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
527 !test_bit(STATUS_EXIT_PENDING, &priv->status);
528}
529
bb8c093b 530static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
b481de9c
ZY		 531{
532 return test_bit(STATUS_ALIVE, &priv->status);
533}
534
bb8c093b 535static inline int iwl3945_is_init(struct iwl3945_priv *priv)
b481de9c
ZY		 536{
537 return test_bit(STATUS_INIT, &priv->status);
538}
539
bb8c093b 540static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
b481de9c
ZY		 541{
542 return test_bit(STATUS_RF_KILL_HW, &priv->status) ||
543 test_bit(STATUS_RF_KILL_SW, &priv->status);
544}
545
bb8c093b 546static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
b481de9c
ZY		 547{
548
bb8c093b 549 if (iwl3945_is_rfkill(priv))
b481de9c
ZY		 550 return 0;
551
bb8c093b 552 return iwl3945_is_ready(priv);
b481de9c
ZY		 553}
554
555/*************** HOST COMMAND QUEUE FUNCTIONS *****/
556
557#define IWL_CMD(x) case x : return #x
558
559static const char *get_cmd_string(u8 cmd)
560{
561 switch (cmd) {
562 IWL_CMD(REPLY_ALIVE);
563 IWL_CMD(REPLY_ERROR);
564 IWL_CMD(REPLY_RXON);
565 IWL_CMD(REPLY_RXON_ASSOC);
566 IWL_CMD(REPLY_QOS_PARAM);
567 IWL_CMD(REPLY_RXON_TIMING);
568 IWL_CMD(REPLY_ADD_STA);
569 IWL_CMD(REPLY_REMOVE_STA);
570 IWL_CMD(REPLY_REMOVE_ALL_STA);
571 IWL_CMD(REPLY_3945_RX);
572 IWL_CMD(REPLY_TX);
573 IWL_CMD(REPLY_RATE_SCALE);
574 IWL_CMD(REPLY_LEDS_CMD);
575 IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
576 IWL_CMD(RADAR_NOTIFICATION);
577 IWL_CMD(REPLY_QUIET_CMD);
578 IWL_CMD(REPLY_CHANNEL_SWITCH);
579 IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
580 IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
581 IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
582 IWL_CMD(POWER_TABLE_CMD);
583 IWL_CMD(PM_SLEEP_NOTIFICATION);
584 IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
585 IWL_CMD(REPLY_SCAN_CMD);
586 IWL_CMD(REPLY_SCAN_ABORT_CMD);
587 IWL_CMD(SCAN_START_NOTIFICATION);
588 IWL_CMD(SCAN_RESULTS_NOTIFICATION);
589 IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
590 IWL_CMD(BEACON_NOTIFICATION);
591 IWL_CMD(REPLY_TX_BEACON);
592 IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
593 IWL_CMD(QUIET_NOTIFICATION);
594 IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
595 IWL_CMD(MEASURE_ABORT_NOTIFICATION);
596 IWL_CMD(REPLY_BT_CONFIG);
597 IWL_CMD(REPLY_STATISTICS_CMD);
598 IWL_CMD(STATISTICS_NOTIFICATION);
599 IWL_CMD(REPLY_CARD_STATE_CMD);
600 IWL_CMD(CARD_STATE_NOTIFICATION);
601 IWL_CMD(MISSED_BEACONS_NOTIFICATION);
602 default:
603 return "UNKNOWN";
604
605 }
606}
607
608#define HOST_COMPLETE_TIMEOUT (HZ / 2)
609
610/**
bb8c093b 611 * iwl3945_enqueue_hcmd - enqueue a uCode command
b481de9c
ZY		 612 * @priv: device private data point
613 * @cmd: a point to the ucode command structure
614 *
615 * The function returns < 0 values to indicate the operation is
616 * failed. On success, it turns the index (> 0) of command in the
617 * command queue.
618 */
bb8c093b 619static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c 620{
bb8c093b
CH		 621 struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
622 struct iwl3945_queue *q = &txq->q;
623 struct iwl3945_tfd_frame *tfd;
b481de9c 624 u32 *control_flags;
bb8c093b 625 struct iwl3945_cmd *out_cmd;
b481de9c
ZY		 626 u32 idx;
627 u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
628 dma_addr_t phys_addr;
629 int pad;
630 u16 count;
631 int ret;
632 unsigned long flags;
633
634 /* If any of the command structures end up being larger than
635 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
636 * we will need to increase the size of the TFD entries */
637 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
638 !(cmd->meta.flags & CMD_SIZE_HUGE));
639
c342a1b9
GG		 640
641 if (iwl3945_is_rfkill(priv)) {
642 IWL_DEBUG_INFO("Not sending command - RF KILL");
643 return -EIO;
644 }
645
bb8c093b 646 if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
b481de9c
ZY		 647 IWL_ERROR("No space for Tx\n");
648 return -ENOSPC;
649 }
650
651 spin_lock_irqsave(&priv->hcmd_lock, flags);
652
fc4b6853 653 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY		 654 memset(tfd, 0, sizeof(*tfd));
655
656 control_flags = (u32 *) tfd;
657
fc4b6853 658 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
b481de9c
ZY		 659 out_cmd = &txq->cmd[idx];
660
661 out_cmd->hdr.cmd = cmd->id;
662 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
663 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
664
665 /* At this point, the out_cmd now has all of the incoming cmd
666 * information */
667
668 out_cmd->hdr.flags = 0;
669 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
fc4b6853 670 INDEX_TO_SEQ(q->write_ptr));
b481de9c
ZY		 671 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
672 out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
673
674 phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
bb8c093b
CH		 675 offsetof(struct iwl3945_cmd, hdr);
676 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
b481de9c
ZY		 677
678 pad = U32_PAD(cmd->len);
679 count = TFD_CTL_COUNT_GET(*control_flags);
680 *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
681
682 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
683 "%d bytes at %d[%d]:%d\n",
684 get_cmd_string(out_cmd->hdr.cmd),
685 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
fc4b6853 686 fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
b481de9c
ZY		 687
688 txq->need_update = 1;
6440adb5
CB		 689
690 /* Increment and update queue's write index */
c54b679d 691 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
bb8c093b 692 ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 693
694 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
695 return ret ? ret : idx;
696}
697
bb8c093b 698static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c
ZY		 699{
700 int ret;
701
702 BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
703
704 /* An asynchronous command can not expect an SKB to be set. */
705 BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
706
707 /* An asynchronous command MUST have a callback. */
708 BUG_ON(!cmd->meta.u.callback);
709
710 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
711 return -EBUSY;
712
bb8c093b 713 ret = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c 714 if (ret < 0) {
bb8c093b 715 IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
b481de9c
ZY		 716 get_cmd_string(cmd->id), ret);
717 return ret;
718 }
719 return 0;
720}
721
bb8c093b 722static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c
ZY		 723{
724 int cmd_idx;
725 int ret;
b481de9c
ZY		 726
727 BUG_ON(cmd->meta.flags & CMD_ASYNC);
728
729 /* A synchronous command can not have a callback set. */
730 BUG_ON(cmd->meta.u.callback != NULL);
731
e5472978 732 if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) {
b481de9c
ZY		 733 IWL_ERROR("Error sending %s: Already sending a host command\n",
734 get_cmd_string(cmd->id));
e5472978
TW		 735 ret = -EBUSY;
736 goto out;
b481de9c
ZY		 737 }
738
739 set_bit(STATUS_HCMD_ACTIVE, &priv->status);
740
741 if (cmd->meta.flags & CMD_WANT_SKB)
742 cmd->meta.source = &cmd->meta;
743
bb8c093b 744 cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c
ZY		 745 if (cmd_idx < 0) {
746 ret = cmd_idx;
bb8c093b 747 IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
b481de9c
ZY		 748 get_cmd_string(cmd->id), ret);
749 goto out;
750 }
751
752 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
753 !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
754 HOST_COMPLETE_TIMEOUT);
755 if (!ret) {
756 if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
757 IWL_ERROR("Error sending %s: time out after %dms.\n",
758 get_cmd_string(cmd->id),
759 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
760
761 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
762 ret = -ETIMEDOUT;
763 goto cancel;
764 }
765 }
766
767 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
768 IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
769 get_cmd_string(cmd->id));
770 ret = -ECANCELED;
771 goto fail;
772 }
773 if (test_bit(STATUS_FW_ERROR, &priv->status)) {
774 IWL_DEBUG_INFO("Command %s failed: FW Error\n",
775 get_cmd_string(cmd->id));
776 ret = -EIO;
777 goto fail;
778 }
779 if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
780 IWL_ERROR("Error: Response NULL in '%s'\n",
781 get_cmd_string(cmd->id));
782 ret = -EIO;
783 goto out;
784 }
785
786 ret = 0;
787 goto out;
788
789cancel:
790 if (cmd->meta.flags & CMD_WANT_SKB) {
bb8c093b 791 struct iwl3945_cmd *qcmd;
b481de9c
ZY		 792
793 /* Cancel the CMD_WANT_SKB flag for the cmd in the
794 * TX cmd queue. Otherwise in case the cmd comes
795 * in later, it will possibly set an invalid
796 * address (cmd->meta.source). */
797 qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
798 qcmd->meta.flags &= ~CMD_WANT_SKB;
799 }
800fail:
801 if (cmd->meta.u.skb) {
802 dev_kfree_skb_any(cmd->meta.u.skb);
803 cmd->meta.u.skb = NULL;
804 }
805out:
e5472978 806 clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status);
b481de9c
ZY		 807 return ret;
808}
809
bb8c093b 810int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c 811{
b481de9c 812 if (cmd->meta.flags & CMD_ASYNC)
bb8c093b 813 return iwl3945_send_cmd_async(priv, cmd);
b481de9c 814
bb8c093b 815 return iwl3945_send_cmd_sync(priv, cmd);
b481de9c
ZY		 816}
817
bb8c093b 818int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
b481de9c 819{
bb8c093b 820 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 821 .id = id,
822 .len = len,
823 .data = data,
824 };
825
bb8c093b 826 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 827}
828
bb8c093b 829static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
b481de9c 830{
bb8c093b 831 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 832 .id = id,
833 .len = sizeof(val),
834 .data = &val,
835 };
836
bb8c093b 837 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 838}
839
bb8c093b 840int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
b481de9c 841{
bb8c093b 842 return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
b481de9c
ZY		 843}
844
b481de9c 845/**
bb8c093b 846 * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
8318d78a
JB		 847 * @band: 2.4 or 5 GHz band
848 * @channel: Any channel valid for the requested band
b481de9c 849
8318d78a 850 * In addition to setting the staging RXON, priv->band is also set.
b481de9c
ZY		 851 *
852 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
8318d78a 853 * in the staging RXON flag structure based on the band
b481de9c 854 */
8318d78a
JB		 855static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv,
856 enum ieee80211_band band,
857 u16 channel)
b481de9c 858{
8318d78a 859 if (!iwl3945_get_channel_info(priv, band, channel)) {
b481de9c 860 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
8318d78a 861 channel, band);
b481de9c
ZY		 862 return -EINVAL;
863 }
864
865 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
8318d78a 866 (priv->band == band))
b481de9c
ZY		 867 return 0;
868
869 priv->staging_rxon.channel = cpu_to_le16(channel);
8318d78a 870 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 871 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
872 else
873 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
874
8318d78a 875 priv->band = band;
b481de9c 876
8318d78a 877 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
b481de9c
ZY		 878
879 return 0;
880}
881
882/**
bb8c093b 883 * iwl3945_check_rxon_cmd - validate RXON structure is valid
b481de9c
ZY		 884 *
885 * NOTE: This is really only useful during development and can eventually
886 * be #ifdef'd out once the driver is stable and folks aren't actively
887 * making changes
888 */
bb8c093b 889static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon)
b481de9c
ZY		 890{
891 int error = 0;
892 int counter = 1;
893
894 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
895 error |= le32_to_cpu(rxon->flags &
896 (RXON_FLG_TGJ_NARROW_BAND_MSK |
897 RXON_FLG_RADAR_DETECT_MSK));
898 if (error)
899 IWL_WARNING("check 24G fields %d | %d\n",
900 counter++, error);
901 } else {
902 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
903 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
904 if (error)
905 IWL_WARNING("check 52 fields %d | %d\n",
906 counter++, error);
907 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
908 if (error)
909 IWL_WARNING("check 52 CCK %d | %d\n",
910 counter++, error);
911 }
912 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
913 if (error)
914 IWL_WARNING("check mac addr %d | %d\n", counter++, error);
915
916 /* make sure basic rates 6Mbps and 1Mbps are supported */
917 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
918 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
919 if (error)
920 IWL_WARNING("check basic rate %d | %d\n", counter++, error);
921
922 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
923 if (error)
924 IWL_WARNING("check assoc id %d | %d\n", counter++, error);
925
926 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
927 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
928 if (error)
929 IWL_WARNING("check CCK and short slot %d | %d\n",
930 counter++, error);
931
932 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
933 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
934 if (error)
935 IWL_WARNING("check CCK & auto detect %d | %d\n",
936 counter++, error);
937
938 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
939 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
940 if (error)
941 IWL_WARNING("check TGG and auto detect %d | %d\n",
942 counter++, error);
943
944 if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
945 error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
946 RXON_FLG_ANT_A_MSK)) == 0);
947 if (error)
948 IWL_WARNING("check antenna %d %d\n", counter++, error);
949
950 if (error)
951 IWL_WARNING("Tuning to channel %d\n",
952 le16_to_cpu(rxon->channel));
953
954 if (error) {
bb8c093b 955 IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
b481de9c
ZY		 956 return -1;
957 }
958 return 0;
959}
960
961/**
9fbab516 962 * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
01ebd063 963 * @priv: staging_rxon is compared to active_rxon
b481de9c 964 *
9fbab516
BC		 965 * If the RXON structure is changing enough to require a new tune,
966 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
967 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
b481de9c 968 */
bb8c093b 969static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
b481de9c
ZY		 970{
971
972 /* These items are only settable from the full RXON command */
973 if (!(priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ||
974 compare_ether_addr(priv->staging_rxon.bssid_addr,
975 priv->active_rxon.bssid_addr) ||
976 compare_ether_addr(priv->staging_rxon.node_addr,
977 priv->active_rxon.node_addr) ||
978 compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
979 priv->active_rxon.wlap_bssid_addr) ||
980 (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
981 (priv->staging_rxon.channel != priv->active_rxon.channel) ||
982 (priv->staging_rxon.air_propagation !=
983 priv->active_rxon.air_propagation) ||
984 (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
985 return 1;
986
987 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
988 * be updated with the RXON_ASSOC command -- however only some
989 * flag transitions are allowed using RXON_ASSOC */
990
991 /* Check if we are not switching bands */
992 if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
993 (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
994 return 1;
995
996 /* Check if we are switching association toggle */
997 if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
998 (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
999 return 1;
1000
1001 return 0;
1002}
1003
bb8c093b 1004static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
b481de9c
ZY		 1005{
1006 int rc = 0;
bb8c093b
CH		 1007 struct iwl3945_rx_packet *res = NULL;
1008 struct iwl3945_rxon_assoc_cmd rxon_assoc;
1009 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 1010 .id = REPLY_RXON_ASSOC,
1011 .len = sizeof(rxon_assoc),
1012 .meta.flags = CMD_WANT_SKB,
1013 .data = &rxon_assoc,
1014 };
bb8c093b
CH		 1015 const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
1016 const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
b481de9c
ZY		 1017
1018 if ((rxon1->flags == rxon2->flags) &&
1019 (rxon1->filter_flags == rxon2->filter_flags) &&
1020 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1021 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1022 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
1023 return 0;
1024 }
1025
1026 rxon_assoc.flags = priv->staging_rxon.flags;
1027 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1028 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1029 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1030 rxon_assoc.reserved = 0;
1031
bb8c093b 1032 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 1033 if (rc)
1034 return rc;
1035
bb8c093b 1036 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1037 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1038 IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
1039 rc = -EIO;
1040 }
1041
1042 priv->alloc_rxb_skb--;
1043 dev_kfree_skb_any(cmd.meta.u.skb);
1044
1045 return rc;
1046}
1047
1048/**
bb8c093b 1049 * iwl3945_commit_rxon - commit staging_rxon to hardware
b481de9c 1050 *
01ebd063 1051 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
ZY		 1052 * the active_rxon structure is updated with the new data. This
1053 * function correctly transitions out of the RXON_ASSOC_MSK state if
1054 * a HW tune is required based on the RXON structure changes.
1055 */
bb8c093b 1056static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
b481de9c
ZY		 1057{
1058 /* cast away the const for active_rxon in this function */
bb8c093b 1059 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
b481de9c 1060 int rc = 0;
0795af57 1061 DECLARE_MAC_BUF(mac);
b481de9c 1062
bb8c093b 1063 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 1064 return -1;
1065
1066 /* always get timestamp with Rx frame */
1067 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
1068
1069 /* select antenna */
1070 priv->staging_rxon.flags &=
1071 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1072 priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
1073
bb8c093b 1074 rc = iwl3945_check_rxon_cmd(&priv->staging_rxon);
b481de9c
ZY		 1075 if (rc) {
1076 IWL_ERROR("Invalid RXON configuration. Not committing.\n");
1077 return -EINVAL;
1078 }
1079
1080 /* If we don't need to send a full RXON, we can use
bb8c093b 1081 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 1082 * and other flags for the current radio configuration. */
bb8c093b
CH		 1083 if (!iwl3945_full_rxon_required(priv)) {
1084 rc = iwl3945_send_rxon_assoc(priv);
b481de9c
ZY		 1085 if (rc) {
1086 IWL_ERROR("Error setting RXON_ASSOC "
1087 "configuration (%d).\n", rc);
1088 return rc;
1089 }
1090
1091 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1092
1093 return 0;
1094 }
1095
1096 /* If we are currently associated and the new config requires
1097 * an RXON_ASSOC and the new config wants the associated mask enabled,
1098 * we must clear the associated from the active configuration
1099 * before we apply the new config */
bb8c093b 1100 if (iwl3945_is_associated(priv) &&
b481de9c
ZY		 1101 (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
1102 IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
1103 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1104
bb8c093b
CH		 1105 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
1106 sizeof(struct iwl3945_rxon_cmd),
b481de9c
ZY		 1107 &priv->active_rxon);
1108
1109 /* If the mask clearing failed then we set
1110 * active_rxon back to what it was previously */
1111 if (rc) {
1112 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1113 IWL_ERROR("Error clearing ASSOC_MSK on current "
1114 "configuration (%d).\n", rc);
1115 return rc;
1116 }
b481de9c
ZY		 1117 }
1118
1119 IWL_DEBUG_INFO("Sending RXON\n"
1120 "* with%s RXON_FILTER_ASSOC_MSK\n"
1121 "* channel = %d\n"
0795af57 1122 "* bssid = %s\n",
b481de9c
ZY		 1123 ((priv->staging_rxon.filter_flags &
1124 RXON_FILTER_ASSOC_MSK) ? "" : "out"),
1125 le16_to_cpu(priv->staging_rxon.channel),
0795af57 1126 print_mac(mac, priv->staging_rxon.bssid_addr));
b481de9c
ZY		 1127
1128 /* Apply the new configuration */
bb8c093b
CH		 1129 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
1130 sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
b481de9c
ZY		 1131 if (rc) {
1132 IWL_ERROR("Error setting new configuration (%d).\n", rc);
1133 return rc;
1134 }
1135
1136 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1137
bb8c093b 1138 iwl3945_clear_stations_table(priv);
556f8db7 1139
b481de9c
ZY		 1140 /* If we issue a new RXON command which required a tune then we must
1141 * send a new TXPOWER command or we won't be able to Tx any frames */
bb8c093b 1142 rc = iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 1143 if (rc) {
1144 IWL_ERROR("Error setting Tx power (%d).\n", rc);
1145 return rc;
1146 }
1147
1148 /* Add the broadcast address so we can send broadcast frames */
bb8c093b 1149 if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
b481de9c
ZY		 1150 IWL_INVALID_STATION) {
1151 IWL_ERROR("Error adding BROADCAST address for transmit.\n");
1152 return -EIO;
1153 }
1154
1155 /* If we have set the ASSOC_MSK and we are in BSS mode then
1156 * add the IWL_AP_ID to the station rate table */
bb8c093b 1157 if (iwl3945_is_associated(priv) &&
b481de9c 1158 (priv->iw_mode == IEEE80211_IF_TYPE_STA))
bb8c093b 1159 if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
b481de9c
ZY		 1160 == IWL_INVALID_STATION) {
1161 IWL_ERROR("Error adding AP address for transmit.\n");
1162 return -EIO;
1163 }
1164
8318d78a 1165 /* Init the hardware's rate fallback order based on the band */
b481de9c
ZY		 1166 rc = iwl3945_init_hw_rate_table(priv);
1167 if (rc) {
1168 IWL_ERROR("Error setting HW rate table: %02X\n", rc);
1169 return -EIO;
1170 }
1171
1172 return 0;
1173}
1174
bb8c093b 1175static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
b481de9c 1176{
bb8c093b 1177 struct iwl3945_bt_cmd bt_cmd = {
b481de9c
ZY		 1178 .flags = 3,
1179 .lead_time = 0xAA,
1180 .max_kill = 1,
1181 .kill_ack_mask = 0,
1182 .kill_cts_mask = 0,
1183 };
1184
bb8c093b
CH		 1185 return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1186 sizeof(struct iwl3945_bt_cmd), &bt_cmd);
b481de9c
ZY		 1187}
1188
bb8c093b 1189static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
b481de9c
ZY		 1190{
1191 int rc = 0;
bb8c093b
CH		 1192 struct iwl3945_rx_packet *res;
1193 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 1194 .id = REPLY_SCAN_ABORT_CMD,
1195 .meta.flags = CMD_WANT_SKB,
1196 };
1197
1198 /* If there isn't a scan actively going on in the hardware
1199 * then we are in between scan bands and not actually
1200 * actively scanning, so don't send the abort command */
1201 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
1202 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1203 return 0;
1204 }
1205
bb8c093b 1206 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 1207 if (rc) {
1208 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1209 return rc;
1210 }
1211
bb8c093b 1212 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1213 if (res->u.status != CAN_ABORT_STATUS) {
1214 /* The scan abort will return 1 for success or
1215 * 2 for "failure". A failure condition can be
1216 * due to simply not being in an active scan which
1217 * can occur if we send the scan abort before we
1218 * the microcode has notified us that a scan is
1219 * completed. */
1220 IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
1221 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1222 clear_bit(STATUS_SCAN_HW, &priv->status);
1223 }
1224
1225 dev_kfree_skb_any(cmd.meta.u.skb);
1226
1227 return rc;
1228}
1229
bb8c093b
CH		 1230static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
1231 struct iwl3945_cmd *cmd,
b481de9c
ZY		 1232 struct sk_buff *skb)
1233{
1234 return 1;
1235}
1236
1237/*
1238 * CARD_STATE_CMD
1239 *
9fbab516 1240 * Use: Sets the device's internal card state to enable, disable, or halt
b481de9c
ZY		 1241 *
1242 * When in the 'enable' state the card operates as normal.
1243 * When in the 'disable' state, the card enters into a low power mode.
1244 * When in the 'halt' state, the card is shut down and must be fully
1245 * restarted to come back on.
1246 */
bb8c093b 1247static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
b481de9c 1248{
bb8c093b 1249 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 1250 .id = REPLY_CARD_STATE_CMD,
1251 .len = sizeof(u32),
1252 .data = &flags,
1253 .meta.flags = meta_flag,
1254 };
1255
1256 if (meta_flag & CMD_ASYNC)
bb8c093b 1257 cmd.meta.u.callback = iwl3945_card_state_sync_callback;
b481de9c 1258
bb8c093b 1259 return iwl3945_send_cmd(priv, &cmd);
b481de9c
ZY		 1260}
1261
bb8c093b
CH		 1262static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
1263 struct iwl3945_cmd *cmd, struct sk_buff *skb)
b481de9c 1264{
bb8c093b 1265 struct iwl3945_rx_packet *res = NULL;
b481de9c
ZY		 1266
1267 if (!skb) {
1268 IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
1269 return 1;
1270 }
1271
bb8c093b 1272 res = (struct iwl3945_rx_packet *)skb->data;
b481de9c
ZY		 1273 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1274 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1275 res->hdr.flags);
1276 return 1;
1277 }
1278
1279 switch (res->u.add_sta.status) {
1280 case ADD_STA_SUCCESS_MSK:
1281 break;
1282 default:
1283 break;
1284 }
1285
1286 /* We didn't cache the SKB; let the caller free it */
1287 return 1;
1288}
1289
bb8c093b
CH		 1290int iwl3945_send_add_station(struct iwl3945_priv *priv,
1291 struct iwl3945_addsta_cmd *sta, u8 flags)
b481de9c 1292{
bb8c093b 1293 struct iwl3945_rx_packet *res = NULL;
b481de9c 1294 int rc = 0;
bb8c093b 1295 struct iwl3945_host_cmd cmd = {
b481de9c 1296 .id = REPLY_ADD_STA,
bb8c093b 1297 .len = sizeof(struct iwl3945_addsta_cmd),
b481de9c
ZY		 1298 .meta.flags = flags,
1299 .data = sta,
1300 };
1301
1302 if (flags & CMD_ASYNC)
bb8c093b 1303 cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
b481de9c
ZY		 1304 else
1305 cmd.meta.flags |= CMD_WANT_SKB;
1306
bb8c093b 1307 rc = iwl3945_send_cmd(priv, &cmd);
b481de9c
ZY		 1308
1309 if (rc || (flags & CMD_ASYNC))
1310 return rc;
1311
bb8c093b 1312 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1313 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1314 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1315 res->hdr.flags);
1316 rc = -EIO;
1317 }
1318
1319 if (rc == 0) {
1320 switch (res->u.add_sta.status) {
1321 case ADD_STA_SUCCESS_MSK:
1322 IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
1323 break;
1324 default:
1325 rc = -EIO;
1326 IWL_WARNING("REPLY_ADD_STA failed\n");
1327 break;
1328 }
1329 }
1330
1331 priv->alloc_rxb_skb--;
1332 dev_kfree_skb_any(cmd.meta.u.skb);
1333
1334 return rc;
1335}
1336
bb8c093b 1337static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
b481de9c
ZY		 1338 struct ieee80211_key_conf *keyconf,
1339 u8 sta_id)
1340{
1341 unsigned long flags;
1342 __le16 key_flags = 0;
1343
1344 switch (keyconf->alg) {
1345 case ALG_CCMP:
1346 key_flags |= STA_KEY_FLG_CCMP;
1347 key_flags |= cpu_to_le16(
1348 keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
1349 key_flags &= ~STA_KEY_FLG_INVALID;
1350 break;
1351 case ALG_TKIP:
1352 case ALG_WEP:
b481de9c
ZY		 1353 default:
1354 return -EINVAL;
1355 }
1356 spin_lock_irqsave(&priv->sta_lock, flags);
1357 priv->stations[sta_id].keyinfo.alg = keyconf->alg;
1358 priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
1359 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
1360 keyconf->keylen);
1361
1362 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
1363 keyconf->keylen);
1364 priv->stations[sta_id].sta.key.key_flags = key_flags;
1365 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1366 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1367
1368 spin_unlock_irqrestore(&priv->sta_lock, flags);
1369
1370 IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
bb8c093b 1371 iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY		 1372 return 0;
1373}
1374
bb8c093b 1375static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
b481de9c
ZY		 1376{
1377 unsigned long flags;
1378
1379 spin_lock_irqsave(&priv->sta_lock, flags);
bb8c093b
CH		 1380 memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
1381 memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl3945_keyinfo));
b481de9c
ZY		 1382 priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
1383 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1384 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1385 spin_unlock_irqrestore(&priv->sta_lock, flags);
1386
1387 IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
bb8c093b 1388 iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY		 1389 return 0;
1390}
1391
bb8c093b 1392static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
b481de9c
ZY		 1393{
1394 struct list_head *element;
1395
1396 IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
1397 priv->frames_count);
1398
1399 while (!list_empty(&priv->free_frames)) {
1400 element = priv->free_frames.next;
1401 list_del(element);
bb8c093b 1402 kfree(list_entry(element, struct iwl3945_frame, list));
b481de9c
ZY		 1403 priv->frames_count--;
1404 }
1405
1406 if (priv->frames_count) {
1407 IWL_WARNING("%d frames still in use. Did we lose one?\n",
1408 priv->frames_count);
1409 priv->frames_count = 0;
1410 }
1411}
1412
bb8c093b 1413static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
b481de9c 1414{
bb8c093b 1415 struct iwl3945_frame *frame;
b481de9c
ZY		 1416 struct list_head *element;
1417 if (list_empty(&priv->free_frames)) {
1418 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
1419 if (!frame) {
1420 IWL_ERROR("Could not allocate frame!\n");
1421 return NULL;
1422 }
1423
1424 priv->frames_count++;
1425 return frame;
1426 }
1427
1428 element = priv->free_frames.next;
1429 list_del(element);
bb8c093b 1430 return list_entry(element, struct iwl3945_frame, list);
b481de9c
ZY		 1431}
1432
bb8c093b 1433static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
b481de9c
ZY		 1434{
1435 memset(frame, 0, sizeof(*frame));
1436 list_add(&frame->list, &priv->free_frames);
1437}
1438
bb8c093b 1439unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
b481de9c
ZY		 1440 struct ieee80211_hdr *hdr,
1441 const u8 *dest, int left)
1442{
1443
bb8c093b 1444 if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
b481de9c
ZY		 1445 ((priv->iw_mode != IEEE80211_IF_TYPE_IBSS) &&
1446 (priv->iw_mode != IEEE80211_IF_TYPE_AP)))
1447 return 0;
1448
1449 if (priv->ibss_beacon->len > left)
1450 return 0;
1451
1452 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
1453
1454 return priv->ibss_beacon->len;
1455}
1456
bb8c093b 1457static u8 iwl3945_rate_get_lowest_plcp(int rate_mask)
b481de9c
ZY		 1458{
1459 u8 i;
1460
1461 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
bb8c093b 1462 i = iwl3945_rates[i].next_ieee) {
b481de9c 1463 if (rate_mask & (1 << i))
bb8c093b 1464 return iwl3945_rates[i].plcp;
b481de9c
ZY		 1465 }
1466
1467 return IWL_RATE_INVALID;
1468}
1469
bb8c093b 1470static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
b481de9c 1471{
bb8c093b 1472 struct iwl3945_frame *frame;
b481de9c
ZY		 1473 unsigned int frame_size;
1474 int rc;
1475 u8 rate;
1476
bb8c093b 1477 frame = iwl3945_get_free_frame(priv);
b481de9c
ZY		 1478
1479 if (!frame) {
1480 IWL_ERROR("Could not obtain free frame buffer for beacon "
1481 "command.\n");
1482 return -ENOMEM;
1483 }
1484
1485 if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) {
bb8c093b 1486 rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic &
b481de9c
ZY		 1487 0xFF0);
1488 if (rate == IWL_INVALID_RATE)
1489 rate = IWL_RATE_6M_PLCP;
1490 } else {
bb8c093b 1491 rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic & 0xF);
b481de9c
ZY		 1492 if (rate == IWL_INVALID_RATE)
1493 rate = IWL_RATE_1M_PLCP;
1494 }
1495
bb8c093b 1496 frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 1497
bb8c093b 1498 rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY		 1499 &frame->u.cmd[0]);
1500
bb8c093b 1501 iwl3945_free_frame(priv, frame);
b481de9c
ZY		 1502
1503 return rc;
1504}
1505
1506/******************************************************************************
1507 *
1508 * EEPROM related functions
1509 *
1510 ******************************************************************************/
1511
bb8c093b 1512static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
b481de9c
ZY		 1513{
1514 memcpy(mac, priv->eeprom.mac_address, 6);
1515}
1516
74a3a250
RC		 1517/*
1518 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
1519 * embedded controller) as EEPROM reader; each read is a series of pulses
1520 * to/from the EEPROM chip, not a single event, so even reads could conflict
1521 * if they weren't arbitrated by some ownership mechanism. Here, the driver
1522 * simply claims ownership, which should be safe when this function is called
1523 * (i.e. before loading uCode!).
1524 */
1525static inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv)
1526{
1527 _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
1528 return 0;
1529}
1530
b481de9c 1531/**
bb8c093b 1532 * iwl3945_eeprom_init - read EEPROM contents
b481de9c 1533 *
6440adb5 1534 * Load the EEPROM contents from adapter into priv->eeprom
b481de9c
ZY		 1535 *
1536 * NOTE: This routine uses the non-debug IO access functions.
1537 */
bb8c093b 1538int iwl3945_eeprom_init(struct iwl3945_priv *priv)
b481de9c 1539{
58ff6d4d 1540 u16 *e = (u16 *)&priv->eeprom;
bb8c093b 1541 u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
b481de9c
ZY		 1542 u32 r;
1543 int sz = sizeof(priv->eeprom);
1544 int rc;
1545 int i;
1546 u16 addr;
1547
1548 /* The EEPROM structure has several padding buffers within it
1549 * and when adding new EEPROM maps is subject to programmer errors
1550 * which may be very difficult to identify without explicitly
1551 * checking the resulting size of the eeprom map. */
1552 BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
1553
1554 if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
1555 IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp);
1556 return -ENOENT;
1557 }
1558
6440adb5 1559 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
bb8c093b 1560 rc = iwl3945_eeprom_acquire_semaphore(priv);
b481de9c 1561 if (rc < 0) {
91e17473 1562 IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
b481de9c
ZY		 1563 return -ENOENT;
1564 }
1565
1566 /* eeprom is an array of 16bit values */
1567 for (addr = 0; addr < sz; addr += sizeof(u16)) {
bb8c093b
CH		 1568 _iwl3945_write32(priv, CSR_EEPROM_REG, addr << 1);
1569 _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
b481de9c
ZY		 1570
1571 for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
1572 i += IWL_EEPROM_ACCESS_DELAY) {
bb8c093b 1573 r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
b481de9c
ZY		 1574 if (r & CSR_EEPROM_REG_READ_VALID_MSK)
1575 break;
1576 udelay(IWL_EEPROM_ACCESS_DELAY);
1577 }
1578
1579 if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) {
1580 IWL_ERROR("Time out reading EEPROM[%d]", addr);
1581 return -ETIMEDOUT;
1582 }
58ff6d4d 1583 e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
b481de9c
ZY		 1584 }
1585
1586 return 0;
1587}
1588
bb8c093b 1589static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
b481de9c
ZY		 1590{
1591 if (priv->hw_setting.shared_virt)
1592 pci_free_consistent(priv->pci_dev,
bb8c093b 1593 sizeof(struct iwl3945_shared),
b481de9c
ZY		 1594 priv->hw_setting.shared_virt,
1595 priv->hw_setting.shared_phys);
1596}
1597
1598/**
bb8c093b 1599 * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
b481de9c
ZY		 1600 *
1601 * return : set the bit for each supported rate insert in ie
1602 */
bb8c093b 1603static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
c7c46676 1604 u16 basic_rate, int *left)
b481de9c
ZY		 1605{
1606 u16 ret_rates = 0, bit;
1607 int i;
c7c46676
TW		 1608 u8 *cnt = ie;
1609 u8 *rates = ie + 1;
b481de9c
ZY		 1610
1611 for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
1612 if (bit & supported_rate) {
1613 ret_rates |= bit;
bb8c093b 1614 rates[*cnt] = iwl3945_rates[i].ieee |
c7c46676
TW		 1615 ((bit & basic_rate) ? 0x80 : 0x00);
1616 (*cnt)++;
1617 (*left)--;
1618 if ((*left <= 0) ||
1619 (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
b481de9c
ZY		 1620 break;
1621 }
1622 }
1623
1624 return ret_rates;
1625}
1626
1627/**
bb8c093b 1628 * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
b481de9c 1629 */
bb8c093b 1630static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
b481de9c
ZY		 1631 struct ieee80211_mgmt *frame,
1632 int left, int is_direct)
1633{
1634 int len = 0;
1635 u8 *pos = NULL;
c7c46676 1636 u16 active_rates, ret_rates, cck_rates;
b481de9c
ZY		 1637
1638 /* Make sure there is enough space for the probe request,
1639 * two mandatory IEs and the data */
1640 left -= 24;
1641 if (left < 0)
1642 return 0;
1643 len += 24;
1644
1645 frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
bb8c093b 1646 memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
b481de9c 1647 memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
bb8c093b 1648 memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
b481de9c
ZY		 1649 frame->seq_ctrl = 0;
1650
1651 /* fill in our indirect SSID IE */
1652 /* ...next IE... */
1653
1654 left -= 2;
1655 if (left < 0)
1656 return 0;
1657 len += 2;
1658 pos = &(frame->u.probe_req.variable[0]);
1659 *pos++ = WLAN_EID_SSID;
1660 *pos++ = 0;
1661
1662 /* fill in our direct SSID IE... */
1663 if (is_direct) {
1664 /* ...next IE... */
1665 left -= 2 + priv->essid_len;
1666 if (left < 0)
1667 return 0;
1668 /* ... fill it in... */
1669 *pos++ = WLAN_EID_SSID;
1670 *pos++ = priv->essid_len;
1671 memcpy(pos, priv->essid, priv->essid_len);
1672 pos += priv->essid_len;
1673 len += 2 + priv->essid_len;
1674 }
1675
1676 /* fill in supported rate */
1677 /* ...next IE... */
1678 left -= 2;
1679 if (left < 0)
1680 return 0;
c7c46676 1681
b481de9c
ZY		 1682 /* ... fill it in... */
1683 *pos++ = WLAN_EID_SUPP_RATES;
1684 *pos = 0;
c7c46676
TW		 1685
1686 priv->active_rate = priv->rates_mask;
1687 active_rates = priv->active_rate;
b481de9c
ZY		 1688 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1689
c7c46676 1690 cck_rates = IWL_CCK_RATES_MASK & active_rates;
bb8c093b 1691 ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
c7c46676
TW		 1692 priv->active_rate_basic, &left);
1693 active_rates &= ~ret_rates;
1694
bb8c093b 1695 ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676
TW		 1696 priv->active_rate_basic, &left);
1697 active_rates &= ~ret_rates;
1698
b481de9c
ZY		 1699 len += 2 + *pos;
1700 pos += (*pos) + 1;
c7c46676 1701 if (active_rates == 0)
b481de9c
ZY		 1702 goto fill_end;
1703
1704 /* fill in supported extended rate */
1705 /* ...next IE... */
1706 left -= 2;
1707 if (left < 0)
1708 return 0;
1709 /* ... fill it in... */
1710 *pos++ = WLAN_EID_EXT_SUPP_RATES;
1711 *pos = 0;
bb8c093b 1712 iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676 1713 priv->active_rate_basic, &left);
b481de9c
ZY		 1714 if (*pos > 0)
1715 len += 2 + *pos;
1716
1717 fill_end:
1718 return (u16)len;
1719}
1720
1721/*
1722 * QoS support
1723*/
bb8c093b
CH		 1724static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
1725 struct iwl3945_qosparam_cmd *qos)
b481de9c
ZY		 1726{
1727
bb8c093b
CH		 1728 return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
1729 sizeof(struct iwl3945_qosparam_cmd), qos);
b481de9c
ZY		 1730}
1731
bb8c093b 1732static void iwl3945_reset_qos(struct iwl3945_priv *priv)
b481de9c
ZY		 1733{
1734 u16 cw_min = 15;
1735 u16 cw_max = 1023;
1736 u8 aifs = 2;
1737 u8 is_legacy = 0;
1738 unsigned long flags;
1739 int i;
1740
1741 spin_lock_irqsave(&priv->lock, flags);
1742 priv->qos_data.qos_active = 0;
1743
1744 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
1745 if (priv->qos_data.qos_enable)
1746 priv->qos_data.qos_active = 1;
1747 if (!(priv->active_rate & 0xfff0)) {
1748 cw_min = 31;
1749 is_legacy = 1;
1750 }
1751 } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
1752 if (priv->qos_data.qos_enable)
1753 priv->qos_data.qos_active = 1;
1754 } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
1755 cw_min = 31;
1756 is_legacy = 1;
1757 }
1758
1759 if (priv->qos_data.qos_active)
1760 aifs = 3;
1761
1762 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
1763 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
1764 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
1765 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
1766 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
1767
1768 if (priv->qos_data.qos_active) {
1769 i = 1;
1770 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
1771 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
1772 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
1773 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
1774 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1775
1776 i = 2;
1777 priv->qos_data.def_qos_parm.ac[i].cw_min =
1778 cpu_to_le16((cw_min + 1) / 2 - 1);
1779 priv->qos_data.def_qos_parm.ac[i].cw_max =
1780 cpu_to_le16(cw_max);
1781 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1782 if (is_legacy)
1783 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1784 cpu_to_le16(6016);
1785 else
1786 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1787 cpu_to_le16(3008);
1788 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1789
1790 i = 3;
1791 priv->qos_data.def_qos_parm.ac[i].cw_min =
1792 cpu_to_le16((cw_min + 1) / 4 - 1);
1793 priv->qos_data.def_qos_parm.ac[i].cw_max =
1794 cpu_to_le16((cw_max + 1) / 2 - 1);
1795 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1796 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1797 if (is_legacy)
1798 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1799 cpu_to_le16(3264);
1800 else
1801 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1802 cpu_to_le16(1504);
1803 } else {
1804 for (i = 1; i < 4; i++) {
1805 priv->qos_data.def_qos_parm.ac[i].cw_min =
1806 cpu_to_le16(cw_min);
1807 priv->qos_data.def_qos_parm.ac[i].cw_max =
1808 cpu_to_le16(cw_max);
1809 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
1810 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
1811 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1812 }
1813 }
1814 IWL_DEBUG_QOS("set QoS to default \n");
1815
1816 spin_unlock_irqrestore(&priv->lock, flags);
1817}
1818
bb8c093b 1819static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
b481de9c
ZY		 1820{
1821 unsigned long flags;
1822
b481de9c
ZY		 1823 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1824 return;
1825
1826 if (!priv->qos_data.qos_enable)
1827 return;
1828
1829 spin_lock_irqsave(&priv->lock, flags);
1830 priv->qos_data.def_qos_parm.qos_flags = 0;
1831
1832 if (priv->qos_data.qos_cap.q_AP.queue_request &&
1833 !priv->qos_data.qos_cap.q_AP.txop_request)
1834 priv->qos_data.def_qos_parm.qos_flags |=
1835 QOS_PARAM_FLG_TXOP_TYPE_MSK;
1836
1837 if (priv->qos_data.qos_active)
1838 priv->qos_data.def_qos_parm.qos_flags |=
1839 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
1840
1841 spin_unlock_irqrestore(&priv->lock, flags);
1842
bb8c093b 1843 if (force || iwl3945_is_associated(priv)) {
b481de9c
ZY		 1844 IWL_DEBUG_QOS("send QoS cmd with Qos active %d \n",
1845 priv->qos_data.qos_active);
1846
bb8c093b 1847 iwl3945_send_qos_params_command(priv,
b481de9c
ZY		 1848 &(priv->qos_data.def_qos_parm));
1849 }
1850}
1851
b481de9c
ZY		 1852/*
1853 * Power management (not Tx power!) functions
1854 */
1855#define MSEC_TO_USEC 1024
1856
1857#define NOSLP __constant_cpu_to_le32(0)
1858#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK
1859#define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
1860#define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
1861 __constant_cpu_to_le32(X1), \
1862 __constant_cpu_to_le32(X2), \
1863 __constant_cpu_to_le32(X3), \
1864 __constant_cpu_to_le32(X4)}
1865
1866
1867/* default power management (not Tx power) table values */
1868/* for tim 0-10 */
bb8c093b 1869static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = {
b481de9c
ZY		 1870 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1871 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
1872 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
1873 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
1874 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
1875 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
1876};
1877
1878/* for tim > 10 */
bb8c093b 1879static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = {
b481de9c
ZY		 1880 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1881 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
1882 SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
1883 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
1884 SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
1885 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
1886 SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
1887 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
1888 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
1889 SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
1890};
1891
bb8c093b 1892int iwl3945_power_init_handle(struct iwl3945_priv *priv)
b481de9c
ZY		 1893{
1894 int rc = 0, i;
bb8c093b
CH		 1895 struct iwl3945_power_mgr *pow_data;
1896 int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC;
b481de9c
ZY		 1897 u16 pci_pm;
1898
1899 IWL_DEBUG_POWER("Initialize power \n");
1900
1901 pow_data = &(priv->power_data);
1902
1903 memset(pow_data, 0, sizeof(*pow_data));
1904
1905 pow_data->active_index = IWL_POWER_RANGE_0;
1906 pow_data->dtim_val = 0xffff;
1907
1908 memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
1909 memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
1910
1911 rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
1912 if (rc != 0)
1913 return 0;
1914 else {
bb8c093b 1915 struct iwl3945_powertable_cmd *cmd;
b481de9c
ZY		 1916
1917 IWL_DEBUG_POWER("adjust power command flags\n");
1918
1919 for (i = 0; i < IWL_POWER_AC; i++) {
1920 cmd = &pow_data->pwr_range_0[i].cmd;
1921
1922 if (pci_pm & 0x1)
1923 cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
1924 else
1925 cmd->flags |= IWL_POWER_PCI_PM_MSK;
1926 }
1927 }
1928 return rc;
1929}
1930
bb8c093b
CH		 1931static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
1932 struct iwl3945_powertable_cmd *cmd, u32 mode)
b481de9c
ZY		 1933{
1934 int rc = 0, i;
1935 u8 skip;
1936 u32 max_sleep = 0;
bb8c093b 1937 struct iwl3945_power_vec_entry *range;
b481de9c 1938 u8 period = 0;
bb8c093b 1939 struct iwl3945_power_mgr *pow_data;
b481de9c
ZY		 1940
1941 if (mode > IWL_POWER_INDEX_5) {
1942 IWL_DEBUG_POWER("Error invalid power mode \n");
1943 return -1;
1944 }
1945 pow_data = &(priv->power_data);
1946
1947 if (pow_data->active_index == IWL_POWER_RANGE_0)
1948 range = &pow_data->pwr_range_0[0];
1949 else
1950 range = &pow_data->pwr_range_1[1];
1951
bb8c093b 1952 memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
b481de9c
ZY		 1953
1954#ifdef IWL_MAC80211_DISABLE
1955 if (priv->assoc_network != NULL) {
1956 unsigned long flags;
1957
1958 period = priv->assoc_network->tim.tim_period;
1959 }
1960#endif /*IWL_MAC80211_DISABLE */
1961 skip = range[mode].no_dtim;
1962
1963 if (period == 0) {
1964 period = 1;
1965 skip = 0;
1966 }
1967
1968 if (skip == 0) {
1969 max_sleep = period;
1970 cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
1971 } else {
1972 __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
1973 max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
1974 cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
1975 }
1976
1977 for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
1978 if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
1979 cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
1980 }
1981
1982 IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
1983 IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
1984 IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
1985 IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
1986 le32_to_cpu(cmd->sleep_interval[0]),
1987 le32_to_cpu(cmd->sleep_interval[1]),
1988 le32_to_cpu(cmd->sleep_interval[2]),
1989 le32_to_cpu(cmd->sleep_interval[3]),
1990 le32_to_cpu(cmd->sleep_interval[4]));
1991
1992 return rc;
1993}
1994
bb8c093b 1995static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
b481de9c 1996{
9a62f73b 1997 u32 uninitialized_var(final_mode);
b481de9c 1998 int rc;
bb8c093b 1999 struct iwl3945_powertable_cmd cmd;
b481de9c
ZY		 2000
2001 /* If on battery, set to 3,
01ebd063 2002 * if plugged into AC power, set to CAM ("continuously aware mode"),
b481de9c
ZY		 2003 * else user level */
2004 switch (mode) {
2005 case IWL_POWER_BATTERY:
2006 final_mode = IWL_POWER_INDEX_3;
2007 break;
2008 case IWL_POWER_AC:
2009 final_mode = IWL_POWER_MODE_CAM;
2010 break;
2011 default:
2012 final_mode = mode;
2013 break;
2014 }
2015
bb8c093b 2016 iwl3945_update_power_cmd(priv, &cmd, final_mode);
b481de9c 2017
bb8c093b 2018 rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
b481de9c
ZY		 2019
2020 if (final_mode == IWL_POWER_MODE_CAM)
2021 clear_bit(STATUS_POWER_PMI, &priv->status);
2022 else
2023 set_bit(STATUS_POWER_PMI, &priv->status);
2024
2025 return rc;
2026}
2027
bb8c093b 2028int iwl3945_is_network_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
b481de9c
ZY		 2029{
2030 /* Filter incoming packets to determine if they are targeted toward
2031 * this network, discarding packets coming from ourselves */
2032 switch (priv->iw_mode) {
2033 case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */
2034 /* packets from our adapter are dropped (echo) */
2035 if (!compare_ether_addr(header->addr2, priv->mac_addr))
2036 return 0;
2037 /* {broad,multi}cast packets to our IBSS go through */
2038 if (is_multicast_ether_addr(header->addr1))
2039 return !compare_ether_addr(header->addr3, priv->bssid);
2040 /* packets to our adapter go through */
2041 return !compare_ether_addr(header->addr1, priv->mac_addr);
2042 case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */
2043 /* packets from our adapter are dropped (echo) */
2044 if (!compare_ether_addr(header->addr3, priv->mac_addr))
2045 return 0;
2046 /* {broad,multi}cast packets to our BSS go through */
2047 if (is_multicast_ether_addr(header->addr1))
2048 return !compare_ether_addr(header->addr2, priv->bssid);
2049 /* packets to our adapter go through */
2050 return !compare_ether_addr(header->addr1, priv->mac_addr);
69dc5d9d
TW		 2051 default:
2052 return 1;
b481de9c
ZY		 2053 }
2054
2055 return 1;
2056}
2057
b481de9c 2058/**
bb8c093b 2059 * iwl3945_scan_cancel - Cancel any currently executing HW scan
b481de9c
ZY		 2060 *
2061 * NOTE: priv->mutex is not required before calling this function
2062 */
bb8c093b 2063static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
b481de9c
ZY		 2064{
2065 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
2066 clear_bit(STATUS_SCANNING, &priv->status);
2067 return 0;
2068 }
2069
2070 if (test_bit(STATUS_SCANNING, &priv->status)) {
2071 if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2072 IWL_DEBUG_SCAN("Queuing scan abort.\n");
2073 set_bit(STATUS_SCAN_ABORTING, &priv->status);
2074 queue_work(priv->workqueue, &priv->abort_scan);
2075
2076 } else
2077 IWL_DEBUG_SCAN("Scan abort already in progress.\n");
2078
2079 return test_bit(STATUS_SCANNING, &priv->status);
2080 }
2081
2082 return 0;
2083}
2084
2085/**
bb8c093b 2086 * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
b481de9c
ZY		 2087 * @ms: amount of time to wait (in milliseconds) for scan to abort
2088 *
2089 * NOTE: priv->mutex must be held before calling this function
2090 */
bb8c093b 2091static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
b481de9c
ZY		 2092{
2093 unsigned long now = jiffies;
2094 int ret;
2095
bb8c093b 2096 ret = iwl3945_scan_cancel(priv);
b481de9c
ZY		 2097 if (ret && ms) {
2098 mutex_unlock(&priv->mutex);
2099 while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
2100 test_bit(STATUS_SCANNING, &priv->status))
2101 msleep(1);
2102 mutex_lock(&priv->mutex);
2103
2104 return test_bit(STATUS_SCANNING, &priv->status);
2105 }
2106
2107 return ret;
2108}
2109
bb8c093b 2110static void iwl3945_sequence_reset(struct iwl3945_priv *priv)
b481de9c
ZY		 2111{
2112 /* Reset ieee stats */
2113
2114 /* We don't reset the net_device_stats (ieee->stats) on
2115 * re-association */
2116
2117 priv->last_seq_num = -1;
2118 priv->last_frag_num = -1;
2119 priv->last_packet_time = 0;
2120
bb8c093b 2121 iwl3945_scan_cancel(priv);
b481de9c
ZY		 2122}
2123
2124#define MAX_UCODE_BEACON_INTERVAL 1024
2125#define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
2126
bb8c093b 2127static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
b481de9c
ZY		 2128{
2129 u16 new_val = 0;
2130 u16 beacon_factor = 0;
2131
2132 beacon_factor =
2133 (beacon_val + MAX_UCODE_BEACON_INTERVAL)
2134 / MAX_UCODE_BEACON_INTERVAL;
2135 new_val = beacon_val / beacon_factor;
2136
2137 return cpu_to_le16(new_val);
2138}
2139
bb8c093b 2140static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
b481de9c
ZY		 2141{
2142 u64 interval_tm_unit;
2143 u64 tsf, result;
2144 unsigned long flags;
2145 struct ieee80211_conf *conf = NULL;
2146 u16 beacon_int = 0;
2147
2148 conf = ieee80211_get_hw_conf(priv->hw);
2149
2150 spin_lock_irqsave(&priv->lock, flags);
2151 priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
2152 priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
2153
2154 priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
2155
2156 tsf = priv->timestamp1;
2157 tsf = ((tsf << 32) | priv->timestamp0);
2158
2159 beacon_int = priv->beacon_int;
2160 spin_unlock_irqrestore(&priv->lock, flags);
2161
2162 if (priv->iw_mode == IEEE80211_IF_TYPE_STA) {
2163 if (beacon_int == 0) {
2164 priv->rxon_timing.beacon_interval = cpu_to_le16(100);
2165 priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
2166 } else {
2167 priv->rxon_timing.beacon_interval =
2168 cpu_to_le16(beacon_int);
2169 priv->rxon_timing.beacon_interval =
bb8c093b 2170 iwl3945_adjust_beacon_interval(
b481de9c
ZY		 2171 le16_to_cpu(priv->rxon_timing.beacon_interval));
2172 }
2173
2174 priv->rxon_timing.atim_window = 0;
2175 } else {
2176 priv->rxon_timing.beacon_interval =
bb8c093b 2177 iwl3945_adjust_beacon_interval(conf->beacon_int);
b481de9c
ZY		 2178 /* TODO: we need to get atim_window from upper stack
2179 * for now we set to 0 */
2180 priv->rxon_timing.atim_window = 0;
2181 }
2182
2183 interval_tm_unit =
2184 (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
2185 result = do_div(tsf, interval_tm_unit);
2186 priv->rxon_timing.beacon_init_val =
2187 cpu_to_le32((u32) ((u64) interval_tm_unit - result));
2188
2189 IWL_DEBUG_ASSOC
2190 ("beacon interval %d beacon timer %d beacon tim %d\n",
2191 le16_to_cpu(priv->rxon_timing.beacon_interval),
2192 le32_to_cpu(priv->rxon_timing.beacon_init_val),
2193 le16_to_cpu(priv->rxon_timing.atim_window));
2194}
2195
bb8c093b 2196static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
b481de9c
ZY		 2197{
2198 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
2199 IWL_ERROR("APs don't scan.\n");
2200 return 0;
2201 }
2202
bb8c093b 2203 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 2204 IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
2205 return -EIO;
2206 }
2207
2208 if (test_bit(STATUS_SCANNING, &priv->status)) {
2209 IWL_DEBUG_SCAN("Scan already in progress.\n");
2210 return -EAGAIN;
2211 }
2212
2213 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2214 IWL_DEBUG_SCAN("Scan request while abort pending. "
2215 "Queuing.\n");
2216 return -EAGAIN;
2217 }
2218
2219 IWL_DEBUG_INFO("Starting scan...\n");
2220 priv->scan_bands = 2;
2221 set_bit(STATUS_SCANNING, &priv->status);
2222 priv->scan_start = jiffies;
2223 priv->scan_pass_start = priv->scan_start;
2224
2225 queue_work(priv->workqueue, &priv->request_scan);
2226
2227 return 0;
2228}
2229
bb8c093b 2230static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
b481de9c 2231{
bb8c093b 2232 struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
b481de9c
ZY		 2233
2234 if (hw_decrypt)
2235 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
2236 else
2237 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
2238
2239 return 0;
2240}
2241
8318d78a
JB		 2242static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv,
2243 enum ieee80211_band band)
b481de9c 2244{
8318d78a 2245 if (band == IEEE80211_BAND_5GHZ) {
b481de9c
ZY		 2246 priv->staging_rxon.flags &=
2247 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
2248 | RXON_FLG_CCK_MSK);
2249 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2250 } else {
bb8c093b 2251 /* Copied from iwl3945_bg_post_associate() */
b481de9c
ZY		 2252 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2253 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2254 else
2255 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2256
2257 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
2258 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2259
2260 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
2261 priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
2262 priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
2263 }
2264}
2265
2266/*
01ebd063 2267 * initialize rxon structure with default values from eeprom
b481de9c 2268 */
bb8c093b 2269static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv)
b481de9c 2270{
bb8c093b 2271 const struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 2272
2273 memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
2274
2275 switch (priv->iw_mode) {
2276 case IEEE80211_IF_TYPE_AP:
2277 priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
2278 break;
2279
2280 case IEEE80211_IF_TYPE_STA:
2281 priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
2282 priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
2283 break;
2284
2285 case IEEE80211_IF_TYPE_IBSS:
2286 priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
2287 priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
2288 priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
2289 RXON_FILTER_ACCEPT_GRP_MSK;
2290 break;
2291
2292 case IEEE80211_IF_TYPE_MNTR:
2293 priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
2294 priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
2295 RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
2296 break;
69dc5d9d
TW		 2297 default:
2298 IWL_ERROR("Unsupported interface type %d\n", priv->iw_mode);
2299 break;
b481de9c
ZY		 2300 }
2301
2302#if 0
2303 /* TODO: Figure out when short_preamble would be set and cache from
2304 * that */
2305 if (!hw_to_local(priv->hw)->short_preamble)
2306 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2307 else
2308 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2309#endif
2310
8318d78a 2311 ch_info = iwl3945_get_channel_info(priv, priv->band,
b481de9c
ZY		 2312 le16_to_cpu(priv->staging_rxon.channel));
2313
2314 if (!ch_info)
2315 ch_info = &priv->channel_info[0];
2316
2317 /*
2318 * in some case A channels are all non IBSS
2319 * in this case force B/G channel
2320 */
2321 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
2322 !(is_channel_ibss(ch_info)))
2323 ch_info = &priv->channel_info[0];
2324
2325 priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
2326 if (is_channel_a_band(ch_info))
8318d78a 2327 priv->band = IEEE80211_BAND_5GHZ;
b481de9c 2328 else
8318d78a 2329 priv->band = IEEE80211_BAND_2GHZ;
b481de9c 2330
8318d78a 2331 iwl3945_set_flags_for_phymode(priv, priv->band);
b481de9c
ZY		 2332
2333 priv->staging_rxon.ofdm_basic_rates =
2334 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2335 priv->staging_rxon.cck_basic_rates =
2336 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2337}
2338
bb8c093b 2339static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
b481de9c 2340{
b481de9c 2341 if (mode == IEEE80211_IF_TYPE_IBSS) {
bb8c093b 2342 const struct iwl3945_channel_info *ch_info;
b481de9c 2343
bb8c093b 2344 ch_info = iwl3945_get_channel_info(priv,
8318d78a 2345 priv->band,
b481de9c
ZY		 2346 le16_to_cpu(priv->staging_rxon.channel));
2347
2348 if (!ch_info || !is_channel_ibss(ch_info)) {
2349 IWL_ERROR("channel %d not IBSS channel\n",
2350 le16_to_cpu(priv->staging_rxon.channel));
2351 return -EINVAL;
2352 }
2353 }
2354
b481de9c
ZY		 2355 priv->iw_mode = mode;
2356
bb8c093b 2357 iwl3945_connection_init_rx_config(priv);
b481de9c
ZY		 2358 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2359
bb8c093b 2360 iwl3945_clear_stations_table(priv);
b481de9c 2361
fde3571f
MA		 2362 /* dont commit rxon if rf-kill is on*/
2363 if (!iwl3945_is_ready_rf(priv))
2364 return -EAGAIN;
2365
2366 cancel_delayed_work(&priv->scan_check);
2367 if (iwl3945_scan_cancel_timeout(priv, 100)) {
2368 IWL_WARNING("Aborted scan still in progress after 100ms\n");
2369 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
2370 return -EAGAIN;
2371 }
2372
bb8c093b 2373 iwl3945_commit_rxon(priv);
b481de9c
ZY		 2374
2375 return 0;
2376}
2377
bb8c093b 2378static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
b481de9c 2379 struct ieee80211_tx_control *ctl,
bb8c093b 2380 struct iwl3945_cmd *cmd,
b481de9c
ZY		 2381 struct sk_buff *skb_frag,
2382 int last_frag)
2383{
1c014420
ID		 2384 struct iwl3945_hw_key *keyinfo =
2385 &priv->stations[ctl->hw_key->hw_key_idx].keyinfo;
b481de9c
ZY		 2386
2387 switch (keyinfo->alg) {
2388 case ALG_CCMP:
2389 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
2390 memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
2391 IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
2392 break;
2393
2394 case ALG_TKIP:
2395#if 0
2396 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
2397
2398 if (last_frag)
2399 memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
2400 8);
2401 else
2402 memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
2403#endif
2404 break;
2405
2406 case ALG_WEP:
2407 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
1c014420 2408 (ctl->hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
b481de9c
ZY		 2409
2410 if (keyinfo->keylen == 13)
2411 cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
2412
2413 memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
2414
2415 IWL_DEBUG_TX("Configuring packet for WEP encryption "
1c014420 2416 "with key %d\n", ctl->hw_key->hw_key_idx);
b481de9c
ZY		 2417 break;
2418
b481de9c
ZY		 2419 default:
2420 printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
2421 break;
2422 }
2423}
2424
2425/*
2426 * handle build REPLY_TX command notification.
2427 */
bb8c093b
CH		 2428static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
2429 struct iwl3945_cmd *cmd,
b481de9c
ZY		 2430 struct ieee80211_tx_control *ctrl,
2431 struct ieee80211_hdr *hdr,
2432 int is_unicast, u8 std_id)
2433{
b481de9c
ZY		 2434 u16 fc = le16_to_cpu(hdr->frame_control);
2435 __le32 tx_flags = cmd->cmd.tx.tx_flags;
2436
2437 cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2438 if (!(ctrl->flags & IEEE80211_TXCTL_NO_ACK)) {
2439 tx_flags |= TX_CMD_FLG_ACK_MSK;
2440 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
2441 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2442 if (ieee80211_is_probe_response(fc) &&
2443 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
2444 tx_flags |= TX_CMD_FLG_TSF_MSK;
2445 } else {
2446 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
2447 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2448 }
2449
2450 cmd->cmd.tx.sta_id = std_id;
2451 if (ieee80211_get_morefrag(hdr))
2452 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
2453
54dbb525
TW		 2454 if (ieee80211_is_qos_data(fc)) {
2455 u8 *qc = ieee80211_get_qos_ctrl(hdr, ieee80211_get_hdrlen(fc));
2456 cmd->cmd.tx.tid_tspec = qc[0] & 0xf;
b481de9c 2457 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 2458 } else {
b481de9c 2459 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 2460 }
b481de9c
ZY		 2461
2462 if (ctrl->flags & IEEE80211_TXCTL_USE_RTS_CTS) {
2463 tx_flags |= TX_CMD_FLG_RTS_MSK;
2464 tx_flags &= ~TX_CMD_FLG_CTS_MSK;
2465 } else if (ctrl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) {
2466 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2467 tx_flags |= TX_CMD_FLG_CTS_MSK;
2468 }
2469
2470 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
2471 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
2472
2473 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
2474 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) {
2475 if ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_REQ ||
2476 (fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_REASSOC_REQ)
bc434dd2 2477 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
b481de9c 2478 else
bc434dd2 2479 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
ab53d8af 2480 } else {
b481de9c 2481 cmd->cmd.tx.timeout.pm_frame_timeout = 0;
ab53d8af
MA		 2482#ifdef CONFIG_IWL3945_LEDS
2483 priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
2484#endif
2485 }
b481de9c
ZY		 2486
2487 cmd->cmd.tx.driver_txop = 0;
2488 cmd->cmd.tx.tx_flags = tx_flags;
2489 cmd->cmd.tx.next_frame_len = 0;
2490}
2491
6440adb5
CB		 2492/**
2493 * iwl3945_get_sta_id - Find station's index within station table
2494 */
bb8c093b 2495static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
b481de9c
ZY		 2496{
2497 int sta_id;
2498 u16 fc = le16_to_cpu(hdr->frame_control);
2499
6440adb5 2500 /* If this frame is broadcast or management, use broadcast station id */
b481de9c
ZY		 2501 if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
2502 is_multicast_ether_addr(hdr->addr1))
2503 return priv->hw_setting.bcast_sta_id;
2504
2505 switch (priv->iw_mode) {
2506
6440adb5
CB		 2507 /* If we are a client station in a BSS network, use the special
2508 * AP station entry (that's the only station we communicate with) */
b481de9c
ZY		 2509 case IEEE80211_IF_TYPE_STA:
2510 return IWL_AP_ID;
2511
2512 /* If we are an AP, then find the station, or use BCAST */
2513 case IEEE80211_IF_TYPE_AP:
bb8c093b 2514 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY		 2515 if (sta_id != IWL_INVALID_STATION)
2516 return sta_id;
2517 return priv->hw_setting.bcast_sta_id;
2518
6440adb5
CB		 2519 /* If this frame is going out to an IBSS network, find the station,
2520 * or create a new station table entry */
0795af57
JP		 2521 case IEEE80211_IF_TYPE_IBSS: {
2522 DECLARE_MAC_BUF(mac);
2523
6440adb5 2524 /* Create new station table entry */
bb8c093b 2525 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY		 2526 if (sta_id != IWL_INVALID_STATION)
2527 return sta_id;
2528
bb8c093b 2529 sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
b481de9c
ZY		 2530
2531 if (sta_id != IWL_INVALID_STATION)
2532 return sta_id;
2533
0795af57 2534 IWL_DEBUG_DROP("Station %s not in station map. "
b481de9c 2535 "Defaulting to broadcast...\n",
0795af57 2536 print_mac(mac, hdr->addr1));
bb8c093b 2537 iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
b481de9c 2538 return priv->hw_setting.bcast_sta_id;
0795af57 2539 }
b481de9c 2540 default:
01ebd063 2541 IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode);
b481de9c
ZY		 2542 return priv->hw_setting.bcast_sta_id;
2543 }
2544}
2545
2546/*
2547 * start REPLY_TX command process
2548 */
bb8c093b 2549static int iwl3945_tx_skb(struct iwl3945_priv *priv,
b481de9c
ZY		 2550 struct sk_buff *skb, struct ieee80211_tx_control *ctl)
2551{
2552 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
bb8c093b 2553 struct iwl3945_tfd_frame *tfd;
b481de9c
ZY		 2554 u32 *control_flags;
2555 int txq_id = ctl->queue;
bb8c093b
CH		 2556 struct iwl3945_tx_queue *txq = NULL;
2557 struct iwl3945_queue *q = NULL;
b481de9c
ZY		 2558 dma_addr_t phys_addr;
2559 dma_addr_t txcmd_phys;
bb8c093b 2560 struct iwl3945_cmd *out_cmd = NULL;
54dbb525
TW		 2561 u16 len, idx, len_org, hdr_len;
2562 u8 id;
2563 u8 unicast;
b481de9c 2564 u8 sta_id;
54dbb525 2565 u8 tid = 0;
b481de9c
ZY		 2566 u16 seq_number = 0;
2567 u16 fc;
b481de9c 2568 u8 wait_write_ptr = 0;
54dbb525 2569 u8 *qc = NULL;
b481de9c
ZY		 2570 unsigned long flags;
2571 int rc;
2572
2573 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2574 if (iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 2575 IWL_DEBUG_DROP("Dropping - RF KILL\n");
2576 goto drop_unlock;
2577 }
2578
32bfd35d
JB		 2579 if (!priv->vif) {
2580 IWL_DEBUG_DROP("Dropping - !priv->vif\n");
b481de9c
ZY		 2581 goto drop_unlock;
2582 }
2583
2e92e6f2 2584 if ((ieee80211_get_tx_rate(priv->hw, ctl)->hw_value & 0xFF) == IWL_INVALID_RATE) {
b481de9c
ZY		 2585 IWL_ERROR("ERROR: No TX rate available.\n");
2586 goto drop_unlock;
2587 }
2588
2589 unicast = !is_multicast_ether_addr(hdr->addr1);
2590 id = 0;
2591
2592 fc = le16_to_cpu(hdr->frame_control);
2593
c8b0e6e1 2594#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 2595 if (ieee80211_is_auth(fc))
2596 IWL_DEBUG_TX("Sending AUTH frame\n");
2597 else if (ieee80211_is_assoc_request(fc))
2598 IWL_DEBUG_TX("Sending ASSOC frame\n");
2599 else if (ieee80211_is_reassoc_request(fc))
2600 IWL_DEBUG_TX("Sending REASSOC frame\n");
2601#endif
2602
7878a5a4 2603 /* drop all data frame if we are not associated */
a6477249
RC		 2604 if ((!iwl3945_is_associated(priv) ||
2605 ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && !priv->assoc_id)) &&
b481de9c 2606 ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA)) {
bb8c093b 2607 IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
b481de9c
ZY		 2608 goto drop_unlock;
2609 }
2610
2611 spin_unlock_irqrestore(&priv->lock, flags);
2612
2613 hdr_len = ieee80211_get_hdrlen(fc);
6440adb5
CB		 2614
2615 /* Find (or create) index into station table for destination station */
bb8c093b 2616 sta_id = iwl3945_get_sta_id(priv, hdr);
b481de9c 2617 if (sta_id == IWL_INVALID_STATION) {
0795af57
JP		 2618 DECLARE_MAC_BUF(mac);
2619
2620 IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
2621 print_mac(mac, hdr->addr1));
b481de9c
ZY		 2622 goto drop;
2623 }
2624
2625 IWL_DEBUG_RATE("station Id %d\n", sta_id);
2626
54dbb525
TW		 2627 if (ieee80211_is_qos_data(fc)) {
2628 qc = ieee80211_get_qos_ctrl(hdr, hdr_len);
2629 tid = qc[0] & 0xf;
b481de9c
ZY		 2630 seq_number = priv->stations[sta_id].tid[tid].seq_number &
2631 IEEE80211_SCTL_SEQ;
2632 hdr->seq_ctrl = cpu_to_le16(seq_number) |
2633 (hdr->seq_ctrl &
2634 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
2635 seq_number += 0x10;
2636 }
6440adb5
CB		 2637
2638 /* Descriptor for chosen Tx queue */
b481de9c
ZY		 2639 txq = &priv->txq[txq_id];
2640 q = &txq->q;
2641
2642 spin_lock_irqsave(&priv->lock, flags);
2643
6440adb5 2644 /* Set up first empty TFD within this queue's circular TFD buffer */
fc4b6853 2645 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY		 2646 memset(tfd, 0, sizeof(*tfd));
2647 control_flags = (u32 *) tfd;
fc4b6853 2648 idx = get_cmd_index(q, q->write_ptr, 0);
b481de9c 2649
6440adb5 2650 /* Set up driver data for this TFD */
bb8c093b 2651 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
fc4b6853
TW		 2652 txq->txb[q->write_ptr].skb[0] = skb;
2653 memcpy(&(txq->txb[q->write_ptr].status.control),
b481de9c 2654 ctl, sizeof(struct ieee80211_tx_control));
6440adb5
CB		 2655
2656 /* Init first empty entry in queue's array of Tx/cmd buffers */
b481de9c
ZY		 2657 out_cmd = &txq->cmd[idx];
2658 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
2659 memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
6440adb5
CB		 2660
2661 /*
2662 * Set up the Tx-command (not MAC!) header.
2663 * Store the chosen Tx queue and TFD index within the sequence field;
2664 * after Tx, uCode's Tx response will return this value so driver can
2665 * locate the frame within the tx queue and do post-tx processing.
2666 */
b481de9c
ZY		 2667 out_cmd->hdr.cmd = REPLY_TX;
2668 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
fc4b6853 2669 INDEX_TO_SEQ(q->write_ptr)));
6440adb5
CB		 2670
2671 /* Copy MAC header from skb into command buffer */
b481de9c
ZY		 2672 memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
2673
6440adb5
CB		 2674 /*
2675 * Use the first empty entry in this queue's command buffer array
2676 * to contain the Tx command and MAC header concatenated together
2677 * (payload data will be in another buffer).
2678 * Size of this varies, due to varying MAC header length.
2679 * If end is not dword aligned, we'll have 2 extra bytes at the end
2680 * of the MAC header (device reads on dword boundaries).
2681 * We'll tell device about this padding later.
2682 */
b481de9c 2683 len = priv->hw_setting.tx_cmd_len +
bb8c093b 2684 sizeof(struct iwl3945_cmd_header) + hdr_len;
b481de9c
ZY		 2685
2686 len_org = len;
2687 len = (len + 3) & ~3;
2688
2689 if (len_org != len)
2690 len_org = 1;
2691 else
2692 len_org = 0;
2693
6440adb5
CB		 2694 /* Physical address of this Tx command's header (not MAC header!),
2695 * within command buffer array. */
bb8c093b
CH		 2696 txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
2697 offsetof(struct iwl3945_cmd, hdr);
b481de9c 2698
6440adb5
CB		 2699 /* Add buffer containing Tx command and MAC(!) header to TFD's
2700 * first entry */
bb8c093b 2701 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
b481de9c
ZY		 2702
2703 if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT))
bb8c093b 2704 iwl3945_build_tx_cmd_hwcrypto(priv, ctl, out_cmd, skb, 0);
b481de9c 2705
6440adb5
CB		 2706 /* Set up TFD's 2nd entry to point directly to remainder of skb,
2707 * if any (802.11 null frames have no payload). */
b481de9c
ZY		 2708 len = skb->len - hdr_len;
2709 if (len) {
2710 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
2711 len, PCI_DMA_TODEVICE);
bb8c093b 2712 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
b481de9c
ZY		 2713 }
2714
b481de9c 2715 if (!len)
6440adb5 2716 /* If there is no payload, then we use only one Tx buffer */
b481de9c
ZY		 2717 *control_flags = TFD_CTL_COUNT_SET(1);
2718 else
6440adb5
CB		 2719 /* Else use 2 buffers.
2720 * Tell 3945 about any padding after MAC header */
b481de9c
ZY		 2721 *control_flags = TFD_CTL_COUNT_SET(2) |
2722 TFD_CTL_PAD_SET(U32_PAD(len));
2723
6440adb5 2724 /* Total # bytes to be transmitted */
b481de9c
ZY		 2725 len = (u16)skb->len;
2726 out_cmd->cmd.tx.len = cpu_to_le16(len);
2727
2728 /* TODO need this for burst mode later on */
bb8c093b 2729 iwl3945_build_tx_cmd_basic(priv, out_cmd, ctl, hdr, unicast, sta_id);
b481de9c
ZY		 2730
2731 /* set is_hcca to 0; it probably will never be implemented */
bb8c093b 2732 iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, ctl, hdr, sta_id, 0);
b481de9c
ZY		 2733
2734 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
2735 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
2736
2737 if (!ieee80211_get_morefrag(hdr)) {
2738 txq->need_update = 1;
2739 if (qc) {
b481de9c
ZY		 2740 priv->stations[sta_id].tid[tid].seq_number = seq_number;
2741 }
2742 } else {
2743 wait_write_ptr = 1;
2744 txq->need_update = 0;
2745 }
2746
bb8c093b 2747 iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
b481de9c
ZY		 2748 sizeof(out_cmd->cmd.tx));
2749
bb8c093b 2750 iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
b481de9c
ZY		 2751 ieee80211_get_hdrlen(fc));
2752
6440adb5 2753 /* Tell device the write index *just past* this latest filled TFD */
c54b679d 2754 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
bb8c093b 2755 rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 2756 spin_unlock_irqrestore(&priv->lock, flags);
2757
2758 if (rc)
2759 return rc;
2760
bb8c093b 2761 if ((iwl3945_queue_space(q) < q->high_mark)
b481de9c
ZY		 2762 && priv->mac80211_registered) {
2763 if (wait_write_ptr) {
2764 spin_lock_irqsave(&priv->lock, flags);
2765 txq->need_update = 1;
bb8c093b 2766 iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 2767 spin_unlock_irqrestore(&priv->lock, flags);
2768 }
2769
2770 ieee80211_stop_queue(priv->hw, ctl->queue);
2771 }
2772
2773 return 0;
2774
2775drop_unlock:
2776 spin_unlock_irqrestore(&priv->lock, flags);
2777drop:
2778 return -1;
2779}
2780
bb8c093b 2781static void iwl3945_set_rate(struct iwl3945_priv *priv)
b481de9c 2782{
8318d78a 2783 const struct ieee80211_supported_band *sband = NULL;
b481de9c
ZY		 2784 struct ieee80211_rate *rate;
2785 int i;
2786
8318d78a
JB		 2787 sband = iwl3945_get_band(priv, priv->band);
2788 if (!sband) {
c4ba9621
SA		 2789 IWL_ERROR("Failed to set rate: unable to get hw mode\n");
2790 return;
2791 }
b481de9c
ZY		 2792
2793 priv->active_rate = 0;
2794 priv->active_rate_basic = 0;
2795
8318d78a
JB		 2796 IWL_DEBUG_RATE("Setting rates for %s GHz\n",
2797 sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
2798
2799 for (i = 0; i < sband->n_bitrates; i++) {
2800 rate = &sband->bitrates[i];
2801 if ((rate->hw_value < IWL_RATE_COUNT) &&
2802 !(rate->flags & IEEE80211_CHAN_DISABLED)) {
2803 IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
2804 rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
2805 priv->active_rate |= (1 << rate->hw_value);
2806 }
b481de9c
ZY		 2807 }
2808
2809 IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
2810 priv->active_rate, priv->active_rate_basic);
2811
2812 /*
2813 * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
2814 * otherwise set it to the default of all CCK rates and 6, 12, 24 for
2815 * OFDM
2816 */
2817 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
2818 priv->staging_rxon.cck_basic_rates =
2819 ((priv->active_rate_basic &
2820 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
2821 else
2822 priv->staging_rxon.cck_basic_rates =
2823 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2824
2825 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
2826 priv->staging_rxon.ofdm_basic_rates =
2827 ((priv->active_rate_basic &
2828 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
2829 IWL_FIRST_OFDM_RATE) & 0xFF;
2830 else
2831 priv->staging_rxon.ofdm_basic_rates =
2832 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2833}
2834
bb8c093b 2835static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
b481de9c
ZY		 2836{
2837 unsigned long flags;
2838
2839 if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
2840 return;
2841
2842 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
2843 disable_radio ? "OFF" : "ON");
2844
2845 if (disable_radio) {
bb8c093b 2846 iwl3945_scan_cancel(priv);
b481de9c
ZY		 2847 /* FIXME: This is a workaround for AP */
2848 if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
2849 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2850 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 2851 CSR_UCODE_SW_BIT_RFKILL);
2852 spin_unlock_irqrestore(&priv->lock, flags);
bb8c093b 2853 iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
b481de9c
ZY		 2854 set_bit(STATUS_RF_KILL_SW, &priv->status);
2855 }
2856 return;
2857 }
2858
2859 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2860 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 2861
2862 clear_bit(STATUS_RF_KILL_SW, &priv->status);
2863 spin_unlock_irqrestore(&priv->lock, flags);
2864
2865 /* wake up ucode */
2866 msleep(10);
2867
2868 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH		 2869 iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
2870 if (!iwl3945_grab_nic_access(priv))
2871 iwl3945_release_nic_access(priv);
b481de9c
ZY		 2872 spin_unlock_irqrestore(&priv->lock, flags);
2873
2874 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
2875 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
2876 "disabled by HW switch\n");
2877 return;
2878 }
2879
2880 queue_work(priv->workqueue, &priv->restart);
2881 return;
2882}
2883
bb8c093b 2884void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
b481de9c
ZY		 2885 u32 decrypt_res, struct ieee80211_rx_status *stats)
2886{
2887 u16 fc =
2888 le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
2889
2890 if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
2891 return;
2892
2893 if (!(fc & IEEE80211_FCTL_PROTECTED))
2894 return;
2895
2896 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
2897 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2898 case RX_RES_STATUS_SEC_TYPE_TKIP:
2899 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2900 RX_RES_STATUS_BAD_ICV_MIC)
2901 stats->flag |= RX_FLAG_MMIC_ERROR;
2902 case RX_RES_STATUS_SEC_TYPE_WEP:
2903 case RX_RES_STATUS_SEC_TYPE_CCMP:
2904 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2905 RX_RES_STATUS_DECRYPT_OK) {
2906 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
2907 stats->flag |= RX_FLAG_DECRYPTED;
2908 }
2909 break;
2910
2911 default:
2912 break;
2913 }
2914}
2915
b481de9c
ZY		 2916#define IWL_PACKET_RETRY_TIME HZ
2917
bb8c093b 2918int iwl3945_is_duplicate_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
b481de9c
ZY		 2919{
2920 u16 sc = le16_to_cpu(header->seq_ctrl);
2921 u16 seq = (sc & IEEE80211_SCTL_SEQ) >> 4;
2922 u16 frag = sc & IEEE80211_SCTL_FRAG;
2923 u16 *last_seq, *last_frag;
2924 unsigned long *last_time;
2925
2926 switch (priv->iw_mode) {
2927 case IEEE80211_IF_TYPE_IBSS:{
2928 struct list_head *p;
bb8c093b 2929 struct iwl3945_ibss_seq *entry = NULL;
b481de9c
ZY		 2930 u8 *mac = header->addr2;
2931 int index = mac[5] & (IWL_IBSS_MAC_HASH_SIZE - 1);
2932
2933 __list_for_each(p, &priv->ibss_mac_hash[index]) {
bb8c093b 2934 entry = list_entry(p, struct iwl3945_ibss_seq, list);
b481de9c
ZY		 2935 if (!compare_ether_addr(entry->mac, mac))
2936 break;
2937 }
2938 if (p == &priv->ibss_mac_hash[index]) {
2939 entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
2940 if (!entry) {
bc434dd2 2941 IWL_ERROR("Cannot malloc new mac entry\n");
b481de9c
ZY		 2942 return 0;
2943 }
2944 memcpy(entry->mac, mac, ETH_ALEN);
2945 entry->seq_num = seq;
2946 entry->frag_num = frag;
2947 entry->packet_time = jiffies;
bc434dd2 2948 list_add(&entry->list, &priv->ibss_mac_hash[index]);
b481de9c
ZY		 2949 return 0;
2950 }
2951 last_seq = &entry->seq_num;
2952 last_frag = &entry->frag_num;
2953 last_time = &entry->packet_time;
2954 break;
2955 }
2956 case IEEE80211_IF_TYPE_STA:
2957 last_seq = &priv->last_seq_num;
2958 last_frag = &priv->last_frag_num;
2959 last_time = &priv->last_packet_time;
2960 break;
2961 default:
2962 return 0;
2963 }
2964 if ((*last_seq == seq) &&
2965 time_after(*last_time + IWL_PACKET_RETRY_TIME, jiffies)) {
2966 if (*last_frag == frag)
2967 goto drop;
2968 if (*last_frag + 1 != frag)
2969 /* out-of-order fragment */
2970 goto drop;
2971 } else
2972 *last_seq = seq;
2973
2974 *last_frag = frag;
2975 *last_time = jiffies;
2976 return 0;
2977
2978 drop:
2979 return 1;
2980}
2981
c8b0e6e1 2982#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 2983
2984#include "iwl-spectrum.h"
2985
2986#define BEACON_TIME_MASK_LOW 0x00FFFFFF
2987#define BEACON_TIME_MASK_HIGH 0xFF000000
2988#define TIME_UNIT 1024
2989
2990/*
2991 * extended beacon time format
2992 * time in usec will be changed into a 32-bit value in 8:24 format
2993 * the high 1 byte is the beacon counts
2994 * the lower 3 bytes is the time in usec within one beacon interval
2995 */
2996
bb8c093b 2997static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
b481de9c
ZY		 2998{
2999 u32 quot;
3000 u32 rem;
3001 u32 interval = beacon_interval * 1024;
3002
3003 if (!interval || !usec)
3004 return 0;
3005
3006 quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
3007 rem = (usec % interval) & BEACON_TIME_MASK_LOW;
3008
3009 return (quot << 24) + rem;
3010}
3011
3012/* base is usually what we get from ucode with each received frame,
3013 * the same as HW timer counter counting down
3014 */
3015
bb8c093b 3016static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
b481de9c
ZY		 3017{
3018 u32 base_low = base & BEACON_TIME_MASK_LOW;
3019 u32 addon_low = addon & BEACON_TIME_MASK_LOW;
3020 u32 interval = beacon_interval * TIME_UNIT;
3021 u32 res = (base & BEACON_TIME_MASK_HIGH) +
3022 (addon & BEACON_TIME_MASK_HIGH);
3023
3024 if (base_low > addon_low)
3025 res += base_low - addon_low;
3026 else if (base_low < addon_low) {
3027 res += interval + base_low - addon_low;
3028 res += (1 << 24);
3029 } else
3030 res += (1 << 24);
3031
3032 return cpu_to_le32(res);
3033}
3034
bb8c093b 3035static int iwl3945_get_measurement(struct iwl3945_priv *priv,
b481de9c
ZY		 3036 struct ieee80211_measurement_params *params,
3037 u8 type)
3038{
bb8c093b
CH		 3039 struct iwl3945_spectrum_cmd spectrum;
3040 struct iwl3945_rx_packet *res;
3041 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 3042 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
3043 .data = (void *)&spectrum,
3044 .meta.flags = CMD_WANT_SKB,
3045 };
3046 u32 add_time = le64_to_cpu(params->start_time);
3047 int rc;
3048 int spectrum_resp_status;
3049 int duration = le16_to_cpu(params->duration);
3050
bb8c093b 3051 if (iwl3945_is_associated(priv))
b481de9c 3052 add_time =
bb8c093b 3053 iwl3945_usecs_to_beacons(
b481de9c
ZY		 3054 le64_to_cpu(params->start_time) - priv->last_tsf,
3055 le16_to_cpu(priv->rxon_timing.beacon_interval));
3056
3057 memset(&spectrum, 0, sizeof(spectrum));
3058
3059 spectrum.channel_count = cpu_to_le16(1);
3060 spectrum.flags =
3061 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
3062 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
3063 cmd.len = sizeof(spectrum);
3064 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
3065
bb8c093b 3066 if (iwl3945_is_associated(priv))
b481de9c 3067 spectrum.start_time =
bb8c093b 3068 iwl3945_add_beacon_time(priv->last_beacon_time,
b481de9c
ZY		 3069 add_time,
3070 le16_to_cpu(priv->rxon_timing.beacon_interval));
3071 else
3072 spectrum.start_time = 0;
3073
3074 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
3075 spectrum.channels[0].channel = params->channel;
3076 spectrum.channels[0].type = type;
3077 if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
3078 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
3079 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
3080
bb8c093b 3081 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 3082 if (rc)
3083 return rc;
3084
bb8c093b 3085 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 3086 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
3087 IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
3088 rc = -EIO;
3089 }
3090
3091 spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
3092 switch (spectrum_resp_status) {
3093 case 0: /* Command will be handled */
3094 if (res->u.spectrum.id != 0xff) {
bc434dd2
IS		 3095 IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
3096 res->u.spectrum.id);
b481de9c
ZY		 3097 priv->measurement_status &= ~MEASUREMENT_READY;
3098 }
3099 priv->measurement_status |= MEASUREMENT_ACTIVE;
3100 rc = 0;
3101 break;
3102
3103 case 1: /* Command will not be handled */
3104 rc = -EAGAIN;
3105 break;
3106 }
3107
3108 dev_kfree_skb_any(cmd.meta.u.skb);
3109
3110 return rc;
3111}
3112#endif
3113
bb8c093b
CH		 3114static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
3115 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3116{
bb8c093b
CH		 3117 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3118 struct iwl3945_alive_resp *palive;
b481de9c
ZY		 3119 struct delayed_work *pwork;
3120
3121 palive = &pkt->u.alive_frame;
3122
3123 IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
3124 "0x%01X 0x%01X\n",
3125 palive->is_valid, palive->ver_type,
3126 palive->ver_subtype);
3127
3128 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
3129 IWL_DEBUG_INFO("Initialization Alive received.\n");
3130 memcpy(&priv->card_alive_init,
3131 &pkt->u.alive_frame,
bb8c093b 3132 sizeof(struct iwl3945_init_alive_resp));
b481de9c
ZY		 3133 pwork = &priv->init_alive_start;
3134 } else {
3135 IWL_DEBUG_INFO("Runtime Alive received.\n");
3136 memcpy(&priv->card_alive, &pkt->u.alive_frame,
bb8c093b 3137 sizeof(struct iwl3945_alive_resp));
b481de9c 3138 pwork = &priv->alive_start;
bb8c093b 3139 iwl3945_disable_events(priv);
b481de9c
ZY		 3140 }
3141
3142 /* We delay the ALIVE response by 5ms to
3143 * give the HW RF Kill time to activate... */
3144 if (palive->is_valid == UCODE_VALID_OK)
3145 queue_delayed_work(priv->workqueue, pwork,
3146 msecs_to_jiffies(5));
3147 else
3148 IWL_WARNING("uCode did not respond OK.\n");
3149}
3150
bb8c093b
CH		 3151static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
3152 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3153{
bb8c093b 3154 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3155
3156 IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
3157 return;
3158}
3159
bb8c093b
CH		 3160static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
3161 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3162{
bb8c093b 3163 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3164
3165 IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
3166 "seq 0x%04X ser 0x%08X\n",
3167 le32_to_cpu(pkt->u.err_resp.error_type),
3168 get_cmd_string(pkt->u.err_resp.cmd_id),
3169 pkt->u.err_resp.cmd_id,
3170 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
3171 le32_to_cpu(pkt->u.err_resp.error_info));
3172}
3173
3174#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
3175
bb8c093b 3176static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3177{
bb8c093b
CH		 3178 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3179 struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
3180 struct iwl3945_csa_notification *csa = &(pkt->u.csa_notif);
b481de9c
ZY		 3181 IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
3182 le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
3183 rxon->channel = csa->channel;
3184 priv->staging_rxon.channel = csa->channel;
3185}
3186
bb8c093b
CH		 3187static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
3188 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3189{
c8b0e6e1 3190#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
bb8c093b
CH		 3191 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3192 struct iwl3945_spectrum_notification *report = &(pkt->u.spectrum_notif);
b481de9c
ZY		 3193
3194 if (!report->state) {
3195 IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
3196 "Spectrum Measure Notification: Start\n");
3197 return;
3198 }
3199
3200 memcpy(&priv->measure_report, report, sizeof(*report));
3201 priv->measurement_status |= MEASUREMENT_READY;
3202#endif
3203}
3204
bb8c093b
CH		 3205static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
3206 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3207{
c8b0e6e1 3208#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3209 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3210 struct iwl3945_sleep_notification *sleep = &(pkt->u.sleep_notif);
b481de9c
ZY		 3211 IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
3212 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
3213#endif
3214}
3215
bb8c093b
CH		 3216static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
3217 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3218{
bb8c093b 3219 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3220 IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
3221 "notification for %s:\n",
3222 le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
bb8c093b 3223 iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
b481de9c
ZY		 3224}
3225
bb8c093b 3226static void iwl3945_bg_beacon_update(struct work_struct *work)
b481de9c 3227{
bb8c093b
CH		 3228 struct iwl3945_priv *priv =
3229 container_of(work, struct iwl3945_priv, beacon_update);
b481de9c
ZY		 3230 struct sk_buff *beacon;
3231
3232 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
32bfd35d 3233 beacon = ieee80211_beacon_get(priv->hw, priv->vif, NULL);
b481de9c
ZY		 3234
3235 if (!beacon) {
3236 IWL_ERROR("update beacon failed\n");
3237 return;
3238 }
3239
3240 mutex_lock(&priv->mutex);
3241 /* new beacon skb is allocated every time; dispose previous.*/
3242 if (priv->ibss_beacon)
3243 dev_kfree_skb(priv->ibss_beacon);
3244
3245 priv->ibss_beacon = beacon;
3246 mutex_unlock(&priv->mutex);
3247
bb8c093b 3248 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 3249}
3250
bb8c093b
CH		 3251static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
3252 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3253{
c8b0e6e1 3254#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3255 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3256 struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
b481de9c
ZY		 3257 u8 rate = beacon->beacon_notify_hdr.rate;
3258
3259 IWL_DEBUG_RX("beacon status %x retries %d iss %d "
3260 "tsf %d %d rate %d\n",
3261 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
3262 beacon->beacon_notify_hdr.failure_frame,
3263 le32_to_cpu(beacon->ibss_mgr_status),
3264 le32_to_cpu(beacon->high_tsf),
3265 le32_to_cpu(beacon->low_tsf), rate);
3266#endif
3267
3268 if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
3269 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
3270 queue_work(priv->workqueue, &priv->beacon_update);
3271}
3272
3273/* Service response to REPLY_SCAN_CMD (0x80) */
bb8c093b
CH		 3274static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
3275 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3276{
c8b0e6e1 3277#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3278 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3279 struct iwl3945_scanreq_notification *notif =
3280 (struct iwl3945_scanreq_notification *)pkt->u.raw;
b481de9c
ZY		 3281
3282 IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
3283#endif
3284}
3285
3286/* Service SCAN_START_NOTIFICATION (0x82) */
bb8c093b
CH		 3287static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
3288 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3289{
bb8c093b
CH		 3290 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3291 struct iwl3945_scanstart_notification *notif =
3292 (struct iwl3945_scanstart_notification *)pkt->u.raw;
b481de9c
ZY		 3293 priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
3294 IWL_DEBUG_SCAN("Scan start: "
3295 "%d [802.11%s] "
3296 "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
3297 notif->channel,
3298 notif->band ? "bg" : "a",
3299 notif->tsf_high,
3300 notif->tsf_low, notif->status, notif->beacon_timer);
3301}
3302
3303/* Service SCAN_RESULTS_NOTIFICATION (0x83) */
bb8c093b
CH		 3304static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
3305 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3306{
bb8c093b
CH		 3307 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3308 struct iwl3945_scanresults_notification *notif =
3309 (struct iwl3945_scanresults_notification *)pkt->u.raw;
b481de9c
ZY		 3310
3311 IWL_DEBUG_SCAN("Scan ch.res: "
3312 "%d [802.11%s] "
3313 "(TSF: 0x%08X:%08X) - %d "
3314 "elapsed=%lu usec (%dms since last)\n",
3315 notif->channel,
3316 notif->band ? "bg" : "a",
3317 le32_to_cpu(notif->tsf_high),
3318 le32_to_cpu(notif->tsf_low),
3319 le32_to_cpu(notif->statistics[0]),
3320 le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
3321 jiffies_to_msecs(elapsed_jiffies
3322 (priv->last_scan_jiffies, jiffies)));
3323
3324 priv->last_scan_jiffies = jiffies;
7878a5a4 3325 priv->next_scan_jiffies = 0;
b481de9c
ZY		 3326}
3327
3328/* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
bb8c093b
CH		 3329static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
3330 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3331{
bb8c093b
CH		 3332 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3333 struct iwl3945_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
b481de9c
ZY		 3334
3335 IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
3336 scan_notif->scanned_channels,
3337 scan_notif->tsf_low,
3338 scan_notif->tsf_high, scan_notif->status);
3339
3340 /* The HW is no longer scanning */
3341 clear_bit(STATUS_SCAN_HW, &priv->status);
3342
3343 /* The scan completion notification came in, so kill that timer... */
3344 cancel_delayed_work(&priv->scan_check);
3345
3346 IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
3347 (priv->scan_bands == 2) ? "2.4" : "5.2",
3348 jiffies_to_msecs(elapsed_jiffies
3349 (priv->scan_pass_start, jiffies)));
3350
3351 /* Remove this scanned band from the list
3352 * of pending bands to scan */
3353 priv->scan_bands--;
3354
3355 /* If a request to abort was given, or the scan did not succeed
3356 * then we reset the scan state machine and terminate,
3357 * re-queuing another scan if one has been requested */
3358 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
3359 IWL_DEBUG_INFO("Aborted scan completed.\n");
3360 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
3361 } else {
3362 /* If there are more bands on this scan pass reschedule */
3363 if (priv->scan_bands > 0)
3364 goto reschedule;
3365 }
3366
3367 priv->last_scan_jiffies = jiffies;
7878a5a4 3368 priv->next_scan_jiffies = 0;
b481de9c
ZY		 3369 IWL_DEBUG_INFO("Setting scan to off\n");
3370
3371 clear_bit(STATUS_SCANNING, &priv->status);
3372
3373 IWL_DEBUG_INFO("Scan took %dms\n",
3374 jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
3375
3376 queue_work(priv->workqueue, &priv->scan_completed);
3377
3378 return;
3379
3380reschedule:
3381 priv->scan_pass_start = jiffies;
3382 queue_work(priv->workqueue, &priv->request_scan);
3383}
3384
3385/* Handle notification from uCode that card's power state is changing
3386 * due to software, hardware, or critical temperature RFKILL */
bb8c093b
CH		 3387static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
3388 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3389{
bb8c093b 3390 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3391 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
3392 unsigned long status = priv->status;
3393
3394 IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
3395 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3396 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
3397
bb8c093b 3398 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 3399 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3400
3401 if (flags & HW_CARD_DISABLED)
3402 set_bit(STATUS_RF_KILL_HW, &priv->status);
3403 else
3404 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3405
3406
3407 if (flags & SW_CARD_DISABLED)
3408 set_bit(STATUS_RF_KILL_SW, &priv->status);
3409 else
3410 clear_bit(STATUS_RF_KILL_SW, &priv->status);
3411
bb8c093b 3412 iwl3945_scan_cancel(priv);
b481de9c
ZY		 3413
3414 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
3415 test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
3416 (test_bit(STATUS_RF_KILL_SW, &status) !=
3417 test_bit(STATUS_RF_KILL_SW, &priv->status)))
3418 queue_work(priv->workqueue, &priv->rf_kill);
3419 else
3420 wake_up_interruptible(&priv->wait_command_queue);
3421}
3422
3423/**
bb8c093b 3424 * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY		 3425 *
3426 * Setup the RX handlers for each of the reply types sent from the uCode
3427 * to the host.
3428 *
3429 * This function chains into the hardware specific files for them to setup
3430 * any hardware specific handlers as well.
3431 */
bb8c093b 3432static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
b481de9c 3433{
bb8c093b
CH		 3434 priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
3435 priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
3436 priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
3437 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
b481de9c 3438 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
bb8c093b
CH		 3439 iwl3945_rx_spectrum_measure_notif;
3440 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
b481de9c 3441 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
bb8c093b
CH		 3442 iwl3945_rx_pm_debug_statistics_notif;
3443 priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
b481de9c 3444
9fbab516
BC		 3445 /*
3446 * The same handler is used for both the REPLY to a discrete
3447 * statistics request from the host as well as for the periodic
3448 * statistics notifications (after received beacons) from the uCode.
b481de9c 3449 */
bb8c093b
CH		 3450 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
3451 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
b481de9c 3452
bb8c093b
CH		 3453 priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
3454 priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
b481de9c 3455 priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
bb8c093b 3456 iwl3945_rx_scan_results_notif;
b481de9c 3457 priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
bb8c093b
CH		 3458 iwl3945_rx_scan_complete_notif;
3459 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
b481de9c 3460
9fbab516 3461 /* Set up hardware specific Rx handlers */
bb8c093b 3462 iwl3945_hw_rx_handler_setup(priv);
b481de9c
ZY		 3463}
3464
91c066f2
TW		 3465/**
3466 * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries
3467 * When FW advances 'R' index, all entries between old and new 'R' index
3468 * need to be reclaimed.
3469 */
3470static void iwl3945_cmd_queue_reclaim(struct iwl3945_priv *priv,
3471 int txq_id, int index)
3472{
3473 struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
3474 struct iwl3945_queue *q = &txq->q;
3475 int nfreed = 0;
3476
3477 if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) {
3478 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
3479 "is out of range [0-%d] %d %d.\n", txq_id,
3480 index, q->n_bd, q->write_ptr, q->read_ptr);
3481 return;
3482 }
3483
3484 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
3485 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
3486 if (nfreed > 1) {
3487 IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
3488 q->write_ptr, q->read_ptr);
3489 queue_work(priv->workqueue, &priv->restart);
3490 break;
3491 }
3492 nfreed++;
3493 }
3494}
3495
3496
b481de9c 3497/**
bb8c093b 3498 * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
b481de9c
ZY		 3499 * @rxb: Rx buffer to reclaim
3500 *
3501 * If an Rx buffer has an async callback associated with it the callback
3502 * will be executed. The attached skb (if present) will only be freed
3503 * if the callback returns 1
3504 */
bb8c093b
CH		 3505static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
3506 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3507{
bb8c093b 3508 struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
b481de9c
ZY		 3509 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3510 int txq_id = SEQ_TO_QUEUE(sequence);
3511 int index = SEQ_TO_INDEX(sequence);
3512 int huge = sequence & SEQ_HUGE_FRAME;
3513 int cmd_index;
bb8c093b 3514 struct iwl3945_cmd *cmd;
b481de9c 3515
b481de9c
ZY		 3516 BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
3517
3518 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
3519 cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
3520
3521 /* Input error checking is done when commands are added to queue. */
3522 if (cmd->meta.flags & CMD_WANT_SKB) {
3523 cmd->meta.source->u.skb = rxb->skb;
3524 rxb->skb = NULL;
3525 } else if (cmd->meta.u.callback &&
3526 !cmd->meta.u.callback(priv, cmd, rxb->skb))
3527 rxb->skb = NULL;
3528
91c066f2 3529 iwl3945_cmd_queue_reclaim(priv, txq_id, index);
b481de9c
ZY		 3530
3531 if (!(cmd->meta.flags & CMD_ASYNC)) {
3532 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
3533 wake_up_interruptible(&priv->wait_command_queue);
3534 }
3535}
3536
3537/************************** RX-FUNCTIONS ****************************/
3538/*
3539 * Rx theory of operation
3540 *
3541 * The host allocates 32 DMA target addresses and passes the host address
3542 * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
3543 * 0 to 31
3544 *
3545 * Rx Queue Indexes
3546 * The host/firmware share two index registers for managing the Rx buffers.
3547 *
3548 * The READ index maps to the first position that the firmware may be writing
3549 * to -- the driver can read up to (but not including) this position and get
3550 * good data.
3551 * The READ index is managed by the firmware once the card is enabled.
3552 *
3553 * The WRITE index maps to the last position the driver has read from -- the
3554 * position preceding WRITE is the last slot the firmware can place a packet.
3555 *
3556 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
3557 * WRITE = READ.
3558 *
9fbab516 3559 * During initialization, the host sets up the READ queue position to the first
b481de9c
ZY		 3560 * INDEX position, and WRITE to the last (READ - 1 wrapped)
3561 *
9fbab516 3562 * When the firmware places a packet in a buffer, it will advance the READ index
b481de9c
ZY		 3563 * and fire the RX interrupt. The driver can then query the READ index and
3564 * process as many packets as possible, moving the WRITE index forward as it
3565 * resets the Rx queue buffers with new memory.
3566 *
3567 * The management in the driver is as follows:
3568 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
3569 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
01ebd063 3570 * to replenish the iwl->rxq->rx_free.
bb8c093b 3571 * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
b481de9c
ZY		 3572 * iwl->rxq is replenished and the READ INDEX is updated (updating the
3573 * 'processed' and 'read' driver indexes as well)
3574 * + A received packet is processed and handed to the kernel network stack,
3575 * detached from the iwl->rxq. The driver 'processed' index is updated.
3576 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
3577 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
3578 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
3579 * were enough free buffers and RX_STALLED is set it is cleared.
3580 *
3581 *
3582 * Driver sequence:
3583 *
9fbab516
BC		 3584 * iwl3945_rx_queue_alloc() Allocates rx_free
3585 * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
bb8c093b 3586 * iwl3945_rx_queue_restock
9fbab516 3587 * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
b481de9c
ZY		 3588 * queue, updates firmware pointers, and updates
3589 * the WRITE index. If insufficient rx_free buffers
bb8c093b 3590 * are available, schedules iwl3945_rx_replenish
b481de9c
ZY		 3591 *
3592 * -- enable interrupts --
9fbab516 3593 * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the
b481de9c
ZY		 3594 * READ INDEX, detaching the SKB from the pool.
3595 * Moves the packet buffer from queue to rx_used.
bb8c093b 3596 * Calls iwl3945_rx_queue_restock to refill any empty
b481de9c
ZY		 3597 * slots.
3598 * ...
3599 *
3600 */
3601
3602/**
bb8c093b 3603 * iwl3945_rx_queue_space - Return number of free slots available in queue.
b481de9c 3604 */
bb8c093b 3605static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
b481de9c
ZY		 3606{
3607 int s = q->read - q->write;
3608 if (s <= 0)
3609 s += RX_QUEUE_SIZE;
3610 /* keep some buffer to not confuse full and empty queue */
3611 s -= 2;
3612 if (s < 0)
3613 s = 0;
3614 return s;
3615}
3616
3617/**
bb8c093b 3618 * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
b481de9c 3619 */
bb8c093b 3620int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
b481de9c
ZY		 3621{
3622 u32 reg = 0;
3623 int rc = 0;
3624 unsigned long flags;
3625
3626 spin_lock_irqsave(&q->lock, flags);
3627
3628 if (q->need_update == 0)
3629 goto exit_unlock;
3630
6440adb5 3631 /* If power-saving is in use, make sure device is awake */
b481de9c 3632 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
bb8c093b 3633 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY		 3634
3635 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
bb8c093b 3636 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 3637 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3638 goto exit_unlock;
3639 }
3640
bb8c093b 3641 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 3642 if (rc)
3643 goto exit_unlock;
3644
6440adb5 3645 /* Device expects a multiple of 8 */
bb8c093b 3646 iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
b481de9c 3647 q->write & ~0x7);
bb8c093b 3648 iwl3945_release_nic_access(priv);
6440adb5
CB		 3649
3650 /* Else device is assumed to be awake */
b481de9c 3651 } else
6440adb5 3652 /* Device expects a multiple of 8 */
bb8c093b 3653 iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
b481de9c
ZY		 3654
3655
3656 q->need_update = 0;
3657
3658 exit_unlock:
3659 spin_unlock_irqrestore(&q->lock, flags);
3660 return rc;
3661}
3662
3663/**
9fbab516 3664 * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
b481de9c 3665 */
bb8c093b 3666static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
b481de9c
ZY		 3667 dma_addr_t dma_addr)
3668{
3669 return cpu_to_le32((u32)dma_addr);
3670}
3671
3672/**
bb8c093b 3673 * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
b481de9c 3674 *
9fbab516 3675 * If there are slots in the RX queue that need to be restocked,
b481de9c 3676 * and we have free pre-allocated buffers, fill the ranks as much
9fbab516 3677 * as we can, pulling from rx_free.
b481de9c
ZY		 3678 *
3679 * This moves the 'write' index forward to catch up with 'processed', and
3680 * also updates the memory address in the firmware to reference the new
3681 * target buffer.
3682 */
bb8c093b 3683static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
b481de9c 3684{
bb8c093b 3685 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 3686 struct list_head *element;
bb8c093b 3687 struct iwl3945_rx_mem_buffer *rxb;
b481de9c
ZY		 3688 unsigned long flags;
3689 int write, rc;
3690
3691 spin_lock_irqsave(&rxq->lock, flags);
3692 write = rxq->write & ~0x7;
bb8c093b 3693 while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
6440adb5 3694 /* Get next free Rx buffer, remove from free list */
b481de9c 3695 element = rxq->rx_free.next;
bb8c093b 3696 rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
b481de9c 3697 list_del(element);
6440adb5
CB		 3698
3699 /* Point to Rx buffer via next RBD in circular buffer */
bb8c093b 3700 rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
b481de9c
ZY		 3701 rxq->queue[rxq->write] = rxb;
3702 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
3703 rxq->free_count--;
3704 }
3705 spin_unlock_irqrestore(&rxq->lock, flags);
3706 /* If the pre-allocated buffer pool is dropping low, schedule to
3707 * refill it */
3708 if (rxq->free_count <= RX_LOW_WATERMARK)
3709 queue_work(priv->workqueue, &priv->rx_replenish);
3710
3711
6440adb5
CB		 3712 /* If we've added more space for the firmware to place data, tell it.
3713 * Increment device's write pointer in multiples of 8. */
b481de9c
ZY		 3714 if ((write != (rxq->write & ~0x7))
3715 || (abs(rxq->write - rxq->read) > 7)) {
3716 spin_lock_irqsave(&rxq->lock, flags);
3717 rxq->need_update = 1;
3718 spin_unlock_irqrestore(&rxq->lock, flags);
bb8c093b 3719 rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 3720 if (rc)
3721 return rc;
3722 }
3723
3724 return 0;
3725}
3726
3727/**
bb8c093b 3728 * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
b481de9c
ZY		 3729 *
3730 * When moving to rx_free an SKB is allocated for the slot.
3731 *
bb8c093b 3732 * Also restock the Rx queue via iwl3945_rx_queue_restock.
01ebd063 3733 * This is called as a scheduled work item (except for during initialization)
b481de9c 3734 */
5c0eef96 3735static void iwl3945_rx_allocate(struct iwl3945_priv *priv)
b481de9c 3736{
bb8c093b 3737 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 3738 struct list_head *element;
bb8c093b 3739 struct iwl3945_rx_mem_buffer *rxb;
b481de9c
ZY		 3740 unsigned long flags;
3741 spin_lock_irqsave(&rxq->lock, flags);
3742 while (!list_empty(&rxq->rx_used)) {
3743 element = rxq->rx_used.next;
bb8c093b 3744 rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
6440adb5
CB		 3745
3746 /* Alloc a new receive buffer */
b481de9c
ZY		 3747 rxb->skb =
3748 alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
3749 if (!rxb->skb) {
3750 if (net_ratelimit())
3751 printk(KERN_CRIT DRV_NAME
3752 ": Can not allocate SKB buffers\n");
3753 /* We don't reschedule replenish work here -- we will
3754 * call the restock method and if it still needs
3755 * more buffers it will schedule replenish */
3756 break;
3757 }
12342c47
ZY		 3758
3759 /* If radiotap head is required, reserve some headroom here.
3760 * The physical head count is a variable rx_stats->phy_count.
3761 * We reserve 4 bytes here. Plus these extra bytes, the
3762 * headroom of the physical head should be enough for the
3763 * radiotap head that iwl3945 supported. See iwl3945_rt.
3764 */
3765 skb_reserve(rxb->skb, 4);
3766
b481de9c
ZY		 3767 priv->alloc_rxb_skb++;
3768 list_del(element);
6440adb5
CB		 3769
3770 /* Get physical address of RB/SKB */
b481de9c
ZY		 3771 rxb->dma_addr =
3772 pci_map_single(priv->pci_dev, rxb->skb->data,
3773 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3774 list_add_tail(&rxb->list, &rxq->rx_free);
3775 rxq->free_count++;
3776 }
3777 spin_unlock_irqrestore(&rxq->lock, flags);
5c0eef96
MA		 3778}
3779
3780/*
3781 * this should be called while priv->lock is locked
3782 */
4fd1f841 3783static void __iwl3945_rx_replenish(void *data)
5c0eef96
MA		 3784{
3785 struct iwl3945_priv *priv = data;
3786
3787 iwl3945_rx_allocate(priv);
3788 iwl3945_rx_queue_restock(priv);
3789}
3790
3791
3792void iwl3945_rx_replenish(void *data)
3793{
3794 struct iwl3945_priv *priv = data;
3795 unsigned long flags;
3796
3797 iwl3945_rx_allocate(priv);
b481de9c
ZY		 3798
3799 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 3800 iwl3945_rx_queue_restock(priv);
b481de9c
ZY		 3801 spin_unlock_irqrestore(&priv->lock, flags);
3802}
3803
3804/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
9fbab516 3805 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
b481de9c
ZY		 3806 * This free routine walks the list of POOL entries and if SKB is set to
3807 * non NULL it is unmapped and freed
3808 */
bb8c093b 3809static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY		 3810{
3811 int i;
3812 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
3813 if (rxq->pool[i].skb != NULL) {
3814 pci_unmap_single(priv->pci_dev,
3815 rxq->pool[i].dma_addr,
3816 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3817 dev_kfree_skb(rxq->pool[i].skb);
3818 }
3819 }
3820
3821 pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
3822 rxq->dma_addr);
3823 rxq->bd = NULL;
3824}
3825
bb8c093b 3826int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
b481de9c 3827{
bb8c093b 3828 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 3829 struct pci_dev *dev = priv->pci_dev;
3830 int i;
3831
3832 spin_lock_init(&rxq->lock);
3833 INIT_LIST_HEAD(&rxq->rx_free);
3834 INIT_LIST_HEAD(&rxq->rx_used);
6440adb5
CB		 3835
3836 /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
b481de9c
ZY		 3837 rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
3838 if (!rxq->bd)
3839 return -ENOMEM;
6440adb5 3840
b481de9c
ZY		 3841 /* Fill the rx_used queue with _all_ of the Rx buffers */
3842 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
3843 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
6440adb5 3844
b481de9c
ZY		 3845 /* Set us so that we have processed and used all buffers, but have
3846 * not restocked the Rx queue with fresh buffers */
3847 rxq->read = rxq->write = 0;
3848 rxq->free_count = 0;
3849 rxq->need_update = 0;
3850 return 0;
3851}
3852
bb8c093b 3853void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY		 3854{
3855 unsigned long flags;
3856 int i;
3857 spin_lock_irqsave(&rxq->lock, flags);
3858 INIT_LIST_HEAD(&rxq->rx_free);
3859 INIT_LIST_HEAD(&rxq->rx_used);
3860 /* Fill the rx_used queue with _all_ of the Rx buffers */
3861 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
3862 /* In the reset function, these buffers may have been allocated
3863 * to an SKB, so we need to unmap and free potential storage */
3864 if (rxq->pool[i].skb != NULL) {
3865 pci_unmap_single(priv->pci_dev,
3866 rxq->pool[i].dma_addr,
3867 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3868 priv->alloc_rxb_skb--;
3869 dev_kfree_skb(rxq->pool[i].skb);
3870 rxq->pool[i].skb = NULL;
3871 }
3872 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
3873 }
3874
3875 /* Set us so that we have processed and used all buffers, but have
3876 * not restocked the Rx queue with fresh buffers */
3877 rxq->read = rxq->write = 0;
3878 rxq->free_count = 0;
3879 spin_unlock_irqrestore(&rxq->lock, flags);
3880}
3881
3882/* Convert linear signal-to-noise ratio into dB */
3883static u8 ratio2dB[100] = {
3884/* 0 1 2 3 4 5 6 7 8 9 */
3885 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
3886 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
3887 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
3888 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
3889 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
3890 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
3891 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
3892 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
3893 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
3894 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
3895};
3896
3897/* Calculates a relative dB value from a ratio of linear
3898 * (i.e. not dB) signal levels.
3899 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
bb8c093b 3900int iwl3945_calc_db_from_ratio(int sig_ratio)
b481de9c 3901{
221c80cf
AB		 3902 /* 1000:1 or higher just report as 60 dB */
3903 if (sig_ratio >= 1000)
b481de9c
ZY		 3904 return 60;
3905
221c80cf 3906 /* 100:1 or higher, divide by 10 and use table,
b481de9c 3907 * add 20 dB to make up for divide by 10 */
221c80cf 3908 if (sig_ratio >= 100)
b481de9c
ZY		 3909 return (20 + (int)ratio2dB[sig_ratio/10]);
3910
3911 /* We shouldn't see this */
3912 if (sig_ratio < 1)
3913 return 0;
3914
3915 /* Use table for ratios 1:1 - 99:1 */
3916 return (int)ratio2dB[sig_ratio];
3917}
3918
3919#define PERFECT_RSSI (-20) /* dBm */
3920#define WORST_RSSI (-95) /* dBm */
3921#define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
3922
3923/* Calculate an indication of rx signal quality (a percentage, not dBm!).
3924 * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
3925 * about formulas used below. */
bb8c093b 3926int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
b481de9c
ZY		 3927{
3928 int sig_qual;
3929 int degradation = PERFECT_RSSI - rssi_dbm;
3930
3931 /* If we get a noise measurement, use signal-to-noise ratio (SNR)
3932 * as indicator; formula is (signal dbm - noise dbm).
3933 * SNR at or above 40 is a great signal (100%).
3934 * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
3935 * Weakest usable signal is usually 10 - 15 dB SNR. */
3936 if (noise_dbm) {
3937 if (rssi_dbm - noise_dbm >= 40)
3938 return 100;
3939 else if (rssi_dbm < noise_dbm)
3940 return 0;
3941 sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
3942
3943 /* Else use just the signal level.
3944 * This formula is a least squares fit of data points collected and
3945 * compared with a reference system that had a percentage (%) display
3946 * for signal quality. */
3947 } else
3948 sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
3949 (15 * RSSI_RANGE + 62 * degradation)) /
3950 (RSSI_RANGE * RSSI_RANGE);
3951
3952 if (sig_qual > 100)
3953 sig_qual = 100;
3954 else if (sig_qual < 1)
3955 sig_qual = 0;
3956
3957 return sig_qual;
3958}
3959
3960/**
9fbab516 3961 * iwl3945_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY		 3962 *
3963 * Uses the priv->rx_handlers callback function array to invoke
3964 * the appropriate handlers, including command responses,
3965 * frame-received notifications, and other notifications.
3966 */
bb8c093b 3967static void iwl3945_rx_handle(struct iwl3945_priv *priv)
b481de9c 3968{
bb8c093b
CH		 3969 struct iwl3945_rx_mem_buffer *rxb;
3970 struct iwl3945_rx_packet *pkt;
3971 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 3972 u32 r, i;
3973 int reclaim;
3974 unsigned long flags;
5c0eef96 3975 u8 fill_rx = 0;
d68ab680 3976 u32 count = 8;
b481de9c 3977
6440adb5
CB		 3978 /* uCode's read index (stored in shared DRAM) indicates the last Rx
3979 * buffer that the driver may process (last buffer filled by ucode). */
bb8c093b 3980 r = iwl3945_hw_get_rx_read(priv);
b481de9c
ZY		 3981 i = rxq->read;
3982
5c0eef96
MA		 3983 if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
3984 fill_rx = 1;
b481de9c
ZY		 3985 /* Rx interrupt, but nothing sent from uCode */
3986 if (i == r)
3987 IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
3988
3989 while (i != r) {
3990 rxb = rxq->queue[i];
3991
9fbab516 3992 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY		 3993 * then a bug has been introduced in the queue refilling
3994 * routines -- catch it here */
3995 BUG_ON(rxb == NULL);
3996
3997 rxq->queue[i] = NULL;
3998
3999 pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
4000 IWL_RX_BUF_SIZE,
4001 PCI_DMA_FROMDEVICE);
bb8c093b 4002 pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
b481de9c
ZY		 4003
4004 /* Reclaim a command buffer only if this packet is a response
4005 * to a (driver-originated) command.
4006 * If the packet (e.g. Rx frame) originated from uCode,
4007 * there is no command buffer to reclaim.
4008 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
4009 * but apparently a few don't get set; catch them here. */
4010 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
4011 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
4012 (pkt->hdr.cmd != REPLY_TX);
4013
4014 /* Based on type of command response or notification,
4015 * handle those that need handling via function in
bb8c093b 4016 * rx_handlers table. See iwl3945_setup_rx_handlers() */
b481de9c
ZY		 4017 if (priv->rx_handlers[pkt->hdr.cmd]) {
4018 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
4019 "r = %d, i = %d, %s, 0x%02x\n", r, i,
4020 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
4021 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
4022 } else {
4023 /* No handling needed */
4024 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
4025 "r %d i %d No handler needed for %s, 0x%02x\n",
4026 r, i, get_cmd_string(pkt->hdr.cmd),
4027 pkt->hdr.cmd);
4028 }
4029
4030 if (reclaim) {
9fbab516
BC		 4031 /* Invoke any callbacks, transfer the skb to caller, and
4032 * fire off the (possibly) blocking iwl3945_send_cmd()
b481de9c
ZY		 4033 * as we reclaim the driver command queue */
4034 if (rxb && rxb->skb)
bb8c093b 4035 iwl3945_tx_cmd_complete(priv, rxb);
b481de9c
ZY		 4036 else
4037 IWL_WARNING("Claim null rxb?\n");
4038 }
4039
4040 /* For now we just don't re-use anything. We can tweak this
4041 * later to try and re-use notification packets and SKBs that
4042 * fail to Rx correctly */
4043 if (rxb->skb != NULL) {
4044 priv->alloc_rxb_skb--;
4045 dev_kfree_skb_any(rxb->skb);
4046 rxb->skb = NULL;
4047 }
4048
4049 pci_unmap_single(priv->pci_dev, rxb->dma_addr,
4050 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
4051 spin_lock_irqsave(&rxq->lock, flags);
4052 list_add_tail(&rxb->list, &priv->rxq.rx_used);
4053 spin_unlock_irqrestore(&rxq->lock, flags);
4054 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA		 4055 /* If there are a lot of unused frames,
4056 * restock the Rx queue so ucode won't assert. */
4057 if (fill_rx) {
4058 count++;
4059 if (count >= 8) {
4060 priv->rxq.read = i;
4061 __iwl3945_rx_replenish(priv);
4062 count = 0;
4063 }
4064 }
b481de9c
ZY		 4065 }
4066
4067 /* Backtrack one entry */
4068 priv->rxq.read = i;
bb8c093b 4069 iwl3945_rx_queue_restock(priv);
b481de9c
ZY		 4070}
4071
6440adb5
CB		 4072/**
4073 * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
4074 */
bb8c093b
CH		 4075static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
4076 struct iwl3945_tx_queue *txq)
b481de9c
ZY		 4077{
4078 u32 reg = 0;
4079 int rc = 0;
4080 int txq_id = txq->q.id;
4081
4082 if (txq->need_update == 0)
4083 return rc;
4084
4085 /* if we're trying to save power */
4086 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
4087 /* wake up nic if it's powered down ...
4088 * uCode will wake up, and interrupt us again, so next
4089 * time we'll skip this part. */
bb8c093b 4090 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY		 4091
4092 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
4093 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
bb8c093b 4094 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 4095 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
4096 return rc;
4097 }
4098
4099 /* restore this queue's parameters in nic hardware. */
bb8c093b 4100 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 4101 if (rc)
4102 return rc;
bb8c093b 4103 iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
fc4b6853 4104 txq->q.write_ptr | (txq_id << 8));
bb8c093b 4105 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4106
4107 /* else not in power-save mode, uCode will never sleep when we're
4108 * trying to tx (during RFKILL, we're not trying to tx). */
4109 } else
bb8c093b 4110 iwl3945_write32(priv, HBUS_TARG_WRPTR,
fc4b6853 4111 txq->q.write_ptr | (txq_id << 8));
b481de9c
ZY		 4112
4113 txq->need_update = 0;
4114
4115 return rc;
4116}
4117
c8b0e6e1 4118#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4119static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon)
b481de9c 4120{
0795af57
JP		 4121 DECLARE_MAC_BUF(mac);
4122
b481de9c 4123 IWL_DEBUG_RADIO("RX CONFIG:\n");
bb8c093b 4124 iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
b481de9c
ZY		 4125 IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
4126 IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
4127 IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
4128 le32_to_cpu(rxon->filter_flags));
4129 IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
4130 IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
4131 rxon->ofdm_basic_rates);
4132 IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
0795af57
JP		 4133 IWL_DEBUG_RADIO("u8[6] node_addr: %s\n",
4134 print_mac(mac, rxon->node_addr));
4135 IWL_DEBUG_RADIO("u8[6] bssid_addr: %s\n",
4136 print_mac(mac, rxon->bssid_addr));
b481de9c
ZY		 4137 IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
4138}
4139#endif
4140
bb8c093b 4141static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
b481de9c
ZY		 4142{
4143 IWL_DEBUG_ISR("Enabling interrupts\n");
4144 set_bit(STATUS_INT_ENABLED, &priv->status);
bb8c093b 4145 iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
b481de9c
ZY		 4146}
4147
0359facc
MA		 4148
4149/* call this function to flush any scheduled tasklet */
4150static inline void iwl_synchronize_irq(struct iwl3945_priv *priv)
4151{
4152 /* wait to make sure we flush pedding tasklet*/
4153 synchronize_irq(priv->pci_dev->irq);
4154 tasklet_kill(&priv->irq_tasklet);
4155}
4156
4157
bb8c093b 4158static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
b481de9c
ZY		 4159{
4160 clear_bit(STATUS_INT_ENABLED, &priv->status);
4161
4162 /* disable interrupts from uCode/NIC to host */
bb8c093b 4163 iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY		 4164
4165 /* acknowledge/clear/reset any interrupts still pending
4166 * from uCode or flow handler (Rx/Tx DMA) */
bb8c093b
CH		 4167 iwl3945_write32(priv, CSR_INT, 0xffffffff);
4168 iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
b481de9c
ZY		 4169 IWL_DEBUG_ISR("Disabled interrupts\n");
4170}
4171
4172static const char *desc_lookup(int i)
4173{
4174 switch (i) {
4175 case 1:
4176 return "FAIL";
4177 case 2:
4178 return "BAD_PARAM";
4179 case 3:
4180 return "BAD_CHECKSUM";
4181 case 4:
4182 return "NMI_INTERRUPT";
4183 case 5:
4184 return "SYSASSERT";
4185 case 6:
4186 return "FATAL_ERROR";
4187 }
4188
4189 return "UNKNOWN";
4190}
4191
4192#define ERROR_START_OFFSET (1 * sizeof(u32))
4193#define ERROR_ELEM_SIZE (7 * sizeof(u32))
4194
bb8c093b 4195static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
b481de9c
ZY		 4196{
4197 u32 i;
4198 u32 desc, time, count, base, data1;
4199 u32 blink1, blink2, ilink1, ilink2;
4200 int rc;
4201
4202 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
4203
bb8c093b 4204 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 4205 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
4206 return;
4207 }
4208
bb8c093b 4209 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 4210 if (rc) {
4211 IWL_WARNING("Can not read from adapter at this time.\n");
4212 return;
4213 }
4214
bb8c093b 4215 count = iwl3945_read_targ_mem(priv, base);
b481de9c
ZY		 4216
4217 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
4218 IWL_ERROR("Start IWL Error Log Dump:\n");
2acae16e 4219 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
b481de9c
ZY		 4220 }
4221
4222 IWL_ERROR("Desc Time asrtPC blink2 "
4223 "ilink1 nmiPC Line\n");
4224 for (i = ERROR_START_OFFSET;
4225 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
4226 i += ERROR_ELEM_SIZE) {
bb8c093b 4227 desc = iwl3945_read_targ_mem(priv, base + i);
b481de9c 4228 time =
bb8c093b 4229 iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
b481de9c 4230 blink1 =
bb8c093b 4231 iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
b481de9c 4232 blink2 =
bb8c093b 4233 iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
b481de9c 4234 ilink1 =
bb8c093b 4235 iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
b481de9c 4236 ilink2 =
bb8c093b 4237 iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
b481de9c 4238 data1 =
bb8c093b 4239 iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
b481de9c
ZY		 4240
4241 IWL_ERROR
4242 ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
4243 desc_lookup(desc), desc, time, blink1, blink2,
4244 ilink1, ilink2, data1);
4245 }
4246
bb8c093b 4247 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4248
4249}
4250
f58177b9 4251#define EVENT_START_OFFSET (6 * sizeof(u32))
b481de9c
ZY		 4252
4253/**
bb8c093b 4254 * iwl3945_print_event_log - Dump error event log to syslog
b481de9c 4255 *
bb8c093b 4256 * NOTE: Must be called with iwl3945_grab_nic_access() already obtained!
b481de9c 4257 */
bb8c093b 4258static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
b481de9c
ZY		 4259 u32 num_events, u32 mode)
4260{
4261 u32 i;
4262 u32 base; /* SRAM byte address of event log header */
4263 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
4264 u32 ptr; /* SRAM byte address of log data */
4265 u32 ev, time, data; /* event log data */
4266
4267 if (num_events == 0)
4268 return;
4269
4270 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
4271
4272 if (mode == 0)
4273 event_size = 2 * sizeof(u32);
4274 else
4275 event_size = 3 * sizeof(u32);
4276
4277 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
4278
4279 /* "time" is actually "data" for mode 0 (no timestamp).
4280 * place event id # at far right for easier visual parsing. */
4281 for (i = 0; i < num_events; i++) {
bb8c093b 4282 ev = iwl3945_read_targ_mem(priv, ptr);
b481de9c 4283 ptr += sizeof(u32);
bb8c093b 4284 time = iwl3945_read_targ_mem(priv, ptr);
b481de9c
ZY		 4285 ptr += sizeof(u32);
4286 if (mode == 0)
4287 IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
4288 else {
bb8c093b 4289 data = iwl3945_read_targ_mem(priv, ptr);
b481de9c
ZY		 4290 ptr += sizeof(u32);
4291 IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
4292 }
4293 }
4294}
4295
bb8c093b 4296static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
b481de9c
ZY		 4297{
4298 int rc;
4299 u32 base; /* SRAM byte address of event log header */
4300 u32 capacity; /* event log capacity in # entries */
4301 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
4302 u32 num_wraps; /* # times uCode wrapped to top of log */
4303 u32 next_entry; /* index of next entry to be written by uCode */
4304 u32 size; /* # entries that we'll print */
4305
4306 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 4307 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 4308 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
4309 return;
4310 }
4311
bb8c093b 4312 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 4313 if (rc) {
4314 IWL_WARNING("Can not read from adapter at this time.\n");
4315 return;
4316 }
4317
4318 /* event log header */
bb8c093b
CH		 4319 capacity = iwl3945_read_targ_mem(priv, base);
4320 mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
4321 num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
4322 next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
b481de9c
ZY		 4323
4324 size = num_wraps ? capacity : next_entry;
4325
4326 /* bail out if nothing in log */
4327 if (size == 0) {
583fab37 4328 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
bb8c093b 4329 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4330 return;
4331 }
4332
583fab37 4333 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
b481de9c
ZY		 4334 size, num_wraps);
4335
4336 /* if uCode has wrapped back to top of log, start at the oldest entry,
4337 * i.e the next one that uCode would fill. */
4338 if (num_wraps)
bb8c093b 4339 iwl3945_print_event_log(priv, next_entry,
b481de9c
ZY		 4340 capacity - next_entry, mode);
4341
4342 /* (then/else) start at top of log */
bb8c093b 4343 iwl3945_print_event_log(priv, 0, next_entry, mode);
b481de9c 4344
bb8c093b 4345 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4346}
4347
4348/**
bb8c093b 4349 * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
b481de9c 4350 */
bb8c093b 4351static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
b481de9c 4352{
bb8c093b 4353 /* Set the FW error flag -- cleared on iwl3945_down */
b481de9c
ZY		 4354 set_bit(STATUS_FW_ERROR, &priv->status);
4355
4356 /* Cancel currently queued command. */
4357 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
4358
c8b0e6e1 4359#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 4360 if (iwl3945_debug_level & IWL_DL_FW_ERRORS) {
4361 iwl3945_dump_nic_error_log(priv);
4362 iwl3945_dump_nic_event_log(priv);
4363 iwl3945_print_rx_config_cmd(&priv->staging_rxon);
b481de9c
ZY		 4364 }
4365#endif
4366
4367 wake_up_interruptible(&priv->wait_command_queue);
4368
4369 /* Keep the restart process from trying to send host
4370 * commands by clearing the INIT status bit */
4371 clear_bit(STATUS_READY, &priv->status);
4372
4373 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
4374 IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
4375 "Restarting adapter due to uCode error.\n");
4376
bb8c093b 4377 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 4378 memcpy(&priv->recovery_rxon, &priv->active_rxon,
4379 sizeof(priv->recovery_rxon));
4380 priv->error_recovering = 1;
4381 }
4382 queue_work(priv->workqueue, &priv->restart);
4383 }
4384}
4385
bb8c093b 4386static void iwl3945_error_recovery(struct iwl3945_priv *priv)
b481de9c
ZY		 4387{
4388 unsigned long flags;
4389
4390 memcpy(&priv->staging_rxon, &priv->recovery_rxon,
4391 sizeof(priv->staging_rxon));
4392 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 4393 iwl3945_commit_rxon(priv);
b481de9c 4394
bb8c093b 4395 iwl3945_add_station(priv, priv->bssid, 1, 0);
b481de9c
ZY		 4396
4397 spin_lock_irqsave(&priv->lock, flags);
4398 priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
4399 priv->error_recovering = 0;
4400 spin_unlock_irqrestore(&priv->lock, flags);
4401}
4402
bb8c093b 4403static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
b481de9c
ZY		 4404{
4405 u32 inta, handled = 0;
4406 u32 inta_fh;
4407 unsigned long flags;
c8b0e6e1 4408#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 4409 u32 inta_mask;
4410#endif
4411
4412 spin_lock_irqsave(&priv->lock, flags);
4413
4414 /* Ack/clear/reset pending uCode interrupts.
4415 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
4416 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
bb8c093b
CH		 4417 inta = iwl3945_read32(priv, CSR_INT);
4418 iwl3945_write32(priv, CSR_INT, inta);
b481de9c
ZY		 4419
4420 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
4421 * Any new interrupts that happen after this, either while we're
4422 * in this tasklet, or later, will show up in next ISR/tasklet. */
bb8c093b
CH		 4423 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
4424 iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 4425
c8b0e6e1 4426#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4427 if (iwl3945_debug_level & IWL_DL_ISR) {
9fbab516
BC		 4428 /* just for debug */
4429 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
b481de9c
ZY		 4430 IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4431 inta, inta_mask, inta_fh);
4432 }
4433#endif
4434
4435 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
4436 * atomic, make sure that inta covers all the interrupts that
4437 * we've discovered, even if FH interrupt came in just after
4438 * reading CSR_INT. */
6f83eaa1 4439 if (inta_fh & CSR39_FH_INT_RX_MASK)
b481de9c 4440 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 4441 if (inta_fh & CSR39_FH_INT_TX_MASK)
b481de9c
ZY		 4442 inta |= CSR_INT_BIT_FH_TX;
4443
4444 /* Now service all interrupt bits discovered above. */
4445 if (inta & CSR_INT_BIT_HW_ERR) {
4446 IWL_ERROR("Microcode HW error detected. Restarting.\n");
4447
4448 /* Tell the device to stop sending interrupts */
bb8c093b 4449 iwl3945_disable_interrupts(priv);
b481de9c 4450
bb8c093b 4451 iwl3945_irq_handle_error(priv);
b481de9c
ZY		 4452
4453 handled |= CSR_INT_BIT_HW_ERR;
4454
4455 spin_unlock_irqrestore(&priv->lock, flags);
4456
4457 return;
4458 }
4459
c8b0e6e1 4460#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4461 if (iwl3945_debug_level & (IWL_DL_ISR)) {
b481de9c 4462 /* NIC fires this, but we don't use it, redundant with WAKEUP */
25c03d8e
JP		 4463 if (inta & CSR_INT_BIT_SCD)
4464 IWL_DEBUG_ISR("Scheduler finished to transmit "
4465 "the frame/frames.\n");
b481de9c
ZY		 4466
4467 /* Alive notification via Rx interrupt will do the real work */
4468 if (inta & CSR_INT_BIT_ALIVE)
4469 IWL_DEBUG_ISR("Alive interrupt\n");
4470 }
4471#endif
4472 /* Safely ignore these bits for debug checks below */
25c03d8e 4473 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c
ZY		 4474
4475 /* HW RF KILL switch toggled (4965 only) */
4476 if (inta & CSR_INT_BIT_RF_KILL) {
4477 int hw_rf_kill = 0;
bb8c093b 4478 if (!(iwl3945_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY		 4479 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
4480 hw_rf_kill = 1;
4481
4482 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR,
4483 "RF_KILL bit toggled to %s.\n",
4484 hw_rf_kill ? "disable radio":"enable radio");
4485
4486 /* Queue restart only if RF_KILL switch was set to "kill"
4487 * when we loaded driver, and is now set to "enable".
4488 * After we're Alive, RF_KILL gets handled by
3230455d 4489 * iwl3945_rx_card_state_notif() */
53e49093
ZY		 4490 if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) {
4491 clear_bit(STATUS_RF_KILL_HW, &priv->status);
b481de9c 4492 queue_work(priv->workqueue, &priv->restart);
53e49093 4493 }
b481de9c
ZY		 4494
4495 handled |= CSR_INT_BIT_RF_KILL;
4496 }
4497
4498 /* Chip got too hot and stopped itself (4965 only) */
4499 if (inta & CSR_INT_BIT_CT_KILL) {
4500 IWL_ERROR("Microcode CT kill error detected.\n");
4501 handled |= CSR_INT_BIT_CT_KILL;
4502 }
4503
4504 /* Error detected by uCode */
4505 if (inta & CSR_INT_BIT_SW_ERR) {
4506 IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
4507 inta);
bb8c093b 4508 iwl3945_irq_handle_error(priv);
b481de9c
ZY		 4509 handled |= CSR_INT_BIT_SW_ERR;
4510 }
4511
4512 /* uCode wakes up after power-down sleep */
4513 if (inta & CSR_INT_BIT_WAKEUP) {
4514 IWL_DEBUG_ISR("Wakeup interrupt\n");
bb8c093b
CH		 4515 iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
4516 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
4517 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
4518 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
4519 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
4520 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
4521 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
b481de9c
ZY		 4522
4523 handled |= CSR_INT_BIT_WAKEUP;
4524 }
4525
4526 /* All uCode command responses, including Tx command responses,
4527 * Rx "responses" (frame-received notification), and other
4528 * notifications from uCode come through here*/
4529 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
bb8c093b 4530 iwl3945_rx_handle(priv);
b481de9c
ZY		 4531 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
4532 }
4533
4534 if (inta & CSR_INT_BIT_FH_TX) {
4535 IWL_DEBUG_ISR("Tx interrupt\n");
4536
bb8c093b
CH		 4537 iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
4538 if (!iwl3945_grab_nic_access(priv)) {
4539 iwl3945_write_direct32(priv,
b481de9c
ZY		 4540 FH_TCSR_CREDIT
4541 (ALM_FH_SRVC_CHNL), 0x0);
bb8c093b 4542 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4543 }
4544 handled |= CSR_INT_BIT_FH_TX;
4545 }
4546
4547 if (inta & ~handled)
4548 IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
4549
4550 if (inta & ~CSR_INI_SET_MASK) {
4551 IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
4552 inta & ~CSR_INI_SET_MASK);
4553 IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
4554 }
4555
4556 /* Re-enable all interrupts */
0359facc
MA		 4557 /* only Re-enable if disabled by irq */
4558 if (test_bit(STATUS_INT_ENABLED, &priv->status))
4559 iwl3945_enable_interrupts(priv);
b481de9c 4560
c8b0e6e1 4561#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 4562 if (iwl3945_debug_level & (IWL_DL_ISR)) {
4563 inta = iwl3945_read32(priv, CSR_INT);
4564 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
4565 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY		 4566 IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4567 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
4568 }
4569#endif
4570 spin_unlock_irqrestore(&priv->lock, flags);
4571}
4572
bb8c093b 4573static irqreturn_t iwl3945_isr(int irq, void *data)
b481de9c 4574{
bb8c093b 4575 struct iwl3945_priv *priv = data;
b481de9c
ZY		 4576 u32 inta, inta_mask;
4577 u32 inta_fh;
4578 if (!priv)
4579 return IRQ_NONE;
4580
4581 spin_lock(&priv->lock);
4582
4583 /* Disable (but don't clear!) interrupts here to avoid
4584 * back-to-back ISRs and sporadic interrupts from our NIC.
4585 * If we have something to service, the tasklet will re-enable ints.
4586 * If we *don't* have something, we'll re-enable before leaving here. */
bb8c093b
CH		 4587 inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */
4588 iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY		 4589
4590 /* Discover which interrupts are active/pending */
bb8c093b
CH		 4591 inta = iwl3945_read32(priv, CSR_INT);
4592 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY		 4593
4594 /* Ignore interrupt if there's nothing in NIC to service.
4595 * This may be due to IRQ shared with another device,
4596 * or due to sporadic interrupts thrown from our NIC. */
4597 if (!inta && !inta_fh) {
4598 IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
4599 goto none;
4600 }
4601
4602 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
4603 /* Hardware disappeared */
4604 IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta);
cb4da1a3 4605 goto unplugged;
b481de9c
ZY		 4606 }
4607
4608 IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4609 inta, inta_mask, inta_fh);
4610
25c03d8e
JP		 4611 inta &= ~CSR_INT_BIT_SCD;
4612
bb8c093b 4613 /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
25c03d8e
JP		 4614 if (likely(inta || inta_fh))
4615 tasklet_schedule(&priv->irq_tasklet);
cb4da1a3 4616unplugged:
b481de9c
ZY		 4617 spin_unlock(&priv->lock);
4618
4619 return IRQ_HANDLED;
4620
4621 none:
4622 /* re-enable interrupts here since we don't have anything to service. */
0359facc
MA		 4623 /* only Re-enable if disabled by irq */
4624 if (test_bit(STATUS_INT_ENABLED, &priv->status))
4625 iwl3945_enable_interrupts(priv);
b481de9c
ZY		 4626 spin_unlock(&priv->lock);
4627 return IRQ_NONE;
4628}
4629
4630/************************** EEPROM BANDS ****************************
4631 *
bb8c093b 4632 * The iwl3945_eeprom_band definitions below provide the mapping from the
b481de9c
ZY		 4633 * EEPROM contents to the specific channel number supported for each
4634 * band.
4635 *
bb8c093b 4636 * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3
b481de9c
ZY		 4637 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
4638 * The specific geography and calibration information for that channel
4639 * is contained in the eeprom map itself.
4640 *
4641 * During init, we copy the eeprom information and channel map
4642 * information into priv->channel_info_24/52 and priv->channel_map_24/52
4643 *
4644 * channel_map_24/52 provides the index in the channel_info array for a
4645 * given channel. We have to have two separate maps as there is channel
4646 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
4647 * band_2
4648 *
4649 * A value of 0xff stored in the channel_map indicates that the channel
4650 * is not supported by the hardware at all.
4651 *
4652 * A value of 0xfe in the channel_map indicates that the channel is not
4653 * valid for Tx with the current hardware. This means that
4654 * while the system can tune and receive on a given channel, it may not
4655 * be able to associate or transmit any frames on that
4656 * channel. There is no corresponding channel information for that
4657 * entry.
4658 *
4659 *********************************************************************/
4660
4661/* 2.4 GHz */
bb8c093b 4662static const u8 iwl3945_eeprom_band_1[14] = {
b481de9c
ZY		 4663 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
4664};
4665
4666/* 5.2 GHz bands */
9fbab516 4667static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
b481de9c
ZY		 4668 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
4669};
4670
9fbab516 4671static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
b481de9c
ZY		 4672 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
4673};
4674
bb8c093b 4675static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
b481de9c
ZY		 4676 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
4677};
4678
bb8c093b 4679static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
b481de9c
ZY		 4680 145, 149, 153, 157, 161, 165
4681};
4682
bb8c093b 4683static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
b481de9c 4684 int *eeprom_ch_count,
bb8c093b 4685 const struct iwl3945_eeprom_channel
b481de9c
ZY		 4686 **eeprom_ch_info,
4687 const u8 **eeprom_ch_index)
4688{
4689 switch (band) {
4690 case 1: /* 2.4GHz band */
bb8c093b 4691 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
b481de9c 4692 *eeprom_ch_info = priv->eeprom.band_1_channels;
bb8c093b 4693 *eeprom_ch_index = iwl3945_eeprom_band_1;
b481de9c 4694 break;
9fbab516 4695 case 2: /* 4.9GHz band */
bb8c093b 4696 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
b481de9c 4697 *eeprom_ch_info = priv->eeprom.band_2_channels;
bb8c093b 4698 *eeprom_ch_index = iwl3945_eeprom_band_2;
b481de9c
ZY		 4699 break;
4700 case 3: /* 5.2GHz band */
bb8c093b 4701 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
b481de9c 4702 *eeprom_ch_info = priv->eeprom.band_3_channels;
bb8c093b 4703 *eeprom_ch_index = iwl3945_eeprom_band_3;
b481de9c 4704 break;
9fbab516 4705 case 4: /* 5.5GHz band */
bb8c093b 4706 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
b481de9c 4707 *eeprom_ch_info = priv->eeprom.band_4_channels;
bb8c093b 4708 *eeprom_ch_index = iwl3945_eeprom_band_4;
b481de9c 4709 break;
9fbab516 4710 case 5: /* 5.7GHz band */
bb8c093b 4711 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
b481de9c 4712 *eeprom_ch_info = priv->eeprom.band_5_channels;
bb8c093b 4713 *eeprom_ch_index = iwl3945_eeprom_band_5;
b481de9c
ZY		 4714 break;
4715 default:
4716 BUG();
4717 return;
4718 }
4719}
4720
6440adb5
CB		 4721/**
4722 * iwl3945_get_channel_info - Find driver's private channel info
4723 *
4724 * Based on band and channel number.
4725 */
bb8c093b 4726const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv,
8318d78a 4727 enum ieee80211_band band, u16 channel)
b481de9c
ZY		 4728{
4729 int i;
4730
8318d78a
JB		 4731 switch (band) {
4732 case IEEE80211_BAND_5GHZ:
b481de9c
ZY		 4733 for (i = 14; i < priv->channel_count; i++) {
4734 if (priv->channel_info[i].channel == channel)
4735 return &priv->channel_info[i];
4736 }
4737 break;
4738
8318d78a 4739 case IEEE80211_BAND_2GHZ:
b481de9c
ZY		 4740 if (channel >= 1 && channel <= 14)
4741 return &priv->channel_info[channel - 1];
4742 break;
8318d78a
JB		 4743 case IEEE80211_NUM_BANDS:
4744 WARN_ON(1);
b481de9c
ZY		 4745 }
4746
4747 return NULL;
4748}
4749
4750#define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
4751 ? # x " " : "")
4752
6440adb5
CB		 4753/**
4754 * iwl3945_init_channel_map - Set up driver's info for all possible channels
4755 */
bb8c093b 4756static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
b481de9c
ZY		 4757{
4758 int eeprom_ch_count = 0;
4759 const u8 *eeprom_ch_index = NULL;
bb8c093b 4760 const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL;
b481de9c 4761 int band, ch;
bb8c093b 4762 struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 4763
4764 if (priv->channel_count) {
4765 IWL_DEBUG_INFO("Channel map already initialized.\n");
4766 return 0;
4767 }
4768
4769 if (priv->eeprom.version < 0x2f) {
4770 IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
4771 priv->eeprom.version);
4772 return -EINVAL;
4773 }
4774
4775 IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
4776
4777 priv->channel_count =
bb8c093b
CH		 4778 ARRAY_SIZE(iwl3945_eeprom_band_1) +
4779 ARRAY_SIZE(iwl3945_eeprom_band_2) +
4780 ARRAY_SIZE(iwl3945_eeprom_band_3) +
4781 ARRAY_SIZE(iwl3945_eeprom_band_4) +
4782 ARRAY_SIZE(iwl3945_eeprom_band_5);
b481de9c
ZY		 4783
4784 IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
4785
bb8c093b 4786 priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) *
b481de9c
ZY		 4787 priv->channel_count, GFP_KERNEL);
4788 if (!priv->channel_info) {
4789 IWL_ERROR("Could not allocate channel_info\n");
4790 priv->channel_count = 0;
4791 return -ENOMEM;
4792 }
4793
4794 ch_info = priv->channel_info;
4795
4796 /* Loop through the 5 EEPROM bands adding them in order to the
4797 * channel map we maintain (that contains additional information than
4798 * what just in the EEPROM) */
4799 for (band = 1; band <= 5; band++) {
4800
bb8c093b 4801 iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
b481de9c
ZY		 4802 &eeprom_ch_info, &eeprom_ch_index);
4803
4804 /* Loop through each band adding each of the channels */
4805 for (ch = 0; ch < eeprom_ch_count; ch++) {
4806 ch_info->channel = eeprom_ch_index[ch];
8318d78a
JB		 4807 ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
4808 IEEE80211_BAND_5GHZ;
b481de9c
ZY		 4809
4810 /* permanently store EEPROM's channel regulatory flags
4811 * and max power in channel info database. */
4812 ch_info->eeprom = eeprom_ch_info[ch];
4813
4814 /* Copy the run-time flags so they are there even on
4815 * invalid channels */
4816 ch_info->flags = eeprom_ch_info[ch].flags;
4817
4818 if (!(is_channel_valid(ch_info))) {
4819 IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
4820 "No traffic\n",
4821 ch_info->channel,
4822 ch_info->flags,
4823 is_channel_a_band(ch_info) ?
4824 "5.2" : "2.4");
4825 ch_info++;
4826 continue;
4827 }
4828
4829 /* Initialize regulatory-based run-time data */
4830 ch_info->max_power_avg = ch_info->curr_txpow =
4831 eeprom_ch_info[ch].max_power_avg;
4832 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
4833 ch_info->min_power = 0;
4834
fe7c4040 4835 IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
b481de9c
ZY		 4836 " %ddBm): Ad-Hoc %ssupported\n",
4837 ch_info->channel,
4838 is_channel_a_band(ch_info) ?
4839 "5.2" : "2.4",
8211ef78 4840 CHECK_AND_PRINT(VALID),
b481de9c
ZY		 4841 CHECK_AND_PRINT(IBSS),
4842 CHECK_AND_PRINT(ACTIVE),
4843 CHECK_AND_PRINT(RADAR),
4844 CHECK_AND_PRINT(WIDE),
b481de9c
ZY		 4845 CHECK_AND_PRINT(DFS),
4846 eeprom_ch_info[ch].flags,
4847 eeprom_ch_info[ch].max_power_avg,
4848 ((eeprom_ch_info[ch].
4849 flags & EEPROM_CHANNEL_IBSS)
4850 && !(eeprom_ch_info[ch].
4851 flags & EEPROM_CHANNEL_RADAR))
4852 ? "" : "not ");
4853
4854 /* Set the user_txpower_limit to the highest power
4855 * supported by any channel */
4856 if (eeprom_ch_info[ch].max_power_avg >
4857 priv->user_txpower_limit)
4858 priv->user_txpower_limit =
4859 eeprom_ch_info[ch].max_power_avg;
4860
4861 ch_info++;
4862 }
4863 }
4864
6440adb5 4865 /* Set up txpower settings in driver for all channels */
b481de9c
ZY		 4866 if (iwl3945_txpower_set_from_eeprom(priv))
4867 return -EIO;
4868
4869 return 0;
4870}
4871
849e0dce
RC		 4872/*
4873 * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
4874 */
4875static void iwl3945_free_channel_map(struct iwl3945_priv *priv)
4876{
4877 kfree(priv->channel_info);
4878 priv->channel_count = 0;
4879}
4880
b481de9c
ZY		 4881/* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
4882 * sending probe req. This should be set long enough to hear probe responses
4883 * from more than one AP. */
4884#define IWL_ACTIVE_DWELL_TIME_24 (20) /* all times in msec */
4885#define IWL_ACTIVE_DWELL_TIME_52 (10)
4886
4887/* For faster active scanning, scan will move to the next channel if fewer than
4888 * PLCP_QUIET_THRESH packets are heard on this channel within
4889 * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
4890 * time if it's a quiet channel (nothing responded to our probe, and there's
4891 * no other traffic).
4892 * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
4893#define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
4894#define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(5) /* msec */
4895
4896/* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
4897 * Must be set longer than active dwell time.
4898 * For the most reliable scan, set > AP beacon interval (typically 100msec). */
4899#define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
4900#define IWL_PASSIVE_DWELL_TIME_52 (10)
4901#define IWL_PASSIVE_DWELL_BASE (100)
4902#define IWL_CHANNEL_TUNE_TIME 5
4903
8318d78a
JB		 4904static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv,
4905 enum ieee80211_band band)
b481de9c 4906{
8318d78a 4907 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 4908 return IWL_ACTIVE_DWELL_TIME_52;
4909 else
4910 return IWL_ACTIVE_DWELL_TIME_24;
4911}
4912
8318d78a
JB		 4913static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv,
4914 enum ieee80211_band band)
b481de9c 4915{
8318d78a
JB		 4916 u16 active = iwl3945_get_active_dwell_time(priv, band);
4917 u16 passive = (band == IEEE80211_BAND_2GHZ) ?
b481de9c
ZY		 4918 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
4919 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
4920
bb8c093b 4921 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 4922 /* If we're associated, we clamp the maximum passive
4923 * dwell time to be 98% of the beacon interval (minus
4924 * 2 * channel tune time) */
4925 passive = priv->beacon_int;
4926 if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
4927 passive = IWL_PASSIVE_DWELL_BASE;
4928 passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
4929 }
4930
4931 if (passive <= active)
4932 passive = active + 1;
4933
4934 return passive;
4935}
4936
8318d78a
JB		 4937static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv,
4938 enum ieee80211_band band,
b481de9c 4939 u8 is_active, u8 direct_mask,
bb8c093b 4940 struct iwl3945_scan_channel *scan_ch)
b481de9c
ZY		 4941{
4942 const struct ieee80211_channel *channels = NULL;
8318d78a 4943 const struct ieee80211_supported_band *sband;
bb8c093b 4944 const struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 4945 u16 passive_dwell = 0;
4946 u16 active_dwell = 0;
4947 int added, i;
4948
8318d78a
JB		 4949 sband = iwl3945_get_band(priv, band);
4950 if (!sband)
b481de9c
ZY		 4951 return 0;
4952
8318d78a 4953 channels = sband->channels;
b481de9c 4954
8318d78a
JB		 4955 active_dwell = iwl3945_get_active_dwell_time(priv, band);
4956 passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
b481de9c 4957
8318d78a 4958 for (i = 0, added = 0; i < sband->n_channels; i++) {
182e2e66
JB		 4959 if (channels[i].flags & IEEE80211_CHAN_DISABLED)
4960 continue;
4961
8318d78a 4962 scan_ch->channel = channels[i].hw_value;
b481de9c 4963
8318d78a 4964 ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
b481de9c
ZY		 4965 if (!is_channel_valid(ch_info)) {
4966 IWL_DEBUG_SCAN("Channel %d is INVALID for this SKU.\n",
4967 scan_ch->channel);
4968 continue;
4969 }
4970
4971 if (!is_active || is_channel_passive(ch_info) ||
8318d78a 4972 (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN))
b481de9c
ZY		 4973 scan_ch->type = 0; /* passive */
4974 else
4975 scan_ch->type = 1; /* active */
4976
4977 if (scan_ch->type & 1)
4978 scan_ch->type |= (direct_mask << 1);
4979
b481de9c
ZY		 4980 scan_ch->active_dwell = cpu_to_le16(active_dwell);
4981 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
4982
9fbab516 4983 /* Set txpower levels to defaults */
b481de9c
ZY		 4984 scan_ch->tpc.dsp_atten = 110;
4985 /* scan_pwr_info->tpc.dsp_atten; */
4986
4987 /*scan_pwr_info->tpc.tx_gain; */
8318d78a 4988 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 4989 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
4990 else {
4991 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
4992 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
9fbab516 4993 * power level:
8a1b0245 4994 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
b481de9c
ZY		 4995 */
4996 }
4997
4998 IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
4999 scan_ch->channel,
5000 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
5001 (scan_ch->type & 1) ?
5002 active_dwell : passive_dwell);
5003
5004 scan_ch++;
5005 added++;
5006 }
5007
5008 IWL_DEBUG_SCAN("total channels to scan %d \n", added);
5009 return added;
5010}
5011
bb8c093b 5012static void iwl3945_init_hw_rates(struct iwl3945_priv *priv,
b481de9c
ZY		 5013 struct ieee80211_rate *rates)
5014{
5015 int i;
5016
5017 for (i = 0; i < IWL_RATE_COUNT; i++) {
8318d78a
JB		 5018 rates[i].bitrate = iwl3945_rates[i].ieee * 5;
5019 rates[i].hw_value = i; /* Rate scaling will work on indexes */
5020 rates[i].hw_value_short = i;
5021 rates[i].flags = 0;
5022 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
b481de9c 5023 /*
8318d78a 5024 * If CCK != 1M then set short preamble rate flag.
b481de9c 5025 */
bb8c093b 5026 rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
8318d78a 5027 0 : IEEE80211_RATE_SHORT_PREAMBLE;
b481de9c 5028 }
b481de9c
ZY		 5029 }
5030}
5031
5032/**
bb8c093b 5033 * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
b481de9c 5034 */
bb8c093b 5035static int iwl3945_init_geos(struct iwl3945_priv *priv)
b481de9c 5036{
bb8c093b 5037 struct iwl3945_channel_info *ch;
8211ef78 5038 struct ieee80211_supported_band *sband;
b481de9c
ZY		 5039 struct ieee80211_channel *channels;
5040 struct ieee80211_channel *geo_ch;
5041 struct ieee80211_rate *rates;
5042 int i = 0;
b481de9c 5043
8318d78a
JB		 5044 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
5045 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
b481de9c
ZY		 5046 IWL_DEBUG_INFO("Geography modes already initialized.\n");
5047 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
5048 return 0;
5049 }
5050
b481de9c
ZY		 5051 channels = kzalloc(sizeof(struct ieee80211_channel) *
5052 priv->channel_count, GFP_KERNEL);
8318d78a 5053 if (!channels)
b481de9c 5054 return -ENOMEM;
b481de9c 5055
8211ef78 5056 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
b481de9c
ZY		 5057 GFP_KERNEL);
5058 if (!rates) {
b481de9c
ZY		 5059 kfree(channels);
5060 return -ENOMEM;
5061 }
5062
b481de9c 5063 /* 5.2GHz channels start after the 2.4GHz channels */
8211ef78
TW		 5064 sband = &priv->bands[IEEE80211_BAND_5GHZ];
5065 sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
5066 /* just OFDM */
5067 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
5068 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
5069
5070 sband = &priv->bands[IEEE80211_BAND_2GHZ];
5071 sband->channels = channels;
5072 /* OFDM & CCK */
5073 sband->bitrates = rates;
5074 sband->n_bitrates = IWL_RATE_COUNT;
b481de9c
ZY		 5075
5076 priv->ieee_channels = channels;
5077 priv->ieee_rates = rates;
5078
bb8c093b 5079 iwl3945_init_hw_rates(priv, rates);
b481de9c 5080
8211ef78 5081 for (i = 0; i < priv->channel_count; i++) {
b481de9c
ZY		 5082 ch = &priv->channel_info[i];
5083
8211ef78
TW		 5084 /* FIXME: might be removed if scan is OK*/
5085 if (!is_channel_valid(ch))
b481de9c 5086 continue;
b481de9c
ZY		 5087
5088 if (is_channel_a_band(ch))
8211ef78 5089 sband = &priv->bands[IEEE80211_BAND_5GHZ];
8318d78a 5090 else
8211ef78 5091 sband = &priv->bands[IEEE80211_BAND_2GHZ];
b481de9c 5092
8211ef78
TW		 5093 geo_ch = &sband->channels[sband->n_channels++];
5094
5095 geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
8318d78a
JB		 5096 geo_ch->max_power = ch->max_power_avg;
5097 geo_ch->max_antenna_gain = 0xff;
7b72304d 5098 geo_ch->hw_value = ch->channel;
b481de9c
ZY		 5099
5100 if (is_channel_valid(ch)) {
8318d78a
JB		 5101 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
5102 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
b481de9c 5103
8318d78a
JB		 5104 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
5105 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
b481de9c
ZY		 5106
5107 if (ch->flags & EEPROM_CHANNEL_RADAR)
8318d78a 5108 geo_ch->flags |= IEEE80211_CHAN_RADAR;
b481de9c
ZY		 5109
5110 if (ch->max_power_avg > priv->max_channel_txpower_limit)
5111 priv->max_channel_txpower_limit =
5112 ch->max_power_avg;
8211ef78 5113 } else {
8318d78a 5114 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
8211ef78
TW		 5115 }
5116
5117 /* Save flags for reg domain usage */
5118 geo_ch->orig_flags = geo_ch->flags;
5119
5120 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
5121 ch->channel, geo_ch->center_freq,
5122 is_channel_a_band(ch) ? "5.2" : "2.4",
5123 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
5124 "restricted" : "valid",
5125 geo_ch->flags);
b481de9c
ZY		 5126 }
5127
82b9a121
TW		 5128 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
5129 priv->cfg->sku & IWL_SKU_A) {
b481de9c
ZY		 5130 printk(KERN_INFO DRV_NAME
5131 ": Incorrectly detected BG card as ABG. Please send "
5132 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
5133 priv->pci_dev->device, priv->pci_dev->subsystem_device);
82b9a121 5134 priv->cfg->sku &= ~IWL_SKU_A;
b481de9c
ZY		 5135 }
5136
5137 printk(KERN_INFO DRV_NAME
5138 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
8318d78a
JB		 5139 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
5140 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
b481de9c 5141
e0e0a67e
JL		 5142 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
5143 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
5144 &priv->bands[IEEE80211_BAND_2GHZ];
5145 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
5146 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
5147 &priv->bands[IEEE80211_BAND_5GHZ];
b481de9c 5148
b481de9c
ZY		 5149 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
5150
5151 return 0;
5152}
5153
849e0dce
RC		 5154/*
5155 * iwl3945_free_geos - undo allocations in iwl3945_init_geos
5156 */
5157static void iwl3945_free_geos(struct iwl3945_priv *priv)
5158{
849e0dce
RC		 5159 kfree(priv->ieee_channels);
5160 kfree(priv->ieee_rates);
5161 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
5162}
5163
b481de9c
ZY		 5164/******************************************************************************
5165 *
5166 * uCode download functions
5167 *
5168 ******************************************************************************/
5169
bb8c093b 5170static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv)
b481de9c 5171{
98c92211
TW		 5172 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
5173 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
5174 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
5175 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
5176 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
5177 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY		 5178}
5179
5180/**
bb8c093b 5181 * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
b481de9c
ZY		 5182 * looking at all data.
5183 */
bb8c093b 5184static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 * image, u32 len)
b481de9c
ZY		 5185{
5186 u32 val;
5187 u32 save_len = len;
5188 int rc = 0;
5189 u32 errcnt;
5190
5191 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5192
bb8c093b 5193 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5194 if (rc)
5195 return rc;
5196
bb8c093b 5197 iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
b481de9c
ZY		 5198
5199 errcnt = 0;
5200 for (; len > 0; len -= sizeof(u32), image++) {
5201 /* read data comes through single port, auto-incr addr */
5202 /* NOTE: Use the debugless read so we don't flood kernel log
5203 * if IWL_DL_IO is set */
bb8c093b 5204 val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY		 5205 if (val != le32_to_cpu(*image)) {
5206 IWL_ERROR("uCode INST section is invalid at "
5207 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5208 save_len - len, val, le32_to_cpu(*image));
5209 rc = -EIO;
5210 errcnt++;
5211 if (errcnt >= 20)
5212 break;
5213 }
5214 }
5215
bb8c093b 5216 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5217
5218 if (!errcnt)
bc434dd2 5219 IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
b481de9c
ZY		 5220
5221 return rc;
5222}
5223
5224
5225/**
bb8c093b 5226 * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
b481de9c
ZY		 5227 * using sample data 100 bytes apart. If these sample points are good,
5228 * it's a pretty good bet that everything between them is good, too.
5229 */
bb8c093b 5230static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len)
b481de9c
ZY		 5231{
5232 u32 val;
5233 int rc = 0;
5234 u32 errcnt = 0;
5235 u32 i;
5236
5237 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5238
bb8c093b 5239 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5240 if (rc)
5241 return rc;
5242
5243 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
5244 /* read data comes through single port, auto-incr addr */
5245 /* NOTE: Use the debugless read so we don't flood kernel log
5246 * if IWL_DL_IO is set */
bb8c093b 5247 iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
b481de9c 5248 i + RTC_INST_LOWER_BOUND);
bb8c093b 5249 val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY		 5250 if (val != le32_to_cpu(*image)) {
5251#if 0 /* Enable this if you want to see details */
5252 IWL_ERROR("uCode INST section is invalid at "
5253 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5254 i, val, *image);
5255#endif
5256 rc = -EIO;
5257 errcnt++;
5258 if (errcnt >= 3)
5259 break;
5260 }
5261 }
5262
bb8c093b 5263 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5264
5265 return rc;
5266}
5267
5268
5269/**
bb8c093b 5270 * iwl3945_verify_ucode - determine which instruction image is in SRAM,
b481de9c
ZY		 5271 * and verify its contents
5272 */
bb8c093b 5273static int iwl3945_verify_ucode(struct iwl3945_priv *priv)
b481de9c
ZY		 5274{
5275 __le32 *image;
5276 u32 len;
5277 int rc = 0;
5278
5279 /* Try bootstrap */
5280 image = (__le32 *)priv->ucode_boot.v_addr;
5281 len = priv->ucode_boot.len;
bb8c093b 5282 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5283 if (rc == 0) {
5284 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
5285 return 0;
5286 }
5287
5288 /* Try initialize */
5289 image = (__le32 *)priv->ucode_init.v_addr;
5290 len = priv->ucode_init.len;
bb8c093b 5291 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5292 if (rc == 0) {
5293 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
5294 return 0;
5295 }
5296
5297 /* Try runtime/protocol */
5298 image = (__le32 *)priv->ucode_code.v_addr;
5299 len = priv->ucode_code.len;
bb8c093b 5300 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5301 if (rc == 0) {
5302 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
5303 return 0;
5304 }
5305
5306 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
5307
9fbab516
BC		 5308 /* Since nothing seems to match, show first several data entries in
5309 * instruction SRAM, so maybe visual inspection will give a clue.
5310 * Selection of bootstrap image (vs. other images) is arbitrary. */
b481de9c
ZY		 5311 image = (__le32 *)priv->ucode_boot.v_addr;
5312 len = priv->ucode_boot.len;
bb8c093b 5313 rc = iwl3945_verify_inst_full(priv, image, len);
b481de9c
ZY		 5314
5315 return rc;
5316}
5317
5318
5319/* check contents of special bootstrap uCode SRAM */
bb8c093b 5320static int iwl3945_verify_bsm(struct iwl3945_priv *priv)
b481de9c
ZY		 5321{
5322 __le32 *image = priv->ucode_boot.v_addr;
5323 u32 len = priv->ucode_boot.len;
5324 u32 reg;
5325 u32 val;
5326
5327 IWL_DEBUG_INFO("Begin verify bsm\n");
5328
5329 /* verify BSM SRAM contents */
bb8c093b 5330 val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG);
b481de9c
ZY		 5331 for (reg = BSM_SRAM_LOWER_BOUND;
5332 reg < BSM_SRAM_LOWER_BOUND + len;
5333 reg += sizeof(u32), image ++) {
bb8c093b 5334 val = iwl3945_read_prph(priv, reg);
b481de9c
ZY		 5335 if (val != le32_to_cpu(*image)) {
5336 IWL_ERROR("BSM uCode verification failed at "
5337 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
5338 BSM_SRAM_LOWER_BOUND,
5339 reg - BSM_SRAM_LOWER_BOUND, len,
5340 val, le32_to_cpu(*image));
5341 return -EIO;
5342 }
5343 }
5344
5345 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
5346
5347 return 0;
5348}
5349
5350/**
bb8c093b 5351 * iwl3945_load_bsm - Load bootstrap instructions
b481de9c
ZY		 5352 *
5353 * BSM operation:
5354 *
5355 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
5356 * in special SRAM that does not power down during RFKILL. When powering back
5357 * up after power-saving sleeps (or during initial uCode load), the BSM loads
5358 * the bootstrap program into the on-board processor, and starts it.
5359 *
5360 * The bootstrap program loads (via DMA) instructions and data for a new
5361 * program from host DRAM locations indicated by the host driver in the
5362 * BSM_DRAM_* registers. Once the new program is loaded, it starts
5363 * automatically.
5364 *
5365 * When initializing the NIC, the host driver points the BSM to the
5366 * "initialize" uCode image. This uCode sets up some internal data, then
5367 * notifies host via "initialize alive" that it is complete.
5368 *
5369 * The host then replaces the BSM_DRAM_* pointer values to point to the
5370 * normal runtime uCode instructions and a backup uCode data cache buffer
5371 * (filled initially with starting data values for the on-board processor),
5372 * then triggers the "initialize" uCode to load and launch the runtime uCode,
5373 * which begins normal operation.
5374 *
5375 * When doing a power-save shutdown, runtime uCode saves data SRAM into
5376 * the backup data cache in DRAM before SRAM is powered down.
5377 *
5378 * When powering back up, the BSM loads the bootstrap program. This reloads
5379 * the runtime uCode instructions and the backup data cache into SRAM,
5380 * and re-launches the runtime uCode from where it left off.
5381 */
bb8c093b 5382static int iwl3945_load_bsm(struct iwl3945_priv *priv)
b481de9c
ZY		 5383{
5384 __le32 *image = priv->ucode_boot.v_addr;
5385 u32 len = priv->ucode_boot.len;
5386 dma_addr_t pinst;
5387 dma_addr_t pdata;
5388 u32 inst_len;
5389 u32 data_len;
5390 int rc;
5391 int i;
5392 u32 done;
5393 u32 reg_offset;
5394
5395 IWL_DEBUG_INFO("Begin load bsm\n");
5396
5397 /* make sure bootstrap program is no larger than BSM's SRAM size */
5398 if (len > IWL_MAX_BSM_SIZE)
5399 return -EINVAL;
5400
5401 /* Tell bootstrap uCode where to find the "Initialize" uCode
9fbab516 5402 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
bb8c093b 5403 * NOTE: iwl3945_initialize_alive_start() will replace these values,
b481de9c
ZY		 5404 * after the "initialize" uCode has run, to point to
5405 * runtime/protocol instructions and backup data cache. */
5406 pinst = priv->ucode_init.p_addr;
5407 pdata = priv->ucode_init_data.p_addr;
5408 inst_len = priv->ucode_init.len;
5409 data_len = priv->ucode_init_data.len;
5410
bb8c093b 5411 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5412 if (rc)
5413 return rc;
5414
bb8c093b
CH		 5415 iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5416 iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5417 iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
5418 iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
b481de9c
ZY		 5419
5420 /* Fill BSM memory with bootstrap instructions */
5421 for (reg_offset = BSM_SRAM_LOWER_BOUND;
5422 reg_offset < BSM_SRAM_LOWER_BOUND + len;
5423 reg_offset += sizeof(u32), image++)
bb8c093b 5424 _iwl3945_write_prph(priv, reg_offset,
b481de9c
ZY		 5425 le32_to_cpu(*image));
5426
bb8c093b 5427 rc = iwl3945_verify_bsm(priv);
b481de9c 5428 if (rc) {
bb8c093b 5429 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5430 return rc;
5431 }
5432
5433 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
bb8c093b
CH		 5434 iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
5435 iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG,
b481de9c 5436 RTC_INST_LOWER_BOUND);
bb8c093b 5437 iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
b481de9c
ZY		 5438
5439 /* Load bootstrap code into instruction SRAM now,
5440 * to prepare to load "initialize" uCode */
bb8c093b 5441 iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY		 5442 BSM_WR_CTRL_REG_BIT_START);
5443
5444 /* Wait for load of bootstrap uCode to finish */
5445 for (i = 0; i < 100; i++) {
bb8c093b 5446 done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG);
b481de9c
ZY		 5447 if (!(done & BSM_WR_CTRL_REG_BIT_START))
5448 break;
5449 udelay(10);
5450 }
5451 if (i < 100)
5452 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
5453 else {
5454 IWL_ERROR("BSM write did not complete!\n");
5455 return -EIO;
5456 }
5457
5458 /* Enable future boot loads whenever power management unit triggers it
5459 * (e.g. when powering back up after power-save shutdown) */
bb8c093b 5460 iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY		 5461 BSM_WR_CTRL_REG_BIT_START_EN);
5462
bb8c093b 5463 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5464
5465 return 0;
5466}
5467
bb8c093b 5468static void iwl3945_nic_start(struct iwl3945_priv *priv)
b481de9c
ZY		 5469{
5470 /* Remove all resets to allow NIC to operate */
bb8c093b 5471 iwl3945_write32(priv, CSR_RESET, 0);
b481de9c
ZY		 5472}
5473
5474/**
bb8c093b 5475 * iwl3945_read_ucode - Read uCode images from disk file.
b481de9c
ZY		 5476 *
5477 * Copy into buffers for card to fetch via bus-mastering
5478 */
bb8c093b 5479static int iwl3945_read_ucode(struct iwl3945_priv *priv)
b481de9c 5480{
bb8c093b 5481 struct iwl3945_ucode *ucode;
90e759d1 5482 int ret = 0;
b481de9c
ZY		 5483 const struct firmware *ucode_raw;
5484 /* firmware file name contains uCode/driver compatibility version */
4bf775cd 5485 const char *name = priv->cfg->fw_name;
b481de9c
ZY		 5486 u8 *src;
5487 size_t len;
5488 u32 ver, inst_size, data_size, init_size, init_data_size, boot_size;
5489
5490 /* Ask kernel firmware_class module to get the boot firmware off disk.
5491 * request_firmware() is synchronous, file is in memory on return. */
90e759d1
TW		 5492 ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev);
5493 if (ret < 0) {
5494 IWL_ERROR("%s firmware file req failed: Reason %d\n",
5495 name, ret);
b481de9c
ZY		 5496 goto error;
5497 }
5498
5499 IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
5500 name, ucode_raw->size);
5501
5502 /* Make sure that we got at least our header! */
5503 if (ucode_raw->size < sizeof(*ucode)) {
5504 IWL_ERROR("File size way too small!\n");
90e759d1 5505 ret = -EINVAL;
b481de9c
ZY		 5506 goto err_release;
5507 }
5508
5509 /* Data from ucode file: header followed by uCode images */
5510 ucode = (void *)ucode_raw->data;
5511
5512 ver = le32_to_cpu(ucode->ver);
5513 inst_size = le32_to_cpu(ucode->inst_size);
5514 data_size = le32_to_cpu(ucode->data_size);
5515 init_size = le32_to_cpu(ucode->init_size);
5516 init_data_size = le32_to_cpu(ucode->init_data_size);
5517 boot_size = le32_to_cpu(ucode->boot_size);
5518
5519 IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver);
bc434dd2
IS		 5520 IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
5521 IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
5522 IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
5523 IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
5524 IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
b481de9c
ZY		 5525
5526 /* Verify size of file vs. image size info in file's header */
5527 if (ucode_raw->size < sizeof(*ucode) +
5528 inst_size + data_size + init_size +
5529 init_data_size + boot_size) {
5530
5531 IWL_DEBUG_INFO("uCode file size %d too small\n",
5532 (int)ucode_raw->size);
90e759d1 5533 ret = -EINVAL;
b481de9c
ZY		 5534 goto err_release;
5535 }
5536
5537 /* Verify that uCode images will fit in card's SRAM */
5538 if (inst_size > IWL_MAX_INST_SIZE) {
90e759d1
TW		 5539 IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
5540 inst_size);
5541 ret = -EINVAL;
b481de9c
ZY		 5542 goto err_release;
5543 }
5544
5545 if (data_size > IWL_MAX_DATA_SIZE) {
90e759d1
TW		 5546 IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
5547 data_size);
5548 ret = -EINVAL;
b481de9c
ZY		 5549 goto err_release;
5550 }
5551 if (init_size > IWL_MAX_INST_SIZE) {
90e759d1
TW		 5552 IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
5553 init_size);
5554 ret = -EINVAL;
b481de9c
ZY		 5555 goto err_release;
5556 }
5557 if (init_data_size > IWL_MAX_DATA_SIZE) {
90e759d1
TW		 5558 IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
5559 init_data_size);
5560 ret = -EINVAL;
b481de9c
ZY		 5561 goto err_release;
5562 }
5563 if (boot_size > IWL_MAX_BSM_SIZE) {
90e759d1
TW		 5564 IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
5565 boot_size);
5566 ret = -EINVAL;
b481de9c
ZY		 5567 goto err_release;
5568 }
5569
5570 /* Allocate ucode buffers for card's bus-master loading ... */
5571
5572 /* Runtime instructions and 2 copies of data:
5573 * 1) unmodified from disk
5574 * 2) backup cache for save/restore during power-downs */
5575 priv->ucode_code.len = inst_size;
98c92211 5576 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY		 5577
5578 priv->ucode_data.len = data_size;
98c92211 5579 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY		 5580
5581 priv->ucode_data_backup.len = data_size;
98c92211 5582 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 5583
90e759d1
TW		 5584 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
5585 !priv->ucode_data_backup.v_addr)
5586 goto err_pci_alloc;
b481de9c
ZY		 5587
5588 /* Initialization instructions and data */
90e759d1
TW		 5589 if (init_size && init_data_size) {
5590 priv->ucode_init.len = init_size;
98c92211 5591 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW		 5592
5593 priv->ucode_init_data.len = init_data_size;
98c92211 5594 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW		 5595
5596 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
5597 goto err_pci_alloc;
5598 }
b481de9c
ZY		 5599
5600 /* Bootstrap (instructions only, no data) */
90e759d1
TW		 5601 if (boot_size) {
5602 priv->ucode_boot.len = boot_size;
98c92211 5603 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 5604
90e759d1
TW		 5605 if (!priv->ucode_boot.v_addr)
5606 goto err_pci_alloc;
5607 }
b481de9c
ZY		 5608
5609 /* Copy images into buffers for card's bus-master reads ... */
5610
5611 /* Runtime instructions (first block of data in file) */
5612 src = &ucode->data[0];
5613 len = priv->ucode_code.len;
90e759d1 5614 IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c
ZY		 5615 memcpy(priv->ucode_code.v_addr, src, len);
5616 IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
5617 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
5618
5619 /* Runtime data (2nd block)
bb8c093b 5620 * NOTE: Copy into backup buffer will be done in iwl3945_up() */
b481de9c
ZY		 5621 src = &ucode->data[inst_size];
5622 len = priv->ucode_data.len;
90e759d1 5623 IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY		 5624 memcpy(priv->ucode_data.v_addr, src, len);
5625 memcpy(priv->ucode_data_backup.v_addr, src, len);
5626
5627 /* Initialization instructions (3rd block) */
5628 if (init_size) {
5629 src = &ucode->data[inst_size + data_size];
5630 len = priv->ucode_init.len;
90e759d1
TW		 5631 IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
5632 len);
b481de9c
ZY		 5633 memcpy(priv->ucode_init.v_addr, src, len);
5634 }
5635
5636 /* Initialization data (4th block) */
5637 if (init_data_size) {
5638 src = &ucode->data[inst_size + data_size + init_size];
5639 len = priv->ucode_init_data.len;
5640 IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
5641 (int)len);
5642 memcpy(priv->ucode_init_data.v_addr, src, len);
5643 }
5644
5645 /* Bootstrap instructions (5th block) */
5646 src = &ucode->data[inst_size + data_size + init_size + init_data_size];
5647 len = priv->ucode_boot.len;
5648 IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
5649 (int)len);
5650 memcpy(priv->ucode_boot.v_addr, src, len);
5651
5652 /* We have our copies now, allow OS release its copies */
5653 release_firmware(ucode_raw);
5654 return 0;
5655
5656 err_pci_alloc:
5657 IWL_ERROR("failed to allocate pci memory\n");
90e759d1 5658 ret = -ENOMEM;
bb8c093b 5659 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY		 5660
5661 err_release:
5662 release_firmware(ucode_raw);
5663
5664 error:
90e759d1 5665 return ret;
b481de9c
ZY		 5666}
5667
5668
5669/**
bb8c093b 5670 * iwl3945_set_ucode_ptrs - Set uCode address location
b481de9c
ZY		 5671 *
5672 * Tell initialization uCode where to find runtime uCode.
5673 *
5674 * BSM registers initially contain pointers to initialization uCode.
5675 * We need to replace them to load runtime uCode inst and data,
5676 * and to save runtime data when powering down.
5677 */
bb8c093b 5678static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv)
b481de9c
ZY		 5679{
5680 dma_addr_t pinst;
5681 dma_addr_t pdata;
5682 int rc = 0;
5683 unsigned long flags;
5684
5685 /* bits 31:0 for 3945 */
5686 pinst = priv->ucode_code.p_addr;
5687 pdata = priv->ucode_data_backup.p_addr;
5688
5689 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5690 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5691 if (rc) {
5692 spin_unlock_irqrestore(&priv->lock, flags);
5693 return rc;
5694 }
5695
5696 /* Tell bootstrap uCode where to find image to load */
bb8c093b
CH		 5697 iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5698 iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5699 iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
b481de9c
ZY		 5700 priv->ucode_data.len);
5701
5702 /* Inst bytecount must be last to set up, bit 31 signals uCode
5703 * that all new ptr/size info is in place */
bb8c093b 5704 iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
b481de9c
ZY		 5705 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
5706
bb8c093b 5707 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5708
5709 spin_unlock_irqrestore(&priv->lock, flags);
5710
5711 IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
5712
5713 return rc;
5714}
5715
5716/**
bb8c093b 5717 * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
b481de9c
ZY		 5718 *
5719 * Called after REPLY_ALIVE notification received from "initialize" uCode.
5720 *
b481de9c 5721 * Tell "initialize" uCode to go ahead and load the runtime uCode.
9fbab516 5722 */
bb8c093b 5723static void iwl3945_init_alive_start(struct iwl3945_priv *priv)
b481de9c
ZY		 5724{
5725 /* Check alive response for "valid" sign from uCode */
5726 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
5727 /* We had an error bringing up the hardware, so take it
5728 * all the way back down so we can try again */
5729 IWL_DEBUG_INFO("Initialize Alive failed.\n");
5730 goto restart;
5731 }
5732
5733 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
5734 * This is a paranoid check, because we would not have gotten the
5735 * "initialize" alive if code weren't properly loaded. */
bb8c093b 5736 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY		 5737 /* Runtime instruction load was bad;
5738 * take it all the way back down so we can try again */
5739 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
5740 goto restart;
5741 }
5742
5743 /* Send pointers to protocol/runtime uCode image ... init code will
5744 * load and launch runtime uCode, which will send us another "Alive"
5745 * notification. */
5746 IWL_DEBUG_INFO("Initialization Alive received.\n");
bb8c093b 5747 if (iwl3945_set_ucode_ptrs(priv)) {
b481de9c
ZY		 5748 /* Runtime instruction load won't happen;
5749 * take it all the way back down so we can try again */
5750 IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
5751 goto restart;
5752 }
5753 return;
5754
5755 restart:
5756 queue_work(priv->workqueue, &priv->restart);
5757}
5758
5759
5760/**
bb8c093b 5761 * iwl3945_alive_start - called after REPLY_ALIVE notification received
b481de9c 5762 * from protocol/runtime uCode (initialization uCode's
bb8c093b 5763 * Alive gets handled by iwl3945_init_alive_start()).
b481de9c 5764 */
bb8c093b 5765static void iwl3945_alive_start(struct iwl3945_priv *priv)
b481de9c
ZY		 5766{
5767 int rc = 0;
5768 int thermal_spin = 0;
5769 u32 rfkill;
5770
5771 IWL_DEBUG_INFO("Runtime Alive received.\n");
5772
5773 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
5774 /* We had an error bringing up the hardware, so take it
5775 * all the way back down so we can try again */
5776 IWL_DEBUG_INFO("Alive failed.\n");
5777 goto restart;
5778 }
5779
5780 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
5781 * This is a paranoid check, because we would not have gotten the
5782 * "runtime" alive if code weren't properly loaded. */
bb8c093b 5783 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY		 5784 /* Runtime instruction load was bad;
5785 * take it all the way back down so we can try again */
5786 IWL_DEBUG_INFO("Bad runtime uCode load.\n");
5787 goto restart;
5788 }
5789
bb8c093b 5790 iwl3945_clear_stations_table(priv);
b481de9c 5791
bb8c093b 5792 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5793 if (rc) {
5794 IWL_WARNING("Can not read rfkill status from adapter\n");
5795 return;
5796 }
5797
bb8c093b 5798 rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG);
b481de9c 5799 IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
bb8c093b 5800 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5801
5802 if (rfkill & 0x1) {
5803 clear_bit(STATUS_RF_KILL_HW, &priv->status);
5804 /* if rfkill is not on, then wait for thermal
5805 * sensor in adapter to kick in */
bb8c093b 5806 while (iwl3945_hw_get_temperature(priv) == 0) {
b481de9c
ZY		 5807 thermal_spin++;
5808 udelay(10);
5809 }
5810
5811 if (thermal_spin)
5812 IWL_DEBUG_INFO("Thermal calibration took %dus\n",
5813 thermal_spin * 10);
5814 } else
5815 set_bit(STATUS_RF_KILL_HW, &priv->status);
5816
9fbab516 5817 /* After the ALIVE response, we can send commands to 3945 uCode */
b481de9c
ZY		 5818 set_bit(STATUS_ALIVE, &priv->status);
5819
5820 /* Clear out the uCode error bit if it is set */
5821 clear_bit(STATUS_FW_ERROR, &priv->status);
5822
bb8c093b 5823 if (iwl3945_is_rfkill(priv))
b481de9c
ZY		 5824 return;
5825
36d6825b 5826 ieee80211_wake_queues(priv->hw);
b481de9c
ZY		 5827
5828 priv->active_rate = priv->rates_mask;
5829 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
5830
bb8c093b 5831 iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
b481de9c 5832
bb8c093b
CH		 5833 if (iwl3945_is_associated(priv)) {
5834 struct iwl3945_rxon_cmd *active_rxon =
5835 (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
b481de9c
ZY		 5836
5837 memcpy(&priv->staging_rxon, &priv->active_rxon,
5838 sizeof(priv->staging_rxon));
5839 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5840 } else {
5841 /* Initialize our rx_config data */
bb8c093b 5842 iwl3945_connection_init_rx_config(priv);
b481de9c
ZY		 5843 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
5844 }
5845
9fbab516 5846 /* Configure Bluetooth device coexistence support */
bb8c093b 5847 iwl3945_send_bt_config(priv);
b481de9c
ZY		 5848
5849 /* Configure the adapter for unassociated operation */
bb8c093b 5850 iwl3945_commit_rxon(priv);
b481de9c
ZY		 5851
5852 /* At this point, the NIC is initialized and operational */
5853 priv->notif_missed_beacons = 0;
b481de9c
ZY		 5854
5855 iwl3945_reg_txpower_periodic(priv);
5856
fe00b5a5
RC		 5857 iwl3945_led_register(priv);
5858
b481de9c 5859 IWL_DEBUG_INFO("ALIVE processing complete.\n");
a9f46786 5860 set_bit(STATUS_READY, &priv->status);
5a66926a 5861 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY		 5862
5863 if (priv->error_recovering)
bb8c093b 5864 iwl3945_error_recovery(priv);
b481de9c 5865
84363e6e 5866 ieee80211_notify_mac(priv->hw, IEEE80211_NOTIFY_RE_ASSOC);
b481de9c
ZY		 5867 return;
5868
5869 restart:
5870 queue_work(priv->workqueue, &priv->restart);
5871}
5872
bb8c093b 5873static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv);
b481de9c 5874
bb8c093b 5875static void __iwl3945_down(struct iwl3945_priv *priv)
b481de9c
ZY		 5876{
5877 unsigned long flags;
5878 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
5879 struct ieee80211_conf *conf = NULL;
5880
5881 IWL_DEBUG_INFO(DRV_NAME " is going down\n");
5882
5883 conf = ieee80211_get_hw_conf(priv->hw);
5884
5885 if (!exit_pending)
5886 set_bit(STATUS_EXIT_PENDING, &priv->status);
5887
ab53d8af 5888 iwl3945_led_unregister(priv);
bb8c093b 5889 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 5890
5891 /* Unblock any waiting calls */
5892 wake_up_interruptible_all(&priv->wait_command_queue);
5893
b481de9c
ZY		 5894 /* Wipe out the EXIT_PENDING status bit if we are not actually
5895 * exiting the module */
5896 if (!exit_pending)
5897 clear_bit(STATUS_EXIT_PENDING, &priv->status);
5898
5899 /* stop and reset the on-board processor */
bb8c093b 5900 iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY		 5901
5902 /* tell the device to stop sending interrupts */
0359facc 5903 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5904 iwl3945_disable_interrupts(priv);
0359facc
MA		 5905 spin_unlock_irqrestore(&priv->lock, flags);
5906 iwl_synchronize_irq(priv);
b481de9c
ZY		 5907
5908 if (priv->mac80211_registered)
5909 ieee80211_stop_queues(priv->hw);
5910
bb8c093b 5911 /* If we have not previously called iwl3945_init() then
b481de9c 5912 * clear all bits but the RF Kill and SUSPEND bits and return */
bb8c093b 5913 if (!iwl3945_is_init(priv)) {
b481de9c
ZY		 5914 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
5915 STATUS_RF_KILL_HW |
5916 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
5917 STATUS_RF_KILL_SW |
9788864e
RC		 5918 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
5919 STATUS_GEO_CONFIGURED |
b481de9c
ZY		 5920 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
5921 STATUS_IN_SUSPEND;
5922 goto exit;
5923 }
5924
5925 /* ...otherwise clear out all the status bits but the RF Kill and
5926 * SUSPEND bits and continue taking the NIC down. */
5927 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
5928 STATUS_RF_KILL_HW |
5929 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
5930 STATUS_RF_KILL_SW |
9788864e
RC		 5931 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
5932 STATUS_GEO_CONFIGURED |
b481de9c
ZY		 5933 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
5934 STATUS_IN_SUSPEND |
5935 test_bit(STATUS_FW_ERROR, &priv->status) <<
5936 STATUS_FW_ERROR;
5937
5938 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5939 iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY		 5940 spin_unlock_irqrestore(&priv->lock, flags);
5941
bb8c093b
CH		 5942 iwl3945_hw_txq_ctx_stop(priv);
5943 iwl3945_hw_rxq_stop(priv);
b481de9c
ZY		 5944
5945 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH		 5946 if (!iwl3945_grab_nic_access(priv)) {
5947 iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
b481de9c 5948 APMG_CLK_VAL_DMA_CLK_RQT);
bb8c093b 5949 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5950 }
5951 spin_unlock_irqrestore(&priv->lock, flags);
5952
5953 udelay(5);
5954
bb8c093b
CH		 5955 iwl3945_hw_nic_stop_master(priv);
5956 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
5957 iwl3945_hw_nic_reset(priv);
b481de9c
ZY		 5958
5959 exit:
bb8c093b 5960 memset(&priv->card_alive, 0, sizeof(struct iwl3945_alive_resp));
b481de9c
ZY		 5961
5962 if (priv->ibss_beacon)
5963 dev_kfree_skb(priv->ibss_beacon);
5964 priv->ibss_beacon = NULL;
5965
5966 /* clear out any free frames */
bb8c093b 5967 iwl3945_clear_free_frames(priv);
b481de9c
ZY		 5968}
5969
bb8c093b 5970static void iwl3945_down(struct iwl3945_priv *priv)
b481de9c
ZY		 5971{
5972 mutex_lock(&priv->mutex);
bb8c093b 5973 __iwl3945_down(priv);
b481de9c 5974 mutex_unlock(&priv->mutex);
b24d22b1 5975
bb8c093b 5976 iwl3945_cancel_deferred_work(priv);
b481de9c
ZY		 5977}
5978
5979#define MAX_HW_RESTARTS 5
5980
bb8c093b 5981static int __iwl3945_up(struct iwl3945_priv *priv)
b481de9c
ZY		 5982{
5983 int rc, i;
5984
5985 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
5986 IWL_WARNING("Exit pending; will not bring the NIC up\n");
5987 return -EIO;
5988 }
5989
5990 if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
5991 IWL_WARNING("Radio disabled by SW RF kill (module "
5992 "parameter)\n");
e655b9f0
ZY		 5993 return -ENODEV;
5994 }
5995
e903fbd4
RC		 5996 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
5997 IWL_ERROR("ucode not available for device bringup\n");
5998 return -EIO;
5999 }
6000
e655b9f0
ZY		 6001 /* If platform's RF_KILL switch is NOT set to KILL */
6002 if (iwl3945_read32(priv, CSR_GP_CNTRL) &
6003 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
6004 clear_bit(STATUS_RF_KILL_HW, &priv->status);
6005 else {
6006 set_bit(STATUS_RF_KILL_HW, &priv->status);
6007 if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
6008 IWL_WARNING("Radio disabled by HW RF Kill switch\n");
6009 return -ENODEV;
6010 }
b481de9c
ZY		 6011 }
6012
bb8c093b 6013 iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 6014
bb8c093b 6015 rc = iwl3945_hw_nic_init(priv);
b481de9c
ZY		 6016 if (rc) {
6017 IWL_ERROR("Unable to int nic\n");
6018 return rc;
6019 }
6020
6021 /* make sure rfkill handshake bits are cleared */
bb8c093b
CH		 6022 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
6023 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 6024 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
6025
6026 /* clear (again), then enable host interrupts */
bb8c093b
CH		 6027 iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
6028 iwl3945_enable_interrupts(priv);
b481de9c
ZY		 6029
6030 /* really make sure rfkill handshake bits are cleared */
bb8c093b
CH		 6031 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
6032 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 6033
6034 /* Copy original ucode data image from disk into backup cache.
6035 * This will be used to initialize the on-board processor's
6036 * data SRAM for a clean start when the runtime program first loads. */
6037 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 6038 priv->ucode_data.len);
b481de9c 6039
e655b9f0
ZY		 6040 /* We return success when we resume from suspend and rf_kill is on. */
6041 if (test_bit(STATUS_RF_KILL_HW, &priv->status))
6042 return 0;
6043
b481de9c
ZY		 6044 for (i = 0; i < MAX_HW_RESTARTS; i++) {
6045
bb8c093b 6046 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 6047
6048 /* load bootstrap state machine,
6049 * load bootstrap program into processor's memory,
6050 * prepare to load the "initialize" uCode */
bb8c093b 6051 rc = iwl3945_load_bsm(priv);
b481de9c
ZY		 6052
6053 if (rc) {
6054 IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
6055 continue;
6056 }
6057
6058 /* start card; "initialize" will load runtime ucode */
bb8c093b 6059 iwl3945_nic_start(priv);
b481de9c 6060
b481de9c
ZY		 6061 IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
6062
6063 return 0;
6064 }
6065
6066 set_bit(STATUS_EXIT_PENDING, &priv->status);
bb8c093b 6067 __iwl3945_down(priv);
b481de9c
ZY		 6068
6069 /* tried to restart and config the device for as long as our
6070 * patience could withstand */
6071 IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
6072 return -EIO;
6073}
6074
6075
6076/*****************************************************************************
6077 *
6078 * Workqueue callbacks
6079 *
6080 *****************************************************************************/
6081
bb8c093b 6082static void iwl3945_bg_init_alive_start(struct work_struct *data)
b481de9c 6083{
bb8c093b
CH		 6084 struct iwl3945_priv *priv =
6085 container_of(data, struct iwl3945_priv, init_alive_start.work);
b481de9c
ZY		 6086
6087 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6088 return;
6089
6090 mutex_lock(&priv->mutex);
bb8c093b 6091 iwl3945_init_alive_start(priv);
b481de9c
ZY		 6092 mutex_unlock(&priv->mutex);
6093}
6094
bb8c093b 6095static void iwl3945_bg_alive_start(struct work_struct *data)
b481de9c 6096{
bb8c093b
CH		 6097 struct iwl3945_priv *priv =
6098 container_of(data, struct iwl3945_priv, alive_start.work);
b481de9c
ZY		 6099
6100 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6101 return;
6102
6103 mutex_lock(&priv->mutex);
bb8c093b 6104 iwl3945_alive_start(priv);
b481de9c
ZY		 6105 mutex_unlock(&priv->mutex);
6106}
6107
bb8c093b 6108static void iwl3945_bg_rf_kill(struct work_struct *work)
b481de9c 6109{
bb8c093b 6110 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill);
b481de9c
ZY		 6111
6112 wake_up_interruptible(&priv->wait_command_queue);
6113
6114 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6115 return;
6116
6117 mutex_lock(&priv->mutex);
6118
bb8c093b 6119 if (!iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 6120 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
6121 "HW and/or SW RF Kill no longer active, restarting "
6122 "device\n");
6123 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
6124 queue_work(priv->workqueue, &priv->restart);
6125 } else {
6126
6127 if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
6128 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
6129 "disabled by SW switch\n");
6130 else
6131 IWL_WARNING("Radio Frequency Kill Switch is On:\n"
6132 "Kill switch must be turned off for "
6133 "wireless networking to work.\n");
6134 }
6135 mutex_unlock(&priv->mutex);
6136}
6137
5ec03976
AK		 6138static void iwl3945_bg_set_monitor(struct work_struct *work)
6139{
6140 struct iwl3945_priv *priv = container_of(work,
6141 struct iwl3945_priv, set_monitor);
6142
6143 IWL_DEBUG(IWL_DL_STATE, "setting monitor mode\n");
6144
6145 mutex_lock(&priv->mutex);
6146
6147 if (!iwl3945_is_ready(priv))
6148 IWL_DEBUG(IWL_DL_STATE, "leave - not ready\n");
6149 else
6150 if (iwl3945_set_mode(priv, IEEE80211_IF_TYPE_MNTR) != 0)
6151 IWL_ERROR("iwl3945_set_mode() failed\n");
6152
6153 mutex_unlock(&priv->mutex);
6154}
6155
b481de9c
ZY		 6156#define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
6157
bb8c093b 6158static void iwl3945_bg_scan_check(struct work_struct *data)
b481de9c 6159{
bb8c093b
CH		 6160 struct iwl3945_priv *priv =
6161 container_of(data, struct iwl3945_priv, scan_check.work);
b481de9c
ZY		 6162
6163 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6164 return;
6165
6166 mutex_lock(&priv->mutex);
6167 if (test_bit(STATUS_SCANNING, &priv->status) ||
6168 test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6169 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
6170 "Scan completion watchdog resetting adapter (%dms)\n",
6171 jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
15e869d8 6172
b481de9c 6173 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
bb8c093b 6174 iwl3945_send_scan_abort(priv);
b481de9c
ZY		 6175 }
6176 mutex_unlock(&priv->mutex);
6177}
6178
bb8c093b 6179static void iwl3945_bg_request_scan(struct work_struct *data)
b481de9c 6180{
bb8c093b
CH		 6181 struct iwl3945_priv *priv =
6182 container_of(data, struct iwl3945_priv, request_scan);
6183 struct iwl3945_host_cmd cmd = {
b481de9c 6184 .id = REPLY_SCAN_CMD,
bb8c093b 6185 .len = sizeof(struct iwl3945_scan_cmd),
b481de9c
ZY		 6186 .meta.flags = CMD_SIZE_HUGE,
6187 };
6188 int rc = 0;
bb8c093b 6189 struct iwl3945_scan_cmd *scan;
b481de9c
ZY		 6190 struct ieee80211_conf *conf = NULL;
6191 u8 direct_mask;
8318d78a 6192 enum ieee80211_band band;
b481de9c
ZY		 6193
6194 conf = ieee80211_get_hw_conf(priv->hw);
6195
6196 mutex_lock(&priv->mutex);
6197
bb8c093b 6198 if (!iwl3945_is_ready(priv)) {
b481de9c
ZY		 6199 IWL_WARNING("request scan called when driver not ready.\n");
6200 goto done;
6201 }
6202
6203 /* Make sure the scan wasn't cancelled before this queued work
6204 * was given the chance to run... */
6205 if (!test_bit(STATUS_SCANNING, &priv->status))
6206 goto done;
6207
6208 /* This should never be called or scheduled if there is currently
6209 * a scan active in the hardware. */
6210 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
6211 IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
6212 "Ignoring second request.\n");
6213 rc = -EIO;
6214 goto done;
6215 }
6216
6217 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
6218 IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
6219 goto done;
6220 }
6221
6222 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6223 IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
6224 goto done;
6225 }
6226
bb8c093b 6227 if (iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 6228 IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
6229 goto done;
6230 }
6231
6232 if (!test_bit(STATUS_READY, &priv->status)) {
6233 IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
6234 goto done;
6235 }
6236
6237 if (!priv->scan_bands) {
6238 IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
6239 goto done;
6240 }
6241
6242 if (!priv->scan) {
bb8c093b 6243 priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
b481de9c
ZY		 6244 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
6245 if (!priv->scan) {
6246 rc = -ENOMEM;
6247 goto done;
6248 }
6249 }
6250 scan = priv->scan;
bb8c093b 6251 memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
b481de9c
ZY		 6252
6253 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
6254 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
6255
bb8c093b 6256 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 6257 u16 interval = 0;
6258 u32 extra;
6259 u32 suspend_time = 100;
6260 u32 scan_suspend_time = 100;
6261 unsigned long flags;
6262
6263 IWL_DEBUG_INFO("Scanning while associated...\n");
6264
6265 spin_lock_irqsave(&priv->lock, flags);
6266 interval = priv->beacon_int;
6267 spin_unlock_irqrestore(&priv->lock, flags);
6268
6269 scan->suspend_time = 0;
15e869d8 6270 scan->max_out_time = cpu_to_le32(200 * 1024);
b481de9c
ZY		 6271 if (!interval)
6272 interval = suspend_time;
6273 /*
6274 * suspend time format:
6275 * 0-19: beacon interval in usec (time before exec.)
6276 * 20-23: 0
6277 * 24-31: number of beacons (suspend between channels)
6278 */
6279
6280 extra = (suspend_time / interval) << 24;
6281 scan_suspend_time = 0xFF0FFFFF &
6282 (extra | ((suspend_time % interval) * 1024));
6283
6284 scan->suspend_time = cpu_to_le32(scan_suspend_time);
6285 IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
6286 scan_suspend_time, interval);
6287 }
6288
6289 /* We should add the ability for user to lock to PASSIVE ONLY */
6290 if (priv->one_direct_scan) {
6291 IWL_DEBUG_SCAN
6292 ("Kicking off one direct scan for '%s'\n",
bb8c093b 6293 iwl3945_escape_essid(priv->direct_ssid,
b481de9c
ZY		 6294 priv->direct_ssid_len));
6295 scan->direct_scan[0].id = WLAN_EID_SSID;
6296 scan->direct_scan[0].len = priv->direct_ssid_len;
6297 memcpy(scan->direct_scan[0].ssid,
6298 priv->direct_ssid, priv->direct_ssid_len);
6299 direct_mask = 1;
bb8c093b 6300 } else if (!iwl3945_is_associated(priv) && priv->essid_len) {
786b4557
BM		 6301 IWL_DEBUG_SCAN
6302 ("Kicking off one direct scan for '%s' when not associated\n",
6303 iwl3945_escape_essid(priv->essid, priv->essid_len));
b481de9c
ZY		 6304 scan->direct_scan[0].id = WLAN_EID_SSID;
6305 scan->direct_scan[0].len = priv->essid_len;
6306 memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len);
6307 direct_mask = 1;
786b4557
BM		 6308 } else {
6309 IWL_DEBUG_SCAN("Kicking off one indirect scan.\n");
b481de9c 6310 direct_mask = 0;
786b4557 6311 }
b481de9c
ZY		 6312
6313 /* We don't build a direct scan probe request; the uCode will do
6314 * that based on the direct_mask added to each channel entry */
6315 scan->tx_cmd.len = cpu_to_le16(
bb8c093b 6316 iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
18904f58 6317 IWL_MAX_SCAN_SIZE - sizeof(*scan), 0));
b481de9c
ZY		 6318 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
6319 scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
6320 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
6321
6322 /* flags + rate selection */
6323
6324 switch (priv->scan_bands) {
6325 case 2:
6326 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
6327 scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
6328 scan->good_CRC_th = 0;
8318d78a 6329 band = IEEE80211_BAND_2GHZ;
b481de9c
ZY		 6330 break;
6331
6332 case 1:
6333 scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
6334 scan->good_CRC_th = IWL_GOOD_CRC_TH;
8318d78a 6335 band = IEEE80211_BAND_5GHZ;
b481de9c
ZY		 6336 break;
6337
6338 default:
6339 IWL_WARNING("Invalid scan band count\n");
6340 goto done;
6341 }
6342
6343 /* select Rx antennas */
6344 scan->flags |= iwl3945_get_antenna_flags(priv);
6345
6346 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR)
6347 scan->filter_flags = RXON_FILTER_PROMISC_MSK;
6348
786b4557 6349 if (direct_mask)
26c0f03f
RC		 6350 scan->channel_count =
6351 iwl3945_get_channels_for_scan(
6352 priv, band, 1, /* active */
6353 direct_mask,
6354 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
786b4557 6355 else
26c0f03f
RC		 6356 scan->channel_count =
6357 iwl3945_get_channels_for_scan(
6358 priv, band, 0, /* passive */
6359 direct_mask,
6360 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
b481de9c
ZY		 6361
6362 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
bb8c093b 6363 scan->channel_count * sizeof(struct iwl3945_scan_channel);
b481de9c
ZY		 6364 cmd.data = scan;
6365 scan->len = cpu_to_le16(cmd.len);
6366
6367 set_bit(STATUS_SCAN_HW, &priv->status);
bb8c093b 6368 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 6369 if (rc)
6370 goto done;
6371
6372 queue_delayed_work(priv->workqueue, &priv->scan_check,
6373 IWL_SCAN_CHECK_WATCHDOG);
6374
6375 mutex_unlock(&priv->mutex);
6376 return;
6377
6378 done:
01ebd063 6379 /* inform mac80211 scan aborted */
b481de9c
ZY		 6380 queue_work(priv->workqueue, &priv->scan_completed);
6381 mutex_unlock(&priv->mutex);
6382}
6383
bb8c093b 6384static void iwl3945_bg_up(struct work_struct *data)
b481de9c 6385{
bb8c093b 6386 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up);
b481de9c
ZY		 6387
6388 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6389 return;
6390
6391 mutex_lock(&priv->mutex);
bb8c093b 6392 __iwl3945_up(priv);
b481de9c
ZY		 6393 mutex_unlock(&priv->mutex);
6394}
6395
bb8c093b 6396static void iwl3945_bg_restart(struct work_struct *data)
b481de9c 6397{
bb8c093b 6398 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart);
b481de9c
ZY		 6399
6400 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6401 return;
6402
bb8c093b 6403 iwl3945_down(priv);
b481de9c
ZY		 6404 queue_work(priv->workqueue, &priv->up);
6405}
6406
bb8c093b 6407static void iwl3945_bg_rx_replenish(struct work_struct *data)
b481de9c 6408{
bb8c093b
CH		 6409 struct iwl3945_priv *priv =
6410 container_of(data, struct iwl3945_priv, rx_replenish);
b481de9c
ZY		 6411
6412 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6413 return;
6414
6415 mutex_lock(&priv->mutex);
bb8c093b 6416 iwl3945_rx_replenish(priv);
b481de9c
ZY		 6417 mutex_unlock(&priv->mutex);
6418}
6419
7878a5a4
MA		 6420#define IWL_DELAY_NEXT_SCAN (HZ*2)
6421
bb8c093b 6422static void iwl3945_bg_post_associate(struct work_struct *data)
b481de9c 6423{
bb8c093b 6424 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv,
b481de9c
ZY		 6425 post_associate.work);
6426
6427 int rc = 0;
6428 struct ieee80211_conf *conf = NULL;
0795af57 6429 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 6430
6431 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
6432 IWL_ERROR("%s Should not be called in AP mode\n", __FUNCTION__);
6433 return;
6434 }
6435
6436
0795af57
JP		 6437 IWL_DEBUG_ASSOC("Associated as %d to: %s\n",
6438 priv->assoc_id,
6439 print_mac(mac, priv->active_rxon.bssid_addr));
b481de9c
ZY		 6440
6441 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6442 return;
6443
6444 mutex_lock(&priv->mutex);
6445
32bfd35d 6446 if (!priv->vif || !priv->is_open) {
6ef89d0a
MA		 6447 mutex_unlock(&priv->mutex);
6448 return;
6449 }
bb8c093b 6450 iwl3945_scan_cancel_timeout(priv, 200);
15e869d8 6451
b481de9c
ZY		 6452 conf = ieee80211_get_hw_conf(priv->hw);
6453
6454 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6455 iwl3945_commit_rxon(priv);
b481de9c 6456
bb8c093b
CH		 6457 memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
6458 iwl3945_setup_rxon_timing(priv);
6459 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY		 6460 sizeof(priv->rxon_timing), &priv->rxon_timing);
6461 if (rc)
6462 IWL_WARNING("REPLY_RXON_TIMING failed - "
6463 "Attempting to continue.\n");
6464
6465 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
6466
6467 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
6468
6469 IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
6470 priv->assoc_id, priv->beacon_int);
6471
6472 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
6473 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
6474 else
6475 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
6476
6477 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
6478 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
6479 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
6480 else
6481 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
6482
6483 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
6484 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
6485
6486 }
6487
bb8c093b 6488 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6489
6490 switch (priv->iw_mode) {
6491 case IEEE80211_IF_TYPE_STA:
bb8c093b 6492 iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
b481de9c
ZY		 6493 break;
6494
6495 case IEEE80211_IF_TYPE_IBSS:
6496
6497 /* clear out the station table */
bb8c093b 6498 iwl3945_clear_stations_table(priv);
b481de9c 6499
bb8c093b
CH		 6500 iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
6501 iwl3945_add_station(priv, priv->bssid, 0, 0);
b481de9c 6502 iwl3945_sync_sta(priv, IWL_STA_ID,
8318d78a 6503 (priv->band == IEEE80211_BAND_5GHZ) ?
b481de9c
ZY		 6504 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
6505 CMD_ASYNC);
bb8c093b
CH		 6506 iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
6507 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 6508
6509 break;
6510
6511 default:
6512 IWL_ERROR("%s Should not be called in %d mode\n",
bc434dd2 6513 __FUNCTION__, priv->iw_mode);
b481de9c
ZY		 6514 break;
6515 }
6516
bb8c093b 6517 iwl3945_sequence_reset(priv);
b481de9c 6518
bb8c093b 6519 iwl3945_activate_qos(priv, 0);
292ae174 6520
7878a5a4
MA		 6521 /* we have just associated, don't start scan too early */
6522 priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
b481de9c
ZY		 6523 mutex_unlock(&priv->mutex);
6524}
6525
bb8c093b 6526static void iwl3945_bg_abort_scan(struct work_struct *work)
b481de9c 6527{
bb8c093b 6528 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan);
b481de9c 6529
bb8c093b 6530 if (!iwl3945_is_ready(priv))
b481de9c
ZY		 6531 return;
6532
6533 mutex_lock(&priv->mutex);
6534
6535 set_bit(STATUS_SCAN_ABORTING, &priv->status);
bb8c093b 6536 iwl3945_send_scan_abort(priv);
b481de9c
ZY		 6537
6538 mutex_unlock(&priv->mutex);
6539}
6540
76bb77e0
ZY		 6541static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf);
6542
bb8c093b 6543static void iwl3945_bg_scan_completed(struct work_struct *work)
b481de9c 6544{
bb8c093b
CH		 6545 struct iwl3945_priv *priv =
6546 container_of(work, struct iwl3945_priv, scan_completed);
b481de9c
ZY		 6547
6548 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
6549
6550 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6551 return;
6552
a0646470
ZY		 6553 if (test_bit(STATUS_CONF_PENDING, &priv->status))
6554 iwl3945_mac_config(priv->hw, ieee80211_get_hw_conf(priv->hw));
76bb77e0 6555
b481de9c
ZY		 6556 ieee80211_scan_completed(priv->hw);
6557
6558 /* Since setting the TXPOWER may have been deferred while
6559 * performing the scan, fire one off */
6560 mutex_lock(&priv->mutex);
bb8c093b 6561 iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 6562 mutex_unlock(&priv->mutex);
6563}
6564
6565/*****************************************************************************
6566 *
6567 * mac80211 entry point functions
6568 *
6569 *****************************************************************************/
6570
5a66926a
ZY		 6571#define UCODE_READY_TIMEOUT (2 * HZ)
6572
bb8c093b 6573static int iwl3945_mac_start(struct ieee80211_hw *hw)
b481de9c 6574{
bb8c093b 6575 struct iwl3945_priv *priv = hw->priv;
5a66926a 6576 int ret;
b481de9c
ZY		 6577
6578 IWL_DEBUG_MAC80211("enter\n");
6579
5a66926a
ZY		 6580 if (pci_enable_device(priv->pci_dev)) {
6581 IWL_ERROR("Fail to pci_enable_device\n");
6582 return -ENODEV;
6583 }
6584 pci_restore_state(priv->pci_dev);
6585 pci_enable_msi(priv->pci_dev);
6586
6587 ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
6588 DRV_NAME, priv);
6589 if (ret) {
6590 IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq);
6591 goto out_disable_msi;
6592 }
6593
b481de9c
ZY		 6594 /* we should be verifying the device is ready to be opened */
6595 mutex_lock(&priv->mutex);
6596
5a66926a
ZY		 6597 memset(&priv->staging_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
6598 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
6599 * ucode filename and max sizes are card-specific. */
6600
6601 if (!priv->ucode_code.len) {
6602 ret = iwl3945_read_ucode(priv);
6603 if (ret) {
6604 IWL_ERROR("Could not read microcode: %d\n", ret);
6605 mutex_unlock(&priv->mutex);
6606 goto out_release_irq;
6607 }
6608 }
b481de9c 6609
e655b9f0 6610 ret = __iwl3945_up(priv);
b481de9c
ZY		 6611
6612 mutex_unlock(&priv->mutex);
5a66926a 6613
e655b9f0
ZY		 6614 if (ret)
6615 goto out_release_irq;
6616
6617 IWL_DEBUG_INFO("Start UP work.\n");
6618
6619 if (test_bit(STATUS_IN_SUSPEND, &priv->status))
6620 return 0;
6621
5a66926a
ZY		 6622 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
6623 * mac80211 will not be run successfully. */
6624 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
6625 test_bit(STATUS_READY, &priv->status),
6626 UCODE_READY_TIMEOUT);
6627 if (!ret) {
6628 if (!test_bit(STATUS_READY, &priv->status)) {
6629 IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n",
6630 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6631 ret = -ETIMEDOUT;
6632 goto out_release_irq;
6633 }
6634 }
6635
e655b9f0 6636 priv->is_open = 1;
b481de9c
ZY		 6637 IWL_DEBUG_MAC80211("leave\n");
6638 return 0;
5a66926a
ZY		 6639
6640out_release_irq:
6641 free_irq(priv->pci_dev->irq, priv);
6642out_disable_msi:
6643 pci_disable_msi(priv->pci_dev);
e655b9f0
ZY		 6644 pci_disable_device(priv->pci_dev);
6645 priv->is_open = 0;
6646 IWL_DEBUG_MAC80211("leave - failed\n");
5a66926a 6647 return ret;
b481de9c
ZY		 6648}
6649
bb8c093b 6650static void iwl3945_mac_stop(struct ieee80211_hw *hw)
b481de9c 6651{
bb8c093b 6652 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6653
6654 IWL_DEBUG_MAC80211("enter\n");
6ef89d0a 6655
e655b9f0
ZY		 6656 if (!priv->is_open) {
6657 IWL_DEBUG_MAC80211("leave - skip\n");
6658 return;
6659 }
6660
b481de9c 6661 priv->is_open = 0;
5a66926a
ZY		 6662
6663 if (iwl3945_is_ready_rf(priv)) {
e655b9f0
ZY		 6664 /* stop mac, cancel any scan request and clear
6665 * RXON_FILTER_ASSOC_MSK BIT
6666 */
5a66926a
ZY		 6667 mutex_lock(&priv->mutex);
6668 iwl3945_scan_cancel_timeout(priv, 100);
6669 cancel_delayed_work(&priv->post_associate);
fde3571f 6670 mutex_unlock(&priv->mutex);
fde3571f
MA		 6671 }
6672
5a66926a
ZY		 6673 iwl3945_down(priv);
6674
6675 flush_workqueue(priv->workqueue);
6676 free_irq(priv->pci_dev->irq, priv);
6677 pci_disable_msi(priv->pci_dev);
6678 pci_save_state(priv->pci_dev);
6679 pci_disable_device(priv->pci_dev);
6ef89d0a 6680
b481de9c 6681 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 6682}
6683
bb8c093b 6684static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
b481de9c
ZY		 6685 struct ieee80211_tx_control *ctl)
6686{
bb8c093b 6687 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6688
6689 IWL_DEBUG_MAC80211("enter\n");
6690
6691 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
6692 IWL_DEBUG_MAC80211("leave - monitor\n");
6693 return -1;
6694 }
6695
6696 IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
2e92e6f2 6697 ieee80211_get_tx_rate(hw, ctl)->bitrate);
b481de9c 6698
bb8c093b 6699 if (iwl3945_tx_skb(priv, skb, ctl))
b481de9c
ZY		 6700 dev_kfree_skb_any(skb);
6701
6702 IWL_DEBUG_MAC80211("leave\n");
6703 return 0;
6704}
6705
bb8c093b 6706static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
b481de9c
ZY		 6707 struct ieee80211_if_init_conf *conf)
6708{
bb8c093b 6709 struct iwl3945_priv *priv = hw->priv;
b481de9c 6710 unsigned long flags;
0795af57 6711 DECLARE_MAC_BUF(mac);
b481de9c 6712
32bfd35d 6713 IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
b481de9c 6714
32bfd35d
JB		 6715 if (priv->vif) {
6716 IWL_DEBUG_MAC80211("leave - vif != NULL\n");
864792e3 6717 return -EOPNOTSUPP;
b481de9c
ZY		 6718 }
6719
6720 spin_lock_irqsave(&priv->lock, flags);
32bfd35d 6721 priv->vif = conf->vif;
b481de9c
ZY		 6722
6723 spin_unlock_irqrestore(&priv->lock, flags);
6724
6725 mutex_lock(&priv->mutex);
864792e3
TW		 6726
6727 if (conf->mac_addr) {
6728 IWL_DEBUG_MAC80211("Set: %s\n", print_mac(mac, conf->mac_addr));
6729 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
6730 }
6731
5a66926a
ZY		 6732 if (iwl3945_is_ready(priv))
6733 iwl3945_set_mode(priv, conf->type);
b481de9c 6734
b481de9c
ZY		 6735 mutex_unlock(&priv->mutex);
6736
5a66926a 6737 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 6738 return 0;
6739}
6740
6741/**
bb8c093b 6742 * iwl3945_mac_config - mac80211 config callback
b481de9c
ZY		 6743 *
6744 * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
6745 * be set inappropriately and the driver currently sets the hardware up to
6746 * use it whenever needed.
6747 */
bb8c093b 6748static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
b481de9c 6749{
bb8c093b
CH		 6750 struct iwl3945_priv *priv = hw->priv;
6751 const struct iwl3945_channel_info *ch_info;
b481de9c 6752 unsigned long flags;
76bb77e0 6753 int ret = 0;
b481de9c
ZY		 6754
6755 mutex_lock(&priv->mutex);
8318d78a 6756 IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
b481de9c 6757
12342c47
ZY		 6758 priv->add_radiotap = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
6759
bb8c093b 6760 if (!iwl3945_is_ready(priv)) {
b481de9c 6761 IWL_DEBUG_MAC80211("leave - not ready\n");
76bb77e0
ZY		 6762 ret = -EIO;
6763 goto out;
b481de9c
ZY		 6764 }
6765
bb8c093b 6766 if (unlikely(!iwl3945_param_disable_hw_scan &&
b481de9c 6767 test_bit(STATUS_SCANNING, &priv->status))) {
a0646470
ZY		 6768 IWL_DEBUG_MAC80211("leave - scanning\n");
6769 set_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 6770 mutex_unlock(&priv->mutex);
a0646470 6771 return 0;
b481de9c
ZY		 6772 }
6773
6774 spin_lock_irqsave(&priv->lock, flags);
6775
8318d78a
JB		 6776 ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
6777 conf->channel->hw_value);
b481de9c
ZY		 6778 if (!is_channel_valid(ch_info)) {
6779 IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this SKU.\n",
8318d78a 6780 conf->channel->hw_value, conf->channel->band);
b481de9c
ZY		 6781 IWL_DEBUG_MAC80211("leave - invalid channel\n");
6782 spin_unlock_irqrestore(&priv->lock, flags);
76bb77e0
ZY		 6783 ret = -EINVAL;
6784 goto out;
b481de9c
ZY		 6785 }
6786
8318d78a 6787 iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
b481de9c 6788
8318d78a 6789 iwl3945_set_flags_for_phymode(priv, conf->channel->band);
b481de9c
ZY		 6790
6791 /* The list of supported rates and rate mask can be different
6792 * for each phymode; since the phymode may have changed, reset
6793 * the rate mask to what mac80211 lists */
bb8c093b 6794 iwl3945_set_rate(priv);
b481de9c
ZY		 6795
6796 spin_unlock_irqrestore(&priv->lock, flags);
6797
6798#ifdef IEEE80211_CONF_CHANNEL_SWITCH
6799 if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
bb8c093b 6800 iwl3945_hw_channel_switch(priv, conf->channel);
76bb77e0 6801 goto out;
b481de9c
ZY		 6802 }
6803#endif
6804
bb8c093b 6805 iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
b481de9c
ZY		 6806
6807 if (!conf->radio_enabled) {
6808 IWL_DEBUG_MAC80211("leave - radio disabled\n");
76bb77e0 6809 goto out;
b481de9c
ZY		 6810 }
6811
bb8c093b 6812 if (iwl3945_is_rfkill(priv)) {
b481de9c 6813 IWL_DEBUG_MAC80211("leave - RF kill\n");
76bb77e0
ZY		 6814 ret = -EIO;
6815 goto out;
b481de9c
ZY		 6816 }
6817
bb8c093b 6818 iwl3945_set_rate(priv);
b481de9c
ZY		 6819
6820 if (memcmp(&priv->active_rxon,
6821 &priv->staging_rxon, sizeof(priv->staging_rxon)))
bb8c093b 6822 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6823 else
6824 IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
6825
6826 IWL_DEBUG_MAC80211("leave\n");
6827
76bb77e0 6828out:
a0646470 6829 clear_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 6830 mutex_unlock(&priv->mutex);
76bb77e0 6831 return ret;
b481de9c
ZY		 6832}
6833
bb8c093b 6834static void iwl3945_config_ap(struct iwl3945_priv *priv)
b481de9c
ZY		 6835{
6836 int rc = 0;
6837
d986bcd1 6838 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY		 6839 return;
6840
6841 /* The following should be done only at AP bring up */
6842 if ((priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) == 0) {
6843
6844 /* RXON - unassoc (to set timing command) */
6845 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6846 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6847
6848 /* RXON Timing */
bb8c093b
CH		 6849 memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
6850 iwl3945_setup_rxon_timing(priv);
6851 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY		 6852 sizeof(priv->rxon_timing), &priv->rxon_timing);
6853 if (rc)
6854 IWL_WARNING("REPLY_RXON_TIMING failed - "
6855 "Attempting to continue.\n");
6856
6857 /* FIXME: what should be the assoc_id for AP? */
6858 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
6859 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
6860 priv->staging_rxon.flags |=
6861 RXON_FLG_SHORT_PREAMBLE_MSK;
6862 else
6863 priv->staging_rxon.flags &=
6864 ~RXON_FLG_SHORT_PREAMBLE_MSK;
6865
6866 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
6867 if (priv->assoc_capability &
6868 WLAN_CAPABILITY_SHORT_SLOT_TIME)
6869 priv->staging_rxon.flags |=
6870 RXON_FLG_SHORT_SLOT_MSK;
6871 else
6872 priv->staging_rxon.flags &=
6873 ~RXON_FLG_SHORT_SLOT_MSK;
6874
6875 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
6876 priv->staging_rxon.flags &=
6877 ~RXON_FLG_SHORT_SLOT_MSK;
6878 }
6879 /* restore RXON assoc */
6880 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
bb8c093b
CH		 6881 iwl3945_commit_rxon(priv);
6882 iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
556f8db7 6883 }
bb8c093b 6884 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 6885
6886 /* FIXME - we need to add code here to detect a totally new
6887 * configuration, reset the AP, unassoc, rxon timing, assoc,
6888 * clear sta table, add BCAST sta... */
6889}
6890
32bfd35d
JB		 6891static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
6892 struct ieee80211_vif *vif,
b481de9c
ZY		 6893 struct ieee80211_if_conf *conf)
6894{
bb8c093b 6895 struct iwl3945_priv *priv = hw->priv;
0795af57 6896 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 6897 unsigned long flags;
6898 int rc;
6899
6900 if (conf == NULL)
6901 return -EIO;
6902
b716bb91
EG		 6903 if (priv->vif != vif) {
6904 IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
b716bb91
EG		 6905 return 0;
6906 }
6907
4150c572
JB		 6908 /* XXX: this MUST use conf->mac_addr */
6909
b481de9c
ZY		 6910 if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
6911 (!conf->beacon || !conf->ssid_len)) {
6912 IWL_DEBUG_MAC80211
6913 ("Leaving in AP mode because HostAPD is not ready.\n");
6914 return 0;
6915 }
6916
5a66926a
ZY		 6917 if (!iwl3945_is_alive(priv))
6918 return -EAGAIN;
6919
b481de9c
ZY		 6920 mutex_lock(&priv->mutex);
6921
b481de9c 6922 if (conf->bssid)
0795af57
JP		 6923 IWL_DEBUG_MAC80211("bssid: %s\n",
6924 print_mac(mac, conf->bssid));
b481de9c 6925
4150c572
JB		 6926/*
6927 * very dubious code was here; the probe filtering flag is never set:
6928 *
b481de9c
ZY		 6929 if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
6930 !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
4150c572 6931 */
b481de9c
ZY		 6932
6933 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
6934 if (!conf->bssid) {
6935 conf->bssid = priv->mac_addr;
6936 memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
0795af57
JP		 6937 IWL_DEBUG_MAC80211("bssid was set to: %s\n",
6938 print_mac(mac, conf->bssid));
b481de9c
ZY		 6939 }
6940 if (priv->ibss_beacon)
6941 dev_kfree_skb(priv->ibss_beacon);
6942
6943 priv->ibss_beacon = conf->beacon;
6944 }
6945
fde3571f
MA		 6946 if (iwl3945_is_rfkill(priv))
6947 goto done;
6948
b481de9c
ZY		 6949 if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
6950 !is_multicast_ether_addr(conf->bssid)) {
6951 /* If there is currently a HW scan going on in the background
6952 * then we need to cancel it else the RXON below will fail. */
bb8c093b 6953 if (iwl3945_scan_cancel_timeout(priv, 100)) {
b481de9c
ZY		 6954 IWL_WARNING("Aborted scan still in progress "
6955 "after 100ms\n");
6956 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
6957 mutex_unlock(&priv->mutex);
6958 return -EAGAIN;
6959 }
6960 memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
6961
6962 /* TODO: Audit driver for usage of these members and see
6963 * if mac80211 deprecates them (priv->bssid looks like it
6964 * shouldn't be there, but I haven't scanned the IBSS code
6965 * to verify) - jpk */
6966 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
6967
6968 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
bb8c093b 6969 iwl3945_config_ap(priv);
b481de9c 6970 else {
bb8c093b 6971 rc = iwl3945_commit_rxon(priv);
b481de9c 6972 if ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && rc)
bb8c093b 6973 iwl3945_add_station(priv,
556f8db7 6974 priv->active_rxon.bssid_addr, 1, 0);
b481de9c
ZY		 6975 }
6976
6977 } else {
bb8c093b 6978 iwl3945_scan_cancel_timeout(priv, 100);
b481de9c 6979 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6980 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6981 }
6982
fde3571f 6983 done:
b481de9c
ZY		 6984 spin_lock_irqsave(&priv->lock, flags);
6985 if (!conf->ssid_len)
6986 memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
6987 else
6988 memcpy(priv->essid, conf->ssid, conf->ssid_len);
6989
6990 priv->essid_len = conf->ssid_len;
6991 spin_unlock_irqrestore(&priv->lock, flags);
6992
6993 IWL_DEBUG_MAC80211("leave\n");
6994 mutex_unlock(&priv->mutex);
6995
6996 return 0;
6997}
6998
bb8c093b 6999static void iwl3945_configure_filter(struct ieee80211_hw *hw,
4150c572
JB		 7000 unsigned int changed_flags,
7001 unsigned int *total_flags,
7002 int mc_count, struct dev_addr_list *mc_list)
7003{
7004 /*
7005 * XXX: dummy
bb8c093b 7006 * see also iwl3945_connection_init_rx_config
4150c572 7007 */
5ec03976
AK		 7008 struct iwl3945_priv *priv = hw->priv;
7009 int new_flags = 0;
7010 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
7011 if (*total_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
7012 IWL_DEBUG_MAC80211("Enter: type %d (0x%x, 0x%x)\n",
7013 IEEE80211_IF_TYPE_MNTR,
7014 changed_flags, *total_flags);
7015 /* queue work 'cuz mac80211 is holding a lock which
7016 * prevents us from issuing (synchronous) f/w cmds */
7017 queue_work(priv->workqueue, &priv->set_monitor);
7018 new_flags &= FIF_PROMISC_IN_BSS |
7019 FIF_OTHER_BSS |
7020 FIF_ALLMULTI;
7021 }
7022 }
7023 *total_flags = new_flags;
4150c572
JB		 7024}
7025
bb8c093b 7026static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
b481de9c
ZY		 7027 struct ieee80211_if_init_conf *conf)
7028{
bb8c093b 7029 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7030
7031 IWL_DEBUG_MAC80211("enter\n");
7032
7033 mutex_lock(&priv->mutex);
6ef89d0a 7034
fde3571f
MA		 7035 if (iwl3945_is_ready_rf(priv)) {
7036 iwl3945_scan_cancel_timeout(priv, 100);
7037 cancel_delayed_work(&priv->post_associate);
7038 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
7039 iwl3945_commit_rxon(priv);
7040 }
32bfd35d
JB		 7041 if (priv->vif == conf->vif) {
7042 priv->vif = NULL;
b481de9c
ZY		 7043 memset(priv->bssid, 0, ETH_ALEN);
7044 memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
7045 priv->essid_len = 0;
7046 }
7047 mutex_unlock(&priv->mutex);
7048
7049 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 7050}
7051
bb8c093b 7052static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
b481de9c
ZY		 7053{
7054 int rc = 0;
7055 unsigned long flags;
bb8c093b 7056 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7057
7058 IWL_DEBUG_MAC80211("enter\n");
7059
15e869d8 7060 mutex_lock(&priv->mutex);
b481de9c
ZY		 7061 spin_lock_irqsave(&priv->lock, flags);
7062
bb8c093b 7063 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7064 rc = -EIO;
7065 IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
7066 goto out_unlock;
7067 }
7068
7069 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { /* APs don't scan */
7070 rc = -EIO;
7071 IWL_ERROR("ERROR: APs don't scan\n");
7072 goto out_unlock;
7073 }
7074
7878a5a4
MA		 7075 /* we don't schedule scan within next_scan_jiffies period */
7076 if (priv->next_scan_jiffies &&
7077 time_after(priv->next_scan_jiffies, jiffies)) {
7078 rc = -EAGAIN;
7079 goto out_unlock;
7080 }
15dbf1b7
BM		 7081 /* if we just finished scan ask for delay for a broadcast scan */
7082 if ((len == 0) && priv->last_scan_jiffies &&
7083 time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN,
7084 jiffies)) {
b481de9c
ZY		 7085 rc = -EAGAIN;
7086 goto out_unlock;
7087 }
7088 if (len) {
7878a5a4 7089 IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
bb8c093b 7090 iwl3945_escape_essid(ssid, len), (int)len);
b481de9c
ZY		 7091
7092 priv->one_direct_scan = 1;
7093 priv->direct_ssid_len = (u8)
7094 min((u8) len, (u8) IW_ESSID_MAX_SIZE);
7095 memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
6ef89d0a
MA		 7096 } else
7097 priv->one_direct_scan = 0;
b481de9c 7098
bb8c093b 7099 rc = iwl3945_scan_initiate(priv);
b481de9c
ZY		 7100
7101 IWL_DEBUG_MAC80211("leave\n");
7102
7103out_unlock:
7104 spin_unlock_irqrestore(&priv->lock, flags);
15e869d8 7105 mutex_unlock(&priv->mutex);
b481de9c
ZY		 7106
7107 return rc;
7108}
7109
bb8c093b 7110static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
b481de9c
ZY		 7111 const u8 *local_addr, const u8 *addr,
7112 struct ieee80211_key_conf *key)
7113{
bb8c093b 7114 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7115 int rc = 0;
7116 u8 sta_id;
7117
7118 IWL_DEBUG_MAC80211("enter\n");
7119
bb8c093b 7120 if (!iwl3945_param_hwcrypto) {
b481de9c
ZY		 7121 IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
7122 return -EOPNOTSUPP;
7123 }
7124
7125 if (is_zero_ether_addr(addr))
7126 /* only support pairwise keys */
7127 return -EOPNOTSUPP;
7128
bb8c093b 7129 sta_id = iwl3945_hw_find_station(priv, addr);
b481de9c 7130 if (sta_id == IWL_INVALID_STATION) {
0795af57
JP		 7131 DECLARE_MAC_BUF(mac);
7132
7133 IWL_DEBUG_MAC80211("leave - %s not in station map.\n",
7134 print_mac(mac, addr));
b481de9c
ZY		 7135 return -EINVAL;
7136 }
7137
7138 mutex_lock(&priv->mutex);
7139
bb8c093b 7140 iwl3945_scan_cancel_timeout(priv, 100);
15e869d8 7141
b481de9c
ZY		 7142 switch (cmd) {
7143 case SET_KEY:
bb8c093b 7144 rc = iwl3945_update_sta_key_info(priv, key, sta_id);
b481de9c 7145 if (!rc) {
bb8c093b
CH		 7146 iwl3945_set_rxon_hwcrypto(priv, 1);
7147 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7148 key->hw_key_idx = sta_id;
7149 IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
7150 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
7151 }
7152 break;
7153 case DISABLE_KEY:
bb8c093b 7154 rc = iwl3945_clear_sta_key_info(priv, sta_id);
b481de9c 7155 if (!rc) {
bb8c093b
CH		 7156 iwl3945_set_rxon_hwcrypto(priv, 0);
7157 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7158 IWL_DEBUG_MAC80211("disable hwcrypto key\n");
7159 }
7160 break;
7161 default:
7162 rc = -EINVAL;
7163 }
7164
7165 IWL_DEBUG_MAC80211("leave\n");
7166 mutex_unlock(&priv->mutex);
7167
7168 return rc;
7169}
7170
e100bb64 7171static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
b481de9c
ZY		 7172 const struct ieee80211_tx_queue_params *params)
7173{
bb8c093b 7174 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7175 unsigned long flags;
7176 int q;
b481de9c
ZY		 7177
7178 IWL_DEBUG_MAC80211("enter\n");
7179
bb8c093b 7180 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7181 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7182 return -EIO;
7183 }
7184
7185 if (queue >= AC_NUM) {
7186 IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
7187 return 0;
7188 }
7189
b481de9c
ZY		 7190 if (!priv->qos_data.qos_enable) {
7191 priv->qos_data.qos_active = 0;
7192 IWL_DEBUG_MAC80211("leave - qos not enabled\n");
7193 return 0;
7194 }
7195 q = AC_NUM - 1 - queue;
7196
7197 spin_lock_irqsave(&priv->lock, flags);
7198
7199 priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
7200 priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
7201 priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
7202 priv->qos_data.def_qos_parm.ac[q].edca_txop =
3330d7be 7203 cpu_to_le16((params->txop * 32));
b481de9c
ZY		 7204
7205 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
7206 priv->qos_data.qos_active = 1;
7207
7208 spin_unlock_irqrestore(&priv->lock, flags);
7209
7210 mutex_lock(&priv->mutex);
7211 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
bb8c093b
CH		 7212 iwl3945_activate_qos(priv, 1);
7213 else if (priv->assoc_id && iwl3945_is_associated(priv))
7214 iwl3945_activate_qos(priv, 0);
b481de9c
ZY		 7215
7216 mutex_unlock(&priv->mutex);
7217
b481de9c
ZY		 7218 IWL_DEBUG_MAC80211("leave\n");
7219 return 0;
7220}
7221
bb8c093b 7222static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
b481de9c
ZY		 7223 struct ieee80211_tx_queue_stats *stats)
7224{
bb8c093b 7225 struct iwl3945_priv *priv = hw->priv;
b481de9c 7226 int i, avail;
bb8c093b
CH		 7227 struct iwl3945_tx_queue *txq;
7228 struct iwl3945_queue *q;
b481de9c
ZY		 7229 unsigned long flags;
7230
7231 IWL_DEBUG_MAC80211("enter\n");
7232
bb8c093b 7233 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7234 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7235 return -EIO;
7236 }
7237
7238 spin_lock_irqsave(&priv->lock, flags);
7239
7240 for (i = 0; i < AC_NUM; i++) {
7241 txq = &priv->txq[i];
7242 q = &txq->q;
bb8c093b 7243 avail = iwl3945_queue_space(q);
b481de9c 7244
57ffc589
JB		 7245 stats[i].len = q->n_window - avail;
7246 stats[i].limit = q->n_window - q->high_mark;
7247 stats[i].count = q->n_window;
b481de9c
ZY		 7248
7249 }
7250 spin_unlock_irqrestore(&priv->lock, flags);
7251
7252 IWL_DEBUG_MAC80211("leave\n");
7253
7254 return 0;
7255}
7256
bb8c093b 7257static int iwl3945_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY		 7258 struct ieee80211_low_level_stats *stats)
7259{
7260 IWL_DEBUG_MAC80211("enter\n");
7261 IWL_DEBUG_MAC80211("leave\n");
7262
7263 return 0;
7264}
7265
bb8c093b 7266static u64 iwl3945_mac_get_tsf(struct ieee80211_hw *hw)
b481de9c
ZY		 7267{
7268 IWL_DEBUG_MAC80211("enter\n");
7269 IWL_DEBUG_MAC80211("leave\n");
7270
7271 return 0;
7272}
7273
bb8c093b 7274static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
b481de9c 7275{
bb8c093b 7276 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7277 unsigned long flags;
7278
7279 mutex_lock(&priv->mutex);
7280 IWL_DEBUG_MAC80211("enter\n");
7281
bb8c093b 7282 iwl3945_reset_qos(priv);
292ae174 7283
b481de9c
ZY		 7284 cancel_delayed_work(&priv->post_associate);
7285
7286 spin_lock_irqsave(&priv->lock, flags);
7287 priv->assoc_id = 0;
7288 priv->assoc_capability = 0;
7289 priv->call_post_assoc_from_beacon = 0;
7290
7291 /* new association get rid of ibss beacon skb */
7292 if (priv->ibss_beacon)
7293 dev_kfree_skb(priv->ibss_beacon);
7294
7295 priv->ibss_beacon = NULL;
7296
7297 priv->beacon_int = priv->hw->conf.beacon_int;
7298 priv->timestamp1 = 0;
7299 priv->timestamp0 = 0;
7300 if ((priv->iw_mode == IEEE80211_IF_TYPE_STA))
7301 priv->beacon_int = 0;
7302
7303 spin_unlock_irqrestore(&priv->lock, flags);
7304
fde3571f
MA		 7305 if (!iwl3945_is_ready_rf(priv)) {
7306 IWL_DEBUG_MAC80211("leave - not ready\n");
7307 mutex_unlock(&priv->mutex);
7308 return;
7309 }
7310
15e869d8
MA		 7311 /* we are restarting association process
7312 * clear RXON_FILTER_ASSOC_MSK bit
7313 */
7314 if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
bb8c093b 7315 iwl3945_scan_cancel_timeout(priv, 100);
15e869d8 7316 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 7317 iwl3945_commit_rxon(priv);
15e869d8
MA		 7318 }
7319
b481de9c
ZY		 7320 /* Per mac80211.h: This is only used in IBSS mode... */
7321 if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
15e869d8 7322
b481de9c
ZY		 7323 IWL_DEBUG_MAC80211("leave - not in IBSS\n");
7324 mutex_unlock(&priv->mutex);
7325 return;
b481de9c
ZY		 7326 }
7327
bb8c093b 7328 iwl3945_set_rate(priv);
b481de9c
ZY		 7329
7330 mutex_unlock(&priv->mutex);
7331
7332 IWL_DEBUG_MAC80211("leave\n");
7333
7334}
7335
bb8c093b 7336static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
b481de9c
ZY		 7337 struct ieee80211_tx_control *control)
7338{
bb8c093b 7339 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7340 unsigned long flags;
7341
7342 mutex_lock(&priv->mutex);
7343 IWL_DEBUG_MAC80211("enter\n");
7344
bb8c093b 7345 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7346 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7347 mutex_unlock(&priv->mutex);
7348 return -EIO;
7349 }
7350
7351 if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
7352 IWL_DEBUG_MAC80211("leave - not IBSS\n");
7353 mutex_unlock(&priv->mutex);
7354 return -EIO;
7355 }
7356
7357 spin_lock_irqsave(&priv->lock, flags);
7358
7359 if (priv->ibss_beacon)
7360 dev_kfree_skb(priv->ibss_beacon);
7361
7362 priv->ibss_beacon = skb;
7363
7364 priv->assoc_id = 0;
7365
7366 IWL_DEBUG_MAC80211("leave\n");
7367 spin_unlock_irqrestore(&priv->lock, flags);
7368
bb8c093b 7369 iwl3945_reset_qos(priv);
b481de9c
ZY		 7370
7371 queue_work(priv->workqueue, &priv->post_associate.work);
7372
7373 mutex_unlock(&priv->mutex);
7374
7375 return 0;
7376}
7377
7378/*****************************************************************************
7379 *
7380 * sysfs attributes
7381 *
7382 *****************************************************************************/
7383
c8b0e6e1 7384#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 7385
7386/*
7387 * The following adds a new attribute to the sysfs representation
7388 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
7389 * used for controlling the debug level.
7390 *
7391 * See the level definitions in iwl for details.
7392 */
7393
7394static ssize_t show_debug_level(struct device_driver *d, char *buf)
7395{
bb8c093b 7396 return sprintf(buf, "0x%08X\n", iwl3945_debug_level);
b481de9c
ZY		 7397}
7398static ssize_t store_debug_level(struct device_driver *d,
7399 const char *buf, size_t count)
7400{
7401 char *p = (char *)buf;
7402 u32 val;
7403
7404 val = simple_strtoul(p, &p, 0);
7405 if (p == buf)
7406 printk(KERN_INFO DRV_NAME
7407 ": %s is not in hex or decimal form.\n", buf);
7408 else
bb8c093b 7409 iwl3945_debug_level = val;
b481de9c
ZY		 7410
7411 return strnlen(buf, count);
7412}
7413
7414static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
7415 show_debug_level, store_debug_level);
7416
c8b0e6e1 7417#endif /* CONFIG_IWL3945_DEBUG */
b481de9c
ZY		 7418
7419static ssize_t show_rf_kill(struct device *d,
7420 struct device_attribute *attr, char *buf)
7421{
7422 /*
7423 * 0 - RF kill not enabled
7424 * 1 - SW based RF kill active (sysfs)
7425 * 2 - HW based RF kill active
7426 * 3 - Both HW and SW based RF kill active
7427 */
bb8c093b 7428 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7429 int val = (test_bit(STATUS_RF_KILL_SW, &priv->status) ? 0x1 : 0x0) |
7430 (test_bit(STATUS_RF_KILL_HW, &priv->status) ? 0x2 : 0x0);
7431
7432 return sprintf(buf, "%i\n", val);
7433}
7434
7435static ssize_t store_rf_kill(struct device *d,
7436 struct device_attribute *attr,
7437 const char *buf, size_t count)
7438{
bb8c093b 7439 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7440
7441 mutex_lock(&priv->mutex);
bb8c093b 7442 iwl3945_radio_kill_sw(priv, buf[0] == '1');
b481de9c
ZY		 7443 mutex_unlock(&priv->mutex);
7444
7445 return count;
7446}
7447
7448static DEVICE_ATTR(rf_kill, S_IWUSR | S_IRUGO, show_rf_kill, store_rf_kill);
7449
7450static ssize_t show_temperature(struct device *d,
7451 struct device_attribute *attr, char *buf)
7452{
bb8c093b 7453 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c 7454
bb8c093b 7455 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7456 return -EAGAIN;
7457
bb8c093b 7458 return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
b481de9c
ZY		 7459}
7460
7461static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
7462
7463static ssize_t show_rs_window(struct device *d,
7464 struct device_attribute *attr,
7465 char *buf)
7466{
bb8c093b
CH		 7467 struct iwl3945_priv *priv = d->driver_data;
7468 return iwl3945_fill_rs_info(priv->hw, buf, IWL_AP_ID);
b481de9c
ZY		 7469}
7470static DEVICE_ATTR(rs_window, S_IRUGO, show_rs_window, NULL);
7471
7472static ssize_t show_tx_power(struct device *d,
7473 struct device_attribute *attr, char *buf)
7474{
bb8c093b 7475 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7476 return sprintf(buf, "%d\n", priv->user_txpower_limit);
7477}
7478
7479static ssize_t store_tx_power(struct device *d,
7480 struct device_attribute *attr,
7481 const char *buf, size_t count)
7482{
bb8c093b 7483 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7484 char *p = (char *)buf;
7485 u32 val;
7486
7487 val = simple_strtoul(p, &p, 10);
7488 if (p == buf)
7489 printk(KERN_INFO DRV_NAME
7490 ": %s is not in decimal form.\n", buf);
7491 else
bb8c093b 7492 iwl3945_hw_reg_set_txpower(priv, val);
b481de9c
ZY		 7493
7494 return count;
7495}
7496
7497static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
7498
7499static ssize_t show_flags(struct device *d,
7500 struct device_attribute *attr, char *buf)
7501{
bb8c093b 7502 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7503
7504 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
7505}
7506
7507static ssize_t store_flags(struct device *d,
7508 struct device_attribute *attr,
7509 const char *buf, size_t count)
7510{
bb8c093b 7511 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7512 u32 flags = simple_strtoul(buf, NULL, 0);
7513
7514 mutex_lock(&priv->mutex);
7515 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
7516 /* Cancel any currently running scans... */
bb8c093b 7517 if (iwl3945_scan_cancel_timeout(priv, 100))
b481de9c
ZY		 7518 IWL_WARNING("Could not cancel scan.\n");
7519 else {
7520 IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
7521 flags);
7522 priv->staging_rxon.flags = cpu_to_le32(flags);
bb8c093b 7523 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7524 }
7525 }
7526 mutex_unlock(&priv->mutex);
7527
7528 return count;
7529}
7530
7531static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
7532
7533static ssize_t show_filter_flags(struct device *d,
7534 struct device_attribute *attr, char *buf)
7535{
bb8c093b 7536 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7537
7538 return sprintf(buf, "0x%04X\n",
7539 le32_to_cpu(priv->active_rxon.filter_flags));
7540}
7541
7542static ssize_t store_filter_flags(struct device *d,
7543 struct device_attribute *attr,
7544 const char *buf, size_t count)
7545{
bb8c093b 7546 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7547 u32 filter_flags = simple_strtoul(buf, NULL, 0);
7548
7549 mutex_lock(&priv->mutex);
7550 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
7551 /* Cancel any currently running scans... */
bb8c093b 7552 if (iwl3945_scan_cancel_timeout(priv, 100))
b481de9c
ZY		 7553 IWL_WARNING("Could not cancel scan.\n");
7554 else {
7555 IWL_DEBUG_INFO("Committing rxon.filter_flags = "
7556 "0x%04X\n", filter_flags);
7557 priv->staging_rxon.filter_flags =
7558 cpu_to_le32(filter_flags);
bb8c093b 7559 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7560 }
7561 }
7562 mutex_unlock(&priv->mutex);
7563
7564 return count;
7565}
7566
7567static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
7568 store_filter_flags);
7569
c8b0e6e1 7570#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 7571
7572static ssize_t show_measurement(struct device *d,
7573 struct device_attribute *attr, char *buf)
7574{
bb8c093b
CH		 7575 struct iwl3945_priv *priv = dev_get_drvdata(d);
7576 struct iwl3945_spectrum_notification measure_report;
b481de9c
ZY		 7577 u32 size = sizeof(measure_report), len = 0, ofs = 0;
7578 u8 *data = (u8 *) & measure_report;
7579 unsigned long flags;
7580
7581 spin_lock_irqsave(&priv->lock, flags);
7582 if (!(priv->measurement_status & MEASUREMENT_READY)) {
7583 spin_unlock_irqrestore(&priv->lock, flags);
7584 return 0;
7585 }
7586 memcpy(&measure_report, &priv->measure_report, size);
7587 priv->measurement_status = 0;
7588 spin_unlock_irqrestore(&priv->lock, flags);
7589
7590 while (size && (PAGE_SIZE - len)) {
7591 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
7592 PAGE_SIZE - len, 1);
7593 len = strlen(buf);
7594 if (PAGE_SIZE - len)
7595 buf[len++] = '\n';
7596
7597 ofs += 16;
7598 size -= min(size, 16U);
7599 }
7600
7601 return len;
7602}
7603
7604static ssize_t store_measurement(struct device *d,
7605 struct device_attribute *attr,
7606 const char *buf, size_t count)
7607{
bb8c093b 7608 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7609 struct ieee80211_measurement_params params = {
7610 .channel = le16_to_cpu(priv->active_rxon.channel),
7611 .start_time = cpu_to_le64(priv->last_tsf),
7612 .duration = cpu_to_le16(1),
7613 };
7614 u8 type = IWL_MEASURE_BASIC;
7615 u8 buffer[32];
7616 u8 channel;
7617
7618 if (count) {
7619 char *p = buffer;
7620 strncpy(buffer, buf, min(sizeof(buffer), count));
7621 channel = simple_strtoul(p, NULL, 0);
7622 if (channel)
7623 params.channel = channel;
7624
7625 p = buffer;
7626 while (*p && *p != ' ')
7627 p++;
7628 if (*p)
7629 type = simple_strtoul(p + 1, NULL, 0);
7630 }
7631
7632 IWL_DEBUG_INFO("Invoking measurement of type %d on "
7633 "channel %d (for '%s')\n", type, params.channel, buf);
bb8c093b 7634 iwl3945_get_measurement(priv, &params, type);
b481de9c
ZY		 7635
7636 return count;
7637}
7638
7639static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
7640 show_measurement, store_measurement);
c8b0e6e1 7641#endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
b481de9c 7642
b481de9c
ZY		 7643static ssize_t store_retry_rate(struct device *d,
7644 struct device_attribute *attr,
7645 const char *buf, size_t count)
7646{
bb8c093b 7647 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7648
7649 priv->retry_rate = simple_strtoul(buf, NULL, 0);
7650 if (priv->retry_rate <= 0)
7651 priv->retry_rate = 1;
7652
7653 return count;
7654}
7655
7656static ssize_t show_retry_rate(struct device *d,
7657 struct device_attribute *attr, char *buf)
7658{
bb8c093b 7659 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7660 return sprintf(buf, "%d", priv->retry_rate);
7661}
7662
7663static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
7664 store_retry_rate);
7665
7666static ssize_t store_power_level(struct device *d,
7667 struct device_attribute *attr,
7668 const char *buf, size_t count)
7669{
bb8c093b 7670 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7671 int rc;
7672 int mode;
7673
7674 mode = simple_strtoul(buf, NULL, 0);
7675 mutex_lock(&priv->mutex);
7676
bb8c093b 7677 if (!iwl3945_is_ready(priv)) {
b481de9c
ZY		 7678 rc = -EAGAIN;
7679 goto out;
7680 }
7681
7682 if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
7683 mode = IWL_POWER_AC;
7684 else
7685 mode |= IWL_POWER_ENABLED;
7686
7687 if (mode != priv->power_mode) {
bb8c093b 7688 rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
b481de9c
ZY		 7689 if (rc) {
7690 IWL_DEBUG_MAC80211("failed setting power mode.\n");
7691 goto out;
7692 }
7693 priv->power_mode = mode;
7694 }
7695
7696 rc = count;
7697
7698 out:
7699 mutex_unlock(&priv->mutex);
7700 return rc;
7701}
7702
7703#define MAX_WX_STRING 80
7704
7705/* Values are in microsecond */
7706static const s32 timeout_duration[] = {
7707 350000,
7708 250000,
7709 75000,
7710 37000,
7711 25000,
7712};
7713static const s32 period_duration[] = {
7714 400000,
7715 700000,
7716 1000000,
7717 1000000,
7718 1000000
7719};
7720
7721static ssize_t show_power_level(struct device *d,
7722 struct device_attribute *attr, char *buf)
7723{
bb8c093b 7724 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7725 int level = IWL_POWER_LEVEL(priv->power_mode);
7726 char *p = buf;
7727
7728 p += sprintf(p, "%d ", level);
7729 switch (level) {
7730 case IWL_POWER_MODE_CAM:
7731 case IWL_POWER_AC:
7732 p += sprintf(p, "(AC)");
7733 break;
7734 case IWL_POWER_BATTERY:
7735 p += sprintf(p, "(BATTERY)");
7736 break;
7737 default:
7738 p += sprintf(p,
7739 "(Timeout %dms, Period %dms)",
7740 timeout_duration[level - 1] / 1000,
7741 period_duration[level - 1] / 1000);
7742 }
7743
7744 if (!(priv->power_mode & IWL_POWER_ENABLED))
7745 p += sprintf(p, " OFF\n");
7746 else
7747 p += sprintf(p, " \n");
7748
7749 return (p - buf + 1);
7750
7751}
7752
7753static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
7754 store_power_level);
7755
7756static ssize_t show_channels(struct device *d,
7757 struct device_attribute *attr, char *buf)
7758{
8318d78a
JB		 7759 /* all this shit doesn't belong into sysfs anyway */
7760 return 0;
b481de9c
ZY		 7761}
7762
7763static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
7764
7765static ssize_t show_statistics(struct device *d,
7766 struct device_attribute *attr, char *buf)
7767{
bb8c093b
CH		 7768 struct iwl3945_priv *priv = dev_get_drvdata(d);
7769 u32 size = sizeof(struct iwl3945_notif_statistics);
b481de9c
ZY		 7770 u32 len = 0, ofs = 0;
7771 u8 *data = (u8 *) & priv->statistics;
7772 int rc = 0;
7773
bb8c093b 7774 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7775 return -EAGAIN;
7776
7777 mutex_lock(&priv->mutex);
bb8c093b 7778 rc = iwl3945_send_statistics_request(priv);
b481de9c
ZY		 7779 mutex_unlock(&priv->mutex);
7780
7781 if (rc) {
7782 len = sprintf(buf,
7783 "Error sending statistics request: 0x%08X\n", rc);
7784 return len;
7785 }
7786
7787 while (size && (PAGE_SIZE - len)) {
7788 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
7789 PAGE_SIZE - len, 1);
7790 len = strlen(buf);
7791 if (PAGE_SIZE - len)
7792 buf[len++] = '\n';
7793
7794 ofs += 16;
7795 size -= min(size, 16U);
7796 }
7797
7798 return len;
7799}
7800
7801static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
7802
7803static ssize_t show_antenna(struct device *d,
7804 struct device_attribute *attr, char *buf)
7805{
bb8c093b 7806 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c 7807
bb8c093b 7808 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7809 return -EAGAIN;
7810
7811 return sprintf(buf, "%d\n", priv->antenna);
7812}
7813
7814static ssize_t store_antenna(struct device *d,
7815 struct device_attribute *attr,
7816 const char *buf, size_t count)
7817{
7818 int ant;
bb8c093b 7819 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7820
7821 if (count == 0)
7822 return 0;
7823
7824 if (sscanf(buf, "%1i", &ant) != 1) {
7825 IWL_DEBUG_INFO("not in hex or decimal form.\n");
7826 return count;
7827 }
7828
7829 if ((ant >= 0) && (ant <= 2)) {
7830 IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
bb8c093b 7831 priv->antenna = (enum iwl3945_antenna)ant;
b481de9c
ZY		 7832 } else
7833 IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
7834
7835
7836 return count;
7837}
7838
7839static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
7840
7841static ssize_t show_status(struct device *d,
7842 struct device_attribute *attr, char *buf)
7843{
bb8c093b
CH		 7844 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
7845 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7846 return -EAGAIN;
7847 return sprintf(buf, "0x%08x\n", (int)priv->status);
7848}
7849
7850static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
7851
7852static ssize_t dump_error_log(struct device *d,
7853 struct device_attribute *attr,
7854 const char *buf, size_t count)
7855{
7856 char *p = (char *)buf;
7857
7858 if (p[0] == '1')
bb8c093b 7859 iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data);
b481de9c
ZY		 7860
7861 return strnlen(buf, count);
7862}
7863
7864static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
7865
7866static ssize_t dump_event_log(struct device *d,
7867 struct device_attribute *attr,
7868 const char *buf, size_t count)
7869{
7870 char *p = (char *)buf;
7871
7872 if (p[0] == '1')
bb8c093b 7873 iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data);
b481de9c
ZY		 7874
7875 return strnlen(buf, count);
7876}
7877
7878static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
7879
7880/*****************************************************************************
7881 *
7882 * driver setup and teardown
7883 *
7884 *****************************************************************************/
7885
bb8c093b 7886static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv)
b481de9c
ZY		 7887{
7888 priv->workqueue = create_workqueue(DRV_NAME);
7889
7890 init_waitqueue_head(&priv->wait_command_queue);
7891
bb8c093b
CH		 7892 INIT_WORK(&priv->up, iwl3945_bg_up);
7893 INIT_WORK(&priv->restart, iwl3945_bg_restart);
7894 INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
7895 INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
7896 INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
7897 INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
7898 INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
7899 INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
5ec03976 7900 INIT_WORK(&priv->set_monitor, iwl3945_bg_set_monitor);
bb8c093b
CH		 7901 INIT_DELAYED_WORK(&priv->post_associate, iwl3945_bg_post_associate);
7902 INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
7903 INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
7904 INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
7905
7906 iwl3945_hw_setup_deferred_work(priv);
b481de9c
ZY		 7907
7908 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
bb8c093b 7909 iwl3945_irq_tasklet, (unsigned long)priv);
b481de9c
ZY		 7910}
7911
bb8c093b 7912static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv)
b481de9c 7913{
bb8c093b 7914 iwl3945_hw_cancel_deferred_work(priv);
b481de9c 7915
e47eb6ad 7916 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY		 7917 cancel_delayed_work(&priv->scan_check);
7918 cancel_delayed_work(&priv->alive_start);
7919 cancel_delayed_work(&priv->post_associate);
7920 cancel_work_sync(&priv->beacon_update);
7921}
7922
bb8c093b 7923static struct attribute *iwl3945_sysfs_entries[] = {
b481de9c
ZY		 7924 &dev_attr_antenna.attr,
7925 &dev_attr_channels.attr,
7926 &dev_attr_dump_errors.attr,
7927 &dev_attr_dump_events.attr,
7928 &dev_attr_flags.attr,
7929 &dev_attr_filter_flags.attr,
c8b0e6e1 7930#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 7931 &dev_attr_measurement.attr,
7932#endif
7933 &dev_attr_power_level.attr,
b481de9c
ZY		 7934 &dev_attr_retry_rate.attr,
7935 &dev_attr_rf_kill.attr,
7936 &dev_attr_rs_window.attr,
7937 &dev_attr_statistics.attr,
7938 &dev_attr_status.attr,
7939 &dev_attr_temperature.attr,
b481de9c
ZY		 7940 &dev_attr_tx_power.attr,
7941
7942 NULL
7943};
7944
bb8c093b 7945static struct attribute_group iwl3945_attribute_group = {
b481de9c 7946 .name = NULL, /* put in device directory */
bb8c093b 7947 .attrs = iwl3945_sysfs_entries,
b481de9c
ZY		 7948};
7949
bb8c093b
CH		 7950static struct ieee80211_ops iwl3945_hw_ops = {
7951 .tx = iwl3945_mac_tx,
7952 .start = iwl3945_mac_start,
7953 .stop = iwl3945_mac_stop,
7954 .add_interface = iwl3945_mac_add_interface,
7955 .remove_interface = iwl3945_mac_remove_interface,
7956 .config = iwl3945_mac_config,
7957 .config_interface = iwl3945_mac_config_interface,
7958 .configure_filter = iwl3945_configure_filter,
7959 .set_key = iwl3945_mac_set_key,
7960 .get_stats = iwl3945_mac_get_stats,
7961 .get_tx_stats = iwl3945_mac_get_tx_stats,
7962 .conf_tx = iwl3945_mac_conf_tx,
7963 .get_tsf = iwl3945_mac_get_tsf,
7964 .reset_tsf = iwl3945_mac_reset_tsf,
7965 .beacon_update = iwl3945_mac_beacon_update,
7966 .hw_scan = iwl3945_mac_hw_scan
b481de9c
ZY		 7967};
7968
bb8c093b 7969static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY		 7970{
7971 int err = 0;
bb8c093b 7972 struct iwl3945_priv *priv;
b481de9c 7973 struct ieee80211_hw *hw;
82b9a121 7974 struct iwl_3945_cfg *cfg = (struct iwl_3945_cfg *)(ent->driver_data);
b481de9c 7975 int i;
0359facc 7976 unsigned long flags;
5a66926a 7977 DECLARE_MAC_BUF(mac);
b481de9c 7978
6440adb5
CB		 7979 /* Disabling hardware scan means that mac80211 will perform scans
7980 * "the hard way", rather than using device's scan. */
bb8c093b 7981 if (iwl3945_param_disable_hw_scan) {
b481de9c 7982 IWL_DEBUG_INFO("Disabling hw_scan\n");
bb8c093b 7983 iwl3945_hw_ops.hw_scan = NULL;
b481de9c
ZY		 7984 }
7985
dfe7d458 7986 if ((iwl3945_param_queues_num > IWL39_MAX_NUM_QUEUES) ||
bb8c093b 7987 (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) {
b481de9c 7988 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
dfe7d458 7989 IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES);
b481de9c
ZY		 7990 err = -EINVAL;
7991 goto out;
7992 }
7993
7994 /* mac80211 allocates memory for this device instance, including
7995 * space for this driver's private structure */
bb8c093b 7996 hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops);
b481de9c
ZY		 7997 if (hw == NULL) {
7998 IWL_ERROR("Can not allocate network device\n");
7999 err = -ENOMEM;
8000 goto out;
8001 }
8002 SET_IEEE80211_DEV(hw, &pdev->dev);
8003
f51359a8
JB		 8004 hw->rate_control_algorithm = "iwl-3945-rs";
8005
b481de9c
ZY		 8006 IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
8007 priv = hw->priv;
8008 priv->hw = hw;
8009
8010 priv->pci_dev = pdev;
82b9a121 8011 priv->cfg = cfg;
6440adb5
CB		 8012
8013 /* Select antenna (may be helpful if only one antenna is connected) */
bb8c093b 8014 priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna;
c8b0e6e1 8015#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8016 iwl3945_debug_level = iwl3945_param_debug;
b481de9c
ZY		 8017 atomic_set(&priv->restrict_refcnt, 0);
8018#endif
8019 priv->retry_rate = 1;
8020
8021 priv->ibss_beacon = NULL;
8022
566bfe5a
BR		 8023 /* Tell mac80211 our characteristics */
8024 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
8025 IEEE80211_HW_SIGNAL_DBM |
8026 IEEE80211_HW_NOISE_DBM;
b481de9c 8027
6440adb5 8028 /* 4 EDCA QOS priorities */
b481de9c
ZY		 8029 hw->queues = 4;
8030
8031 spin_lock_init(&priv->lock);
8032 spin_lock_init(&priv->power_data.lock);
8033 spin_lock_init(&priv->sta_lock);
8034 spin_lock_init(&priv->hcmd_lock);
8035
8036 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
8037 INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
8038
8039 INIT_LIST_HEAD(&priv->free_frames);
8040
8041 mutex_init(&priv->mutex);
8042 if (pci_enable_device(pdev)) {
8043 err = -ENODEV;
8044 goto out_ieee80211_free_hw;
8045 }
8046
8047 pci_set_master(pdev);
8048
6440adb5 8049 /* Clear the driver's (not device's) station table */
bb8c093b 8050 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 8051
8052 priv->data_retry_limit = -1;
8053 priv->ieee_channels = NULL;
8054 priv->ieee_rates = NULL;
8318d78a 8055 priv->band = IEEE80211_BAND_2GHZ;
b481de9c
ZY		 8056
8057 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
8058 if (!err)
8059 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
8060 if (err) {
8061 printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
8062 goto out_pci_disable_device;
8063 }
8064
8065 pci_set_drvdata(pdev, priv);
8066 err = pci_request_regions(pdev, DRV_NAME);
8067 if (err)
8068 goto out_pci_disable_device;
6440adb5 8069
b481de9c
ZY		 8070 /* We disable the RETRY_TIMEOUT register (0x41) to keep
8071 * PCI Tx retries from interfering with C3 CPU state */
8072 pci_write_config_byte(pdev, 0x41, 0x00);
6440adb5 8073
b481de9c
ZY		 8074 priv->hw_base = pci_iomap(pdev, 0, 0);
8075 if (!priv->hw_base) {
8076 err = -ENODEV;
8077 goto out_pci_release_regions;
8078 }
8079
8080 IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
8081 (unsigned long long) pci_resource_len(pdev, 0));
8082 IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
8083
8084 /* Initialize module parameter values here */
8085
6440adb5 8086 /* Disable radio (SW RF KILL) via parameter when loading driver */
bb8c093b 8087 if (iwl3945_param_disable) {
b481de9c
ZY		 8088 set_bit(STATUS_RF_KILL_SW, &priv->status);
8089 IWL_DEBUG_INFO("Radio disabled.\n");
8090 }
8091
8092 priv->iw_mode = IEEE80211_IF_TYPE_STA;
8093
b481de9c 8094 printk(KERN_INFO DRV_NAME
82b9a121 8095 ": Detected Intel Wireless WiFi Link %s\n", priv->cfg->name);
b481de9c
ZY		 8096
8097 /* Device-specific setup */
bb8c093b 8098 if (iwl3945_hw_set_hw_setting(priv)) {
b481de9c 8099 IWL_ERROR("failed to set hw settings\n");
b481de9c
ZY		 8100 goto out_iounmap;
8101 }
8102
bb8c093b 8103 if (iwl3945_param_qos_enable)
b481de9c
ZY		 8104 priv->qos_data.qos_enable = 1;
8105
bb8c093b 8106 iwl3945_reset_qos(priv);
b481de9c
ZY		 8107
8108 priv->qos_data.qos_active = 0;
8109 priv->qos_data.qos_cap.val = 0;
b481de9c 8110
8318d78a 8111 iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
bb8c093b
CH		 8112 iwl3945_setup_deferred_work(priv);
8113 iwl3945_setup_rx_handlers(priv);
b481de9c
ZY		 8114
8115 priv->rates_mask = IWL_RATES_MASK;
8116 /* If power management is turned on, default to AC mode */
8117 priv->power_mode = IWL_POWER_AC;
8118 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
8119
0359facc 8120 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 8121 iwl3945_disable_interrupts(priv);
0359facc 8122 spin_unlock_irqrestore(&priv->lock, flags);
49df2b33 8123
bb8c093b 8124 err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c
ZY		 8125 if (err) {
8126 IWL_ERROR("failed to create sysfs device attributes\n");
b481de9c
ZY		 8127 goto out_release_irq;
8128 }
8129
5a66926a
ZY		 8130 /* nic init */
8131 iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
8132 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
8133
8134 iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
8135 err = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
8136 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
8137 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
8138 if (err < 0) {
8139 IWL_DEBUG_INFO("Failed to init the card\n");
8140 goto out_remove_sysfs;
8141 }
8142 /* Read the EEPROM */
8143 err = iwl3945_eeprom_init(priv);
b481de9c 8144 if (err) {
5a66926a
ZY		 8145 IWL_ERROR("Unable to init EEPROM\n");
8146 goto out_remove_sysfs;
b481de9c 8147 }
5a66926a
ZY		 8148 /* MAC Address location in EEPROM same for 3945/4965 */
8149 get_eeprom_mac(priv, priv->mac_addr);
8150 IWL_DEBUG_INFO("MAC address: %s\n", print_mac(mac, priv->mac_addr));
8151 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
b481de9c 8152
849e0dce
RC		 8153 err = iwl3945_init_channel_map(priv);
8154 if (err) {
8155 IWL_ERROR("initializing regulatory failed: %d\n", err);
8156 goto out_remove_sysfs;
8157 }
8158
8159 err = iwl3945_init_geos(priv);
8160 if (err) {
8161 IWL_ERROR("initializing geos failed: %d\n", err);
8162 goto out_free_channel_map;
8163 }
849e0dce 8164
5a66926a
ZY		 8165 err = ieee80211_register_hw(priv->hw);
8166 if (err) {
8167 IWL_ERROR("Failed to register network device (error %d)\n", err);
849e0dce 8168 goto out_free_geos;
5a66926a 8169 }
b481de9c 8170
5a66926a
ZY		 8171 priv->hw->conf.beacon_int = 100;
8172 priv->mac80211_registered = 1;
8173 pci_save_state(pdev);
8174 pci_disable_device(pdev);
b481de9c
ZY		 8175
8176 return 0;
8177
849e0dce
RC		 8178 out_free_geos:
8179 iwl3945_free_geos(priv);
8180 out_free_channel_map:
8181 iwl3945_free_channel_map(priv);
5a66926a 8182 out_remove_sysfs:
bb8c093b 8183 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c
ZY		 8184
8185 out_release_irq:
b481de9c
ZY		 8186 destroy_workqueue(priv->workqueue);
8187 priv->workqueue = NULL;
bb8c093b 8188 iwl3945_unset_hw_setting(priv);
b481de9c
ZY		 8189
8190 out_iounmap:
8191 pci_iounmap(pdev, priv->hw_base);
8192 out_pci_release_regions:
8193 pci_release_regions(pdev);
8194 out_pci_disable_device:
8195 pci_disable_device(pdev);
8196 pci_set_drvdata(pdev, NULL);
8197 out_ieee80211_free_hw:
8198 ieee80211_free_hw(priv->hw);
8199 out:
8200 return err;
8201}
8202
c83dbf68 8203static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
b481de9c 8204{
bb8c093b 8205 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c
ZY		 8206 struct list_head *p, *q;
8207 int i;
0359facc 8208 unsigned long flags;
b481de9c
ZY		 8209
8210 if (!priv)
8211 return;
8212
8213 IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
8214
b481de9c 8215 set_bit(STATUS_EXIT_PENDING, &priv->status);
b24d22b1 8216
bb8c093b 8217 iwl3945_down(priv);
b481de9c 8218
0359facc
MA		 8219 /* make sure we flush any pending irq or
8220 * tasklet for the driver
8221 */
8222 spin_lock_irqsave(&priv->lock, flags);
8223 iwl3945_disable_interrupts(priv);
8224 spin_unlock_irqrestore(&priv->lock, flags);
8225
8226 iwl_synchronize_irq(priv);
8227
b481de9c
ZY		 8228 /* Free MAC hash list for ADHOC */
8229 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) {
8230 list_for_each_safe(p, q, &priv->ibss_mac_hash[i]) {
8231 list_del(p);
bb8c093b 8232 kfree(list_entry(p, struct iwl3945_ibss_seq, list));
b481de9c
ZY		 8233 }
8234 }
8235
bb8c093b 8236 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 8237
bb8c093b 8238 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY		 8239
8240 if (priv->rxq.bd)
bb8c093b
CH		 8241 iwl3945_rx_queue_free(priv, &priv->rxq);
8242 iwl3945_hw_txq_ctx_free(priv);
b481de9c 8243
bb8c093b
CH		 8244 iwl3945_unset_hw_setting(priv);
8245 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 8246
8247 if (priv->mac80211_registered) {
8248 ieee80211_unregister_hw(priv->hw);
b481de9c
ZY		 8249 }
8250
6ef89d0a
MA		 8251 /*netif_stop_queue(dev); */
8252 flush_workqueue(priv->workqueue);
8253
bb8c093b 8254 /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
b481de9c
ZY		 8255 * priv->workqueue... so we can't take down the workqueue
8256 * until now... */
8257 destroy_workqueue(priv->workqueue);
8258 priv->workqueue = NULL;
8259
b481de9c
ZY		 8260 pci_iounmap(pdev, priv->hw_base);
8261 pci_release_regions(pdev);
8262 pci_disable_device(pdev);
8263 pci_set_drvdata(pdev, NULL);
8264
849e0dce
RC		 8265 iwl3945_free_channel_map(priv);
8266 iwl3945_free_geos(priv);
b481de9c
ZY		 8267
8268 if (priv->ibss_beacon)
8269 dev_kfree_skb(priv->ibss_beacon);
8270
8271 ieee80211_free_hw(priv->hw);
8272}
8273
8274#ifdef CONFIG_PM
8275
bb8c093b 8276static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
b481de9c 8277{
bb8c093b 8278 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c 8279
e655b9f0
ZY		 8280 if (priv->is_open) {
8281 set_bit(STATUS_IN_SUSPEND, &priv->status);
8282 iwl3945_mac_stop(priv->hw);
8283 priv->is_open = 1;
8284 }
b481de9c 8285
b481de9c
ZY		 8286 pci_set_power_state(pdev, PCI_D3hot);
8287
b481de9c
ZY		 8288 return 0;
8289}
8290
bb8c093b 8291static int iwl3945_pci_resume(struct pci_dev *pdev)
b481de9c 8292{
bb8c093b 8293 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c 8294
b481de9c 8295 pci_set_power_state(pdev, PCI_D0);
b481de9c 8296
e655b9f0
ZY		 8297 if (priv->is_open)
8298 iwl3945_mac_start(priv->hw);
b481de9c 8299
e655b9f0 8300 clear_bit(STATUS_IN_SUSPEND, &priv->status);
b481de9c
ZY		 8301 return 0;
8302}
8303
8304#endif /* CONFIG_PM */
8305
8306/*****************************************************************************
8307 *
8308 * driver and module entry point
8309 *
8310 *****************************************************************************/
8311
bb8c093b 8312static struct pci_driver iwl3945_driver = {
b481de9c 8313 .name = DRV_NAME,
bb8c093b
CH		 8314 .id_table = iwl3945_hw_card_ids,
8315 .probe = iwl3945_pci_probe,
8316 .remove = __devexit_p(iwl3945_pci_remove),
b481de9c 8317#ifdef CONFIG_PM
bb8c093b
CH		 8318 .suspend = iwl3945_pci_suspend,
8319 .resume = iwl3945_pci_resume,
b481de9c
ZY		 8320#endif
8321};
8322
bb8c093b 8323static int __init iwl3945_init(void)
b481de9c
ZY		 8324{
8325
8326 int ret;
8327 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
8328 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2
RC		 8329
8330 ret = iwl3945_rate_control_register();
8331 if (ret) {
8332 IWL_ERROR("Unable to register rate control algorithm: %d\n", ret);
8333 return ret;
8334 }
8335
bb8c093b 8336 ret = pci_register_driver(&iwl3945_driver);
b481de9c
ZY		 8337 if (ret) {
8338 IWL_ERROR("Unable to initialize PCI module\n");
897e1cf2 8339 goto error_register;
b481de9c 8340 }
c8b0e6e1 8341#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8342 ret = driver_create_file(&iwl3945_driver.driver, &driver_attr_debug_level);
b481de9c
ZY		 8343 if (ret) {
8344 IWL_ERROR("Unable to create driver sysfs file\n");
897e1cf2 8345 goto error_debug;
b481de9c
ZY		 8346 }
8347#endif
8348
8349 return ret;
897e1cf2
RC		 8350
8351#ifdef CONFIG_IWL3945_DEBUG
8352error_debug:
8353 pci_unregister_driver(&iwl3945_driver);
8354#endif
8355error_register:
8356 iwl3945_rate_control_unregister();
8357 return ret;
b481de9c
ZY		 8358}
8359
bb8c093b 8360static void __exit iwl3945_exit(void)
b481de9c 8361{
c8b0e6e1 8362#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8363 driver_remove_file(&iwl3945_driver.driver, &driver_attr_debug_level);
b481de9c 8364#endif
bb8c093b 8365 pci_unregister_driver(&iwl3945_driver);
897e1cf2 8366 iwl3945_rate_control_unregister();
b481de9c
ZY		 8367}
8368
bb8c093b 8369module_param_named(antenna, iwl3945_param_antenna, int, 0444);
b481de9c 8370MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
bb8c093b 8371module_param_named(disable, iwl3945_param_disable, int, 0444);
b481de9c 8372MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
bb8c093b 8373module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444);
b481de9c
ZY		 8374MODULE_PARM_DESC(hwcrypto,
8375 "using hardware crypto engine (default 0 [software])\n");
bb8c093b 8376module_param_named(debug, iwl3945_param_debug, int, 0444);
b481de9c 8377MODULE_PARM_DESC(debug, "debug output mask");
bb8c093b 8378module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444);
b481de9c
ZY		 8379MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
8380
bb8c093b 8381module_param_named(queues_num, iwl3945_param_queues_num, int, 0444);
b481de9c
ZY		 8382MODULE_PARM_DESC(queues_num, "number of hw queues.");
8383
8384/* QoS */
bb8c093b 8385module_param_named(qos_enable, iwl3945_param_qos_enable, int, 0444);
b481de9c
ZY		 8386MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
8387
bb8c093b
CH		 8388module_exit(iwl3945_exit);
8389module_init(iwl3945_init);
Linux kernel - Deliverables
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