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mac80211: use multi-queue master netdevice
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl3945-base.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
b481de9c
ZY		 30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/version.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/dma-mapping.h>
36#include <linux/delay.h>
37#include <linux/skbuff.h>
38#include <linux/netdevice.h>
39#include <linux/wireless.h>
40#include <linux/firmware.h>
b481de9c
ZY		 41#include <linux/etherdevice.h>
42#include <linux/if_arp.h>
43
44#include <net/ieee80211_radiotap.h>
45#include <net/mac80211.h>
46
47#include <asm/div64.h>
48
82b9a121 49#include "iwl-3945-core.h"
b481de9c
ZY		 50#include "iwl-3945.h"
51#include "iwl-helpers.h"
52
c8b0e6e1 53#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 54u32 iwl3945_debug_level;
b481de9c
ZY		 55#endif
56
bb8c093b
CH		 57static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
58 struct iwl3945_tx_queue *txq);
416e1438 59
b481de9c
ZY		 60/******************************************************************************
61 *
62 * module boiler plate
63 *
64 ******************************************************************************/
65
66/* module parameters */
6440adb5
CB		 67static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */
68static int iwl3945_param_debug; /* def: 0 = minimal debug log messages */
69static int iwl3945_param_disable; /* def: 0 = enable radio */
9fbab516 70static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */
6440adb5
CB		 71int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */
72static int iwl3945_param_qos_enable = 1; /* def: 1 = use quality of service */
dfe7d458 73int iwl3945_param_queues_num = IWL39_MAX_NUM_QUEUES; /* def: 8 Tx queues */
b481de9c
ZY		 74
75/*
76 * module name, copyright, version, etc.
77 * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
78 */
79
80#define DRV_DESCRIPTION \
81"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
82
c8b0e6e1 83#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 84#define VD "d"
85#else
86#define VD
87#endif
88
c8b0e6e1 89#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 90#define VS "s"
91#else
92#define VS
93#endif
94
b9e0b449 95#define IWLWIFI_VERSION "1.2.26k" VD VS
eb7ae89c 96#define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation"
b481de9c
ZY		 97#define DRV_VERSION IWLWIFI_VERSION
98
b481de9c
ZY		 99
100MODULE_DESCRIPTION(DRV_DESCRIPTION);
101MODULE_VERSION(DRV_VERSION);
102MODULE_AUTHOR(DRV_COPYRIGHT);
103MODULE_LICENSE("GPL");
104
8318d78a
JB		 105static const struct ieee80211_supported_band *iwl3945_get_band(
106 struct iwl3945_priv *priv, enum ieee80211_band band)
b481de9c 107{
8318d78a 108 return priv->hw->wiphy->bands[band];
b481de9c
ZY		 109}
110
bb8c093b 111static int iwl3945_is_empty_essid(const char *essid, int essid_len)
b481de9c
ZY		 112{
113 /* Single white space is for Linksys APs */
114 if (essid_len == 1 && essid[0] == ' ')
115 return 1;
116
117 /* Otherwise, if the entire essid is 0, we assume it is hidden */
118 while (essid_len) {
119 essid_len--;
120 if (essid[essid_len] != '\0')
121 return 0;
122 }
123
124 return 1;
125}
126
bb8c093b 127static const char *iwl3945_escape_essid(const char *essid, u8 essid_len)
b481de9c
ZY		 128{
129 static char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
130 const char *s = essid;
131 char *d = escaped;
132
bb8c093b 133 if (iwl3945_is_empty_essid(essid, essid_len)) {
b481de9c
ZY		 134 memcpy(escaped, "<hidden>", sizeof("<hidden>"));
135 return escaped;
136 }
137
138 essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE);
139 while (essid_len--) {
140 if (*s == '\0') {
141 *d++ = '\\';
142 *d++ = '0';
143 s++;
144 } else
145 *d++ = *s++;
146 }
147 *d = '\0';
148 return escaped;
149}
150
b481de9c
ZY		 151/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
152 * DMA services
153 *
154 * Theory of operation
155 *
6440adb5
CB		 156 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
157 * of buffer descriptors, each of which points to one or more data buffers for
158 * the device to read from or fill. Driver and device exchange status of each
159 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
160 * entries in each circular buffer, to protect against confusing empty and full
161 * queue states.
162 *
163 * The device reads or writes the data in the queues via the device's several
164 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
b481de9c
ZY		 165 *
166 * For Tx queue, there are low mark and high mark limits. If, after queuing
167 * the packet for Tx, free space become < low mark, Tx queue stopped. When
168 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
169 * Tx queue resumed.
170 *
6440adb5
CB		 171 * The 3945 operates with six queues: One receive queue, one transmit queue
172 * (#4) for sending commands to the device firmware, and four transmit queues
173 * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
b481de9c
ZY		 174 ***************************************************/
175
c54b679d 176int iwl3945_queue_space(const struct iwl3945_queue *q)
b481de9c 177{
fc4b6853 178 int s = q->read_ptr - q->write_ptr;
b481de9c 179
fc4b6853 180 if (q->read_ptr > q->write_ptr)
b481de9c
ZY		 181 s -= q->n_bd;
182
183 if (s <= 0)
184 s += q->n_window;
185 /* keep some reserve to not confuse empty and full situations */
186 s -= 2;
187 if (s < 0)
188 s = 0;
189 return s;
190}
191
c54b679d 192int iwl3945_x2_queue_used(const struct iwl3945_queue *q, int i)
b481de9c 193{
fc4b6853
TW		 194 return q->write_ptr > q->read_ptr ?
195 (i >= q->read_ptr && i < q->write_ptr) :
196 !(i < q->read_ptr && i >= q->write_ptr);
b481de9c
ZY		 197}
198
c54b679d 199
bb8c093b 200static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge)
b481de9c 201{
6440adb5 202 /* This is for scan command, the big buffer at end of command array */
b481de9c 203 if (is_huge)
6440adb5 204 return q->n_window; /* must be power of 2 */
b481de9c 205
6440adb5 206 /* Otherwise, use normal size buffers */
b481de9c
ZY		 207 return index & (q->n_window - 1);
208}
209
6440adb5
CB		 210/**
211 * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
212 */
bb8c093b 213static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q,
b481de9c
ZY		 214 int count, int slots_num, u32 id)
215{
216 q->n_bd = count;
217 q->n_window = slots_num;
218 q->id = id;
219
c54b679d
TW		 220 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
221 * and iwl_queue_dec_wrap are broken. */
b481de9c
ZY		 222 BUG_ON(!is_power_of_2(count));
223
224 /* slots_num must be power-of-two size, otherwise
225 * get_cmd_index is broken. */
226 BUG_ON(!is_power_of_2(slots_num));
227
228 q->low_mark = q->n_window / 4;
229 if (q->low_mark < 4)
230 q->low_mark = 4;
231
232 q->high_mark = q->n_window / 8;
233 if (q->high_mark < 2)
234 q->high_mark = 2;
235
fc4b6853 236 q->write_ptr = q->read_ptr = 0;
b481de9c
ZY		 237
238 return 0;
239}
240
6440adb5
CB		 241/**
242 * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
243 */
bb8c093b
CH		 244static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
245 struct iwl3945_tx_queue *txq, u32 id)
b481de9c
ZY		 246{
247 struct pci_dev *dev = priv->pci_dev;
248
6440adb5
CB		 249 /* Driver private data, only for Tx (not command) queues,
250 * not shared with device. */
b481de9c
ZY		 251 if (id != IWL_CMD_QUEUE_NUM) {
252 txq->txb = kmalloc(sizeof(txq->txb[0]) *
253 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
254 if (!txq->txb) {
01ebd063 255 IWL_ERROR("kmalloc for auxiliary BD "
b481de9c
ZY		 256 "structures failed\n");
257 goto error;
258 }
259 } else
260 txq->txb = NULL;
261
6440adb5
CB		 262 /* Circular buffer of transmit frame descriptors (TFDs),
263 * shared with device */
b481de9c
ZY		 264 txq->bd = pci_alloc_consistent(dev,
265 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
266 &txq->q.dma_addr);
267
268 if (!txq->bd) {
269 IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
270 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
271 goto error;
272 }
273 txq->q.id = id;
274
275 return 0;
276
277 error:
278 if (txq->txb) {
279 kfree(txq->txb);
280 txq->txb = NULL;
281 }
282
283 return -ENOMEM;
284}
285
6440adb5
CB		 286/**
287 * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
288 */
bb8c093b
CH		 289int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
290 struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
b481de9c
ZY		 291{
292 struct pci_dev *dev = priv->pci_dev;
293 int len;
294 int rc = 0;
295
6440adb5
CB		 296 /*
297 * Alloc buffer array for commands (Tx or other types of commands).
298 * For the command queue (#4), allocate command space + one big
299 * command for scan, since scan command is very huge; the system will
300 * not have two scans at the same time, so only one is needed.
301 * For data Tx queues (all other queues), no super-size command
302 * space is needed.
303 */
bb8c093b 304 len = sizeof(struct iwl3945_cmd) * slots_num;
b481de9c
ZY		 305 if (txq_id == IWL_CMD_QUEUE_NUM)
306 len += IWL_MAX_SCAN_SIZE;
307 txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
308 if (!txq->cmd)
309 return -ENOMEM;
310
6440adb5 311 /* Alloc driver data array and TFD circular buffer */
bb8c093b 312 rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
b481de9c
ZY		 313 if (rc) {
314 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
315
316 return -ENOMEM;
317 }
318 txq->need_update = 0;
319
320 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
c54b679d 321 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
b481de9c 322 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
6440adb5
CB		 323
324 /* Initialize queue high/low-water, head/tail indexes */
bb8c093b 325 iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
b481de9c 326
6440adb5 327 /* Tell device where to find queue, enable DMA channel. */
bb8c093b 328 iwl3945_hw_tx_queue_init(priv, txq);
b481de9c
ZY		 329
330 return 0;
331}
332
333/**
bb8c093b 334 * iwl3945_tx_queue_free - Deallocate DMA queue.
b481de9c
ZY		 335 * @txq: Transmit queue to deallocate.
336 *
337 * Empty queue by removing and destroying all BD's.
6440adb5
CB		 338 * Free all buffers.
339 * 0-fill, but do not free "txq" descriptor structure.
b481de9c 340 */
bb8c093b 341void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c 342{
bb8c093b 343 struct iwl3945_queue *q = &txq->q;
b481de9c
ZY		 344 struct pci_dev *dev = priv->pci_dev;
345 int len;
346
347 if (q->n_bd == 0)
348 return;
349
350 /* first, empty all BD's */
fc4b6853 351 for (; q->write_ptr != q->read_ptr;
c54b679d 352 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
bb8c093b 353 iwl3945_hw_txq_free_tfd(priv, txq);
b481de9c 354
bb8c093b 355 len = sizeof(struct iwl3945_cmd) * q->n_window;
b481de9c
ZY		 356 if (q->id == IWL_CMD_QUEUE_NUM)
357 len += IWL_MAX_SCAN_SIZE;
358
6440adb5 359 /* De-alloc array of command/tx buffers */
b481de9c
ZY		 360 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
361
6440adb5 362 /* De-alloc circular buffer of TFDs */
b481de9c 363 if (txq->q.n_bd)
bb8c093b 364 pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
b481de9c
ZY		 365 txq->q.n_bd, txq->bd, txq->q.dma_addr);
366
6440adb5 367 /* De-alloc array of per-TFD driver data */
b481de9c
ZY		 368 if (txq->txb) {
369 kfree(txq->txb);
370 txq->txb = NULL;
371 }
372
6440adb5 373 /* 0-fill queue descriptor structure */
b481de9c
ZY		 374 memset(txq, 0, sizeof(*txq));
375}
376
bb8c093b 377const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
b481de9c
ZY		 378
379/*************** STATION TABLE MANAGEMENT ****
9fbab516 380 * mac80211 should be examined to determine if sta_info is duplicating
b481de9c
ZY		 381 * the functionality provided here
382 */
383
384/**************************************************************/
01ebd063 385#if 0 /* temporary disable till we add real remove station */
6440adb5
CB		 386/**
387 * iwl3945_remove_station - Remove driver's knowledge of station.
388 *
389 * NOTE: This does not remove station from device's station table.
390 */
bb8c093b 391static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
b481de9c
ZY		 392{
393 int index = IWL_INVALID_STATION;
394 int i;
395 unsigned long flags;
396
397 spin_lock_irqsave(&priv->sta_lock, flags);
398
399 if (is_ap)
400 index = IWL_AP_ID;
401 else if (is_broadcast_ether_addr(addr))
402 index = priv->hw_setting.bcast_sta_id;
403 else
404 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
405 if (priv->stations[i].used &&
406 !compare_ether_addr(priv->stations[i].sta.sta.addr,
407 addr)) {
408 index = i;
409 break;
410 }
411
412 if (unlikely(index == IWL_INVALID_STATION))
413 goto out;
414
415 if (priv->stations[index].used) {
416 priv->stations[index].used = 0;
417 priv->num_stations--;
418 }
419
420 BUG_ON(priv->num_stations < 0);
421
422out:
423 spin_unlock_irqrestore(&priv->sta_lock, flags);
424 return 0;
425}
556f8db7 426#endif
6440adb5
CB		 427
428/**
429 * iwl3945_clear_stations_table - Clear the driver's station table
430 *
431 * NOTE: This does not clear or otherwise alter the device's station table.
432 */
bb8c093b 433static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
b481de9c
ZY		 434{
435 unsigned long flags;
436
437 spin_lock_irqsave(&priv->sta_lock, flags);
438
439 priv->num_stations = 0;
440 memset(priv->stations, 0, sizeof(priv->stations));
441
442 spin_unlock_irqrestore(&priv->sta_lock, flags);
443}
444
6440adb5
CB		 445/**
446 * iwl3945_add_station - Add station to station tables in driver and device
447 */
bb8c093b 448u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
b481de9c
ZY		 449{
450 int i;
451 int index = IWL_INVALID_STATION;
bb8c093b 452 struct iwl3945_station_entry *station;
b481de9c 453 unsigned long flags_spin;
0795af57 454 DECLARE_MAC_BUF(mac);
c14c521e 455 u8 rate;
b481de9c
ZY		 456
457 spin_lock_irqsave(&priv->sta_lock, flags_spin);
458 if (is_ap)
459 index = IWL_AP_ID;
460 else if (is_broadcast_ether_addr(addr))
461 index = priv->hw_setting.bcast_sta_id;
462 else
463 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
464 if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
465 addr)) {
466 index = i;
467 break;
468 }
469
470 if (!priv->stations[i].used &&
471 index == IWL_INVALID_STATION)
472 index = i;
473 }
474
01ebd063 475 /* These two conditions has the same outcome but keep them separate
b481de9c
ZY		 476 since they have different meaning */
477 if (unlikely(index == IWL_INVALID_STATION)) {
478 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
479 return index;
480 }
481
482 if (priv->stations[index].used &&
483 !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
484 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
485 return index;
486 }
487
0795af57 488 IWL_DEBUG_ASSOC("Add STA ID %d: %s\n", index, print_mac(mac, addr));
b481de9c
ZY		 489 station = &priv->stations[index];
490 station->used = 1;
491 priv->num_stations++;
492
6440adb5 493 /* Set up the REPLY_ADD_STA command to send to device */
bb8c093b 494 memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
b481de9c
ZY		 495 memcpy(station->sta.sta.addr, addr, ETH_ALEN);
496 station->sta.mode = 0;
497 station->sta.sta.sta_id = index;
498 station->sta.station_flags = 0;
499
8318d78a 500 if (priv->band == IEEE80211_BAND_5GHZ)
69946333
TW		 501 rate = IWL_RATE_6M_PLCP;
502 else
503 rate = IWL_RATE_1M_PLCP;
c14c521e
ZY		 504
505 /* Turn on both antennas for the station... */
506 station->sta.rate_n_flags =
bb8c093b 507 iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
c14c521e
ZY		 508 station->current_rate.rate_n_flags =
509 le16_to_cpu(station->sta.rate_n_flags);
510
b481de9c 511 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
6440adb5
CB		 512
513 /* Add station to device's station table */
bb8c093b 514 iwl3945_send_add_station(priv, &station->sta, flags);
b481de9c
ZY		 515 return index;
516
517}
518
519/*************** DRIVER STATUS FUNCTIONS *****/
520
bb8c093b 521static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
b481de9c
ZY		 522{
523 /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
524 * set but EXIT_PENDING is not */
525 return test_bit(STATUS_READY, &priv->status) &&
526 test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
527 !test_bit(STATUS_EXIT_PENDING, &priv->status);
528}
529
bb8c093b 530static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
b481de9c
ZY		 531{
532 return test_bit(STATUS_ALIVE, &priv->status);
533}
534
bb8c093b 535static inline int iwl3945_is_init(struct iwl3945_priv *priv)
b481de9c
ZY		 536{
537 return test_bit(STATUS_INIT, &priv->status);
538}
539
bb8c093b 540static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
b481de9c
ZY		 541{
542 return test_bit(STATUS_RF_KILL_HW, &priv->status) ||
543 test_bit(STATUS_RF_KILL_SW, &priv->status);
544}
545
bb8c093b 546static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
b481de9c
ZY		 547{
548
bb8c093b 549 if (iwl3945_is_rfkill(priv))
b481de9c
ZY		 550 return 0;
551
bb8c093b 552 return iwl3945_is_ready(priv);
b481de9c
ZY		 553}
554
555/*************** HOST COMMAND QUEUE FUNCTIONS *****/
556
557#define IWL_CMD(x) case x : return #x
558
559static const char *get_cmd_string(u8 cmd)
560{
561 switch (cmd) {
562 IWL_CMD(REPLY_ALIVE);
563 IWL_CMD(REPLY_ERROR);
564 IWL_CMD(REPLY_RXON);
565 IWL_CMD(REPLY_RXON_ASSOC);
566 IWL_CMD(REPLY_QOS_PARAM);
567 IWL_CMD(REPLY_RXON_TIMING);
568 IWL_CMD(REPLY_ADD_STA);
569 IWL_CMD(REPLY_REMOVE_STA);
570 IWL_CMD(REPLY_REMOVE_ALL_STA);
571 IWL_CMD(REPLY_3945_RX);
572 IWL_CMD(REPLY_TX);
573 IWL_CMD(REPLY_RATE_SCALE);
574 IWL_CMD(REPLY_LEDS_CMD);
575 IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
576 IWL_CMD(RADAR_NOTIFICATION);
577 IWL_CMD(REPLY_QUIET_CMD);
578 IWL_CMD(REPLY_CHANNEL_SWITCH);
579 IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
580 IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
581 IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
582 IWL_CMD(POWER_TABLE_CMD);
583 IWL_CMD(PM_SLEEP_NOTIFICATION);
584 IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
585 IWL_CMD(REPLY_SCAN_CMD);
586 IWL_CMD(REPLY_SCAN_ABORT_CMD);
587 IWL_CMD(SCAN_START_NOTIFICATION);
588 IWL_CMD(SCAN_RESULTS_NOTIFICATION);
589 IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
590 IWL_CMD(BEACON_NOTIFICATION);
591 IWL_CMD(REPLY_TX_BEACON);
592 IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
593 IWL_CMD(QUIET_NOTIFICATION);
594 IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
595 IWL_CMD(MEASURE_ABORT_NOTIFICATION);
596 IWL_CMD(REPLY_BT_CONFIG);
597 IWL_CMD(REPLY_STATISTICS_CMD);
598 IWL_CMD(STATISTICS_NOTIFICATION);
599 IWL_CMD(REPLY_CARD_STATE_CMD);
600 IWL_CMD(CARD_STATE_NOTIFICATION);
601 IWL_CMD(MISSED_BEACONS_NOTIFICATION);
602 default:
603 return "UNKNOWN";
604
605 }
606}
607
608#define HOST_COMPLETE_TIMEOUT (HZ / 2)
609
610/**
bb8c093b 611 * iwl3945_enqueue_hcmd - enqueue a uCode command
b481de9c
ZY		 612 * @priv: device private data point
613 * @cmd: a point to the ucode command structure
614 *
615 * The function returns < 0 values to indicate the operation is
616 * failed. On success, it turns the index (> 0) of command in the
617 * command queue.
618 */
bb8c093b 619static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c 620{
bb8c093b
CH		 621 struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
622 struct iwl3945_queue *q = &txq->q;
623 struct iwl3945_tfd_frame *tfd;
b481de9c 624 u32 *control_flags;
bb8c093b 625 struct iwl3945_cmd *out_cmd;
b481de9c
ZY		 626 u32 idx;
627 u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
628 dma_addr_t phys_addr;
629 int pad;
630 u16 count;
631 int ret;
632 unsigned long flags;
633
634 /* If any of the command structures end up being larger than
635 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
636 * we will need to increase the size of the TFD entries */
637 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
638 !(cmd->meta.flags & CMD_SIZE_HUGE));
639
c342a1b9
GG		 640
641 if (iwl3945_is_rfkill(priv)) {
642 IWL_DEBUG_INFO("Not sending command - RF KILL");
643 return -EIO;
644 }
645
bb8c093b 646 if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
b481de9c
ZY		 647 IWL_ERROR("No space for Tx\n");
648 return -ENOSPC;
649 }
650
651 spin_lock_irqsave(&priv->hcmd_lock, flags);
652
fc4b6853 653 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY		 654 memset(tfd, 0, sizeof(*tfd));
655
656 control_flags = (u32 *) tfd;
657
fc4b6853 658 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
b481de9c
ZY		 659 out_cmd = &txq->cmd[idx];
660
661 out_cmd->hdr.cmd = cmd->id;
662 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
663 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
664
665 /* At this point, the out_cmd now has all of the incoming cmd
666 * information */
667
668 out_cmd->hdr.flags = 0;
669 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
fc4b6853 670 INDEX_TO_SEQ(q->write_ptr));
b481de9c
ZY		 671 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
672 out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
673
674 phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
bb8c093b
CH		 675 offsetof(struct iwl3945_cmd, hdr);
676 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
b481de9c
ZY		 677
678 pad = U32_PAD(cmd->len);
679 count = TFD_CTL_COUNT_GET(*control_flags);
680 *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
681
682 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
683 "%d bytes at %d[%d]:%d\n",
684 get_cmd_string(out_cmd->hdr.cmd),
685 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
fc4b6853 686 fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
b481de9c
ZY		 687
688 txq->need_update = 1;
6440adb5
CB		 689
690 /* Increment and update queue's write index */
c54b679d 691 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
bb8c093b 692 ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 693
694 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
695 return ret ? ret : idx;
696}
697
bb8c093b 698static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c
ZY		 699{
700 int ret;
701
702 BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
703
704 /* An asynchronous command can not expect an SKB to be set. */
705 BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
706
707 /* An asynchronous command MUST have a callback. */
708 BUG_ON(!cmd->meta.u.callback);
709
710 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
711 return -EBUSY;
712
bb8c093b 713 ret = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c 714 if (ret < 0) {
bb8c093b 715 IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
b481de9c
ZY		 716 get_cmd_string(cmd->id), ret);
717 return ret;
718 }
719 return 0;
720}
721
bb8c093b 722static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c
ZY		 723{
724 int cmd_idx;
725 int ret;
b481de9c
ZY		 726
727 BUG_ON(cmd->meta.flags & CMD_ASYNC);
728
729 /* A synchronous command can not have a callback set. */
730 BUG_ON(cmd->meta.u.callback != NULL);
731
e5472978 732 if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) {
b481de9c
ZY		 733 IWL_ERROR("Error sending %s: Already sending a host command\n",
734 get_cmd_string(cmd->id));
e5472978
TW		 735 ret = -EBUSY;
736 goto out;
b481de9c
ZY		 737 }
738
739 set_bit(STATUS_HCMD_ACTIVE, &priv->status);
740
741 if (cmd->meta.flags & CMD_WANT_SKB)
742 cmd->meta.source = &cmd->meta;
743
bb8c093b 744 cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c
ZY		 745 if (cmd_idx < 0) {
746 ret = cmd_idx;
bb8c093b 747 IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
b481de9c
ZY		 748 get_cmd_string(cmd->id), ret);
749 goto out;
750 }
751
752 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
753 !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
754 HOST_COMPLETE_TIMEOUT);
755 if (!ret) {
756 if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
757 IWL_ERROR("Error sending %s: time out after %dms.\n",
758 get_cmd_string(cmd->id),
759 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
760
761 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
762 ret = -ETIMEDOUT;
763 goto cancel;
764 }
765 }
766
767 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
768 IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
769 get_cmd_string(cmd->id));
770 ret = -ECANCELED;
771 goto fail;
772 }
773 if (test_bit(STATUS_FW_ERROR, &priv->status)) {
774 IWL_DEBUG_INFO("Command %s failed: FW Error\n",
775 get_cmd_string(cmd->id));
776 ret = -EIO;
777 goto fail;
778 }
779 if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
780 IWL_ERROR("Error: Response NULL in '%s'\n",
781 get_cmd_string(cmd->id));
782 ret = -EIO;
783 goto out;
784 }
785
786 ret = 0;
787 goto out;
788
789cancel:
790 if (cmd->meta.flags & CMD_WANT_SKB) {
bb8c093b 791 struct iwl3945_cmd *qcmd;
b481de9c
ZY		 792
793 /* Cancel the CMD_WANT_SKB flag for the cmd in the
794 * TX cmd queue. Otherwise in case the cmd comes
795 * in later, it will possibly set an invalid
796 * address (cmd->meta.source). */
797 qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
798 qcmd->meta.flags &= ~CMD_WANT_SKB;
799 }
800fail:
801 if (cmd->meta.u.skb) {
802 dev_kfree_skb_any(cmd->meta.u.skb);
803 cmd->meta.u.skb = NULL;
804 }
805out:
e5472978 806 clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status);
b481de9c
ZY		 807 return ret;
808}
809
bb8c093b 810int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c 811{
b481de9c 812 if (cmd->meta.flags & CMD_ASYNC)
bb8c093b 813 return iwl3945_send_cmd_async(priv, cmd);
b481de9c 814
bb8c093b 815 return iwl3945_send_cmd_sync(priv, cmd);
b481de9c
ZY		 816}
817
bb8c093b 818int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
b481de9c 819{
bb8c093b 820 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 821 .id = id,
822 .len = len,
823 .data = data,
824 };
825
bb8c093b 826 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 827}
828
bb8c093b 829static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
b481de9c 830{
bb8c093b 831 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 832 .id = id,
833 .len = sizeof(val),
834 .data = &val,
835 };
836
bb8c093b 837 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 838}
839
bb8c093b 840int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
b481de9c 841{
bb8c093b 842 return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
b481de9c
ZY		 843}
844
b481de9c 845/**
bb8c093b 846 * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
8318d78a
JB		 847 * @band: 2.4 or 5 GHz band
848 * @channel: Any channel valid for the requested band
b481de9c 849
8318d78a 850 * In addition to setting the staging RXON, priv->band is also set.
b481de9c
ZY		 851 *
852 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
8318d78a 853 * in the staging RXON flag structure based on the band
b481de9c 854 */
8318d78a
JB		 855static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv,
856 enum ieee80211_band band,
857 u16 channel)
b481de9c 858{
8318d78a 859 if (!iwl3945_get_channel_info(priv, band, channel)) {
b481de9c 860 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
8318d78a 861 channel, band);
b481de9c
ZY		 862 return -EINVAL;
863 }
864
865 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
8318d78a 866 (priv->band == band))
b481de9c
ZY		 867 return 0;
868
869 priv->staging_rxon.channel = cpu_to_le16(channel);
8318d78a 870 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 871 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
872 else
873 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
874
8318d78a 875 priv->band = band;
b481de9c 876
8318d78a 877 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
b481de9c
ZY		 878
879 return 0;
880}
881
882/**
bb8c093b 883 * iwl3945_check_rxon_cmd - validate RXON structure is valid
b481de9c
ZY		 884 *
885 * NOTE: This is really only useful during development and can eventually
886 * be #ifdef'd out once the driver is stable and folks aren't actively
887 * making changes
888 */
bb8c093b 889static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon)
b481de9c
ZY		 890{
891 int error = 0;
892 int counter = 1;
893
894 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
895 error |= le32_to_cpu(rxon->flags &
896 (RXON_FLG_TGJ_NARROW_BAND_MSK |
897 RXON_FLG_RADAR_DETECT_MSK));
898 if (error)
899 IWL_WARNING("check 24G fields %d | %d\n",
900 counter++, error);
901 } else {
902 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
903 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
904 if (error)
905 IWL_WARNING("check 52 fields %d | %d\n",
906 counter++, error);
907 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
908 if (error)
909 IWL_WARNING("check 52 CCK %d | %d\n",
910 counter++, error);
911 }
912 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
913 if (error)
914 IWL_WARNING("check mac addr %d | %d\n", counter++, error);
915
916 /* make sure basic rates 6Mbps and 1Mbps are supported */
917 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
918 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
919 if (error)
920 IWL_WARNING("check basic rate %d | %d\n", counter++, error);
921
922 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
923 if (error)
924 IWL_WARNING("check assoc id %d | %d\n", counter++, error);
925
926 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
927 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
928 if (error)
929 IWL_WARNING("check CCK and short slot %d | %d\n",
930 counter++, error);
931
932 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
933 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
934 if (error)
935 IWL_WARNING("check CCK & auto detect %d | %d\n",
936 counter++, error);
937
938 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
939 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
940 if (error)
941 IWL_WARNING("check TGG and auto detect %d | %d\n",
942 counter++, error);
943
944 if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
945 error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
946 RXON_FLG_ANT_A_MSK)) == 0);
947 if (error)
948 IWL_WARNING("check antenna %d %d\n", counter++, error);
949
950 if (error)
951 IWL_WARNING("Tuning to channel %d\n",
952 le16_to_cpu(rxon->channel));
953
954 if (error) {
bb8c093b 955 IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
b481de9c
ZY		 956 return -1;
957 }
958 return 0;
959}
960
961/**
9fbab516 962 * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
01ebd063 963 * @priv: staging_rxon is compared to active_rxon
b481de9c 964 *
9fbab516
BC		 965 * If the RXON structure is changing enough to require a new tune,
966 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
967 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
b481de9c 968 */
bb8c093b 969static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
b481de9c
ZY		 970{
971
972 /* These items are only settable from the full RXON command */
973 if (!(priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ||
974 compare_ether_addr(priv->staging_rxon.bssid_addr,
975 priv->active_rxon.bssid_addr) ||
976 compare_ether_addr(priv->staging_rxon.node_addr,
977 priv->active_rxon.node_addr) ||
978 compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
979 priv->active_rxon.wlap_bssid_addr) ||
980 (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
981 (priv->staging_rxon.channel != priv->active_rxon.channel) ||
982 (priv->staging_rxon.air_propagation !=
983 priv->active_rxon.air_propagation) ||
984 (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
985 return 1;
986
987 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
988 * be updated with the RXON_ASSOC command -- however only some
989 * flag transitions are allowed using RXON_ASSOC */
990
991 /* Check if we are not switching bands */
992 if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
993 (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
994 return 1;
995
996 /* Check if we are switching association toggle */
997 if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
998 (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
999 return 1;
1000
1001 return 0;
1002}
1003
bb8c093b 1004static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
b481de9c
ZY		 1005{
1006 int rc = 0;
bb8c093b
CH		 1007 struct iwl3945_rx_packet *res = NULL;
1008 struct iwl3945_rxon_assoc_cmd rxon_assoc;
1009 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 1010 .id = REPLY_RXON_ASSOC,
1011 .len = sizeof(rxon_assoc),
1012 .meta.flags = CMD_WANT_SKB,
1013 .data = &rxon_assoc,
1014 };
bb8c093b
CH		 1015 const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
1016 const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
b481de9c
ZY		 1017
1018 if ((rxon1->flags == rxon2->flags) &&
1019 (rxon1->filter_flags == rxon2->filter_flags) &&
1020 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1021 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1022 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
1023 return 0;
1024 }
1025
1026 rxon_assoc.flags = priv->staging_rxon.flags;
1027 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1028 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1029 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1030 rxon_assoc.reserved = 0;
1031
bb8c093b 1032 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 1033 if (rc)
1034 return rc;
1035
bb8c093b 1036 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1037 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1038 IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
1039 rc = -EIO;
1040 }
1041
1042 priv->alloc_rxb_skb--;
1043 dev_kfree_skb_any(cmd.meta.u.skb);
1044
1045 return rc;
1046}
1047
1048/**
bb8c093b 1049 * iwl3945_commit_rxon - commit staging_rxon to hardware
b481de9c 1050 *
01ebd063 1051 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
ZY		 1052 * the active_rxon structure is updated with the new data. This
1053 * function correctly transitions out of the RXON_ASSOC_MSK state if
1054 * a HW tune is required based on the RXON structure changes.
1055 */
bb8c093b 1056static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
b481de9c
ZY		 1057{
1058 /* cast away the const for active_rxon in this function */
bb8c093b 1059 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
b481de9c 1060 int rc = 0;
0795af57 1061 DECLARE_MAC_BUF(mac);
b481de9c 1062
bb8c093b 1063 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 1064 return -1;
1065
1066 /* always get timestamp with Rx frame */
1067 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
1068
1069 /* select antenna */
1070 priv->staging_rxon.flags &=
1071 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1072 priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
1073
bb8c093b 1074 rc = iwl3945_check_rxon_cmd(&priv->staging_rxon);
b481de9c
ZY		 1075 if (rc) {
1076 IWL_ERROR("Invalid RXON configuration. Not committing.\n");
1077 return -EINVAL;
1078 }
1079
1080 /* If we don't need to send a full RXON, we can use
bb8c093b 1081 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 1082 * and other flags for the current radio configuration. */
bb8c093b
CH		 1083 if (!iwl3945_full_rxon_required(priv)) {
1084 rc = iwl3945_send_rxon_assoc(priv);
b481de9c
ZY		 1085 if (rc) {
1086 IWL_ERROR("Error setting RXON_ASSOC "
1087 "configuration (%d).\n", rc);
1088 return rc;
1089 }
1090
1091 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1092
1093 return 0;
1094 }
1095
1096 /* If we are currently associated and the new config requires
1097 * an RXON_ASSOC and the new config wants the associated mask enabled,
1098 * we must clear the associated from the active configuration
1099 * before we apply the new config */
bb8c093b 1100 if (iwl3945_is_associated(priv) &&
b481de9c
ZY		 1101 (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
1102 IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
1103 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1104
bb8c093b
CH		 1105 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
1106 sizeof(struct iwl3945_rxon_cmd),
b481de9c
ZY		 1107 &priv->active_rxon);
1108
1109 /* If the mask clearing failed then we set
1110 * active_rxon back to what it was previously */
1111 if (rc) {
1112 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1113 IWL_ERROR("Error clearing ASSOC_MSK on current "
1114 "configuration (%d).\n", rc);
1115 return rc;
1116 }
b481de9c
ZY		 1117 }
1118
1119 IWL_DEBUG_INFO("Sending RXON\n"
1120 "* with%s RXON_FILTER_ASSOC_MSK\n"
1121 "* channel = %d\n"
0795af57 1122 "* bssid = %s\n",
b481de9c
ZY		 1123 ((priv->staging_rxon.filter_flags &
1124 RXON_FILTER_ASSOC_MSK) ? "" : "out"),
1125 le16_to_cpu(priv->staging_rxon.channel),
0795af57 1126 print_mac(mac, priv->staging_rxon.bssid_addr));
b481de9c
ZY		 1127
1128 /* Apply the new configuration */
bb8c093b
CH		 1129 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
1130 sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
b481de9c
ZY		 1131 if (rc) {
1132 IWL_ERROR("Error setting new configuration (%d).\n", rc);
1133 return rc;
1134 }
1135
1136 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1137
bb8c093b 1138 iwl3945_clear_stations_table(priv);
556f8db7 1139
b481de9c
ZY		 1140 /* If we issue a new RXON command which required a tune then we must
1141 * send a new TXPOWER command or we won't be able to Tx any frames */
bb8c093b 1142 rc = iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 1143 if (rc) {
1144 IWL_ERROR("Error setting Tx power (%d).\n", rc);
1145 return rc;
1146 }
1147
1148 /* Add the broadcast address so we can send broadcast frames */
bb8c093b 1149 if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
b481de9c
ZY		 1150 IWL_INVALID_STATION) {
1151 IWL_ERROR("Error adding BROADCAST address for transmit.\n");
1152 return -EIO;
1153 }
1154
1155 /* If we have set the ASSOC_MSK and we are in BSS mode then
1156 * add the IWL_AP_ID to the station rate table */
bb8c093b 1157 if (iwl3945_is_associated(priv) &&
b481de9c 1158 (priv->iw_mode == IEEE80211_IF_TYPE_STA))
bb8c093b 1159 if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
b481de9c
ZY		 1160 == IWL_INVALID_STATION) {
1161 IWL_ERROR("Error adding AP address for transmit.\n");
1162 return -EIO;
1163 }
1164
8318d78a 1165 /* Init the hardware's rate fallback order based on the band */
b481de9c
ZY		 1166 rc = iwl3945_init_hw_rate_table(priv);
1167 if (rc) {
1168 IWL_ERROR("Error setting HW rate table: %02X\n", rc);
1169 return -EIO;
1170 }
1171
1172 return 0;
1173}
1174
bb8c093b 1175static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
b481de9c 1176{
bb8c093b 1177 struct iwl3945_bt_cmd bt_cmd = {
b481de9c
ZY		 1178 .flags = 3,
1179 .lead_time = 0xAA,
1180 .max_kill = 1,
1181 .kill_ack_mask = 0,
1182 .kill_cts_mask = 0,
1183 };
1184
bb8c093b
CH		 1185 return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1186 sizeof(struct iwl3945_bt_cmd), &bt_cmd);
b481de9c
ZY		 1187}
1188
bb8c093b 1189static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
b481de9c
ZY		 1190{
1191 int rc = 0;
bb8c093b
CH		 1192 struct iwl3945_rx_packet *res;
1193 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 1194 .id = REPLY_SCAN_ABORT_CMD,
1195 .meta.flags = CMD_WANT_SKB,
1196 };
1197
1198 /* If there isn't a scan actively going on in the hardware
1199 * then we are in between scan bands and not actually
1200 * actively scanning, so don't send the abort command */
1201 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
1202 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1203 return 0;
1204 }
1205
bb8c093b 1206 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 1207 if (rc) {
1208 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1209 return rc;
1210 }
1211
bb8c093b 1212 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1213 if (res->u.status != CAN_ABORT_STATUS) {
1214 /* The scan abort will return 1 for success or
1215 * 2 for "failure". A failure condition can be
1216 * due to simply not being in an active scan which
1217 * can occur if we send the scan abort before we
1218 * the microcode has notified us that a scan is
1219 * completed. */
1220 IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
1221 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1222 clear_bit(STATUS_SCAN_HW, &priv->status);
1223 }
1224
1225 dev_kfree_skb_any(cmd.meta.u.skb);
1226
1227 return rc;
1228}
1229
bb8c093b
CH		 1230static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
1231 struct iwl3945_cmd *cmd,
b481de9c
ZY		 1232 struct sk_buff *skb)
1233{
1234 return 1;
1235}
1236
1237/*
1238 * CARD_STATE_CMD
1239 *
9fbab516 1240 * Use: Sets the device's internal card state to enable, disable, or halt
b481de9c
ZY		 1241 *
1242 * When in the 'enable' state the card operates as normal.
1243 * When in the 'disable' state, the card enters into a low power mode.
1244 * When in the 'halt' state, the card is shut down and must be fully
1245 * restarted to come back on.
1246 */
bb8c093b 1247static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
b481de9c 1248{
bb8c093b 1249 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 1250 .id = REPLY_CARD_STATE_CMD,
1251 .len = sizeof(u32),
1252 .data = &flags,
1253 .meta.flags = meta_flag,
1254 };
1255
1256 if (meta_flag & CMD_ASYNC)
bb8c093b 1257 cmd.meta.u.callback = iwl3945_card_state_sync_callback;
b481de9c 1258
bb8c093b 1259 return iwl3945_send_cmd(priv, &cmd);
b481de9c
ZY		 1260}
1261
bb8c093b
CH		 1262static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
1263 struct iwl3945_cmd *cmd, struct sk_buff *skb)
b481de9c 1264{
bb8c093b 1265 struct iwl3945_rx_packet *res = NULL;
b481de9c
ZY		 1266
1267 if (!skb) {
1268 IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
1269 return 1;
1270 }
1271
bb8c093b 1272 res = (struct iwl3945_rx_packet *)skb->data;
b481de9c
ZY		 1273 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1274 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1275 res->hdr.flags);
1276 return 1;
1277 }
1278
1279 switch (res->u.add_sta.status) {
1280 case ADD_STA_SUCCESS_MSK:
1281 break;
1282 default:
1283 break;
1284 }
1285
1286 /* We didn't cache the SKB; let the caller free it */
1287 return 1;
1288}
1289
bb8c093b
CH		 1290int iwl3945_send_add_station(struct iwl3945_priv *priv,
1291 struct iwl3945_addsta_cmd *sta, u8 flags)
b481de9c 1292{
bb8c093b 1293 struct iwl3945_rx_packet *res = NULL;
b481de9c 1294 int rc = 0;
bb8c093b 1295 struct iwl3945_host_cmd cmd = {
b481de9c 1296 .id = REPLY_ADD_STA,
bb8c093b 1297 .len = sizeof(struct iwl3945_addsta_cmd),
b481de9c
ZY		 1298 .meta.flags = flags,
1299 .data = sta,
1300 };
1301
1302 if (flags & CMD_ASYNC)
bb8c093b 1303 cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
b481de9c
ZY		 1304 else
1305 cmd.meta.flags |= CMD_WANT_SKB;
1306
bb8c093b 1307 rc = iwl3945_send_cmd(priv, &cmd);
b481de9c
ZY		 1308
1309 if (rc || (flags & CMD_ASYNC))
1310 return rc;
1311
bb8c093b 1312 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1313 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1314 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1315 res->hdr.flags);
1316 rc = -EIO;
1317 }
1318
1319 if (rc == 0) {
1320 switch (res->u.add_sta.status) {
1321 case ADD_STA_SUCCESS_MSK:
1322 IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
1323 break;
1324 default:
1325 rc = -EIO;
1326 IWL_WARNING("REPLY_ADD_STA failed\n");
1327 break;
1328 }
1329 }
1330
1331 priv->alloc_rxb_skb--;
1332 dev_kfree_skb_any(cmd.meta.u.skb);
1333
1334 return rc;
1335}
1336
bb8c093b 1337static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
b481de9c
ZY		 1338 struct ieee80211_key_conf *keyconf,
1339 u8 sta_id)
1340{
1341 unsigned long flags;
1342 __le16 key_flags = 0;
1343
1344 switch (keyconf->alg) {
1345 case ALG_CCMP:
1346 key_flags |= STA_KEY_FLG_CCMP;
1347 key_flags |= cpu_to_le16(
1348 keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
1349 key_flags &= ~STA_KEY_FLG_INVALID;
1350 break;
1351 case ALG_TKIP:
1352 case ALG_WEP:
b481de9c
ZY		 1353 default:
1354 return -EINVAL;
1355 }
1356 spin_lock_irqsave(&priv->sta_lock, flags);
1357 priv->stations[sta_id].keyinfo.alg = keyconf->alg;
1358 priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
1359 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
1360 keyconf->keylen);
1361
1362 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
1363 keyconf->keylen);
1364 priv->stations[sta_id].sta.key.key_flags = key_flags;
1365 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1366 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1367
1368 spin_unlock_irqrestore(&priv->sta_lock, flags);
1369
1370 IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
bb8c093b 1371 iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY		 1372 return 0;
1373}
1374
bb8c093b 1375static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
b481de9c
ZY		 1376{
1377 unsigned long flags;
1378
1379 spin_lock_irqsave(&priv->sta_lock, flags);
bb8c093b
CH		 1380 memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
1381 memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl3945_keyinfo));
b481de9c
ZY		 1382 priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
1383 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1384 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1385 spin_unlock_irqrestore(&priv->sta_lock, flags);
1386
1387 IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
bb8c093b 1388 iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY		 1389 return 0;
1390}
1391
bb8c093b 1392static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
b481de9c
ZY		 1393{
1394 struct list_head *element;
1395
1396 IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
1397 priv->frames_count);
1398
1399 while (!list_empty(&priv->free_frames)) {
1400 element = priv->free_frames.next;
1401 list_del(element);
bb8c093b 1402 kfree(list_entry(element, struct iwl3945_frame, list));
b481de9c
ZY		 1403 priv->frames_count--;
1404 }
1405
1406 if (priv->frames_count) {
1407 IWL_WARNING("%d frames still in use. Did we lose one?\n",
1408 priv->frames_count);
1409 priv->frames_count = 0;
1410 }
1411}
1412
bb8c093b 1413static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
b481de9c 1414{
bb8c093b 1415 struct iwl3945_frame *frame;
b481de9c
ZY		 1416 struct list_head *element;
1417 if (list_empty(&priv->free_frames)) {
1418 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
1419 if (!frame) {
1420 IWL_ERROR("Could not allocate frame!\n");
1421 return NULL;
1422 }
1423
1424 priv->frames_count++;
1425 return frame;
1426 }
1427
1428 element = priv->free_frames.next;
1429 list_del(element);
bb8c093b 1430 return list_entry(element, struct iwl3945_frame, list);
b481de9c
ZY		 1431}
1432
bb8c093b 1433static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
b481de9c
ZY		 1434{
1435 memset(frame, 0, sizeof(*frame));
1436 list_add(&frame->list, &priv->free_frames);
1437}
1438
bb8c093b 1439unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
b481de9c
ZY		 1440 struct ieee80211_hdr *hdr,
1441 const u8 *dest, int left)
1442{
1443
bb8c093b 1444 if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
b481de9c
ZY		 1445 ((priv->iw_mode != IEEE80211_IF_TYPE_IBSS) &&
1446 (priv->iw_mode != IEEE80211_IF_TYPE_AP)))
1447 return 0;
1448
1449 if (priv->ibss_beacon->len > left)
1450 return 0;
1451
1452 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
1453
1454 return priv->ibss_beacon->len;
1455}
1456
bb8c093b 1457static u8 iwl3945_rate_get_lowest_plcp(int rate_mask)
b481de9c
ZY		 1458{
1459 u8 i;
1460
1461 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
bb8c093b 1462 i = iwl3945_rates[i].next_ieee) {
b481de9c 1463 if (rate_mask & (1 << i))
bb8c093b 1464 return iwl3945_rates[i].plcp;
b481de9c
ZY		 1465 }
1466
1467 return IWL_RATE_INVALID;
1468}
1469
bb8c093b 1470static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
b481de9c 1471{
bb8c093b 1472 struct iwl3945_frame *frame;
b481de9c
ZY		 1473 unsigned int frame_size;
1474 int rc;
1475 u8 rate;
1476
bb8c093b 1477 frame = iwl3945_get_free_frame(priv);
b481de9c
ZY		 1478
1479 if (!frame) {
1480 IWL_ERROR("Could not obtain free frame buffer for beacon "
1481 "command.\n");
1482 return -ENOMEM;
1483 }
1484
1485 if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) {
bb8c093b 1486 rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic &
b481de9c
ZY		 1487 0xFF0);
1488 if (rate == IWL_INVALID_RATE)
1489 rate = IWL_RATE_6M_PLCP;
1490 } else {
bb8c093b 1491 rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic & 0xF);
b481de9c
ZY		 1492 if (rate == IWL_INVALID_RATE)
1493 rate = IWL_RATE_1M_PLCP;
1494 }
1495
bb8c093b 1496 frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 1497
bb8c093b 1498 rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY		 1499 &frame->u.cmd[0]);
1500
bb8c093b 1501 iwl3945_free_frame(priv, frame);
b481de9c
ZY		 1502
1503 return rc;
1504}
1505
1506/******************************************************************************
1507 *
1508 * EEPROM related functions
1509 *
1510 ******************************************************************************/
1511
bb8c093b 1512static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
b481de9c
ZY		 1513{
1514 memcpy(mac, priv->eeprom.mac_address, 6);
1515}
1516
74a3a250
RC		 1517/*
1518 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
1519 * embedded controller) as EEPROM reader; each read is a series of pulses
1520 * to/from the EEPROM chip, not a single event, so even reads could conflict
1521 * if they weren't arbitrated by some ownership mechanism. Here, the driver
1522 * simply claims ownership, which should be safe when this function is called
1523 * (i.e. before loading uCode!).
1524 */
1525static inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv)
1526{
1527 _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
1528 return 0;
1529}
1530
b481de9c 1531/**
bb8c093b 1532 * iwl3945_eeprom_init - read EEPROM contents
b481de9c 1533 *
6440adb5 1534 * Load the EEPROM contents from adapter into priv->eeprom
b481de9c
ZY		 1535 *
1536 * NOTE: This routine uses the non-debug IO access functions.
1537 */
bb8c093b 1538int iwl3945_eeprom_init(struct iwl3945_priv *priv)
b481de9c 1539{
58ff6d4d 1540 u16 *e = (u16 *)&priv->eeprom;
bb8c093b 1541 u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
b481de9c
ZY		 1542 u32 r;
1543 int sz = sizeof(priv->eeprom);
1544 int rc;
1545 int i;
1546 u16 addr;
1547
1548 /* The EEPROM structure has several padding buffers within it
1549 * and when adding new EEPROM maps is subject to programmer errors
1550 * which may be very difficult to identify without explicitly
1551 * checking the resulting size of the eeprom map. */
1552 BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
1553
1554 if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
1555 IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp);
1556 return -ENOENT;
1557 }
1558
6440adb5 1559 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
bb8c093b 1560 rc = iwl3945_eeprom_acquire_semaphore(priv);
b481de9c 1561 if (rc < 0) {
91e17473 1562 IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
b481de9c
ZY		 1563 return -ENOENT;
1564 }
1565
1566 /* eeprom is an array of 16bit values */
1567 for (addr = 0; addr < sz; addr += sizeof(u16)) {
bb8c093b
CH		 1568 _iwl3945_write32(priv, CSR_EEPROM_REG, addr << 1);
1569 _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
b481de9c
ZY		 1570
1571 for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
1572 i += IWL_EEPROM_ACCESS_DELAY) {
bb8c093b 1573 r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
b481de9c
ZY		 1574 if (r & CSR_EEPROM_REG_READ_VALID_MSK)
1575 break;
1576 udelay(IWL_EEPROM_ACCESS_DELAY);
1577 }
1578
1579 if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) {
1580 IWL_ERROR("Time out reading EEPROM[%d]", addr);
1581 return -ETIMEDOUT;
1582 }
58ff6d4d 1583 e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
b481de9c
ZY		 1584 }
1585
1586 return 0;
1587}
1588
bb8c093b 1589static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
b481de9c
ZY		 1590{
1591 if (priv->hw_setting.shared_virt)
1592 pci_free_consistent(priv->pci_dev,
bb8c093b 1593 sizeof(struct iwl3945_shared),
b481de9c
ZY		 1594 priv->hw_setting.shared_virt,
1595 priv->hw_setting.shared_phys);
1596}
1597
1598/**
bb8c093b 1599 * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
b481de9c
ZY		 1600 *
1601 * return : set the bit for each supported rate insert in ie
1602 */
bb8c093b 1603static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
c7c46676 1604 u16 basic_rate, int *left)
b481de9c
ZY		 1605{
1606 u16 ret_rates = 0, bit;
1607 int i;
c7c46676
TW		 1608 u8 *cnt = ie;
1609 u8 *rates = ie + 1;
b481de9c
ZY		 1610
1611 for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
1612 if (bit & supported_rate) {
1613 ret_rates |= bit;
bb8c093b 1614 rates[*cnt] = iwl3945_rates[i].ieee |
c7c46676
TW		 1615 ((bit & basic_rate) ? 0x80 : 0x00);
1616 (*cnt)++;
1617 (*left)--;
1618 if ((*left <= 0) ||
1619 (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
b481de9c
ZY		 1620 break;
1621 }
1622 }
1623
1624 return ret_rates;
1625}
1626
1627/**
bb8c093b 1628 * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
b481de9c 1629 */
bb8c093b 1630static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
b481de9c
ZY		 1631 struct ieee80211_mgmt *frame,
1632 int left, int is_direct)
1633{
1634 int len = 0;
1635 u8 *pos = NULL;
c7c46676 1636 u16 active_rates, ret_rates, cck_rates;
b481de9c
ZY		 1637
1638 /* Make sure there is enough space for the probe request,
1639 * two mandatory IEs and the data */
1640 left -= 24;
1641 if (left < 0)
1642 return 0;
1643 len += 24;
1644
1645 frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
bb8c093b 1646 memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
b481de9c 1647 memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
bb8c093b 1648 memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
b481de9c
ZY		 1649 frame->seq_ctrl = 0;
1650
1651 /* fill in our indirect SSID IE */
1652 /* ...next IE... */
1653
1654 left -= 2;
1655 if (left < 0)
1656 return 0;
1657 len += 2;
1658 pos = &(frame->u.probe_req.variable[0]);
1659 *pos++ = WLAN_EID_SSID;
1660 *pos++ = 0;
1661
1662 /* fill in our direct SSID IE... */
1663 if (is_direct) {
1664 /* ...next IE... */
1665 left -= 2 + priv->essid_len;
1666 if (left < 0)
1667 return 0;
1668 /* ... fill it in... */
1669 *pos++ = WLAN_EID_SSID;
1670 *pos++ = priv->essid_len;
1671 memcpy(pos, priv->essid, priv->essid_len);
1672 pos += priv->essid_len;
1673 len += 2 + priv->essid_len;
1674 }
1675
1676 /* fill in supported rate */
1677 /* ...next IE... */
1678 left -= 2;
1679 if (left < 0)
1680 return 0;
c7c46676 1681
b481de9c
ZY		 1682 /* ... fill it in... */
1683 *pos++ = WLAN_EID_SUPP_RATES;
1684 *pos = 0;
c7c46676
TW		 1685
1686 priv->active_rate = priv->rates_mask;
1687 active_rates = priv->active_rate;
b481de9c
ZY		 1688 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1689
c7c46676 1690 cck_rates = IWL_CCK_RATES_MASK & active_rates;
bb8c093b 1691 ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
c7c46676
TW		 1692 priv->active_rate_basic, &left);
1693 active_rates &= ~ret_rates;
1694
bb8c093b 1695 ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676
TW		 1696 priv->active_rate_basic, &left);
1697 active_rates &= ~ret_rates;
1698
b481de9c
ZY		 1699 len += 2 + *pos;
1700 pos += (*pos) + 1;
c7c46676 1701 if (active_rates == 0)
b481de9c
ZY		 1702 goto fill_end;
1703
1704 /* fill in supported extended rate */
1705 /* ...next IE... */
1706 left -= 2;
1707 if (left < 0)
1708 return 0;
1709 /* ... fill it in... */
1710 *pos++ = WLAN_EID_EXT_SUPP_RATES;
1711 *pos = 0;
bb8c093b 1712 iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676 1713 priv->active_rate_basic, &left);
b481de9c
ZY		 1714 if (*pos > 0)
1715 len += 2 + *pos;
1716
1717 fill_end:
1718 return (u16)len;
1719}
1720
1721/*
1722 * QoS support
1723*/
bb8c093b
CH		 1724static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
1725 struct iwl3945_qosparam_cmd *qos)
b481de9c
ZY		 1726{
1727
bb8c093b
CH		 1728 return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
1729 sizeof(struct iwl3945_qosparam_cmd), qos);
b481de9c
ZY		 1730}
1731
bb8c093b 1732static void iwl3945_reset_qos(struct iwl3945_priv *priv)
b481de9c
ZY		 1733{
1734 u16 cw_min = 15;
1735 u16 cw_max = 1023;
1736 u8 aifs = 2;
1737 u8 is_legacy = 0;
1738 unsigned long flags;
1739 int i;
1740
1741 spin_lock_irqsave(&priv->lock, flags);
1742 priv->qos_data.qos_active = 0;
1743
1744 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
1745 if (priv->qos_data.qos_enable)
1746 priv->qos_data.qos_active = 1;
1747 if (!(priv->active_rate & 0xfff0)) {
1748 cw_min = 31;
1749 is_legacy = 1;
1750 }
1751 } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
1752 if (priv->qos_data.qos_enable)
1753 priv->qos_data.qos_active = 1;
1754 } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
1755 cw_min = 31;
1756 is_legacy = 1;
1757 }
1758
1759 if (priv->qos_data.qos_active)
1760 aifs = 3;
1761
1762 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
1763 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
1764 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
1765 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
1766 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
1767
1768 if (priv->qos_data.qos_active) {
1769 i = 1;
1770 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
1771 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
1772 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
1773 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
1774 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1775
1776 i = 2;
1777 priv->qos_data.def_qos_parm.ac[i].cw_min =
1778 cpu_to_le16((cw_min + 1) / 2 - 1);
1779 priv->qos_data.def_qos_parm.ac[i].cw_max =
1780 cpu_to_le16(cw_max);
1781 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1782 if (is_legacy)
1783 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1784 cpu_to_le16(6016);
1785 else
1786 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1787 cpu_to_le16(3008);
1788 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1789
1790 i = 3;
1791 priv->qos_data.def_qos_parm.ac[i].cw_min =
1792 cpu_to_le16((cw_min + 1) / 4 - 1);
1793 priv->qos_data.def_qos_parm.ac[i].cw_max =
1794 cpu_to_le16((cw_max + 1) / 2 - 1);
1795 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1796 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1797 if (is_legacy)
1798 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1799 cpu_to_le16(3264);
1800 else
1801 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1802 cpu_to_le16(1504);
1803 } else {
1804 for (i = 1; i < 4; i++) {
1805 priv->qos_data.def_qos_parm.ac[i].cw_min =
1806 cpu_to_le16(cw_min);
1807 priv->qos_data.def_qos_parm.ac[i].cw_max =
1808 cpu_to_le16(cw_max);
1809 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
1810 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
1811 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1812 }
1813 }
1814 IWL_DEBUG_QOS("set QoS to default \n");
1815
1816 spin_unlock_irqrestore(&priv->lock, flags);
1817}
1818
bb8c093b 1819static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
b481de9c
ZY		 1820{
1821 unsigned long flags;
1822
b481de9c
ZY		 1823 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1824 return;
1825
1826 if (!priv->qos_data.qos_enable)
1827 return;
1828
1829 spin_lock_irqsave(&priv->lock, flags);
1830 priv->qos_data.def_qos_parm.qos_flags = 0;
1831
1832 if (priv->qos_data.qos_cap.q_AP.queue_request &&
1833 !priv->qos_data.qos_cap.q_AP.txop_request)
1834 priv->qos_data.def_qos_parm.qos_flags |=
1835 QOS_PARAM_FLG_TXOP_TYPE_MSK;
1836
1837 if (priv->qos_data.qos_active)
1838 priv->qos_data.def_qos_parm.qos_flags |=
1839 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
1840
1841 spin_unlock_irqrestore(&priv->lock, flags);
1842
bb8c093b 1843 if (force || iwl3945_is_associated(priv)) {
b481de9c
ZY		 1844 IWL_DEBUG_QOS("send QoS cmd with Qos active %d \n",
1845 priv->qos_data.qos_active);
1846
bb8c093b 1847 iwl3945_send_qos_params_command(priv,
b481de9c
ZY		 1848 &(priv->qos_data.def_qos_parm));
1849 }
1850}
1851
b481de9c
ZY		 1852/*
1853 * Power management (not Tx power!) functions
1854 */
1855#define MSEC_TO_USEC 1024
1856
1857#define NOSLP __constant_cpu_to_le32(0)
1858#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK
1859#define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
1860#define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
1861 __constant_cpu_to_le32(X1), \
1862 __constant_cpu_to_le32(X2), \
1863 __constant_cpu_to_le32(X3), \
1864 __constant_cpu_to_le32(X4)}
1865
1866
1867/* default power management (not Tx power) table values */
1868/* for tim 0-10 */
bb8c093b 1869static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = {
b481de9c
ZY		 1870 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1871 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
1872 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
1873 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
1874 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
1875 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
1876};
1877
1878/* for tim > 10 */
bb8c093b 1879static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = {
b481de9c
ZY		 1880 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1881 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
1882 SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
1883 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
1884 SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
1885 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
1886 SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
1887 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
1888 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
1889 SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
1890};
1891
bb8c093b 1892int iwl3945_power_init_handle(struct iwl3945_priv *priv)
b481de9c
ZY		 1893{
1894 int rc = 0, i;
bb8c093b
CH		 1895 struct iwl3945_power_mgr *pow_data;
1896 int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC;
b481de9c
ZY		 1897 u16 pci_pm;
1898
1899 IWL_DEBUG_POWER("Initialize power \n");
1900
1901 pow_data = &(priv->power_data);
1902
1903 memset(pow_data, 0, sizeof(*pow_data));
1904
1905 pow_data->active_index = IWL_POWER_RANGE_0;
1906 pow_data->dtim_val = 0xffff;
1907
1908 memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
1909 memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
1910
1911 rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
1912 if (rc != 0)
1913 return 0;
1914 else {
bb8c093b 1915 struct iwl3945_powertable_cmd *cmd;
b481de9c
ZY		 1916
1917 IWL_DEBUG_POWER("adjust power command flags\n");
1918
1919 for (i = 0; i < IWL_POWER_AC; i++) {
1920 cmd = &pow_data->pwr_range_0[i].cmd;
1921
1922 if (pci_pm & 0x1)
1923 cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
1924 else
1925 cmd->flags |= IWL_POWER_PCI_PM_MSK;
1926 }
1927 }
1928 return rc;
1929}
1930
bb8c093b
CH		 1931static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
1932 struct iwl3945_powertable_cmd *cmd, u32 mode)
b481de9c
ZY		 1933{
1934 int rc = 0, i;
1935 u8 skip;
1936 u32 max_sleep = 0;
bb8c093b 1937 struct iwl3945_power_vec_entry *range;
b481de9c 1938 u8 period = 0;
bb8c093b 1939 struct iwl3945_power_mgr *pow_data;
b481de9c
ZY		 1940
1941 if (mode > IWL_POWER_INDEX_5) {
1942 IWL_DEBUG_POWER("Error invalid power mode \n");
1943 return -1;
1944 }
1945 pow_data = &(priv->power_data);
1946
1947 if (pow_data->active_index == IWL_POWER_RANGE_0)
1948 range = &pow_data->pwr_range_0[0];
1949 else
1950 range = &pow_data->pwr_range_1[1];
1951
bb8c093b 1952 memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
b481de9c
ZY		 1953
1954#ifdef IWL_MAC80211_DISABLE
1955 if (priv->assoc_network != NULL) {
1956 unsigned long flags;
1957
1958 period = priv->assoc_network->tim.tim_period;
1959 }
1960#endif /*IWL_MAC80211_DISABLE */
1961 skip = range[mode].no_dtim;
1962
1963 if (period == 0) {
1964 period = 1;
1965 skip = 0;
1966 }
1967
1968 if (skip == 0) {
1969 max_sleep = period;
1970 cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
1971 } else {
1972 __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
1973 max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
1974 cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
1975 }
1976
1977 for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
1978 if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
1979 cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
1980 }
1981
1982 IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
1983 IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
1984 IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
1985 IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
1986 le32_to_cpu(cmd->sleep_interval[0]),
1987 le32_to_cpu(cmd->sleep_interval[1]),
1988 le32_to_cpu(cmd->sleep_interval[2]),
1989 le32_to_cpu(cmd->sleep_interval[3]),
1990 le32_to_cpu(cmd->sleep_interval[4]));
1991
1992 return rc;
1993}
1994
bb8c093b 1995static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
b481de9c 1996{
9a62f73b 1997 u32 uninitialized_var(final_mode);
b481de9c 1998 int rc;
bb8c093b 1999 struct iwl3945_powertable_cmd cmd;
b481de9c
ZY		 2000
2001 /* If on battery, set to 3,
01ebd063 2002 * if plugged into AC power, set to CAM ("continuously aware mode"),
b481de9c
ZY		 2003 * else user level */
2004 switch (mode) {
2005 case IWL_POWER_BATTERY:
2006 final_mode = IWL_POWER_INDEX_3;
2007 break;
2008 case IWL_POWER_AC:
2009 final_mode = IWL_POWER_MODE_CAM;
2010 break;
2011 default:
2012 final_mode = mode;
2013 break;
2014 }
2015
bb8c093b 2016 iwl3945_update_power_cmd(priv, &cmd, final_mode);
b481de9c 2017
bb8c093b 2018 rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
b481de9c
ZY		 2019
2020 if (final_mode == IWL_POWER_MODE_CAM)
2021 clear_bit(STATUS_POWER_PMI, &priv->status);
2022 else
2023 set_bit(STATUS_POWER_PMI, &priv->status);
2024
2025 return rc;
2026}
2027
bb8c093b 2028int iwl3945_is_network_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
b481de9c
ZY		 2029{
2030 /* Filter incoming packets to determine if they are targeted toward
2031 * this network, discarding packets coming from ourselves */
2032 switch (priv->iw_mode) {
2033 case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */
2034 /* packets from our adapter are dropped (echo) */
2035 if (!compare_ether_addr(header->addr2, priv->mac_addr))
2036 return 0;
2037 /* {broad,multi}cast packets to our IBSS go through */
2038 if (is_multicast_ether_addr(header->addr1))
2039 return !compare_ether_addr(header->addr3, priv->bssid);
2040 /* packets to our adapter go through */
2041 return !compare_ether_addr(header->addr1, priv->mac_addr);
2042 case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */
2043 /* packets from our adapter are dropped (echo) */
2044 if (!compare_ether_addr(header->addr3, priv->mac_addr))
2045 return 0;
2046 /* {broad,multi}cast packets to our BSS go through */
2047 if (is_multicast_ether_addr(header->addr1))
2048 return !compare_ether_addr(header->addr2, priv->bssid);
2049 /* packets to our adapter go through */
2050 return !compare_ether_addr(header->addr1, priv->mac_addr);
69dc5d9d
TW		 2051 default:
2052 return 1;
b481de9c
ZY		 2053 }
2054
2055 return 1;
2056}
2057
b481de9c 2058/**
bb8c093b 2059 * iwl3945_scan_cancel - Cancel any currently executing HW scan
b481de9c
ZY		 2060 *
2061 * NOTE: priv->mutex is not required before calling this function
2062 */
bb8c093b 2063static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
b481de9c
ZY		 2064{
2065 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
2066 clear_bit(STATUS_SCANNING, &priv->status);
2067 return 0;
2068 }
2069
2070 if (test_bit(STATUS_SCANNING, &priv->status)) {
2071 if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2072 IWL_DEBUG_SCAN("Queuing scan abort.\n");
2073 set_bit(STATUS_SCAN_ABORTING, &priv->status);
2074 queue_work(priv->workqueue, &priv->abort_scan);
2075
2076 } else
2077 IWL_DEBUG_SCAN("Scan abort already in progress.\n");
2078
2079 return test_bit(STATUS_SCANNING, &priv->status);
2080 }
2081
2082 return 0;
2083}
2084
2085/**
bb8c093b 2086 * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
b481de9c
ZY		 2087 * @ms: amount of time to wait (in milliseconds) for scan to abort
2088 *
2089 * NOTE: priv->mutex must be held before calling this function
2090 */
bb8c093b 2091static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
b481de9c
ZY		 2092{
2093 unsigned long now = jiffies;
2094 int ret;
2095
bb8c093b 2096 ret = iwl3945_scan_cancel(priv);
b481de9c
ZY		 2097 if (ret && ms) {
2098 mutex_unlock(&priv->mutex);
2099 while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
2100 test_bit(STATUS_SCANNING, &priv->status))
2101 msleep(1);
2102 mutex_lock(&priv->mutex);
2103
2104 return test_bit(STATUS_SCANNING, &priv->status);
2105 }
2106
2107 return ret;
2108}
2109
bb8c093b 2110static void iwl3945_sequence_reset(struct iwl3945_priv *priv)
b481de9c
ZY		 2111{
2112 /* Reset ieee stats */
2113
2114 /* We don't reset the net_device_stats (ieee->stats) on
2115 * re-association */
2116
2117 priv->last_seq_num = -1;
2118 priv->last_frag_num = -1;
2119 priv->last_packet_time = 0;
2120
bb8c093b 2121 iwl3945_scan_cancel(priv);
b481de9c
ZY		 2122}
2123
2124#define MAX_UCODE_BEACON_INTERVAL 1024
2125#define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
2126
bb8c093b 2127static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
b481de9c
ZY		 2128{
2129 u16 new_val = 0;
2130 u16 beacon_factor = 0;
2131
2132 beacon_factor =
2133 (beacon_val + MAX_UCODE_BEACON_INTERVAL)
2134 / MAX_UCODE_BEACON_INTERVAL;
2135 new_val = beacon_val / beacon_factor;
2136
2137 return cpu_to_le16(new_val);
2138}
2139
bb8c093b 2140static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
b481de9c
ZY		 2141{
2142 u64 interval_tm_unit;
2143 u64 tsf, result;
2144 unsigned long flags;
2145 struct ieee80211_conf *conf = NULL;
2146 u16 beacon_int = 0;
2147
2148 conf = ieee80211_get_hw_conf(priv->hw);
2149
2150 spin_lock_irqsave(&priv->lock, flags);
2151 priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
2152 priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
2153
2154 priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
2155
2156 tsf = priv->timestamp1;
2157 tsf = ((tsf << 32) | priv->timestamp0);
2158
2159 beacon_int = priv->beacon_int;
2160 spin_unlock_irqrestore(&priv->lock, flags);
2161
2162 if (priv->iw_mode == IEEE80211_IF_TYPE_STA) {
2163 if (beacon_int == 0) {
2164 priv->rxon_timing.beacon_interval = cpu_to_le16(100);
2165 priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
2166 } else {
2167 priv->rxon_timing.beacon_interval =
2168 cpu_to_le16(beacon_int);
2169 priv->rxon_timing.beacon_interval =
bb8c093b 2170 iwl3945_adjust_beacon_interval(
b481de9c
ZY		 2171 le16_to_cpu(priv->rxon_timing.beacon_interval));
2172 }
2173
2174 priv->rxon_timing.atim_window = 0;
2175 } else {
2176 priv->rxon_timing.beacon_interval =
bb8c093b 2177 iwl3945_adjust_beacon_interval(conf->beacon_int);
b481de9c
ZY		 2178 /* TODO: we need to get atim_window from upper stack
2179 * for now we set to 0 */
2180 priv->rxon_timing.atim_window = 0;
2181 }
2182
2183 interval_tm_unit =
2184 (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
2185 result = do_div(tsf, interval_tm_unit);
2186 priv->rxon_timing.beacon_init_val =
2187 cpu_to_le32((u32) ((u64) interval_tm_unit - result));
2188
2189 IWL_DEBUG_ASSOC
2190 ("beacon interval %d beacon timer %d beacon tim %d\n",
2191 le16_to_cpu(priv->rxon_timing.beacon_interval),
2192 le32_to_cpu(priv->rxon_timing.beacon_init_val),
2193 le16_to_cpu(priv->rxon_timing.atim_window));
2194}
2195
bb8c093b 2196static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
b481de9c
ZY		 2197{
2198 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
2199 IWL_ERROR("APs don't scan.\n");
2200 return 0;
2201 }
2202
bb8c093b 2203 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 2204 IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
2205 return -EIO;
2206 }
2207
2208 if (test_bit(STATUS_SCANNING, &priv->status)) {
2209 IWL_DEBUG_SCAN("Scan already in progress.\n");
2210 return -EAGAIN;
2211 }
2212
2213 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2214 IWL_DEBUG_SCAN("Scan request while abort pending. "
2215 "Queuing.\n");
2216 return -EAGAIN;
2217 }
2218
2219 IWL_DEBUG_INFO("Starting scan...\n");
2220 priv->scan_bands = 2;
2221 set_bit(STATUS_SCANNING, &priv->status);
2222 priv->scan_start = jiffies;
2223 priv->scan_pass_start = priv->scan_start;
2224
2225 queue_work(priv->workqueue, &priv->request_scan);
2226
2227 return 0;
2228}
2229
bb8c093b 2230static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
b481de9c 2231{
bb8c093b 2232 struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
b481de9c
ZY		 2233
2234 if (hw_decrypt)
2235 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
2236 else
2237 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
2238
2239 return 0;
2240}
2241
8318d78a
JB		 2242static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv,
2243 enum ieee80211_band band)
b481de9c 2244{
8318d78a 2245 if (band == IEEE80211_BAND_5GHZ) {
b481de9c
ZY		 2246 priv->staging_rxon.flags &=
2247 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
2248 | RXON_FLG_CCK_MSK);
2249 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2250 } else {
bb8c093b 2251 /* Copied from iwl3945_bg_post_associate() */
b481de9c
ZY		 2252 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2253 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2254 else
2255 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2256
2257 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
2258 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2259
2260 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
2261 priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
2262 priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
2263 }
2264}
2265
2266/*
01ebd063 2267 * initialize rxon structure with default values from eeprom
b481de9c 2268 */
bb8c093b 2269static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv)
b481de9c 2270{
bb8c093b 2271 const struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 2272
2273 memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
2274
2275 switch (priv->iw_mode) {
2276 case IEEE80211_IF_TYPE_AP:
2277 priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
2278 break;
2279
2280 case IEEE80211_IF_TYPE_STA:
2281 priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
2282 priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
2283 break;
2284
2285 case IEEE80211_IF_TYPE_IBSS:
2286 priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
2287 priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
2288 priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
2289 RXON_FILTER_ACCEPT_GRP_MSK;
2290 break;
2291
2292 case IEEE80211_IF_TYPE_MNTR:
2293 priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
2294 priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
2295 RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
2296 break;
69dc5d9d
TW		 2297 default:
2298 IWL_ERROR("Unsupported interface type %d\n", priv->iw_mode);
2299 break;
b481de9c
ZY		 2300 }
2301
2302#if 0
2303 /* TODO: Figure out when short_preamble would be set and cache from
2304 * that */
2305 if (!hw_to_local(priv->hw)->short_preamble)
2306 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2307 else
2308 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2309#endif
2310
8318d78a 2311 ch_info = iwl3945_get_channel_info(priv, priv->band,
b481de9c
ZY		 2312 le16_to_cpu(priv->staging_rxon.channel));
2313
2314 if (!ch_info)
2315 ch_info = &priv->channel_info[0];
2316
2317 /*
2318 * in some case A channels are all non IBSS
2319 * in this case force B/G channel
2320 */
2321 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
2322 !(is_channel_ibss(ch_info)))
2323 ch_info = &priv->channel_info[0];
2324
2325 priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
2326 if (is_channel_a_band(ch_info))
8318d78a 2327 priv->band = IEEE80211_BAND_5GHZ;
b481de9c 2328 else
8318d78a 2329 priv->band = IEEE80211_BAND_2GHZ;
b481de9c 2330
8318d78a 2331 iwl3945_set_flags_for_phymode(priv, priv->band);
b481de9c
ZY		 2332
2333 priv->staging_rxon.ofdm_basic_rates =
2334 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2335 priv->staging_rxon.cck_basic_rates =
2336 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2337}
2338
bb8c093b 2339static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
b481de9c 2340{
b481de9c 2341 if (mode == IEEE80211_IF_TYPE_IBSS) {
bb8c093b 2342 const struct iwl3945_channel_info *ch_info;
b481de9c 2343
bb8c093b 2344 ch_info = iwl3945_get_channel_info(priv,
8318d78a 2345 priv->band,
b481de9c
ZY		 2346 le16_to_cpu(priv->staging_rxon.channel));
2347
2348 if (!ch_info || !is_channel_ibss(ch_info)) {
2349 IWL_ERROR("channel %d not IBSS channel\n",
2350 le16_to_cpu(priv->staging_rxon.channel));
2351 return -EINVAL;
2352 }
2353 }
2354
b481de9c
ZY		 2355 priv->iw_mode = mode;
2356
bb8c093b 2357 iwl3945_connection_init_rx_config(priv);
b481de9c
ZY		 2358 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2359
bb8c093b 2360 iwl3945_clear_stations_table(priv);
b481de9c 2361
fde3571f
MA		 2362 /* dont commit rxon if rf-kill is on*/
2363 if (!iwl3945_is_ready_rf(priv))
2364 return -EAGAIN;
2365
2366 cancel_delayed_work(&priv->scan_check);
2367 if (iwl3945_scan_cancel_timeout(priv, 100)) {
2368 IWL_WARNING("Aborted scan still in progress after 100ms\n");
2369 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
2370 return -EAGAIN;
2371 }
2372
bb8c093b 2373 iwl3945_commit_rxon(priv);
b481de9c
ZY		 2374
2375 return 0;
2376}
2377
bb8c093b 2378static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
e039fa4a 2379 struct ieee80211_tx_info *info,
bb8c093b 2380 struct iwl3945_cmd *cmd,
b481de9c
ZY		 2381 struct sk_buff *skb_frag,
2382 int last_frag)
2383{
1c014420 2384 struct iwl3945_hw_key *keyinfo =
e039fa4a 2385 &priv->stations[info->control.hw_key->hw_key_idx].keyinfo;
b481de9c
ZY		 2386
2387 switch (keyinfo->alg) {
2388 case ALG_CCMP:
2389 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
2390 memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
2391 IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
2392 break;
2393
2394 case ALG_TKIP:
2395#if 0
2396 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
2397
2398 if (last_frag)
2399 memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
2400 8);
2401 else
2402 memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
2403#endif
2404 break;
2405
2406 case ALG_WEP:
2407 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
e039fa4a 2408 (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
b481de9c
ZY		 2409
2410 if (keyinfo->keylen == 13)
2411 cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
2412
2413 memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
2414
2415 IWL_DEBUG_TX("Configuring packet for WEP encryption "
e039fa4a 2416 "with key %d\n", info->control.hw_key->hw_key_idx);
b481de9c
ZY		 2417 break;
2418
b481de9c
ZY		 2419 default:
2420 printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
2421 break;
2422 }
2423}
2424
2425/*
2426 * handle build REPLY_TX command notification.
2427 */
bb8c093b
CH		 2428static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
2429 struct iwl3945_cmd *cmd,
e039fa4a 2430 struct ieee80211_tx_info *info,
b481de9c
ZY		 2431 struct ieee80211_hdr *hdr,
2432 int is_unicast, u8 std_id)
2433{
b481de9c
ZY		 2434 u16 fc = le16_to_cpu(hdr->frame_control);
2435 __le32 tx_flags = cmd->cmd.tx.tx_flags;
2436
2437 cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e039fa4a 2438 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
b481de9c
ZY		 2439 tx_flags |= TX_CMD_FLG_ACK_MSK;
2440 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
2441 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2442 if (ieee80211_is_probe_response(fc) &&
2443 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
2444 tx_flags |= TX_CMD_FLG_TSF_MSK;
2445 } else {
2446 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
2447 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2448 }
2449
2450 cmd->cmd.tx.sta_id = std_id;
2451 if (ieee80211_get_morefrag(hdr))
2452 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
2453
54dbb525
TW		 2454 if (ieee80211_is_qos_data(fc)) {
2455 u8 *qc = ieee80211_get_qos_ctrl(hdr, ieee80211_get_hdrlen(fc));
2456 cmd->cmd.tx.tid_tspec = qc[0] & 0xf;
b481de9c 2457 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 2458 } else {
b481de9c 2459 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 2460 }
b481de9c 2461
e039fa4a 2462 if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) {
b481de9c
ZY		 2463 tx_flags |= TX_CMD_FLG_RTS_MSK;
2464 tx_flags &= ~TX_CMD_FLG_CTS_MSK;
e039fa4a 2465 } else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) {
b481de9c
ZY		 2466 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2467 tx_flags |= TX_CMD_FLG_CTS_MSK;
2468 }
2469
2470 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
2471 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
2472
2473 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
2474 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) {
2475 if ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_REQ ||
2476 (fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_REASSOC_REQ)
bc434dd2 2477 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
b481de9c 2478 else
bc434dd2 2479 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
ab53d8af 2480 } else {
b481de9c 2481 cmd->cmd.tx.timeout.pm_frame_timeout = 0;
ab53d8af
MA		 2482#ifdef CONFIG_IWL3945_LEDS
2483 priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
2484#endif
2485 }
b481de9c
ZY		 2486
2487 cmd->cmd.tx.driver_txop = 0;
2488 cmd->cmd.tx.tx_flags = tx_flags;
2489 cmd->cmd.tx.next_frame_len = 0;
2490}
2491
6440adb5
CB		 2492/**
2493 * iwl3945_get_sta_id - Find station's index within station table
2494 */
bb8c093b 2495static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
b481de9c
ZY		 2496{
2497 int sta_id;
2498 u16 fc = le16_to_cpu(hdr->frame_control);
2499
6440adb5 2500 /* If this frame is broadcast or management, use broadcast station id */
b481de9c
ZY		 2501 if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
2502 is_multicast_ether_addr(hdr->addr1))
2503 return priv->hw_setting.bcast_sta_id;
2504
2505 switch (priv->iw_mode) {
2506
6440adb5
CB		 2507 /* If we are a client station in a BSS network, use the special
2508 * AP station entry (that's the only station we communicate with) */
b481de9c
ZY		 2509 case IEEE80211_IF_TYPE_STA:
2510 return IWL_AP_ID;
2511
2512 /* If we are an AP, then find the station, or use BCAST */
2513 case IEEE80211_IF_TYPE_AP:
bb8c093b 2514 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY		 2515 if (sta_id != IWL_INVALID_STATION)
2516 return sta_id;
2517 return priv->hw_setting.bcast_sta_id;
2518
6440adb5
CB		 2519 /* If this frame is going out to an IBSS network, find the station,
2520 * or create a new station table entry */
0795af57
JP		 2521 case IEEE80211_IF_TYPE_IBSS: {
2522 DECLARE_MAC_BUF(mac);
2523
6440adb5 2524 /* Create new station table entry */
bb8c093b 2525 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY		 2526 if (sta_id != IWL_INVALID_STATION)
2527 return sta_id;
2528
bb8c093b 2529 sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
b481de9c
ZY		 2530
2531 if (sta_id != IWL_INVALID_STATION)
2532 return sta_id;
2533
0795af57 2534 IWL_DEBUG_DROP("Station %s not in station map. "
b481de9c 2535 "Defaulting to broadcast...\n",
0795af57 2536 print_mac(mac, hdr->addr1));
bb8c093b 2537 iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
b481de9c 2538 return priv->hw_setting.bcast_sta_id;
0795af57 2539 }
b481de9c 2540 default:
01ebd063 2541 IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode);
b481de9c
ZY		 2542 return priv->hw_setting.bcast_sta_id;
2543 }
2544}
2545
2546/*
2547 * start REPLY_TX command process
2548 */
e039fa4a 2549static int iwl3945_tx_skb(struct iwl3945_priv *priv, struct sk_buff *skb)
b481de9c
ZY		 2550{
2551 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
e039fa4a 2552 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bb8c093b 2553 struct iwl3945_tfd_frame *tfd;
b481de9c 2554 u32 *control_flags;
e2530083 2555 int txq_id = skb_get_queue_mapping(skb);
bb8c093b
CH		 2556 struct iwl3945_tx_queue *txq = NULL;
2557 struct iwl3945_queue *q = NULL;
b481de9c
ZY		 2558 dma_addr_t phys_addr;
2559 dma_addr_t txcmd_phys;
bb8c093b 2560 struct iwl3945_cmd *out_cmd = NULL;
54dbb525
TW		 2561 u16 len, idx, len_org, hdr_len;
2562 u8 id;
2563 u8 unicast;
b481de9c 2564 u8 sta_id;
54dbb525 2565 u8 tid = 0;
b481de9c
ZY		 2566 u16 seq_number = 0;
2567 u16 fc;
b481de9c 2568 u8 wait_write_ptr = 0;
54dbb525 2569 u8 *qc = NULL;
b481de9c
ZY		 2570 unsigned long flags;
2571 int rc;
2572
2573 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2574 if (iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 2575 IWL_DEBUG_DROP("Dropping - RF KILL\n");
2576 goto drop_unlock;
2577 }
2578
32bfd35d
JB		 2579 if (!priv->vif) {
2580 IWL_DEBUG_DROP("Dropping - !priv->vif\n");
b481de9c
ZY		 2581 goto drop_unlock;
2582 }
2583
e039fa4a 2584 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
b481de9c
ZY		 2585 IWL_ERROR("ERROR: No TX rate available.\n");
2586 goto drop_unlock;
2587 }
2588
2589 unicast = !is_multicast_ether_addr(hdr->addr1);
2590 id = 0;
2591
2592 fc = le16_to_cpu(hdr->frame_control);
2593
c8b0e6e1 2594#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 2595 if (ieee80211_is_auth(fc))
2596 IWL_DEBUG_TX("Sending AUTH frame\n");
2597 else if (ieee80211_is_assoc_request(fc))
2598 IWL_DEBUG_TX("Sending ASSOC frame\n");
2599 else if (ieee80211_is_reassoc_request(fc))
2600 IWL_DEBUG_TX("Sending REASSOC frame\n");
2601#endif
2602
7878a5a4 2603 /* drop all data frame if we are not associated */
a6477249
RC		 2604 if ((!iwl3945_is_associated(priv) ||
2605 ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && !priv->assoc_id)) &&
b481de9c 2606 ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA)) {
bb8c093b 2607 IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
b481de9c
ZY		 2608 goto drop_unlock;
2609 }
2610
2611 spin_unlock_irqrestore(&priv->lock, flags);
2612
2613 hdr_len = ieee80211_get_hdrlen(fc);
6440adb5
CB		 2614
2615 /* Find (or create) index into station table for destination station */
bb8c093b 2616 sta_id = iwl3945_get_sta_id(priv, hdr);
b481de9c 2617 if (sta_id == IWL_INVALID_STATION) {
0795af57
JP		 2618 DECLARE_MAC_BUF(mac);
2619
2620 IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
2621 print_mac(mac, hdr->addr1));
b481de9c
ZY		 2622 goto drop;
2623 }
2624
2625 IWL_DEBUG_RATE("station Id %d\n", sta_id);
2626
54dbb525
TW		 2627 if (ieee80211_is_qos_data(fc)) {
2628 qc = ieee80211_get_qos_ctrl(hdr, hdr_len);
2629 tid = qc[0] & 0xf;
b481de9c
ZY		 2630 seq_number = priv->stations[sta_id].tid[tid].seq_number &
2631 IEEE80211_SCTL_SEQ;
2632 hdr->seq_ctrl = cpu_to_le16(seq_number) |
2633 (hdr->seq_ctrl &
2634 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
2635 seq_number += 0x10;
2636 }
6440adb5
CB		 2637
2638 /* Descriptor for chosen Tx queue */
b481de9c
ZY		 2639 txq = &priv->txq[txq_id];
2640 q = &txq->q;
2641
2642 spin_lock_irqsave(&priv->lock, flags);
2643
6440adb5 2644 /* Set up first empty TFD within this queue's circular TFD buffer */
fc4b6853 2645 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY		 2646 memset(tfd, 0, sizeof(*tfd));
2647 control_flags = (u32 *) tfd;
fc4b6853 2648 idx = get_cmd_index(q, q->write_ptr, 0);
b481de9c 2649
6440adb5 2650 /* Set up driver data for this TFD */
bb8c093b 2651 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
fc4b6853 2652 txq->txb[q->write_ptr].skb[0] = skb;
6440adb5
CB		 2653
2654 /* Init first empty entry in queue's array of Tx/cmd buffers */
b481de9c
ZY		 2655 out_cmd = &txq->cmd[idx];
2656 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
2657 memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
6440adb5
CB		 2658
2659 /*
2660 * Set up the Tx-command (not MAC!) header.
2661 * Store the chosen Tx queue and TFD index within the sequence field;
2662 * after Tx, uCode's Tx response will return this value so driver can
2663 * locate the frame within the tx queue and do post-tx processing.
2664 */
b481de9c
ZY		 2665 out_cmd->hdr.cmd = REPLY_TX;
2666 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
fc4b6853 2667 INDEX_TO_SEQ(q->write_ptr)));
6440adb5
CB		 2668
2669 /* Copy MAC header from skb into command buffer */
b481de9c
ZY		 2670 memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
2671
6440adb5
CB		 2672 /*
2673 * Use the first empty entry in this queue's command buffer array
2674 * to contain the Tx command and MAC header concatenated together
2675 * (payload data will be in another buffer).
2676 * Size of this varies, due to varying MAC header length.
2677 * If end is not dword aligned, we'll have 2 extra bytes at the end
2678 * of the MAC header (device reads on dword boundaries).
2679 * We'll tell device about this padding later.
2680 */
b481de9c 2681 len = priv->hw_setting.tx_cmd_len +
bb8c093b 2682 sizeof(struct iwl3945_cmd_header) + hdr_len;
b481de9c
ZY		 2683
2684 len_org = len;
2685 len = (len + 3) & ~3;
2686
2687 if (len_org != len)
2688 len_org = 1;
2689 else
2690 len_org = 0;
2691
6440adb5
CB		 2692 /* Physical address of this Tx command's header (not MAC header!),
2693 * within command buffer array. */
bb8c093b
CH		 2694 txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
2695 offsetof(struct iwl3945_cmd, hdr);
b481de9c 2696
6440adb5
CB		 2697 /* Add buffer containing Tx command and MAC(!) header to TFD's
2698 * first entry */
bb8c093b 2699 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
b481de9c 2700
e039fa4a
JB		 2701 if (!(info->flags & IEEE80211_TX_CTL_DO_NOT_ENCRYPT))
2702 iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0);
b481de9c 2703
6440adb5
CB		 2704 /* Set up TFD's 2nd entry to point directly to remainder of skb,
2705 * if any (802.11 null frames have no payload). */
b481de9c
ZY		 2706 len = skb->len - hdr_len;
2707 if (len) {
2708 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
2709 len, PCI_DMA_TODEVICE);
bb8c093b 2710 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
b481de9c
ZY		 2711 }
2712
b481de9c 2713 if (!len)
6440adb5 2714 /* If there is no payload, then we use only one Tx buffer */
b481de9c
ZY		 2715 *control_flags = TFD_CTL_COUNT_SET(1);
2716 else
6440adb5
CB		 2717 /* Else use 2 buffers.
2718 * Tell 3945 about any padding after MAC header */
b481de9c
ZY		 2719 *control_flags = TFD_CTL_COUNT_SET(2) |
2720 TFD_CTL_PAD_SET(U32_PAD(len));
2721
6440adb5 2722 /* Total # bytes to be transmitted */
b481de9c
ZY		 2723 len = (u16)skb->len;
2724 out_cmd->cmd.tx.len = cpu_to_le16(len);
2725
2726 /* TODO need this for burst mode later on */
e039fa4a 2727 iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, unicast, sta_id);
b481de9c
ZY		 2728
2729 /* set is_hcca to 0; it probably will never be implemented */
e039fa4a 2730 iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
b481de9c
ZY		 2731
2732 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
2733 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
2734
2735 if (!ieee80211_get_morefrag(hdr)) {
2736 txq->need_update = 1;
2737 if (qc) {
b481de9c
ZY		 2738 priv->stations[sta_id].tid[tid].seq_number = seq_number;
2739 }
2740 } else {
2741 wait_write_ptr = 1;
2742 txq->need_update = 0;
2743 }
2744
bb8c093b 2745 iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
b481de9c
ZY		 2746 sizeof(out_cmd->cmd.tx));
2747
bb8c093b 2748 iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
b481de9c
ZY		 2749 ieee80211_get_hdrlen(fc));
2750
6440adb5 2751 /* Tell device the write index *just past* this latest filled TFD */
c54b679d 2752 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
bb8c093b 2753 rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 2754 spin_unlock_irqrestore(&priv->lock, flags);
2755
2756 if (rc)
2757 return rc;
2758
bb8c093b 2759 if ((iwl3945_queue_space(q) < q->high_mark)
b481de9c
ZY		 2760 && priv->mac80211_registered) {
2761 if (wait_write_ptr) {
2762 spin_lock_irqsave(&priv->lock, flags);
2763 txq->need_update = 1;
bb8c093b 2764 iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 2765 spin_unlock_irqrestore(&priv->lock, flags);
2766 }
2767
e2530083 2768 ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
b481de9c
ZY		 2769 }
2770
2771 return 0;
2772
2773drop_unlock:
2774 spin_unlock_irqrestore(&priv->lock, flags);
2775drop:
2776 return -1;
2777}
2778
bb8c093b 2779static void iwl3945_set_rate(struct iwl3945_priv *priv)
b481de9c 2780{
8318d78a 2781 const struct ieee80211_supported_band *sband = NULL;
b481de9c
ZY		 2782 struct ieee80211_rate *rate;
2783 int i;
2784
8318d78a
JB		 2785 sband = iwl3945_get_band(priv, priv->band);
2786 if (!sband) {
c4ba9621
SA		 2787 IWL_ERROR("Failed to set rate: unable to get hw mode\n");
2788 return;
2789 }
b481de9c
ZY		 2790
2791 priv->active_rate = 0;
2792 priv->active_rate_basic = 0;
2793
8318d78a
JB		 2794 IWL_DEBUG_RATE("Setting rates for %s GHz\n",
2795 sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
2796
2797 for (i = 0; i < sband->n_bitrates; i++) {
2798 rate = &sband->bitrates[i];
2799 if ((rate->hw_value < IWL_RATE_COUNT) &&
2800 !(rate->flags & IEEE80211_CHAN_DISABLED)) {
2801 IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
2802 rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
2803 priv->active_rate |= (1 << rate->hw_value);
2804 }
b481de9c
ZY		 2805 }
2806
2807 IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
2808 priv->active_rate, priv->active_rate_basic);
2809
2810 /*
2811 * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
2812 * otherwise set it to the default of all CCK rates and 6, 12, 24 for
2813 * OFDM
2814 */
2815 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
2816 priv->staging_rxon.cck_basic_rates =
2817 ((priv->active_rate_basic &
2818 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
2819 else
2820 priv->staging_rxon.cck_basic_rates =
2821 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2822
2823 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
2824 priv->staging_rxon.ofdm_basic_rates =
2825 ((priv->active_rate_basic &
2826 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
2827 IWL_FIRST_OFDM_RATE) & 0xFF;
2828 else
2829 priv->staging_rxon.ofdm_basic_rates =
2830 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2831}
2832
bb8c093b 2833static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
b481de9c
ZY		 2834{
2835 unsigned long flags;
2836
2837 if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
2838 return;
2839
2840 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
2841 disable_radio ? "OFF" : "ON");
2842
2843 if (disable_radio) {
bb8c093b 2844 iwl3945_scan_cancel(priv);
b481de9c
ZY		 2845 /* FIXME: This is a workaround for AP */
2846 if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
2847 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2848 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 2849 CSR_UCODE_SW_BIT_RFKILL);
2850 spin_unlock_irqrestore(&priv->lock, flags);
bb8c093b 2851 iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
b481de9c
ZY		 2852 set_bit(STATUS_RF_KILL_SW, &priv->status);
2853 }
2854 return;
2855 }
2856
2857 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2858 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 2859
2860 clear_bit(STATUS_RF_KILL_SW, &priv->status);
2861 spin_unlock_irqrestore(&priv->lock, flags);
2862
2863 /* wake up ucode */
2864 msleep(10);
2865
2866 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH		 2867 iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
2868 if (!iwl3945_grab_nic_access(priv))
2869 iwl3945_release_nic_access(priv);
b481de9c
ZY		 2870 spin_unlock_irqrestore(&priv->lock, flags);
2871
2872 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
2873 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
2874 "disabled by HW switch\n");
2875 return;
2876 }
2877
2878 queue_work(priv->workqueue, &priv->restart);
2879 return;
2880}
2881
bb8c093b 2882void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
b481de9c
ZY		 2883 u32 decrypt_res, struct ieee80211_rx_status *stats)
2884{
2885 u16 fc =
2886 le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
2887
2888 if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
2889 return;
2890
2891 if (!(fc & IEEE80211_FCTL_PROTECTED))
2892 return;
2893
2894 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
2895 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2896 case RX_RES_STATUS_SEC_TYPE_TKIP:
2897 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2898 RX_RES_STATUS_BAD_ICV_MIC)
2899 stats->flag |= RX_FLAG_MMIC_ERROR;
2900 case RX_RES_STATUS_SEC_TYPE_WEP:
2901 case RX_RES_STATUS_SEC_TYPE_CCMP:
2902 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2903 RX_RES_STATUS_DECRYPT_OK) {
2904 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
2905 stats->flag |= RX_FLAG_DECRYPTED;
2906 }
2907 break;
2908
2909 default:
2910 break;
2911 }
2912}
2913
b481de9c
ZY		 2914#define IWL_PACKET_RETRY_TIME HZ
2915
bb8c093b 2916int iwl3945_is_duplicate_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
b481de9c
ZY		 2917{
2918 u16 sc = le16_to_cpu(header->seq_ctrl);
2919 u16 seq = (sc & IEEE80211_SCTL_SEQ) >> 4;
2920 u16 frag = sc & IEEE80211_SCTL_FRAG;
2921 u16 *last_seq, *last_frag;
2922 unsigned long *last_time;
2923
2924 switch (priv->iw_mode) {
2925 case IEEE80211_IF_TYPE_IBSS:{
2926 struct list_head *p;
bb8c093b 2927 struct iwl3945_ibss_seq *entry = NULL;
b481de9c
ZY		 2928 u8 *mac = header->addr2;
2929 int index = mac[5] & (IWL_IBSS_MAC_HASH_SIZE - 1);
2930
2931 __list_for_each(p, &priv->ibss_mac_hash[index]) {
bb8c093b 2932 entry = list_entry(p, struct iwl3945_ibss_seq, list);
b481de9c
ZY		 2933 if (!compare_ether_addr(entry->mac, mac))
2934 break;
2935 }
2936 if (p == &priv->ibss_mac_hash[index]) {
2937 entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
2938 if (!entry) {
bc434dd2 2939 IWL_ERROR("Cannot malloc new mac entry\n");
b481de9c
ZY		 2940 return 0;
2941 }
2942 memcpy(entry->mac, mac, ETH_ALEN);
2943 entry->seq_num = seq;
2944 entry->frag_num = frag;
2945 entry->packet_time = jiffies;
bc434dd2 2946 list_add(&entry->list, &priv->ibss_mac_hash[index]);
b481de9c
ZY		 2947 return 0;
2948 }
2949 last_seq = &entry->seq_num;
2950 last_frag = &entry->frag_num;
2951 last_time = &entry->packet_time;
2952 break;
2953 }
2954 case IEEE80211_IF_TYPE_STA:
2955 last_seq = &priv->last_seq_num;
2956 last_frag = &priv->last_frag_num;
2957 last_time = &priv->last_packet_time;
2958 break;
2959 default:
2960 return 0;
2961 }
2962 if ((*last_seq == seq) &&
2963 time_after(*last_time + IWL_PACKET_RETRY_TIME, jiffies)) {
2964 if (*last_frag == frag)
2965 goto drop;
2966 if (*last_frag + 1 != frag)
2967 /* out-of-order fragment */
2968 goto drop;
2969 } else
2970 *last_seq = seq;
2971
2972 *last_frag = frag;
2973 *last_time = jiffies;
2974 return 0;
2975
2976 drop:
2977 return 1;
2978}
2979
c8b0e6e1 2980#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 2981
2982#include "iwl-spectrum.h"
2983
2984#define BEACON_TIME_MASK_LOW 0x00FFFFFF
2985#define BEACON_TIME_MASK_HIGH 0xFF000000
2986#define TIME_UNIT 1024
2987
2988/*
2989 * extended beacon time format
2990 * time in usec will be changed into a 32-bit value in 8:24 format
2991 * the high 1 byte is the beacon counts
2992 * the lower 3 bytes is the time in usec within one beacon interval
2993 */
2994
bb8c093b 2995static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
b481de9c
ZY		 2996{
2997 u32 quot;
2998 u32 rem;
2999 u32 interval = beacon_interval * 1024;
3000
3001 if (!interval || !usec)
3002 return 0;
3003
3004 quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
3005 rem = (usec % interval) & BEACON_TIME_MASK_LOW;
3006
3007 return (quot << 24) + rem;
3008}
3009
3010/* base is usually what we get from ucode with each received frame,
3011 * the same as HW timer counter counting down
3012 */
3013
bb8c093b 3014static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
b481de9c
ZY		 3015{
3016 u32 base_low = base & BEACON_TIME_MASK_LOW;
3017 u32 addon_low = addon & BEACON_TIME_MASK_LOW;
3018 u32 interval = beacon_interval * TIME_UNIT;
3019 u32 res = (base & BEACON_TIME_MASK_HIGH) +
3020 (addon & BEACON_TIME_MASK_HIGH);
3021
3022 if (base_low > addon_low)
3023 res += base_low - addon_low;
3024 else if (base_low < addon_low) {
3025 res += interval + base_low - addon_low;
3026 res += (1 << 24);
3027 } else
3028 res += (1 << 24);
3029
3030 return cpu_to_le32(res);
3031}
3032
bb8c093b 3033static int iwl3945_get_measurement(struct iwl3945_priv *priv,
b481de9c
ZY		 3034 struct ieee80211_measurement_params *params,
3035 u8 type)
3036{
bb8c093b
CH		 3037 struct iwl3945_spectrum_cmd spectrum;
3038 struct iwl3945_rx_packet *res;
3039 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 3040 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
3041 .data = (void *)&spectrum,
3042 .meta.flags = CMD_WANT_SKB,
3043 };
3044 u32 add_time = le64_to_cpu(params->start_time);
3045 int rc;
3046 int spectrum_resp_status;
3047 int duration = le16_to_cpu(params->duration);
3048
bb8c093b 3049 if (iwl3945_is_associated(priv))
b481de9c 3050 add_time =
bb8c093b 3051 iwl3945_usecs_to_beacons(
b481de9c
ZY		 3052 le64_to_cpu(params->start_time) - priv->last_tsf,
3053 le16_to_cpu(priv->rxon_timing.beacon_interval));
3054
3055 memset(&spectrum, 0, sizeof(spectrum));
3056
3057 spectrum.channel_count = cpu_to_le16(1);
3058 spectrum.flags =
3059 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
3060 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
3061 cmd.len = sizeof(spectrum);
3062 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
3063
bb8c093b 3064 if (iwl3945_is_associated(priv))
b481de9c 3065 spectrum.start_time =
bb8c093b 3066 iwl3945_add_beacon_time(priv->last_beacon_time,
b481de9c
ZY		 3067 add_time,
3068 le16_to_cpu(priv->rxon_timing.beacon_interval));
3069 else
3070 spectrum.start_time = 0;
3071
3072 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
3073 spectrum.channels[0].channel = params->channel;
3074 spectrum.channels[0].type = type;
3075 if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
3076 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
3077 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
3078
bb8c093b 3079 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 3080 if (rc)
3081 return rc;
3082
bb8c093b 3083 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 3084 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
3085 IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
3086 rc = -EIO;
3087 }
3088
3089 spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
3090 switch (spectrum_resp_status) {
3091 case 0: /* Command will be handled */
3092 if (res->u.spectrum.id != 0xff) {
bc434dd2
IS		 3093 IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
3094 res->u.spectrum.id);
b481de9c
ZY		 3095 priv->measurement_status &= ~MEASUREMENT_READY;
3096 }
3097 priv->measurement_status |= MEASUREMENT_ACTIVE;
3098 rc = 0;
3099 break;
3100
3101 case 1: /* Command will not be handled */
3102 rc = -EAGAIN;
3103 break;
3104 }
3105
3106 dev_kfree_skb_any(cmd.meta.u.skb);
3107
3108 return rc;
3109}
3110#endif
3111
bb8c093b
CH		 3112static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
3113 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3114{
bb8c093b
CH		 3115 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3116 struct iwl3945_alive_resp *palive;
b481de9c
ZY		 3117 struct delayed_work *pwork;
3118
3119 palive = &pkt->u.alive_frame;
3120
3121 IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
3122 "0x%01X 0x%01X\n",
3123 palive->is_valid, palive->ver_type,
3124 palive->ver_subtype);
3125
3126 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
3127 IWL_DEBUG_INFO("Initialization Alive received.\n");
3128 memcpy(&priv->card_alive_init,
3129 &pkt->u.alive_frame,
bb8c093b 3130 sizeof(struct iwl3945_init_alive_resp));
b481de9c
ZY		 3131 pwork = &priv->init_alive_start;
3132 } else {
3133 IWL_DEBUG_INFO("Runtime Alive received.\n");
3134 memcpy(&priv->card_alive, &pkt->u.alive_frame,
bb8c093b 3135 sizeof(struct iwl3945_alive_resp));
b481de9c 3136 pwork = &priv->alive_start;
bb8c093b 3137 iwl3945_disable_events(priv);
b481de9c
ZY		 3138 }
3139
3140 /* We delay the ALIVE response by 5ms to
3141 * give the HW RF Kill time to activate... */
3142 if (palive->is_valid == UCODE_VALID_OK)
3143 queue_delayed_work(priv->workqueue, pwork,
3144 msecs_to_jiffies(5));
3145 else
3146 IWL_WARNING("uCode did not respond OK.\n");
3147}
3148
bb8c093b
CH		 3149static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
3150 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3151{
bb8c093b 3152 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3153
3154 IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
3155 return;
3156}
3157
bb8c093b
CH		 3158static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
3159 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3160{
bb8c093b 3161 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3162
3163 IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
3164 "seq 0x%04X ser 0x%08X\n",
3165 le32_to_cpu(pkt->u.err_resp.error_type),
3166 get_cmd_string(pkt->u.err_resp.cmd_id),
3167 pkt->u.err_resp.cmd_id,
3168 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
3169 le32_to_cpu(pkt->u.err_resp.error_info));
3170}
3171
3172#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
3173
bb8c093b 3174static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3175{
bb8c093b
CH		 3176 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3177 struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
3178 struct iwl3945_csa_notification *csa = &(pkt->u.csa_notif);
b481de9c
ZY		 3179 IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
3180 le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
3181 rxon->channel = csa->channel;
3182 priv->staging_rxon.channel = csa->channel;
3183}
3184
bb8c093b
CH		 3185static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
3186 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3187{
c8b0e6e1 3188#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
bb8c093b
CH		 3189 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3190 struct iwl3945_spectrum_notification *report = &(pkt->u.spectrum_notif);
b481de9c
ZY		 3191
3192 if (!report->state) {
3193 IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
3194 "Spectrum Measure Notification: Start\n");
3195 return;
3196 }
3197
3198 memcpy(&priv->measure_report, report, sizeof(*report));
3199 priv->measurement_status |= MEASUREMENT_READY;
3200#endif
3201}
3202
bb8c093b
CH		 3203static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
3204 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3205{
c8b0e6e1 3206#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3207 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3208 struct iwl3945_sleep_notification *sleep = &(pkt->u.sleep_notif);
b481de9c
ZY		 3209 IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
3210 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
3211#endif
3212}
3213
bb8c093b
CH		 3214static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
3215 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3216{
bb8c093b 3217 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3218 IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
3219 "notification for %s:\n",
3220 le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
bb8c093b 3221 iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
b481de9c
ZY		 3222}
3223
bb8c093b 3224static void iwl3945_bg_beacon_update(struct work_struct *work)
b481de9c 3225{
bb8c093b
CH		 3226 struct iwl3945_priv *priv =
3227 container_of(work, struct iwl3945_priv, beacon_update);
b481de9c
ZY		 3228 struct sk_buff *beacon;
3229
3230 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 3231 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY		 3232
3233 if (!beacon) {
3234 IWL_ERROR("update beacon failed\n");
3235 return;
3236 }
3237
3238 mutex_lock(&priv->mutex);
3239 /* new beacon skb is allocated every time; dispose previous.*/
3240 if (priv->ibss_beacon)
3241 dev_kfree_skb(priv->ibss_beacon);
3242
3243 priv->ibss_beacon = beacon;
3244 mutex_unlock(&priv->mutex);
3245
bb8c093b 3246 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 3247}
3248
bb8c093b
CH		 3249static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
3250 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3251{
c8b0e6e1 3252#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3253 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3254 struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
b481de9c
ZY		 3255 u8 rate = beacon->beacon_notify_hdr.rate;
3256
3257 IWL_DEBUG_RX("beacon status %x retries %d iss %d "
3258 "tsf %d %d rate %d\n",
3259 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
3260 beacon->beacon_notify_hdr.failure_frame,
3261 le32_to_cpu(beacon->ibss_mgr_status),
3262 le32_to_cpu(beacon->high_tsf),
3263 le32_to_cpu(beacon->low_tsf), rate);
3264#endif
3265
3266 if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
3267 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
3268 queue_work(priv->workqueue, &priv->beacon_update);
3269}
3270
3271/* Service response to REPLY_SCAN_CMD (0x80) */
bb8c093b
CH		 3272static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
3273 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3274{
c8b0e6e1 3275#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3276 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3277 struct iwl3945_scanreq_notification *notif =
3278 (struct iwl3945_scanreq_notification *)pkt->u.raw;
b481de9c
ZY		 3279
3280 IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
3281#endif
3282}
3283
3284/* Service SCAN_START_NOTIFICATION (0x82) */
bb8c093b
CH		 3285static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
3286 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3287{
bb8c093b
CH		 3288 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3289 struct iwl3945_scanstart_notification *notif =
3290 (struct iwl3945_scanstart_notification *)pkt->u.raw;
b481de9c
ZY		 3291 priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
3292 IWL_DEBUG_SCAN("Scan start: "
3293 "%d [802.11%s] "
3294 "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
3295 notif->channel,
3296 notif->band ? "bg" : "a",
3297 notif->tsf_high,
3298 notif->tsf_low, notif->status, notif->beacon_timer);
3299}
3300
3301/* Service SCAN_RESULTS_NOTIFICATION (0x83) */
bb8c093b
CH		 3302static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
3303 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3304{
bb8c093b
CH		 3305 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3306 struct iwl3945_scanresults_notification *notif =
3307 (struct iwl3945_scanresults_notification *)pkt->u.raw;
b481de9c
ZY		 3308
3309 IWL_DEBUG_SCAN("Scan ch.res: "
3310 "%d [802.11%s] "
3311 "(TSF: 0x%08X:%08X) - %d "
3312 "elapsed=%lu usec (%dms since last)\n",
3313 notif->channel,
3314 notif->band ? "bg" : "a",
3315 le32_to_cpu(notif->tsf_high),
3316 le32_to_cpu(notif->tsf_low),
3317 le32_to_cpu(notif->statistics[0]),
3318 le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
3319 jiffies_to_msecs(elapsed_jiffies
3320 (priv->last_scan_jiffies, jiffies)));
3321
3322 priv->last_scan_jiffies = jiffies;
7878a5a4 3323 priv->next_scan_jiffies = 0;
b481de9c
ZY		 3324}
3325
3326/* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
bb8c093b
CH		 3327static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
3328 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3329{
bb8c093b
CH		 3330 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3331 struct iwl3945_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
b481de9c
ZY		 3332
3333 IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
3334 scan_notif->scanned_channels,
3335 scan_notif->tsf_low,
3336 scan_notif->tsf_high, scan_notif->status);
3337
3338 /* The HW is no longer scanning */
3339 clear_bit(STATUS_SCAN_HW, &priv->status);
3340
3341 /* The scan completion notification came in, so kill that timer... */
3342 cancel_delayed_work(&priv->scan_check);
3343
3344 IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
3345 (priv->scan_bands == 2) ? "2.4" : "5.2",
3346 jiffies_to_msecs(elapsed_jiffies
3347 (priv->scan_pass_start, jiffies)));
3348
3349 /* Remove this scanned band from the list
3350 * of pending bands to scan */
3351 priv->scan_bands--;
3352
3353 /* If a request to abort was given, or the scan did not succeed
3354 * then we reset the scan state machine and terminate,
3355 * re-queuing another scan if one has been requested */
3356 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
3357 IWL_DEBUG_INFO("Aborted scan completed.\n");
3358 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
3359 } else {
3360 /* If there are more bands on this scan pass reschedule */
3361 if (priv->scan_bands > 0)
3362 goto reschedule;
3363 }
3364
3365 priv->last_scan_jiffies = jiffies;
7878a5a4 3366 priv->next_scan_jiffies = 0;
b481de9c
ZY		 3367 IWL_DEBUG_INFO("Setting scan to off\n");
3368
3369 clear_bit(STATUS_SCANNING, &priv->status);
3370
3371 IWL_DEBUG_INFO("Scan took %dms\n",
3372 jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
3373
3374 queue_work(priv->workqueue, &priv->scan_completed);
3375
3376 return;
3377
3378reschedule:
3379 priv->scan_pass_start = jiffies;
3380 queue_work(priv->workqueue, &priv->request_scan);
3381}
3382
3383/* Handle notification from uCode that card's power state is changing
3384 * due to software, hardware, or critical temperature RFKILL */
bb8c093b
CH		 3385static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
3386 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3387{
bb8c093b 3388 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3389 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
3390 unsigned long status = priv->status;
3391
3392 IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
3393 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3394 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
3395
bb8c093b 3396 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 3397 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3398
3399 if (flags & HW_CARD_DISABLED)
3400 set_bit(STATUS_RF_KILL_HW, &priv->status);
3401 else
3402 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3403
3404
3405 if (flags & SW_CARD_DISABLED)
3406 set_bit(STATUS_RF_KILL_SW, &priv->status);
3407 else
3408 clear_bit(STATUS_RF_KILL_SW, &priv->status);
3409
bb8c093b 3410 iwl3945_scan_cancel(priv);
b481de9c
ZY		 3411
3412 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
3413 test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
3414 (test_bit(STATUS_RF_KILL_SW, &status) !=
3415 test_bit(STATUS_RF_KILL_SW, &priv->status)))
3416 queue_work(priv->workqueue, &priv->rf_kill);
3417 else
3418 wake_up_interruptible(&priv->wait_command_queue);
3419}
3420
3421/**
bb8c093b 3422 * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY		 3423 *
3424 * Setup the RX handlers for each of the reply types sent from the uCode
3425 * to the host.
3426 *
3427 * This function chains into the hardware specific files for them to setup
3428 * any hardware specific handlers as well.
3429 */
bb8c093b 3430static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
b481de9c 3431{
bb8c093b
CH		 3432 priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
3433 priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
3434 priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
3435 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
b481de9c 3436 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
bb8c093b
CH		 3437 iwl3945_rx_spectrum_measure_notif;
3438 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
b481de9c 3439 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
bb8c093b
CH		 3440 iwl3945_rx_pm_debug_statistics_notif;
3441 priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
b481de9c 3442
9fbab516
BC		 3443 /*
3444 * The same handler is used for both the REPLY to a discrete
3445 * statistics request from the host as well as for the periodic
3446 * statistics notifications (after received beacons) from the uCode.
b481de9c 3447 */
bb8c093b
CH		 3448 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
3449 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
b481de9c 3450
bb8c093b
CH		 3451 priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
3452 priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
b481de9c 3453 priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
bb8c093b 3454 iwl3945_rx_scan_results_notif;
b481de9c 3455 priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
bb8c093b
CH		 3456 iwl3945_rx_scan_complete_notif;
3457 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
b481de9c 3458
9fbab516 3459 /* Set up hardware specific Rx handlers */
bb8c093b 3460 iwl3945_hw_rx_handler_setup(priv);
b481de9c
ZY		 3461}
3462
91c066f2
TW		 3463/**
3464 * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries
3465 * When FW advances 'R' index, all entries between old and new 'R' index
3466 * need to be reclaimed.
3467 */
3468static void iwl3945_cmd_queue_reclaim(struct iwl3945_priv *priv,
3469 int txq_id, int index)
3470{
3471 struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
3472 struct iwl3945_queue *q = &txq->q;
3473 int nfreed = 0;
3474
3475 if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) {
3476 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
3477 "is out of range [0-%d] %d %d.\n", txq_id,
3478 index, q->n_bd, q->write_ptr, q->read_ptr);
3479 return;
3480 }
3481
3482 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
3483 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
3484 if (nfreed > 1) {
3485 IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
3486 q->write_ptr, q->read_ptr);
3487 queue_work(priv->workqueue, &priv->restart);
3488 break;
3489 }
3490 nfreed++;
3491 }
3492}
3493
3494
b481de9c 3495/**
bb8c093b 3496 * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
b481de9c
ZY		 3497 * @rxb: Rx buffer to reclaim
3498 *
3499 * If an Rx buffer has an async callback associated with it the callback
3500 * will be executed. The attached skb (if present) will only be freed
3501 * if the callback returns 1
3502 */
bb8c093b
CH		 3503static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
3504 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3505{
bb8c093b 3506 struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
b481de9c
ZY		 3507 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3508 int txq_id = SEQ_TO_QUEUE(sequence);
3509 int index = SEQ_TO_INDEX(sequence);
3510 int huge = sequence & SEQ_HUGE_FRAME;
3511 int cmd_index;
bb8c093b 3512 struct iwl3945_cmd *cmd;
b481de9c 3513
b481de9c
ZY		 3514 BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
3515
3516 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
3517 cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
3518
3519 /* Input error checking is done when commands are added to queue. */
3520 if (cmd->meta.flags & CMD_WANT_SKB) {
3521 cmd->meta.source->u.skb = rxb->skb;
3522 rxb->skb = NULL;
3523 } else if (cmd->meta.u.callback &&
3524 !cmd->meta.u.callback(priv, cmd, rxb->skb))
3525 rxb->skb = NULL;
3526
91c066f2 3527 iwl3945_cmd_queue_reclaim(priv, txq_id, index);
b481de9c
ZY		 3528
3529 if (!(cmd->meta.flags & CMD_ASYNC)) {
3530 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
3531 wake_up_interruptible(&priv->wait_command_queue);
3532 }
3533}
3534
3535/************************** RX-FUNCTIONS ****************************/
3536/*
3537 * Rx theory of operation
3538 *
3539 * The host allocates 32 DMA target addresses and passes the host address
3540 * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
3541 * 0 to 31
3542 *
3543 * Rx Queue Indexes
3544 * The host/firmware share two index registers for managing the Rx buffers.
3545 *
3546 * The READ index maps to the first position that the firmware may be writing
3547 * to -- the driver can read up to (but not including) this position and get
3548 * good data.
3549 * The READ index is managed by the firmware once the card is enabled.
3550 *
3551 * The WRITE index maps to the last position the driver has read from -- the
3552 * position preceding WRITE is the last slot the firmware can place a packet.
3553 *
3554 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
3555 * WRITE = READ.
3556 *
9fbab516 3557 * During initialization, the host sets up the READ queue position to the first
b481de9c
ZY		 3558 * INDEX position, and WRITE to the last (READ - 1 wrapped)
3559 *
9fbab516 3560 * When the firmware places a packet in a buffer, it will advance the READ index
b481de9c
ZY		 3561 * and fire the RX interrupt. The driver can then query the READ index and
3562 * process as many packets as possible, moving the WRITE index forward as it
3563 * resets the Rx queue buffers with new memory.
3564 *
3565 * The management in the driver is as follows:
3566 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
3567 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
01ebd063 3568 * to replenish the iwl->rxq->rx_free.
bb8c093b 3569 * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
b481de9c
ZY		 3570 * iwl->rxq is replenished and the READ INDEX is updated (updating the
3571 * 'processed' and 'read' driver indexes as well)
3572 * + A received packet is processed and handed to the kernel network stack,
3573 * detached from the iwl->rxq. The driver 'processed' index is updated.
3574 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
3575 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
3576 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
3577 * were enough free buffers and RX_STALLED is set it is cleared.
3578 *
3579 *
3580 * Driver sequence:
3581 *
9fbab516
BC		 3582 * iwl3945_rx_queue_alloc() Allocates rx_free
3583 * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
bb8c093b 3584 * iwl3945_rx_queue_restock
9fbab516 3585 * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
b481de9c
ZY		 3586 * queue, updates firmware pointers, and updates
3587 * the WRITE index. If insufficient rx_free buffers
bb8c093b 3588 * are available, schedules iwl3945_rx_replenish
b481de9c
ZY		 3589 *
3590 * -- enable interrupts --
9fbab516 3591 * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the
b481de9c
ZY		 3592 * READ INDEX, detaching the SKB from the pool.
3593 * Moves the packet buffer from queue to rx_used.
bb8c093b 3594 * Calls iwl3945_rx_queue_restock to refill any empty
b481de9c
ZY		 3595 * slots.
3596 * ...
3597 *
3598 */
3599
3600/**
bb8c093b 3601 * iwl3945_rx_queue_space - Return number of free slots available in queue.
b481de9c 3602 */
bb8c093b 3603static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
b481de9c
ZY		 3604{
3605 int s = q->read - q->write;
3606 if (s <= 0)
3607 s += RX_QUEUE_SIZE;
3608 /* keep some buffer to not confuse full and empty queue */
3609 s -= 2;
3610 if (s < 0)
3611 s = 0;
3612 return s;
3613}
3614
3615/**
bb8c093b 3616 * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
b481de9c 3617 */
bb8c093b 3618int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
b481de9c
ZY		 3619{
3620 u32 reg = 0;
3621 int rc = 0;
3622 unsigned long flags;
3623
3624 spin_lock_irqsave(&q->lock, flags);
3625
3626 if (q->need_update == 0)
3627 goto exit_unlock;
3628
6440adb5 3629 /* If power-saving is in use, make sure device is awake */
b481de9c 3630 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
bb8c093b 3631 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY		 3632
3633 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
bb8c093b 3634 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 3635 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3636 goto exit_unlock;
3637 }
3638
bb8c093b 3639 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 3640 if (rc)
3641 goto exit_unlock;
3642
6440adb5 3643 /* Device expects a multiple of 8 */
bb8c093b 3644 iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
b481de9c 3645 q->write & ~0x7);
bb8c093b 3646 iwl3945_release_nic_access(priv);
6440adb5
CB		 3647
3648 /* Else device is assumed to be awake */
b481de9c 3649 } else
6440adb5 3650 /* Device expects a multiple of 8 */
bb8c093b 3651 iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
b481de9c
ZY		 3652
3653
3654 q->need_update = 0;
3655
3656 exit_unlock:
3657 spin_unlock_irqrestore(&q->lock, flags);
3658 return rc;
3659}
3660
3661/**
9fbab516 3662 * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
b481de9c 3663 */
bb8c093b 3664static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
b481de9c
ZY		 3665 dma_addr_t dma_addr)
3666{
3667 return cpu_to_le32((u32)dma_addr);
3668}
3669
3670/**
bb8c093b 3671 * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
b481de9c 3672 *
9fbab516 3673 * If there are slots in the RX queue that need to be restocked,
b481de9c 3674 * and we have free pre-allocated buffers, fill the ranks as much
9fbab516 3675 * as we can, pulling from rx_free.
b481de9c
ZY		 3676 *
3677 * This moves the 'write' index forward to catch up with 'processed', and
3678 * also updates the memory address in the firmware to reference the new
3679 * target buffer.
3680 */
bb8c093b 3681static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
b481de9c 3682{
bb8c093b 3683 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 3684 struct list_head *element;
bb8c093b 3685 struct iwl3945_rx_mem_buffer *rxb;
b481de9c
ZY		 3686 unsigned long flags;
3687 int write, rc;
3688
3689 spin_lock_irqsave(&rxq->lock, flags);
3690 write = rxq->write & ~0x7;
bb8c093b 3691 while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
6440adb5 3692 /* Get next free Rx buffer, remove from free list */
b481de9c 3693 element = rxq->rx_free.next;
bb8c093b 3694 rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
b481de9c 3695 list_del(element);
6440adb5
CB		 3696
3697 /* Point to Rx buffer via next RBD in circular buffer */
bb8c093b 3698 rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
b481de9c
ZY		 3699 rxq->queue[rxq->write] = rxb;
3700 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
3701 rxq->free_count--;
3702 }
3703 spin_unlock_irqrestore(&rxq->lock, flags);
3704 /* If the pre-allocated buffer pool is dropping low, schedule to
3705 * refill it */
3706 if (rxq->free_count <= RX_LOW_WATERMARK)
3707 queue_work(priv->workqueue, &priv->rx_replenish);
3708
3709
6440adb5
CB		 3710 /* If we've added more space for the firmware to place data, tell it.
3711 * Increment device's write pointer in multiples of 8. */
b481de9c
ZY		 3712 if ((write != (rxq->write & ~0x7))
3713 || (abs(rxq->write - rxq->read) > 7)) {
3714 spin_lock_irqsave(&rxq->lock, flags);
3715 rxq->need_update = 1;
3716 spin_unlock_irqrestore(&rxq->lock, flags);
bb8c093b 3717 rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 3718 if (rc)
3719 return rc;
3720 }
3721
3722 return 0;
3723}
3724
3725/**
bb8c093b 3726 * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
b481de9c
ZY		 3727 *
3728 * When moving to rx_free an SKB is allocated for the slot.
3729 *
bb8c093b 3730 * Also restock the Rx queue via iwl3945_rx_queue_restock.
01ebd063 3731 * This is called as a scheduled work item (except for during initialization)
b481de9c 3732 */
5c0eef96 3733static void iwl3945_rx_allocate(struct iwl3945_priv *priv)
b481de9c 3734{
bb8c093b 3735 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 3736 struct list_head *element;
bb8c093b 3737 struct iwl3945_rx_mem_buffer *rxb;
b481de9c
ZY		 3738 unsigned long flags;
3739 spin_lock_irqsave(&rxq->lock, flags);
3740 while (!list_empty(&rxq->rx_used)) {
3741 element = rxq->rx_used.next;
bb8c093b 3742 rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
6440adb5
CB		 3743
3744 /* Alloc a new receive buffer */
b481de9c
ZY		 3745 rxb->skb =
3746 alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
3747 if (!rxb->skb) {
3748 if (net_ratelimit())
3749 printk(KERN_CRIT DRV_NAME
3750 ": Can not allocate SKB buffers\n");
3751 /* We don't reschedule replenish work here -- we will
3752 * call the restock method and if it still needs
3753 * more buffers it will schedule replenish */
3754 break;
3755 }
12342c47
ZY		 3756
3757 /* If radiotap head is required, reserve some headroom here.
3758 * The physical head count is a variable rx_stats->phy_count.
3759 * We reserve 4 bytes here. Plus these extra bytes, the
3760 * headroom of the physical head should be enough for the
3761 * radiotap head that iwl3945 supported. See iwl3945_rt.
3762 */
3763 skb_reserve(rxb->skb, 4);
3764
b481de9c
ZY		 3765 priv->alloc_rxb_skb++;
3766 list_del(element);
6440adb5
CB		 3767
3768 /* Get physical address of RB/SKB */
b481de9c
ZY		 3769 rxb->dma_addr =
3770 pci_map_single(priv->pci_dev, rxb->skb->data,
3771 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3772 list_add_tail(&rxb->list, &rxq->rx_free);
3773 rxq->free_count++;
3774 }
3775 spin_unlock_irqrestore(&rxq->lock, flags);
5c0eef96
MA		 3776}
3777
3778/*
3779 * this should be called while priv->lock is locked
3780 */
4fd1f841 3781static void __iwl3945_rx_replenish(void *data)
5c0eef96
MA		 3782{
3783 struct iwl3945_priv *priv = data;
3784
3785 iwl3945_rx_allocate(priv);
3786 iwl3945_rx_queue_restock(priv);
3787}
3788
3789
3790void iwl3945_rx_replenish(void *data)
3791{
3792 struct iwl3945_priv *priv = data;
3793 unsigned long flags;
3794
3795 iwl3945_rx_allocate(priv);
b481de9c
ZY		 3796
3797 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 3798 iwl3945_rx_queue_restock(priv);
b481de9c
ZY		 3799 spin_unlock_irqrestore(&priv->lock, flags);
3800}
3801
3802/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
9fbab516 3803 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
b481de9c
ZY		 3804 * This free routine walks the list of POOL entries and if SKB is set to
3805 * non NULL it is unmapped and freed
3806 */
bb8c093b 3807static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY		 3808{
3809 int i;
3810 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
3811 if (rxq->pool[i].skb != NULL) {
3812 pci_unmap_single(priv->pci_dev,
3813 rxq->pool[i].dma_addr,
3814 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3815 dev_kfree_skb(rxq->pool[i].skb);
3816 }
3817 }
3818
3819 pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
3820 rxq->dma_addr);
3821 rxq->bd = NULL;
3822}
3823
bb8c093b 3824int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
b481de9c 3825{
bb8c093b 3826 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 3827 struct pci_dev *dev = priv->pci_dev;
3828 int i;
3829
3830 spin_lock_init(&rxq->lock);
3831 INIT_LIST_HEAD(&rxq->rx_free);
3832 INIT_LIST_HEAD(&rxq->rx_used);
6440adb5
CB		 3833
3834 /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
b481de9c
ZY		 3835 rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
3836 if (!rxq->bd)
3837 return -ENOMEM;
6440adb5 3838
b481de9c
ZY		 3839 /* Fill the rx_used queue with _all_ of the Rx buffers */
3840 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
3841 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
6440adb5 3842
b481de9c
ZY		 3843 /* Set us so that we have processed and used all buffers, but have
3844 * not restocked the Rx queue with fresh buffers */
3845 rxq->read = rxq->write = 0;
3846 rxq->free_count = 0;
3847 rxq->need_update = 0;
3848 return 0;
3849}
3850
bb8c093b 3851void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY		 3852{
3853 unsigned long flags;
3854 int i;
3855 spin_lock_irqsave(&rxq->lock, flags);
3856 INIT_LIST_HEAD(&rxq->rx_free);
3857 INIT_LIST_HEAD(&rxq->rx_used);
3858 /* Fill the rx_used queue with _all_ of the Rx buffers */
3859 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
3860 /* In the reset function, these buffers may have been allocated
3861 * to an SKB, so we need to unmap and free potential storage */
3862 if (rxq->pool[i].skb != NULL) {
3863 pci_unmap_single(priv->pci_dev,
3864 rxq->pool[i].dma_addr,
3865 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3866 priv->alloc_rxb_skb--;
3867 dev_kfree_skb(rxq->pool[i].skb);
3868 rxq->pool[i].skb = NULL;
3869 }
3870 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
3871 }
3872
3873 /* Set us so that we have processed and used all buffers, but have
3874 * not restocked the Rx queue with fresh buffers */
3875 rxq->read = rxq->write = 0;
3876 rxq->free_count = 0;
3877 spin_unlock_irqrestore(&rxq->lock, flags);
3878}
3879
3880/* Convert linear signal-to-noise ratio into dB */
3881static u8 ratio2dB[100] = {
3882/* 0 1 2 3 4 5 6 7 8 9 */
3883 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
3884 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
3885 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
3886 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
3887 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
3888 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
3889 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
3890 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
3891 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
3892 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
3893};
3894
3895/* Calculates a relative dB value from a ratio of linear
3896 * (i.e. not dB) signal levels.
3897 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
bb8c093b 3898int iwl3945_calc_db_from_ratio(int sig_ratio)
b481de9c 3899{
221c80cf
AB		 3900 /* 1000:1 or higher just report as 60 dB */
3901 if (sig_ratio >= 1000)
b481de9c
ZY		 3902 return 60;
3903
221c80cf 3904 /* 100:1 or higher, divide by 10 and use table,
b481de9c 3905 * add 20 dB to make up for divide by 10 */
221c80cf 3906 if (sig_ratio >= 100)
b481de9c
ZY		 3907 return (20 + (int)ratio2dB[sig_ratio/10]);
3908
3909 /* We shouldn't see this */
3910 if (sig_ratio < 1)
3911 return 0;
3912
3913 /* Use table for ratios 1:1 - 99:1 */
3914 return (int)ratio2dB[sig_ratio];
3915}
3916
3917#define PERFECT_RSSI (-20) /* dBm */
3918#define WORST_RSSI (-95) /* dBm */
3919#define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
3920
3921/* Calculate an indication of rx signal quality (a percentage, not dBm!).
3922 * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
3923 * about formulas used below. */
bb8c093b 3924int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
b481de9c
ZY		 3925{
3926 int sig_qual;
3927 int degradation = PERFECT_RSSI - rssi_dbm;
3928
3929 /* If we get a noise measurement, use signal-to-noise ratio (SNR)
3930 * as indicator; formula is (signal dbm - noise dbm).
3931 * SNR at or above 40 is a great signal (100%).
3932 * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
3933 * Weakest usable signal is usually 10 - 15 dB SNR. */
3934 if (noise_dbm) {
3935 if (rssi_dbm - noise_dbm >= 40)
3936 return 100;
3937 else if (rssi_dbm < noise_dbm)
3938 return 0;
3939 sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
3940
3941 /* Else use just the signal level.
3942 * This formula is a least squares fit of data points collected and
3943 * compared with a reference system that had a percentage (%) display
3944 * for signal quality. */
3945 } else
3946 sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
3947 (15 * RSSI_RANGE + 62 * degradation)) /
3948 (RSSI_RANGE * RSSI_RANGE);
3949
3950 if (sig_qual > 100)
3951 sig_qual = 100;
3952 else if (sig_qual < 1)
3953 sig_qual = 0;
3954
3955 return sig_qual;
3956}
3957
3958/**
9fbab516 3959 * iwl3945_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY		 3960 *
3961 * Uses the priv->rx_handlers callback function array to invoke
3962 * the appropriate handlers, including command responses,
3963 * frame-received notifications, and other notifications.
3964 */
bb8c093b 3965static void iwl3945_rx_handle(struct iwl3945_priv *priv)
b481de9c 3966{
bb8c093b
CH		 3967 struct iwl3945_rx_mem_buffer *rxb;
3968 struct iwl3945_rx_packet *pkt;
3969 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 3970 u32 r, i;
3971 int reclaim;
3972 unsigned long flags;
5c0eef96 3973 u8 fill_rx = 0;
d68ab680 3974 u32 count = 8;
b481de9c 3975
6440adb5
CB		 3976 /* uCode's read index (stored in shared DRAM) indicates the last Rx
3977 * buffer that the driver may process (last buffer filled by ucode). */
bb8c093b 3978 r = iwl3945_hw_get_rx_read(priv);
b481de9c
ZY		 3979 i = rxq->read;
3980
5c0eef96
MA		 3981 if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
3982 fill_rx = 1;
b481de9c
ZY		 3983 /* Rx interrupt, but nothing sent from uCode */
3984 if (i == r)
3985 IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
3986
3987 while (i != r) {
3988 rxb = rxq->queue[i];
3989
9fbab516 3990 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY		 3991 * then a bug has been introduced in the queue refilling
3992 * routines -- catch it here */
3993 BUG_ON(rxb == NULL);
3994
3995 rxq->queue[i] = NULL;
3996
3997 pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
3998 IWL_RX_BUF_SIZE,
3999 PCI_DMA_FROMDEVICE);
bb8c093b 4000 pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
b481de9c
ZY		 4001
4002 /* Reclaim a command buffer only if this packet is a response
4003 * to a (driver-originated) command.
4004 * If the packet (e.g. Rx frame) originated from uCode,
4005 * there is no command buffer to reclaim.
4006 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
4007 * but apparently a few don't get set; catch them here. */
4008 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
4009 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
4010 (pkt->hdr.cmd != REPLY_TX);
4011
4012 /* Based on type of command response or notification,
4013 * handle those that need handling via function in
bb8c093b 4014 * rx_handlers table. See iwl3945_setup_rx_handlers() */
b481de9c
ZY		 4015 if (priv->rx_handlers[pkt->hdr.cmd]) {
4016 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
4017 "r = %d, i = %d, %s, 0x%02x\n", r, i,
4018 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
4019 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
4020 } else {
4021 /* No handling needed */
4022 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
4023 "r %d i %d No handler needed for %s, 0x%02x\n",
4024 r, i, get_cmd_string(pkt->hdr.cmd),
4025 pkt->hdr.cmd);
4026 }
4027
4028 if (reclaim) {
9fbab516
BC		 4029 /* Invoke any callbacks, transfer the skb to caller, and
4030 * fire off the (possibly) blocking iwl3945_send_cmd()
b481de9c
ZY		 4031 * as we reclaim the driver command queue */
4032 if (rxb && rxb->skb)
bb8c093b 4033 iwl3945_tx_cmd_complete(priv, rxb);
b481de9c
ZY		 4034 else
4035 IWL_WARNING("Claim null rxb?\n");
4036 }
4037
4038 /* For now we just don't re-use anything. We can tweak this
4039 * later to try and re-use notification packets and SKBs that
4040 * fail to Rx correctly */
4041 if (rxb->skb != NULL) {
4042 priv->alloc_rxb_skb--;
4043 dev_kfree_skb_any(rxb->skb);
4044 rxb->skb = NULL;
4045 }
4046
4047 pci_unmap_single(priv->pci_dev, rxb->dma_addr,
4048 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
4049 spin_lock_irqsave(&rxq->lock, flags);
4050 list_add_tail(&rxb->list, &priv->rxq.rx_used);
4051 spin_unlock_irqrestore(&rxq->lock, flags);
4052 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA		 4053 /* If there are a lot of unused frames,
4054 * restock the Rx queue so ucode won't assert. */
4055 if (fill_rx) {
4056 count++;
4057 if (count >= 8) {
4058 priv->rxq.read = i;
4059 __iwl3945_rx_replenish(priv);
4060 count = 0;
4061 }
4062 }
b481de9c
ZY		 4063 }
4064
4065 /* Backtrack one entry */
4066 priv->rxq.read = i;
bb8c093b 4067 iwl3945_rx_queue_restock(priv);
b481de9c
ZY		 4068}
4069
6440adb5
CB		 4070/**
4071 * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
4072 */
bb8c093b
CH		 4073static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
4074 struct iwl3945_tx_queue *txq)
b481de9c
ZY		 4075{
4076 u32 reg = 0;
4077 int rc = 0;
4078 int txq_id = txq->q.id;
4079
4080 if (txq->need_update == 0)
4081 return rc;
4082
4083 /* if we're trying to save power */
4084 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
4085 /* wake up nic if it's powered down ...
4086 * uCode will wake up, and interrupt us again, so next
4087 * time we'll skip this part. */
bb8c093b 4088 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY		 4089
4090 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
4091 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
bb8c093b 4092 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 4093 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
4094 return rc;
4095 }
4096
4097 /* restore this queue's parameters in nic hardware. */
bb8c093b 4098 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 4099 if (rc)
4100 return rc;
bb8c093b 4101 iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
fc4b6853 4102 txq->q.write_ptr | (txq_id << 8));
bb8c093b 4103 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4104
4105 /* else not in power-save mode, uCode will never sleep when we're
4106 * trying to tx (during RFKILL, we're not trying to tx). */
4107 } else
bb8c093b 4108 iwl3945_write32(priv, HBUS_TARG_WRPTR,
fc4b6853 4109 txq->q.write_ptr | (txq_id << 8));
b481de9c
ZY		 4110
4111 txq->need_update = 0;
4112
4113 return rc;
4114}
4115
c8b0e6e1 4116#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4117static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon)
b481de9c 4118{
0795af57
JP		 4119 DECLARE_MAC_BUF(mac);
4120
b481de9c 4121 IWL_DEBUG_RADIO("RX CONFIG:\n");
bb8c093b 4122 iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
b481de9c
ZY		 4123 IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
4124 IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
4125 IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
4126 le32_to_cpu(rxon->filter_flags));
4127 IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
4128 IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
4129 rxon->ofdm_basic_rates);
4130 IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
0795af57
JP		 4131 IWL_DEBUG_RADIO("u8[6] node_addr: %s\n",
4132 print_mac(mac, rxon->node_addr));
4133 IWL_DEBUG_RADIO("u8[6] bssid_addr: %s\n",
4134 print_mac(mac, rxon->bssid_addr));
b481de9c
ZY		 4135 IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
4136}
4137#endif
4138
bb8c093b 4139static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
b481de9c
ZY		 4140{
4141 IWL_DEBUG_ISR("Enabling interrupts\n");
4142 set_bit(STATUS_INT_ENABLED, &priv->status);
bb8c093b 4143 iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
b481de9c
ZY		 4144}
4145
0359facc
MA		 4146
4147/* call this function to flush any scheduled tasklet */
4148static inline void iwl_synchronize_irq(struct iwl3945_priv *priv)
4149{
4150 /* wait to make sure we flush pedding tasklet*/
4151 synchronize_irq(priv->pci_dev->irq);
4152 tasklet_kill(&priv->irq_tasklet);
4153}
4154
4155
bb8c093b 4156static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
b481de9c
ZY		 4157{
4158 clear_bit(STATUS_INT_ENABLED, &priv->status);
4159
4160 /* disable interrupts from uCode/NIC to host */
bb8c093b 4161 iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY		 4162
4163 /* acknowledge/clear/reset any interrupts still pending
4164 * from uCode or flow handler (Rx/Tx DMA) */
bb8c093b
CH		 4165 iwl3945_write32(priv, CSR_INT, 0xffffffff);
4166 iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
b481de9c
ZY		 4167 IWL_DEBUG_ISR("Disabled interrupts\n");
4168}
4169
4170static const char *desc_lookup(int i)
4171{
4172 switch (i) {
4173 case 1:
4174 return "FAIL";
4175 case 2:
4176 return "BAD_PARAM";
4177 case 3:
4178 return "BAD_CHECKSUM";
4179 case 4:
4180 return "NMI_INTERRUPT";
4181 case 5:
4182 return "SYSASSERT";
4183 case 6:
4184 return "FATAL_ERROR";
4185 }
4186
4187 return "UNKNOWN";
4188}
4189
4190#define ERROR_START_OFFSET (1 * sizeof(u32))
4191#define ERROR_ELEM_SIZE (7 * sizeof(u32))
4192
bb8c093b 4193static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
b481de9c
ZY		 4194{
4195 u32 i;
4196 u32 desc, time, count, base, data1;
4197 u32 blink1, blink2, ilink1, ilink2;
4198 int rc;
4199
4200 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
4201
bb8c093b 4202 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 4203 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
4204 return;
4205 }
4206
bb8c093b 4207 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 4208 if (rc) {
4209 IWL_WARNING("Can not read from adapter at this time.\n");
4210 return;
4211 }
4212
bb8c093b 4213 count = iwl3945_read_targ_mem(priv, base);
b481de9c
ZY		 4214
4215 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
4216 IWL_ERROR("Start IWL Error Log Dump:\n");
2acae16e 4217 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
b481de9c
ZY		 4218 }
4219
4220 IWL_ERROR("Desc Time asrtPC blink2 "
4221 "ilink1 nmiPC Line\n");
4222 for (i = ERROR_START_OFFSET;
4223 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
4224 i += ERROR_ELEM_SIZE) {
bb8c093b 4225 desc = iwl3945_read_targ_mem(priv, base + i);
b481de9c 4226 time =
bb8c093b 4227 iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
b481de9c 4228 blink1 =
bb8c093b 4229 iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
b481de9c 4230 blink2 =
bb8c093b 4231 iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
b481de9c 4232 ilink1 =
bb8c093b 4233 iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
b481de9c 4234 ilink2 =
bb8c093b 4235 iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
b481de9c 4236 data1 =
bb8c093b 4237 iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
b481de9c
ZY		 4238
4239 IWL_ERROR
4240 ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
4241 desc_lookup(desc), desc, time, blink1, blink2,
4242 ilink1, ilink2, data1);
4243 }
4244
bb8c093b 4245 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4246
4247}
4248
f58177b9 4249#define EVENT_START_OFFSET (6 * sizeof(u32))
b481de9c
ZY		 4250
4251/**
bb8c093b 4252 * iwl3945_print_event_log - Dump error event log to syslog
b481de9c 4253 *
bb8c093b 4254 * NOTE: Must be called with iwl3945_grab_nic_access() already obtained!
b481de9c 4255 */
bb8c093b 4256static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
b481de9c
ZY		 4257 u32 num_events, u32 mode)
4258{
4259 u32 i;
4260 u32 base; /* SRAM byte address of event log header */
4261 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
4262 u32 ptr; /* SRAM byte address of log data */
4263 u32 ev, time, data; /* event log data */
4264
4265 if (num_events == 0)
4266 return;
4267
4268 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
4269
4270 if (mode == 0)
4271 event_size = 2 * sizeof(u32);
4272 else
4273 event_size = 3 * sizeof(u32);
4274
4275 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
4276
4277 /* "time" is actually "data" for mode 0 (no timestamp).
4278 * place event id # at far right for easier visual parsing. */
4279 for (i = 0; i < num_events; i++) {
bb8c093b 4280 ev = iwl3945_read_targ_mem(priv, ptr);
b481de9c 4281 ptr += sizeof(u32);
bb8c093b 4282 time = iwl3945_read_targ_mem(priv, ptr);
b481de9c
ZY		 4283 ptr += sizeof(u32);
4284 if (mode == 0)
4285 IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
4286 else {
bb8c093b 4287 data = iwl3945_read_targ_mem(priv, ptr);
b481de9c
ZY		 4288 ptr += sizeof(u32);
4289 IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
4290 }
4291 }
4292}
4293
bb8c093b 4294static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
b481de9c
ZY		 4295{
4296 int rc;
4297 u32 base; /* SRAM byte address of event log header */
4298 u32 capacity; /* event log capacity in # entries */
4299 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
4300 u32 num_wraps; /* # times uCode wrapped to top of log */
4301 u32 next_entry; /* index of next entry to be written by uCode */
4302 u32 size; /* # entries that we'll print */
4303
4304 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 4305 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 4306 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
4307 return;
4308 }
4309
bb8c093b 4310 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 4311 if (rc) {
4312 IWL_WARNING("Can not read from adapter at this time.\n");
4313 return;
4314 }
4315
4316 /* event log header */
bb8c093b
CH		 4317 capacity = iwl3945_read_targ_mem(priv, base);
4318 mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
4319 num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
4320 next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
b481de9c
ZY		 4321
4322 size = num_wraps ? capacity : next_entry;
4323
4324 /* bail out if nothing in log */
4325 if (size == 0) {
583fab37 4326 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
bb8c093b 4327 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4328 return;
4329 }
4330
583fab37 4331 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
b481de9c
ZY		 4332 size, num_wraps);
4333
4334 /* if uCode has wrapped back to top of log, start at the oldest entry,
4335 * i.e the next one that uCode would fill. */
4336 if (num_wraps)
bb8c093b 4337 iwl3945_print_event_log(priv, next_entry,
b481de9c
ZY		 4338 capacity - next_entry, mode);
4339
4340 /* (then/else) start at top of log */
bb8c093b 4341 iwl3945_print_event_log(priv, 0, next_entry, mode);
b481de9c 4342
bb8c093b 4343 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4344}
4345
4346/**
bb8c093b 4347 * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
b481de9c 4348 */
bb8c093b 4349static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
b481de9c 4350{
bb8c093b 4351 /* Set the FW error flag -- cleared on iwl3945_down */
b481de9c
ZY		 4352 set_bit(STATUS_FW_ERROR, &priv->status);
4353
4354 /* Cancel currently queued command. */
4355 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
4356
c8b0e6e1 4357#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 4358 if (iwl3945_debug_level & IWL_DL_FW_ERRORS) {
4359 iwl3945_dump_nic_error_log(priv);
4360 iwl3945_dump_nic_event_log(priv);
4361 iwl3945_print_rx_config_cmd(&priv->staging_rxon);
b481de9c
ZY		 4362 }
4363#endif
4364
4365 wake_up_interruptible(&priv->wait_command_queue);
4366
4367 /* Keep the restart process from trying to send host
4368 * commands by clearing the INIT status bit */
4369 clear_bit(STATUS_READY, &priv->status);
4370
4371 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
4372 IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
4373 "Restarting adapter due to uCode error.\n");
4374
bb8c093b 4375 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 4376 memcpy(&priv->recovery_rxon, &priv->active_rxon,
4377 sizeof(priv->recovery_rxon));
4378 priv->error_recovering = 1;
4379 }
4380 queue_work(priv->workqueue, &priv->restart);
4381 }
4382}
4383
bb8c093b 4384static void iwl3945_error_recovery(struct iwl3945_priv *priv)
b481de9c
ZY		 4385{
4386 unsigned long flags;
4387
4388 memcpy(&priv->staging_rxon, &priv->recovery_rxon,
4389 sizeof(priv->staging_rxon));
4390 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 4391 iwl3945_commit_rxon(priv);
b481de9c 4392
bb8c093b 4393 iwl3945_add_station(priv, priv->bssid, 1, 0);
b481de9c
ZY		 4394
4395 spin_lock_irqsave(&priv->lock, flags);
4396 priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
4397 priv->error_recovering = 0;
4398 spin_unlock_irqrestore(&priv->lock, flags);
4399}
4400
bb8c093b 4401static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
b481de9c
ZY		 4402{
4403 u32 inta, handled = 0;
4404 u32 inta_fh;
4405 unsigned long flags;
c8b0e6e1 4406#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 4407 u32 inta_mask;
4408#endif
4409
4410 spin_lock_irqsave(&priv->lock, flags);
4411
4412 /* Ack/clear/reset pending uCode interrupts.
4413 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
4414 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
bb8c093b
CH		 4415 inta = iwl3945_read32(priv, CSR_INT);
4416 iwl3945_write32(priv, CSR_INT, inta);
b481de9c
ZY		 4417
4418 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
4419 * Any new interrupts that happen after this, either while we're
4420 * in this tasklet, or later, will show up in next ISR/tasklet. */
bb8c093b
CH		 4421 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
4422 iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 4423
c8b0e6e1 4424#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4425 if (iwl3945_debug_level & IWL_DL_ISR) {
9fbab516
BC		 4426 /* just for debug */
4427 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
b481de9c
ZY		 4428 IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4429 inta, inta_mask, inta_fh);
4430 }
4431#endif
4432
4433 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
4434 * atomic, make sure that inta covers all the interrupts that
4435 * we've discovered, even if FH interrupt came in just after
4436 * reading CSR_INT. */
6f83eaa1 4437 if (inta_fh & CSR39_FH_INT_RX_MASK)
b481de9c 4438 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 4439 if (inta_fh & CSR39_FH_INT_TX_MASK)
b481de9c
ZY		 4440 inta |= CSR_INT_BIT_FH_TX;
4441
4442 /* Now service all interrupt bits discovered above. */
4443 if (inta & CSR_INT_BIT_HW_ERR) {
4444 IWL_ERROR("Microcode HW error detected. Restarting.\n");
4445
4446 /* Tell the device to stop sending interrupts */
bb8c093b 4447 iwl3945_disable_interrupts(priv);
b481de9c 4448
bb8c093b 4449 iwl3945_irq_handle_error(priv);
b481de9c
ZY		 4450
4451 handled |= CSR_INT_BIT_HW_ERR;
4452
4453 spin_unlock_irqrestore(&priv->lock, flags);
4454
4455 return;
4456 }
4457
c8b0e6e1 4458#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4459 if (iwl3945_debug_level & (IWL_DL_ISR)) {
b481de9c 4460 /* NIC fires this, but we don't use it, redundant with WAKEUP */
25c03d8e
JP		 4461 if (inta & CSR_INT_BIT_SCD)
4462 IWL_DEBUG_ISR("Scheduler finished to transmit "
4463 "the frame/frames.\n");
b481de9c
ZY		 4464
4465 /* Alive notification via Rx interrupt will do the real work */
4466 if (inta & CSR_INT_BIT_ALIVE)
4467 IWL_DEBUG_ISR("Alive interrupt\n");
4468 }
4469#endif
4470 /* Safely ignore these bits for debug checks below */
25c03d8e 4471 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c
ZY		 4472
4473 /* HW RF KILL switch toggled (4965 only) */
4474 if (inta & CSR_INT_BIT_RF_KILL) {
4475 int hw_rf_kill = 0;
bb8c093b 4476 if (!(iwl3945_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY		 4477 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
4478 hw_rf_kill = 1;
4479
4480 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR,
4481 "RF_KILL bit toggled to %s.\n",
4482 hw_rf_kill ? "disable radio":"enable radio");
4483
4484 /* Queue restart only if RF_KILL switch was set to "kill"
4485 * when we loaded driver, and is now set to "enable".
4486 * After we're Alive, RF_KILL gets handled by
3230455d 4487 * iwl3945_rx_card_state_notif() */
53e49093
ZY		 4488 if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) {
4489 clear_bit(STATUS_RF_KILL_HW, &priv->status);
b481de9c 4490 queue_work(priv->workqueue, &priv->restart);
53e49093 4491 }
b481de9c
ZY		 4492
4493 handled |= CSR_INT_BIT_RF_KILL;
4494 }
4495
4496 /* Chip got too hot and stopped itself (4965 only) */
4497 if (inta & CSR_INT_BIT_CT_KILL) {
4498 IWL_ERROR("Microcode CT kill error detected.\n");
4499 handled |= CSR_INT_BIT_CT_KILL;
4500 }
4501
4502 /* Error detected by uCode */
4503 if (inta & CSR_INT_BIT_SW_ERR) {
4504 IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
4505 inta);
bb8c093b 4506 iwl3945_irq_handle_error(priv);
b481de9c
ZY		 4507 handled |= CSR_INT_BIT_SW_ERR;
4508 }
4509
4510 /* uCode wakes up after power-down sleep */
4511 if (inta & CSR_INT_BIT_WAKEUP) {
4512 IWL_DEBUG_ISR("Wakeup interrupt\n");
bb8c093b
CH		 4513 iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
4514 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
4515 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
4516 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
4517 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
4518 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
4519 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
b481de9c
ZY		 4520
4521 handled |= CSR_INT_BIT_WAKEUP;
4522 }
4523
4524 /* All uCode command responses, including Tx command responses,
4525 * Rx "responses" (frame-received notification), and other
4526 * notifications from uCode come through here*/
4527 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
bb8c093b 4528 iwl3945_rx_handle(priv);
b481de9c
ZY		 4529 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
4530 }
4531
4532 if (inta & CSR_INT_BIT_FH_TX) {
4533 IWL_DEBUG_ISR("Tx interrupt\n");
4534
bb8c093b
CH		 4535 iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
4536 if (!iwl3945_grab_nic_access(priv)) {
4537 iwl3945_write_direct32(priv,
b481de9c
ZY		 4538 FH_TCSR_CREDIT
4539 (ALM_FH_SRVC_CHNL), 0x0);
bb8c093b 4540 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4541 }
4542 handled |= CSR_INT_BIT_FH_TX;
4543 }
4544
4545 if (inta & ~handled)
4546 IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
4547
4548 if (inta & ~CSR_INI_SET_MASK) {
4549 IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
4550 inta & ~CSR_INI_SET_MASK);
4551 IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
4552 }
4553
4554 /* Re-enable all interrupts */
0359facc
MA		 4555 /* only Re-enable if disabled by irq */
4556 if (test_bit(STATUS_INT_ENABLED, &priv->status))
4557 iwl3945_enable_interrupts(priv);
b481de9c 4558
c8b0e6e1 4559#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 4560 if (iwl3945_debug_level & (IWL_DL_ISR)) {
4561 inta = iwl3945_read32(priv, CSR_INT);
4562 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
4563 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY		 4564 IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4565 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
4566 }
4567#endif
4568 spin_unlock_irqrestore(&priv->lock, flags);
4569}
4570
bb8c093b 4571static irqreturn_t iwl3945_isr(int irq, void *data)
b481de9c 4572{
bb8c093b 4573 struct iwl3945_priv *priv = data;
b481de9c
ZY		 4574 u32 inta, inta_mask;
4575 u32 inta_fh;
4576 if (!priv)
4577 return IRQ_NONE;
4578
4579 spin_lock(&priv->lock);
4580
4581 /* Disable (but don't clear!) interrupts here to avoid
4582 * back-to-back ISRs and sporadic interrupts from our NIC.
4583 * If we have something to service, the tasklet will re-enable ints.
4584 * If we *don't* have something, we'll re-enable before leaving here. */
bb8c093b
CH		 4585 inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */
4586 iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY		 4587
4588 /* Discover which interrupts are active/pending */
bb8c093b
CH		 4589 inta = iwl3945_read32(priv, CSR_INT);
4590 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY		 4591
4592 /* Ignore interrupt if there's nothing in NIC to service.
4593 * This may be due to IRQ shared with another device,
4594 * or due to sporadic interrupts thrown from our NIC. */
4595 if (!inta && !inta_fh) {
4596 IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
4597 goto none;
4598 }
4599
4600 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
4601 /* Hardware disappeared */
4602 IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta);
cb4da1a3 4603 goto unplugged;
b481de9c
ZY		 4604 }
4605
4606 IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4607 inta, inta_mask, inta_fh);
4608
25c03d8e
JP		 4609 inta &= ~CSR_INT_BIT_SCD;
4610
bb8c093b 4611 /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
25c03d8e
JP		 4612 if (likely(inta || inta_fh))
4613 tasklet_schedule(&priv->irq_tasklet);
cb4da1a3 4614unplugged:
b481de9c
ZY		 4615 spin_unlock(&priv->lock);
4616
4617 return IRQ_HANDLED;
4618
4619 none:
4620 /* re-enable interrupts here since we don't have anything to service. */
0359facc
MA		 4621 /* only Re-enable if disabled by irq */
4622 if (test_bit(STATUS_INT_ENABLED, &priv->status))
4623 iwl3945_enable_interrupts(priv);
b481de9c
ZY		 4624 spin_unlock(&priv->lock);
4625 return IRQ_NONE;
4626}
4627
4628/************************** EEPROM BANDS ****************************
4629 *
bb8c093b 4630 * The iwl3945_eeprom_band definitions below provide the mapping from the
b481de9c
ZY		 4631 * EEPROM contents to the specific channel number supported for each
4632 * band.
4633 *
bb8c093b 4634 * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3
b481de9c
ZY		 4635 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
4636 * The specific geography and calibration information for that channel
4637 * is contained in the eeprom map itself.
4638 *
4639 * During init, we copy the eeprom information and channel map
4640 * information into priv->channel_info_24/52 and priv->channel_map_24/52
4641 *
4642 * channel_map_24/52 provides the index in the channel_info array for a
4643 * given channel. We have to have two separate maps as there is channel
4644 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
4645 * band_2
4646 *
4647 * A value of 0xff stored in the channel_map indicates that the channel
4648 * is not supported by the hardware at all.
4649 *
4650 * A value of 0xfe in the channel_map indicates that the channel is not
4651 * valid for Tx with the current hardware. This means that
4652 * while the system can tune and receive on a given channel, it may not
4653 * be able to associate or transmit any frames on that
4654 * channel. There is no corresponding channel information for that
4655 * entry.
4656 *
4657 *********************************************************************/
4658
4659/* 2.4 GHz */
bb8c093b 4660static const u8 iwl3945_eeprom_band_1[14] = {
b481de9c
ZY		 4661 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
4662};
4663
4664/* 5.2 GHz bands */
9fbab516 4665static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
b481de9c
ZY		 4666 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
4667};
4668
9fbab516 4669static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
b481de9c
ZY		 4670 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
4671};
4672
bb8c093b 4673static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
b481de9c
ZY		 4674 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
4675};
4676
bb8c093b 4677static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
b481de9c
ZY		 4678 145, 149, 153, 157, 161, 165
4679};
4680
bb8c093b 4681static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
b481de9c 4682 int *eeprom_ch_count,
bb8c093b 4683 const struct iwl3945_eeprom_channel
b481de9c
ZY		 4684 **eeprom_ch_info,
4685 const u8 **eeprom_ch_index)
4686{
4687 switch (band) {
4688 case 1: /* 2.4GHz band */
bb8c093b 4689 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
b481de9c 4690 *eeprom_ch_info = priv->eeprom.band_1_channels;
bb8c093b 4691 *eeprom_ch_index = iwl3945_eeprom_band_1;
b481de9c 4692 break;
9fbab516 4693 case 2: /* 4.9GHz band */
bb8c093b 4694 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
b481de9c 4695 *eeprom_ch_info = priv->eeprom.band_2_channels;
bb8c093b 4696 *eeprom_ch_index = iwl3945_eeprom_band_2;
b481de9c
ZY		 4697 break;
4698 case 3: /* 5.2GHz band */
bb8c093b 4699 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
b481de9c 4700 *eeprom_ch_info = priv->eeprom.band_3_channels;
bb8c093b 4701 *eeprom_ch_index = iwl3945_eeprom_band_3;
b481de9c 4702 break;
9fbab516 4703 case 4: /* 5.5GHz band */
bb8c093b 4704 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
b481de9c 4705 *eeprom_ch_info = priv->eeprom.band_4_channels;
bb8c093b 4706 *eeprom_ch_index = iwl3945_eeprom_band_4;
b481de9c 4707 break;
9fbab516 4708 case 5: /* 5.7GHz band */
bb8c093b 4709 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
b481de9c 4710 *eeprom_ch_info = priv->eeprom.band_5_channels;
bb8c093b 4711 *eeprom_ch_index = iwl3945_eeprom_band_5;
b481de9c
ZY		 4712 break;
4713 default:
4714 BUG();
4715 return;
4716 }
4717}
4718
6440adb5
CB		 4719/**
4720 * iwl3945_get_channel_info - Find driver's private channel info
4721 *
4722 * Based on band and channel number.
4723 */
bb8c093b 4724const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv,
8318d78a 4725 enum ieee80211_band band, u16 channel)
b481de9c
ZY		 4726{
4727 int i;
4728
8318d78a
JB		 4729 switch (band) {
4730 case IEEE80211_BAND_5GHZ:
b481de9c
ZY		 4731 for (i = 14; i < priv->channel_count; i++) {
4732 if (priv->channel_info[i].channel == channel)
4733 return &priv->channel_info[i];
4734 }
4735 break;
4736
8318d78a 4737 case IEEE80211_BAND_2GHZ:
b481de9c
ZY		 4738 if (channel >= 1 && channel <= 14)
4739 return &priv->channel_info[channel - 1];
4740 break;
8318d78a
JB		 4741 case IEEE80211_NUM_BANDS:
4742 WARN_ON(1);
b481de9c
ZY		 4743 }
4744
4745 return NULL;
4746}
4747
4748#define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
4749 ? # x " " : "")
4750
6440adb5
CB		 4751/**
4752 * iwl3945_init_channel_map - Set up driver's info for all possible channels
4753 */
bb8c093b 4754static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
b481de9c
ZY		 4755{
4756 int eeprom_ch_count = 0;
4757 const u8 *eeprom_ch_index = NULL;
bb8c093b 4758 const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL;
b481de9c 4759 int band, ch;
bb8c093b 4760 struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 4761
4762 if (priv->channel_count) {
4763 IWL_DEBUG_INFO("Channel map already initialized.\n");
4764 return 0;
4765 }
4766
4767 if (priv->eeprom.version < 0x2f) {
4768 IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
4769 priv->eeprom.version);
4770 return -EINVAL;
4771 }
4772
4773 IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
4774
4775 priv->channel_count =
bb8c093b
CH		 4776 ARRAY_SIZE(iwl3945_eeprom_band_1) +
4777 ARRAY_SIZE(iwl3945_eeprom_band_2) +
4778 ARRAY_SIZE(iwl3945_eeprom_band_3) +
4779 ARRAY_SIZE(iwl3945_eeprom_band_4) +
4780 ARRAY_SIZE(iwl3945_eeprom_band_5);
b481de9c
ZY		 4781
4782 IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
4783
bb8c093b 4784 priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) *
b481de9c
ZY		 4785 priv->channel_count, GFP_KERNEL);
4786 if (!priv->channel_info) {
4787 IWL_ERROR("Could not allocate channel_info\n");
4788 priv->channel_count = 0;
4789 return -ENOMEM;
4790 }
4791
4792 ch_info = priv->channel_info;
4793
4794 /* Loop through the 5 EEPROM bands adding them in order to the
4795 * channel map we maintain (that contains additional information than
4796 * what just in the EEPROM) */
4797 for (band = 1; band <= 5; band++) {
4798
bb8c093b 4799 iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
b481de9c
ZY		 4800 &eeprom_ch_info, &eeprom_ch_index);
4801
4802 /* Loop through each band adding each of the channels */
4803 for (ch = 0; ch < eeprom_ch_count; ch++) {
4804 ch_info->channel = eeprom_ch_index[ch];
8318d78a
JB		 4805 ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
4806 IEEE80211_BAND_5GHZ;
b481de9c
ZY		 4807
4808 /* permanently store EEPROM's channel regulatory flags
4809 * and max power in channel info database. */
4810 ch_info->eeprom = eeprom_ch_info[ch];
4811
4812 /* Copy the run-time flags so they are there even on
4813 * invalid channels */
4814 ch_info->flags = eeprom_ch_info[ch].flags;
4815
4816 if (!(is_channel_valid(ch_info))) {
4817 IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
4818 "No traffic\n",
4819 ch_info->channel,
4820 ch_info->flags,
4821 is_channel_a_band(ch_info) ?
4822 "5.2" : "2.4");
4823 ch_info++;
4824 continue;
4825 }
4826
4827 /* Initialize regulatory-based run-time data */
4828 ch_info->max_power_avg = ch_info->curr_txpow =
4829 eeprom_ch_info[ch].max_power_avg;
4830 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
4831 ch_info->min_power = 0;
4832
fe7c4040 4833 IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
b481de9c
ZY		 4834 " %ddBm): Ad-Hoc %ssupported\n",
4835 ch_info->channel,
4836 is_channel_a_band(ch_info) ?
4837 "5.2" : "2.4",
8211ef78 4838 CHECK_AND_PRINT(VALID),
b481de9c
ZY		 4839 CHECK_AND_PRINT(IBSS),
4840 CHECK_AND_PRINT(ACTIVE),
4841 CHECK_AND_PRINT(RADAR),
4842 CHECK_AND_PRINT(WIDE),
b481de9c
ZY		 4843 CHECK_AND_PRINT(DFS),
4844 eeprom_ch_info[ch].flags,
4845 eeprom_ch_info[ch].max_power_avg,
4846 ((eeprom_ch_info[ch].
4847 flags & EEPROM_CHANNEL_IBSS)
4848 && !(eeprom_ch_info[ch].
4849 flags & EEPROM_CHANNEL_RADAR))
4850 ? "" : "not ");
4851
4852 /* Set the user_txpower_limit to the highest power
4853 * supported by any channel */
4854 if (eeprom_ch_info[ch].max_power_avg >
4855 priv->user_txpower_limit)
4856 priv->user_txpower_limit =
4857 eeprom_ch_info[ch].max_power_avg;
4858
4859 ch_info++;
4860 }
4861 }
4862
6440adb5 4863 /* Set up txpower settings in driver for all channels */
b481de9c
ZY		 4864 if (iwl3945_txpower_set_from_eeprom(priv))
4865 return -EIO;
4866
4867 return 0;
4868}
4869
849e0dce
RC		 4870/*
4871 * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
4872 */
4873static void iwl3945_free_channel_map(struct iwl3945_priv *priv)
4874{
4875 kfree(priv->channel_info);
4876 priv->channel_count = 0;
4877}
4878
b481de9c
ZY		 4879/* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
4880 * sending probe req. This should be set long enough to hear probe responses
4881 * from more than one AP. */
4882#define IWL_ACTIVE_DWELL_TIME_24 (20) /* all times in msec */
4883#define IWL_ACTIVE_DWELL_TIME_52 (10)
4884
4885/* For faster active scanning, scan will move to the next channel if fewer than
4886 * PLCP_QUIET_THRESH packets are heard on this channel within
4887 * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
4888 * time if it's a quiet channel (nothing responded to our probe, and there's
4889 * no other traffic).
4890 * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
4891#define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
4892#define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(5) /* msec */
4893
4894/* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
4895 * Must be set longer than active dwell time.
4896 * For the most reliable scan, set > AP beacon interval (typically 100msec). */
4897#define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
4898#define IWL_PASSIVE_DWELL_TIME_52 (10)
4899#define IWL_PASSIVE_DWELL_BASE (100)
4900#define IWL_CHANNEL_TUNE_TIME 5
4901
8318d78a
JB		 4902static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv,
4903 enum ieee80211_band band)
b481de9c 4904{
8318d78a 4905 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 4906 return IWL_ACTIVE_DWELL_TIME_52;
4907 else
4908 return IWL_ACTIVE_DWELL_TIME_24;
4909}
4910
8318d78a
JB		 4911static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv,
4912 enum ieee80211_band band)
b481de9c 4913{
8318d78a
JB		 4914 u16 active = iwl3945_get_active_dwell_time(priv, band);
4915 u16 passive = (band == IEEE80211_BAND_2GHZ) ?
b481de9c
ZY		 4916 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
4917 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
4918
bb8c093b 4919 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 4920 /* If we're associated, we clamp the maximum passive
4921 * dwell time to be 98% of the beacon interval (minus
4922 * 2 * channel tune time) */
4923 passive = priv->beacon_int;
4924 if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
4925 passive = IWL_PASSIVE_DWELL_BASE;
4926 passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
4927 }
4928
4929 if (passive <= active)
4930 passive = active + 1;
4931
4932 return passive;
4933}
4934
8318d78a
JB		 4935static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv,
4936 enum ieee80211_band band,
b481de9c 4937 u8 is_active, u8 direct_mask,
bb8c093b 4938 struct iwl3945_scan_channel *scan_ch)
b481de9c
ZY		 4939{
4940 const struct ieee80211_channel *channels = NULL;
8318d78a 4941 const struct ieee80211_supported_band *sband;
bb8c093b 4942 const struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 4943 u16 passive_dwell = 0;
4944 u16 active_dwell = 0;
4945 int added, i;
4946
8318d78a
JB		 4947 sband = iwl3945_get_band(priv, band);
4948 if (!sband)
b481de9c
ZY		 4949 return 0;
4950
8318d78a 4951 channels = sband->channels;
b481de9c 4952
8318d78a
JB		 4953 active_dwell = iwl3945_get_active_dwell_time(priv, band);
4954 passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
b481de9c 4955
8318d78a 4956 for (i = 0, added = 0; i < sband->n_channels; i++) {
182e2e66
JB		 4957 if (channels[i].flags & IEEE80211_CHAN_DISABLED)
4958 continue;
4959
8318d78a 4960 scan_ch->channel = channels[i].hw_value;
b481de9c 4961
8318d78a 4962 ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
b481de9c
ZY		 4963 if (!is_channel_valid(ch_info)) {
4964 IWL_DEBUG_SCAN("Channel %d is INVALID for this SKU.\n",
4965 scan_ch->channel);
4966 continue;
4967 }
4968
4969 if (!is_active || is_channel_passive(ch_info) ||
8318d78a 4970 (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN))
b481de9c
ZY		 4971 scan_ch->type = 0; /* passive */
4972 else
4973 scan_ch->type = 1; /* active */
4974
4975 if (scan_ch->type & 1)
4976 scan_ch->type |= (direct_mask << 1);
4977
b481de9c
ZY		 4978 scan_ch->active_dwell = cpu_to_le16(active_dwell);
4979 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
4980
9fbab516 4981 /* Set txpower levels to defaults */
b481de9c
ZY		 4982 scan_ch->tpc.dsp_atten = 110;
4983 /* scan_pwr_info->tpc.dsp_atten; */
4984
4985 /*scan_pwr_info->tpc.tx_gain; */
8318d78a 4986 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 4987 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
4988 else {
4989 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
4990 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
9fbab516 4991 * power level:
8a1b0245 4992 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
b481de9c
ZY		 4993 */
4994 }
4995
4996 IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
4997 scan_ch->channel,
4998 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
4999 (scan_ch->type & 1) ?
5000 active_dwell : passive_dwell);
5001
5002 scan_ch++;
5003 added++;
5004 }
5005
5006 IWL_DEBUG_SCAN("total channels to scan %d \n", added);
5007 return added;
5008}
5009
bb8c093b 5010static void iwl3945_init_hw_rates(struct iwl3945_priv *priv,
b481de9c
ZY		 5011 struct ieee80211_rate *rates)
5012{
5013 int i;
5014
5015 for (i = 0; i < IWL_RATE_COUNT; i++) {
8318d78a
JB		 5016 rates[i].bitrate = iwl3945_rates[i].ieee * 5;
5017 rates[i].hw_value = i; /* Rate scaling will work on indexes */
5018 rates[i].hw_value_short = i;
5019 rates[i].flags = 0;
5020 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
b481de9c 5021 /*
8318d78a 5022 * If CCK != 1M then set short preamble rate flag.
b481de9c 5023 */
bb8c093b 5024 rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
8318d78a 5025 0 : IEEE80211_RATE_SHORT_PREAMBLE;
b481de9c 5026 }
b481de9c
ZY		 5027 }
5028}
5029
5030/**
bb8c093b 5031 * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
b481de9c 5032 */
bb8c093b 5033static int iwl3945_init_geos(struct iwl3945_priv *priv)
b481de9c 5034{
bb8c093b 5035 struct iwl3945_channel_info *ch;
8211ef78 5036 struct ieee80211_supported_band *sband;
b481de9c
ZY		 5037 struct ieee80211_channel *channels;
5038 struct ieee80211_channel *geo_ch;
5039 struct ieee80211_rate *rates;
5040 int i = 0;
b481de9c 5041
8318d78a
JB		 5042 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
5043 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
b481de9c
ZY		 5044 IWL_DEBUG_INFO("Geography modes already initialized.\n");
5045 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
5046 return 0;
5047 }
5048
b481de9c
ZY		 5049 channels = kzalloc(sizeof(struct ieee80211_channel) *
5050 priv->channel_count, GFP_KERNEL);
8318d78a 5051 if (!channels)
b481de9c 5052 return -ENOMEM;
b481de9c 5053
8211ef78 5054 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
b481de9c
ZY		 5055 GFP_KERNEL);
5056 if (!rates) {
b481de9c
ZY		 5057 kfree(channels);
5058 return -ENOMEM;
5059 }
5060
b481de9c 5061 /* 5.2GHz channels start after the 2.4GHz channels */
8211ef78
TW		 5062 sband = &priv->bands[IEEE80211_BAND_5GHZ];
5063 sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
5064 /* just OFDM */
5065 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
5066 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
5067
5068 sband = &priv->bands[IEEE80211_BAND_2GHZ];
5069 sband->channels = channels;
5070 /* OFDM & CCK */
5071 sband->bitrates = rates;
5072 sband->n_bitrates = IWL_RATE_COUNT;
b481de9c
ZY		 5073
5074 priv->ieee_channels = channels;
5075 priv->ieee_rates = rates;
5076
bb8c093b 5077 iwl3945_init_hw_rates(priv, rates);
b481de9c 5078
8211ef78 5079 for (i = 0; i < priv->channel_count; i++) {
b481de9c
ZY		 5080 ch = &priv->channel_info[i];
5081
8211ef78
TW		 5082 /* FIXME: might be removed if scan is OK*/
5083 if (!is_channel_valid(ch))
b481de9c 5084 continue;
b481de9c
ZY		 5085
5086 if (is_channel_a_band(ch))
8211ef78 5087 sband = &priv->bands[IEEE80211_BAND_5GHZ];
8318d78a 5088 else
8211ef78 5089 sband = &priv->bands[IEEE80211_BAND_2GHZ];
b481de9c 5090
8211ef78
TW		 5091 geo_ch = &sband->channels[sband->n_channels++];
5092
5093 geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
8318d78a
JB		 5094 geo_ch->max_power = ch->max_power_avg;
5095 geo_ch->max_antenna_gain = 0xff;
7b72304d 5096 geo_ch->hw_value = ch->channel;
b481de9c
ZY		 5097
5098 if (is_channel_valid(ch)) {
8318d78a
JB		 5099 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
5100 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
b481de9c 5101
8318d78a
JB		 5102 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
5103 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
b481de9c
ZY		 5104
5105 if (ch->flags & EEPROM_CHANNEL_RADAR)
8318d78a 5106 geo_ch->flags |= IEEE80211_CHAN_RADAR;
b481de9c
ZY		 5107
5108 if (ch->max_power_avg > priv->max_channel_txpower_limit)
5109 priv->max_channel_txpower_limit =
5110 ch->max_power_avg;
8211ef78 5111 } else {
8318d78a 5112 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
8211ef78
TW		 5113 }
5114
5115 /* Save flags for reg domain usage */
5116 geo_ch->orig_flags = geo_ch->flags;
5117
5118 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
5119 ch->channel, geo_ch->center_freq,
5120 is_channel_a_band(ch) ? "5.2" : "2.4",
5121 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
5122 "restricted" : "valid",
5123 geo_ch->flags);
b481de9c
ZY		 5124 }
5125
82b9a121
TW		 5126 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
5127 priv->cfg->sku & IWL_SKU_A) {
b481de9c
ZY		 5128 printk(KERN_INFO DRV_NAME
5129 ": Incorrectly detected BG card as ABG. Please send "
5130 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
5131 priv->pci_dev->device, priv->pci_dev->subsystem_device);
82b9a121 5132 priv->cfg->sku &= ~IWL_SKU_A;
b481de9c
ZY		 5133 }
5134
5135 printk(KERN_INFO DRV_NAME
5136 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
8318d78a
JB		 5137 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
5138 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
b481de9c 5139
e0e0a67e
JL		 5140 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
5141 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
5142 &priv->bands[IEEE80211_BAND_2GHZ];
5143 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
5144 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
5145 &priv->bands[IEEE80211_BAND_5GHZ];
b481de9c 5146
b481de9c
ZY		 5147 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
5148
5149 return 0;
5150}
5151
849e0dce
RC		 5152/*
5153 * iwl3945_free_geos - undo allocations in iwl3945_init_geos
5154 */
5155static void iwl3945_free_geos(struct iwl3945_priv *priv)
5156{
849e0dce
RC		 5157 kfree(priv->ieee_channels);
5158 kfree(priv->ieee_rates);
5159 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
5160}
5161
b481de9c
ZY		 5162/******************************************************************************
5163 *
5164 * uCode download functions
5165 *
5166 ******************************************************************************/
5167
bb8c093b 5168static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv)
b481de9c 5169{
98c92211
TW		 5170 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
5171 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
5172 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
5173 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
5174 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
5175 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY		 5176}
5177
5178/**
bb8c093b 5179 * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
b481de9c
ZY		 5180 * looking at all data.
5181 */
bb8c093b 5182static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 * image, u32 len)
b481de9c
ZY		 5183{
5184 u32 val;
5185 u32 save_len = len;
5186 int rc = 0;
5187 u32 errcnt;
5188
5189 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5190
bb8c093b 5191 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5192 if (rc)
5193 return rc;
5194
bb8c093b 5195 iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
b481de9c
ZY		 5196
5197 errcnt = 0;
5198 for (; len > 0; len -= sizeof(u32), image++) {
5199 /* read data comes through single port, auto-incr addr */
5200 /* NOTE: Use the debugless read so we don't flood kernel log
5201 * if IWL_DL_IO is set */
bb8c093b 5202 val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY		 5203 if (val != le32_to_cpu(*image)) {
5204 IWL_ERROR("uCode INST section is invalid at "
5205 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5206 save_len - len, val, le32_to_cpu(*image));
5207 rc = -EIO;
5208 errcnt++;
5209 if (errcnt >= 20)
5210 break;
5211 }
5212 }
5213
bb8c093b 5214 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5215
5216 if (!errcnt)
bc434dd2 5217 IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
b481de9c
ZY		 5218
5219 return rc;
5220}
5221
5222
5223/**
bb8c093b 5224 * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
b481de9c
ZY		 5225 * using sample data 100 bytes apart. If these sample points are good,
5226 * it's a pretty good bet that everything between them is good, too.
5227 */
bb8c093b 5228static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len)
b481de9c
ZY		 5229{
5230 u32 val;
5231 int rc = 0;
5232 u32 errcnt = 0;
5233 u32 i;
5234
5235 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5236
bb8c093b 5237 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5238 if (rc)
5239 return rc;
5240
5241 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
5242 /* read data comes through single port, auto-incr addr */
5243 /* NOTE: Use the debugless read so we don't flood kernel log
5244 * if IWL_DL_IO is set */
bb8c093b 5245 iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
b481de9c 5246 i + RTC_INST_LOWER_BOUND);
bb8c093b 5247 val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY		 5248 if (val != le32_to_cpu(*image)) {
5249#if 0 /* Enable this if you want to see details */
5250 IWL_ERROR("uCode INST section is invalid at "
5251 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5252 i, val, *image);
5253#endif
5254 rc = -EIO;
5255 errcnt++;
5256 if (errcnt >= 3)
5257 break;
5258 }
5259 }
5260
bb8c093b 5261 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5262
5263 return rc;
5264}
5265
5266
5267/**
bb8c093b 5268 * iwl3945_verify_ucode - determine which instruction image is in SRAM,
b481de9c
ZY		 5269 * and verify its contents
5270 */
bb8c093b 5271static int iwl3945_verify_ucode(struct iwl3945_priv *priv)
b481de9c
ZY		 5272{
5273 __le32 *image;
5274 u32 len;
5275 int rc = 0;
5276
5277 /* Try bootstrap */
5278 image = (__le32 *)priv->ucode_boot.v_addr;
5279 len = priv->ucode_boot.len;
bb8c093b 5280 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5281 if (rc == 0) {
5282 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
5283 return 0;
5284 }
5285
5286 /* Try initialize */
5287 image = (__le32 *)priv->ucode_init.v_addr;
5288 len = priv->ucode_init.len;
bb8c093b 5289 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5290 if (rc == 0) {
5291 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
5292 return 0;
5293 }
5294
5295 /* Try runtime/protocol */
5296 image = (__le32 *)priv->ucode_code.v_addr;
5297 len = priv->ucode_code.len;
bb8c093b 5298 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5299 if (rc == 0) {
5300 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
5301 return 0;
5302 }
5303
5304 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
5305
9fbab516
BC		 5306 /* Since nothing seems to match, show first several data entries in
5307 * instruction SRAM, so maybe visual inspection will give a clue.
5308 * Selection of bootstrap image (vs. other images) is arbitrary. */
b481de9c
ZY		 5309 image = (__le32 *)priv->ucode_boot.v_addr;
5310 len = priv->ucode_boot.len;
bb8c093b 5311 rc = iwl3945_verify_inst_full(priv, image, len);
b481de9c
ZY		 5312
5313 return rc;
5314}
5315
5316
5317/* check contents of special bootstrap uCode SRAM */
bb8c093b 5318static int iwl3945_verify_bsm(struct iwl3945_priv *priv)
b481de9c
ZY		 5319{
5320 __le32 *image = priv->ucode_boot.v_addr;
5321 u32 len = priv->ucode_boot.len;
5322 u32 reg;
5323 u32 val;
5324
5325 IWL_DEBUG_INFO("Begin verify bsm\n");
5326
5327 /* verify BSM SRAM contents */
bb8c093b 5328 val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG);
b481de9c
ZY		 5329 for (reg = BSM_SRAM_LOWER_BOUND;
5330 reg < BSM_SRAM_LOWER_BOUND + len;
5331 reg += sizeof(u32), image ++) {
bb8c093b 5332 val = iwl3945_read_prph(priv, reg);
b481de9c
ZY		 5333 if (val != le32_to_cpu(*image)) {
5334 IWL_ERROR("BSM uCode verification failed at "
5335 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
5336 BSM_SRAM_LOWER_BOUND,
5337 reg - BSM_SRAM_LOWER_BOUND, len,
5338 val, le32_to_cpu(*image));
5339 return -EIO;
5340 }
5341 }
5342
5343 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
5344
5345 return 0;
5346}
5347
5348/**
bb8c093b 5349 * iwl3945_load_bsm - Load bootstrap instructions
b481de9c
ZY		 5350 *
5351 * BSM operation:
5352 *
5353 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
5354 * in special SRAM that does not power down during RFKILL. When powering back
5355 * up after power-saving sleeps (or during initial uCode load), the BSM loads
5356 * the bootstrap program into the on-board processor, and starts it.
5357 *
5358 * The bootstrap program loads (via DMA) instructions and data for a new
5359 * program from host DRAM locations indicated by the host driver in the
5360 * BSM_DRAM_* registers. Once the new program is loaded, it starts
5361 * automatically.
5362 *
5363 * When initializing the NIC, the host driver points the BSM to the
5364 * "initialize" uCode image. This uCode sets up some internal data, then
5365 * notifies host via "initialize alive" that it is complete.
5366 *
5367 * The host then replaces the BSM_DRAM_* pointer values to point to the
5368 * normal runtime uCode instructions and a backup uCode data cache buffer
5369 * (filled initially with starting data values for the on-board processor),
5370 * then triggers the "initialize" uCode to load and launch the runtime uCode,
5371 * which begins normal operation.
5372 *
5373 * When doing a power-save shutdown, runtime uCode saves data SRAM into
5374 * the backup data cache in DRAM before SRAM is powered down.
5375 *
5376 * When powering back up, the BSM loads the bootstrap program. This reloads
5377 * the runtime uCode instructions and the backup data cache into SRAM,
5378 * and re-launches the runtime uCode from where it left off.
5379 */
bb8c093b 5380static int iwl3945_load_bsm(struct iwl3945_priv *priv)
b481de9c
ZY		 5381{
5382 __le32 *image = priv->ucode_boot.v_addr;
5383 u32 len = priv->ucode_boot.len;
5384 dma_addr_t pinst;
5385 dma_addr_t pdata;
5386 u32 inst_len;
5387 u32 data_len;
5388 int rc;
5389 int i;
5390 u32 done;
5391 u32 reg_offset;
5392
5393 IWL_DEBUG_INFO("Begin load bsm\n");
5394
5395 /* make sure bootstrap program is no larger than BSM's SRAM size */
5396 if (len > IWL_MAX_BSM_SIZE)
5397 return -EINVAL;
5398
5399 /* Tell bootstrap uCode where to find the "Initialize" uCode
9fbab516 5400 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
bb8c093b 5401 * NOTE: iwl3945_initialize_alive_start() will replace these values,
b481de9c
ZY		 5402 * after the "initialize" uCode has run, to point to
5403 * runtime/protocol instructions and backup data cache. */
5404 pinst = priv->ucode_init.p_addr;
5405 pdata = priv->ucode_init_data.p_addr;
5406 inst_len = priv->ucode_init.len;
5407 data_len = priv->ucode_init_data.len;
5408
bb8c093b 5409 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5410 if (rc)
5411 return rc;
5412
bb8c093b
CH		 5413 iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5414 iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5415 iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
5416 iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
b481de9c
ZY		 5417
5418 /* Fill BSM memory with bootstrap instructions */
5419 for (reg_offset = BSM_SRAM_LOWER_BOUND;
5420 reg_offset < BSM_SRAM_LOWER_BOUND + len;
5421 reg_offset += sizeof(u32), image++)
bb8c093b 5422 _iwl3945_write_prph(priv, reg_offset,
b481de9c
ZY		 5423 le32_to_cpu(*image));
5424
bb8c093b 5425 rc = iwl3945_verify_bsm(priv);
b481de9c 5426 if (rc) {
bb8c093b 5427 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5428 return rc;
5429 }
5430
5431 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
bb8c093b
CH		 5432 iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
5433 iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG,
b481de9c 5434 RTC_INST_LOWER_BOUND);
bb8c093b 5435 iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
b481de9c
ZY		 5436
5437 /* Load bootstrap code into instruction SRAM now,
5438 * to prepare to load "initialize" uCode */
bb8c093b 5439 iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY		 5440 BSM_WR_CTRL_REG_BIT_START);
5441
5442 /* Wait for load of bootstrap uCode to finish */
5443 for (i = 0; i < 100; i++) {
bb8c093b 5444 done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG);
b481de9c
ZY		 5445 if (!(done & BSM_WR_CTRL_REG_BIT_START))
5446 break;
5447 udelay(10);
5448 }
5449 if (i < 100)
5450 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
5451 else {
5452 IWL_ERROR("BSM write did not complete!\n");
5453 return -EIO;
5454 }
5455
5456 /* Enable future boot loads whenever power management unit triggers it
5457 * (e.g. when powering back up after power-save shutdown) */
bb8c093b 5458 iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY		 5459 BSM_WR_CTRL_REG_BIT_START_EN);
5460
bb8c093b 5461 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5462
5463 return 0;
5464}
5465
bb8c093b 5466static void iwl3945_nic_start(struct iwl3945_priv *priv)
b481de9c
ZY		 5467{
5468 /* Remove all resets to allow NIC to operate */
bb8c093b 5469 iwl3945_write32(priv, CSR_RESET, 0);
b481de9c
ZY		 5470}
5471
5472/**
bb8c093b 5473 * iwl3945_read_ucode - Read uCode images from disk file.
b481de9c
ZY		 5474 *
5475 * Copy into buffers for card to fetch via bus-mastering
5476 */
bb8c093b 5477static int iwl3945_read_ucode(struct iwl3945_priv *priv)
b481de9c 5478{
bb8c093b 5479 struct iwl3945_ucode *ucode;
90e759d1 5480 int ret = 0;
b481de9c
ZY		 5481 const struct firmware *ucode_raw;
5482 /* firmware file name contains uCode/driver compatibility version */
4bf775cd 5483 const char *name = priv->cfg->fw_name;
b481de9c
ZY		 5484 u8 *src;
5485 size_t len;
5486 u32 ver, inst_size, data_size, init_size, init_data_size, boot_size;
5487
5488 /* Ask kernel firmware_class module to get the boot firmware off disk.
5489 * request_firmware() is synchronous, file is in memory on return. */
90e759d1
TW		 5490 ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev);
5491 if (ret < 0) {
5492 IWL_ERROR("%s firmware file req failed: Reason %d\n",
5493 name, ret);
b481de9c
ZY		 5494 goto error;
5495 }
5496
5497 IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
5498 name, ucode_raw->size);
5499
5500 /* Make sure that we got at least our header! */
5501 if (ucode_raw->size < sizeof(*ucode)) {
5502 IWL_ERROR("File size way too small!\n");
90e759d1 5503 ret = -EINVAL;
b481de9c
ZY		 5504 goto err_release;
5505 }
5506
5507 /* Data from ucode file: header followed by uCode images */
5508 ucode = (void *)ucode_raw->data;
5509
5510 ver = le32_to_cpu(ucode->ver);
5511 inst_size = le32_to_cpu(ucode->inst_size);
5512 data_size = le32_to_cpu(ucode->data_size);
5513 init_size = le32_to_cpu(ucode->init_size);
5514 init_data_size = le32_to_cpu(ucode->init_data_size);
5515 boot_size = le32_to_cpu(ucode->boot_size);
5516
5517 IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver);
bc434dd2
IS		 5518 IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
5519 IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
5520 IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
5521 IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
5522 IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
b481de9c
ZY		 5523
5524 /* Verify size of file vs. image size info in file's header */
5525 if (ucode_raw->size < sizeof(*ucode) +
5526 inst_size + data_size + init_size +
5527 init_data_size + boot_size) {
5528
5529 IWL_DEBUG_INFO("uCode file size %d too small\n",
5530 (int)ucode_raw->size);
90e759d1 5531 ret = -EINVAL;
b481de9c
ZY		 5532 goto err_release;
5533 }
5534
5535 /* Verify that uCode images will fit in card's SRAM */
5536 if (inst_size > IWL_MAX_INST_SIZE) {
90e759d1
TW		 5537 IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
5538 inst_size);
5539 ret = -EINVAL;
b481de9c
ZY		 5540 goto err_release;
5541 }
5542
5543 if (data_size > IWL_MAX_DATA_SIZE) {
90e759d1
TW		 5544 IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
5545 data_size);
5546 ret = -EINVAL;
b481de9c
ZY		 5547 goto err_release;
5548 }
5549 if (init_size > IWL_MAX_INST_SIZE) {
90e759d1
TW		 5550 IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
5551 init_size);
5552 ret = -EINVAL;
b481de9c
ZY		 5553 goto err_release;
5554 }
5555 if (init_data_size > IWL_MAX_DATA_SIZE) {
90e759d1
TW		 5556 IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
5557 init_data_size);
5558 ret = -EINVAL;
b481de9c
ZY		 5559 goto err_release;
5560 }
5561 if (boot_size > IWL_MAX_BSM_SIZE) {
90e759d1
TW		 5562 IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
5563 boot_size);
5564 ret = -EINVAL;
b481de9c
ZY		 5565 goto err_release;
5566 }
5567
5568 /* Allocate ucode buffers for card's bus-master loading ... */
5569
5570 /* Runtime instructions and 2 copies of data:
5571 * 1) unmodified from disk
5572 * 2) backup cache for save/restore during power-downs */
5573 priv->ucode_code.len = inst_size;
98c92211 5574 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY		 5575
5576 priv->ucode_data.len = data_size;
98c92211 5577 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY		 5578
5579 priv->ucode_data_backup.len = data_size;
98c92211 5580 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 5581
90e759d1
TW		 5582 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
5583 !priv->ucode_data_backup.v_addr)
5584 goto err_pci_alloc;
b481de9c
ZY		 5585
5586 /* Initialization instructions and data */
90e759d1
TW		 5587 if (init_size && init_data_size) {
5588 priv->ucode_init.len = init_size;
98c92211 5589 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW		 5590
5591 priv->ucode_init_data.len = init_data_size;
98c92211 5592 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW		 5593
5594 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
5595 goto err_pci_alloc;
5596 }
b481de9c
ZY		 5597
5598 /* Bootstrap (instructions only, no data) */
90e759d1
TW		 5599 if (boot_size) {
5600 priv->ucode_boot.len = boot_size;
98c92211 5601 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 5602
90e759d1
TW		 5603 if (!priv->ucode_boot.v_addr)
5604 goto err_pci_alloc;
5605 }
b481de9c
ZY		 5606
5607 /* Copy images into buffers for card's bus-master reads ... */
5608
5609 /* Runtime instructions (first block of data in file) */
5610 src = &ucode->data[0];
5611 len = priv->ucode_code.len;
90e759d1 5612 IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c
ZY		 5613 memcpy(priv->ucode_code.v_addr, src, len);
5614 IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
5615 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
5616
5617 /* Runtime data (2nd block)
bb8c093b 5618 * NOTE: Copy into backup buffer will be done in iwl3945_up() */
b481de9c
ZY		 5619 src = &ucode->data[inst_size];
5620 len = priv->ucode_data.len;
90e759d1 5621 IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY		 5622 memcpy(priv->ucode_data.v_addr, src, len);
5623 memcpy(priv->ucode_data_backup.v_addr, src, len);
5624
5625 /* Initialization instructions (3rd block) */
5626 if (init_size) {
5627 src = &ucode->data[inst_size + data_size];
5628 len = priv->ucode_init.len;
90e759d1
TW		 5629 IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
5630 len);
b481de9c
ZY		 5631 memcpy(priv->ucode_init.v_addr, src, len);
5632 }
5633
5634 /* Initialization data (4th block) */
5635 if (init_data_size) {
5636 src = &ucode->data[inst_size + data_size + init_size];
5637 len = priv->ucode_init_data.len;
5638 IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
5639 (int)len);
5640 memcpy(priv->ucode_init_data.v_addr, src, len);
5641 }
5642
5643 /* Bootstrap instructions (5th block) */
5644 src = &ucode->data[inst_size + data_size + init_size + init_data_size];
5645 len = priv->ucode_boot.len;
5646 IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
5647 (int)len);
5648 memcpy(priv->ucode_boot.v_addr, src, len);
5649
5650 /* We have our copies now, allow OS release its copies */
5651 release_firmware(ucode_raw);
5652 return 0;
5653
5654 err_pci_alloc:
5655 IWL_ERROR("failed to allocate pci memory\n");
90e759d1 5656 ret = -ENOMEM;
bb8c093b 5657 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY		 5658
5659 err_release:
5660 release_firmware(ucode_raw);
5661
5662 error:
90e759d1 5663 return ret;
b481de9c
ZY		 5664}
5665
5666
5667/**
bb8c093b 5668 * iwl3945_set_ucode_ptrs - Set uCode address location
b481de9c
ZY		 5669 *
5670 * Tell initialization uCode where to find runtime uCode.
5671 *
5672 * BSM registers initially contain pointers to initialization uCode.
5673 * We need to replace them to load runtime uCode inst and data,
5674 * and to save runtime data when powering down.
5675 */
bb8c093b 5676static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv)
b481de9c
ZY		 5677{
5678 dma_addr_t pinst;
5679 dma_addr_t pdata;
5680 int rc = 0;
5681 unsigned long flags;
5682
5683 /* bits 31:0 for 3945 */
5684 pinst = priv->ucode_code.p_addr;
5685 pdata = priv->ucode_data_backup.p_addr;
5686
5687 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5688 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5689 if (rc) {
5690 spin_unlock_irqrestore(&priv->lock, flags);
5691 return rc;
5692 }
5693
5694 /* Tell bootstrap uCode where to find image to load */
bb8c093b
CH		 5695 iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5696 iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5697 iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
b481de9c
ZY		 5698 priv->ucode_data.len);
5699
5700 /* Inst bytecount must be last to set up, bit 31 signals uCode
5701 * that all new ptr/size info is in place */
bb8c093b 5702 iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
b481de9c
ZY		 5703 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
5704
bb8c093b 5705 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5706
5707 spin_unlock_irqrestore(&priv->lock, flags);
5708
5709 IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
5710
5711 return rc;
5712}
5713
5714/**
bb8c093b 5715 * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
b481de9c
ZY		 5716 *
5717 * Called after REPLY_ALIVE notification received from "initialize" uCode.
5718 *
b481de9c 5719 * Tell "initialize" uCode to go ahead and load the runtime uCode.
9fbab516 5720 */
bb8c093b 5721static void iwl3945_init_alive_start(struct iwl3945_priv *priv)
b481de9c
ZY		 5722{
5723 /* Check alive response for "valid" sign from uCode */
5724 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
5725 /* We had an error bringing up the hardware, so take it
5726 * all the way back down so we can try again */
5727 IWL_DEBUG_INFO("Initialize Alive failed.\n");
5728 goto restart;
5729 }
5730
5731 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
5732 * This is a paranoid check, because we would not have gotten the
5733 * "initialize" alive if code weren't properly loaded. */
bb8c093b 5734 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY		 5735 /* Runtime instruction load was bad;
5736 * take it all the way back down so we can try again */
5737 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
5738 goto restart;
5739 }
5740
5741 /* Send pointers to protocol/runtime uCode image ... init code will
5742 * load and launch runtime uCode, which will send us another "Alive"
5743 * notification. */
5744 IWL_DEBUG_INFO("Initialization Alive received.\n");
bb8c093b 5745 if (iwl3945_set_ucode_ptrs(priv)) {
b481de9c
ZY		 5746 /* Runtime instruction load won't happen;
5747 * take it all the way back down so we can try again */
5748 IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
5749 goto restart;
5750 }
5751 return;
5752
5753 restart:
5754 queue_work(priv->workqueue, &priv->restart);
5755}
5756
5757
5758/**
bb8c093b 5759 * iwl3945_alive_start - called after REPLY_ALIVE notification received
b481de9c 5760 * from protocol/runtime uCode (initialization uCode's
bb8c093b 5761 * Alive gets handled by iwl3945_init_alive_start()).
b481de9c 5762 */
bb8c093b 5763static void iwl3945_alive_start(struct iwl3945_priv *priv)
b481de9c
ZY		 5764{
5765 int rc = 0;
5766 int thermal_spin = 0;
5767 u32 rfkill;
5768
5769 IWL_DEBUG_INFO("Runtime Alive received.\n");
5770
5771 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
5772 /* We had an error bringing up the hardware, so take it
5773 * all the way back down so we can try again */
5774 IWL_DEBUG_INFO("Alive failed.\n");
5775 goto restart;
5776 }
5777
5778 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
5779 * This is a paranoid check, because we would not have gotten the
5780 * "runtime" alive if code weren't properly loaded. */
bb8c093b 5781 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY		 5782 /* Runtime instruction load was bad;
5783 * take it all the way back down so we can try again */
5784 IWL_DEBUG_INFO("Bad runtime uCode load.\n");
5785 goto restart;
5786 }
5787
bb8c093b 5788 iwl3945_clear_stations_table(priv);
b481de9c 5789
bb8c093b 5790 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5791 if (rc) {
5792 IWL_WARNING("Can not read rfkill status from adapter\n");
5793 return;
5794 }
5795
bb8c093b 5796 rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG);
b481de9c 5797 IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
bb8c093b 5798 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5799
5800 if (rfkill & 0x1) {
5801 clear_bit(STATUS_RF_KILL_HW, &priv->status);
5802 /* if rfkill is not on, then wait for thermal
5803 * sensor in adapter to kick in */
bb8c093b 5804 while (iwl3945_hw_get_temperature(priv) == 0) {
b481de9c
ZY		 5805 thermal_spin++;
5806 udelay(10);
5807 }
5808
5809 if (thermal_spin)
5810 IWL_DEBUG_INFO("Thermal calibration took %dus\n",
5811 thermal_spin * 10);
5812 } else
5813 set_bit(STATUS_RF_KILL_HW, &priv->status);
5814
9fbab516 5815 /* After the ALIVE response, we can send commands to 3945 uCode */
b481de9c
ZY		 5816 set_bit(STATUS_ALIVE, &priv->status);
5817
5818 /* Clear out the uCode error bit if it is set */
5819 clear_bit(STATUS_FW_ERROR, &priv->status);
5820
bb8c093b 5821 if (iwl3945_is_rfkill(priv))
b481de9c
ZY		 5822 return;
5823
36d6825b 5824 ieee80211_wake_queues(priv->hw);
b481de9c
ZY		 5825
5826 priv->active_rate = priv->rates_mask;
5827 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
5828
bb8c093b 5829 iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
b481de9c 5830
bb8c093b
CH		 5831 if (iwl3945_is_associated(priv)) {
5832 struct iwl3945_rxon_cmd *active_rxon =
5833 (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
b481de9c
ZY		 5834
5835 memcpy(&priv->staging_rxon, &priv->active_rxon,
5836 sizeof(priv->staging_rxon));
5837 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5838 } else {
5839 /* Initialize our rx_config data */
bb8c093b 5840 iwl3945_connection_init_rx_config(priv);
b481de9c
ZY		 5841 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
5842 }
5843
9fbab516 5844 /* Configure Bluetooth device coexistence support */
bb8c093b 5845 iwl3945_send_bt_config(priv);
b481de9c
ZY		 5846
5847 /* Configure the adapter for unassociated operation */
bb8c093b 5848 iwl3945_commit_rxon(priv);
b481de9c
ZY		 5849
5850 /* At this point, the NIC is initialized and operational */
5851 priv->notif_missed_beacons = 0;
b481de9c
ZY		 5852
5853 iwl3945_reg_txpower_periodic(priv);
5854
fe00b5a5
RC		 5855 iwl3945_led_register(priv);
5856
b481de9c 5857 IWL_DEBUG_INFO("ALIVE processing complete.\n");
a9f46786 5858 set_bit(STATUS_READY, &priv->status);
5a66926a 5859 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY		 5860
5861 if (priv->error_recovering)
bb8c093b 5862 iwl3945_error_recovery(priv);
b481de9c 5863
84363e6e 5864 ieee80211_notify_mac(priv->hw, IEEE80211_NOTIFY_RE_ASSOC);
b481de9c
ZY		 5865 return;
5866
5867 restart:
5868 queue_work(priv->workqueue, &priv->restart);
5869}
5870
bb8c093b 5871static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv);
b481de9c 5872
bb8c093b 5873static void __iwl3945_down(struct iwl3945_priv *priv)
b481de9c
ZY		 5874{
5875 unsigned long flags;
5876 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
5877 struct ieee80211_conf *conf = NULL;
5878
5879 IWL_DEBUG_INFO(DRV_NAME " is going down\n");
5880
5881 conf = ieee80211_get_hw_conf(priv->hw);
5882
5883 if (!exit_pending)
5884 set_bit(STATUS_EXIT_PENDING, &priv->status);
5885
ab53d8af 5886 iwl3945_led_unregister(priv);
bb8c093b 5887 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 5888
5889 /* Unblock any waiting calls */
5890 wake_up_interruptible_all(&priv->wait_command_queue);
5891
b481de9c
ZY		 5892 /* Wipe out the EXIT_PENDING status bit if we are not actually
5893 * exiting the module */
5894 if (!exit_pending)
5895 clear_bit(STATUS_EXIT_PENDING, &priv->status);
5896
5897 /* stop and reset the on-board processor */
bb8c093b 5898 iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY		 5899
5900 /* tell the device to stop sending interrupts */
0359facc 5901 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5902 iwl3945_disable_interrupts(priv);
0359facc
MA		 5903 spin_unlock_irqrestore(&priv->lock, flags);
5904 iwl_synchronize_irq(priv);
b481de9c
ZY		 5905
5906 if (priv->mac80211_registered)
5907 ieee80211_stop_queues(priv->hw);
5908
bb8c093b 5909 /* If we have not previously called iwl3945_init() then
b481de9c 5910 * clear all bits but the RF Kill and SUSPEND bits and return */
bb8c093b 5911 if (!iwl3945_is_init(priv)) {
b481de9c
ZY		 5912 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
5913 STATUS_RF_KILL_HW |
5914 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
5915 STATUS_RF_KILL_SW |
9788864e
RC		 5916 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
5917 STATUS_GEO_CONFIGURED |
b481de9c
ZY		 5918 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
5919 STATUS_IN_SUSPEND;
5920 goto exit;
5921 }
5922
5923 /* ...otherwise clear out all the status bits but the RF Kill and
5924 * SUSPEND bits and continue taking the NIC down. */
5925 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
5926 STATUS_RF_KILL_HW |
5927 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
5928 STATUS_RF_KILL_SW |
9788864e
RC		 5929 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
5930 STATUS_GEO_CONFIGURED |
b481de9c
ZY		 5931 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
5932 STATUS_IN_SUSPEND |
5933 test_bit(STATUS_FW_ERROR, &priv->status) <<
5934 STATUS_FW_ERROR;
5935
5936 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5937 iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY		 5938 spin_unlock_irqrestore(&priv->lock, flags);
5939
bb8c093b
CH		 5940 iwl3945_hw_txq_ctx_stop(priv);
5941 iwl3945_hw_rxq_stop(priv);
b481de9c
ZY		 5942
5943 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH		 5944 if (!iwl3945_grab_nic_access(priv)) {
5945 iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
b481de9c 5946 APMG_CLK_VAL_DMA_CLK_RQT);
bb8c093b 5947 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5948 }
5949 spin_unlock_irqrestore(&priv->lock, flags);
5950
5951 udelay(5);
5952
bb8c093b
CH		 5953 iwl3945_hw_nic_stop_master(priv);
5954 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
5955 iwl3945_hw_nic_reset(priv);
b481de9c
ZY		 5956
5957 exit:
bb8c093b 5958 memset(&priv->card_alive, 0, sizeof(struct iwl3945_alive_resp));
b481de9c
ZY		 5959
5960 if (priv->ibss_beacon)
5961 dev_kfree_skb(priv->ibss_beacon);
5962 priv->ibss_beacon = NULL;
5963
5964 /* clear out any free frames */
bb8c093b 5965 iwl3945_clear_free_frames(priv);
b481de9c
ZY		 5966}
5967
bb8c093b 5968static void iwl3945_down(struct iwl3945_priv *priv)
b481de9c
ZY		 5969{
5970 mutex_lock(&priv->mutex);
bb8c093b 5971 __iwl3945_down(priv);
b481de9c 5972 mutex_unlock(&priv->mutex);
b24d22b1 5973
bb8c093b 5974 iwl3945_cancel_deferred_work(priv);
b481de9c
ZY		 5975}
5976
5977#define MAX_HW_RESTARTS 5
5978
bb8c093b 5979static int __iwl3945_up(struct iwl3945_priv *priv)
b481de9c
ZY		 5980{
5981 int rc, i;
5982
5983 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
5984 IWL_WARNING("Exit pending; will not bring the NIC up\n");
5985 return -EIO;
5986 }
5987
5988 if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
5989 IWL_WARNING("Radio disabled by SW RF kill (module "
5990 "parameter)\n");
e655b9f0
ZY		 5991 return -ENODEV;
5992 }
5993
e903fbd4
RC		 5994 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
5995 IWL_ERROR("ucode not available for device bringup\n");
5996 return -EIO;
5997 }
5998
e655b9f0
ZY		 5999 /* If platform's RF_KILL switch is NOT set to KILL */
6000 if (iwl3945_read32(priv, CSR_GP_CNTRL) &
6001 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
6002 clear_bit(STATUS_RF_KILL_HW, &priv->status);
6003 else {
6004 set_bit(STATUS_RF_KILL_HW, &priv->status);
6005 if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
6006 IWL_WARNING("Radio disabled by HW RF Kill switch\n");
6007 return -ENODEV;
6008 }
b481de9c
ZY		 6009 }
6010
bb8c093b 6011 iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 6012
bb8c093b 6013 rc = iwl3945_hw_nic_init(priv);
b481de9c
ZY		 6014 if (rc) {
6015 IWL_ERROR("Unable to int nic\n");
6016 return rc;
6017 }
6018
6019 /* make sure rfkill handshake bits are cleared */
bb8c093b
CH		 6020 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
6021 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 6022 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
6023
6024 /* clear (again), then enable host interrupts */
bb8c093b
CH		 6025 iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
6026 iwl3945_enable_interrupts(priv);
b481de9c
ZY		 6027
6028 /* really make sure rfkill handshake bits are cleared */
bb8c093b
CH		 6029 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
6030 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 6031
6032 /* Copy original ucode data image from disk into backup cache.
6033 * This will be used to initialize the on-board processor's
6034 * data SRAM for a clean start when the runtime program first loads. */
6035 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 6036 priv->ucode_data.len);
b481de9c 6037
e655b9f0
ZY		 6038 /* We return success when we resume from suspend and rf_kill is on. */
6039 if (test_bit(STATUS_RF_KILL_HW, &priv->status))
6040 return 0;
6041
b481de9c
ZY		 6042 for (i = 0; i < MAX_HW_RESTARTS; i++) {
6043
bb8c093b 6044 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 6045
6046 /* load bootstrap state machine,
6047 * load bootstrap program into processor's memory,
6048 * prepare to load the "initialize" uCode */
bb8c093b 6049 rc = iwl3945_load_bsm(priv);
b481de9c
ZY		 6050
6051 if (rc) {
6052 IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
6053 continue;
6054 }
6055
6056 /* start card; "initialize" will load runtime ucode */
bb8c093b 6057 iwl3945_nic_start(priv);
b481de9c 6058
b481de9c
ZY		 6059 IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
6060
6061 return 0;
6062 }
6063
6064 set_bit(STATUS_EXIT_PENDING, &priv->status);
bb8c093b 6065 __iwl3945_down(priv);
b481de9c
ZY		 6066
6067 /* tried to restart and config the device for as long as our
6068 * patience could withstand */
6069 IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
6070 return -EIO;
6071}
6072
6073
6074/*****************************************************************************
6075 *
6076 * Workqueue callbacks
6077 *
6078 *****************************************************************************/
6079
bb8c093b 6080static void iwl3945_bg_init_alive_start(struct work_struct *data)
b481de9c 6081{
bb8c093b
CH		 6082 struct iwl3945_priv *priv =
6083 container_of(data, struct iwl3945_priv, init_alive_start.work);
b481de9c
ZY		 6084
6085 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6086 return;
6087
6088 mutex_lock(&priv->mutex);
bb8c093b 6089 iwl3945_init_alive_start(priv);
b481de9c
ZY		 6090 mutex_unlock(&priv->mutex);
6091}
6092
bb8c093b 6093static void iwl3945_bg_alive_start(struct work_struct *data)
b481de9c 6094{
bb8c093b
CH		 6095 struct iwl3945_priv *priv =
6096 container_of(data, struct iwl3945_priv, alive_start.work);
b481de9c
ZY		 6097
6098 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6099 return;
6100
6101 mutex_lock(&priv->mutex);
bb8c093b 6102 iwl3945_alive_start(priv);
b481de9c
ZY		 6103 mutex_unlock(&priv->mutex);
6104}
6105
bb8c093b 6106static void iwl3945_bg_rf_kill(struct work_struct *work)
b481de9c 6107{
bb8c093b 6108 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill);
b481de9c
ZY		 6109
6110 wake_up_interruptible(&priv->wait_command_queue);
6111
6112 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6113 return;
6114
6115 mutex_lock(&priv->mutex);
6116
bb8c093b 6117 if (!iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 6118 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
6119 "HW and/or SW RF Kill no longer active, restarting "
6120 "device\n");
6121 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
6122 queue_work(priv->workqueue, &priv->restart);
6123 } else {
6124
6125 if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
6126 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
6127 "disabled by SW switch\n");
6128 else
6129 IWL_WARNING("Radio Frequency Kill Switch is On:\n"
6130 "Kill switch must be turned off for "
6131 "wireless networking to work.\n");
6132 }
6133 mutex_unlock(&priv->mutex);
6134}
6135
5ec03976
AK		 6136static void iwl3945_bg_set_monitor(struct work_struct *work)
6137{
6138 struct iwl3945_priv *priv = container_of(work,
6139 struct iwl3945_priv, set_monitor);
6140
6141 IWL_DEBUG(IWL_DL_STATE, "setting monitor mode\n");
6142
6143 mutex_lock(&priv->mutex);
6144
6145 if (!iwl3945_is_ready(priv))
6146 IWL_DEBUG(IWL_DL_STATE, "leave - not ready\n");
6147 else
6148 if (iwl3945_set_mode(priv, IEEE80211_IF_TYPE_MNTR) != 0)
6149 IWL_ERROR("iwl3945_set_mode() failed\n");
6150
6151 mutex_unlock(&priv->mutex);
6152}
6153
b481de9c
ZY		 6154#define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
6155
bb8c093b 6156static void iwl3945_bg_scan_check(struct work_struct *data)
b481de9c 6157{
bb8c093b
CH		 6158 struct iwl3945_priv *priv =
6159 container_of(data, struct iwl3945_priv, scan_check.work);
b481de9c
ZY		 6160
6161 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6162 return;
6163
6164 mutex_lock(&priv->mutex);
6165 if (test_bit(STATUS_SCANNING, &priv->status) ||
6166 test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6167 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
6168 "Scan completion watchdog resetting adapter (%dms)\n",
6169 jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
15e869d8 6170
b481de9c 6171 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
bb8c093b 6172 iwl3945_send_scan_abort(priv);
b481de9c
ZY		 6173 }
6174 mutex_unlock(&priv->mutex);
6175}
6176
bb8c093b 6177static void iwl3945_bg_request_scan(struct work_struct *data)
b481de9c 6178{
bb8c093b
CH		 6179 struct iwl3945_priv *priv =
6180 container_of(data, struct iwl3945_priv, request_scan);
6181 struct iwl3945_host_cmd cmd = {
b481de9c 6182 .id = REPLY_SCAN_CMD,
bb8c093b 6183 .len = sizeof(struct iwl3945_scan_cmd),
b481de9c
ZY		 6184 .meta.flags = CMD_SIZE_HUGE,
6185 };
6186 int rc = 0;
bb8c093b 6187 struct iwl3945_scan_cmd *scan;
b481de9c
ZY		 6188 struct ieee80211_conf *conf = NULL;
6189 u8 direct_mask;
8318d78a 6190 enum ieee80211_band band;
b481de9c
ZY		 6191
6192 conf = ieee80211_get_hw_conf(priv->hw);
6193
6194 mutex_lock(&priv->mutex);
6195
bb8c093b 6196 if (!iwl3945_is_ready(priv)) {
b481de9c
ZY		 6197 IWL_WARNING("request scan called when driver not ready.\n");
6198 goto done;
6199 }
6200
6201 /* Make sure the scan wasn't cancelled before this queued work
6202 * was given the chance to run... */
6203 if (!test_bit(STATUS_SCANNING, &priv->status))
6204 goto done;
6205
6206 /* This should never be called or scheduled if there is currently
6207 * a scan active in the hardware. */
6208 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
6209 IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
6210 "Ignoring second request.\n");
6211 rc = -EIO;
6212 goto done;
6213 }
6214
6215 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
6216 IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
6217 goto done;
6218 }
6219
6220 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6221 IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
6222 goto done;
6223 }
6224
bb8c093b 6225 if (iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 6226 IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
6227 goto done;
6228 }
6229
6230 if (!test_bit(STATUS_READY, &priv->status)) {
6231 IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
6232 goto done;
6233 }
6234
6235 if (!priv->scan_bands) {
6236 IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
6237 goto done;
6238 }
6239
6240 if (!priv->scan) {
bb8c093b 6241 priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
b481de9c
ZY		 6242 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
6243 if (!priv->scan) {
6244 rc = -ENOMEM;
6245 goto done;
6246 }
6247 }
6248 scan = priv->scan;
bb8c093b 6249 memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
b481de9c
ZY		 6250
6251 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
6252 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
6253
bb8c093b 6254 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 6255 u16 interval = 0;
6256 u32 extra;
6257 u32 suspend_time = 100;
6258 u32 scan_suspend_time = 100;
6259 unsigned long flags;
6260
6261 IWL_DEBUG_INFO("Scanning while associated...\n");
6262
6263 spin_lock_irqsave(&priv->lock, flags);
6264 interval = priv->beacon_int;
6265 spin_unlock_irqrestore(&priv->lock, flags);
6266
6267 scan->suspend_time = 0;
15e869d8 6268 scan->max_out_time = cpu_to_le32(200 * 1024);
b481de9c
ZY		 6269 if (!interval)
6270 interval = suspend_time;
6271 /*
6272 * suspend time format:
6273 * 0-19: beacon interval in usec (time before exec.)
6274 * 20-23: 0
6275 * 24-31: number of beacons (suspend between channels)
6276 */
6277
6278 extra = (suspend_time / interval) << 24;
6279 scan_suspend_time = 0xFF0FFFFF &
6280 (extra | ((suspend_time % interval) * 1024));
6281
6282 scan->suspend_time = cpu_to_le32(scan_suspend_time);
6283 IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
6284 scan_suspend_time, interval);
6285 }
6286
6287 /* We should add the ability for user to lock to PASSIVE ONLY */
6288 if (priv->one_direct_scan) {
6289 IWL_DEBUG_SCAN
6290 ("Kicking off one direct scan for '%s'\n",
bb8c093b 6291 iwl3945_escape_essid(priv->direct_ssid,
b481de9c
ZY		 6292 priv->direct_ssid_len));
6293 scan->direct_scan[0].id = WLAN_EID_SSID;
6294 scan->direct_scan[0].len = priv->direct_ssid_len;
6295 memcpy(scan->direct_scan[0].ssid,
6296 priv->direct_ssid, priv->direct_ssid_len);
6297 direct_mask = 1;
bb8c093b 6298 } else if (!iwl3945_is_associated(priv) && priv->essid_len) {
786b4557
BM		 6299 IWL_DEBUG_SCAN
6300 ("Kicking off one direct scan for '%s' when not associated\n",
6301 iwl3945_escape_essid(priv->essid, priv->essid_len));
b481de9c
ZY		 6302 scan->direct_scan[0].id = WLAN_EID_SSID;
6303 scan->direct_scan[0].len = priv->essid_len;
6304 memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len);
6305 direct_mask = 1;
786b4557
BM		 6306 } else {
6307 IWL_DEBUG_SCAN("Kicking off one indirect scan.\n");
b481de9c 6308 direct_mask = 0;
786b4557 6309 }
b481de9c
ZY		 6310
6311 /* We don't build a direct scan probe request; the uCode will do
6312 * that based on the direct_mask added to each channel entry */
6313 scan->tx_cmd.len = cpu_to_le16(
bb8c093b 6314 iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
18904f58 6315 IWL_MAX_SCAN_SIZE - sizeof(*scan), 0));
b481de9c
ZY		 6316 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
6317 scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
6318 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
6319
6320 /* flags + rate selection */
6321
6322 switch (priv->scan_bands) {
6323 case 2:
6324 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
6325 scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
6326 scan->good_CRC_th = 0;
8318d78a 6327 band = IEEE80211_BAND_2GHZ;
b481de9c
ZY		 6328 break;
6329
6330 case 1:
6331 scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
6332 scan->good_CRC_th = IWL_GOOD_CRC_TH;
8318d78a 6333 band = IEEE80211_BAND_5GHZ;
b481de9c
ZY		 6334 break;
6335
6336 default:
6337 IWL_WARNING("Invalid scan band count\n");
6338 goto done;
6339 }
6340
6341 /* select Rx antennas */
6342 scan->flags |= iwl3945_get_antenna_flags(priv);
6343
6344 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR)
6345 scan->filter_flags = RXON_FILTER_PROMISC_MSK;
6346
786b4557 6347 if (direct_mask)
26c0f03f
RC		 6348 scan->channel_count =
6349 iwl3945_get_channels_for_scan(
6350 priv, band, 1, /* active */
6351 direct_mask,
6352 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
786b4557 6353 else
26c0f03f
RC		 6354 scan->channel_count =
6355 iwl3945_get_channels_for_scan(
6356 priv, band, 0, /* passive */
6357 direct_mask,
6358 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
b481de9c
ZY		 6359
6360 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
bb8c093b 6361 scan->channel_count * sizeof(struct iwl3945_scan_channel);
b481de9c
ZY		 6362 cmd.data = scan;
6363 scan->len = cpu_to_le16(cmd.len);
6364
6365 set_bit(STATUS_SCAN_HW, &priv->status);
bb8c093b 6366 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 6367 if (rc)
6368 goto done;
6369
6370 queue_delayed_work(priv->workqueue, &priv->scan_check,
6371 IWL_SCAN_CHECK_WATCHDOG);
6372
6373 mutex_unlock(&priv->mutex);
6374 return;
6375
6376 done:
01ebd063 6377 /* inform mac80211 scan aborted */
b481de9c
ZY		 6378 queue_work(priv->workqueue, &priv->scan_completed);
6379 mutex_unlock(&priv->mutex);
6380}
6381
bb8c093b 6382static void iwl3945_bg_up(struct work_struct *data)
b481de9c 6383{
bb8c093b 6384 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up);
b481de9c
ZY		 6385
6386 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6387 return;
6388
6389 mutex_lock(&priv->mutex);
bb8c093b 6390 __iwl3945_up(priv);
b481de9c
ZY		 6391 mutex_unlock(&priv->mutex);
6392}
6393
bb8c093b 6394static void iwl3945_bg_restart(struct work_struct *data)
b481de9c 6395{
bb8c093b 6396 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart);
b481de9c
ZY		 6397
6398 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6399 return;
6400
bb8c093b 6401 iwl3945_down(priv);
b481de9c
ZY		 6402 queue_work(priv->workqueue, &priv->up);
6403}
6404
bb8c093b 6405static void iwl3945_bg_rx_replenish(struct work_struct *data)
b481de9c 6406{
bb8c093b
CH		 6407 struct iwl3945_priv *priv =
6408 container_of(data, struct iwl3945_priv, rx_replenish);
b481de9c
ZY		 6409
6410 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6411 return;
6412
6413 mutex_lock(&priv->mutex);
bb8c093b 6414 iwl3945_rx_replenish(priv);
b481de9c
ZY		 6415 mutex_unlock(&priv->mutex);
6416}
6417
7878a5a4
MA		 6418#define IWL_DELAY_NEXT_SCAN (HZ*2)
6419
bb8c093b 6420static void iwl3945_bg_post_associate(struct work_struct *data)
b481de9c 6421{
bb8c093b 6422 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv,
b481de9c
ZY		 6423 post_associate.work);
6424
6425 int rc = 0;
6426 struct ieee80211_conf *conf = NULL;
0795af57 6427 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 6428
6429 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
6430 IWL_ERROR("%s Should not be called in AP mode\n", __FUNCTION__);
6431 return;
6432 }
6433
6434
0795af57
JP		 6435 IWL_DEBUG_ASSOC("Associated as %d to: %s\n",
6436 priv->assoc_id,
6437 print_mac(mac, priv->active_rxon.bssid_addr));
b481de9c
ZY		 6438
6439 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6440 return;
6441
6442 mutex_lock(&priv->mutex);
6443
32bfd35d 6444 if (!priv->vif || !priv->is_open) {
6ef89d0a
MA		 6445 mutex_unlock(&priv->mutex);
6446 return;
6447 }
bb8c093b 6448 iwl3945_scan_cancel_timeout(priv, 200);
15e869d8 6449
b481de9c
ZY		 6450 conf = ieee80211_get_hw_conf(priv->hw);
6451
6452 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6453 iwl3945_commit_rxon(priv);
b481de9c 6454
bb8c093b
CH		 6455 memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
6456 iwl3945_setup_rxon_timing(priv);
6457 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY		 6458 sizeof(priv->rxon_timing), &priv->rxon_timing);
6459 if (rc)
6460 IWL_WARNING("REPLY_RXON_TIMING failed - "
6461 "Attempting to continue.\n");
6462
6463 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
6464
6465 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
6466
6467 IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
6468 priv->assoc_id, priv->beacon_int);
6469
6470 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
6471 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
6472 else
6473 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
6474
6475 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
6476 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
6477 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
6478 else
6479 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
6480
6481 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
6482 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
6483
6484 }
6485
bb8c093b 6486 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6487
6488 switch (priv->iw_mode) {
6489 case IEEE80211_IF_TYPE_STA:
bb8c093b 6490 iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
b481de9c
ZY		 6491 break;
6492
6493 case IEEE80211_IF_TYPE_IBSS:
6494
6495 /* clear out the station table */
bb8c093b 6496 iwl3945_clear_stations_table(priv);
b481de9c 6497
bb8c093b
CH		 6498 iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
6499 iwl3945_add_station(priv, priv->bssid, 0, 0);
b481de9c 6500 iwl3945_sync_sta(priv, IWL_STA_ID,
8318d78a 6501 (priv->band == IEEE80211_BAND_5GHZ) ?
b481de9c
ZY		 6502 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
6503 CMD_ASYNC);
bb8c093b
CH		 6504 iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
6505 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 6506
6507 break;
6508
6509 default:
6510 IWL_ERROR("%s Should not be called in %d mode\n",
bc434dd2 6511 __FUNCTION__, priv->iw_mode);
b481de9c
ZY		 6512 break;
6513 }
6514
bb8c093b 6515 iwl3945_sequence_reset(priv);
b481de9c 6516
bb8c093b 6517 iwl3945_activate_qos(priv, 0);
292ae174 6518
7878a5a4
MA		 6519 /* we have just associated, don't start scan too early */
6520 priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
b481de9c
ZY		 6521 mutex_unlock(&priv->mutex);
6522}
6523
bb8c093b 6524static void iwl3945_bg_abort_scan(struct work_struct *work)
b481de9c 6525{
bb8c093b 6526 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan);
b481de9c 6527
bb8c093b 6528 if (!iwl3945_is_ready(priv))
b481de9c
ZY		 6529 return;
6530
6531 mutex_lock(&priv->mutex);
6532
6533 set_bit(STATUS_SCAN_ABORTING, &priv->status);
bb8c093b 6534 iwl3945_send_scan_abort(priv);
b481de9c
ZY		 6535
6536 mutex_unlock(&priv->mutex);
6537}
6538
76bb77e0
ZY		 6539static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf);
6540
bb8c093b 6541static void iwl3945_bg_scan_completed(struct work_struct *work)
b481de9c 6542{
bb8c093b
CH		 6543 struct iwl3945_priv *priv =
6544 container_of(work, struct iwl3945_priv, scan_completed);
b481de9c
ZY		 6545
6546 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
6547
6548 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6549 return;
6550
a0646470
ZY		 6551 if (test_bit(STATUS_CONF_PENDING, &priv->status))
6552 iwl3945_mac_config(priv->hw, ieee80211_get_hw_conf(priv->hw));
76bb77e0 6553
b481de9c
ZY		 6554 ieee80211_scan_completed(priv->hw);
6555
6556 /* Since setting the TXPOWER may have been deferred while
6557 * performing the scan, fire one off */
6558 mutex_lock(&priv->mutex);
bb8c093b 6559 iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 6560 mutex_unlock(&priv->mutex);
6561}
6562
6563/*****************************************************************************
6564 *
6565 * mac80211 entry point functions
6566 *
6567 *****************************************************************************/
6568
5a66926a
ZY		 6569#define UCODE_READY_TIMEOUT (2 * HZ)
6570
bb8c093b 6571static int iwl3945_mac_start(struct ieee80211_hw *hw)
b481de9c 6572{
bb8c093b 6573 struct iwl3945_priv *priv = hw->priv;
5a66926a 6574 int ret;
b481de9c
ZY		 6575
6576 IWL_DEBUG_MAC80211("enter\n");
6577
5a66926a
ZY		 6578 if (pci_enable_device(priv->pci_dev)) {
6579 IWL_ERROR("Fail to pci_enable_device\n");
6580 return -ENODEV;
6581 }
6582 pci_restore_state(priv->pci_dev);
6583 pci_enable_msi(priv->pci_dev);
6584
6585 ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
6586 DRV_NAME, priv);
6587 if (ret) {
6588 IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq);
6589 goto out_disable_msi;
6590 }
6591
b481de9c
ZY		 6592 /* we should be verifying the device is ready to be opened */
6593 mutex_lock(&priv->mutex);
6594
5a66926a
ZY		 6595 memset(&priv->staging_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
6596 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
6597 * ucode filename and max sizes are card-specific. */
6598
6599 if (!priv->ucode_code.len) {
6600 ret = iwl3945_read_ucode(priv);
6601 if (ret) {
6602 IWL_ERROR("Could not read microcode: %d\n", ret);
6603 mutex_unlock(&priv->mutex);
6604 goto out_release_irq;
6605 }
6606 }
b481de9c 6607
e655b9f0 6608 ret = __iwl3945_up(priv);
b481de9c
ZY		 6609
6610 mutex_unlock(&priv->mutex);
5a66926a 6611
e655b9f0
ZY		 6612 if (ret)
6613 goto out_release_irq;
6614
6615 IWL_DEBUG_INFO("Start UP work.\n");
6616
6617 if (test_bit(STATUS_IN_SUSPEND, &priv->status))
6618 return 0;
6619
5a66926a
ZY		 6620 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
6621 * mac80211 will not be run successfully. */
6622 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
6623 test_bit(STATUS_READY, &priv->status),
6624 UCODE_READY_TIMEOUT);
6625 if (!ret) {
6626 if (!test_bit(STATUS_READY, &priv->status)) {
6627 IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n",
6628 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6629 ret = -ETIMEDOUT;
6630 goto out_release_irq;
6631 }
6632 }
6633
e655b9f0 6634 priv->is_open = 1;
b481de9c
ZY		 6635 IWL_DEBUG_MAC80211("leave\n");
6636 return 0;
5a66926a
ZY		 6637
6638out_release_irq:
6639 free_irq(priv->pci_dev->irq, priv);
6640out_disable_msi:
6641 pci_disable_msi(priv->pci_dev);
e655b9f0
ZY		 6642 pci_disable_device(priv->pci_dev);
6643 priv->is_open = 0;
6644 IWL_DEBUG_MAC80211("leave - failed\n");
5a66926a 6645 return ret;
b481de9c
ZY		 6646}
6647
bb8c093b 6648static void iwl3945_mac_stop(struct ieee80211_hw *hw)
b481de9c 6649{
bb8c093b 6650 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6651
6652 IWL_DEBUG_MAC80211("enter\n");
6ef89d0a 6653
e655b9f0
ZY		 6654 if (!priv->is_open) {
6655 IWL_DEBUG_MAC80211("leave - skip\n");
6656 return;
6657 }
6658
b481de9c 6659 priv->is_open = 0;
5a66926a
ZY		 6660
6661 if (iwl3945_is_ready_rf(priv)) {
e655b9f0
ZY		 6662 /* stop mac, cancel any scan request and clear
6663 * RXON_FILTER_ASSOC_MSK BIT
6664 */
5a66926a
ZY		 6665 mutex_lock(&priv->mutex);
6666 iwl3945_scan_cancel_timeout(priv, 100);
6667 cancel_delayed_work(&priv->post_associate);
fde3571f 6668 mutex_unlock(&priv->mutex);
fde3571f
MA		 6669 }
6670
5a66926a
ZY		 6671 iwl3945_down(priv);
6672
6673 flush_workqueue(priv->workqueue);
6674 free_irq(priv->pci_dev->irq, priv);
6675 pci_disable_msi(priv->pci_dev);
6676 pci_save_state(priv->pci_dev);
6677 pci_disable_device(priv->pci_dev);
6ef89d0a 6678
b481de9c 6679 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 6680}
6681
e039fa4a 6682static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 6683{
bb8c093b 6684 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6685
6686 IWL_DEBUG_MAC80211("enter\n");
6687
6688 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
6689 IWL_DEBUG_MAC80211("leave - monitor\n");
6690 return -1;
6691 }
6692
6693 IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 6694 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 6695
e039fa4a 6696 if (iwl3945_tx_skb(priv, skb))
b481de9c
ZY		 6697 dev_kfree_skb_any(skb);
6698
6699 IWL_DEBUG_MAC80211("leave\n");
6700 return 0;
6701}
6702
bb8c093b 6703static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
b481de9c
ZY		 6704 struct ieee80211_if_init_conf *conf)
6705{
bb8c093b 6706 struct iwl3945_priv *priv = hw->priv;
b481de9c 6707 unsigned long flags;
0795af57 6708 DECLARE_MAC_BUF(mac);
b481de9c 6709
32bfd35d 6710 IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
b481de9c 6711
32bfd35d
JB		 6712 if (priv->vif) {
6713 IWL_DEBUG_MAC80211("leave - vif != NULL\n");
864792e3 6714 return -EOPNOTSUPP;
b481de9c
ZY		 6715 }
6716
6717 spin_lock_irqsave(&priv->lock, flags);
32bfd35d 6718 priv->vif = conf->vif;
b481de9c
ZY		 6719
6720 spin_unlock_irqrestore(&priv->lock, flags);
6721
6722 mutex_lock(&priv->mutex);
864792e3
TW		 6723
6724 if (conf->mac_addr) {
6725 IWL_DEBUG_MAC80211("Set: %s\n", print_mac(mac, conf->mac_addr));
6726 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
6727 }
6728
5a66926a
ZY		 6729 if (iwl3945_is_ready(priv))
6730 iwl3945_set_mode(priv, conf->type);
b481de9c 6731
b481de9c
ZY		 6732 mutex_unlock(&priv->mutex);
6733
5a66926a 6734 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 6735 return 0;
6736}
6737
6738/**
bb8c093b 6739 * iwl3945_mac_config - mac80211 config callback
b481de9c
ZY		 6740 *
6741 * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
6742 * be set inappropriately and the driver currently sets the hardware up to
6743 * use it whenever needed.
6744 */
bb8c093b 6745static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
b481de9c 6746{
bb8c093b
CH		 6747 struct iwl3945_priv *priv = hw->priv;
6748 const struct iwl3945_channel_info *ch_info;
b481de9c 6749 unsigned long flags;
76bb77e0 6750 int ret = 0;
b481de9c
ZY		 6751
6752 mutex_lock(&priv->mutex);
8318d78a 6753 IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
b481de9c 6754
12342c47
ZY		 6755 priv->add_radiotap = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
6756
bb8c093b 6757 if (!iwl3945_is_ready(priv)) {
b481de9c 6758 IWL_DEBUG_MAC80211("leave - not ready\n");
76bb77e0
ZY		 6759 ret = -EIO;
6760 goto out;
b481de9c
ZY		 6761 }
6762
bb8c093b 6763 if (unlikely(!iwl3945_param_disable_hw_scan &&
b481de9c 6764 test_bit(STATUS_SCANNING, &priv->status))) {
a0646470
ZY		 6765 IWL_DEBUG_MAC80211("leave - scanning\n");
6766 set_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 6767 mutex_unlock(&priv->mutex);
a0646470 6768 return 0;
b481de9c
ZY		 6769 }
6770
6771 spin_lock_irqsave(&priv->lock, flags);
6772
8318d78a
JB		 6773 ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
6774 conf->channel->hw_value);
b481de9c
ZY		 6775 if (!is_channel_valid(ch_info)) {
6776 IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this SKU.\n",
8318d78a 6777 conf->channel->hw_value, conf->channel->band);
b481de9c
ZY		 6778 IWL_DEBUG_MAC80211("leave - invalid channel\n");
6779 spin_unlock_irqrestore(&priv->lock, flags);
76bb77e0
ZY		 6780 ret = -EINVAL;
6781 goto out;
b481de9c
ZY		 6782 }
6783
8318d78a 6784 iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
b481de9c 6785
8318d78a 6786 iwl3945_set_flags_for_phymode(priv, conf->channel->band);
b481de9c
ZY		 6787
6788 /* The list of supported rates and rate mask can be different
6789 * for each phymode; since the phymode may have changed, reset
6790 * the rate mask to what mac80211 lists */
bb8c093b 6791 iwl3945_set_rate(priv);
b481de9c
ZY		 6792
6793 spin_unlock_irqrestore(&priv->lock, flags);
6794
6795#ifdef IEEE80211_CONF_CHANNEL_SWITCH
6796 if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
bb8c093b 6797 iwl3945_hw_channel_switch(priv, conf->channel);
76bb77e0 6798 goto out;
b481de9c
ZY		 6799 }
6800#endif
6801
bb8c093b 6802 iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
b481de9c
ZY		 6803
6804 if (!conf->radio_enabled) {
6805 IWL_DEBUG_MAC80211("leave - radio disabled\n");
76bb77e0 6806 goto out;
b481de9c
ZY		 6807 }
6808
bb8c093b 6809 if (iwl3945_is_rfkill(priv)) {
b481de9c 6810 IWL_DEBUG_MAC80211("leave - RF kill\n");
76bb77e0
ZY		 6811 ret = -EIO;
6812 goto out;
b481de9c
ZY		 6813 }
6814
bb8c093b 6815 iwl3945_set_rate(priv);
b481de9c
ZY		 6816
6817 if (memcmp(&priv->active_rxon,
6818 &priv->staging_rxon, sizeof(priv->staging_rxon)))
bb8c093b 6819 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6820 else
6821 IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
6822
6823 IWL_DEBUG_MAC80211("leave\n");
6824
76bb77e0 6825out:
a0646470 6826 clear_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 6827 mutex_unlock(&priv->mutex);
76bb77e0 6828 return ret;
b481de9c
ZY		 6829}
6830
bb8c093b 6831static void iwl3945_config_ap(struct iwl3945_priv *priv)
b481de9c
ZY		 6832{
6833 int rc = 0;
6834
d986bcd1 6835 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY		 6836 return;
6837
6838 /* The following should be done only at AP bring up */
6839 if ((priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) == 0) {
6840
6841 /* RXON - unassoc (to set timing command) */
6842 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6843 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6844
6845 /* RXON Timing */
bb8c093b
CH		 6846 memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
6847 iwl3945_setup_rxon_timing(priv);
6848 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY		 6849 sizeof(priv->rxon_timing), &priv->rxon_timing);
6850 if (rc)
6851 IWL_WARNING("REPLY_RXON_TIMING failed - "
6852 "Attempting to continue.\n");
6853
6854 /* FIXME: what should be the assoc_id for AP? */
6855 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
6856 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
6857 priv->staging_rxon.flags |=
6858 RXON_FLG_SHORT_PREAMBLE_MSK;
6859 else
6860 priv->staging_rxon.flags &=
6861 ~RXON_FLG_SHORT_PREAMBLE_MSK;
6862
6863 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
6864 if (priv->assoc_capability &
6865 WLAN_CAPABILITY_SHORT_SLOT_TIME)
6866 priv->staging_rxon.flags |=
6867 RXON_FLG_SHORT_SLOT_MSK;
6868 else
6869 priv->staging_rxon.flags &=
6870 ~RXON_FLG_SHORT_SLOT_MSK;
6871
6872 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
6873 priv->staging_rxon.flags &=
6874 ~RXON_FLG_SHORT_SLOT_MSK;
6875 }
6876 /* restore RXON assoc */
6877 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
bb8c093b
CH		 6878 iwl3945_commit_rxon(priv);
6879 iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
556f8db7 6880 }
bb8c093b 6881 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 6882
6883 /* FIXME - we need to add code here to detect a totally new
6884 * configuration, reset the AP, unassoc, rxon timing, assoc,
6885 * clear sta table, add BCAST sta... */
6886}
6887
32bfd35d
JB		 6888static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
6889 struct ieee80211_vif *vif,
b481de9c
ZY		 6890 struct ieee80211_if_conf *conf)
6891{
bb8c093b 6892 struct iwl3945_priv *priv = hw->priv;
0795af57 6893 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 6894 unsigned long flags;
6895 int rc;
6896
6897 if (conf == NULL)
6898 return -EIO;
6899
b716bb91
EG		 6900 if (priv->vif != vif) {
6901 IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
b716bb91
EG		 6902 return 0;
6903 }
6904
4150c572
JB		 6905 /* XXX: this MUST use conf->mac_addr */
6906
b481de9c
ZY		 6907 if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
6908 (!conf->beacon || !conf->ssid_len)) {
6909 IWL_DEBUG_MAC80211
6910 ("Leaving in AP mode because HostAPD is not ready.\n");
6911 return 0;
6912 }
6913
5a66926a
ZY		 6914 if (!iwl3945_is_alive(priv))
6915 return -EAGAIN;
6916
b481de9c
ZY		 6917 mutex_lock(&priv->mutex);
6918
b481de9c 6919 if (conf->bssid)
0795af57
JP		 6920 IWL_DEBUG_MAC80211("bssid: %s\n",
6921 print_mac(mac, conf->bssid));
b481de9c 6922
4150c572
JB		 6923/*
6924 * very dubious code was here; the probe filtering flag is never set:
6925 *
b481de9c
ZY		 6926 if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
6927 !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
4150c572 6928 */
b481de9c
ZY		 6929
6930 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
6931 if (!conf->bssid) {
6932 conf->bssid = priv->mac_addr;
6933 memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
0795af57
JP		 6934 IWL_DEBUG_MAC80211("bssid was set to: %s\n",
6935 print_mac(mac, conf->bssid));
b481de9c
ZY		 6936 }
6937 if (priv->ibss_beacon)
6938 dev_kfree_skb(priv->ibss_beacon);
6939
6940 priv->ibss_beacon = conf->beacon;
6941 }
6942
fde3571f
MA		 6943 if (iwl3945_is_rfkill(priv))
6944 goto done;
6945
b481de9c
ZY		 6946 if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
6947 !is_multicast_ether_addr(conf->bssid)) {
6948 /* If there is currently a HW scan going on in the background
6949 * then we need to cancel it else the RXON below will fail. */
bb8c093b 6950 if (iwl3945_scan_cancel_timeout(priv, 100)) {
b481de9c
ZY		 6951 IWL_WARNING("Aborted scan still in progress "
6952 "after 100ms\n");
6953 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
6954 mutex_unlock(&priv->mutex);
6955 return -EAGAIN;
6956 }
6957 memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
6958
6959 /* TODO: Audit driver for usage of these members and see
6960 * if mac80211 deprecates them (priv->bssid looks like it
6961 * shouldn't be there, but I haven't scanned the IBSS code
6962 * to verify) - jpk */
6963 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
6964
6965 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
bb8c093b 6966 iwl3945_config_ap(priv);
b481de9c 6967 else {
bb8c093b 6968 rc = iwl3945_commit_rxon(priv);
b481de9c 6969 if ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && rc)
bb8c093b 6970 iwl3945_add_station(priv,
556f8db7 6971 priv->active_rxon.bssid_addr, 1, 0);
b481de9c
ZY		 6972 }
6973
6974 } else {
bb8c093b 6975 iwl3945_scan_cancel_timeout(priv, 100);
b481de9c 6976 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6977 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6978 }
6979
fde3571f 6980 done:
b481de9c
ZY		 6981 spin_lock_irqsave(&priv->lock, flags);
6982 if (!conf->ssid_len)
6983 memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
6984 else
6985 memcpy(priv->essid, conf->ssid, conf->ssid_len);
6986
6987 priv->essid_len = conf->ssid_len;
6988 spin_unlock_irqrestore(&priv->lock, flags);
6989
6990 IWL_DEBUG_MAC80211("leave\n");
6991 mutex_unlock(&priv->mutex);
6992
6993 return 0;
6994}
6995
bb8c093b 6996static void iwl3945_configure_filter(struct ieee80211_hw *hw,
4150c572
JB		 6997 unsigned int changed_flags,
6998 unsigned int *total_flags,
6999 int mc_count, struct dev_addr_list *mc_list)
7000{
7001 /*
7002 * XXX: dummy
bb8c093b 7003 * see also iwl3945_connection_init_rx_config
4150c572 7004 */
5ec03976
AK		 7005 struct iwl3945_priv *priv = hw->priv;
7006 int new_flags = 0;
7007 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
7008 if (*total_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
7009 IWL_DEBUG_MAC80211("Enter: type %d (0x%x, 0x%x)\n",
7010 IEEE80211_IF_TYPE_MNTR,
7011 changed_flags, *total_flags);
7012 /* queue work 'cuz mac80211 is holding a lock which
7013 * prevents us from issuing (synchronous) f/w cmds */
7014 queue_work(priv->workqueue, &priv->set_monitor);
7015 new_flags &= FIF_PROMISC_IN_BSS |
7016 FIF_OTHER_BSS |
7017 FIF_ALLMULTI;
7018 }
7019 }
7020 *total_flags = new_flags;
4150c572
JB		 7021}
7022
bb8c093b 7023static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
b481de9c
ZY		 7024 struct ieee80211_if_init_conf *conf)
7025{
bb8c093b 7026 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7027
7028 IWL_DEBUG_MAC80211("enter\n");
7029
7030 mutex_lock(&priv->mutex);
6ef89d0a 7031
fde3571f
MA		 7032 if (iwl3945_is_ready_rf(priv)) {
7033 iwl3945_scan_cancel_timeout(priv, 100);
7034 cancel_delayed_work(&priv->post_associate);
7035 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
7036 iwl3945_commit_rxon(priv);
7037 }
32bfd35d
JB		 7038 if (priv->vif == conf->vif) {
7039 priv->vif = NULL;
b481de9c
ZY		 7040 memset(priv->bssid, 0, ETH_ALEN);
7041 memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
7042 priv->essid_len = 0;
7043 }
7044 mutex_unlock(&priv->mutex);
7045
7046 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 7047}
7048
bb8c093b 7049static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
b481de9c
ZY		 7050{
7051 int rc = 0;
7052 unsigned long flags;
bb8c093b 7053 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7054
7055 IWL_DEBUG_MAC80211("enter\n");
7056
15e869d8 7057 mutex_lock(&priv->mutex);
b481de9c
ZY		 7058 spin_lock_irqsave(&priv->lock, flags);
7059
bb8c093b 7060 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7061 rc = -EIO;
7062 IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
7063 goto out_unlock;
7064 }
7065
7066 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { /* APs don't scan */
7067 rc = -EIO;
7068 IWL_ERROR("ERROR: APs don't scan\n");
7069 goto out_unlock;
7070 }
7071
7878a5a4
MA		 7072 /* we don't schedule scan within next_scan_jiffies period */
7073 if (priv->next_scan_jiffies &&
7074 time_after(priv->next_scan_jiffies, jiffies)) {
7075 rc = -EAGAIN;
7076 goto out_unlock;
7077 }
15dbf1b7
BM		 7078 /* if we just finished scan ask for delay for a broadcast scan */
7079 if ((len == 0) && priv->last_scan_jiffies &&
7080 time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN,
7081 jiffies)) {
b481de9c
ZY		 7082 rc = -EAGAIN;
7083 goto out_unlock;
7084 }
7085 if (len) {
7878a5a4 7086 IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
bb8c093b 7087 iwl3945_escape_essid(ssid, len), (int)len);
b481de9c
ZY		 7088
7089 priv->one_direct_scan = 1;
7090 priv->direct_ssid_len = (u8)
7091 min((u8) len, (u8) IW_ESSID_MAX_SIZE);
7092 memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
6ef89d0a
MA		 7093 } else
7094 priv->one_direct_scan = 0;
b481de9c 7095
bb8c093b 7096 rc = iwl3945_scan_initiate(priv);
b481de9c
ZY		 7097
7098 IWL_DEBUG_MAC80211("leave\n");
7099
7100out_unlock:
7101 spin_unlock_irqrestore(&priv->lock, flags);
15e869d8 7102 mutex_unlock(&priv->mutex);
b481de9c
ZY		 7103
7104 return rc;
7105}
7106
bb8c093b 7107static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
b481de9c
ZY		 7108 const u8 *local_addr, const u8 *addr,
7109 struct ieee80211_key_conf *key)
7110{
bb8c093b 7111 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7112 int rc = 0;
7113 u8 sta_id;
7114
7115 IWL_DEBUG_MAC80211("enter\n");
7116
bb8c093b 7117 if (!iwl3945_param_hwcrypto) {
b481de9c
ZY		 7118 IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
7119 return -EOPNOTSUPP;
7120 }
7121
7122 if (is_zero_ether_addr(addr))
7123 /* only support pairwise keys */
7124 return -EOPNOTSUPP;
7125
bb8c093b 7126 sta_id = iwl3945_hw_find_station(priv, addr);
b481de9c 7127 if (sta_id == IWL_INVALID_STATION) {
0795af57
JP		 7128 DECLARE_MAC_BUF(mac);
7129
7130 IWL_DEBUG_MAC80211("leave - %s not in station map.\n",
7131 print_mac(mac, addr));
b481de9c
ZY		 7132 return -EINVAL;
7133 }
7134
7135 mutex_lock(&priv->mutex);
7136
bb8c093b 7137 iwl3945_scan_cancel_timeout(priv, 100);
15e869d8 7138
b481de9c
ZY		 7139 switch (cmd) {
7140 case SET_KEY:
bb8c093b 7141 rc = iwl3945_update_sta_key_info(priv, key, sta_id);
b481de9c 7142 if (!rc) {
bb8c093b
CH		 7143 iwl3945_set_rxon_hwcrypto(priv, 1);
7144 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7145 key->hw_key_idx = sta_id;
7146 IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
7147 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
7148 }
7149 break;
7150 case DISABLE_KEY:
bb8c093b 7151 rc = iwl3945_clear_sta_key_info(priv, sta_id);
b481de9c 7152 if (!rc) {
bb8c093b
CH		 7153 iwl3945_set_rxon_hwcrypto(priv, 0);
7154 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7155 IWL_DEBUG_MAC80211("disable hwcrypto key\n");
7156 }
7157 break;
7158 default:
7159 rc = -EINVAL;
7160 }
7161
7162 IWL_DEBUG_MAC80211("leave\n");
7163 mutex_unlock(&priv->mutex);
7164
7165 return rc;
7166}
7167
e100bb64 7168static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
b481de9c
ZY		 7169 const struct ieee80211_tx_queue_params *params)
7170{
bb8c093b 7171 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7172 unsigned long flags;
7173 int q;
b481de9c
ZY		 7174
7175 IWL_DEBUG_MAC80211("enter\n");
7176
bb8c093b 7177 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7178 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7179 return -EIO;
7180 }
7181
7182 if (queue >= AC_NUM) {
7183 IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
7184 return 0;
7185 }
7186
b481de9c
ZY		 7187 if (!priv->qos_data.qos_enable) {
7188 priv->qos_data.qos_active = 0;
7189 IWL_DEBUG_MAC80211("leave - qos not enabled\n");
7190 return 0;
7191 }
7192 q = AC_NUM - 1 - queue;
7193
7194 spin_lock_irqsave(&priv->lock, flags);
7195
7196 priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
7197 priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
7198 priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
7199 priv->qos_data.def_qos_parm.ac[q].edca_txop =
3330d7be 7200 cpu_to_le16((params->txop * 32));
b481de9c
ZY		 7201
7202 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
7203 priv->qos_data.qos_active = 1;
7204
7205 spin_unlock_irqrestore(&priv->lock, flags);
7206
7207 mutex_lock(&priv->mutex);
7208 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
bb8c093b
CH		 7209 iwl3945_activate_qos(priv, 1);
7210 else if (priv->assoc_id && iwl3945_is_associated(priv))
7211 iwl3945_activate_qos(priv, 0);
b481de9c
ZY		 7212
7213 mutex_unlock(&priv->mutex);
7214
b481de9c
ZY		 7215 IWL_DEBUG_MAC80211("leave\n");
7216 return 0;
7217}
7218
bb8c093b 7219static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
b481de9c
ZY		 7220 struct ieee80211_tx_queue_stats *stats)
7221{
bb8c093b 7222 struct iwl3945_priv *priv = hw->priv;
b481de9c 7223 int i, avail;
bb8c093b
CH		 7224 struct iwl3945_tx_queue *txq;
7225 struct iwl3945_queue *q;
b481de9c
ZY		 7226 unsigned long flags;
7227
7228 IWL_DEBUG_MAC80211("enter\n");
7229
bb8c093b 7230 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7231 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7232 return -EIO;
7233 }
7234
7235 spin_lock_irqsave(&priv->lock, flags);
7236
7237 for (i = 0; i < AC_NUM; i++) {
7238 txq = &priv->txq[i];
7239 q = &txq->q;
bb8c093b 7240 avail = iwl3945_queue_space(q);
b481de9c 7241
57ffc589
JB		 7242 stats[i].len = q->n_window - avail;
7243 stats[i].limit = q->n_window - q->high_mark;
7244 stats[i].count = q->n_window;
b481de9c
ZY		 7245
7246 }
7247 spin_unlock_irqrestore(&priv->lock, flags);
7248
7249 IWL_DEBUG_MAC80211("leave\n");
7250
7251 return 0;
7252}
7253
bb8c093b 7254static int iwl3945_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY		 7255 struct ieee80211_low_level_stats *stats)
7256{
7257 IWL_DEBUG_MAC80211("enter\n");
7258 IWL_DEBUG_MAC80211("leave\n");
7259
7260 return 0;
7261}
7262
bb8c093b 7263static u64 iwl3945_mac_get_tsf(struct ieee80211_hw *hw)
b481de9c
ZY		 7264{
7265 IWL_DEBUG_MAC80211("enter\n");
7266 IWL_DEBUG_MAC80211("leave\n");
7267
7268 return 0;
7269}
7270
bb8c093b 7271static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
b481de9c 7272{
bb8c093b 7273 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7274 unsigned long flags;
7275
7276 mutex_lock(&priv->mutex);
7277 IWL_DEBUG_MAC80211("enter\n");
7278
bb8c093b 7279 iwl3945_reset_qos(priv);
292ae174 7280
b481de9c
ZY		 7281 cancel_delayed_work(&priv->post_associate);
7282
7283 spin_lock_irqsave(&priv->lock, flags);
7284 priv->assoc_id = 0;
7285 priv->assoc_capability = 0;
7286 priv->call_post_assoc_from_beacon = 0;
7287
7288 /* new association get rid of ibss beacon skb */
7289 if (priv->ibss_beacon)
7290 dev_kfree_skb(priv->ibss_beacon);
7291
7292 priv->ibss_beacon = NULL;
7293
7294 priv->beacon_int = priv->hw->conf.beacon_int;
7295 priv->timestamp1 = 0;
7296 priv->timestamp0 = 0;
7297 if ((priv->iw_mode == IEEE80211_IF_TYPE_STA))
7298 priv->beacon_int = 0;
7299
7300 spin_unlock_irqrestore(&priv->lock, flags);
7301
fde3571f
MA		 7302 if (!iwl3945_is_ready_rf(priv)) {
7303 IWL_DEBUG_MAC80211("leave - not ready\n");
7304 mutex_unlock(&priv->mutex);
7305 return;
7306 }
7307
15e869d8
MA		 7308 /* we are restarting association process
7309 * clear RXON_FILTER_ASSOC_MSK bit
7310 */
7311 if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
bb8c093b 7312 iwl3945_scan_cancel_timeout(priv, 100);
15e869d8 7313 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 7314 iwl3945_commit_rxon(priv);
15e869d8
MA		 7315 }
7316
b481de9c
ZY		 7317 /* Per mac80211.h: This is only used in IBSS mode... */
7318 if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
15e869d8 7319
b481de9c
ZY		 7320 IWL_DEBUG_MAC80211("leave - not in IBSS\n");
7321 mutex_unlock(&priv->mutex);
7322 return;
b481de9c
ZY		 7323 }
7324
bb8c093b 7325 iwl3945_set_rate(priv);
b481de9c
ZY		 7326
7327 mutex_unlock(&priv->mutex);
7328
7329 IWL_DEBUG_MAC80211("leave\n");
7330
7331}
7332
e039fa4a 7333static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 7334{
bb8c093b 7335 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7336 unsigned long flags;
7337
7338 mutex_lock(&priv->mutex);
7339 IWL_DEBUG_MAC80211("enter\n");
7340
bb8c093b 7341 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7342 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7343 mutex_unlock(&priv->mutex);
7344 return -EIO;
7345 }
7346
7347 if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
7348 IWL_DEBUG_MAC80211("leave - not IBSS\n");
7349 mutex_unlock(&priv->mutex);
7350 return -EIO;
7351 }
7352
7353 spin_lock_irqsave(&priv->lock, flags);
7354
7355 if (priv->ibss_beacon)
7356 dev_kfree_skb(priv->ibss_beacon);
7357
7358 priv->ibss_beacon = skb;
7359
7360 priv->assoc_id = 0;
7361
7362 IWL_DEBUG_MAC80211("leave\n");
7363 spin_unlock_irqrestore(&priv->lock, flags);
7364
bb8c093b 7365 iwl3945_reset_qos(priv);
b481de9c
ZY		 7366
7367 queue_work(priv->workqueue, &priv->post_associate.work);
7368
7369 mutex_unlock(&priv->mutex);
7370
7371 return 0;
7372}
7373
7374/*****************************************************************************
7375 *
7376 * sysfs attributes
7377 *
7378 *****************************************************************************/
7379
c8b0e6e1 7380#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 7381
7382/*
7383 * The following adds a new attribute to the sysfs representation
7384 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
7385 * used for controlling the debug level.
7386 *
7387 * See the level definitions in iwl for details.
7388 */
7389
7390static ssize_t show_debug_level(struct device_driver *d, char *buf)
7391{
bb8c093b 7392 return sprintf(buf, "0x%08X\n", iwl3945_debug_level);
b481de9c
ZY		 7393}
7394static ssize_t store_debug_level(struct device_driver *d,
7395 const char *buf, size_t count)
7396{
7397 char *p = (char *)buf;
7398 u32 val;
7399
7400 val = simple_strtoul(p, &p, 0);
7401 if (p == buf)
7402 printk(KERN_INFO DRV_NAME
7403 ": %s is not in hex or decimal form.\n", buf);
7404 else
bb8c093b 7405 iwl3945_debug_level = val;
b481de9c
ZY		 7406
7407 return strnlen(buf, count);
7408}
7409
7410static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
7411 show_debug_level, store_debug_level);
7412
c8b0e6e1 7413#endif /* CONFIG_IWL3945_DEBUG */
b481de9c
ZY		 7414
7415static ssize_t show_rf_kill(struct device *d,
7416 struct device_attribute *attr, char *buf)
7417{
7418 /*
7419 * 0 - RF kill not enabled
7420 * 1 - SW based RF kill active (sysfs)
7421 * 2 - HW based RF kill active
7422 * 3 - Both HW and SW based RF kill active
7423 */
bb8c093b 7424 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7425 int val = (test_bit(STATUS_RF_KILL_SW, &priv->status) ? 0x1 : 0x0) |
7426 (test_bit(STATUS_RF_KILL_HW, &priv->status) ? 0x2 : 0x0);
7427
7428 return sprintf(buf, "%i\n", val);
7429}
7430
7431static ssize_t store_rf_kill(struct device *d,
7432 struct device_attribute *attr,
7433 const char *buf, size_t count)
7434{
bb8c093b 7435 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7436
7437 mutex_lock(&priv->mutex);
bb8c093b 7438 iwl3945_radio_kill_sw(priv, buf[0] == '1');
b481de9c
ZY		 7439 mutex_unlock(&priv->mutex);
7440
7441 return count;
7442}
7443
7444static DEVICE_ATTR(rf_kill, S_IWUSR | S_IRUGO, show_rf_kill, store_rf_kill);
7445
7446static ssize_t show_temperature(struct device *d,
7447 struct device_attribute *attr, char *buf)
7448{
bb8c093b 7449 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c 7450
bb8c093b 7451 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7452 return -EAGAIN;
7453
bb8c093b 7454 return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
b481de9c
ZY		 7455}
7456
7457static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
7458
7459static ssize_t show_rs_window(struct device *d,
7460 struct device_attribute *attr,
7461 char *buf)
7462{
bb8c093b
CH		 7463 struct iwl3945_priv *priv = d->driver_data;
7464 return iwl3945_fill_rs_info(priv->hw, buf, IWL_AP_ID);
b481de9c
ZY		 7465}
7466static DEVICE_ATTR(rs_window, S_IRUGO, show_rs_window, NULL);
7467
7468static ssize_t show_tx_power(struct device *d,
7469 struct device_attribute *attr, char *buf)
7470{
bb8c093b 7471 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7472 return sprintf(buf, "%d\n", priv->user_txpower_limit);
7473}
7474
7475static ssize_t store_tx_power(struct device *d,
7476 struct device_attribute *attr,
7477 const char *buf, size_t count)
7478{
bb8c093b 7479 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7480 char *p = (char *)buf;
7481 u32 val;
7482
7483 val = simple_strtoul(p, &p, 10);
7484 if (p == buf)
7485 printk(KERN_INFO DRV_NAME
7486 ": %s is not in decimal form.\n", buf);
7487 else
bb8c093b 7488 iwl3945_hw_reg_set_txpower(priv, val);
b481de9c
ZY		 7489
7490 return count;
7491}
7492
7493static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
7494
7495static ssize_t show_flags(struct device *d,
7496 struct device_attribute *attr, char *buf)
7497{
bb8c093b 7498 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7499
7500 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
7501}
7502
7503static ssize_t store_flags(struct device *d,
7504 struct device_attribute *attr,
7505 const char *buf, size_t count)
7506{
bb8c093b 7507 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7508 u32 flags = simple_strtoul(buf, NULL, 0);
7509
7510 mutex_lock(&priv->mutex);
7511 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
7512 /* Cancel any currently running scans... */
bb8c093b 7513 if (iwl3945_scan_cancel_timeout(priv, 100))
b481de9c
ZY		 7514 IWL_WARNING("Could not cancel scan.\n");
7515 else {
7516 IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
7517 flags);
7518 priv->staging_rxon.flags = cpu_to_le32(flags);
bb8c093b 7519 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7520 }
7521 }
7522 mutex_unlock(&priv->mutex);
7523
7524 return count;
7525}
7526
7527static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
7528
7529static ssize_t show_filter_flags(struct device *d,
7530 struct device_attribute *attr, char *buf)
7531{
bb8c093b 7532 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7533
7534 return sprintf(buf, "0x%04X\n",
7535 le32_to_cpu(priv->active_rxon.filter_flags));
7536}
7537
7538static ssize_t store_filter_flags(struct device *d,
7539 struct device_attribute *attr,
7540 const char *buf, size_t count)
7541{
bb8c093b 7542 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7543 u32 filter_flags = simple_strtoul(buf, NULL, 0);
7544
7545 mutex_lock(&priv->mutex);
7546 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
7547 /* Cancel any currently running scans... */
bb8c093b 7548 if (iwl3945_scan_cancel_timeout(priv, 100))
b481de9c
ZY		 7549 IWL_WARNING("Could not cancel scan.\n");
7550 else {
7551 IWL_DEBUG_INFO("Committing rxon.filter_flags = "
7552 "0x%04X\n", filter_flags);
7553 priv->staging_rxon.filter_flags =
7554 cpu_to_le32(filter_flags);
bb8c093b 7555 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7556 }
7557 }
7558 mutex_unlock(&priv->mutex);
7559
7560 return count;
7561}
7562
7563static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
7564 store_filter_flags);
7565
c8b0e6e1 7566#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 7567
7568static ssize_t show_measurement(struct device *d,
7569 struct device_attribute *attr, char *buf)
7570{
bb8c093b
CH		 7571 struct iwl3945_priv *priv = dev_get_drvdata(d);
7572 struct iwl3945_spectrum_notification measure_report;
b481de9c
ZY		 7573 u32 size = sizeof(measure_report), len = 0, ofs = 0;
7574 u8 *data = (u8 *) & measure_report;
7575 unsigned long flags;
7576
7577 spin_lock_irqsave(&priv->lock, flags);
7578 if (!(priv->measurement_status & MEASUREMENT_READY)) {
7579 spin_unlock_irqrestore(&priv->lock, flags);
7580 return 0;
7581 }
7582 memcpy(&measure_report, &priv->measure_report, size);
7583 priv->measurement_status = 0;
7584 spin_unlock_irqrestore(&priv->lock, flags);
7585
7586 while (size && (PAGE_SIZE - len)) {
7587 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
7588 PAGE_SIZE - len, 1);
7589 len = strlen(buf);
7590 if (PAGE_SIZE - len)
7591 buf[len++] = '\n';
7592
7593 ofs += 16;
7594 size -= min(size, 16U);
7595 }
7596
7597 return len;
7598}
7599
7600static ssize_t store_measurement(struct device *d,
7601 struct device_attribute *attr,
7602 const char *buf, size_t count)
7603{
bb8c093b 7604 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7605 struct ieee80211_measurement_params params = {
7606 .channel = le16_to_cpu(priv->active_rxon.channel),
7607 .start_time = cpu_to_le64(priv->last_tsf),
7608 .duration = cpu_to_le16(1),
7609 };
7610 u8 type = IWL_MEASURE_BASIC;
7611 u8 buffer[32];
7612 u8 channel;
7613
7614 if (count) {
7615 char *p = buffer;
7616 strncpy(buffer, buf, min(sizeof(buffer), count));
7617 channel = simple_strtoul(p, NULL, 0);
7618 if (channel)
7619 params.channel = channel;
7620
7621 p = buffer;
7622 while (*p && *p != ' ')
7623 p++;
7624 if (*p)
7625 type = simple_strtoul(p + 1, NULL, 0);
7626 }
7627
7628 IWL_DEBUG_INFO("Invoking measurement of type %d on "
7629 "channel %d (for '%s')\n", type, params.channel, buf);
bb8c093b 7630 iwl3945_get_measurement(priv, &params, type);
b481de9c
ZY		 7631
7632 return count;
7633}
7634
7635static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
7636 show_measurement, store_measurement);
c8b0e6e1 7637#endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
b481de9c 7638
b481de9c
ZY		 7639static ssize_t store_retry_rate(struct device *d,
7640 struct device_attribute *attr,
7641 const char *buf, size_t count)
7642{
bb8c093b 7643 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7644
7645 priv->retry_rate = simple_strtoul(buf, NULL, 0);
7646 if (priv->retry_rate <= 0)
7647 priv->retry_rate = 1;
7648
7649 return count;
7650}
7651
7652static ssize_t show_retry_rate(struct device *d,
7653 struct device_attribute *attr, char *buf)
7654{
bb8c093b 7655 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7656 return sprintf(buf, "%d", priv->retry_rate);
7657}
7658
7659static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
7660 store_retry_rate);
7661
7662static ssize_t store_power_level(struct device *d,
7663 struct device_attribute *attr,
7664 const char *buf, size_t count)
7665{
bb8c093b 7666 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7667 int rc;
7668 int mode;
7669
7670 mode = simple_strtoul(buf, NULL, 0);
7671 mutex_lock(&priv->mutex);
7672
bb8c093b 7673 if (!iwl3945_is_ready(priv)) {
b481de9c
ZY		 7674 rc = -EAGAIN;
7675 goto out;
7676 }
7677
7678 if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
7679 mode = IWL_POWER_AC;
7680 else
7681 mode |= IWL_POWER_ENABLED;
7682
7683 if (mode != priv->power_mode) {
bb8c093b 7684 rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
b481de9c
ZY		 7685 if (rc) {
7686 IWL_DEBUG_MAC80211("failed setting power mode.\n");
7687 goto out;
7688 }
7689 priv->power_mode = mode;
7690 }
7691
7692 rc = count;
7693
7694 out:
7695 mutex_unlock(&priv->mutex);
7696 return rc;
7697}
7698
7699#define MAX_WX_STRING 80
7700
7701/* Values are in microsecond */
7702static const s32 timeout_duration[] = {
7703 350000,
7704 250000,
7705 75000,
7706 37000,
7707 25000,
7708};
7709static const s32 period_duration[] = {
7710 400000,
7711 700000,
7712 1000000,
7713 1000000,
7714 1000000
7715};
7716
7717static ssize_t show_power_level(struct device *d,
7718 struct device_attribute *attr, char *buf)
7719{
bb8c093b 7720 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7721 int level = IWL_POWER_LEVEL(priv->power_mode);
7722 char *p = buf;
7723
7724 p += sprintf(p, "%d ", level);
7725 switch (level) {
7726 case IWL_POWER_MODE_CAM:
7727 case IWL_POWER_AC:
7728 p += sprintf(p, "(AC)");
7729 break;
7730 case IWL_POWER_BATTERY:
7731 p += sprintf(p, "(BATTERY)");
7732 break;
7733 default:
7734 p += sprintf(p,
7735 "(Timeout %dms, Period %dms)",
7736 timeout_duration[level - 1] / 1000,
7737 period_duration[level - 1] / 1000);
7738 }
7739
7740 if (!(priv->power_mode & IWL_POWER_ENABLED))
7741 p += sprintf(p, " OFF\n");
7742 else
7743 p += sprintf(p, " \n");
7744
7745 return (p - buf + 1);
7746
7747}
7748
7749static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
7750 store_power_level);
7751
7752static ssize_t show_channels(struct device *d,
7753 struct device_attribute *attr, char *buf)
7754{
8318d78a
JB		 7755 /* all this shit doesn't belong into sysfs anyway */
7756 return 0;
b481de9c
ZY		 7757}
7758
7759static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
7760
7761static ssize_t show_statistics(struct device *d,
7762 struct device_attribute *attr, char *buf)
7763{
bb8c093b
CH		 7764 struct iwl3945_priv *priv = dev_get_drvdata(d);
7765 u32 size = sizeof(struct iwl3945_notif_statistics);
b481de9c
ZY		 7766 u32 len = 0, ofs = 0;
7767 u8 *data = (u8 *) & priv->statistics;
7768 int rc = 0;
7769
bb8c093b 7770 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7771 return -EAGAIN;
7772
7773 mutex_lock(&priv->mutex);
bb8c093b 7774 rc = iwl3945_send_statistics_request(priv);
b481de9c
ZY		 7775 mutex_unlock(&priv->mutex);
7776
7777 if (rc) {
7778 len = sprintf(buf,
7779 "Error sending statistics request: 0x%08X\n", rc);
7780 return len;
7781 }
7782
7783 while (size && (PAGE_SIZE - len)) {
7784 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
7785 PAGE_SIZE - len, 1);
7786 len = strlen(buf);
7787 if (PAGE_SIZE - len)
7788 buf[len++] = '\n';
7789
7790 ofs += 16;
7791 size -= min(size, 16U);
7792 }
7793
7794 return len;
7795}
7796
7797static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
7798
7799static ssize_t show_antenna(struct device *d,
7800 struct device_attribute *attr, char *buf)
7801{
bb8c093b 7802 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c 7803
bb8c093b 7804 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7805 return -EAGAIN;
7806
7807 return sprintf(buf, "%d\n", priv->antenna);
7808}
7809
7810static ssize_t store_antenna(struct device *d,
7811 struct device_attribute *attr,
7812 const char *buf, size_t count)
7813{
7814 int ant;
bb8c093b 7815 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7816
7817 if (count == 0)
7818 return 0;
7819
7820 if (sscanf(buf, "%1i", &ant) != 1) {
7821 IWL_DEBUG_INFO("not in hex or decimal form.\n");
7822 return count;
7823 }
7824
7825 if ((ant >= 0) && (ant <= 2)) {
7826 IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
bb8c093b 7827 priv->antenna = (enum iwl3945_antenna)ant;
b481de9c
ZY		 7828 } else
7829 IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
7830
7831
7832 return count;
7833}
7834
7835static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
7836
7837static ssize_t show_status(struct device *d,
7838 struct device_attribute *attr, char *buf)
7839{
bb8c093b
CH		 7840 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
7841 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7842 return -EAGAIN;
7843 return sprintf(buf, "0x%08x\n", (int)priv->status);
7844}
7845
7846static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
7847
7848static ssize_t dump_error_log(struct device *d,
7849 struct device_attribute *attr,
7850 const char *buf, size_t count)
7851{
7852 char *p = (char *)buf;
7853
7854 if (p[0] == '1')
bb8c093b 7855 iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data);
b481de9c
ZY		 7856
7857 return strnlen(buf, count);
7858}
7859
7860static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
7861
7862static ssize_t dump_event_log(struct device *d,
7863 struct device_attribute *attr,
7864 const char *buf, size_t count)
7865{
7866 char *p = (char *)buf;
7867
7868 if (p[0] == '1')
bb8c093b 7869 iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data);
b481de9c
ZY		 7870
7871 return strnlen(buf, count);
7872}
7873
7874static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
7875
7876/*****************************************************************************
7877 *
7878 * driver setup and teardown
7879 *
7880 *****************************************************************************/
7881
bb8c093b 7882static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv)
b481de9c
ZY		 7883{
7884 priv->workqueue = create_workqueue(DRV_NAME);
7885
7886 init_waitqueue_head(&priv->wait_command_queue);
7887
bb8c093b
CH		 7888 INIT_WORK(&priv->up, iwl3945_bg_up);
7889 INIT_WORK(&priv->restart, iwl3945_bg_restart);
7890 INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
7891 INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
7892 INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
7893 INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
7894 INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
7895 INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
5ec03976 7896 INIT_WORK(&priv->set_monitor, iwl3945_bg_set_monitor);
bb8c093b
CH		 7897 INIT_DELAYED_WORK(&priv->post_associate, iwl3945_bg_post_associate);
7898 INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
7899 INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
7900 INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
7901
7902 iwl3945_hw_setup_deferred_work(priv);
b481de9c
ZY		 7903
7904 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
bb8c093b 7905 iwl3945_irq_tasklet, (unsigned long)priv);
b481de9c
ZY		 7906}
7907
bb8c093b 7908static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv)
b481de9c 7909{
bb8c093b 7910 iwl3945_hw_cancel_deferred_work(priv);
b481de9c 7911
e47eb6ad 7912 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY		 7913 cancel_delayed_work(&priv->scan_check);
7914 cancel_delayed_work(&priv->alive_start);
7915 cancel_delayed_work(&priv->post_associate);
7916 cancel_work_sync(&priv->beacon_update);
7917}
7918
bb8c093b 7919static struct attribute *iwl3945_sysfs_entries[] = {
b481de9c
ZY		 7920 &dev_attr_antenna.attr,
7921 &dev_attr_channels.attr,
7922 &dev_attr_dump_errors.attr,
7923 &dev_attr_dump_events.attr,
7924 &dev_attr_flags.attr,
7925 &dev_attr_filter_flags.attr,
c8b0e6e1 7926#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 7927 &dev_attr_measurement.attr,
7928#endif
7929 &dev_attr_power_level.attr,
b481de9c
ZY		 7930 &dev_attr_retry_rate.attr,
7931 &dev_attr_rf_kill.attr,
7932 &dev_attr_rs_window.attr,
7933 &dev_attr_statistics.attr,
7934 &dev_attr_status.attr,
7935 &dev_attr_temperature.attr,
b481de9c
ZY		 7936 &dev_attr_tx_power.attr,
7937
7938 NULL
7939};
7940
bb8c093b 7941static struct attribute_group iwl3945_attribute_group = {
b481de9c 7942 .name = NULL, /* put in device directory */
bb8c093b 7943 .attrs = iwl3945_sysfs_entries,
b481de9c
ZY		 7944};
7945
bb8c093b
CH		 7946static struct ieee80211_ops iwl3945_hw_ops = {
7947 .tx = iwl3945_mac_tx,
7948 .start = iwl3945_mac_start,
7949 .stop = iwl3945_mac_stop,
7950 .add_interface = iwl3945_mac_add_interface,
7951 .remove_interface = iwl3945_mac_remove_interface,
7952 .config = iwl3945_mac_config,
7953 .config_interface = iwl3945_mac_config_interface,
7954 .configure_filter = iwl3945_configure_filter,
7955 .set_key = iwl3945_mac_set_key,
7956 .get_stats = iwl3945_mac_get_stats,
7957 .get_tx_stats = iwl3945_mac_get_tx_stats,
7958 .conf_tx = iwl3945_mac_conf_tx,
7959 .get_tsf = iwl3945_mac_get_tsf,
7960 .reset_tsf = iwl3945_mac_reset_tsf,
7961 .beacon_update = iwl3945_mac_beacon_update,
7962 .hw_scan = iwl3945_mac_hw_scan
b481de9c
ZY		 7963};
7964
bb8c093b 7965static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY		 7966{
7967 int err = 0;
bb8c093b 7968 struct iwl3945_priv *priv;
b481de9c 7969 struct ieee80211_hw *hw;
82b9a121 7970 struct iwl_3945_cfg *cfg = (struct iwl_3945_cfg *)(ent->driver_data);
b481de9c 7971 int i;
0359facc 7972 unsigned long flags;
5a66926a 7973 DECLARE_MAC_BUF(mac);
b481de9c 7974
6440adb5
CB		 7975 /* Disabling hardware scan means that mac80211 will perform scans
7976 * "the hard way", rather than using device's scan. */
bb8c093b 7977 if (iwl3945_param_disable_hw_scan) {
b481de9c 7978 IWL_DEBUG_INFO("Disabling hw_scan\n");
bb8c093b 7979 iwl3945_hw_ops.hw_scan = NULL;
b481de9c
ZY		 7980 }
7981
dfe7d458 7982 if ((iwl3945_param_queues_num > IWL39_MAX_NUM_QUEUES) ||
bb8c093b 7983 (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) {
b481de9c 7984 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
dfe7d458 7985 IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES);
b481de9c
ZY		 7986 err = -EINVAL;
7987 goto out;
7988 }
7989
7990 /* mac80211 allocates memory for this device instance, including
7991 * space for this driver's private structure */
bb8c093b 7992 hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops);
b481de9c
ZY		 7993 if (hw == NULL) {
7994 IWL_ERROR("Can not allocate network device\n");
7995 err = -ENOMEM;
7996 goto out;
7997 }
7998 SET_IEEE80211_DEV(hw, &pdev->dev);
7999
f51359a8
JB		 8000 hw->rate_control_algorithm = "iwl-3945-rs";
8001
b481de9c
ZY		 8002 IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
8003 priv = hw->priv;
8004 priv->hw = hw;
8005
8006 priv->pci_dev = pdev;
82b9a121 8007 priv->cfg = cfg;
6440adb5
CB		 8008
8009 /* Select antenna (may be helpful if only one antenna is connected) */
bb8c093b 8010 priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna;
c8b0e6e1 8011#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8012 iwl3945_debug_level = iwl3945_param_debug;
b481de9c
ZY		 8013 atomic_set(&priv->restrict_refcnt, 0);
8014#endif
8015 priv->retry_rate = 1;
8016
8017 priv->ibss_beacon = NULL;
8018
566bfe5a
BR		 8019 /* Tell mac80211 our characteristics */
8020 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
8021 IEEE80211_HW_SIGNAL_DBM |
8022 IEEE80211_HW_NOISE_DBM;
b481de9c 8023
6440adb5 8024 /* 4 EDCA QOS priorities */
b481de9c
ZY		 8025 hw->queues = 4;
8026
8027 spin_lock_init(&priv->lock);
8028 spin_lock_init(&priv->power_data.lock);
8029 spin_lock_init(&priv->sta_lock);
8030 spin_lock_init(&priv->hcmd_lock);
8031
8032 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
8033 INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
8034
8035 INIT_LIST_HEAD(&priv->free_frames);
8036
8037 mutex_init(&priv->mutex);
8038 if (pci_enable_device(pdev)) {
8039 err = -ENODEV;
8040 goto out_ieee80211_free_hw;
8041 }
8042
8043 pci_set_master(pdev);
8044
6440adb5 8045 /* Clear the driver's (not device's) station table */
bb8c093b 8046 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 8047
8048 priv->data_retry_limit = -1;
8049 priv->ieee_channels = NULL;
8050 priv->ieee_rates = NULL;
8318d78a 8051 priv->band = IEEE80211_BAND_2GHZ;
b481de9c
ZY		 8052
8053 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
8054 if (!err)
8055 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
8056 if (err) {
8057 printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
8058 goto out_pci_disable_device;
8059 }
8060
8061 pci_set_drvdata(pdev, priv);
8062 err = pci_request_regions(pdev, DRV_NAME);
8063 if (err)
8064 goto out_pci_disable_device;
6440adb5 8065
b481de9c
ZY		 8066 /* We disable the RETRY_TIMEOUT register (0x41) to keep
8067 * PCI Tx retries from interfering with C3 CPU state */
8068 pci_write_config_byte(pdev, 0x41, 0x00);
6440adb5 8069
b481de9c
ZY		 8070 priv->hw_base = pci_iomap(pdev, 0, 0);
8071 if (!priv->hw_base) {
8072 err = -ENODEV;
8073 goto out_pci_release_regions;
8074 }
8075
8076 IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
8077 (unsigned long long) pci_resource_len(pdev, 0));
8078 IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
8079
8080 /* Initialize module parameter values here */
8081
6440adb5 8082 /* Disable radio (SW RF KILL) via parameter when loading driver */
bb8c093b 8083 if (iwl3945_param_disable) {
b481de9c
ZY		 8084 set_bit(STATUS_RF_KILL_SW, &priv->status);
8085 IWL_DEBUG_INFO("Radio disabled.\n");
8086 }
8087
8088 priv->iw_mode = IEEE80211_IF_TYPE_STA;
8089
b481de9c 8090 printk(KERN_INFO DRV_NAME
82b9a121 8091 ": Detected Intel Wireless WiFi Link %s\n", priv->cfg->name);
b481de9c
ZY		 8092
8093 /* Device-specific setup */
bb8c093b 8094 if (iwl3945_hw_set_hw_setting(priv)) {
b481de9c 8095 IWL_ERROR("failed to set hw settings\n");
b481de9c
ZY		 8096 goto out_iounmap;
8097 }
8098
bb8c093b 8099 if (iwl3945_param_qos_enable)
b481de9c
ZY		 8100 priv->qos_data.qos_enable = 1;
8101
bb8c093b 8102 iwl3945_reset_qos(priv);
b481de9c
ZY		 8103
8104 priv->qos_data.qos_active = 0;
8105 priv->qos_data.qos_cap.val = 0;
b481de9c 8106
8318d78a 8107 iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
bb8c093b
CH		 8108 iwl3945_setup_deferred_work(priv);
8109 iwl3945_setup_rx_handlers(priv);
b481de9c
ZY		 8110
8111 priv->rates_mask = IWL_RATES_MASK;
8112 /* If power management is turned on, default to AC mode */
8113 priv->power_mode = IWL_POWER_AC;
8114 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
8115
0359facc 8116 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 8117 iwl3945_disable_interrupts(priv);
0359facc 8118 spin_unlock_irqrestore(&priv->lock, flags);
49df2b33 8119
bb8c093b 8120 err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c
ZY		 8121 if (err) {
8122 IWL_ERROR("failed to create sysfs device attributes\n");
b481de9c
ZY		 8123 goto out_release_irq;
8124 }
8125
5a66926a
ZY		 8126 /* nic init */
8127 iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
8128 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
8129
8130 iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
8131 err = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
8132 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
8133 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
8134 if (err < 0) {
8135 IWL_DEBUG_INFO("Failed to init the card\n");
8136 goto out_remove_sysfs;
8137 }
8138 /* Read the EEPROM */
8139 err = iwl3945_eeprom_init(priv);
b481de9c 8140 if (err) {
5a66926a
ZY		 8141 IWL_ERROR("Unable to init EEPROM\n");
8142 goto out_remove_sysfs;
b481de9c 8143 }
5a66926a
ZY		 8144 /* MAC Address location in EEPROM same for 3945/4965 */
8145 get_eeprom_mac(priv, priv->mac_addr);
8146 IWL_DEBUG_INFO("MAC address: %s\n", print_mac(mac, priv->mac_addr));
8147 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
b481de9c 8148
849e0dce
RC		 8149 err = iwl3945_init_channel_map(priv);
8150 if (err) {
8151 IWL_ERROR("initializing regulatory failed: %d\n", err);
8152 goto out_remove_sysfs;
8153 }
8154
8155 err = iwl3945_init_geos(priv);
8156 if (err) {
8157 IWL_ERROR("initializing geos failed: %d\n", err);
8158 goto out_free_channel_map;
8159 }
849e0dce 8160
5a66926a
ZY		 8161 err = ieee80211_register_hw(priv->hw);
8162 if (err) {
8163 IWL_ERROR("Failed to register network device (error %d)\n", err);
849e0dce 8164 goto out_free_geos;
5a66926a 8165 }
b481de9c 8166
5a66926a
ZY		 8167 priv->hw->conf.beacon_int = 100;
8168 priv->mac80211_registered = 1;
8169 pci_save_state(pdev);
8170 pci_disable_device(pdev);
b481de9c
ZY		 8171
8172 return 0;
8173
849e0dce
RC		 8174 out_free_geos:
8175 iwl3945_free_geos(priv);
8176 out_free_channel_map:
8177 iwl3945_free_channel_map(priv);
5a66926a 8178 out_remove_sysfs:
bb8c093b 8179 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c
ZY		 8180
8181 out_release_irq:
b481de9c
ZY		 8182 destroy_workqueue(priv->workqueue);
8183 priv->workqueue = NULL;
bb8c093b 8184 iwl3945_unset_hw_setting(priv);
b481de9c
ZY		 8185
8186 out_iounmap:
8187 pci_iounmap(pdev, priv->hw_base);
8188 out_pci_release_regions:
8189 pci_release_regions(pdev);
8190 out_pci_disable_device:
8191 pci_disable_device(pdev);
8192 pci_set_drvdata(pdev, NULL);
8193 out_ieee80211_free_hw:
8194 ieee80211_free_hw(priv->hw);
8195 out:
8196 return err;
8197}
8198
c83dbf68 8199static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
b481de9c 8200{
bb8c093b 8201 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c
ZY		 8202 struct list_head *p, *q;
8203 int i;
0359facc 8204 unsigned long flags;
b481de9c
ZY		 8205
8206 if (!priv)
8207 return;
8208
8209 IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
8210
b481de9c 8211 set_bit(STATUS_EXIT_PENDING, &priv->status);
b24d22b1 8212
bb8c093b 8213 iwl3945_down(priv);
b481de9c 8214
0359facc
MA		 8215 /* make sure we flush any pending irq or
8216 * tasklet for the driver
8217 */
8218 spin_lock_irqsave(&priv->lock, flags);
8219 iwl3945_disable_interrupts(priv);
8220 spin_unlock_irqrestore(&priv->lock, flags);
8221
8222 iwl_synchronize_irq(priv);
8223
b481de9c
ZY		 8224 /* Free MAC hash list for ADHOC */
8225 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) {
8226 list_for_each_safe(p, q, &priv->ibss_mac_hash[i]) {
8227 list_del(p);
bb8c093b 8228 kfree(list_entry(p, struct iwl3945_ibss_seq, list));
b481de9c
ZY		 8229 }
8230 }
8231
bb8c093b 8232 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 8233
bb8c093b 8234 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY		 8235
8236 if (priv->rxq.bd)
bb8c093b
CH		 8237 iwl3945_rx_queue_free(priv, &priv->rxq);
8238 iwl3945_hw_txq_ctx_free(priv);
b481de9c 8239
bb8c093b
CH		 8240 iwl3945_unset_hw_setting(priv);
8241 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 8242
8243 if (priv->mac80211_registered) {
8244 ieee80211_unregister_hw(priv->hw);
b481de9c
ZY		 8245 }
8246
6ef89d0a
MA		 8247 /*netif_stop_queue(dev); */
8248 flush_workqueue(priv->workqueue);
8249
bb8c093b 8250 /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
b481de9c
ZY		 8251 * priv->workqueue... so we can't take down the workqueue
8252 * until now... */
8253 destroy_workqueue(priv->workqueue);
8254 priv->workqueue = NULL;
8255
b481de9c
ZY		 8256 pci_iounmap(pdev, priv->hw_base);
8257 pci_release_regions(pdev);
8258 pci_disable_device(pdev);
8259 pci_set_drvdata(pdev, NULL);
8260
849e0dce
RC		 8261 iwl3945_free_channel_map(priv);
8262 iwl3945_free_geos(priv);
b481de9c
ZY		 8263
8264 if (priv->ibss_beacon)
8265 dev_kfree_skb(priv->ibss_beacon);
8266
8267 ieee80211_free_hw(priv->hw);
8268}
8269
8270#ifdef CONFIG_PM
8271
bb8c093b 8272static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
b481de9c 8273{
bb8c093b 8274 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c 8275
e655b9f0
ZY		 8276 if (priv->is_open) {
8277 set_bit(STATUS_IN_SUSPEND, &priv->status);
8278 iwl3945_mac_stop(priv->hw);
8279 priv->is_open = 1;
8280 }
b481de9c 8281
b481de9c
ZY		 8282 pci_set_power_state(pdev, PCI_D3hot);
8283
b481de9c
ZY		 8284 return 0;
8285}
8286
bb8c093b 8287static int iwl3945_pci_resume(struct pci_dev *pdev)
b481de9c 8288{
bb8c093b 8289 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c 8290
b481de9c 8291 pci_set_power_state(pdev, PCI_D0);
b481de9c 8292
e655b9f0
ZY		 8293 if (priv->is_open)
8294 iwl3945_mac_start(priv->hw);
b481de9c 8295
e655b9f0 8296 clear_bit(STATUS_IN_SUSPEND, &priv->status);
b481de9c
ZY		 8297 return 0;
8298}
8299
8300#endif /* CONFIG_PM */
8301
8302/*****************************************************************************
8303 *
8304 * driver and module entry point
8305 *
8306 *****************************************************************************/
8307
bb8c093b 8308static struct pci_driver iwl3945_driver = {
b481de9c 8309 .name = DRV_NAME,
bb8c093b
CH		 8310 .id_table = iwl3945_hw_card_ids,
8311 .probe = iwl3945_pci_probe,
8312 .remove = __devexit_p(iwl3945_pci_remove),
b481de9c 8313#ifdef CONFIG_PM
bb8c093b
CH		 8314 .suspend = iwl3945_pci_suspend,
8315 .resume = iwl3945_pci_resume,
b481de9c
ZY		 8316#endif
8317};
8318
bb8c093b 8319static int __init iwl3945_init(void)
b481de9c
ZY		 8320{
8321
8322 int ret;
8323 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
8324 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2
RC		 8325
8326 ret = iwl3945_rate_control_register();
8327 if (ret) {
8328 IWL_ERROR("Unable to register rate control algorithm: %d\n", ret);
8329 return ret;
8330 }
8331
bb8c093b 8332 ret = pci_register_driver(&iwl3945_driver);
b481de9c
ZY		 8333 if (ret) {
8334 IWL_ERROR("Unable to initialize PCI module\n");
897e1cf2 8335 goto error_register;
b481de9c 8336 }
c8b0e6e1 8337#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8338 ret = driver_create_file(&iwl3945_driver.driver, &driver_attr_debug_level);
b481de9c
ZY		 8339 if (ret) {
8340 IWL_ERROR("Unable to create driver sysfs file\n");
897e1cf2 8341 goto error_debug;
b481de9c
ZY		 8342 }
8343#endif
8344
8345 return ret;
897e1cf2
RC		 8346
8347#ifdef CONFIG_IWL3945_DEBUG
8348error_debug:
8349 pci_unregister_driver(&iwl3945_driver);
8350#endif
8351error_register:
8352 iwl3945_rate_control_unregister();
8353 return ret;
b481de9c
ZY		 8354}
8355
bb8c093b 8356static void __exit iwl3945_exit(void)
b481de9c 8357{
c8b0e6e1 8358#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8359 driver_remove_file(&iwl3945_driver.driver, &driver_attr_debug_level);
b481de9c 8360#endif
bb8c093b 8361 pci_unregister_driver(&iwl3945_driver);
897e1cf2 8362 iwl3945_rate_control_unregister();
b481de9c
ZY		 8363}
8364
bb8c093b 8365module_param_named(antenna, iwl3945_param_antenna, int, 0444);
b481de9c 8366MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
bb8c093b 8367module_param_named(disable, iwl3945_param_disable, int, 0444);
b481de9c 8368MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
bb8c093b 8369module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444);
b481de9c
ZY		 8370MODULE_PARM_DESC(hwcrypto,
8371 "using hardware crypto engine (default 0 [software])\n");
bb8c093b 8372module_param_named(debug, iwl3945_param_debug, int, 0444);
b481de9c 8373MODULE_PARM_DESC(debug, "debug output mask");
bb8c093b 8374module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444);
b481de9c
ZY		 8375MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
8376
bb8c093b 8377module_param_named(queues_num, iwl3945_param_queues_num, int, 0444);
b481de9c
ZY		 8378MODULE_PARM_DESC(queues_num, "number of hw queues.");
8379
8380/* QoS */
bb8c093b 8381module_param_named(qos_enable, iwl3945_param_qos_enable, int, 0444);
b481de9c
ZY		 8382MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
8383
bb8c093b
CH		 8384module_exit(iwl3945_exit);
8385module_init(iwl3945_init);
Linux kernel - Deliverables
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