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mac80211: introduce hw config change flags
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl3945-base.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
b481de9c
ZY		 30#include <linux/kernel.h>
31#include <linux/module.h>
b481de9c
ZY		 32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
36#include <linux/skbuff.h>
37#include <linux/netdevice.h>
38#include <linux/wireless.h>
39#include <linux/firmware.h>
b481de9c
ZY		 40#include <linux/etherdevice.h>
41#include <linux/if_arp.h>
42
43#include <net/ieee80211_radiotap.h>
44#include <net/mac80211.h>
45
46#include <asm/div64.h>
47
82b9a121 48#include "iwl-3945-core.h"
b481de9c
ZY		 49#include "iwl-3945.h"
50#include "iwl-helpers.h"
51
c8b0e6e1 52#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 53u32 iwl3945_debug_level;
b481de9c
ZY		 54#endif
55
bb8c093b
CH		 56static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
57 struct iwl3945_tx_queue *txq);
416e1438 58
b481de9c
ZY		 59/******************************************************************************
60 *
61 * module boiler plate
62 *
63 ******************************************************************************/
64
65/* module parameters */
6440adb5
CB		 66static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */
67static int iwl3945_param_debug; /* def: 0 = minimal debug log messages */
68static int iwl3945_param_disable; /* def: 0 = enable radio */
9fbab516 69static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */
6440adb5
CB		 70int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */
71static int iwl3945_param_qos_enable = 1; /* def: 1 = use quality of service */
dfe7d458 72int iwl3945_param_queues_num = IWL39_MAX_NUM_QUEUES; /* def: 8 Tx queues */
b481de9c
ZY		 73
74/*
75 * module name, copyright, version, etc.
76 * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
77 */
78
79#define DRV_DESCRIPTION \
80"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
81
c8b0e6e1 82#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 83#define VD "d"
84#else
85#define VD
86#endif
87
c8b0e6e1 88#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 89#define VS "s"
90#else
91#define VS
92#endif
93
b9e0b449 94#define IWLWIFI_VERSION "1.2.26k" VD VS
eb7ae89c 95#define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation"
b481de9c
ZY		 96#define DRV_VERSION IWLWIFI_VERSION
97
b481de9c
ZY		 98
99MODULE_DESCRIPTION(DRV_DESCRIPTION);
100MODULE_VERSION(DRV_VERSION);
101MODULE_AUTHOR(DRV_COPYRIGHT);
102MODULE_LICENSE("GPL");
103
8318d78a
JB		 104static const struct ieee80211_supported_band *iwl3945_get_band(
105 struct iwl3945_priv *priv, enum ieee80211_band band)
b481de9c 106{
8318d78a 107 return priv->hw->wiphy->bands[band];
b481de9c
ZY		 108}
109
bb8c093b 110static int iwl3945_is_empty_essid(const char *essid, int essid_len)
b481de9c
ZY		 111{
112 /* Single white space is for Linksys APs */
113 if (essid_len == 1 && essid[0] == ' ')
114 return 1;
115
116 /* Otherwise, if the entire essid is 0, we assume it is hidden */
117 while (essid_len) {
118 essid_len--;
119 if (essid[essid_len] != '\0')
120 return 0;
121 }
122
123 return 1;
124}
125
bb8c093b 126static const char *iwl3945_escape_essid(const char *essid, u8 essid_len)
b481de9c
ZY		 127{
128 static char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
129 const char *s = essid;
130 char *d = escaped;
131
bb8c093b 132 if (iwl3945_is_empty_essid(essid, essid_len)) {
b481de9c
ZY		 133 memcpy(escaped, "<hidden>", sizeof("<hidden>"));
134 return escaped;
135 }
136
137 essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE);
138 while (essid_len--) {
139 if (*s == '\0') {
140 *d++ = '\\';
141 *d++ = '0';
142 s++;
143 } else
144 *d++ = *s++;
145 }
146 *d = '\0';
147 return escaped;
148}
149
b481de9c
ZY		 150/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
151 * DMA services
152 *
153 * Theory of operation
154 *
6440adb5
CB		 155 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
156 * of buffer descriptors, each of which points to one or more data buffers for
157 * the device to read from or fill. Driver and device exchange status of each
158 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
159 * entries in each circular buffer, to protect against confusing empty and full
160 * queue states.
161 *
162 * The device reads or writes the data in the queues via the device's several
163 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
b481de9c
ZY		 164 *
165 * For Tx queue, there are low mark and high mark limits. If, after queuing
166 * the packet for Tx, free space become < low mark, Tx queue stopped. When
167 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
168 * Tx queue resumed.
169 *
6440adb5
CB		 170 * The 3945 operates with six queues: One receive queue, one transmit queue
171 * (#4) for sending commands to the device firmware, and four transmit queues
172 * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
b481de9c
ZY		 173 ***************************************************/
174
c54b679d 175int iwl3945_queue_space(const struct iwl3945_queue *q)
b481de9c 176{
fc4b6853 177 int s = q->read_ptr - q->write_ptr;
b481de9c 178
fc4b6853 179 if (q->read_ptr > q->write_ptr)
b481de9c
ZY		 180 s -= q->n_bd;
181
182 if (s <= 0)
183 s += q->n_window;
184 /* keep some reserve to not confuse empty and full situations */
185 s -= 2;
186 if (s < 0)
187 s = 0;
188 return s;
189}
190
c54b679d 191int iwl3945_x2_queue_used(const struct iwl3945_queue *q, int i)
b481de9c 192{
fc4b6853
TW		 193 return q->write_ptr > q->read_ptr ?
194 (i >= q->read_ptr && i < q->write_ptr) :
195 !(i < q->read_ptr && i >= q->write_ptr);
b481de9c
ZY		 196}
197
c54b679d 198
bb8c093b 199static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge)
b481de9c 200{
6440adb5 201 /* This is for scan command, the big buffer at end of command array */
b481de9c 202 if (is_huge)
6440adb5 203 return q->n_window; /* must be power of 2 */
b481de9c 204
6440adb5 205 /* Otherwise, use normal size buffers */
b481de9c
ZY		 206 return index & (q->n_window - 1);
207}
208
6440adb5
CB		 209/**
210 * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
211 */
bb8c093b 212static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q,
b481de9c
ZY		 213 int count, int slots_num, u32 id)
214{
215 q->n_bd = count;
216 q->n_window = slots_num;
217 q->id = id;
218
c54b679d
TW		 219 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
220 * and iwl_queue_dec_wrap are broken. */
b481de9c
ZY		 221 BUG_ON(!is_power_of_2(count));
222
223 /* slots_num must be power-of-two size, otherwise
224 * get_cmd_index is broken. */
225 BUG_ON(!is_power_of_2(slots_num));
226
227 q->low_mark = q->n_window / 4;
228 if (q->low_mark < 4)
229 q->low_mark = 4;
230
231 q->high_mark = q->n_window / 8;
232 if (q->high_mark < 2)
233 q->high_mark = 2;
234
fc4b6853 235 q->write_ptr = q->read_ptr = 0;
b481de9c
ZY		 236
237 return 0;
238}
239
6440adb5
CB		 240/**
241 * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
242 */
bb8c093b
CH		 243static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
244 struct iwl3945_tx_queue *txq, u32 id)
b481de9c
ZY		 245{
246 struct pci_dev *dev = priv->pci_dev;
247
6440adb5
CB		 248 /* Driver private data, only for Tx (not command) queues,
249 * not shared with device. */
b481de9c
ZY		 250 if (id != IWL_CMD_QUEUE_NUM) {
251 txq->txb = kmalloc(sizeof(txq->txb[0]) *
252 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
253 if (!txq->txb) {
01ebd063 254 IWL_ERROR("kmalloc for auxiliary BD "
b481de9c
ZY		 255 "structures failed\n");
256 goto error;
257 }
258 } else
259 txq->txb = NULL;
260
6440adb5
CB		 261 /* Circular buffer of transmit frame descriptors (TFDs),
262 * shared with device */
b481de9c
ZY		 263 txq->bd = pci_alloc_consistent(dev,
264 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
265 &txq->q.dma_addr);
266
267 if (!txq->bd) {
268 IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
269 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
270 goto error;
271 }
272 txq->q.id = id;
273
274 return 0;
275
276 error:
3ac7f146
TW		 277 kfree(txq->txb);
278 txq->txb = NULL;
b481de9c
ZY		 279
280 return -ENOMEM;
281}
282
6440adb5
CB		 283/**
284 * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
285 */
bb8c093b
CH		 286int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
287 struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
b481de9c
ZY		 288{
289 struct pci_dev *dev = priv->pci_dev;
290 int len;
291 int rc = 0;
292
6440adb5
CB		 293 /*
294 * Alloc buffer array for commands (Tx or other types of commands).
295 * For the command queue (#4), allocate command space + one big
296 * command for scan, since scan command is very huge; the system will
297 * not have two scans at the same time, so only one is needed.
298 * For data Tx queues (all other queues), no super-size command
299 * space is needed.
300 */
bb8c093b 301 len = sizeof(struct iwl3945_cmd) * slots_num;
b481de9c
ZY		 302 if (txq_id == IWL_CMD_QUEUE_NUM)
303 len += IWL_MAX_SCAN_SIZE;
304 txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
305 if (!txq->cmd)
306 return -ENOMEM;
307
6440adb5 308 /* Alloc driver data array and TFD circular buffer */
bb8c093b 309 rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
b481de9c
ZY		 310 if (rc) {
311 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
312
313 return -ENOMEM;
314 }
315 txq->need_update = 0;
316
317 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
c54b679d 318 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
b481de9c 319 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
6440adb5
CB		 320
321 /* Initialize queue high/low-water, head/tail indexes */
bb8c093b 322 iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
b481de9c 323
6440adb5 324 /* Tell device where to find queue, enable DMA channel. */
bb8c093b 325 iwl3945_hw_tx_queue_init(priv, txq);
b481de9c
ZY		 326
327 return 0;
328}
329
330/**
bb8c093b 331 * iwl3945_tx_queue_free - Deallocate DMA queue.
b481de9c
ZY		 332 * @txq: Transmit queue to deallocate.
333 *
334 * Empty queue by removing and destroying all BD's.
6440adb5
CB		 335 * Free all buffers.
336 * 0-fill, but do not free "txq" descriptor structure.
b481de9c 337 */
bb8c093b 338void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c 339{
bb8c093b 340 struct iwl3945_queue *q = &txq->q;
b481de9c
ZY		 341 struct pci_dev *dev = priv->pci_dev;
342 int len;
343
344 if (q->n_bd == 0)
345 return;
346
347 /* first, empty all BD's */
fc4b6853 348 for (; q->write_ptr != q->read_ptr;
c54b679d 349 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
bb8c093b 350 iwl3945_hw_txq_free_tfd(priv, txq);
b481de9c 351
bb8c093b 352 len = sizeof(struct iwl3945_cmd) * q->n_window;
b481de9c
ZY		 353 if (q->id == IWL_CMD_QUEUE_NUM)
354 len += IWL_MAX_SCAN_SIZE;
355
6440adb5 356 /* De-alloc array of command/tx buffers */
b481de9c
ZY		 357 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
358
6440adb5 359 /* De-alloc circular buffer of TFDs */
b481de9c 360 if (txq->q.n_bd)
bb8c093b 361 pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
b481de9c
ZY		 362 txq->q.n_bd, txq->bd, txq->q.dma_addr);
363
6440adb5 364 /* De-alloc array of per-TFD driver data */
3ac7f146
TW		 365 kfree(txq->txb);
366 txq->txb = NULL;
b481de9c 367
6440adb5 368 /* 0-fill queue descriptor structure */
b481de9c
ZY		 369 memset(txq, 0, sizeof(*txq));
370}
371
bb8c093b 372const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
b481de9c
ZY		 373
374/*************** STATION TABLE MANAGEMENT ****
9fbab516 375 * mac80211 should be examined to determine if sta_info is duplicating
b481de9c
ZY		 376 * the functionality provided here
377 */
378
379/**************************************************************/
01ebd063 380#if 0 /* temporary disable till we add real remove station */
6440adb5
CB		 381/**
382 * iwl3945_remove_station - Remove driver's knowledge of station.
383 *
384 * NOTE: This does not remove station from device's station table.
385 */
bb8c093b 386static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
b481de9c
ZY		 387{
388 int index = IWL_INVALID_STATION;
389 int i;
390 unsigned long flags;
391
392 spin_lock_irqsave(&priv->sta_lock, flags);
393
394 if (is_ap)
395 index = IWL_AP_ID;
396 else if (is_broadcast_ether_addr(addr))
397 index = priv->hw_setting.bcast_sta_id;
398 else
399 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
400 if (priv->stations[i].used &&
401 !compare_ether_addr(priv->stations[i].sta.sta.addr,
402 addr)) {
403 index = i;
404 break;
405 }
406
407 if (unlikely(index == IWL_INVALID_STATION))
408 goto out;
409
410 if (priv->stations[index].used) {
411 priv->stations[index].used = 0;
412 priv->num_stations--;
413 }
414
415 BUG_ON(priv->num_stations < 0);
416
417out:
418 spin_unlock_irqrestore(&priv->sta_lock, flags);
419 return 0;
420}
556f8db7 421#endif
6440adb5
CB		 422
423/**
424 * iwl3945_clear_stations_table - Clear the driver's station table
425 *
426 * NOTE: This does not clear or otherwise alter the device's station table.
427 */
bb8c093b 428static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
b481de9c
ZY		 429{
430 unsigned long flags;
431
432 spin_lock_irqsave(&priv->sta_lock, flags);
433
434 priv->num_stations = 0;
435 memset(priv->stations, 0, sizeof(priv->stations));
436
437 spin_unlock_irqrestore(&priv->sta_lock, flags);
438}
439
6440adb5
CB		 440/**
441 * iwl3945_add_station - Add station to station tables in driver and device
442 */
bb8c093b 443u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
b481de9c
ZY		 444{
445 int i;
446 int index = IWL_INVALID_STATION;
bb8c093b 447 struct iwl3945_station_entry *station;
b481de9c 448 unsigned long flags_spin;
c14c521e 449 u8 rate;
b481de9c
ZY		 450
451 spin_lock_irqsave(&priv->sta_lock, flags_spin);
452 if (is_ap)
453 index = IWL_AP_ID;
454 else if (is_broadcast_ether_addr(addr))
455 index = priv->hw_setting.bcast_sta_id;
456 else
457 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
458 if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
459 addr)) {
460 index = i;
461 break;
462 }
463
464 if (!priv->stations[i].used &&
465 index == IWL_INVALID_STATION)
466 index = i;
467 }
468
01ebd063 469 /* These two conditions has the same outcome but keep them separate
b481de9c
ZY		 470 since they have different meaning */
471 if (unlikely(index == IWL_INVALID_STATION)) {
472 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
473 return index;
474 }
475
476 if (priv->stations[index].used &&
477 !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
478 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
479 return index;
480 }
481
e174961c 482 IWL_DEBUG_ASSOC("Add STA ID %d: %pM\n", index, addr);
b481de9c
ZY		 483 station = &priv->stations[index];
484 station->used = 1;
485 priv->num_stations++;
486
6440adb5 487 /* Set up the REPLY_ADD_STA command to send to device */
bb8c093b 488 memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
b481de9c
ZY		 489 memcpy(station->sta.sta.addr, addr, ETH_ALEN);
490 station->sta.mode = 0;
491 station->sta.sta.sta_id = index;
492 station->sta.station_flags = 0;
493
8318d78a 494 if (priv->band == IEEE80211_BAND_5GHZ)
69946333
TW		 495 rate = IWL_RATE_6M_PLCP;
496 else
497 rate = IWL_RATE_1M_PLCP;
c14c521e
ZY		 498
499 /* Turn on both antennas for the station... */
500 station->sta.rate_n_flags =
bb8c093b 501 iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
c14c521e
ZY		 502 station->current_rate.rate_n_flags =
503 le16_to_cpu(station->sta.rate_n_flags);
504
b481de9c 505 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
6440adb5
CB		 506
507 /* Add station to device's station table */
bb8c093b 508 iwl3945_send_add_station(priv, &station->sta, flags);
b481de9c
ZY		 509 return index;
510
511}
512
513/*************** DRIVER STATUS FUNCTIONS *****/
514
bb8c093b 515static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
b481de9c
ZY		 516{
517 /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
518 * set but EXIT_PENDING is not */
519 return test_bit(STATUS_READY, &priv->status) &&
520 test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
521 !test_bit(STATUS_EXIT_PENDING, &priv->status);
522}
523
bb8c093b 524static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
b481de9c
ZY		 525{
526 return test_bit(STATUS_ALIVE, &priv->status);
527}
528
bb8c093b 529static inline int iwl3945_is_init(struct iwl3945_priv *priv)
b481de9c
ZY		 530{
531 return test_bit(STATUS_INIT, &priv->status);
532}
533
80fcc9e2
AG		 534static inline int iwl3945_is_rfkill_sw(struct iwl3945_priv *priv)
535{
536 return test_bit(STATUS_RF_KILL_SW, &priv->status);
537}
538
539static inline int iwl3945_is_rfkill_hw(struct iwl3945_priv *priv)
540{
541 return test_bit(STATUS_RF_KILL_HW, &priv->status);
542}
543
bb8c093b 544static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
b481de9c 545{
80fcc9e2
AG		 546 return iwl3945_is_rfkill_hw(priv) ||
547 iwl3945_is_rfkill_sw(priv);
b481de9c
ZY		 548}
549
bb8c093b 550static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
b481de9c
ZY		 551{
552
bb8c093b 553 if (iwl3945_is_rfkill(priv))
b481de9c
ZY		 554 return 0;
555
bb8c093b 556 return iwl3945_is_ready(priv);
b481de9c
ZY		 557}
558
559/*************** HOST COMMAND QUEUE FUNCTIONS *****/
560
561#define IWL_CMD(x) case x : return #x
562
563static const char *get_cmd_string(u8 cmd)
564{
565 switch (cmd) {
566 IWL_CMD(REPLY_ALIVE);
567 IWL_CMD(REPLY_ERROR);
568 IWL_CMD(REPLY_RXON);
569 IWL_CMD(REPLY_RXON_ASSOC);
570 IWL_CMD(REPLY_QOS_PARAM);
571 IWL_CMD(REPLY_RXON_TIMING);
572 IWL_CMD(REPLY_ADD_STA);
573 IWL_CMD(REPLY_REMOVE_STA);
574 IWL_CMD(REPLY_REMOVE_ALL_STA);
575 IWL_CMD(REPLY_3945_RX);
576 IWL_CMD(REPLY_TX);
577 IWL_CMD(REPLY_RATE_SCALE);
578 IWL_CMD(REPLY_LEDS_CMD);
579 IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
580 IWL_CMD(RADAR_NOTIFICATION);
581 IWL_CMD(REPLY_QUIET_CMD);
582 IWL_CMD(REPLY_CHANNEL_SWITCH);
583 IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
584 IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
585 IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
586 IWL_CMD(POWER_TABLE_CMD);
587 IWL_CMD(PM_SLEEP_NOTIFICATION);
588 IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
589 IWL_CMD(REPLY_SCAN_CMD);
590 IWL_CMD(REPLY_SCAN_ABORT_CMD);
591 IWL_CMD(SCAN_START_NOTIFICATION);
592 IWL_CMD(SCAN_RESULTS_NOTIFICATION);
593 IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
594 IWL_CMD(BEACON_NOTIFICATION);
595 IWL_CMD(REPLY_TX_BEACON);
596 IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
597 IWL_CMD(QUIET_NOTIFICATION);
598 IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
599 IWL_CMD(MEASURE_ABORT_NOTIFICATION);
600 IWL_CMD(REPLY_BT_CONFIG);
601 IWL_CMD(REPLY_STATISTICS_CMD);
602 IWL_CMD(STATISTICS_NOTIFICATION);
603 IWL_CMD(REPLY_CARD_STATE_CMD);
604 IWL_CMD(CARD_STATE_NOTIFICATION);
605 IWL_CMD(MISSED_BEACONS_NOTIFICATION);
606 default:
607 return "UNKNOWN";
608
609 }
610}
611
612#define HOST_COMPLETE_TIMEOUT (HZ / 2)
613
614/**
bb8c093b 615 * iwl3945_enqueue_hcmd - enqueue a uCode command
b481de9c
ZY		 616 * @priv: device private data point
617 * @cmd: a point to the ucode command structure
618 *
619 * The function returns < 0 values to indicate the operation is
620 * failed. On success, it turns the index (> 0) of command in the
621 * command queue.
622 */
bb8c093b 623static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c 624{
bb8c093b
CH		 625 struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
626 struct iwl3945_queue *q = &txq->q;
627 struct iwl3945_tfd_frame *tfd;
b481de9c 628 u32 *control_flags;
bb8c093b 629 struct iwl3945_cmd *out_cmd;
b481de9c
ZY		 630 u32 idx;
631 u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
632 dma_addr_t phys_addr;
633 int pad;
634 u16 count;
635 int ret;
636 unsigned long flags;
637
638 /* If any of the command structures end up being larger than
639 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
640 * we will need to increase the size of the TFD entries */
641 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
642 !(cmd->meta.flags & CMD_SIZE_HUGE));
643
c342a1b9
GG		 644
645 if (iwl3945_is_rfkill(priv)) {
646 IWL_DEBUG_INFO("Not sending command - RF KILL");
647 return -EIO;
648 }
649
bb8c093b 650 if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
b481de9c
ZY		 651 IWL_ERROR("No space for Tx\n");
652 return -ENOSPC;
653 }
654
655 spin_lock_irqsave(&priv->hcmd_lock, flags);
656
fc4b6853 657 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY		 658 memset(tfd, 0, sizeof(*tfd));
659
660 control_flags = (u32 *) tfd;
661
fc4b6853 662 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
b481de9c
ZY		 663 out_cmd = &txq->cmd[idx];
664
665 out_cmd->hdr.cmd = cmd->id;
666 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
667 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
668
669 /* At this point, the out_cmd now has all of the incoming cmd
670 * information */
671
672 out_cmd->hdr.flags = 0;
673 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
fc4b6853 674 INDEX_TO_SEQ(q->write_ptr));
b481de9c
ZY		 675 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
676 out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
677
678 phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
bb8c093b
CH		 679 offsetof(struct iwl3945_cmd, hdr);
680 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
b481de9c
ZY		 681
682 pad = U32_PAD(cmd->len);
683 count = TFD_CTL_COUNT_GET(*control_flags);
684 *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
685
686 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
687 "%d bytes at %d[%d]:%d\n",
688 get_cmd_string(out_cmd->hdr.cmd),
689 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
fc4b6853 690 fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
b481de9c
ZY		 691
692 txq->need_update = 1;
6440adb5
CB		 693
694 /* Increment and update queue's write index */
c54b679d 695 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
bb8c093b 696 ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 697
698 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
699 return ret ? ret : idx;
700}
701
bb8c093b 702static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c
ZY		 703{
704 int ret;
705
706 BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
707
708 /* An asynchronous command can not expect an SKB to be set. */
709 BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
710
711 /* An asynchronous command MUST have a callback. */
712 BUG_ON(!cmd->meta.u.callback);
713
714 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
715 return -EBUSY;
716
bb8c093b 717 ret = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c 718 if (ret < 0) {
bb8c093b 719 IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
b481de9c
ZY		 720 get_cmd_string(cmd->id), ret);
721 return ret;
722 }
723 return 0;
724}
725
bb8c093b 726static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c
ZY		 727{
728 int cmd_idx;
729 int ret;
b481de9c
ZY		 730
731 BUG_ON(cmd->meta.flags & CMD_ASYNC);
732
733 /* A synchronous command can not have a callback set. */
734 BUG_ON(cmd->meta.u.callback != NULL);
735
e5472978 736 if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) {
b481de9c
ZY		 737 IWL_ERROR("Error sending %s: Already sending a host command\n",
738 get_cmd_string(cmd->id));
e5472978
TW		 739 ret = -EBUSY;
740 goto out;
b481de9c
ZY		 741 }
742
743 set_bit(STATUS_HCMD_ACTIVE, &priv->status);
744
745 if (cmd->meta.flags & CMD_WANT_SKB)
746 cmd->meta.source = &cmd->meta;
747
bb8c093b 748 cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c
ZY		 749 if (cmd_idx < 0) {
750 ret = cmd_idx;
bb8c093b 751 IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
b481de9c
ZY		 752 get_cmd_string(cmd->id), ret);
753 goto out;
754 }
755
756 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
757 !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
758 HOST_COMPLETE_TIMEOUT);
759 if (!ret) {
760 if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
761 IWL_ERROR("Error sending %s: time out after %dms.\n",
762 get_cmd_string(cmd->id),
763 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
764
765 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
766 ret = -ETIMEDOUT;
767 goto cancel;
768 }
769 }
770
771 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
772 IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
773 get_cmd_string(cmd->id));
774 ret = -ECANCELED;
775 goto fail;
776 }
777 if (test_bit(STATUS_FW_ERROR, &priv->status)) {
778 IWL_DEBUG_INFO("Command %s failed: FW Error\n",
779 get_cmd_string(cmd->id));
780 ret = -EIO;
781 goto fail;
782 }
783 if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
784 IWL_ERROR("Error: Response NULL in '%s'\n",
785 get_cmd_string(cmd->id));
786 ret = -EIO;
787 goto out;
788 }
789
790 ret = 0;
791 goto out;
792
793cancel:
794 if (cmd->meta.flags & CMD_WANT_SKB) {
bb8c093b 795 struct iwl3945_cmd *qcmd;
b481de9c
ZY		 796
797 /* Cancel the CMD_WANT_SKB flag for the cmd in the
798 * TX cmd queue. Otherwise in case the cmd comes
799 * in later, it will possibly set an invalid
800 * address (cmd->meta.source). */
801 qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
802 qcmd->meta.flags &= ~CMD_WANT_SKB;
803 }
804fail:
805 if (cmd->meta.u.skb) {
806 dev_kfree_skb_any(cmd->meta.u.skb);
807 cmd->meta.u.skb = NULL;
808 }
809out:
e5472978 810 clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status);
b481de9c
ZY		 811 return ret;
812}
813
bb8c093b 814int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c 815{
b481de9c 816 if (cmd->meta.flags & CMD_ASYNC)
bb8c093b 817 return iwl3945_send_cmd_async(priv, cmd);
b481de9c 818
bb8c093b 819 return iwl3945_send_cmd_sync(priv, cmd);
b481de9c
ZY		 820}
821
bb8c093b 822int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
b481de9c 823{
bb8c093b 824 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 825 .id = id,
826 .len = len,
827 .data = data,
828 };
829
bb8c093b 830 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 831}
832
bb8c093b 833static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
b481de9c 834{
bb8c093b 835 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 836 .id = id,
837 .len = sizeof(val),
838 .data = &val,
839 };
840
bb8c093b 841 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 842}
843
bb8c093b 844int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
b481de9c 845{
bb8c093b 846 return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
b481de9c
ZY		 847}
848
b481de9c 849/**
bb8c093b 850 * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
8318d78a
JB		 851 * @band: 2.4 or 5 GHz band
852 * @channel: Any channel valid for the requested band
b481de9c 853
8318d78a 854 * In addition to setting the staging RXON, priv->band is also set.
b481de9c
ZY		 855 *
856 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
8318d78a 857 * in the staging RXON flag structure based on the band
b481de9c 858 */
8318d78a
JB		 859static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv,
860 enum ieee80211_band band,
861 u16 channel)
b481de9c 862{
8318d78a 863 if (!iwl3945_get_channel_info(priv, band, channel)) {
b481de9c 864 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
8318d78a 865 channel, band);
b481de9c
ZY		 866 return -EINVAL;
867 }
868
869 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
8318d78a 870 (priv->band == band))
b481de9c
ZY		 871 return 0;
872
873 priv->staging_rxon.channel = cpu_to_le16(channel);
8318d78a 874 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 875 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
876 else
877 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
878
8318d78a 879 priv->band = band;
b481de9c 880
8318d78a 881 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
b481de9c
ZY		 882
883 return 0;
884}
885
886/**
bb8c093b 887 * iwl3945_check_rxon_cmd - validate RXON structure is valid
b481de9c
ZY		 888 *
889 * NOTE: This is really only useful during development and can eventually
890 * be #ifdef'd out once the driver is stable and folks aren't actively
891 * making changes
892 */
bb8c093b 893static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon)
b481de9c
ZY		 894{
895 int error = 0;
896 int counter = 1;
897
898 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
899 error |= le32_to_cpu(rxon->flags &
900 (RXON_FLG_TGJ_NARROW_BAND_MSK |
901 RXON_FLG_RADAR_DETECT_MSK));
902 if (error)
903 IWL_WARNING("check 24G fields %d | %d\n",
904 counter++, error);
905 } else {
906 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
907 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
908 if (error)
909 IWL_WARNING("check 52 fields %d | %d\n",
910 counter++, error);
911 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
912 if (error)
913 IWL_WARNING("check 52 CCK %d | %d\n",
914 counter++, error);
915 }
916 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
917 if (error)
918 IWL_WARNING("check mac addr %d | %d\n", counter++, error);
919
920 /* make sure basic rates 6Mbps and 1Mbps are supported */
921 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
922 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
923 if (error)
924 IWL_WARNING("check basic rate %d | %d\n", counter++, error);
925
926 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
927 if (error)
928 IWL_WARNING("check assoc id %d | %d\n", counter++, error);
929
930 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
931 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
932 if (error)
933 IWL_WARNING("check CCK and short slot %d | %d\n",
934 counter++, error);
935
936 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
937 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
938 if (error)
939 IWL_WARNING("check CCK & auto detect %d | %d\n",
940 counter++, error);
941
942 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
943 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
944 if (error)
945 IWL_WARNING("check TGG and auto detect %d | %d\n",
946 counter++, error);
947
948 if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
949 error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
950 RXON_FLG_ANT_A_MSK)) == 0);
951 if (error)
952 IWL_WARNING("check antenna %d %d\n", counter++, error);
953
954 if (error)
955 IWL_WARNING("Tuning to channel %d\n",
956 le16_to_cpu(rxon->channel));
957
958 if (error) {
bb8c093b 959 IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
b481de9c
ZY		 960 return -1;
961 }
962 return 0;
963}
964
965/**
9fbab516 966 * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
01ebd063 967 * @priv: staging_rxon is compared to active_rxon
b481de9c 968 *
9fbab516
BC		 969 * If the RXON structure is changing enough to require a new tune,
970 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
971 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
b481de9c 972 */
bb8c093b 973static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
b481de9c
ZY		 974{
975
976 /* These items are only settable from the full RXON command */
5d1e2325 977 if (!(iwl3945_is_associated(priv)) ||
b481de9c
ZY		 978 compare_ether_addr(priv->staging_rxon.bssid_addr,
979 priv->active_rxon.bssid_addr) ||
980 compare_ether_addr(priv->staging_rxon.node_addr,
981 priv->active_rxon.node_addr) ||
982 compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
983 priv->active_rxon.wlap_bssid_addr) ||
984 (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
985 (priv->staging_rxon.channel != priv->active_rxon.channel) ||
986 (priv->staging_rxon.air_propagation !=
987 priv->active_rxon.air_propagation) ||
988 (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
989 return 1;
990
991 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
992 * be updated with the RXON_ASSOC command -- however only some
993 * flag transitions are allowed using RXON_ASSOC */
994
995 /* Check if we are not switching bands */
996 if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
997 (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
998 return 1;
999
1000 /* Check if we are switching association toggle */
1001 if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
1002 (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
1003 return 1;
1004
1005 return 0;
1006}
1007
bb8c093b 1008static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
b481de9c
ZY		 1009{
1010 int rc = 0;
bb8c093b
CH		 1011 struct iwl3945_rx_packet *res = NULL;
1012 struct iwl3945_rxon_assoc_cmd rxon_assoc;
1013 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 1014 .id = REPLY_RXON_ASSOC,
1015 .len = sizeof(rxon_assoc),
1016 .meta.flags = CMD_WANT_SKB,
1017 .data = &rxon_assoc,
1018 };
bb8c093b
CH		 1019 const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
1020 const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
b481de9c
ZY		 1021
1022 if ((rxon1->flags == rxon2->flags) &&
1023 (rxon1->filter_flags == rxon2->filter_flags) &&
1024 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1025 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1026 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
1027 return 0;
1028 }
1029
1030 rxon_assoc.flags = priv->staging_rxon.flags;
1031 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1032 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1033 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1034 rxon_assoc.reserved = 0;
1035
bb8c093b 1036 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 1037 if (rc)
1038 return rc;
1039
bb8c093b 1040 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1041 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1042 IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
1043 rc = -EIO;
1044 }
1045
1046 priv->alloc_rxb_skb--;
1047 dev_kfree_skb_any(cmd.meta.u.skb);
1048
1049 return rc;
1050}
1051
1052/**
bb8c093b 1053 * iwl3945_commit_rxon - commit staging_rxon to hardware
b481de9c 1054 *
01ebd063 1055 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
ZY		 1056 * the active_rxon structure is updated with the new data. This
1057 * function correctly transitions out of the RXON_ASSOC_MSK state if
1058 * a HW tune is required based on the RXON structure changes.
1059 */
bb8c093b 1060static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
b481de9c
ZY		 1061{
1062 /* cast away the const for active_rxon in this function */
bb8c093b 1063 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
b481de9c
ZY		 1064 int rc = 0;
1065
bb8c093b 1066 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 1067 return -1;
1068
1069 /* always get timestamp with Rx frame */
1070 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
1071
1072 /* select antenna */
1073 priv->staging_rxon.flags &=
1074 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1075 priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
1076
bb8c093b 1077 rc = iwl3945_check_rxon_cmd(&priv->staging_rxon);
b481de9c
ZY		 1078 if (rc) {
1079 IWL_ERROR("Invalid RXON configuration. Not committing.\n");
1080 return -EINVAL;
1081 }
1082
1083 /* If we don't need to send a full RXON, we can use
bb8c093b 1084 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 1085 * and other flags for the current radio configuration. */
bb8c093b
CH		 1086 if (!iwl3945_full_rxon_required(priv)) {
1087 rc = iwl3945_send_rxon_assoc(priv);
b481de9c
ZY		 1088 if (rc) {
1089 IWL_ERROR("Error setting RXON_ASSOC "
1090 "configuration (%d).\n", rc);
1091 return rc;
1092 }
1093
1094 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1095
1096 return 0;
1097 }
1098
1099 /* If we are currently associated and the new config requires
1100 * an RXON_ASSOC and the new config wants the associated mask enabled,
1101 * we must clear the associated from the active configuration
1102 * before we apply the new config */
bb8c093b 1103 if (iwl3945_is_associated(priv) &&
b481de9c
ZY		 1104 (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
1105 IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
1106 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1107
bb8c093b
CH		 1108 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
1109 sizeof(struct iwl3945_rxon_cmd),
b481de9c
ZY		 1110 &priv->active_rxon);
1111
1112 /* If the mask clearing failed then we set
1113 * active_rxon back to what it was previously */
1114 if (rc) {
1115 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1116 IWL_ERROR("Error clearing ASSOC_MSK on current "
1117 "configuration (%d).\n", rc);
1118 return rc;
1119 }
b481de9c
ZY		 1120 }
1121
1122 IWL_DEBUG_INFO("Sending RXON\n"
1123 "* with%s RXON_FILTER_ASSOC_MSK\n"
1124 "* channel = %d\n"
e174961c 1125 "* bssid = %pM\n",
b481de9c
ZY		 1126 ((priv->staging_rxon.filter_flags &
1127 RXON_FILTER_ASSOC_MSK) ? "" : "out"),
1128 le16_to_cpu(priv->staging_rxon.channel),
e174961c 1129 priv->staging_rxon.bssid_addr);
b481de9c
ZY		 1130
1131 /* Apply the new configuration */
bb8c093b
CH		 1132 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
1133 sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
b481de9c
ZY		 1134 if (rc) {
1135 IWL_ERROR("Error setting new configuration (%d).\n", rc);
1136 return rc;
1137 }
1138
1139 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1140
bb8c093b 1141 iwl3945_clear_stations_table(priv);
556f8db7 1142
b481de9c
ZY		 1143 /* If we issue a new RXON command which required a tune then we must
1144 * send a new TXPOWER command or we won't be able to Tx any frames */
bb8c093b 1145 rc = iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 1146 if (rc) {
1147 IWL_ERROR("Error setting Tx power (%d).\n", rc);
1148 return rc;
1149 }
1150
1151 /* Add the broadcast address so we can send broadcast frames */
bb8c093b 1152 if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
b481de9c
ZY		 1153 IWL_INVALID_STATION) {
1154 IWL_ERROR("Error adding BROADCAST address for transmit.\n");
1155 return -EIO;
1156 }
1157
1158 /* If we have set the ASSOC_MSK and we are in BSS mode then
1159 * add the IWL_AP_ID to the station rate table */
bb8c093b 1160 if (iwl3945_is_associated(priv) &&
05c914fe 1161 (priv->iw_mode == NL80211_IFTYPE_STATION))
bb8c093b 1162 if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
b481de9c
ZY		 1163 == IWL_INVALID_STATION) {
1164 IWL_ERROR("Error adding AP address for transmit.\n");
1165 return -EIO;
1166 }
1167
8318d78a 1168 /* Init the hardware's rate fallback order based on the band */
b481de9c
ZY		 1169 rc = iwl3945_init_hw_rate_table(priv);
1170 if (rc) {
1171 IWL_ERROR("Error setting HW rate table: %02X\n", rc);
1172 return -EIO;
1173 }
1174
1175 return 0;
1176}
1177
bb8c093b 1178static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
b481de9c 1179{
bb8c093b 1180 struct iwl3945_bt_cmd bt_cmd = {
b481de9c
ZY		 1181 .flags = 3,
1182 .lead_time = 0xAA,
1183 .max_kill = 1,
1184 .kill_ack_mask = 0,
1185 .kill_cts_mask = 0,
1186 };
1187
bb8c093b
CH		 1188 return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1189 sizeof(struct iwl3945_bt_cmd), &bt_cmd);
b481de9c
ZY		 1190}
1191
bb8c093b 1192static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
b481de9c
ZY		 1193{
1194 int rc = 0;
bb8c093b
CH		 1195 struct iwl3945_rx_packet *res;
1196 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 1197 .id = REPLY_SCAN_ABORT_CMD,
1198 .meta.flags = CMD_WANT_SKB,
1199 };
1200
1201 /* If there isn't a scan actively going on in the hardware
1202 * then we are in between scan bands and not actually
1203 * actively scanning, so don't send the abort command */
1204 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
1205 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1206 return 0;
1207 }
1208
bb8c093b 1209 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 1210 if (rc) {
1211 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1212 return rc;
1213 }
1214
bb8c093b 1215 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1216 if (res->u.status != CAN_ABORT_STATUS) {
1217 /* The scan abort will return 1 for success or
1218 * 2 for "failure". A failure condition can be
1219 * due to simply not being in an active scan which
1220 * can occur if we send the scan abort before we
1221 * the microcode has notified us that a scan is
1222 * completed. */
1223 IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
1224 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1225 clear_bit(STATUS_SCAN_HW, &priv->status);
1226 }
1227
1228 dev_kfree_skb_any(cmd.meta.u.skb);
1229
1230 return rc;
1231}
1232
bb8c093b
CH		 1233static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
1234 struct iwl3945_cmd *cmd,
b481de9c
ZY		 1235 struct sk_buff *skb)
1236{
1237 return 1;
1238}
1239
1240/*
1241 * CARD_STATE_CMD
1242 *
9fbab516 1243 * Use: Sets the device's internal card state to enable, disable, or halt
b481de9c
ZY		 1244 *
1245 * When in the 'enable' state the card operates as normal.
1246 * When in the 'disable' state, the card enters into a low power mode.
1247 * When in the 'halt' state, the card is shut down and must be fully
1248 * restarted to come back on.
1249 */
bb8c093b 1250static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
b481de9c 1251{
bb8c093b 1252 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 1253 .id = REPLY_CARD_STATE_CMD,
1254 .len = sizeof(u32),
1255 .data = &flags,
1256 .meta.flags = meta_flag,
1257 };
1258
1259 if (meta_flag & CMD_ASYNC)
bb8c093b 1260 cmd.meta.u.callback = iwl3945_card_state_sync_callback;
b481de9c 1261
bb8c093b 1262 return iwl3945_send_cmd(priv, &cmd);
b481de9c
ZY		 1263}
1264
bb8c093b
CH		 1265static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
1266 struct iwl3945_cmd *cmd, struct sk_buff *skb)
b481de9c 1267{
bb8c093b 1268 struct iwl3945_rx_packet *res = NULL;
b481de9c
ZY		 1269
1270 if (!skb) {
1271 IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
1272 return 1;
1273 }
1274
bb8c093b 1275 res = (struct iwl3945_rx_packet *)skb->data;
b481de9c
ZY		 1276 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1277 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1278 res->hdr.flags);
1279 return 1;
1280 }
1281
1282 switch (res->u.add_sta.status) {
1283 case ADD_STA_SUCCESS_MSK:
1284 break;
1285 default:
1286 break;
1287 }
1288
1289 /* We didn't cache the SKB; let the caller free it */
1290 return 1;
1291}
1292
bb8c093b
CH		 1293int iwl3945_send_add_station(struct iwl3945_priv *priv,
1294 struct iwl3945_addsta_cmd *sta, u8 flags)
b481de9c 1295{
bb8c093b 1296 struct iwl3945_rx_packet *res = NULL;
b481de9c 1297 int rc = 0;
bb8c093b 1298 struct iwl3945_host_cmd cmd = {
b481de9c 1299 .id = REPLY_ADD_STA,
bb8c093b 1300 .len = sizeof(struct iwl3945_addsta_cmd),
b481de9c
ZY		 1301 .meta.flags = flags,
1302 .data = sta,
1303 };
1304
1305 if (flags & CMD_ASYNC)
bb8c093b 1306 cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
b481de9c
ZY		 1307 else
1308 cmd.meta.flags |= CMD_WANT_SKB;
1309
bb8c093b 1310 rc = iwl3945_send_cmd(priv, &cmd);
b481de9c
ZY		 1311
1312 if (rc || (flags & CMD_ASYNC))
1313 return rc;
1314
bb8c093b 1315 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1316 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1317 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1318 res->hdr.flags);
1319 rc = -EIO;
1320 }
1321
1322 if (rc == 0) {
1323 switch (res->u.add_sta.status) {
1324 case ADD_STA_SUCCESS_MSK:
1325 IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
1326 break;
1327 default:
1328 rc = -EIO;
1329 IWL_WARNING("REPLY_ADD_STA failed\n");
1330 break;
1331 }
1332 }
1333
1334 priv->alloc_rxb_skb--;
1335 dev_kfree_skb_any(cmd.meta.u.skb);
1336
1337 return rc;
1338}
1339
bb8c093b 1340static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
b481de9c
ZY		 1341 struct ieee80211_key_conf *keyconf,
1342 u8 sta_id)
1343{
1344 unsigned long flags;
1345 __le16 key_flags = 0;
1346
1347 switch (keyconf->alg) {
1348 case ALG_CCMP:
1349 key_flags |= STA_KEY_FLG_CCMP;
1350 key_flags |= cpu_to_le16(
1351 keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
1352 key_flags &= ~STA_KEY_FLG_INVALID;
1353 break;
1354 case ALG_TKIP:
1355 case ALG_WEP:
b481de9c
ZY		 1356 default:
1357 return -EINVAL;
1358 }
1359 spin_lock_irqsave(&priv->sta_lock, flags);
1360 priv->stations[sta_id].keyinfo.alg = keyconf->alg;
1361 priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
1362 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
1363 keyconf->keylen);
1364
1365 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
1366 keyconf->keylen);
1367 priv->stations[sta_id].sta.key.key_flags = key_flags;
1368 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1369 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1370
1371 spin_unlock_irqrestore(&priv->sta_lock, flags);
1372
1373 IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
bb8c093b 1374 iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY		 1375 return 0;
1376}
1377
bb8c093b 1378static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
b481de9c
ZY		 1379{
1380 unsigned long flags;
1381
1382 spin_lock_irqsave(&priv->sta_lock, flags);
bb8c093b
CH		 1383 memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
1384 memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl3945_keyinfo));
b481de9c
ZY		 1385 priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
1386 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1387 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1388 spin_unlock_irqrestore(&priv->sta_lock, flags);
1389
1390 IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
bb8c093b 1391 iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY		 1392 return 0;
1393}
1394
bb8c093b 1395static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
b481de9c
ZY		 1396{
1397 struct list_head *element;
1398
1399 IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
1400 priv->frames_count);
1401
1402 while (!list_empty(&priv->free_frames)) {
1403 element = priv->free_frames.next;
1404 list_del(element);
bb8c093b 1405 kfree(list_entry(element, struct iwl3945_frame, list));
b481de9c
ZY		 1406 priv->frames_count--;
1407 }
1408
1409 if (priv->frames_count) {
1410 IWL_WARNING("%d frames still in use. Did we lose one?\n",
1411 priv->frames_count);
1412 priv->frames_count = 0;
1413 }
1414}
1415
bb8c093b 1416static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
b481de9c 1417{
bb8c093b 1418 struct iwl3945_frame *frame;
b481de9c
ZY		 1419 struct list_head *element;
1420 if (list_empty(&priv->free_frames)) {
1421 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
1422 if (!frame) {
1423 IWL_ERROR("Could not allocate frame!\n");
1424 return NULL;
1425 }
1426
1427 priv->frames_count++;
1428 return frame;
1429 }
1430
1431 element = priv->free_frames.next;
1432 list_del(element);
bb8c093b 1433 return list_entry(element, struct iwl3945_frame, list);
b481de9c
ZY		 1434}
1435
bb8c093b 1436static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
b481de9c
ZY		 1437{
1438 memset(frame, 0, sizeof(*frame));
1439 list_add(&frame->list, &priv->free_frames);
1440}
1441
bb8c093b 1442unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
b481de9c
ZY		 1443 struct ieee80211_hdr *hdr,
1444 const u8 *dest, int left)
1445{
1446
bb8c093b 1447 if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB		 1448 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
1449 (priv->iw_mode != NL80211_IFTYPE_AP)))
b481de9c
ZY		 1450 return 0;
1451
1452 if (priv->ibss_beacon->len > left)
1453 return 0;
1454
1455 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
1456
1457 return priv->ibss_beacon->len;
1458}
1459
bb8c093b 1460static u8 iwl3945_rate_get_lowest_plcp(int rate_mask)
b481de9c
ZY		 1461{
1462 u8 i;
1463
1464 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
bb8c093b 1465 i = iwl3945_rates[i].next_ieee) {
b481de9c 1466 if (rate_mask & (1 << i))
bb8c093b 1467 return iwl3945_rates[i].plcp;
b481de9c
ZY		 1468 }
1469
1470 return IWL_RATE_INVALID;
1471}
1472
bb8c093b 1473static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
b481de9c 1474{
bb8c093b 1475 struct iwl3945_frame *frame;
b481de9c
ZY		 1476 unsigned int frame_size;
1477 int rc;
1478 u8 rate;
1479
bb8c093b 1480 frame = iwl3945_get_free_frame(priv);
b481de9c
ZY		 1481
1482 if (!frame) {
1483 IWL_ERROR("Could not obtain free frame buffer for beacon "
1484 "command.\n");
1485 return -ENOMEM;
1486 }
1487
1488 if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) {
bb8c093b 1489 rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic &
b481de9c
ZY		 1490 0xFF0);
1491 if (rate == IWL_INVALID_RATE)
1492 rate = IWL_RATE_6M_PLCP;
1493 } else {
bb8c093b 1494 rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic & 0xF);
b481de9c
ZY		 1495 if (rate == IWL_INVALID_RATE)
1496 rate = IWL_RATE_1M_PLCP;
1497 }
1498
bb8c093b 1499 frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 1500
bb8c093b 1501 rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY		 1502 &frame->u.cmd[0]);
1503
bb8c093b 1504 iwl3945_free_frame(priv, frame);
b481de9c
ZY		 1505
1506 return rc;
1507}
1508
1509/******************************************************************************
1510 *
1511 * EEPROM related functions
1512 *
1513 ******************************************************************************/
1514
bb8c093b 1515static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
b481de9c
ZY		 1516{
1517 memcpy(mac, priv->eeprom.mac_address, 6);
1518}
1519
74a3a250
RC		 1520/*
1521 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
1522 * embedded controller) as EEPROM reader; each read is a series of pulses
1523 * to/from the EEPROM chip, not a single event, so even reads could conflict
1524 * if they weren't arbitrated by some ownership mechanism. Here, the driver
1525 * simply claims ownership, which should be safe when this function is called
1526 * (i.e. before loading uCode!).
1527 */
1528static inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv)
1529{
1530 _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
1531 return 0;
1532}
1533
b481de9c 1534/**
bb8c093b 1535 * iwl3945_eeprom_init - read EEPROM contents
b481de9c 1536 *
6440adb5 1537 * Load the EEPROM contents from adapter into priv->eeprom
b481de9c
ZY		 1538 *
1539 * NOTE: This routine uses the non-debug IO access functions.
1540 */
bb8c093b 1541int iwl3945_eeprom_init(struct iwl3945_priv *priv)
b481de9c 1542{
58ff6d4d 1543 u16 *e = (u16 *)&priv->eeprom;
bb8c093b 1544 u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
b481de9c
ZY		 1545 u32 r;
1546 int sz = sizeof(priv->eeprom);
1547 int rc;
1548 int i;
1549 u16 addr;
1550
1551 /* The EEPROM structure has several padding buffers within it
1552 * and when adding new EEPROM maps is subject to programmer errors
1553 * which may be very difficult to identify without explicitly
1554 * checking the resulting size of the eeprom map. */
1555 BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
1556
1557 if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
6f147926 1558 IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x\n", gp);
b481de9c
ZY		 1559 return -ENOENT;
1560 }
1561
6440adb5 1562 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
bb8c093b 1563 rc = iwl3945_eeprom_acquire_semaphore(priv);
b481de9c 1564 if (rc < 0) {
91e17473 1565 IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
b481de9c
ZY		 1566 return -ENOENT;
1567 }
1568
1569 /* eeprom is an array of 16bit values */
1570 for (addr = 0; addr < sz; addr += sizeof(u16)) {
bb8c093b
CH		 1571 _iwl3945_write32(priv, CSR_EEPROM_REG, addr << 1);
1572 _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
b481de9c
ZY		 1573
1574 for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
1575 i += IWL_EEPROM_ACCESS_DELAY) {
bb8c093b 1576 r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
b481de9c
ZY		 1577 if (r & CSR_EEPROM_REG_READ_VALID_MSK)
1578 break;
1579 udelay(IWL_EEPROM_ACCESS_DELAY);
1580 }
1581
1582 if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) {
6f147926 1583 IWL_ERROR("Time out reading EEPROM[%d]\n", addr);
b481de9c
ZY		 1584 return -ETIMEDOUT;
1585 }
58ff6d4d 1586 e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
b481de9c
ZY		 1587 }
1588
1589 return 0;
1590}
1591
bb8c093b 1592static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
b481de9c
ZY		 1593{
1594 if (priv->hw_setting.shared_virt)
1595 pci_free_consistent(priv->pci_dev,
bb8c093b 1596 sizeof(struct iwl3945_shared),
b481de9c
ZY		 1597 priv->hw_setting.shared_virt,
1598 priv->hw_setting.shared_phys);
1599}
1600
1601/**
bb8c093b 1602 * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
b481de9c
ZY		 1603 *
1604 * return : set the bit for each supported rate insert in ie
1605 */
bb8c093b 1606static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
c7c46676 1607 u16 basic_rate, int *left)
b481de9c
ZY		 1608{
1609 u16 ret_rates = 0, bit;
1610 int i;
c7c46676
TW		 1611 u8 *cnt = ie;
1612 u8 *rates = ie + 1;
b481de9c
ZY		 1613
1614 for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
1615 if (bit & supported_rate) {
1616 ret_rates |= bit;
bb8c093b 1617 rates[*cnt] = iwl3945_rates[i].ieee |
c7c46676
TW		 1618 ((bit & basic_rate) ? 0x80 : 0x00);
1619 (*cnt)++;
1620 (*left)--;
1621 if ((*left <= 0) ||
1622 (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
b481de9c
ZY		 1623 break;
1624 }
1625 }
1626
1627 return ret_rates;
1628}
1629
1630/**
bb8c093b 1631 * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
b481de9c 1632 */
bb8c093b 1633static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
b481de9c
ZY		 1634 struct ieee80211_mgmt *frame,
1635 int left, int is_direct)
1636{
1637 int len = 0;
1638 u8 *pos = NULL;
c7c46676 1639 u16 active_rates, ret_rates, cck_rates;
b481de9c
ZY		 1640
1641 /* Make sure there is enough space for the probe request,
1642 * two mandatory IEs and the data */
1643 left -= 24;
1644 if (left < 0)
1645 return 0;
1646 len += 24;
1647
1648 frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
bb8c093b 1649 memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
b481de9c 1650 memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
bb8c093b 1651 memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
b481de9c
ZY		 1652 frame->seq_ctrl = 0;
1653
1654 /* fill in our indirect SSID IE */
1655 /* ...next IE... */
1656
1657 left -= 2;
1658 if (left < 0)
1659 return 0;
1660 len += 2;
1661 pos = &(frame->u.probe_req.variable[0]);
1662 *pos++ = WLAN_EID_SSID;
1663 *pos++ = 0;
1664
1665 /* fill in our direct SSID IE... */
1666 if (is_direct) {
1667 /* ...next IE... */
1668 left -= 2 + priv->essid_len;
1669 if (left < 0)
1670 return 0;
1671 /* ... fill it in... */
1672 *pos++ = WLAN_EID_SSID;
1673 *pos++ = priv->essid_len;
1674 memcpy(pos, priv->essid, priv->essid_len);
1675 pos += priv->essid_len;
1676 len += 2 + priv->essid_len;
1677 }
1678
1679 /* fill in supported rate */
1680 /* ...next IE... */
1681 left -= 2;
1682 if (left < 0)
1683 return 0;
c7c46676 1684
b481de9c
ZY		 1685 /* ... fill it in... */
1686 *pos++ = WLAN_EID_SUPP_RATES;
1687 *pos = 0;
c7c46676
TW		 1688
1689 priv->active_rate = priv->rates_mask;
1690 active_rates = priv->active_rate;
b481de9c
ZY		 1691 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1692
c7c46676 1693 cck_rates = IWL_CCK_RATES_MASK & active_rates;
bb8c093b 1694 ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
c7c46676
TW		 1695 priv->active_rate_basic, &left);
1696 active_rates &= ~ret_rates;
1697
bb8c093b 1698 ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676
TW		 1699 priv->active_rate_basic, &left);
1700 active_rates &= ~ret_rates;
1701
b481de9c
ZY		 1702 len += 2 + *pos;
1703 pos += (*pos) + 1;
c7c46676 1704 if (active_rates == 0)
b481de9c
ZY		 1705 goto fill_end;
1706
1707 /* fill in supported extended rate */
1708 /* ...next IE... */
1709 left -= 2;
1710 if (left < 0)
1711 return 0;
1712 /* ... fill it in... */
1713 *pos++ = WLAN_EID_EXT_SUPP_RATES;
1714 *pos = 0;
bb8c093b 1715 iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676 1716 priv->active_rate_basic, &left);
b481de9c
ZY		 1717 if (*pos > 0)
1718 len += 2 + *pos;
1719
1720 fill_end:
1721 return (u16)len;
1722}
1723
1724/*
1725 * QoS support
1726*/
bb8c093b
CH		 1727static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
1728 struct iwl3945_qosparam_cmd *qos)
b481de9c
ZY		 1729{
1730
bb8c093b
CH		 1731 return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
1732 sizeof(struct iwl3945_qosparam_cmd), qos);
b481de9c
ZY		 1733}
1734
bb8c093b 1735static void iwl3945_reset_qos(struct iwl3945_priv *priv)
b481de9c
ZY		 1736{
1737 u16 cw_min = 15;
1738 u16 cw_max = 1023;
1739 u8 aifs = 2;
1740 u8 is_legacy = 0;
1741 unsigned long flags;
1742 int i;
1743
1744 spin_lock_irqsave(&priv->lock, flags);
1745 priv->qos_data.qos_active = 0;
1746
05c914fe 1747 if (priv->iw_mode == NL80211_IFTYPE_ADHOC) {
b481de9c
ZY		 1748 if (priv->qos_data.qos_enable)
1749 priv->qos_data.qos_active = 1;
1750 if (!(priv->active_rate & 0xfff0)) {
1751 cw_min = 31;
1752 is_legacy = 1;
1753 }
05c914fe 1754 } else if (priv->iw_mode == NL80211_IFTYPE_AP) {
b481de9c
ZY		 1755 if (priv->qos_data.qos_enable)
1756 priv->qos_data.qos_active = 1;
1757 } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
1758 cw_min = 31;
1759 is_legacy = 1;
1760 }
1761
1762 if (priv->qos_data.qos_active)
1763 aifs = 3;
1764
1765 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
1766 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
1767 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
1768 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
1769 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
1770
1771 if (priv->qos_data.qos_active) {
1772 i = 1;
1773 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
1774 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
1775 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
1776 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
1777 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1778
1779 i = 2;
1780 priv->qos_data.def_qos_parm.ac[i].cw_min =
1781 cpu_to_le16((cw_min + 1) / 2 - 1);
1782 priv->qos_data.def_qos_parm.ac[i].cw_max =
1783 cpu_to_le16(cw_max);
1784 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1785 if (is_legacy)
1786 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1787 cpu_to_le16(6016);
1788 else
1789 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1790 cpu_to_le16(3008);
1791 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1792
1793 i = 3;
1794 priv->qos_data.def_qos_parm.ac[i].cw_min =
1795 cpu_to_le16((cw_min + 1) / 4 - 1);
1796 priv->qos_data.def_qos_parm.ac[i].cw_max =
1797 cpu_to_le16((cw_max + 1) / 2 - 1);
1798 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1799 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1800 if (is_legacy)
1801 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1802 cpu_to_le16(3264);
1803 else
1804 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1805 cpu_to_le16(1504);
1806 } else {
1807 for (i = 1; i < 4; i++) {
1808 priv->qos_data.def_qos_parm.ac[i].cw_min =
1809 cpu_to_le16(cw_min);
1810 priv->qos_data.def_qos_parm.ac[i].cw_max =
1811 cpu_to_le16(cw_max);
1812 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
1813 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
1814 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1815 }
1816 }
1817 IWL_DEBUG_QOS("set QoS to default \n");
1818
1819 spin_unlock_irqrestore(&priv->lock, flags);
1820}
1821
bb8c093b 1822static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
b481de9c
ZY		 1823{
1824 unsigned long flags;
1825
b481de9c
ZY		 1826 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1827 return;
1828
1829 if (!priv->qos_data.qos_enable)
1830 return;
1831
1832 spin_lock_irqsave(&priv->lock, flags);
1833 priv->qos_data.def_qos_parm.qos_flags = 0;
1834
1835 if (priv->qos_data.qos_cap.q_AP.queue_request &&
1836 !priv->qos_data.qos_cap.q_AP.txop_request)
1837 priv->qos_data.def_qos_parm.qos_flags |=
1838 QOS_PARAM_FLG_TXOP_TYPE_MSK;
1839
1840 if (priv->qos_data.qos_active)
1841 priv->qos_data.def_qos_parm.qos_flags |=
1842 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
1843
1844 spin_unlock_irqrestore(&priv->lock, flags);
1845
bb8c093b 1846 if (force || iwl3945_is_associated(priv)) {
b481de9c
ZY		 1847 IWL_DEBUG_QOS("send QoS cmd with Qos active %d \n",
1848 priv->qos_data.qos_active);
1849
bb8c093b 1850 iwl3945_send_qos_params_command(priv,
b481de9c
ZY		 1851 &(priv->qos_data.def_qos_parm));
1852 }
1853}
1854
b481de9c
ZY		 1855/*
1856 * Power management (not Tx power!) functions
1857 */
1858#define MSEC_TO_USEC 1024
1859
1860#define NOSLP __constant_cpu_to_le32(0)
1861#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK
1862#define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
1863#define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
1864 __constant_cpu_to_le32(X1), \
1865 __constant_cpu_to_le32(X2), \
1866 __constant_cpu_to_le32(X3), \
1867 __constant_cpu_to_le32(X4)}
1868
1869
1870/* default power management (not Tx power) table values */
1871/* for tim 0-10 */
bb8c093b 1872static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = {
b481de9c
ZY		 1873 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1874 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
1875 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
1876 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
1877 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
1878 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
1879};
1880
1881/* for tim > 10 */
bb8c093b 1882static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = {
b481de9c
ZY		 1883 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1884 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
1885 SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
1886 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
1887 SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
1888 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
1889 SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
1890 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
1891 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
1892 SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
1893};
1894
bb8c093b 1895int iwl3945_power_init_handle(struct iwl3945_priv *priv)
b481de9c
ZY		 1896{
1897 int rc = 0, i;
bb8c093b
CH		 1898 struct iwl3945_power_mgr *pow_data;
1899 int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC;
b481de9c
ZY		 1900 u16 pci_pm;
1901
1902 IWL_DEBUG_POWER("Initialize power \n");
1903
1904 pow_data = &(priv->power_data);
1905
1906 memset(pow_data, 0, sizeof(*pow_data));
1907
1908 pow_data->active_index = IWL_POWER_RANGE_0;
1909 pow_data->dtim_val = 0xffff;
1910
1911 memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
1912 memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
1913
1914 rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
1915 if (rc != 0)
1916 return 0;
1917 else {
bb8c093b 1918 struct iwl3945_powertable_cmd *cmd;
b481de9c
ZY		 1919
1920 IWL_DEBUG_POWER("adjust power command flags\n");
1921
1922 for (i = 0; i < IWL_POWER_AC; i++) {
1923 cmd = &pow_data->pwr_range_0[i].cmd;
1924
1925 if (pci_pm & 0x1)
1926 cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
1927 else
1928 cmd->flags |= IWL_POWER_PCI_PM_MSK;
1929 }
1930 }
1931 return rc;
1932}
1933
bb8c093b
CH		 1934static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
1935 struct iwl3945_powertable_cmd *cmd, u32 mode)
b481de9c
ZY		 1936{
1937 int rc = 0, i;
1938 u8 skip;
1939 u32 max_sleep = 0;
bb8c093b 1940 struct iwl3945_power_vec_entry *range;
b481de9c 1941 u8 period = 0;
bb8c093b 1942 struct iwl3945_power_mgr *pow_data;
b481de9c
ZY		 1943
1944 if (mode > IWL_POWER_INDEX_5) {
1945 IWL_DEBUG_POWER("Error invalid power mode \n");
1946 return -1;
1947 }
1948 pow_data = &(priv->power_data);
1949
1950 if (pow_data->active_index == IWL_POWER_RANGE_0)
1951 range = &pow_data->pwr_range_0[0];
1952 else
1953 range = &pow_data->pwr_range_1[1];
1954
bb8c093b 1955 memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
b481de9c
ZY		 1956
1957#ifdef IWL_MAC80211_DISABLE
1958 if (priv->assoc_network != NULL) {
1959 unsigned long flags;
1960
1961 period = priv->assoc_network->tim.tim_period;
1962 }
1963#endif /*IWL_MAC80211_DISABLE */
1964 skip = range[mode].no_dtim;
1965
1966 if (period == 0) {
1967 period = 1;
1968 skip = 0;
1969 }
1970
1971 if (skip == 0) {
1972 max_sleep = period;
1973 cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
1974 } else {
1975 __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
1976 max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
1977 cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
1978 }
1979
1980 for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
1981 if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
1982 cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
1983 }
1984
1985 IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
1986 IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
1987 IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
1988 IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
1989 le32_to_cpu(cmd->sleep_interval[0]),
1990 le32_to_cpu(cmd->sleep_interval[1]),
1991 le32_to_cpu(cmd->sleep_interval[2]),
1992 le32_to_cpu(cmd->sleep_interval[3]),
1993 le32_to_cpu(cmd->sleep_interval[4]));
1994
1995 return rc;
1996}
1997
bb8c093b 1998static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
b481de9c 1999{
9a62f73b 2000 u32 uninitialized_var(final_mode);
b481de9c 2001 int rc;
bb8c093b 2002 struct iwl3945_powertable_cmd cmd;
b481de9c
ZY		 2003
2004 /* If on battery, set to 3,
01ebd063 2005 * if plugged into AC power, set to CAM ("continuously aware mode"),
b481de9c
ZY		 2006 * else user level */
2007 switch (mode) {
2008 case IWL_POWER_BATTERY:
2009 final_mode = IWL_POWER_INDEX_3;
2010 break;
2011 case IWL_POWER_AC:
2012 final_mode = IWL_POWER_MODE_CAM;
2013 break;
2014 default:
2015 final_mode = mode;
2016 break;
2017 }
2018
bb8c093b 2019 iwl3945_update_power_cmd(priv, &cmd, final_mode);
b481de9c 2020
bb8c093b 2021 rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
b481de9c
ZY		 2022
2023 if (final_mode == IWL_POWER_MODE_CAM)
2024 clear_bit(STATUS_POWER_PMI, &priv->status);
2025 else
2026 set_bit(STATUS_POWER_PMI, &priv->status);
2027
2028 return rc;
2029}
2030
b481de9c 2031/**
bb8c093b 2032 * iwl3945_scan_cancel - Cancel any currently executing HW scan
b481de9c
ZY		 2033 *
2034 * NOTE: priv->mutex is not required before calling this function
2035 */
bb8c093b 2036static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
b481de9c
ZY		 2037{
2038 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
2039 clear_bit(STATUS_SCANNING, &priv->status);
2040 return 0;
2041 }
2042
2043 if (test_bit(STATUS_SCANNING, &priv->status)) {
2044 if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2045 IWL_DEBUG_SCAN("Queuing scan abort.\n");
2046 set_bit(STATUS_SCAN_ABORTING, &priv->status);
2047 queue_work(priv->workqueue, &priv->abort_scan);
2048
2049 } else
2050 IWL_DEBUG_SCAN("Scan abort already in progress.\n");
2051
2052 return test_bit(STATUS_SCANNING, &priv->status);
2053 }
2054
2055 return 0;
2056}
2057
2058/**
bb8c093b 2059 * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
b481de9c
ZY		 2060 * @ms: amount of time to wait (in milliseconds) for scan to abort
2061 *
2062 * NOTE: priv->mutex must be held before calling this function
2063 */
bb8c093b 2064static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
b481de9c
ZY		 2065{
2066 unsigned long now = jiffies;
2067 int ret;
2068
bb8c093b 2069 ret = iwl3945_scan_cancel(priv);
b481de9c
ZY		 2070 if (ret && ms) {
2071 mutex_unlock(&priv->mutex);
2072 while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
2073 test_bit(STATUS_SCANNING, &priv->status))
2074 msleep(1);
2075 mutex_lock(&priv->mutex);
2076
2077 return test_bit(STATUS_SCANNING, &priv->status);
2078 }
2079
2080 return ret;
2081}
2082
b481de9c
ZY		 2083#define MAX_UCODE_BEACON_INTERVAL 1024
2084#define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
2085
bb8c093b 2086static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
b481de9c
ZY		 2087{
2088 u16 new_val = 0;
2089 u16 beacon_factor = 0;
2090
2091 beacon_factor =
2092 (beacon_val + MAX_UCODE_BEACON_INTERVAL)
2093 / MAX_UCODE_BEACON_INTERVAL;
2094 new_val = beacon_val / beacon_factor;
2095
2096 return cpu_to_le16(new_val);
2097}
2098
bb8c093b 2099static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
b481de9c
ZY		 2100{
2101 u64 interval_tm_unit;
2102 u64 tsf, result;
2103 unsigned long flags;
2104 struct ieee80211_conf *conf = NULL;
2105 u16 beacon_int = 0;
2106
2107 conf = ieee80211_get_hw_conf(priv->hw);
2108
2109 spin_lock_irqsave(&priv->lock, flags);
2110 priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
2111 priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
2112
2113 priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
2114
2115 tsf = priv->timestamp1;
2116 tsf = ((tsf << 32) | priv->timestamp0);
2117
2118 beacon_int = priv->beacon_int;
2119 spin_unlock_irqrestore(&priv->lock, flags);
2120
05c914fe 2121 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
b481de9c
ZY		 2122 if (beacon_int == 0) {
2123 priv->rxon_timing.beacon_interval = cpu_to_le16(100);
2124 priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
2125 } else {
2126 priv->rxon_timing.beacon_interval =
2127 cpu_to_le16(beacon_int);
2128 priv->rxon_timing.beacon_interval =
bb8c093b 2129 iwl3945_adjust_beacon_interval(
b481de9c
ZY		 2130 le16_to_cpu(priv->rxon_timing.beacon_interval));
2131 }
2132
2133 priv->rxon_timing.atim_window = 0;
2134 } else {
2135 priv->rxon_timing.beacon_interval =
bb8c093b 2136 iwl3945_adjust_beacon_interval(conf->beacon_int);
b481de9c
ZY		 2137 /* TODO: we need to get atim_window from upper stack
2138 * for now we set to 0 */
2139 priv->rxon_timing.atim_window = 0;
2140 }
2141
2142 interval_tm_unit =
2143 (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
2144 result = do_div(tsf, interval_tm_unit);
2145 priv->rxon_timing.beacon_init_val =
2146 cpu_to_le32((u32) ((u64) interval_tm_unit - result));
2147
2148 IWL_DEBUG_ASSOC
2149 ("beacon interval %d beacon timer %d beacon tim %d\n",
2150 le16_to_cpu(priv->rxon_timing.beacon_interval),
2151 le32_to_cpu(priv->rxon_timing.beacon_init_val),
2152 le16_to_cpu(priv->rxon_timing.atim_window));
2153}
2154
bb8c093b 2155static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
b481de9c 2156{
05c914fe 2157 if (priv->iw_mode == NL80211_IFTYPE_AP) {
b481de9c
ZY		 2158 IWL_ERROR("APs don't scan.\n");
2159 return 0;
2160 }
2161
bb8c093b 2162 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 2163 IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
2164 return -EIO;
2165 }
2166
2167 if (test_bit(STATUS_SCANNING, &priv->status)) {
2168 IWL_DEBUG_SCAN("Scan already in progress.\n");
2169 return -EAGAIN;
2170 }
2171
2172 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2173 IWL_DEBUG_SCAN("Scan request while abort pending. "
2174 "Queuing.\n");
2175 return -EAGAIN;
2176 }
2177
2178 IWL_DEBUG_INFO("Starting scan...\n");
66b5004d
RR		 2179 if (priv->cfg->sku & IWL_SKU_G)
2180 priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ);
2181 if (priv->cfg->sku & IWL_SKU_A)
2182 priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ);
b481de9c
ZY		 2183 set_bit(STATUS_SCANNING, &priv->status);
2184 priv->scan_start = jiffies;
2185 priv->scan_pass_start = priv->scan_start;
2186
2187 queue_work(priv->workqueue, &priv->request_scan);
2188
2189 return 0;
2190}
2191
bb8c093b 2192static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
b481de9c 2193{
bb8c093b 2194 struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
b481de9c
ZY		 2195
2196 if (hw_decrypt)
2197 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
2198 else
2199 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
2200
2201 return 0;
2202}
2203
8318d78a
JB		 2204static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv,
2205 enum ieee80211_band band)
b481de9c 2206{
8318d78a 2207 if (band == IEEE80211_BAND_5GHZ) {
b481de9c
ZY		 2208 priv->staging_rxon.flags &=
2209 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
2210 | RXON_FLG_CCK_MSK);
2211 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2212 } else {
bb8c093b 2213 /* Copied from iwl3945_bg_post_associate() */
b481de9c
ZY		 2214 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2215 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2216 else
2217 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2218
05c914fe 2219 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY		 2220 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2221
2222 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
2223 priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
2224 priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
2225 }
2226}
2227
2228/*
01ebd063 2229 * initialize rxon structure with default values from eeprom
b481de9c 2230 */
bb8c093b 2231static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv)
b481de9c 2232{
bb8c093b 2233 const struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 2234
2235 memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
2236
2237 switch (priv->iw_mode) {
05c914fe 2238 case NL80211_IFTYPE_AP:
b481de9c
ZY		 2239 priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
2240 break;
2241
05c914fe 2242 case NL80211_IFTYPE_STATION:
b481de9c
ZY		 2243 priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
2244 priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
2245 break;
2246
05c914fe 2247 case NL80211_IFTYPE_ADHOC:
b481de9c
ZY		 2248 priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
2249 priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
2250 priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
2251 RXON_FILTER_ACCEPT_GRP_MSK;
2252 break;
2253
05c914fe 2254 case NL80211_IFTYPE_MONITOR:
b481de9c
ZY		 2255 priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
2256 priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
2257 RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
2258 break;
69dc5d9d
TW		 2259 default:
2260 IWL_ERROR("Unsupported interface type %d\n", priv->iw_mode);
2261 break;
b481de9c
ZY		 2262 }
2263
2264#if 0
2265 /* TODO: Figure out when short_preamble would be set and cache from
2266 * that */
2267 if (!hw_to_local(priv->hw)->short_preamble)
2268 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2269 else
2270 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2271#endif
2272
8318d78a 2273 ch_info = iwl3945_get_channel_info(priv, priv->band,
25b3f57c 2274 le16_to_cpu(priv->active_rxon.channel));
b481de9c
ZY		 2275
2276 if (!ch_info)
2277 ch_info = &priv->channel_info[0];
2278
2279 /*
2280 * in some case A channels are all non IBSS
2281 * in this case force B/G channel
2282 */
05c914fe 2283 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) &&
b481de9c
ZY		 2284 !(is_channel_ibss(ch_info)))
2285 ch_info = &priv->channel_info[0];
2286
2287 priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
2288 if (is_channel_a_band(ch_info))
8318d78a 2289 priv->band = IEEE80211_BAND_5GHZ;
b481de9c 2290 else
8318d78a 2291 priv->band = IEEE80211_BAND_2GHZ;
b481de9c 2292
8318d78a 2293 iwl3945_set_flags_for_phymode(priv, priv->band);
b481de9c
ZY		 2294
2295 priv->staging_rxon.ofdm_basic_rates =
2296 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2297 priv->staging_rxon.cck_basic_rates =
2298 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2299}
2300
bb8c093b 2301static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
b481de9c 2302{
05c914fe 2303 if (mode == NL80211_IFTYPE_ADHOC) {
bb8c093b 2304 const struct iwl3945_channel_info *ch_info;
b481de9c 2305
bb8c093b 2306 ch_info = iwl3945_get_channel_info(priv,
8318d78a 2307 priv->band,
b481de9c
ZY		 2308 le16_to_cpu(priv->staging_rxon.channel));
2309
2310 if (!ch_info || !is_channel_ibss(ch_info)) {
2311 IWL_ERROR("channel %d not IBSS channel\n",
2312 le16_to_cpu(priv->staging_rxon.channel));
2313 return -EINVAL;
2314 }
2315 }
2316
b481de9c
ZY		 2317 priv->iw_mode = mode;
2318
bb8c093b 2319 iwl3945_connection_init_rx_config(priv);
b481de9c
ZY		 2320 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2321
bb8c093b 2322 iwl3945_clear_stations_table(priv);
b481de9c 2323
fde3571f
MA		 2324 /* dont commit rxon if rf-kill is on*/
2325 if (!iwl3945_is_ready_rf(priv))
2326 return -EAGAIN;
2327
2328 cancel_delayed_work(&priv->scan_check);
2329 if (iwl3945_scan_cancel_timeout(priv, 100)) {
2330 IWL_WARNING("Aborted scan still in progress after 100ms\n");
2331 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
2332 return -EAGAIN;
2333 }
2334
bb8c093b 2335 iwl3945_commit_rxon(priv);
b481de9c
ZY		 2336
2337 return 0;
2338}
2339
bb8c093b 2340static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
e039fa4a 2341 struct ieee80211_tx_info *info,
bb8c093b 2342 struct iwl3945_cmd *cmd,
b481de9c
ZY		 2343 struct sk_buff *skb_frag,
2344 int last_frag)
2345{
1c014420 2346 struct iwl3945_hw_key *keyinfo =
e039fa4a 2347 &priv->stations[info->control.hw_key->hw_key_idx].keyinfo;
b481de9c
ZY		 2348
2349 switch (keyinfo->alg) {
2350 case ALG_CCMP:
2351 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
2352 memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
2353 IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
2354 break;
2355
2356 case ALG_TKIP:
2357#if 0
2358 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
2359
2360 if (last_frag)
2361 memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
2362 8);
2363 else
2364 memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
2365#endif
2366 break;
2367
2368 case ALG_WEP:
2369 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
e039fa4a 2370 (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
b481de9c
ZY		 2371
2372 if (keyinfo->keylen == 13)
2373 cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
2374
2375 memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
2376
2377 IWL_DEBUG_TX("Configuring packet for WEP encryption "
e039fa4a 2378 "with key %d\n", info->control.hw_key->hw_key_idx);
b481de9c
ZY		 2379 break;
2380
b481de9c
ZY		 2381 default:
2382 printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
2383 break;
2384 }
2385}
2386
2387/*
2388 * handle build REPLY_TX command notification.
2389 */
bb8c093b
CH		 2390static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
2391 struct iwl3945_cmd *cmd,
e039fa4a 2392 struct ieee80211_tx_info *info,
b481de9c
ZY		 2393 struct ieee80211_hdr *hdr,
2394 int is_unicast, u8 std_id)
2395{
fd7c8a40 2396 __le16 fc = hdr->frame_control;
b481de9c
ZY		 2397 __le32 tx_flags = cmd->cmd.tx.tx_flags;
2398
2399 cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e039fa4a 2400 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
b481de9c 2401 tx_flags |= TX_CMD_FLG_ACK_MSK;
fd7c8a40 2402 if (ieee80211_is_mgmt(fc))
b481de9c 2403 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
fd7c8a40 2404 if (ieee80211_is_probe_resp(fc) &&
b481de9c
ZY		 2405 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
2406 tx_flags |= TX_CMD_FLG_TSF_MSK;
2407 } else {
2408 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
2409 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2410 }
2411
2412 cmd->cmd.tx.sta_id = std_id;
8b7b1e05 2413 if (ieee80211_has_morefrags(fc))
b481de9c
ZY		 2414 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
2415
fd7c8a40
HH		 2416 if (ieee80211_is_data_qos(fc)) {
2417 u8 *qc = ieee80211_get_qos_ctl(hdr);
54dbb525 2418 cmd->cmd.tx.tid_tspec = qc[0] & 0xf;
b481de9c 2419 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 2420 } else {
b481de9c 2421 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 2422 }
b481de9c 2423
e039fa4a 2424 if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) {
b481de9c
ZY		 2425 tx_flags |= TX_CMD_FLG_RTS_MSK;
2426 tx_flags &= ~TX_CMD_FLG_CTS_MSK;
e039fa4a 2427 } else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) {
b481de9c
ZY		 2428 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2429 tx_flags |= TX_CMD_FLG_CTS_MSK;
2430 }
2431
2432 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
2433 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
2434
2435 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
fd7c8a40
HH		 2436 if (ieee80211_is_mgmt(fc)) {
2437 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
bc434dd2 2438 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
b481de9c 2439 else
bc434dd2 2440 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
ab53d8af 2441 } else {
b481de9c 2442 cmd->cmd.tx.timeout.pm_frame_timeout = 0;
ab53d8af
MA		 2443#ifdef CONFIG_IWL3945_LEDS
2444 priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
2445#endif
2446 }
b481de9c
ZY		 2447
2448 cmd->cmd.tx.driver_txop = 0;
2449 cmd->cmd.tx.tx_flags = tx_flags;
2450 cmd->cmd.tx.next_frame_len = 0;
2451}
2452
6440adb5
CB		 2453/**
2454 * iwl3945_get_sta_id - Find station's index within station table
2455 */
bb8c093b 2456static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
b481de9c
ZY		 2457{
2458 int sta_id;
2459 u16 fc = le16_to_cpu(hdr->frame_control);
2460
6440adb5 2461 /* If this frame is broadcast or management, use broadcast station id */
b481de9c
ZY		 2462 if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
2463 is_multicast_ether_addr(hdr->addr1))
2464 return priv->hw_setting.bcast_sta_id;
2465
2466 switch (priv->iw_mode) {
2467
6440adb5
CB		 2468 /* If we are a client station in a BSS network, use the special
2469 * AP station entry (that's the only station we communicate with) */
05c914fe 2470 case NL80211_IFTYPE_STATION:
b481de9c
ZY		 2471 return IWL_AP_ID;
2472
2473 /* If we are an AP, then find the station, or use BCAST */
05c914fe 2474 case NL80211_IFTYPE_AP:
bb8c093b 2475 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY		 2476 if (sta_id != IWL_INVALID_STATION)
2477 return sta_id;
2478 return priv->hw_setting.bcast_sta_id;
2479
6440adb5
CB		 2480 /* If this frame is going out to an IBSS network, find the station,
2481 * or create a new station table entry */
05c914fe 2482 case NL80211_IFTYPE_ADHOC: {
6440adb5 2483 /* Create new station table entry */
bb8c093b 2484 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY		 2485 if (sta_id != IWL_INVALID_STATION)
2486 return sta_id;
2487
bb8c093b 2488 sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
b481de9c
ZY		 2489
2490 if (sta_id != IWL_INVALID_STATION)
2491 return sta_id;
2492
e174961c 2493 IWL_DEBUG_DROP("Station %pM not in station map. "
b481de9c 2494 "Defaulting to broadcast...\n",
e174961c 2495 hdr->addr1);
bb8c093b 2496 iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
b481de9c 2497 return priv->hw_setting.bcast_sta_id;
0795af57 2498 }
914233d6
SG		 2499 /* If we are in monitor mode, use BCAST. This is required for
2500 * packet injection. */
05c914fe 2501 case NL80211_IFTYPE_MONITOR:
914233d6
SG		 2502 return priv->hw_setting.bcast_sta_id;
2503
b481de9c 2504 default:
6f147926 2505 IWL_WARNING("Unknown mode of operation: %d\n", priv->iw_mode);
b481de9c
ZY		 2506 return priv->hw_setting.bcast_sta_id;
2507 }
2508}
2509
2510/*
2511 * start REPLY_TX command process
2512 */
e039fa4a 2513static int iwl3945_tx_skb(struct iwl3945_priv *priv, struct sk_buff *skb)
b481de9c
ZY		 2514{
2515 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
e039fa4a 2516 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bb8c093b 2517 struct iwl3945_tfd_frame *tfd;
b481de9c 2518 u32 *control_flags;
e2530083 2519 int txq_id = skb_get_queue_mapping(skb);
bb8c093b
CH		 2520 struct iwl3945_tx_queue *txq = NULL;
2521 struct iwl3945_queue *q = NULL;
b481de9c
ZY		 2522 dma_addr_t phys_addr;
2523 dma_addr_t txcmd_phys;
bb8c093b 2524 struct iwl3945_cmd *out_cmd = NULL;
54dbb525
TW		 2525 u16 len, idx, len_org, hdr_len;
2526 u8 id;
2527 u8 unicast;
b481de9c 2528 u8 sta_id;
54dbb525 2529 u8 tid = 0;
b481de9c 2530 u16 seq_number = 0;
fd7c8a40 2531 __le16 fc;
b481de9c 2532 u8 wait_write_ptr = 0;
54dbb525 2533 u8 *qc = NULL;
b481de9c
ZY		 2534 unsigned long flags;
2535 int rc;
2536
2537 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2538 if (iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 2539 IWL_DEBUG_DROP("Dropping - RF KILL\n");
2540 goto drop_unlock;
2541 }
2542
e039fa4a 2543 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
b481de9c
ZY		 2544 IWL_ERROR("ERROR: No TX rate available.\n");
2545 goto drop_unlock;
2546 }
2547
2548 unicast = !is_multicast_ether_addr(hdr->addr1);
2549 id = 0;
2550
fd7c8a40 2551 fc = hdr->frame_control;
b481de9c 2552
c8b0e6e1 2553#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 2554 if (ieee80211_is_auth(fc))
2555 IWL_DEBUG_TX("Sending AUTH frame\n");
fd7c8a40 2556 else if (ieee80211_is_assoc_req(fc))
b481de9c 2557 IWL_DEBUG_TX("Sending ASSOC frame\n");
fd7c8a40 2558 else if (ieee80211_is_reassoc_req(fc))
b481de9c
ZY		 2559 IWL_DEBUG_TX("Sending REASSOC frame\n");
2560#endif
2561
7878a5a4 2562 /* drop all data frame if we are not associated */
914233d6 2563 if (ieee80211_is_data(fc) &&
05c914fe 2564 (priv->iw_mode != NL80211_IFTYPE_MONITOR) && /* packet injection */
914233d6 2565 (!iwl3945_is_associated(priv) ||
05c914fe 2566 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
bb8c093b 2567 IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
b481de9c
ZY		 2568 goto drop_unlock;
2569 }
2570
2571 spin_unlock_irqrestore(&priv->lock, flags);
2572
7294ec95 2573 hdr_len = ieee80211_hdrlen(fc);
6440adb5
CB		 2574
2575 /* Find (or create) index into station table for destination station */
bb8c093b 2576 sta_id = iwl3945_get_sta_id(priv, hdr);
b481de9c 2577 if (sta_id == IWL_INVALID_STATION) {
e174961c
JB		 2578 IWL_DEBUG_DROP("Dropping - INVALID STATION: %pM\n",
2579 hdr->addr1);
b481de9c
ZY		 2580 goto drop;
2581 }
2582
2583 IWL_DEBUG_RATE("station Id %d\n", sta_id);
2584
fd7c8a40
HH		 2585 if (ieee80211_is_data_qos(fc)) {
2586 qc = ieee80211_get_qos_ctl(hdr);
7294ec95 2587 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
b481de9c
ZY		 2588 seq_number = priv->stations[sta_id].tid[tid].seq_number &
2589 IEEE80211_SCTL_SEQ;
2590 hdr->seq_ctrl = cpu_to_le16(seq_number) |
2591 (hdr->seq_ctrl &
2592 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
2593 seq_number += 0x10;
2594 }
6440adb5
CB		 2595
2596 /* Descriptor for chosen Tx queue */
b481de9c
ZY		 2597 txq = &priv->txq[txq_id];
2598 q = &txq->q;
2599
2600 spin_lock_irqsave(&priv->lock, flags);
2601
6440adb5 2602 /* Set up first empty TFD within this queue's circular TFD buffer */
fc4b6853 2603 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY		 2604 memset(tfd, 0, sizeof(*tfd));
2605 control_flags = (u32 *) tfd;
fc4b6853 2606 idx = get_cmd_index(q, q->write_ptr, 0);
b481de9c 2607
6440adb5 2608 /* Set up driver data for this TFD */
bb8c093b 2609 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
fc4b6853 2610 txq->txb[q->write_ptr].skb[0] = skb;
6440adb5
CB		 2611
2612 /* Init first empty entry in queue's array of Tx/cmd buffers */
b481de9c
ZY		 2613 out_cmd = &txq->cmd[idx];
2614 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
2615 memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
6440adb5
CB		 2616
2617 /*
2618 * Set up the Tx-command (not MAC!) header.
2619 * Store the chosen Tx queue and TFD index within the sequence field;
2620 * after Tx, uCode's Tx response will return this value so driver can
2621 * locate the frame within the tx queue and do post-tx processing.
2622 */
b481de9c
ZY		 2623 out_cmd->hdr.cmd = REPLY_TX;
2624 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
fc4b6853 2625 INDEX_TO_SEQ(q->write_ptr)));
6440adb5
CB		 2626
2627 /* Copy MAC header from skb into command buffer */
b481de9c
ZY		 2628 memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
2629
6440adb5
CB		 2630 /*
2631 * Use the first empty entry in this queue's command buffer array
2632 * to contain the Tx command and MAC header concatenated together
2633 * (payload data will be in another buffer).
2634 * Size of this varies, due to varying MAC header length.
2635 * If end is not dword aligned, we'll have 2 extra bytes at the end
2636 * of the MAC header (device reads on dword boundaries).
2637 * We'll tell device about this padding later.
2638 */
b481de9c 2639 len = priv->hw_setting.tx_cmd_len +
bb8c093b 2640 sizeof(struct iwl3945_cmd_header) + hdr_len;
b481de9c
ZY		 2641
2642 len_org = len;
2643 len = (len + 3) & ~3;
2644
2645 if (len_org != len)
2646 len_org = 1;
2647 else
2648 len_org = 0;
2649
6440adb5
CB		 2650 /* Physical address of this Tx command's header (not MAC header!),
2651 * within command buffer array. */
bb8c093b
CH		 2652 txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
2653 offsetof(struct iwl3945_cmd, hdr);
b481de9c 2654
6440adb5
CB		 2655 /* Add buffer containing Tx command and MAC(!) header to TFD's
2656 * first entry */
bb8c093b 2657 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
b481de9c 2658
d0f09804 2659 if (info->control.hw_key)
e039fa4a 2660 iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0);
b481de9c 2661
6440adb5
CB		 2662 /* Set up TFD's 2nd entry to point directly to remainder of skb,
2663 * if any (802.11 null frames have no payload). */
b481de9c
ZY		 2664 len = skb->len - hdr_len;
2665 if (len) {
2666 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
2667 len, PCI_DMA_TODEVICE);
bb8c093b 2668 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
b481de9c
ZY		 2669 }
2670
b481de9c 2671 if (!len)
6440adb5 2672 /* If there is no payload, then we use only one Tx buffer */
b481de9c
ZY		 2673 *control_flags = TFD_CTL_COUNT_SET(1);
2674 else
6440adb5
CB		 2675 /* Else use 2 buffers.
2676 * Tell 3945 about any padding after MAC header */
b481de9c
ZY		 2677 *control_flags = TFD_CTL_COUNT_SET(2) |
2678 TFD_CTL_PAD_SET(U32_PAD(len));
2679
6440adb5 2680 /* Total # bytes to be transmitted */
b481de9c
ZY		 2681 len = (u16)skb->len;
2682 out_cmd->cmd.tx.len = cpu_to_le16(len);
2683
2684 /* TODO need this for burst mode later on */
e039fa4a 2685 iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, unicast, sta_id);
b481de9c
ZY		 2686
2687 /* set is_hcca to 0; it probably will never be implemented */
e039fa4a 2688 iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
b481de9c
ZY		 2689
2690 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
2691 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
2692
8b7b1e05 2693 if (!ieee80211_has_morefrags(hdr->frame_control)) {
b481de9c 2694 txq->need_update = 1;
3ac7f146 2695 if (qc)
b481de9c 2696 priv->stations[sta_id].tid[tid].seq_number = seq_number;
b481de9c
ZY		 2697 } else {
2698 wait_write_ptr = 1;
2699 txq->need_update = 0;
2700 }
2701
bb8c093b 2702 iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
b481de9c
ZY		 2703 sizeof(out_cmd->cmd.tx));
2704
bb8c093b 2705 iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
7294ec95 2706 ieee80211_hdrlen(fc));
b481de9c 2707
6440adb5 2708 /* Tell device the write index *just past* this latest filled TFD */
c54b679d 2709 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
bb8c093b 2710 rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 2711 spin_unlock_irqrestore(&priv->lock, flags);
2712
2713 if (rc)
2714 return rc;
2715
bb8c093b 2716 if ((iwl3945_queue_space(q) < q->high_mark)
b481de9c
ZY		 2717 && priv->mac80211_registered) {
2718 if (wait_write_ptr) {
2719 spin_lock_irqsave(&priv->lock, flags);
2720 txq->need_update = 1;
bb8c093b 2721 iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 2722 spin_unlock_irqrestore(&priv->lock, flags);
2723 }
2724
e2530083 2725 ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
b481de9c
ZY		 2726 }
2727
2728 return 0;
2729
2730drop_unlock:
2731 spin_unlock_irqrestore(&priv->lock, flags);
2732drop:
2733 return -1;
2734}
2735
bb8c093b 2736static void iwl3945_set_rate(struct iwl3945_priv *priv)
b481de9c 2737{
8318d78a 2738 const struct ieee80211_supported_band *sband = NULL;
b481de9c
ZY		 2739 struct ieee80211_rate *rate;
2740 int i;
2741
8318d78a
JB		 2742 sband = iwl3945_get_band(priv, priv->band);
2743 if (!sband) {
c4ba9621
SA		 2744 IWL_ERROR("Failed to set rate: unable to get hw mode\n");
2745 return;
2746 }
b481de9c
ZY		 2747
2748 priv->active_rate = 0;
2749 priv->active_rate_basic = 0;
2750
8318d78a
JB		 2751 IWL_DEBUG_RATE("Setting rates for %s GHz\n",
2752 sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
2753
2754 for (i = 0; i < sband->n_bitrates; i++) {
2755 rate = &sband->bitrates[i];
2756 if ((rate->hw_value < IWL_RATE_COUNT) &&
2757 !(rate->flags & IEEE80211_CHAN_DISABLED)) {
2758 IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
2759 rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
2760 priv->active_rate |= (1 << rate->hw_value);
2761 }
b481de9c
ZY		 2762 }
2763
2764 IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
2765 priv->active_rate, priv->active_rate_basic);
2766
2767 /*
2768 * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
2769 * otherwise set it to the default of all CCK rates and 6, 12, 24 for
2770 * OFDM
2771 */
2772 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
2773 priv->staging_rxon.cck_basic_rates =
2774 ((priv->active_rate_basic &
2775 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
2776 else
2777 priv->staging_rxon.cck_basic_rates =
2778 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2779
2780 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
2781 priv->staging_rxon.ofdm_basic_rates =
2782 ((priv->active_rate_basic &
2783 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
2784 IWL_FIRST_OFDM_RATE) & 0xFF;
2785 else
2786 priv->staging_rxon.ofdm_basic_rates =
2787 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2788}
2789
bb8c093b 2790static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
b481de9c
ZY		 2791{
2792 unsigned long flags;
2793
2794 if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
2795 return;
2796
2797 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
2798 disable_radio ? "OFF" : "ON");
2799
2800 if (disable_radio) {
bb8c093b 2801 iwl3945_scan_cancel(priv);
b481de9c 2802 /* FIXME: This is a workaround for AP */
05c914fe 2803 if (priv->iw_mode != NL80211_IFTYPE_AP) {
b481de9c 2804 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2805 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 2806 CSR_UCODE_SW_BIT_RFKILL);
2807 spin_unlock_irqrestore(&priv->lock, flags);
bb8c093b 2808 iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
b481de9c
ZY		 2809 set_bit(STATUS_RF_KILL_SW, &priv->status);
2810 }
2811 return;
2812 }
2813
2814 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2815 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 2816
2817 clear_bit(STATUS_RF_KILL_SW, &priv->status);
2818 spin_unlock_irqrestore(&priv->lock, flags);
2819
2820 /* wake up ucode */
2821 msleep(10);
2822
2823 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH		 2824 iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
2825 if (!iwl3945_grab_nic_access(priv))
2826 iwl3945_release_nic_access(priv);
b481de9c
ZY		 2827 spin_unlock_irqrestore(&priv->lock, flags);
2828
2829 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
2830 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
2831 "disabled by HW switch\n");
2832 return;
2833 }
2834
808e72a0
ZY		 2835 if (priv->is_open)
2836 queue_work(priv->workqueue, &priv->restart);
b481de9c
ZY		 2837 return;
2838}
2839
bb8c093b 2840void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
b481de9c
ZY		 2841 u32 decrypt_res, struct ieee80211_rx_status *stats)
2842{
2843 u16 fc =
2844 le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
2845
2846 if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
2847 return;
2848
2849 if (!(fc & IEEE80211_FCTL_PROTECTED))
2850 return;
2851
2852 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
2853 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2854 case RX_RES_STATUS_SEC_TYPE_TKIP:
2855 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2856 RX_RES_STATUS_BAD_ICV_MIC)
2857 stats->flag |= RX_FLAG_MMIC_ERROR;
2858 case RX_RES_STATUS_SEC_TYPE_WEP:
2859 case RX_RES_STATUS_SEC_TYPE_CCMP:
2860 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2861 RX_RES_STATUS_DECRYPT_OK) {
2862 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
2863 stats->flag |= RX_FLAG_DECRYPTED;
2864 }
2865 break;
2866
2867 default:
2868 break;
2869 }
2870}
2871
c8b0e6e1 2872#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 2873
2874#include "iwl-spectrum.h"
2875
2876#define BEACON_TIME_MASK_LOW 0x00FFFFFF
2877#define BEACON_TIME_MASK_HIGH 0xFF000000
2878#define TIME_UNIT 1024
2879
2880/*
2881 * extended beacon time format
2882 * time in usec will be changed into a 32-bit value in 8:24 format
2883 * the high 1 byte is the beacon counts
2884 * the lower 3 bytes is the time in usec within one beacon interval
2885 */
2886
bb8c093b 2887static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
b481de9c
ZY		 2888{
2889 u32 quot;
2890 u32 rem;
2891 u32 interval = beacon_interval * 1024;
2892
2893 if (!interval || !usec)
2894 return 0;
2895
2896 quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
2897 rem = (usec % interval) & BEACON_TIME_MASK_LOW;
2898
2899 return (quot << 24) + rem;
2900}
2901
2902/* base is usually what we get from ucode with each received frame,
2903 * the same as HW timer counter counting down
2904 */
2905
bb8c093b 2906static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
b481de9c
ZY		 2907{
2908 u32 base_low = base & BEACON_TIME_MASK_LOW;
2909 u32 addon_low = addon & BEACON_TIME_MASK_LOW;
2910 u32 interval = beacon_interval * TIME_UNIT;
2911 u32 res = (base & BEACON_TIME_MASK_HIGH) +
2912 (addon & BEACON_TIME_MASK_HIGH);
2913
2914 if (base_low > addon_low)
2915 res += base_low - addon_low;
2916 else if (base_low < addon_low) {
2917 res += interval + base_low - addon_low;
2918 res += (1 << 24);
2919 } else
2920 res += (1 << 24);
2921
2922 return cpu_to_le32(res);
2923}
2924
bb8c093b 2925static int iwl3945_get_measurement(struct iwl3945_priv *priv,
b481de9c
ZY		 2926 struct ieee80211_measurement_params *params,
2927 u8 type)
2928{
bb8c093b
CH		 2929 struct iwl3945_spectrum_cmd spectrum;
2930 struct iwl3945_rx_packet *res;
2931 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 2932 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
2933 .data = (void *)&spectrum,
2934 .meta.flags = CMD_WANT_SKB,
2935 };
2936 u32 add_time = le64_to_cpu(params->start_time);
2937 int rc;
2938 int spectrum_resp_status;
2939 int duration = le16_to_cpu(params->duration);
2940
bb8c093b 2941 if (iwl3945_is_associated(priv))
b481de9c 2942 add_time =
bb8c093b 2943 iwl3945_usecs_to_beacons(
b481de9c
ZY		 2944 le64_to_cpu(params->start_time) - priv->last_tsf,
2945 le16_to_cpu(priv->rxon_timing.beacon_interval));
2946
2947 memset(&spectrum, 0, sizeof(spectrum));
2948
2949 spectrum.channel_count = cpu_to_le16(1);
2950 spectrum.flags =
2951 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
2952 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
2953 cmd.len = sizeof(spectrum);
2954 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
2955
bb8c093b 2956 if (iwl3945_is_associated(priv))
b481de9c 2957 spectrum.start_time =
bb8c093b 2958 iwl3945_add_beacon_time(priv->last_beacon_time,
b481de9c
ZY		 2959 add_time,
2960 le16_to_cpu(priv->rxon_timing.beacon_interval));
2961 else
2962 spectrum.start_time = 0;
2963
2964 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
2965 spectrum.channels[0].channel = params->channel;
2966 spectrum.channels[0].type = type;
2967 if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
2968 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
2969 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
2970
bb8c093b 2971 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 2972 if (rc)
2973 return rc;
2974
bb8c093b 2975 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 2976 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
2977 IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
2978 rc = -EIO;
2979 }
2980
2981 spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
2982 switch (spectrum_resp_status) {
2983 case 0: /* Command will be handled */
2984 if (res->u.spectrum.id != 0xff) {
bc434dd2
IS		 2985 IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
2986 res->u.spectrum.id);
b481de9c
ZY		 2987 priv->measurement_status &= ~MEASUREMENT_READY;
2988 }
2989 priv->measurement_status |= MEASUREMENT_ACTIVE;
2990 rc = 0;
2991 break;
2992
2993 case 1: /* Command will not be handled */
2994 rc = -EAGAIN;
2995 break;
2996 }
2997
2998 dev_kfree_skb_any(cmd.meta.u.skb);
2999
3000 return rc;
3001}
3002#endif
3003
bb8c093b
CH		 3004static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
3005 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3006{
bb8c093b
CH		 3007 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3008 struct iwl3945_alive_resp *palive;
b481de9c
ZY		 3009 struct delayed_work *pwork;
3010
3011 palive = &pkt->u.alive_frame;
3012
3013 IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
3014 "0x%01X 0x%01X\n",
3015 palive->is_valid, palive->ver_type,
3016 palive->ver_subtype);
3017
3018 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
3019 IWL_DEBUG_INFO("Initialization Alive received.\n");
3020 memcpy(&priv->card_alive_init,
3021 &pkt->u.alive_frame,
bb8c093b 3022 sizeof(struct iwl3945_init_alive_resp));
b481de9c
ZY		 3023 pwork = &priv->init_alive_start;
3024 } else {
3025 IWL_DEBUG_INFO("Runtime Alive received.\n");
3026 memcpy(&priv->card_alive, &pkt->u.alive_frame,
bb8c093b 3027 sizeof(struct iwl3945_alive_resp));
b481de9c 3028 pwork = &priv->alive_start;
bb8c093b 3029 iwl3945_disable_events(priv);
b481de9c
ZY		 3030 }
3031
3032 /* We delay the ALIVE response by 5ms to
3033 * give the HW RF Kill time to activate... */
3034 if (palive->is_valid == UCODE_VALID_OK)
3035 queue_delayed_work(priv->workqueue, pwork,
3036 msecs_to_jiffies(5));
3037 else
3038 IWL_WARNING("uCode did not respond OK.\n");
3039}
3040
bb8c093b
CH		 3041static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
3042 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3043{
bb8c093b 3044 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3045
3046 IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
3047 return;
3048}
3049
bb8c093b
CH		 3050static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
3051 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3052{
bb8c093b 3053 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3054
3055 IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
3056 "seq 0x%04X ser 0x%08X\n",
3057 le32_to_cpu(pkt->u.err_resp.error_type),
3058 get_cmd_string(pkt->u.err_resp.cmd_id),
3059 pkt->u.err_resp.cmd_id,
3060 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
3061 le32_to_cpu(pkt->u.err_resp.error_info));
3062}
3063
3064#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
3065
bb8c093b 3066static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3067{
bb8c093b
CH		 3068 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3069 struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
3070 struct iwl3945_csa_notification *csa = &(pkt->u.csa_notif);
b481de9c
ZY		 3071 IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
3072 le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
3073 rxon->channel = csa->channel;
3074 priv->staging_rxon.channel = csa->channel;
3075}
3076
bb8c093b
CH		 3077static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
3078 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3079{
c8b0e6e1 3080#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
bb8c093b
CH		 3081 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3082 struct iwl3945_spectrum_notification *report = &(pkt->u.spectrum_notif);
b481de9c
ZY		 3083
3084 if (!report->state) {
3085 IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
3086 "Spectrum Measure Notification: Start\n");
3087 return;
3088 }
3089
3090 memcpy(&priv->measure_report, report, sizeof(*report));
3091 priv->measurement_status |= MEASUREMENT_READY;
3092#endif
3093}
3094
bb8c093b
CH		 3095static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
3096 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3097{
c8b0e6e1 3098#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3099 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3100 struct iwl3945_sleep_notification *sleep = &(pkt->u.sleep_notif);
b481de9c
ZY		 3101 IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
3102 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
3103#endif
3104}
3105
bb8c093b
CH		 3106static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
3107 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3108{
bb8c093b 3109 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3110 IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
3111 "notification for %s:\n",
3112 le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
bb8c093b 3113 iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
b481de9c
ZY		 3114}
3115
bb8c093b 3116static void iwl3945_bg_beacon_update(struct work_struct *work)
b481de9c 3117{
bb8c093b
CH		 3118 struct iwl3945_priv *priv =
3119 container_of(work, struct iwl3945_priv, beacon_update);
b481de9c
ZY		 3120 struct sk_buff *beacon;
3121
3122 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 3123 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY		 3124
3125 if (!beacon) {
3126 IWL_ERROR("update beacon failed\n");
3127 return;
3128 }
3129
3130 mutex_lock(&priv->mutex);
3131 /* new beacon skb is allocated every time; dispose previous.*/
3132 if (priv->ibss_beacon)
3133 dev_kfree_skb(priv->ibss_beacon);
3134
3135 priv->ibss_beacon = beacon;
3136 mutex_unlock(&priv->mutex);
3137
bb8c093b 3138 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 3139}
3140
bb8c093b
CH		 3141static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
3142 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3143{
c8b0e6e1 3144#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3145 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3146 struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
b481de9c
ZY		 3147 u8 rate = beacon->beacon_notify_hdr.rate;
3148
3149 IWL_DEBUG_RX("beacon status %x retries %d iss %d "
3150 "tsf %d %d rate %d\n",
3151 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
3152 beacon->beacon_notify_hdr.failure_frame,
3153 le32_to_cpu(beacon->ibss_mgr_status),
3154 le32_to_cpu(beacon->high_tsf),
3155 le32_to_cpu(beacon->low_tsf), rate);
3156#endif
3157
05c914fe 3158 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY		 3159 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
3160 queue_work(priv->workqueue, &priv->beacon_update);
3161}
3162
3163/* Service response to REPLY_SCAN_CMD (0x80) */
bb8c093b
CH		 3164static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
3165 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3166{
c8b0e6e1 3167#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3168 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3169 struct iwl3945_scanreq_notification *notif =
3170 (struct iwl3945_scanreq_notification *)pkt->u.raw;
b481de9c
ZY		 3171
3172 IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
3173#endif
3174}
3175
3176/* Service SCAN_START_NOTIFICATION (0x82) */
bb8c093b
CH		 3177static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
3178 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3179{
bb8c093b
CH		 3180 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3181 struct iwl3945_scanstart_notification *notif =
3182 (struct iwl3945_scanstart_notification *)pkt->u.raw;
b481de9c
ZY		 3183 priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
3184 IWL_DEBUG_SCAN("Scan start: "
3185 "%d [802.11%s] "
3186 "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
3187 notif->channel,
3188 notif->band ? "bg" : "a",
3189 notif->tsf_high,
3190 notif->tsf_low, notif->status, notif->beacon_timer);
3191}
3192
3193/* Service SCAN_RESULTS_NOTIFICATION (0x83) */
bb8c093b
CH		 3194static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
3195 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3196{
bb8c093b
CH		 3197 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3198 struct iwl3945_scanresults_notification *notif =
3199 (struct iwl3945_scanresults_notification *)pkt->u.raw;
b481de9c
ZY		 3200
3201 IWL_DEBUG_SCAN("Scan ch.res: "
3202 "%d [802.11%s] "
3203 "(TSF: 0x%08X:%08X) - %d "
3204 "elapsed=%lu usec (%dms since last)\n",
3205 notif->channel,
3206 notif->band ? "bg" : "a",
3207 le32_to_cpu(notif->tsf_high),
3208 le32_to_cpu(notif->tsf_low),
3209 le32_to_cpu(notif->statistics[0]),
3210 le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
3211 jiffies_to_msecs(elapsed_jiffies
3212 (priv->last_scan_jiffies, jiffies)));
3213
3214 priv->last_scan_jiffies = jiffies;
7878a5a4 3215 priv->next_scan_jiffies = 0;
b481de9c
ZY		 3216}
3217
3218/* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
bb8c093b
CH		 3219static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
3220 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3221{
bb8c093b
CH		 3222 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3223 struct iwl3945_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
b481de9c
ZY		 3224
3225 IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
3226 scan_notif->scanned_channels,
3227 scan_notif->tsf_low,
3228 scan_notif->tsf_high, scan_notif->status);
3229
3230 /* The HW is no longer scanning */
3231 clear_bit(STATUS_SCAN_HW, &priv->status);
3232
3233 /* The scan completion notification came in, so kill that timer... */
3234 cancel_delayed_work(&priv->scan_check);
3235
3236 IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
66b5004d
RR		 3237 (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ?
3238 "2.4" : "5.2",
b481de9c
ZY		 3239 jiffies_to_msecs(elapsed_jiffies
3240 (priv->scan_pass_start, jiffies)));
3241
66b5004d
RR		 3242 /* Remove this scanned band from the list of pending
3243 * bands to scan, band G precedes A in order of scanning
3244 * as seen in iwl3945_bg_request_scan */
3245 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ))
3246 priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ);
3247 else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ))
3248 priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ);
b481de9c
ZY		 3249
3250 /* If a request to abort was given, or the scan did not succeed
3251 * then we reset the scan state machine and terminate,
3252 * re-queuing another scan if one has been requested */
3253 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
3254 IWL_DEBUG_INFO("Aborted scan completed.\n");
3255 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
3256 } else {
3257 /* If there are more bands on this scan pass reschedule */
3258 if (priv->scan_bands > 0)
3259 goto reschedule;
3260 }
3261
3262 priv->last_scan_jiffies = jiffies;
7878a5a4 3263 priv->next_scan_jiffies = 0;
b481de9c
ZY		 3264 IWL_DEBUG_INFO("Setting scan to off\n");
3265
3266 clear_bit(STATUS_SCANNING, &priv->status);
3267
3268 IWL_DEBUG_INFO("Scan took %dms\n",
3269 jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
3270
3271 queue_work(priv->workqueue, &priv->scan_completed);
3272
3273 return;
3274
3275reschedule:
3276 priv->scan_pass_start = jiffies;
3277 queue_work(priv->workqueue, &priv->request_scan);
3278}
3279
3280/* Handle notification from uCode that card's power state is changing
3281 * due to software, hardware, or critical temperature RFKILL */
bb8c093b
CH		 3282static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
3283 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3284{
bb8c093b 3285 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3286 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
3287 unsigned long status = priv->status;
3288
3289 IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
3290 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3291 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
3292
bb8c093b 3293 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 3294 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3295
3296 if (flags & HW_CARD_DISABLED)
3297 set_bit(STATUS_RF_KILL_HW, &priv->status);
3298 else
3299 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3300
3301
3302 if (flags & SW_CARD_DISABLED)
3303 set_bit(STATUS_RF_KILL_SW, &priv->status);
3304 else
3305 clear_bit(STATUS_RF_KILL_SW, &priv->status);
3306
bb8c093b 3307 iwl3945_scan_cancel(priv);
b481de9c
ZY		 3308
3309 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
3310 test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
3311 (test_bit(STATUS_RF_KILL_SW, &status) !=
3312 test_bit(STATUS_RF_KILL_SW, &priv->status)))
3313 queue_work(priv->workqueue, &priv->rf_kill);
3314 else
3315 wake_up_interruptible(&priv->wait_command_queue);
3316}
3317
3318/**
bb8c093b 3319 * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY		 3320 *
3321 * Setup the RX handlers for each of the reply types sent from the uCode
3322 * to the host.
3323 *
3324 * This function chains into the hardware specific files for them to setup
3325 * any hardware specific handlers as well.
3326 */
bb8c093b 3327static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
b481de9c 3328{
bb8c093b
CH		 3329 priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
3330 priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
3331 priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
3332 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
b481de9c 3333 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
bb8c093b
CH		 3334 iwl3945_rx_spectrum_measure_notif;
3335 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
b481de9c 3336 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
bb8c093b
CH		 3337 iwl3945_rx_pm_debug_statistics_notif;
3338 priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
b481de9c 3339
9fbab516
BC		 3340 /*
3341 * The same handler is used for both the REPLY to a discrete
3342 * statistics request from the host as well as for the periodic
3343 * statistics notifications (after received beacons) from the uCode.
b481de9c 3344 */
bb8c093b
CH		 3345 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
3346 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
b481de9c 3347
bb8c093b
CH		 3348 priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
3349 priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
b481de9c 3350 priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
bb8c093b 3351 iwl3945_rx_scan_results_notif;
b481de9c 3352 priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
bb8c093b
CH		 3353 iwl3945_rx_scan_complete_notif;
3354 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
b481de9c 3355
9fbab516 3356 /* Set up hardware specific Rx handlers */
bb8c093b 3357 iwl3945_hw_rx_handler_setup(priv);
b481de9c
ZY		 3358}
3359
91c066f2
TW		 3360/**
3361 * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries
3362 * When FW advances 'R' index, all entries between old and new 'R' index
3363 * need to be reclaimed.
3364 */
3365static void iwl3945_cmd_queue_reclaim(struct iwl3945_priv *priv,
3366 int txq_id, int index)
3367{
3368 struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
3369 struct iwl3945_queue *q = &txq->q;
3370 int nfreed = 0;
3371
3372 if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) {
3373 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
3374 "is out of range [0-%d] %d %d.\n", txq_id,
3375 index, q->n_bd, q->write_ptr, q->read_ptr);
3376 return;
3377 }
3378
3379 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
3380 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
3381 if (nfreed > 1) {
3382 IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
3383 q->write_ptr, q->read_ptr);
3384 queue_work(priv->workqueue, &priv->restart);
3385 break;
3386 }
3387 nfreed++;
3388 }
3389}
3390
3391
b481de9c 3392/**
bb8c093b 3393 * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
b481de9c
ZY		 3394 * @rxb: Rx buffer to reclaim
3395 *
3396 * If an Rx buffer has an async callback associated with it the callback
3397 * will be executed. The attached skb (if present) will only be freed
3398 * if the callback returns 1
3399 */
bb8c093b
CH		 3400static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
3401 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3402{
bb8c093b 3403 struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
b481de9c
ZY		 3404 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3405 int txq_id = SEQ_TO_QUEUE(sequence);
3406 int index = SEQ_TO_INDEX(sequence);
3407 int huge = sequence & SEQ_HUGE_FRAME;
3408 int cmd_index;
bb8c093b 3409 struct iwl3945_cmd *cmd;
b481de9c 3410
b481de9c
ZY		 3411 BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
3412
3413 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
3414 cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
3415
3416 /* Input error checking is done when commands are added to queue. */
3417 if (cmd->meta.flags & CMD_WANT_SKB) {
3418 cmd->meta.source->u.skb = rxb->skb;
3419 rxb->skb = NULL;
3420 } else if (cmd->meta.u.callback &&
3421 !cmd->meta.u.callback(priv, cmd, rxb->skb))
3422 rxb->skb = NULL;
3423
91c066f2 3424 iwl3945_cmd_queue_reclaim(priv, txq_id, index);
b481de9c
ZY		 3425
3426 if (!(cmd->meta.flags & CMD_ASYNC)) {
3427 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
3428 wake_up_interruptible(&priv->wait_command_queue);
3429 }
3430}
3431
3432/************************** RX-FUNCTIONS ****************************/
3433/*
3434 * Rx theory of operation
3435 *
3436 * The host allocates 32 DMA target addresses and passes the host address
3437 * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
3438 * 0 to 31
3439 *
3440 * Rx Queue Indexes
3441 * The host/firmware share two index registers for managing the Rx buffers.
3442 *
3443 * The READ index maps to the first position that the firmware may be writing
3444 * to -- the driver can read up to (but not including) this position and get
3445 * good data.
3446 * The READ index is managed by the firmware once the card is enabled.
3447 *
3448 * The WRITE index maps to the last position the driver has read from -- the
3449 * position preceding WRITE is the last slot the firmware can place a packet.
3450 *
3451 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
3452 * WRITE = READ.
3453 *
9fbab516 3454 * During initialization, the host sets up the READ queue position to the first
b481de9c
ZY		 3455 * INDEX position, and WRITE to the last (READ - 1 wrapped)
3456 *
9fbab516 3457 * When the firmware places a packet in a buffer, it will advance the READ index
b481de9c
ZY		 3458 * and fire the RX interrupt. The driver can then query the READ index and
3459 * process as many packets as possible, moving the WRITE index forward as it
3460 * resets the Rx queue buffers with new memory.
3461 *
3462 * The management in the driver is as follows:
3463 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
3464 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
01ebd063 3465 * to replenish the iwl->rxq->rx_free.
bb8c093b 3466 * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
b481de9c
ZY		 3467 * iwl->rxq is replenished and the READ INDEX is updated (updating the
3468 * 'processed' and 'read' driver indexes as well)
3469 * + A received packet is processed and handed to the kernel network stack,
3470 * detached from the iwl->rxq. The driver 'processed' index is updated.
3471 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
3472 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
3473 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
3474 * were enough free buffers and RX_STALLED is set it is cleared.
3475 *
3476 *
3477 * Driver sequence:
3478 *
9fbab516
BC		 3479 * iwl3945_rx_queue_alloc() Allocates rx_free
3480 * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
bb8c093b 3481 * iwl3945_rx_queue_restock
9fbab516 3482 * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
b481de9c
ZY		 3483 * queue, updates firmware pointers, and updates
3484 * the WRITE index. If insufficient rx_free buffers
bb8c093b 3485 * are available, schedules iwl3945_rx_replenish
b481de9c
ZY		 3486 *
3487 * -- enable interrupts --
9fbab516 3488 * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the
b481de9c
ZY		 3489 * READ INDEX, detaching the SKB from the pool.
3490 * Moves the packet buffer from queue to rx_used.
bb8c093b 3491 * Calls iwl3945_rx_queue_restock to refill any empty
b481de9c
ZY		 3492 * slots.
3493 * ...
3494 *
3495 */
3496
3497/**
bb8c093b 3498 * iwl3945_rx_queue_space - Return number of free slots available in queue.
b481de9c 3499 */
bb8c093b 3500static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
b481de9c
ZY		 3501{
3502 int s = q->read - q->write;
3503 if (s <= 0)
3504 s += RX_QUEUE_SIZE;
3505 /* keep some buffer to not confuse full and empty queue */
3506 s -= 2;
3507 if (s < 0)
3508 s = 0;
3509 return s;
3510}
3511
3512/**
bb8c093b 3513 * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
b481de9c 3514 */
bb8c093b 3515int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
b481de9c
ZY		 3516{
3517 u32 reg = 0;
3518 int rc = 0;
3519 unsigned long flags;
3520
3521 spin_lock_irqsave(&q->lock, flags);
3522
3523 if (q->need_update == 0)
3524 goto exit_unlock;
3525
6440adb5 3526 /* If power-saving is in use, make sure device is awake */
b481de9c 3527 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
bb8c093b 3528 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY		 3529
3530 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
bb8c093b 3531 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 3532 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3533 goto exit_unlock;
3534 }
3535
bb8c093b 3536 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 3537 if (rc)
3538 goto exit_unlock;
3539
6440adb5 3540 /* Device expects a multiple of 8 */
bb8c093b 3541 iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
b481de9c 3542 q->write & ~0x7);
bb8c093b 3543 iwl3945_release_nic_access(priv);
6440adb5
CB		 3544
3545 /* Else device is assumed to be awake */
b481de9c 3546 } else
6440adb5 3547 /* Device expects a multiple of 8 */
bb8c093b 3548 iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
b481de9c
ZY		 3549
3550
3551 q->need_update = 0;
3552
3553 exit_unlock:
3554 spin_unlock_irqrestore(&q->lock, flags);
3555 return rc;
3556}
3557
3558/**
9fbab516 3559 * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
b481de9c 3560 */
bb8c093b 3561static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
b481de9c
ZY		 3562 dma_addr_t dma_addr)
3563{
3564 return cpu_to_le32((u32)dma_addr);
3565}
3566
3567/**
bb8c093b 3568 * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
b481de9c 3569 *
9fbab516 3570 * If there are slots in the RX queue that need to be restocked,
b481de9c 3571 * and we have free pre-allocated buffers, fill the ranks as much
9fbab516 3572 * as we can, pulling from rx_free.
b481de9c
ZY		 3573 *
3574 * This moves the 'write' index forward to catch up with 'processed', and
3575 * also updates the memory address in the firmware to reference the new
3576 * target buffer.
3577 */
bb8c093b 3578static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
b481de9c 3579{
bb8c093b 3580 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 3581 struct list_head *element;
bb8c093b 3582 struct iwl3945_rx_mem_buffer *rxb;
b481de9c
ZY		 3583 unsigned long flags;
3584 int write, rc;
3585
3586 spin_lock_irqsave(&rxq->lock, flags);
3587 write = rxq->write & ~0x7;
bb8c093b 3588 while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
6440adb5 3589 /* Get next free Rx buffer, remove from free list */
b481de9c 3590 element = rxq->rx_free.next;
bb8c093b 3591 rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
b481de9c 3592 list_del(element);
6440adb5
CB		 3593
3594 /* Point to Rx buffer via next RBD in circular buffer */
bb8c093b 3595 rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
b481de9c
ZY		 3596 rxq->queue[rxq->write] = rxb;
3597 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
3598 rxq->free_count--;
3599 }
3600 spin_unlock_irqrestore(&rxq->lock, flags);
3601 /* If the pre-allocated buffer pool is dropping low, schedule to
3602 * refill it */
3603 if (rxq->free_count <= RX_LOW_WATERMARK)
3604 queue_work(priv->workqueue, &priv->rx_replenish);
3605
3606
6440adb5
CB		 3607 /* If we've added more space for the firmware to place data, tell it.
3608 * Increment device's write pointer in multiples of 8. */
b481de9c
ZY		 3609 if ((write != (rxq->write & ~0x7))
3610 || (abs(rxq->write - rxq->read) > 7)) {
3611 spin_lock_irqsave(&rxq->lock, flags);
3612 rxq->need_update = 1;
3613 spin_unlock_irqrestore(&rxq->lock, flags);
bb8c093b 3614 rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 3615 if (rc)
3616 return rc;
3617 }
3618
3619 return 0;
3620}
3621
3622/**
bb8c093b 3623 * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
b481de9c
ZY		 3624 *
3625 * When moving to rx_free an SKB is allocated for the slot.
3626 *
bb8c093b 3627 * Also restock the Rx queue via iwl3945_rx_queue_restock.
01ebd063 3628 * This is called as a scheduled work item (except for during initialization)
b481de9c 3629 */
5c0eef96 3630static void iwl3945_rx_allocate(struct iwl3945_priv *priv)
b481de9c 3631{
bb8c093b 3632 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 3633 struct list_head *element;
bb8c093b 3634 struct iwl3945_rx_mem_buffer *rxb;
b481de9c
ZY		 3635 unsigned long flags;
3636 spin_lock_irqsave(&rxq->lock, flags);
3637 while (!list_empty(&rxq->rx_used)) {
3638 element = rxq->rx_used.next;
bb8c093b 3639 rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
6440adb5
CB		 3640
3641 /* Alloc a new receive buffer */
b481de9c
ZY		 3642 rxb->skb =
3643 alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
3644 if (!rxb->skb) {
3645 if (net_ratelimit())
3646 printk(KERN_CRIT DRV_NAME
3647 ": Can not allocate SKB buffers\n");
3648 /* We don't reschedule replenish work here -- we will
3649 * call the restock method and if it still needs
3650 * more buffers it will schedule replenish */
3651 break;
3652 }
12342c47
ZY		 3653
3654 /* If radiotap head is required, reserve some headroom here.
3655 * The physical head count is a variable rx_stats->phy_count.
3656 * We reserve 4 bytes here. Plus these extra bytes, the
3657 * headroom of the physical head should be enough for the
3658 * radiotap head that iwl3945 supported. See iwl3945_rt.
3659 */
3660 skb_reserve(rxb->skb, 4);
3661
b481de9c
ZY		 3662 priv->alloc_rxb_skb++;
3663 list_del(element);
6440adb5
CB		 3664
3665 /* Get physical address of RB/SKB */
b481de9c
ZY		 3666 rxb->dma_addr =
3667 pci_map_single(priv->pci_dev, rxb->skb->data,
3668 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3669 list_add_tail(&rxb->list, &rxq->rx_free);
3670 rxq->free_count++;
3671 }
3672 spin_unlock_irqrestore(&rxq->lock, flags);
5c0eef96
MA		 3673}
3674
3675/*
3676 * this should be called while priv->lock is locked
3677 */
4fd1f841 3678static void __iwl3945_rx_replenish(void *data)
5c0eef96
MA		 3679{
3680 struct iwl3945_priv *priv = data;
3681
3682 iwl3945_rx_allocate(priv);
3683 iwl3945_rx_queue_restock(priv);
3684}
3685
3686
3687void iwl3945_rx_replenish(void *data)
3688{
3689 struct iwl3945_priv *priv = data;
3690 unsigned long flags;
3691
3692 iwl3945_rx_allocate(priv);
b481de9c
ZY		 3693
3694 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 3695 iwl3945_rx_queue_restock(priv);
b481de9c
ZY		 3696 spin_unlock_irqrestore(&priv->lock, flags);
3697}
3698
3699/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
9fbab516 3700 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
b481de9c
ZY		 3701 * This free routine walks the list of POOL entries and if SKB is set to
3702 * non NULL it is unmapped and freed
3703 */
bb8c093b 3704static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY		 3705{
3706 int i;
3707 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
3708 if (rxq->pool[i].skb != NULL) {
3709 pci_unmap_single(priv->pci_dev,
3710 rxq->pool[i].dma_addr,
3711 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3712 dev_kfree_skb(rxq->pool[i].skb);
3713 }
3714 }
3715
3716 pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
3717 rxq->dma_addr);
3718 rxq->bd = NULL;
3719}
3720
bb8c093b 3721int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
b481de9c 3722{
bb8c093b 3723 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 3724 struct pci_dev *dev = priv->pci_dev;
3725 int i;
3726
3727 spin_lock_init(&rxq->lock);
3728 INIT_LIST_HEAD(&rxq->rx_free);
3729 INIT_LIST_HEAD(&rxq->rx_used);
6440adb5
CB		 3730
3731 /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
b481de9c
ZY		 3732 rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
3733 if (!rxq->bd)
3734 return -ENOMEM;
6440adb5 3735
b481de9c
ZY		 3736 /* Fill the rx_used queue with _all_ of the Rx buffers */
3737 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
3738 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
6440adb5 3739
b481de9c
ZY		 3740 /* Set us so that we have processed and used all buffers, but have
3741 * not restocked the Rx queue with fresh buffers */
3742 rxq->read = rxq->write = 0;
3743 rxq->free_count = 0;
3744 rxq->need_update = 0;
3745 return 0;
3746}
3747
bb8c093b 3748void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY		 3749{
3750 unsigned long flags;
3751 int i;
3752 spin_lock_irqsave(&rxq->lock, flags);
3753 INIT_LIST_HEAD(&rxq->rx_free);
3754 INIT_LIST_HEAD(&rxq->rx_used);
3755 /* Fill the rx_used queue with _all_ of the Rx buffers */
3756 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
3757 /* In the reset function, these buffers may have been allocated
3758 * to an SKB, so we need to unmap and free potential storage */
3759 if (rxq->pool[i].skb != NULL) {
3760 pci_unmap_single(priv->pci_dev,
3761 rxq->pool[i].dma_addr,
3762 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3763 priv->alloc_rxb_skb--;
3764 dev_kfree_skb(rxq->pool[i].skb);
3765 rxq->pool[i].skb = NULL;
3766 }
3767 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
3768 }
3769
3770 /* Set us so that we have processed and used all buffers, but have
3771 * not restocked the Rx queue with fresh buffers */
3772 rxq->read = rxq->write = 0;
3773 rxq->free_count = 0;
3774 spin_unlock_irqrestore(&rxq->lock, flags);
3775}
3776
3777/* Convert linear signal-to-noise ratio into dB */
3778static u8 ratio2dB[100] = {
3779/* 0 1 2 3 4 5 6 7 8 9 */
3780 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
3781 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
3782 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
3783 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
3784 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
3785 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
3786 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
3787 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
3788 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
3789 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
3790};
3791
3792/* Calculates a relative dB value from a ratio of linear
3793 * (i.e. not dB) signal levels.
3794 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
bb8c093b 3795int iwl3945_calc_db_from_ratio(int sig_ratio)
b481de9c 3796{
221c80cf
AB		 3797 /* 1000:1 or higher just report as 60 dB */
3798 if (sig_ratio >= 1000)
b481de9c
ZY		 3799 return 60;
3800
221c80cf 3801 /* 100:1 or higher, divide by 10 and use table,
b481de9c 3802 * add 20 dB to make up for divide by 10 */
221c80cf 3803 if (sig_ratio >= 100)
3ac7f146 3804 return 20 + (int)ratio2dB[sig_ratio/10];
b481de9c
ZY		 3805
3806 /* We shouldn't see this */
3807 if (sig_ratio < 1)
3808 return 0;
3809
3810 /* Use table for ratios 1:1 - 99:1 */
3811 return (int)ratio2dB[sig_ratio];
3812}
3813
3814#define PERFECT_RSSI (-20) /* dBm */
3815#define WORST_RSSI (-95) /* dBm */
3816#define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
3817
3818/* Calculate an indication of rx signal quality (a percentage, not dBm!).
3819 * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
3820 * about formulas used below. */
bb8c093b 3821int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
b481de9c
ZY		 3822{
3823 int sig_qual;
3824 int degradation = PERFECT_RSSI - rssi_dbm;
3825
3826 /* If we get a noise measurement, use signal-to-noise ratio (SNR)
3827 * as indicator; formula is (signal dbm - noise dbm).
3828 * SNR at or above 40 is a great signal (100%).
3829 * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
3830 * Weakest usable signal is usually 10 - 15 dB SNR. */
3831 if (noise_dbm) {
3832 if (rssi_dbm - noise_dbm >= 40)
3833 return 100;
3834 else if (rssi_dbm < noise_dbm)
3835 return 0;
3836 sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
3837
3838 /* Else use just the signal level.
3839 * This formula is a least squares fit of data points collected and
3840 * compared with a reference system that had a percentage (%) display
3841 * for signal quality. */
3842 } else
3843 sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
3844 (15 * RSSI_RANGE + 62 * degradation)) /
3845 (RSSI_RANGE * RSSI_RANGE);
3846
3847 if (sig_qual > 100)
3848 sig_qual = 100;
3849 else if (sig_qual < 1)
3850 sig_qual = 0;
3851
3852 return sig_qual;
3853}
3854
3855/**
9fbab516 3856 * iwl3945_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY		 3857 *
3858 * Uses the priv->rx_handlers callback function array to invoke
3859 * the appropriate handlers, including command responses,
3860 * frame-received notifications, and other notifications.
3861 */
bb8c093b 3862static void iwl3945_rx_handle(struct iwl3945_priv *priv)
b481de9c 3863{
bb8c093b
CH		 3864 struct iwl3945_rx_mem_buffer *rxb;
3865 struct iwl3945_rx_packet *pkt;
3866 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 3867 u32 r, i;
3868 int reclaim;
3869 unsigned long flags;
5c0eef96 3870 u8 fill_rx = 0;
d68ab680 3871 u32 count = 8;
b481de9c 3872
6440adb5
CB		 3873 /* uCode's read index (stored in shared DRAM) indicates the last Rx
3874 * buffer that the driver may process (last buffer filled by ucode). */
bb8c093b 3875 r = iwl3945_hw_get_rx_read(priv);
b481de9c
ZY		 3876 i = rxq->read;
3877
5c0eef96
MA		 3878 if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
3879 fill_rx = 1;
b481de9c
ZY		 3880 /* Rx interrupt, but nothing sent from uCode */
3881 if (i == r)
3882 IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
3883
3884 while (i != r) {
3885 rxb = rxq->queue[i];
3886
9fbab516 3887 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY		 3888 * then a bug has been introduced in the queue refilling
3889 * routines -- catch it here */
3890 BUG_ON(rxb == NULL);
3891
3892 rxq->queue[i] = NULL;
3893
3894 pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
3895 IWL_RX_BUF_SIZE,
3896 PCI_DMA_FROMDEVICE);
bb8c093b 3897 pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
b481de9c
ZY		 3898
3899 /* Reclaim a command buffer only if this packet is a response
3900 * to a (driver-originated) command.
3901 * If the packet (e.g. Rx frame) originated from uCode,
3902 * there is no command buffer to reclaim.
3903 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
3904 * but apparently a few don't get set; catch them here. */
3905 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
3906 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
3907 (pkt->hdr.cmd != REPLY_TX);
3908
3909 /* Based on type of command response or notification,
3910 * handle those that need handling via function in
bb8c093b 3911 * rx_handlers table. See iwl3945_setup_rx_handlers() */
b481de9c
ZY		 3912 if (priv->rx_handlers[pkt->hdr.cmd]) {
3913 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
3914 "r = %d, i = %d, %s, 0x%02x\n", r, i,
3915 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
3916 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
3917 } else {
3918 /* No handling needed */
3919 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
3920 "r %d i %d No handler needed for %s, 0x%02x\n",
3921 r, i, get_cmd_string(pkt->hdr.cmd),
3922 pkt->hdr.cmd);
3923 }
3924
3925 if (reclaim) {
9fbab516
BC		 3926 /* Invoke any callbacks, transfer the skb to caller, and
3927 * fire off the (possibly) blocking iwl3945_send_cmd()
b481de9c
ZY		 3928 * as we reclaim the driver command queue */
3929 if (rxb && rxb->skb)
bb8c093b 3930 iwl3945_tx_cmd_complete(priv, rxb);
b481de9c
ZY		 3931 else
3932 IWL_WARNING("Claim null rxb?\n");
3933 }
3934
3935 /* For now we just don't re-use anything. We can tweak this
3936 * later to try and re-use notification packets and SKBs that
3937 * fail to Rx correctly */
3938 if (rxb->skb != NULL) {
3939 priv->alloc_rxb_skb--;
3940 dev_kfree_skb_any(rxb->skb);
3941 rxb->skb = NULL;
3942 }
3943
3944 pci_unmap_single(priv->pci_dev, rxb->dma_addr,
3945 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3946 spin_lock_irqsave(&rxq->lock, flags);
3947 list_add_tail(&rxb->list, &priv->rxq.rx_used);
3948 spin_unlock_irqrestore(&rxq->lock, flags);
3949 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA		 3950 /* If there are a lot of unused frames,
3951 * restock the Rx queue so ucode won't assert. */
3952 if (fill_rx) {
3953 count++;
3954 if (count >= 8) {
3955 priv->rxq.read = i;
3956 __iwl3945_rx_replenish(priv);
3957 count = 0;
3958 }
3959 }
b481de9c
ZY		 3960 }
3961
3962 /* Backtrack one entry */
3963 priv->rxq.read = i;
bb8c093b 3964 iwl3945_rx_queue_restock(priv);
b481de9c
ZY		 3965}
3966
6440adb5
CB		 3967/**
3968 * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
3969 */
bb8c093b
CH		 3970static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
3971 struct iwl3945_tx_queue *txq)
b481de9c
ZY		 3972{
3973 u32 reg = 0;
3974 int rc = 0;
3975 int txq_id = txq->q.id;
3976
3977 if (txq->need_update == 0)
3978 return rc;
3979
3980 /* if we're trying to save power */
3981 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
3982 /* wake up nic if it's powered down ...
3983 * uCode will wake up, and interrupt us again, so next
3984 * time we'll skip this part. */
bb8c093b 3985 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY		 3986
3987 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
3988 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
bb8c093b 3989 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 3990 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3991 return rc;
3992 }
3993
3994 /* restore this queue's parameters in nic hardware. */
bb8c093b 3995 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 3996 if (rc)
3997 return rc;
bb8c093b 3998 iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
fc4b6853 3999 txq->q.write_ptr | (txq_id << 8));
bb8c093b 4000 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4001
4002 /* else not in power-save mode, uCode will never sleep when we're
4003 * trying to tx (during RFKILL, we're not trying to tx). */
4004 } else
bb8c093b 4005 iwl3945_write32(priv, HBUS_TARG_WRPTR,
fc4b6853 4006 txq->q.write_ptr | (txq_id << 8));
b481de9c
ZY		 4007
4008 txq->need_update = 0;
4009
4010 return rc;
4011}
4012
c8b0e6e1 4013#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4014static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon)
b481de9c
ZY		 4015{
4016 IWL_DEBUG_RADIO("RX CONFIG:\n");
bb8c093b 4017 iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
b481de9c
ZY		 4018 IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
4019 IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
4020 IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
4021 le32_to_cpu(rxon->filter_flags));
4022 IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
4023 IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
4024 rxon->ofdm_basic_rates);
4025 IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
e174961c
JB		 4026 IWL_DEBUG_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
4027 IWL_DEBUG_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
b481de9c
ZY		 4028 IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
4029}
4030#endif
4031
bb8c093b 4032static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
b481de9c
ZY		 4033{
4034 IWL_DEBUG_ISR("Enabling interrupts\n");
4035 set_bit(STATUS_INT_ENABLED, &priv->status);
bb8c093b 4036 iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
b481de9c
ZY		 4037}
4038
0359facc
MA		 4039
4040/* call this function to flush any scheduled tasklet */
4041static inline void iwl_synchronize_irq(struct iwl3945_priv *priv)
4042{
4043 /* wait to make sure we flush pedding tasklet*/
4044 synchronize_irq(priv->pci_dev->irq);
4045 tasklet_kill(&priv->irq_tasklet);
4046}
4047
4048
bb8c093b 4049static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
b481de9c
ZY		 4050{
4051 clear_bit(STATUS_INT_ENABLED, &priv->status);
4052
4053 /* disable interrupts from uCode/NIC to host */
bb8c093b 4054 iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY		 4055
4056 /* acknowledge/clear/reset any interrupts still pending
4057 * from uCode or flow handler (Rx/Tx DMA) */
bb8c093b
CH		 4058 iwl3945_write32(priv, CSR_INT, 0xffffffff);
4059 iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
b481de9c
ZY		 4060 IWL_DEBUG_ISR("Disabled interrupts\n");
4061}
4062
4063static const char *desc_lookup(int i)
4064{
4065 switch (i) {
4066 case 1:
4067 return "FAIL";
4068 case 2:
4069 return "BAD_PARAM";
4070 case 3:
4071 return "BAD_CHECKSUM";
4072 case 4:
4073 return "NMI_INTERRUPT";
4074 case 5:
4075 return "SYSASSERT";
4076 case 6:
4077 return "FATAL_ERROR";
4078 }
4079
4080 return "UNKNOWN";
4081}
4082
4083#define ERROR_START_OFFSET (1 * sizeof(u32))
4084#define ERROR_ELEM_SIZE (7 * sizeof(u32))
4085
bb8c093b 4086static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
b481de9c
ZY		 4087{
4088 u32 i;
4089 u32 desc, time, count, base, data1;
4090 u32 blink1, blink2, ilink1, ilink2;
4091 int rc;
4092
4093 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
4094
bb8c093b 4095 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 4096 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
4097 return;
4098 }
4099
bb8c093b 4100 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 4101 if (rc) {
4102 IWL_WARNING("Can not read from adapter at this time.\n");
4103 return;
4104 }
4105
bb8c093b 4106 count = iwl3945_read_targ_mem(priv, base);
b481de9c
ZY		 4107
4108 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
4109 IWL_ERROR("Start IWL Error Log Dump:\n");
2acae16e 4110 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
b481de9c
ZY		 4111 }
4112
4113 IWL_ERROR("Desc Time asrtPC blink2 "
4114 "ilink1 nmiPC Line\n");
4115 for (i = ERROR_START_OFFSET;
4116 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
4117 i += ERROR_ELEM_SIZE) {
bb8c093b 4118 desc = iwl3945_read_targ_mem(priv, base + i);
b481de9c 4119 time =
bb8c093b 4120 iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
b481de9c 4121 blink1 =
bb8c093b 4122 iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
b481de9c 4123 blink2 =
bb8c093b 4124 iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
b481de9c 4125 ilink1 =
bb8c093b 4126 iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
b481de9c 4127 ilink2 =
bb8c093b 4128 iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
b481de9c 4129 data1 =
bb8c093b 4130 iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
b481de9c
ZY		 4131
4132 IWL_ERROR
4133 ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
4134 desc_lookup(desc), desc, time, blink1, blink2,
4135 ilink1, ilink2, data1);
4136 }
4137
bb8c093b 4138 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4139
4140}
4141
f58177b9 4142#define EVENT_START_OFFSET (6 * sizeof(u32))
b481de9c
ZY		 4143
4144/**
bb8c093b 4145 * iwl3945_print_event_log - Dump error event log to syslog
b481de9c 4146 *
bb8c093b 4147 * NOTE: Must be called with iwl3945_grab_nic_access() already obtained!
b481de9c 4148 */
bb8c093b 4149static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
b481de9c
ZY		 4150 u32 num_events, u32 mode)
4151{
4152 u32 i;
4153 u32 base; /* SRAM byte address of event log header */
4154 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
4155 u32 ptr; /* SRAM byte address of log data */
4156 u32 ev, time, data; /* event log data */
4157
4158 if (num_events == 0)
4159 return;
4160
4161 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
4162
4163 if (mode == 0)
4164 event_size = 2 * sizeof(u32);
4165 else
4166 event_size = 3 * sizeof(u32);
4167
4168 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
4169
4170 /* "time" is actually "data" for mode 0 (no timestamp).
4171 * place event id # at far right for easier visual parsing. */
4172 for (i = 0; i < num_events; i++) {
bb8c093b 4173 ev = iwl3945_read_targ_mem(priv, ptr);
b481de9c 4174 ptr += sizeof(u32);
bb8c093b 4175 time = iwl3945_read_targ_mem(priv, ptr);
b481de9c
ZY		 4176 ptr += sizeof(u32);
4177 if (mode == 0)
4178 IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
4179 else {
bb8c093b 4180 data = iwl3945_read_targ_mem(priv, ptr);
b481de9c
ZY		 4181 ptr += sizeof(u32);
4182 IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
4183 }
4184 }
4185}
4186
bb8c093b 4187static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
b481de9c
ZY		 4188{
4189 int rc;
4190 u32 base; /* SRAM byte address of event log header */
4191 u32 capacity; /* event log capacity in # entries */
4192 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
4193 u32 num_wraps; /* # times uCode wrapped to top of log */
4194 u32 next_entry; /* index of next entry to be written by uCode */
4195 u32 size; /* # entries that we'll print */
4196
4197 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 4198 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 4199 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
4200 return;
4201 }
4202
bb8c093b 4203 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 4204 if (rc) {
4205 IWL_WARNING("Can not read from adapter at this time.\n");
4206 return;
4207 }
4208
4209 /* event log header */
bb8c093b
CH		 4210 capacity = iwl3945_read_targ_mem(priv, base);
4211 mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
4212 num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
4213 next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
b481de9c
ZY		 4214
4215 size = num_wraps ? capacity : next_entry;
4216
4217 /* bail out if nothing in log */
4218 if (size == 0) {
583fab37 4219 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
bb8c093b 4220 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4221 return;
4222 }
4223
583fab37 4224 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
b481de9c
ZY		 4225 size, num_wraps);
4226
4227 /* if uCode has wrapped back to top of log, start at the oldest entry,
4228 * i.e the next one that uCode would fill. */
4229 if (num_wraps)
bb8c093b 4230 iwl3945_print_event_log(priv, next_entry,
b481de9c
ZY		 4231 capacity - next_entry, mode);
4232
4233 /* (then/else) start at top of log */
bb8c093b 4234 iwl3945_print_event_log(priv, 0, next_entry, mode);
b481de9c 4235
bb8c093b 4236 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4237}
4238
4239/**
bb8c093b 4240 * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
b481de9c 4241 */
bb8c093b 4242static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
b481de9c 4243{
bb8c093b 4244 /* Set the FW error flag -- cleared on iwl3945_down */
b481de9c
ZY		 4245 set_bit(STATUS_FW_ERROR, &priv->status);
4246
4247 /* Cancel currently queued command. */
4248 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
4249
c8b0e6e1 4250#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 4251 if (iwl3945_debug_level & IWL_DL_FW_ERRORS) {
4252 iwl3945_dump_nic_error_log(priv);
4253 iwl3945_dump_nic_event_log(priv);
4254 iwl3945_print_rx_config_cmd(&priv->staging_rxon);
b481de9c
ZY		 4255 }
4256#endif
4257
4258 wake_up_interruptible(&priv->wait_command_queue);
4259
4260 /* Keep the restart process from trying to send host
4261 * commands by clearing the INIT status bit */
4262 clear_bit(STATUS_READY, &priv->status);
4263
4264 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
4265 IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
4266 "Restarting adapter due to uCode error.\n");
4267
bb8c093b 4268 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 4269 memcpy(&priv->recovery_rxon, &priv->active_rxon,
4270 sizeof(priv->recovery_rxon));
4271 priv->error_recovering = 1;
4272 }
4273 queue_work(priv->workqueue, &priv->restart);
4274 }
4275}
4276
bb8c093b 4277static void iwl3945_error_recovery(struct iwl3945_priv *priv)
b481de9c
ZY		 4278{
4279 unsigned long flags;
4280
4281 memcpy(&priv->staging_rxon, &priv->recovery_rxon,
4282 sizeof(priv->staging_rxon));
4283 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 4284 iwl3945_commit_rxon(priv);
b481de9c 4285
bb8c093b 4286 iwl3945_add_station(priv, priv->bssid, 1, 0);
b481de9c
ZY		 4287
4288 spin_lock_irqsave(&priv->lock, flags);
4289 priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
4290 priv->error_recovering = 0;
4291 spin_unlock_irqrestore(&priv->lock, flags);
4292}
4293
bb8c093b 4294static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
b481de9c
ZY		 4295{
4296 u32 inta, handled = 0;
4297 u32 inta_fh;
4298 unsigned long flags;
c8b0e6e1 4299#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 4300 u32 inta_mask;
4301#endif
4302
4303 spin_lock_irqsave(&priv->lock, flags);
4304
4305 /* Ack/clear/reset pending uCode interrupts.
4306 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
4307 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
bb8c093b
CH		 4308 inta = iwl3945_read32(priv, CSR_INT);
4309 iwl3945_write32(priv, CSR_INT, inta);
b481de9c
ZY		 4310
4311 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
4312 * Any new interrupts that happen after this, either while we're
4313 * in this tasklet, or later, will show up in next ISR/tasklet. */
bb8c093b
CH		 4314 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
4315 iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 4316
c8b0e6e1 4317#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4318 if (iwl3945_debug_level & IWL_DL_ISR) {
9fbab516
BC		 4319 /* just for debug */
4320 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
b481de9c
ZY		 4321 IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4322 inta, inta_mask, inta_fh);
4323 }
4324#endif
4325
4326 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
4327 * atomic, make sure that inta covers all the interrupts that
4328 * we've discovered, even if FH interrupt came in just after
4329 * reading CSR_INT. */
6f83eaa1 4330 if (inta_fh & CSR39_FH_INT_RX_MASK)
b481de9c 4331 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 4332 if (inta_fh & CSR39_FH_INT_TX_MASK)
b481de9c
ZY		 4333 inta |= CSR_INT_BIT_FH_TX;
4334
4335 /* Now service all interrupt bits discovered above. */
4336 if (inta & CSR_INT_BIT_HW_ERR) {
4337 IWL_ERROR("Microcode HW error detected. Restarting.\n");
4338
4339 /* Tell the device to stop sending interrupts */
bb8c093b 4340 iwl3945_disable_interrupts(priv);
b481de9c 4341
bb8c093b 4342 iwl3945_irq_handle_error(priv);
b481de9c
ZY		 4343
4344 handled |= CSR_INT_BIT_HW_ERR;
4345
4346 spin_unlock_irqrestore(&priv->lock, flags);
4347
4348 return;
4349 }
4350
c8b0e6e1 4351#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4352 if (iwl3945_debug_level & (IWL_DL_ISR)) {
b481de9c 4353 /* NIC fires this, but we don't use it, redundant with WAKEUP */
25c03d8e
JP		 4354 if (inta & CSR_INT_BIT_SCD)
4355 IWL_DEBUG_ISR("Scheduler finished to transmit "
4356 "the frame/frames.\n");
b481de9c
ZY		 4357
4358 /* Alive notification via Rx interrupt will do the real work */
4359 if (inta & CSR_INT_BIT_ALIVE)
4360 IWL_DEBUG_ISR("Alive interrupt\n");
4361 }
4362#endif
4363 /* Safely ignore these bits for debug checks below */
25c03d8e 4364 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c
ZY		 4365
4366 /* HW RF KILL switch toggled (4965 only) */
4367 if (inta & CSR_INT_BIT_RF_KILL) {
4368 int hw_rf_kill = 0;
bb8c093b 4369 if (!(iwl3945_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY		 4370 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
4371 hw_rf_kill = 1;
4372
4373 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR,
4374 "RF_KILL bit toggled to %s.\n",
4375 hw_rf_kill ? "disable radio":"enable radio");
4376
4377 /* Queue restart only if RF_KILL switch was set to "kill"
4378 * when we loaded driver, and is now set to "enable".
4379 * After we're Alive, RF_KILL gets handled by
3230455d 4380 * iwl3945_rx_card_state_notif() */
53e49093
ZY		 4381 if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) {
4382 clear_bit(STATUS_RF_KILL_HW, &priv->status);
b481de9c 4383 queue_work(priv->workqueue, &priv->restart);
53e49093 4384 }
b481de9c
ZY		 4385
4386 handled |= CSR_INT_BIT_RF_KILL;
4387 }
4388
4389 /* Chip got too hot and stopped itself (4965 only) */
4390 if (inta & CSR_INT_BIT_CT_KILL) {
4391 IWL_ERROR("Microcode CT kill error detected.\n");
4392 handled |= CSR_INT_BIT_CT_KILL;
4393 }
4394
4395 /* Error detected by uCode */
4396 if (inta & CSR_INT_BIT_SW_ERR) {
4397 IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
4398 inta);
bb8c093b 4399 iwl3945_irq_handle_error(priv);
b481de9c
ZY		 4400 handled |= CSR_INT_BIT_SW_ERR;
4401 }
4402
4403 /* uCode wakes up after power-down sleep */
4404 if (inta & CSR_INT_BIT_WAKEUP) {
4405 IWL_DEBUG_ISR("Wakeup interrupt\n");
bb8c093b
CH		 4406 iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
4407 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
4408 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
4409 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
4410 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
4411 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
4412 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
b481de9c
ZY		 4413
4414 handled |= CSR_INT_BIT_WAKEUP;
4415 }
4416
4417 /* All uCode command responses, including Tx command responses,
4418 * Rx "responses" (frame-received notification), and other
4419 * notifications from uCode come through here*/
4420 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
bb8c093b 4421 iwl3945_rx_handle(priv);
b481de9c
ZY		 4422 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
4423 }
4424
4425 if (inta & CSR_INT_BIT_FH_TX) {
4426 IWL_DEBUG_ISR("Tx interrupt\n");
4427
bb8c093b
CH		 4428 iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
4429 if (!iwl3945_grab_nic_access(priv)) {
4430 iwl3945_write_direct32(priv,
b481de9c
ZY		 4431 FH_TCSR_CREDIT
4432 (ALM_FH_SRVC_CHNL), 0x0);
bb8c093b 4433 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4434 }
4435 handled |= CSR_INT_BIT_FH_TX;
4436 }
4437
4438 if (inta & ~handled)
4439 IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
4440
4441 if (inta & ~CSR_INI_SET_MASK) {
4442 IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
4443 inta & ~CSR_INI_SET_MASK);
4444 IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
4445 }
4446
4447 /* Re-enable all interrupts */
0359facc
MA		 4448 /* only Re-enable if disabled by irq */
4449 if (test_bit(STATUS_INT_ENABLED, &priv->status))
4450 iwl3945_enable_interrupts(priv);
b481de9c 4451
c8b0e6e1 4452#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 4453 if (iwl3945_debug_level & (IWL_DL_ISR)) {
4454 inta = iwl3945_read32(priv, CSR_INT);
4455 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
4456 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY		 4457 IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4458 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
4459 }
4460#endif
4461 spin_unlock_irqrestore(&priv->lock, flags);
4462}
4463
bb8c093b 4464static irqreturn_t iwl3945_isr(int irq, void *data)
b481de9c 4465{
bb8c093b 4466 struct iwl3945_priv *priv = data;
b481de9c
ZY		 4467 u32 inta, inta_mask;
4468 u32 inta_fh;
4469 if (!priv)
4470 return IRQ_NONE;
4471
4472 spin_lock(&priv->lock);
4473
4474 /* Disable (but don't clear!) interrupts here to avoid
4475 * back-to-back ISRs and sporadic interrupts from our NIC.
4476 * If we have something to service, the tasklet will re-enable ints.
4477 * If we *don't* have something, we'll re-enable before leaving here. */
bb8c093b
CH		 4478 inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */
4479 iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY		 4480
4481 /* Discover which interrupts are active/pending */
bb8c093b
CH		 4482 inta = iwl3945_read32(priv, CSR_INT);
4483 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY		 4484
4485 /* Ignore interrupt if there's nothing in NIC to service.
4486 * This may be due to IRQ shared with another device,
4487 * or due to sporadic interrupts thrown from our NIC. */
4488 if (!inta && !inta_fh) {
4489 IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
4490 goto none;
4491 }
4492
4493 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
4494 /* Hardware disappeared */
4495 IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta);
cb4da1a3 4496 goto unplugged;
b481de9c
ZY		 4497 }
4498
4499 IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4500 inta, inta_mask, inta_fh);
4501
25c03d8e
JP		 4502 inta &= ~CSR_INT_BIT_SCD;
4503
bb8c093b 4504 /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
25c03d8e
JP		 4505 if (likely(inta || inta_fh))
4506 tasklet_schedule(&priv->irq_tasklet);
cb4da1a3 4507unplugged:
b481de9c
ZY		 4508 spin_unlock(&priv->lock);
4509
4510 return IRQ_HANDLED;
4511
4512 none:
4513 /* re-enable interrupts here since we don't have anything to service. */
0359facc
MA		 4514 /* only Re-enable if disabled by irq */
4515 if (test_bit(STATUS_INT_ENABLED, &priv->status))
4516 iwl3945_enable_interrupts(priv);
b481de9c
ZY		 4517 spin_unlock(&priv->lock);
4518 return IRQ_NONE;
4519}
4520
4521/************************** EEPROM BANDS ****************************
4522 *
bb8c093b 4523 * The iwl3945_eeprom_band definitions below provide the mapping from the
b481de9c
ZY		 4524 * EEPROM contents to the specific channel number supported for each
4525 * band.
4526 *
bb8c093b 4527 * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3
b481de9c
ZY		 4528 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
4529 * The specific geography and calibration information for that channel
4530 * is contained in the eeprom map itself.
4531 *
4532 * During init, we copy the eeprom information and channel map
4533 * information into priv->channel_info_24/52 and priv->channel_map_24/52
4534 *
4535 * channel_map_24/52 provides the index in the channel_info array for a
4536 * given channel. We have to have two separate maps as there is channel
4537 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
4538 * band_2
4539 *
4540 * A value of 0xff stored in the channel_map indicates that the channel
4541 * is not supported by the hardware at all.
4542 *
4543 * A value of 0xfe in the channel_map indicates that the channel is not
4544 * valid for Tx with the current hardware. This means that
4545 * while the system can tune and receive on a given channel, it may not
4546 * be able to associate or transmit any frames on that
4547 * channel. There is no corresponding channel information for that
4548 * entry.
4549 *
4550 *********************************************************************/
4551
4552/* 2.4 GHz */
bb8c093b 4553static const u8 iwl3945_eeprom_band_1[14] = {
b481de9c
ZY		 4554 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
4555};
4556
4557/* 5.2 GHz bands */
9fbab516 4558static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
b481de9c
ZY		 4559 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
4560};
4561
9fbab516 4562static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
b481de9c
ZY		 4563 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
4564};
4565
bb8c093b 4566static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
b481de9c
ZY		 4567 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
4568};
4569
bb8c093b 4570static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
b481de9c
ZY		 4571 145, 149, 153, 157, 161, 165
4572};
4573
bb8c093b 4574static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
b481de9c 4575 int *eeprom_ch_count,
bb8c093b 4576 const struct iwl3945_eeprom_channel
b481de9c
ZY		 4577 **eeprom_ch_info,
4578 const u8 **eeprom_ch_index)
4579{
4580 switch (band) {
4581 case 1: /* 2.4GHz band */
bb8c093b 4582 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
b481de9c 4583 *eeprom_ch_info = priv->eeprom.band_1_channels;
bb8c093b 4584 *eeprom_ch_index = iwl3945_eeprom_band_1;
b481de9c 4585 break;
9fbab516 4586 case 2: /* 4.9GHz band */
bb8c093b 4587 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
b481de9c 4588 *eeprom_ch_info = priv->eeprom.band_2_channels;
bb8c093b 4589 *eeprom_ch_index = iwl3945_eeprom_band_2;
b481de9c
ZY		 4590 break;
4591 case 3: /* 5.2GHz band */
bb8c093b 4592 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
b481de9c 4593 *eeprom_ch_info = priv->eeprom.band_3_channels;
bb8c093b 4594 *eeprom_ch_index = iwl3945_eeprom_band_3;
b481de9c 4595 break;
9fbab516 4596 case 4: /* 5.5GHz band */
bb8c093b 4597 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
b481de9c 4598 *eeprom_ch_info = priv->eeprom.band_4_channels;
bb8c093b 4599 *eeprom_ch_index = iwl3945_eeprom_band_4;
b481de9c 4600 break;
9fbab516 4601 case 5: /* 5.7GHz band */
bb8c093b 4602 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
b481de9c 4603 *eeprom_ch_info = priv->eeprom.band_5_channels;
bb8c093b 4604 *eeprom_ch_index = iwl3945_eeprom_band_5;
b481de9c
ZY		 4605 break;
4606 default:
4607 BUG();
4608 return;
4609 }
4610}
4611
6440adb5
CB		 4612/**
4613 * iwl3945_get_channel_info - Find driver's private channel info
4614 *
4615 * Based on band and channel number.
4616 */
bb8c093b 4617const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv,
8318d78a 4618 enum ieee80211_band band, u16 channel)
b481de9c
ZY		 4619{
4620 int i;
4621
8318d78a
JB		 4622 switch (band) {
4623 case IEEE80211_BAND_5GHZ:
b481de9c
ZY		 4624 for (i = 14; i < priv->channel_count; i++) {
4625 if (priv->channel_info[i].channel == channel)
4626 return &priv->channel_info[i];
4627 }
4628 break;
4629
8318d78a 4630 case IEEE80211_BAND_2GHZ:
b481de9c
ZY		 4631 if (channel >= 1 && channel <= 14)
4632 return &priv->channel_info[channel - 1];
4633 break;
8318d78a
JB		 4634 case IEEE80211_NUM_BANDS:
4635 WARN_ON(1);
b481de9c
ZY		 4636 }
4637
4638 return NULL;
4639}
4640
4641#define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
4642 ? # x " " : "")
4643
6440adb5
CB		 4644/**
4645 * iwl3945_init_channel_map - Set up driver's info for all possible channels
4646 */
bb8c093b 4647static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
b481de9c
ZY		 4648{
4649 int eeprom_ch_count = 0;
4650 const u8 *eeprom_ch_index = NULL;
bb8c093b 4651 const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL;
b481de9c 4652 int band, ch;
bb8c093b 4653 struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 4654
4655 if (priv->channel_count) {
4656 IWL_DEBUG_INFO("Channel map already initialized.\n");
4657 return 0;
4658 }
4659
4660 if (priv->eeprom.version < 0x2f) {
4661 IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
4662 priv->eeprom.version);
4663 return -EINVAL;
4664 }
4665
4666 IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
4667
4668 priv->channel_count =
bb8c093b
CH		 4669 ARRAY_SIZE(iwl3945_eeprom_band_1) +
4670 ARRAY_SIZE(iwl3945_eeprom_band_2) +
4671 ARRAY_SIZE(iwl3945_eeprom_band_3) +
4672 ARRAY_SIZE(iwl3945_eeprom_band_4) +
4673 ARRAY_SIZE(iwl3945_eeprom_band_5);
b481de9c
ZY		 4674
4675 IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
4676
bb8c093b 4677 priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) *
b481de9c
ZY		 4678 priv->channel_count, GFP_KERNEL);
4679 if (!priv->channel_info) {
4680 IWL_ERROR("Could not allocate channel_info\n");
4681 priv->channel_count = 0;
4682 return -ENOMEM;
4683 }
4684
4685 ch_info = priv->channel_info;
4686
4687 /* Loop through the 5 EEPROM bands adding them in order to the
4688 * channel map we maintain (that contains additional information than
4689 * what just in the EEPROM) */
4690 for (band = 1; band <= 5; band++) {
4691
bb8c093b 4692 iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
b481de9c
ZY		 4693 &eeprom_ch_info, &eeprom_ch_index);
4694
4695 /* Loop through each band adding each of the channels */
4696 for (ch = 0; ch < eeprom_ch_count; ch++) {
4697 ch_info->channel = eeprom_ch_index[ch];
8318d78a
JB		 4698 ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
4699 IEEE80211_BAND_5GHZ;
b481de9c
ZY		 4700
4701 /* permanently store EEPROM's channel regulatory flags
4702 * and max power in channel info database. */
4703 ch_info->eeprom = eeprom_ch_info[ch];
4704
4705 /* Copy the run-time flags so they are there even on
4706 * invalid channels */
4707 ch_info->flags = eeprom_ch_info[ch].flags;
4708
4709 if (!(is_channel_valid(ch_info))) {
4710 IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
4711 "No traffic\n",
4712 ch_info->channel,
4713 ch_info->flags,
4714 is_channel_a_band(ch_info) ?
4715 "5.2" : "2.4");
4716 ch_info++;
4717 continue;
4718 }
4719
4720 /* Initialize regulatory-based run-time data */
4721 ch_info->max_power_avg = ch_info->curr_txpow =
4722 eeprom_ch_info[ch].max_power_avg;
4723 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
4724 ch_info->min_power = 0;
4725
fe7c4040 4726 IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
b481de9c
ZY		 4727 " %ddBm): Ad-Hoc %ssupported\n",
4728 ch_info->channel,
4729 is_channel_a_band(ch_info) ?
4730 "5.2" : "2.4",
8211ef78 4731 CHECK_AND_PRINT(VALID),
b481de9c
ZY		 4732 CHECK_AND_PRINT(IBSS),
4733 CHECK_AND_PRINT(ACTIVE),
4734 CHECK_AND_PRINT(RADAR),
4735 CHECK_AND_PRINT(WIDE),
b481de9c
ZY		 4736 CHECK_AND_PRINT(DFS),
4737 eeprom_ch_info[ch].flags,
4738 eeprom_ch_info[ch].max_power_avg,
4739 ((eeprom_ch_info[ch].
4740 flags & EEPROM_CHANNEL_IBSS)
4741 && !(eeprom_ch_info[ch].
4742 flags & EEPROM_CHANNEL_RADAR))
4743 ? "" : "not ");
4744
4745 /* Set the user_txpower_limit to the highest power
4746 * supported by any channel */
4747 if (eeprom_ch_info[ch].max_power_avg >
4748 priv->user_txpower_limit)
4749 priv->user_txpower_limit =
4750 eeprom_ch_info[ch].max_power_avg;
4751
4752 ch_info++;
4753 }
4754 }
4755
6440adb5 4756 /* Set up txpower settings in driver for all channels */
b481de9c
ZY		 4757 if (iwl3945_txpower_set_from_eeprom(priv))
4758 return -EIO;
4759
4760 return 0;
4761}
4762
849e0dce
RC		 4763/*
4764 * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
4765 */
4766static void iwl3945_free_channel_map(struct iwl3945_priv *priv)
4767{
4768 kfree(priv->channel_info);
4769 priv->channel_count = 0;
4770}
4771
b481de9c
ZY		 4772/* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
4773 * sending probe req. This should be set long enough to hear probe responses
4774 * from more than one AP. */
f9340520
AK		 4775#define IWL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
4776#define IWL_ACTIVE_DWELL_TIME_52 (20)
4777
4778#define IWL_ACTIVE_DWELL_FACTOR_24GHZ (3)
4779#define IWL_ACTIVE_DWELL_FACTOR_52GHZ (2)
b481de9c
ZY		 4780
4781/* For faster active scanning, scan will move to the next channel if fewer than
4782 * PLCP_QUIET_THRESH packets are heard on this channel within
4783 * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
4784 * time if it's a quiet channel (nothing responded to our probe, and there's
4785 * no other traffic).
4786 * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
4787#define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
f9340520 4788#define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(10) /* msec */
b481de9c
ZY		 4789
4790/* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
4791 * Must be set longer than active dwell time.
4792 * For the most reliable scan, set > AP beacon interval (typically 100msec). */
4793#define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
4794#define IWL_PASSIVE_DWELL_TIME_52 (10)
4795#define IWL_PASSIVE_DWELL_BASE (100)
4796#define IWL_CHANNEL_TUNE_TIME 5
4797
f9340520
AK		 4798#define IWL_SCAN_PROBE_MASK(n) cpu_to_le32((BIT(n) | (BIT(n) - BIT(1))))
4799
8318d78a 4800static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv,
f9340520
AK		 4801 enum ieee80211_band band,
4802 u8 n_probes)
b481de9c 4803{
8318d78a 4804 if (band == IEEE80211_BAND_5GHZ)
f9340520
AK		 4805 return IWL_ACTIVE_DWELL_TIME_52 +
4806 IWL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
b481de9c 4807 else
f9340520
AK		 4808 return IWL_ACTIVE_DWELL_TIME_24 +
4809 IWL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
b481de9c
ZY		 4810}
4811
8318d78a
JB		 4812static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv,
4813 enum ieee80211_band band)
b481de9c 4814{
8318d78a 4815 u16 passive = (band == IEEE80211_BAND_2GHZ) ?
b481de9c
ZY		 4816 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
4817 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
4818
bb8c093b 4819 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 4820 /* If we're associated, we clamp the maximum passive
4821 * dwell time to be 98% of the beacon interval (minus
4822 * 2 * channel tune time) */
4823 passive = priv->beacon_int;
4824 if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
4825 passive = IWL_PASSIVE_DWELL_BASE;
4826 passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
4827 }
4828
b481de9c
ZY		 4829 return passive;
4830}
4831
8318d78a
JB		 4832static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv,
4833 enum ieee80211_band band,
f9340520 4834 u8 is_active, u8 n_probes,
bb8c093b 4835 struct iwl3945_scan_channel *scan_ch)
b481de9c
ZY		 4836{
4837 const struct ieee80211_channel *channels = NULL;
8318d78a 4838 const struct ieee80211_supported_band *sband;
bb8c093b 4839 const struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 4840 u16 passive_dwell = 0;
4841 u16 active_dwell = 0;
4842 int added, i;
4843
8318d78a
JB		 4844 sband = iwl3945_get_band(priv, band);
4845 if (!sband)
b481de9c
ZY		 4846 return 0;
4847
8318d78a 4848 channels = sband->channels;
b481de9c 4849
f9340520 4850 active_dwell = iwl3945_get_active_dwell_time(priv, band, n_probes);
8318d78a 4851 passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
b481de9c 4852
8f4807a1
AK		 4853 if (passive_dwell <= active_dwell)
4854 passive_dwell = active_dwell + 1;
4855
8318d78a 4856 for (i = 0, added = 0; i < sband->n_channels; i++) {
182e2e66
JB		 4857 if (channels[i].flags & IEEE80211_CHAN_DISABLED)
4858 continue;
4859
8318d78a 4860 scan_ch->channel = channels[i].hw_value;
b481de9c 4861
8318d78a 4862 ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
b481de9c 4863 if (!is_channel_valid(ch_info)) {
66b5004d 4864 IWL_DEBUG_SCAN("Channel %d is INVALID for this band.\n",
b481de9c
ZY		 4865 scan_ch->channel);
4866 continue;
4867 }
4868
4869 if (!is_active || is_channel_passive(ch_info) ||
8318d78a 4870 (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN))
b481de9c
ZY		 4871 scan_ch->type = 0; /* passive */
4872 else
4873 scan_ch->type = 1; /* active */
4874
f9340520
AK		 4875 if ((scan_ch->type & 1) && n_probes)
4876 scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
b481de9c 4877
b481de9c
ZY		 4878 scan_ch->active_dwell = cpu_to_le16(active_dwell);
4879 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
4880
9fbab516 4881 /* Set txpower levels to defaults */
b481de9c
ZY		 4882 scan_ch->tpc.dsp_atten = 110;
4883 /* scan_pwr_info->tpc.dsp_atten; */
4884
4885 /*scan_pwr_info->tpc.tx_gain; */
8318d78a 4886 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 4887 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
4888 else {
4889 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
4890 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
9fbab516 4891 * power level:
8a1b0245 4892 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
b481de9c
ZY		 4893 */
4894 }
4895
4896 IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
4897 scan_ch->channel,
4898 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
4899 (scan_ch->type & 1) ?
4900 active_dwell : passive_dwell);
4901
4902 scan_ch++;
4903 added++;
4904 }
4905
4906 IWL_DEBUG_SCAN("total channels to scan %d \n", added);
4907 return added;
4908}
4909
bb8c093b 4910static void iwl3945_init_hw_rates(struct iwl3945_priv *priv,
b481de9c
ZY		 4911 struct ieee80211_rate *rates)
4912{
4913 int i;
4914
4915 for (i = 0; i < IWL_RATE_COUNT; i++) {
8318d78a
JB		 4916 rates[i].bitrate = iwl3945_rates[i].ieee * 5;
4917 rates[i].hw_value = i; /* Rate scaling will work on indexes */
4918 rates[i].hw_value_short = i;
4919 rates[i].flags = 0;
4920 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
b481de9c 4921 /*
8318d78a 4922 * If CCK != 1M then set short preamble rate flag.
b481de9c 4923 */
bb8c093b 4924 rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
8318d78a 4925 0 : IEEE80211_RATE_SHORT_PREAMBLE;
b481de9c 4926 }
b481de9c
ZY		 4927 }
4928}
4929
4930/**
bb8c093b 4931 * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
b481de9c 4932 */
bb8c093b 4933static int iwl3945_init_geos(struct iwl3945_priv *priv)
b481de9c 4934{
bb8c093b 4935 struct iwl3945_channel_info *ch;
8211ef78 4936 struct ieee80211_supported_band *sband;
b481de9c
ZY		 4937 struct ieee80211_channel *channels;
4938 struct ieee80211_channel *geo_ch;
4939 struct ieee80211_rate *rates;
4940 int i = 0;
b481de9c 4941
8318d78a
JB		 4942 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
4943 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
b481de9c
ZY		 4944 IWL_DEBUG_INFO("Geography modes already initialized.\n");
4945 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
4946 return 0;
4947 }
4948
b481de9c
ZY		 4949 channels = kzalloc(sizeof(struct ieee80211_channel) *
4950 priv->channel_count, GFP_KERNEL);
8318d78a 4951 if (!channels)
b481de9c 4952 return -ENOMEM;
b481de9c 4953
8211ef78 4954 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
b481de9c
ZY		 4955 GFP_KERNEL);
4956 if (!rates) {
b481de9c
ZY		 4957 kfree(channels);
4958 return -ENOMEM;
4959 }
4960
b481de9c 4961 /* 5.2GHz channels start after the 2.4GHz channels */
8211ef78
TW		 4962 sband = &priv->bands[IEEE80211_BAND_5GHZ];
4963 sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
4964 /* just OFDM */
4965 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
4966 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
4967
4968 sband = &priv->bands[IEEE80211_BAND_2GHZ];
4969 sband->channels = channels;
4970 /* OFDM & CCK */
4971 sband->bitrates = rates;
4972 sband->n_bitrates = IWL_RATE_COUNT;
b481de9c
ZY		 4973
4974 priv->ieee_channels = channels;
4975 priv->ieee_rates = rates;
4976
bb8c093b 4977 iwl3945_init_hw_rates(priv, rates);
b481de9c 4978
8211ef78 4979 for (i = 0; i < priv->channel_count; i++) {
b481de9c
ZY		 4980 ch = &priv->channel_info[i];
4981
8211ef78
TW		 4982 /* FIXME: might be removed if scan is OK*/
4983 if (!is_channel_valid(ch))
b481de9c 4984 continue;
b481de9c
ZY		 4985
4986 if (is_channel_a_band(ch))
8211ef78 4987 sband = &priv->bands[IEEE80211_BAND_5GHZ];
8318d78a 4988 else
8211ef78 4989 sband = &priv->bands[IEEE80211_BAND_2GHZ];
b481de9c 4990
8211ef78
TW		 4991 geo_ch = &sband->channels[sband->n_channels++];
4992
4993 geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
8318d78a
JB		 4994 geo_ch->max_power = ch->max_power_avg;
4995 geo_ch->max_antenna_gain = 0xff;
7b72304d 4996 geo_ch->hw_value = ch->channel;
b481de9c
ZY		 4997
4998 if (is_channel_valid(ch)) {
8318d78a
JB		 4999 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
5000 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
b481de9c 5001
8318d78a
JB		 5002 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
5003 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
b481de9c
ZY		 5004
5005 if (ch->flags & EEPROM_CHANNEL_RADAR)
8318d78a 5006 geo_ch->flags |= IEEE80211_CHAN_RADAR;
b481de9c
ZY		 5007
5008 if (ch->max_power_avg > priv->max_channel_txpower_limit)
5009 priv->max_channel_txpower_limit =
5010 ch->max_power_avg;
8211ef78 5011 } else {
8318d78a 5012 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
8211ef78
TW		 5013 }
5014
5015 /* Save flags for reg domain usage */
5016 geo_ch->orig_flags = geo_ch->flags;
5017
5018 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
5019 ch->channel, geo_ch->center_freq,
5020 is_channel_a_band(ch) ? "5.2" : "2.4",
5021 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
5022 "restricted" : "valid",
5023 geo_ch->flags);
b481de9c
ZY		 5024 }
5025
82b9a121
TW		 5026 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
5027 priv->cfg->sku & IWL_SKU_A) {
b481de9c
ZY		 5028 printk(KERN_INFO DRV_NAME
5029 ": Incorrectly detected BG card as ABG. Please send "
5030 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
5031 priv->pci_dev->device, priv->pci_dev->subsystem_device);
82b9a121 5032 priv->cfg->sku &= ~IWL_SKU_A;
b481de9c
ZY		 5033 }
5034
5035 printk(KERN_INFO DRV_NAME
5036 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
8318d78a
JB		 5037 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
5038 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
b481de9c 5039
e0e0a67e
JL		 5040 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
5041 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
5042 &priv->bands[IEEE80211_BAND_2GHZ];
5043 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
5044 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
5045 &priv->bands[IEEE80211_BAND_5GHZ];
b481de9c 5046
b481de9c
ZY		 5047 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
5048
5049 return 0;
5050}
5051
849e0dce
RC		 5052/*
5053 * iwl3945_free_geos - undo allocations in iwl3945_init_geos
5054 */
5055static void iwl3945_free_geos(struct iwl3945_priv *priv)
5056{
849e0dce
RC		 5057 kfree(priv->ieee_channels);
5058 kfree(priv->ieee_rates);
5059 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
5060}
5061
b481de9c
ZY		 5062/******************************************************************************
5063 *
5064 * uCode download functions
5065 *
5066 ******************************************************************************/
5067
bb8c093b 5068static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv)
b481de9c 5069{
98c92211
TW		 5070 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
5071 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
5072 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
5073 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
5074 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
5075 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY		 5076}
5077
5078/**
bb8c093b 5079 * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
b481de9c
ZY		 5080 * looking at all data.
5081 */
3ac7f146 5082static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 *image, u32 len)
b481de9c
ZY		 5083{
5084 u32 val;
5085 u32 save_len = len;
5086 int rc = 0;
5087 u32 errcnt;
5088
5089 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5090
bb8c093b 5091 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5092 if (rc)
5093 return rc;
5094
bb8c093b 5095 iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
b481de9c
ZY		 5096
5097 errcnt = 0;
5098 for (; len > 0; len -= sizeof(u32), image++) {
5099 /* read data comes through single port, auto-incr addr */
5100 /* NOTE: Use the debugless read so we don't flood kernel log
5101 * if IWL_DL_IO is set */
bb8c093b 5102 val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY		 5103 if (val != le32_to_cpu(*image)) {
5104 IWL_ERROR("uCode INST section is invalid at "
5105 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5106 save_len - len, val, le32_to_cpu(*image));
5107 rc = -EIO;
5108 errcnt++;
5109 if (errcnt >= 20)
5110 break;
5111 }
5112 }
5113
bb8c093b 5114 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5115
5116 if (!errcnt)
bc434dd2 5117 IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
b481de9c
ZY		 5118
5119 return rc;
5120}
5121
5122
5123/**
bb8c093b 5124 * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
b481de9c
ZY		 5125 * using sample data 100 bytes apart. If these sample points are good,
5126 * it's a pretty good bet that everything between them is good, too.
5127 */
bb8c093b 5128static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len)
b481de9c
ZY		 5129{
5130 u32 val;
5131 int rc = 0;
5132 u32 errcnt = 0;
5133 u32 i;
5134
5135 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5136
bb8c093b 5137 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5138 if (rc)
5139 return rc;
5140
5141 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
5142 /* read data comes through single port, auto-incr addr */
5143 /* NOTE: Use the debugless read so we don't flood kernel log
5144 * if IWL_DL_IO is set */
bb8c093b 5145 iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
b481de9c 5146 i + RTC_INST_LOWER_BOUND);
bb8c093b 5147 val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY		 5148 if (val != le32_to_cpu(*image)) {
5149#if 0 /* Enable this if you want to see details */
5150 IWL_ERROR("uCode INST section is invalid at "
5151 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5152 i, val, *image);
5153#endif
5154 rc = -EIO;
5155 errcnt++;
5156 if (errcnt >= 3)
5157 break;
5158 }
5159 }
5160
bb8c093b 5161 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5162
5163 return rc;
5164}
5165
5166
5167/**
bb8c093b 5168 * iwl3945_verify_ucode - determine which instruction image is in SRAM,
b481de9c
ZY		 5169 * and verify its contents
5170 */
bb8c093b 5171static int iwl3945_verify_ucode(struct iwl3945_priv *priv)
b481de9c
ZY		 5172{
5173 __le32 *image;
5174 u32 len;
5175 int rc = 0;
5176
5177 /* Try bootstrap */
5178 image = (__le32 *)priv->ucode_boot.v_addr;
5179 len = priv->ucode_boot.len;
bb8c093b 5180 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5181 if (rc == 0) {
5182 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
5183 return 0;
5184 }
5185
5186 /* Try initialize */
5187 image = (__le32 *)priv->ucode_init.v_addr;
5188 len = priv->ucode_init.len;
bb8c093b 5189 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5190 if (rc == 0) {
5191 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
5192 return 0;
5193 }
5194
5195 /* Try runtime/protocol */
5196 image = (__le32 *)priv->ucode_code.v_addr;
5197 len = priv->ucode_code.len;
bb8c093b 5198 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5199 if (rc == 0) {
5200 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
5201 return 0;
5202 }
5203
5204 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
5205
9fbab516
BC		 5206 /* Since nothing seems to match, show first several data entries in
5207 * instruction SRAM, so maybe visual inspection will give a clue.
5208 * Selection of bootstrap image (vs. other images) is arbitrary. */
b481de9c
ZY		 5209 image = (__le32 *)priv->ucode_boot.v_addr;
5210 len = priv->ucode_boot.len;
bb8c093b 5211 rc = iwl3945_verify_inst_full(priv, image, len);
b481de9c
ZY		 5212
5213 return rc;
5214}
5215
5216
5217/* check contents of special bootstrap uCode SRAM */
bb8c093b 5218static int iwl3945_verify_bsm(struct iwl3945_priv *priv)
b481de9c
ZY		 5219{
5220 __le32 *image = priv->ucode_boot.v_addr;
5221 u32 len = priv->ucode_boot.len;
5222 u32 reg;
5223 u32 val;
5224
5225 IWL_DEBUG_INFO("Begin verify bsm\n");
5226
5227 /* verify BSM SRAM contents */
bb8c093b 5228 val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG);
b481de9c
ZY		 5229 for (reg = BSM_SRAM_LOWER_BOUND;
5230 reg < BSM_SRAM_LOWER_BOUND + len;
3ac7f146 5231 reg += sizeof(u32), image++) {
bb8c093b 5232 val = iwl3945_read_prph(priv, reg);
b481de9c
ZY		 5233 if (val != le32_to_cpu(*image)) {
5234 IWL_ERROR("BSM uCode verification failed at "
5235 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
5236 BSM_SRAM_LOWER_BOUND,
5237 reg - BSM_SRAM_LOWER_BOUND, len,
5238 val, le32_to_cpu(*image));
5239 return -EIO;
5240 }
5241 }
5242
5243 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
5244
5245 return 0;
5246}
5247
5248/**
bb8c093b 5249 * iwl3945_load_bsm - Load bootstrap instructions
b481de9c
ZY		 5250 *
5251 * BSM operation:
5252 *
5253 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
5254 * in special SRAM that does not power down during RFKILL. When powering back
5255 * up after power-saving sleeps (or during initial uCode load), the BSM loads
5256 * the bootstrap program into the on-board processor, and starts it.
5257 *
5258 * The bootstrap program loads (via DMA) instructions and data for a new
5259 * program from host DRAM locations indicated by the host driver in the
5260 * BSM_DRAM_* registers. Once the new program is loaded, it starts
5261 * automatically.
5262 *
5263 * When initializing the NIC, the host driver points the BSM to the
5264 * "initialize" uCode image. This uCode sets up some internal data, then
5265 * notifies host via "initialize alive" that it is complete.
5266 *
5267 * The host then replaces the BSM_DRAM_* pointer values to point to the
5268 * normal runtime uCode instructions and a backup uCode data cache buffer
5269 * (filled initially with starting data values for the on-board processor),
5270 * then triggers the "initialize" uCode to load and launch the runtime uCode,
5271 * which begins normal operation.
5272 *
5273 * When doing a power-save shutdown, runtime uCode saves data SRAM into
5274 * the backup data cache in DRAM before SRAM is powered down.
5275 *
5276 * When powering back up, the BSM loads the bootstrap program. This reloads
5277 * the runtime uCode instructions and the backup data cache into SRAM,
5278 * and re-launches the runtime uCode from where it left off.
5279 */
bb8c093b 5280static int iwl3945_load_bsm(struct iwl3945_priv *priv)
b481de9c
ZY		 5281{
5282 __le32 *image = priv->ucode_boot.v_addr;
5283 u32 len = priv->ucode_boot.len;
5284 dma_addr_t pinst;
5285 dma_addr_t pdata;
5286 u32 inst_len;
5287 u32 data_len;
5288 int rc;
5289 int i;
5290 u32 done;
5291 u32 reg_offset;
5292
5293 IWL_DEBUG_INFO("Begin load bsm\n");
5294
5295 /* make sure bootstrap program is no larger than BSM's SRAM size */
5296 if (len > IWL_MAX_BSM_SIZE)
5297 return -EINVAL;
5298
5299 /* Tell bootstrap uCode where to find the "Initialize" uCode
9fbab516 5300 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
bb8c093b 5301 * NOTE: iwl3945_initialize_alive_start() will replace these values,
b481de9c
ZY		 5302 * after the "initialize" uCode has run, to point to
5303 * runtime/protocol instructions and backup data cache. */
5304 pinst = priv->ucode_init.p_addr;
5305 pdata = priv->ucode_init_data.p_addr;
5306 inst_len = priv->ucode_init.len;
5307 data_len = priv->ucode_init_data.len;
5308
bb8c093b 5309 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5310 if (rc)
5311 return rc;
5312
bb8c093b
CH		 5313 iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5314 iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5315 iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
5316 iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
b481de9c
ZY		 5317
5318 /* Fill BSM memory with bootstrap instructions */
5319 for (reg_offset = BSM_SRAM_LOWER_BOUND;
5320 reg_offset < BSM_SRAM_LOWER_BOUND + len;
5321 reg_offset += sizeof(u32), image++)
bb8c093b 5322 _iwl3945_write_prph(priv, reg_offset,
b481de9c
ZY		 5323 le32_to_cpu(*image));
5324
bb8c093b 5325 rc = iwl3945_verify_bsm(priv);
b481de9c 5326 if (rc) {
bb8c093b 5327 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5328 return rc;
5329 }
5330
5331 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
bb8c093b
CH		 5332 iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
5333 iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG,
b481de9c 5334 RTC_INST_LOWER_BOUND);
bb8c093b 5335 iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
b481de9c
ZY		 5336
5337 /* Load bootstrap code into instruction SRAM now,
5338 * to prepare to load "initialize" uCode */
bb8c093b 5339 iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY		 5340 BSM_WR_CTRL_REG_BIT_START);
5341
5342 /* Wait for load of bootstrap uCode to finish */
5343 for (i = 0; i < 100; i++) {
bb8c093b 5344 done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG);
b481de9c
ZY		 5345 if (!(done & BSM_WR_CTRL_REG_BIT_START))
5346 break;
5347 udelay(10);
5348 }
5349 if (i < 100)
5350 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
5351 else {
5352 IWL_ERROR("BSM write did not complete!\n");
5353 return -EIO;
5354 }
5355
5356 /* Enable future boot loads whenever power management unit triggers it
5357 * (e.g. when powering back up after power-save shutdown) */
bb8c093b 5358 iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY		 5359 BSM_WR_CTRL_REG_BIT_START_EN);
5360
bb8c093b 5361 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5362
5363 return 0;
5364}
5365
bb8c093b 5366static void iwl3945_nic_start(struct iwl3945_priv *priv)
b481de9c
ZY		 5367{
5368 /* Remove all resets to allow NIC to operate */
bb8c093b 5369 iwl3945_write32(priv, CSR_RESET, 0);
b481de9c
ZY		 5370}
5371
5372/**
bb8c093b 5373 * iwl3945_read_ucode - Read uCode images from disk file.
b481de9c
ZY		 5374 *
5375 * Copy into buffers for card to fetch via bus-mastering
5376 */
bb8c093b 5377static int iwl3945_read_ucode(struct iwl3945_priv *priv)
b481de9c 5378{
bb8c093b 5379 struct iwl3945_ucode *ucode;
90e759d1 5380 int ret = 0;
b481de9c
ZY		 5381 const struct firmware *ucode_raw;
5382 /* firmware file name contains uCode/driver compatibility version */
4bf775cd 5383 const char *name = priv->cfg->fw_name;
b481de9c
ZY		 5384 u8 *src;
5385 size_t len;
5386 u32 ver, inst_size, data_size, init_size, init_data_size, boot_size;
5387
5388 /* Ask kernel firmware_class module to get the boot firmware off disk.
5389 * request_firmware() is synchronous, file is in memory on return. */
90e759d1
TW		 5390 ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev);
5391 if (ret < 0) {
5392 IWL_ERROR("%s firmware file req failed: Reason %d\n",
5393 name, ret);
b481de9c
ZY		 5394 goto error;
5395 }
5396
5397 IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
5398 name, ucode_raw->size);
5399
5400 /* Make sure that we got at least our header! */
5401 if (ucode_raw->size < sizeof(*ucode)) {
5402 IWL_ERROR("File size way too small!\n");
90e759d1 5403 ret = -EINVAL;
b481de9c
ZY		 5404 goto err_release;
5405 }
5406
5407 /* Data from ucode file: header followed by uCode images */
5408 ucode = (void *)ucode_raw->data;
5409
5410 ver = le32_to_cpu(ucode->ver);
5411 inst_size = le32_to_cpu(ucode->inst_size);
5412 data_size = le32_to_cpu(ucode->data_size);
5413 init_size = le32_to_cpu(ucode->init_size);
5414 init_data_size = le32_to_cpu(ucode->init_data_size);
5415 boot_size = le32_to_cpu(ucode->boot_size);
5416
5417 IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver);
bc434dd2
IS		 5418 IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
5419 IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
5420 IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
5421 IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
5422 IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
b481de9c
ZY		 5423
5424 /* Verify size of file vs. image size info in file's header */
5425 if (ucode_raw->size < sizeof(*ucode) +
5426 inst_size + data_size + init_size +
5427 init_data_size + boot_size) {
5428
5429 IWL_DEBUG_INFO("uCode file size %d too small\n",
5430 (int)ucode_raw->size);
90e759d1 5431 ret = -EINVAL;
b481de9c
ZY		 5432 goto err_release;
5433 }
5434
5435 /* Verify that uCode images will fit in card's SRAM */
5436 if (inst_size > IWL_MAX_INST_SIZE) {
90e759d1
TW		 5437 IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
5438 inst_size);
5439 ret = -EINVAL;
b481de9c
ZY		 5440 goto err_release;
5441 }
5442
5443 if (data_size > IWL_MAX_DATA_SIZE) {
90e759d1
TW		 5444 IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
5445 data_size);
5446 ret = -EINVAL;
b481de9c
ZY		 5447 goto err_release;
5448 }
5449 if (init_size > IWL_MAX_INST_SIZE) {
90e759d1
TW		 5450 IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
5451 init_size);
5452 ret = -EINVAL;
b481de9c
ZY		 5453 goto err_release;
5454 }
5455 if (init_data_size > IWL_MAX_DATA_SIZE) {
90e759d1
TW		 5456 IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
5457 init_data_size);
5458 ret = -EINVAL;
b481de9c
ZY		 5459 goto err_release;
5460 }
5461 if (boot_size > IWL_MAX_BSM_SIZE) {
90e759d1
TW		 5462 IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
5463 boot_size);
5464 ret = -EINVAL;
b481de9c
ZY		 5465 goto err_release;
5466 }
5467
5468 /* Allocate ucode buffers for card's bus-master loading ... */
5469
5470 /* Runtime instructions and 2 copies of data:
5471 * 1) unmodified from disk
5472 * 2) backup cache for save/restore during power-downs */
5473 priv->ucode_code.len = inst_size;
98c92211 5474 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY		 5475
5476 priv->ucode_data.len = data_size;
98c92211 5477 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY		 5478
5479 priv->ucode_data_backup.len = data_size;
98c92211 5480 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 5481
90e759d1
TW		 5482 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
5483 !priv->ucode_data_backup.v_addr)
5484 goto err_pci_alloc;
b481de9c
ZY		 5485
5486 /* Initialization instructions and data */
90e759d1
TW		 5487 if (init_size && init_data_size) {
5488 priv->ucode_init.len = init_size;
98c92211 5489 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW		 5490
5491 priv->ucode_init_data.len = init_data_size;
98c92211 5492 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW		 5493
5494 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
5495 goto err_pci_alloc;
5496 }
b481de9c
ZY		 5497
5498 /* Bootstrap (instructions only, no data) */
90e759d1
TW		 5499 if (boot_size) {
5500 priv->ucode_boot.len = boot_size;
98c92211 5501 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 5502
90e759d1
TW		 5503 if (!priv->ucode_boot.v_addr)
5504 goto err_pci_alloc;
5505 }
b481de9c
ZY		 5506
5507 /* Copy images into buffers for card's bus-master reads ... */
5508
5509 /* Runtime instructions (first block of data in file) */
5510 src = &ucode->data[0];
5511 len = priv->ucode_code.len;
90e759d1 5512 IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c
ZY		 5513 memcpy(priv->ucode_code.v_addr, src, len);
5514 IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
5515 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
5516
5517 /* Runtime data (2nd block)
bb8c093b 5518 * NOTE: Copy into backup buffer will be done in iwl3945_up() */
b481de9c
ZY		 5519 src = &ucode->data[inst_size];
5520 len = priv->ucode_data.len;
90e759d1 5521 IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY		 5522 memcpy(priv->ucode_data.v_addr, src, len);
5523 memcpy(priv->ucode_data_backup.v_addr, src, len);
5524
5525 /* Initialization instructions (3rd block) */
5526 if (init_size) {
5527 src = &ucode->data[inst_size + data_size];
5528 len = priv->ucode_init.len;
90e759d1
TW		 5529 IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
5530 len);
b481de9c
ZY		 5531 memcpy(priv->ucode_init.v_addr, src, len);
5532 }
5533
5534 /* Initialization data (4th block) */
5535 if (init_data_size) {
5536 src = &ucode->data[inst_size + data_size + init_size];
5537 len = priv->ucode_init_data.len;
5538 IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
5539 (int)len);
5540 memcpy(priv->ucode_init_data.v_addr, src, len);
5541 }
5542
5543 /* Bootstrap instructions (5th block) */
5544 src = &ucode->data[inst_size + data_size + init_size + init_data_size];
5545 len = priv->ucode_boot.len;
5546 IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
5547 (int)len);
5548 memcpy(priv->ucode_boot.v_addr, src, len);
5549
5550 /* We have our copies now, allow OS release its copies */
5551 release_firmware(ucode_raw);
5552 return 0;
5553
5554 err_pci_alloc:
5555 IWL_ERROR("failed to allocate pci memory\n");
90e759d1 5556 ret = -ENOMEM;
bb8c093b 5557 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY		 5558
5559 err_release:
5560 release_firmware(ucode_raw);
5561
5562 error:
90e759d1 5563 return ret;
b481de9c
ZY		 5564}
5565
5566
5567/**
bb8c093b 5568 * iwl3945_set_ucode_ptrs - Set uCode address location
b481de9c
ZY		 5569 *
5570 * Tell initialization uCode where to find runtime uCode.
5571 *
5572 * BSM registers initially contain pointers to initialization uCode.
5573 * We need to replace them to load runtime uCode inst and data,
5574 * and to save runtime data when powering down.
5575 */
bb8c093b 5576static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv)
b481de9c
ZY		 5577{
5578 dma_addr_t pinst;
5579 dma_addr_t pdata;
5580 int rc = 0;
5581 unsigned long flags;
5582
5583 /* bits 31:0 for 3945 */
5584 pinst = priv->ucode_code.p_addr;
5585 pdata = priv->ucode_data_backup.p_addr;
5586
5587 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5588 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5589 if (rc) {
5590 spin_unlock_irqrestore(&priv->lock, flags);
5591 return rc;
5592 }
5593
5594 /* Tell bootstrap uCode where to find image to load */
bb8c093b
CH		 5595 iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5596 iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5597 iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
b481de9c
ZY		 5598 priv->ucode_data.len);
5599
5600 /* Inst bytecount must be last to set up, bit 31 signals uCode
5601 * that all new ptr/size info is in place */
bb8c093b 5602 iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
b481de9c
ZY		 5603 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
5604
bb8c093b 5605 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5606
5607 spin_unlock_irqrestore(&priv->lock, flags);
5608
5609 IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
5610
5611 return rc;
5612}
5613
5614/**
bb8c093b 5615 * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
b481de9c
ZY		 5616 *
5617 * Called after REPLY_ALIVE notification received from "initialize" uCode.
5618 *
b481de9c 5619 * Tell "initialize" uCode to go ahead and load the runtime uCode.
9fbab516 5620 */
bb8c093b 5621static void iwl3945_init_alive_start(struct iwl3945_priv *priv)
b481de9c
ZY		 5622{
5623 /* Check alive response for "valid" sign from uCode */
5624 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
5625 /* We had an error bringing up the hardware, so take it
5626 * all the way back down so we can try again */
5627 IWL_DEBUG_INFO("Initialize Alive failed.\n");
5628 goto restart;
5629 }
5630
5631 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
5632 * This is a paranoid check, because we would not have gotten the
5633 * "initialize" alive if code weren't properly loaded. */
bb8c093b 5634 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY		 5635 /* Runtime instruction load was bad;
5636 * take it all the way back down so we can try again */
5637 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
5638 goto restart;
5639 }
5640
5641 /* Send pointers to protocol/runtime uCode image ... init code will
5642 * load and launch runtime uCode, which will send us another "Alive"
5643 * notification. */
5644 IWL_DEBUG_INFO("Initialization Alive received.\n");
bb8c093b 5645 if (iwl3945_set_ucode_ptrs(priv)) {
b481de9c
ZY		 5646 /* Runtime instruction load won't happen;
5647 * take it all the way back down so we can try again */
5648 IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
5649 goto restart;
5650 }
5651 return;
5652
5653 restart:
5654 queue_work(priv->workqueue, &priv->restart);
5655}
5656
5657
5658/**
bb8c093b 5659 * iwl3945_alive_start - called after REPLY_ALIVE notification received
b481de9c 5660 * from protocol/runtime uCode (initialization uCode's
bb8c093b 5661 * Alive gets handled by iwl3945_init_alive_start()).
b481de9c 5662 */
bb8c093b 5663static void iwl3945_alive_start(struct iwl3945_priv *priv)
b481de9c
ZY		 5664{
5665 int rc = 0;
5666 int thermal_spin = 0;
5667 u32 rfkill;
5668
5669 IWL_DEBUG_INFO("Runtime Alive received.\n");
5670
5671 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
5672 /* We had an error bringing up the hardware, so take it
5673 * all the way back down so we can try again */
5674 IWL_DEBUG_INFO("Alive failed.\n");
5675 goto restart;
5676 }
5677
5678 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
5679 * This is a paranoid check, because we would not have gotten the
5680 * "runtime" alive if code weren't properly loaded. */
bb8c093b 5681 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY		 5682 /* Runtime instruction load was bad;
5683 * take it all the way back down so we can try again */
5684 IWL_DEBUG_INFO("Bad runtime uCode load.\n");
5685 goto restart;
5686 }
5687
bb8c093b 5688 iwl3945_clear_stations_table(priv);
b481de9c 5689
bb8c093b 5690 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5691 if (rc) {
5692 IWL_WARNING("Can not read rfkill status from adapter\n");
5693 return;
5694 }
5695
bb8c093b 5696 rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG);
b481de9c 5697 IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
bb8c093b 5698 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5699
5700 if (rfkill & 0x1) {
5701 clear_bit(STATUS_RF_KILL_HW, &priv->status);
5702 /* if rfkill is not on, then wait for thermal
5703 * sensor in adapter to kick in */
bb8c093b 5704 while (iwl3945_hw_get_temperature(priv) == 0) {
b481de9c
ZY		 5705 thermal_spin++;
5706 udelay(10);
5707 }
5708
5709 if (thermal_spin)
5710 IWL_DEBUG_INFO("Thermal calibration took %dus\n",
5711 thermal_spin * 10);
5712 } else
5713 set_bit(STATUS_RF_KILL_HW, &priv->status);
5714
9fbab516 5715 /* After the ALIVE response, we can send commands to 3945 uCode */
b481de9c
ZY		 5716 set_bit(STATUS_ALIVE, &priv->status);
5717
5718 /* Clear out the uCode error bit if it is set */
5719 clear_bit(STATUS_FW_ERROR, &priv->status);
5720
bb8c093b 5721 if (iwl3945_is_rfkill(priv))
b481de9c
ZY		 5722 return;
5723
36d6825b 5724 ieee80211_wake_queues(priv->hw);
b481de9c
ZY		 5725
5726 priv->active_rate = priv->rates_mask;
5727 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
5728
bb8c093b 5729 iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
b481de9c 5730
bb8c093b
CH		 5731 if (iwl3945_is_associated(priv)) {
5732 struct iwl3945_rxon_cmd *active_rxon =
5733 (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
b481de9c
ZY		 5734
5735 memcpy(&priv->staging_rxon, &priv->active_rxon,
5736 sizeof(priv->staging_rxon));
5737 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5738 } else {
5739 /* Initialize our rx_config data */
bb8c093b 5740 iwl3945_connection_init_rx_config(priv);
b481de9c
ZY		 5741 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
5742 }
5743
9fbab516 5744 /* Configure Bluetooth device coexistence support */
bb8c093b 5745 iwl3945_send_bt_config(priv);
b481de9c
ZY		 5746
5747 /* Configure the adapter for unassociated operation */
bb8c093b 5748 iwl3945_commit_rxon(priv);
b481de9c 5749
b481de9c
ZY		 5750 iwl3945_reg_txpower_periodic(priv);
5751
fe00b5a5
RC		 5752 iwl3945_led_register(priv);
5753
b481de9c 5754 IWL_DEBUG_INFO("ALIVE processing complete.\n");
a9f46786 5755 set_bit(STATUS_READY, &priv->status);
5a66926a 5756 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY		 5757
5758 if (priv->error_recovering)
bb8c093b 5759 iwl3945_error_recovery(priv);
b481de9c 5760
84363e6e 5761 ieee80211_notify_mac(priv->hw, IEEE80211_NOTIFY_RE_ASSOC);
b481de9c
ZY		 5762 return;
5763
5764 restart:
5765 queue_work(priv->workqueue, &priv->restart);
5766}
5767
bb8c093b 5768static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv);
b481de9c 5769
bb8c093b 5770static void __iwl3945_down(struct iwl3945_priv *priv)
b481de9c
ZY		 5771{
5772 unsigned long flags;
5773 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
5774 struct ieee80211_conf *conf = NULL;
5775
5776 IWL_DEBUG_INFO(DRV_NAME " is going down\n");
5777
5778 conf = ieee80211_get_hw_conf(priv->hw);
5779
5780 if (!exit_pending)
5781 set_bit(STATUS_EXIT_PENDING, &priv->status);
5782
ab53d8af 5783 iwl3945_led_unregister(priv);
bb8c093b 5784 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 5785
5786 /* Unblock any waiting calls */
5787 wake_up_interruptible_all(&priv->wait_command_queue);
5788
b481de9c
ZY		 5789 /* Wipe out the EXIT_PENDING status bit if we are not actually
5790 * exiting the module */
5791 if (!exit_pending)
5792 clear_bit(STATUS_EXIT_PENDING, &priv->status);
5793
5794 /* stop and reset the on-board processor */
bb8c093b 5795 iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY		 5796
5797 /* tell the device to stop sending interrupts */
0359facc 5798 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5799 iwl3945_disable_interrupts(priv);
0359facc
MA		 5800 spin_unlock_irqrestore(&priv->lock, flags);
5801 iwl_synchronize_irq(priv);
b481de9c
ZY		 5802
5803 if (priv->mac80211_registered)
5804 ieee80211_stop_queues(priv->hw);
5805
bb8c093b 5806 /* If we have not previously called iwl3945_init() then
b481de9c 5807 * clear all bits but the RF Kill and SUSPEND bits and return */
bb8c093b 5808 if (!iwl3945_is_init(priv)) {
b481de9c
ZY		 5809 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
5810 STATUS_RF_KILL_HW |
5811 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
5812 STATUS_RF_KILL_SW |
9788864e
RC		 5813 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
5814 STATUS_GEO_CONFIGURED |
b481de9c 5815 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
ebef2008
AK		 5816 STATUS_IN_SUSPEND |
5817 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
5818 STATUS_EXIT_PENDING;
b481de9c
ZY		 5819 goto exit;
5820 }
5821
5822 /* ...otherwise clear out all the status bits but the RF Kill and
5823 * SUSPEND bits and continue taking the NIC down. */
5824 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
5825 STATUS_RF_KILL_HW |
5826 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
5827 STATUS_RF_KILL_SW |
9788864e
RC		 5828 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
5829 STATUS_GEO_CONFIGURED |
b481de9c
ZY		 5830 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
5831 STATUS_IN_SUSPEND |
5832 test_bit(STATUS_FW_ERROR, &priv->status) <<
ebef2008
AK		 5833 STATUS_FW_ERROR |
5834 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
5835 STATUS_EXIT_PENDING;
b481de9c
ZY		 5836
5837 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5838 iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY		 5839 spin_unlock_irqrestore(&priv->lock, flags);
5840
bb8c093b
CH		 5841 iwl3945_hw_txq_ctx_stop(priv);
5842 iwl3945_hw_rxq_stop(priv);
b481de9c
ZY		 5843
5844 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH		 5845 if (!iwl3945_grab_nic_access(priv)) {
5846 iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
b481de9c 5847 APMG_CLK_VAL_DMA_CLK_RQT);
bb8c093b 5848 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5849 }
5850 spin_unlock_irqrestore(&priv->lock, flags);
5851
5852 udelay(5);
5853
bb8c093b
CH		 5854 iwl3945_hw_nic_stop_master(priv);
5855 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
5856 iwl3945_hw_nic_reset(priv);
b481de9c
ZY		 5857
5858 exit:
bb8c093b 5859 memset(&priv->card_alive, 0, sizeof(struct iwl3945_alive_resp));
b481de9c
ZY		 5860
5861 if (priv->ibss_beacon)
5862 dev_kfree_skb(priv->ibss_beacon);
5863 priv->ibss_beacon = NULL;
5864
5865 /* clear out any free frames */
bb8c093b 5866 iwl3945_clear_free_frames(priv);
b481de9c
ZY		 5867}
5868
bb8c093b 5869static void iwl3945_down(struct iwl3945_priv *priv)
b481de9c
ZY		 5870{
5871 mutex_lock(&priv->mutex);
bb8c093b 5872 __iwl3945_down(priv);
b481de9c 5873 mutex_unlock(&priv->mutex);
b24d22b1 5874
bb8c093b 5875 iwl3945_cancel_deferred_work(priv);
b481de9c
ZY		 5876}
5877
5878#define MAX_HW_RESTARTS 5
5879
bb8c093b 5880static int __iwl3945_up(struct iwl3945_priv *priv)
b481de9c
ZY		 5881{
5882 int rc, i;
5883
5884 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
5885 IWL_WARNING("Exit pending; will not bring the NIC up\n");
5886 return -EIO;
5887 }
5888
5889 if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
5890 IWL_WARNING("Radio disabled by SW RF kill (module "
5891 "parameter)\n");
e655b9f0
ZY		 5892 return -ENODEV;
5893 }
5894
e903fbd4
RC		 5895 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
5896 IWL_ERROR("ucode not available for device bringup\n");
5897 return -EIO;
5898 }
5899
e655b9f0
ZY		 5900 /* If platform's RF_KILL switch is NOT set to KILL */
5901 if (iwl3945_read32(priv, CSR_GP_CNTRL) &
5902 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
5903 clear_bit(STATUS_RF_KILL_HW, &priv->status);
5904 else {
5905 set_bit(STATUS_RF_KILL_HW, &priv->status);
5906 if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
5907 IWL_WARNING("Radio disabled by HW RF Kill switch\n");
5908 return -ENODEV;
5909 }
b481de9c 5910 }
80fcc9e2 5911
bb8c093b 5912 iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 5913
bb8c093b 5914 rc = iwl3945_hw_nic_init(priv);
b481de9c
ZY		 5915 if (rc) {
5916 IWL_ERROR("Unable to int nic\n");
5917 return rc;
5918 }
5919
5920 /* make sure rfkill handshake bits are cleared */
bb8c093b
CH		 5921 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5922 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 5923 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
5924
5925 /* clear (again), then enable host interrupts */
bb8c093b
CH		 5926 iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
5927 iwl3945_enable_interrupts(priv);
b481de9c
ZY		 5928
5929 /* really make sure rfkill handshake bits are cleared */
bb8c093b
CH		 5930 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5931 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 5932
5933 /* Copy original ucode data image from disk into backup cache.
5934 * This will be used to initialize the on-board processor's
5935 * data SRAM for a clean start when the runtime program first loads. */
5936 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 5937 priv->ucode_data.len);
b481de9c 5938
e655b9f0
ZY		 5939 /* We return success when we resume from suspend and rf_kill is on. */
5940 if (test_bit(STATUS_RF_KILL_HW, &priv->status))
5941 return 0;
5942
b481de9c
ZY		 5943 for (i = 0; i < MAX_HW_RESTARTS; i++) {
5944
bb8c093b 5945 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 5946
5947 /* load bootstrap state machine,
5948 * load bootstrap program into processor's memory,
5949 * prepare to load the "initialize" uCode */
bb8c093b 5950 rc = iwl3945_load_bsm(priv);
b481de9c
ZY		 5951
5952 if (rc) {
5953 IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
5954 continue;
5955 }
5956
5957 /* start card; "initialize" will load runtime ucode */
bb8c093b 5958 iwl3945_nic_start(priv);
b481de9c 5959
b481de9c
ZY		 5960 IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
5961
5962 return 0;
5963 }
5964
5965 set_bit(STATUS_EXIT_PENDING, &priv->status);
bb8c093b 5966 __iwl3945_down(priv);
ebef2008 5967 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY		 5968
5969 /* tried to restart and config the device for as long as our
5970 * patience could withstand */
5971 IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
5972 return -EIO;
5973}
5974
5975
5976/*****************************************************************************
5977 *
5978 * Workqueue callbacks
5979 *
5980 *****************************************************************************/
5981
bb8c093b 5982static void iwl3945_bg_init_alive_start(struct work_struct *data)
b481de9c 5983{
bb8c093b
CH		 5984 struct iwl3945_priv *priv =
5985 container_of(data, struct iwl3945_priv, init_alive_start.work);
b481de9c
ZY		 5986
5987 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5988 return;
5989
5990 mutex_lock(&priv->mutex);
bb8c093b 5991 iwl3945_init_alive_start(priv);
b481de9c
ZY		 5992 mutex_unlock(&priv->mutex);
5993}
5994
bb8c093b 5995static void iwl3945_bg_alive_start(struct work_struct *data)
b481de9c 5996{
bb8c093b
CH		 5997 struct iwl3945_priv *priv =
5998 container_of(data, struct iwl3945_priv, alive_start.work);
b481de9c
ZY		 5999
6000 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6001 return;
6002
6003 mutex_lock(&priv->mutex);
bb8c093b 6004 iwl3945_alive_start(priv);
b481de9c
ZY		 6005 mutex_unlock(&priv->mutex);
6006}
6007
bb8c093b 6008static void iwl3945_bg_rf_kill(struct work_struct *work)
b481de9c 6009{
bb8c093b 6010 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill);
b481de9c
ZY		 6011
6012 wake_up_interruptible(&priv->wait_command_queue);
6013
6014 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6015 return;
6016
6017 mutex_lock(&priv->mutex);
6018
bb8c093b 6019 if (!iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 6020 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
6021 "HW and/or SW RF Kill no longer active, restarting "
6022 "device\n");
6023 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
6024 queue_work(priv->workqueue, &priv->restart);
6025 } else {
6026
6027 if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
6028 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
6029 "disabled by SW switch\n");
6030 else
6031 IWL_WARNING("Radio Frequency Kill Switch is On:\n"
6032 "Kill switch must be turned off for "
6033 "wireless networking to work.\n");
6034 }
ebef2008 6035
b481de9c 6036 mutex_unlock(&priv->mutex);
80fcc9e2 6037 iwl3945_rfkill_set_hw_state(priv);
b481de9c
ZY		 6038}
6039
5ec03976
AK		 6040static void iwl3945_bg_set_monitor(struct work_struct *work)
6041{
6042 struct iwl3945_priv *priv = container_of(work,
6043 struct iwl3945_priv, set_monitor);
6044
6045 IWL_DEBUG(IWL_DL_STATE, "setting monitor mode\n");
6046
6047 mutex_lock(&priv->mutex);
6048
6049 if (!iwl3945_is_ready(priv))
6050 IWL_DEBUG(IWL_DL_STATE, "leave - not ready\n");
6051 else
05c914fe 6052 if (iwl3945_set_mode(priv, NL80211_IFTYPE_MONITOR) != 0)
5ec03976
AK		 6053 IWL_ERROR("iwl3945_set_mode() failed\n");
6054
6055 mutex_unlock(&priv->mutex);
6056}
6057
b481de9c
ZY		 6058#define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
6059
bb8c093b 6060static void iwl3945_bg_scan_check(struct work_struct *data)
b481de9c 6061{
bb8c093b
CH		 6062 struct iwl3945_priv *priv =
6063 container_of(data, struct iwl3945_priv, scan_check.work);
b481de9c
ZY		 6064
6065 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6066 return;
6067
6068 mutex_lock(&priv->mutex);
6069 if (test_bit(STATUS_SCANNING, &priv->status) ||
6070 test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6071 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
6072 "Scan completion watchdog resetting adapter (%dms)\n",
6073 jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
15e869d8 6074
b481de9c 6075 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
bb8c093b 6076 iwl3945_send_scan_abort(priv);
b481de9c
ZY		 6077 }
6078 mutex_unlock(&priv->mutex);
6079}
6080
bb8c093b 6081static void iwl3945_bg_request_scan(struct work_struct *data)
b481de9c 6082{
bb8c093b
CH		 6083 struct iwl3945_priv *priv =
6084 container_of(data, struct iwl3945_priv, request_scan);
6085 struct iwl3945_host_cmd cmd = {
b481de9c 6086 .id = REPLY_SCAN_CMD,
bb8c093b 6087 .len = sizeof(struct iwl3945_scan_cmd),
b481de9c
ZY		 6088 .meta.flags = CMD_SIZE_HUGE,
6089 };
6090 int rc = 0;
bb8c093b 6091 struct iwl3945_scan_cmd *scan;
b481de9c 6092 struct ieee80211_conf *conf = NULL;
f9340520 6093 u8 n_probes = 2;
8318d78a 6094 enum ieee80211_band band;
b481de9c
ZY		 6095
6096 conf = ieee80211_get_hw_conf(priv->hw);
6097
6098 mutex_lock(&priv->mutex);
6099
bb8c093b 6100 if (!iwl3945_is_ready(priv)) {
b481de9c
ZY		 6101 IWL_WARNING("request scan called when driver not ready.\n");
6102 goto done;
6103 }
6104
6105 /* Make sure the scan wasn't cancelled before this queued work
6106 * was given the chance to run... */
6107 if (!test_bit(STATUS_SCANNING, &priv->status))
6108 goto done;
6109
6110 /* This should never be called or scheduled if there is currently
6111 * a scan active in the hardware. */
6112 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
6113 IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
6114 "Ignoring second request.\n");
6115 rc = -EIO;
6116 goto done;
6117 }
6118
6119 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
6120 IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
6121 goto done;
6122 }
6123
6124 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6125 IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
6126 goto done;
6127 }
6128
bb8c093b 6129 if (iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 6130 IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
6131 goto done;
6132 }
6133
6134 if (!test_bit(STATUS_READY, &priv->status)) {
6135 IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
6136 goto done;
6137 }
6138
6139 if (!priv->scan_bands) {
6140 IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
6141 goto done;
6142 }
6143
6144 if (!priv->scan) {
bb8c093b 6145 priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
b481de9c
ZY		 6146 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
6147 if (!priv->scan) {
6148 rc = -ENOMEM;
6149 goto done;
6150 }
6151 }
6152 scan = priv->scan;
bb8c093b 6153 memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
b481de9c
ZY		 6154
6155 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
6156 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
6157
bb8c093b 6158 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 6159 u16 interval = 0;
6160 u32 extra;
6161 u32 suspend_time = 100;
6162 u32 scan_suspend_time = 100;
6163 unsigned long flags;
6164
6165 IWL_DEBUG_INFO("Scanning while associated...\n");
6166
6167 spin_lock_irqsave(&priv->lock, flags);
6168 interval = priv->beacon_int;
6169 spin_unlock_irqrestore(&priv->lock, flags);
6170
6171 scan->suspend_time = 0;
15e869d8 6172 scan->max_out_time = cpu_to_le32(200 * 1024);
b481de9c
ZY		 6173 if (!interval)
6174 interval = suspend_time;
6175 /*
6176 * suspend time format:
6177 * 0-19: beacon interval in usec (time before exec.)
6178 * 20-23: 0
6179 * 24-31: number of beacons (suspend between channels)
6180 */
6181
6182 extra = (suspend_time / interval) << 24;
6183 scan_suspend_time = 0xFF0FFFFF &
6184 (extra | ((suspend_time % interval) * 1024));
6185
6186 scan->suspend_time = cpu_to_le32(scan_suspend_time);
6187 IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
6188 scan_suspend_time, interval);
6189 }
6190
6191 /* We should add the ability for user to lock to PASSIVE ONLY */
6192 if (priv->one_direct_scan) {
6193 IWL_DEBUG_SCAN
6194 ("Kicking off one direct scan for '%s'\n",
bb8c093b 6195 iwl3945_escape_essid(priv->direct_ssid,
b481de9c
ZY		 6196 priv->direct_ssid_len));
6197 scan->direct_scan[0].id = WLAN_EID_SSID;
6198 scan->direct_scan[0].len = priv->direct_ssid_len;
6199 memcpy(scan->direct_scan[0].ssid,
6200 priv->direct_ssid, priv->direct_ssid_len);
f9340520 6201 n_probes++;
bb8c093b 6202 } else if (!iwl3945_is_associated(priv) && priv->essid_len) {
786b4557
BM		 6203 IWL_DEBUG_SCAN
6204 ("Kicking off one direct scan for '%s' when not associated\n",
6205 iwl3945_escape_essid(priv->essid, priv->essid_len));
b481de9c
ZY		 6206 scan->direct_scan[0].id = WLAN_EID_SSID;
6207 scan->direct_scan[0].len = priv->essid_len;
6208 memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len);
f9340520
AK		 6209 n_probes++;
6210 } else
786b4557 6211 IWL_DEBUG_SCAN("Kicking off one indirect scan.\n");
b481de9c
ZY		 6212
6213 /* We don't build a direct scan probe request; the uCode will do
6214 * that based on the direct_mask added to each channel entry */
6215 scan->tx_cmd.len = cpu_to_le16(
bb8c093b 6216 iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
18904f58 6217 IWL_MAX_SCAN_SIZE - sizeof(*scan), 0));
b481de9c
ZY		 6218 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
6219 scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
6220 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
6221
6222 /* flags + rate selection */
6223
66b5004d 6224 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
b481de9c
ZY		 6225 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
6226 scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
6227 scan->good_CRC_th = 0;
8318d78a 6228 band = IEEE80211_BAND_2GHZ;
66b5004d 6229 } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
b481de9c
ZY		 6230 scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
6231 scan->good_CRC_th = IWL_GOOD_CRC_TH;
8318d78a 6232 band = IEEE80211_BAND_5GHZ;
66b5004d 6233 } else {
b481de9c
ZY		 6234 IWL_WARNING("Invalid scan band count\n");
6235 goto done;
6236 }
6237
6238 /* select Rx antennas */
6239 scan->flags |= iwl3945_get_antenna_flags(priv);
6240
05c914fe 6241 if (priv->iw_mode == NL80211_IFTYPE_MONITOR)
b481de9c
ZY		 6242 scan->filter_flags = RXON_FILTER_PROMISC_MSK;
6243
f9340520
AK		 6244 scan->channel_count =
6245 iwl3945_get_channels_for_scan(priv, band, 1, /* active */
6246 n_probes,
6247 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
b481de9c
ZY		 6248
6249 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
bb8c093b 6250 scan->channel_count * sizeof(struct iwl3945_scan_channel);
b481de9c
ZY		 6251 cmd.data = scan;
6252 scan->len = cpu_to_le16(cmd.len);
6253
6254 set_bit(STATUS_SCAN_HW, &priv->status);
bb8c093b 6255 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 6256 if (rc)
6257 goto done;
6258
6259 queue_delayed_work(priv->workqueue, &priv->scan_check,
6260 IWL_SCAN_CHECK_WATCHDOG);
6261
6262 mutex_unlock(&priv->mutex);
6263 return;
6264
6265 done:
01ebd063 6266 /* inform mac80211 scan aborted */
b481de9c
ZY		 6267 queue_work(priv->workqueue, &priv->scan_completed);
6268 mutex_unlock(&priv->mutex);
6269}
6270
bb8c093b 6271static void iwl3945_bg_up(struct work_struct *data)
b481de9c 6272{
bb8c093b 6273 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up);
b481de9c
ZY		 6274
6275 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6276 return;
6277
6278 mutex_lock(&priv->mutex);
bb8c093b 6279 __iwl3945_up(priv);
b481de9c 6280 mutex_unlock(&priv->mutex);
80fcc9e2 6281 iwl3945_rfkill_set_hw_state(priv);
b481de9c
ZY		 6282}
6283
bb8c093b 6284static void iwl3945_bg_restart(struct work_struct *data)
b481de9c 6285{
bb8c093b 6286 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart);
b481de9c
ZY		 6287
6288 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6289 return;
6290
bb8c093b 6291 iwl3945_down(priv);
b481de9c
ZY		 6292 queue_work(priv->workqueue, &priv->up);
6293}
6294
bb8c093b 6295static void iwl3945_bg_rx_replenish(struct work_struct *data)
b481de9c 6296{
bb8c093b
CH		 6297 struct iwl3945_priv *priv =
6298 container_of(data, struct iwl3945_priv, rx_replenish);
b481de9c
ZY		 6299
6300 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6301 return;
6302
6303 mutex_lock(&priv->mutex);
bb8c093b 6304 iwl3945_rx_replenish(priv);
b481de9c
ZY		 6305 mutex_unlock(&priv->mutex);
6306}
6307
7878a5a4
MA		 6308#define IWL_DELAY_NEXT_SCAN (HZ*2)
6309
cd56d331 6310static void iwl3945_post_associate(struct iwl3945_priv *priv)
b481de9c 6311{
b481de9c
ZY		 6312 int rc = 0;
6313 struct ieee80211_conf *conf = NULL;
6314
05c914fe 6315 if (priv->iw_mode == NL80211_IFTYPE_AP) {
3ac7f146 6316 IWL_ERROR("%s Should not be called in AP mode\n", __func__);
b481de9c
ZY		 6317 return;
6318 }
6319
6320
e174961c
JB		 6321 IWL_DEBUG_ASSOC("Associated as %d to: %pM\n",
6322 priv->assoc_id, priv->active_rxon.bssid_addr);
b481de9c
ZY		 6323
6324 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6325 return;
6326
322a9811 6327 if (!priv->vif || !priv->is_open)
6ef89d0a 6328 return;
322a9811 6329
bb8c093b 6330 iwl3945_scan_cancel_timeout(priv, 200);
15e869d8 6331
b481de9c
ZY		 6332 conf = ieee80211_get_hw_conf(priv->hw);
6333
6334 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6335 iwl3945_commit_rxon(priv);
b481de9c 6336
bb8c093b
CH		 6337 memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
6338 iwl3945_setup_rxon_timing(priv);
6339 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY		 6340 sizeof(priv->rxon_timing), &priv->rxon_timing);
6341 if (rc)
6342 IWL_WARNING("REPLY_RXON_TIMING failed - "
6343 "Attempting to continue.\n");
6344
6345 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
6346
6347 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
6348
6349 IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
6350 priv->assoc_id, priv->beacon_int);
6351
6352 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
6353 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
6354 else
6355 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
6356
6357 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
6358 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
6359 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
6360 else
6361 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
6362
05c914fe 6363 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY		 6364 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
6365
6366 }
6367
bb8c093b 6368 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6369
6370 switch (priv->iw_mode) {
05c914fe 6371 case NL80211_IFTYPE_STATION:
bb8c093b 6372 iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
b481de9c
ZY		 6373 break;
6374
05c914fe 6375 case NL80211_IFTYPE_ADHOC:
b481de9c
ZY		 6376
6377 /* clear out the station table */
bb8c093b 6378 iwl3945_clear_stations_table(priv);
b481de9c 6379
bb8c093b
CH		 6380 iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
6381 iwl3945_add_station(priv, priv->bssid, 0, 0);
b481de9c 6382 iwl3945_sync_sta(priv, IWL_STA_ID,
8318d78a 6383 (priv->band == IEEE80211_BAND_5GHZ) ?
b481de9c
ZY		 6384 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
6385 CMD_ASYNC);
bb8c093b
CH		 6386 iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
6387 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 6388
6389 break;
6390
6391 default:
6392 IWL_ERROR("%s Should not be called in %d mode\n",
3ac7f146 6393 __func__, priv->iw_mode);
b481de9c
ZY		 6394 break;
6395 }
6396
bb8c093b 6397 iwl3945_activate_qos(priv, 0);
292ae174 6398
7878a5a4
MA		 6399 /* we have just associated, don't start scan too early */
6400 priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
cd56d331
AK		 6401}
6402
bb8c093b 6403static void iwl3945_bg_abort_scan(struct work_struct *work)
b481de9c 6404{
bb8c093b 6405 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan);
b481de9c 6406
bb8c093b 6407 if (!iwl3945_is_ready(priv))
b481de9c
ZY		 6408 return;
6409
6410 mutex_lock(&priv->mutex);
6411
6412 set_bit(STATUS_SCAN_ABORTING, &priv->status);
bb8c093b 6413 iwl3945_send_scan_abort(priv);
b481de9c
ZY		 6414
6415 mutex_unlock(&priv->mutex);
6416}
6417
e8975581 6418static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed);
76bb77e0 6419
bb8c093b 6420static void iwl3945_bg_scan_completed(struct work_struct *work)
b481de9c 6421{
bb8c093b
CH		 6422 struct iwl3945_priv *priv =
6423 container_of(work, struct iwl3945_priv, scan_completed);
b481de9c
ZY		 6424
6425 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
6426
6427 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6428 return;
6429
a0646470 6430 if (test_bit(STATUS_CONF_PENDING, &priv->status))
e8975581 6431 iwl3945_mac_config(priv->hw, 0);
76bb77e0 6432
b481de9c
ZY		 6433 ieee80211_scan_completed(priv->hw);
6434
6435 /* Since setting the TXPOWER may have been deferred while
6436 * performing the scan, fire one off */
6437 mutex_lock(&priv->mutex);
bb8c093b 6438 iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 6439 mutex_unlock(&priv->mutex);
6440}
6441
6442/*****************************************************************************
6443 *
6444 * mac80211 entry point functions
6445 *
6446 *****************************************************************************/
6447
5a66926a
ZY		 6448#define UCODE_READY_TIMEOUT (2 * HZ)
6449
bb8c093b 6450static int iwl3945_mac_start(struct ieee80211_hw *hw)
b481de9c 6451{
bb8c093b 6452 struct iwl3945_priv *priv = hw->priv;
5a66926a 6453 int ret;
b481de9c
ZY		 6454
6455 IWL_DEBUG_MAC80211("enter\n");
6456
5a66926a
ZY		 6457 if (pci_enable_device(priv->pci_dev)) {
6458 IWL_ERROR("Fail to pci_enable_device\n");
6459 return -ENODEV;
6460 }
6461 pci_restore_state(priv->pci_dev);
6462 pci_enable_msi(priv->pci_dev);
6463
6464 ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
6465 DRV_NAME, priv);
6466 if (ret) {
6467 IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq);
6468 goto out_disable_msi;
6469 }
6470
b481de9c
ZY		 6471 /* we should be verifying the device is ready to be opened */
6472 mutex_lock(&priv->mutex);
6473
5a66926a
ZY		 6474 memset(&priv->staging_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
6475 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
6476 * ucode filename and max sizes are card-specific. */
6477
6478 if (!priv->ucode_code.len) {
6479 ret = iwl3945_read_ucode(priv);
6480 if (ret) {
6481 IWL_ERROR("Could not read microcode: %d\n", ret);
6482 mutex_unlock(&priv->mutex);
6483 goto out_release_irq;
6484 }
6485 }
b481de9c 6486
e655b9f0 6487 ret = __iwl3945_up(priv);
b481de9c
ZY		 6488
6489 mutex_unlock(&priv->mutex);
5a66926a 6490
80fcc9e2
AG		 6491 iwl3945_rfkill_set_hw_state(priv);
6492
e655b9f0
ZY		 6493 if (ret)
6494 goto out_release_irq;
6495
6496 IWL_DEBUG_INFO("Start UP work.\n");
6497
6498 if (test_bit(STATUS_IN_SUSPEND, &priv->status))
6499 return 0;
6500
5a66926a
ZY		 6501 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
6502 * mac80211 will not be run successfully. */
6503 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
6504 test_bit(STATUS_READY, &priv->status),
6505 UCODE_READY_TIMEOUT);
6506 if (!ret) {
6507 if (!test_bit(STATUS_READY, &priv->status)) {
6508 IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n",
6509 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6510 ret = -ETIMEDOUT;
6511 goto out_release_irq;
6512 }
6513 }
6514
e655b9f0 6515 priv->is_open = 1;
b481de9c
ZY		 6516 IWL_DEBUG_MAC80211("leave\n");
6517 return 0;
5a66926a
ZY		 6518
6519out_release_irq:
6520 free_irq(priv->pci_dev->irq, priv);
6521out_disable_msi:
6522 pci_disable_msi(priv->pci_dev);
e655b9f0
ZY		 6523 pci_disable_device(priv->pci_dev);
6524 priv->is_open = 0;
6525 IWL_DEBUG_MAC80211("leave - failed\n");
5a66926a 6526 return ret;
b481de9c
ZY		 6527}
6528
bb8c093b 6529static void iwl3945_mac_stop(struct ieee80211_hw *hw)
b481de9c 6530{
bb8c093b 6531 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6532
6533 IWL_DEBUG_MAC80211("enter\n");
6ef89d0a 6534
e655b9f0
ZY		 6535 if (!priv->is_open) {
6536 IWL_DEBUG_MAC80211("leave - skip\n");
6537 return;
6538 }
6539
b481de9c 6540 priv->is_open = 0;
5a66926a
ZY		 6541
6542 if (iwl3945_is_ready_rf(priv)) {
e655b9f0
ZY		 6543 /* stop mac, cancel any scan request and clear
6544 * RXON_FILTER_ASSOC_MSK BIT
6545 */
5a66926a
ZY		 6546 mutex_lock(&priv->mutex);
6547 iwl3945_scan_cancel_timeout(priv, 100);
fde3571f 6548 mutex_unlock(&priv->mutex);
fde3571f
MA		 6549 }
6550
5a66926a
ZY		 6551 iwl3945_down(priv);
6552
6553 flush_workqueue(priv->workqueue);
6554 free_irq(priv->pci_dev->irq, priv);
6555 pci_disable_msi(priv->pci_dev);
6556 pci_save_state(priv->pci_dev);
6557 pci_disable_device(priv->pci_dev);
6ef89d0a 6558
b481de9c 6559 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 6560}
6561
e039fa4a 6562static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 6563{
bb8c093b 6564 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6565
6566 IWL_DEBUG_MAC80211("enter\n");
6567
b481de9c 6568 IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 6569 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 6570
e039fa4a 6571 if (iwl3945_tx_skb(priv, skb))
b481de9c
ZY		 6572 dev_kfree_skb_any(skb);
6573
6574 IWL_DEBUG_MAC80211("leave\n");
6575 return 0;
6576}
6577
bb8c093b 6578static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
b481de9c
ZY		 6579 struct ieee80211_if_init_conf *conf)
6580{
bb8c093b 6581 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6582 unsigned long flags;
6583
32bfd35d 6584 IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
b481de9c 6585
32bfd35d
JB		 6586 if (priv->vif) {
6587 IWL_DEBUG_MAC80211("leave - vif != NULL\n");
864792e3 6588 return -EOPNOTSUPP;
b481de9c
ZY		 6589 }
6590
6591 spin_lock_irqsave(&priv->lock, flags);
32bfd35d 6592 priv->vif = conf->vif;
b481de9c
ZY		 6593
6594 spin_unlock_irqrestore(&priv->lock, flags);
6595
6596 mutex_lock(&priv->mutex);
864792e3
TW		 6597
6598 if (conf->mac_addr) {
e174961c 6599 IWL_DEBUG_MAC80211("Set: %pM\n", conf->mac_addr);
864792e3
TW		 6600 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
6601 }
6602
5a66926a
ZY		 6603 if (iwl3945_is_ready(priv))
6604 iwl3945_set_mode(priv, conf->type);
b481de9c 6605
b481de9c
ZY		 6606 mutex_unlock(&priv->mutex);
6607
5a66926a 6608 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 6609 return 0;
6610}
6611
6612/**
bb8c093b 6613 * iwl3945_mac_config - mac80211 config callback
b481de9c
ZY		 6614 *
6615 * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
6616 * be set inappropriately and the driver currently sets the hardware up to
6617 * use it whenever needed.
6618 */
e8975581 6619static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed)
b481de9c 6620{
bb8c093b
CH		 6621 struct iwl3945_priv *priv = hw->priv;
6622 const struct iwl3945_channel_info *ch_info;
e8975581 6623 struct ieee80211_conf *conf = &hw->conf;
b481de9c 6624 unsigned long flags;
76bb77e0 6625 int ret = 0;
b481de9c
ZY		 6626
6627 mutex_lock(&priv->mutex);
8318d78a 6628 IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
b481de9c 6629
bb8c093b 6630 if (!iwl3945_is_ready(priv)) {
b481de9c 6631 IWL_DEBUG_MAC80211("leave - not ready\n");
76bb77e0
ZY		 6632 ret = -EIO;
6633 goto out;
b481de9c
ZY		 6634 }
6635
bb8c093b 6636 if (unlikely(!iwl3945_param_disable_hw_scan &&
b481de9c 6637 test_bit(STATUS_SCANNING, &priv->status))) {
a0646470
ZY		 6638 IWL_DEBUG_MAC80211("leave - scanning\n");
6639 set_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 6640 mutex_unlock(&priv->mutex);
a0646470 6641 return 0;
b481de9c
ZY		 6642 }
6643
6644 spin_lock_irqsave(&priv->lock, flags);
6645
8318d78a
JB		 6646 ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
6647 conf->channel->hw_value);
b481de9c 6648 if (!is_channel_valid(ch_info)) {
66b5004d 6649 IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this band.\n",
8318d78a 6650 conf->channel->hw_value, conf->channel->band);
b481de9c
ZY		 6651 IWL_DEBUG_MAC80211("leave - invalid channel\n");
6652 spin_unlock_irqrestore(&priv->lock, flags);
76bb77e0
ZY		 6653 ret = -EINVAL;
6654 goto out;
b481de9c
ZY		 6655 }
6656
8318d78a 6657 iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
b481de9c 6658
8318d78a 6659 iwl3945_set_flags_for_phymode(priv, conf->channel->band);
b481de9c
ZY		 6660
6661 /* The list of supported rates and rate mask can be different
6662 * for each phymode; since the phymode may have changed, reset
6663 * the rate mask to what mac80211 lists */
bb8c093b 6664 iwl3945_set_rate(priv);
b481de9c
ZY		 6665
6666 spin_unlock_irqrestore(&priv->lock, flags);
6667
6668#ifdef IEEE80211_CONF_CHANNEL_SWITCH
6669 if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
bb8c093b 6670 iwl3945_hw_channel_switch(priv, conf->channel);
76bb77e0 6671 goto out;
b481de9c
ZY		 6672 }
6673#endif
6674
bb8c093b 6675 iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
b481de9c
ZY		 6676
6677 if (!conf->radio_enabled) {
6678 IWL_DEBUG_MAC80211("leave - radio disabled\n");
76bb77e0 6679 goto out;
b481de9c
ZY		 6680 }
6681
bb8c093b 6682 if (iwl3945_is_rfkill(priv)) {
b481de9c 6683 IWL_DEBUG_MAC80211("leave - RF kill\n");
76bb77e0
ZY		 6684 ret = -EIO;
6685 goto out;
b481de9c
ZY		 6686 }
6687
bb8c093b 6688 iwl3945_set_rate(priv);
b481de9c
ZY		 6689
6690 if (memcmp(&priv->active_rxon,
6691 &priv->staging_rxon, sizeof(priv->staging_rxon)))
bb8c093b 6692 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6693 else
6694 IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
6695
6696 IWL_DEBUG_MAC80211("leave\n");
6697
76bb77e0 6698out:
a0646470 6699 clear_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 6700 mutex_unlock(&priv->mutex);
76bb77e0 6701 return ret;
b481de9c
ZY		 6702}
6703
bb8c093b 6704static void iwl3945_config_ap(struct iwl3945_priv *priv)
b481de9c
ZY		 6705{
6706 int rc = 0;
6707
d986bcd1 6708 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY		 6709 return;
6710
6711 /* The following should be done only at AP bring up */
5d1e2325 6712 if (!(iwl3945_is_associated(priv))) {
b481de9c
ZY		 6713
6714 /* RXON - unassoc (to set timing command) */
6715 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6716 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6717
6718 /* RXON Timing */
bb8c093b
CH		 6719 memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
6720 iwl3945_setup_rxon_timing(priv);
6721 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY		 6722 sizeof(priv->rxon_timing), &priv->rxon_timing);
6723 if (rc)
6724 IWL_WARNING("REPLY_RXON_TIMING failed - "
6725 "Attempting to continue.\n");
6726
6727 /* FIXME: what should be the assoc_id for AP? */
6728 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
6729 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
6730 priv->staging_rxon.flags |=
6731 RXON_FLG_SHORT_PREAMBLE_MSK;
6732 else
6733 priv->staging_rxon.flags &=
6734 ~RXON_FLG_SHORT_PREAMBLE_MSK;
6735
6736 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
6737 if (priv->assoc_capability &
6738 WLAN_CAPABILITY_SHORT_SLOT_TIME)
6739 priv->staging_rxon.flags |=
6740 RXON_FLG_SHORT_SLOT_MSK;
6741 else
6742 priv->staging_rxon.flags &=
6743 ~RXON_FLG_SHORT_SLOT_MSK;
6744
05c914fe 6745 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY		 6746 priv->staging_rxon.flags &=
6747 ~RXON_FLG_SHORT_SLOT_MSK;
6748 }
6749 /* restore RXON assoc */
6750 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
bb8c093b
CH		 6751 iwl3945_commit_rxon(priv);
6752 iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
556f8db7 6753 }
bb8c093b 6754 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 6755
6756 /* FIXME - we need to add code here to detect a totally new
6757 * configuration, reset the AP, unassoc, rxon timing, assoc,
6758 * clear sta table, add BCAST sta... */
6759}
6760
9d139c81
JB		 6761/* temporary */
6762static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb);
6763
32bfd35d
JB		 6764static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
6765 struct ieee80211_vif *vif,
b481de9c
ZY		 6766 struct ieee80211_if_conf *conf)
6767{
bb8c093b 6768 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6769 unsigned long flags;
6770 int rc;
6771
6772 if (conf == NULL)
6773 return -EIO;
6774
b716bb91
EG		 6775 if (priv->vif != vif) {
6776 IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
b716bb91
EG		 6777 return 0;
6778 }
6779
9d139c81 6780 /* handle this temporarily here */
05c914fe 6781 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
9d139c81
JB		 6782 conf->changed & IEEE80211_IFCC_BEACON) {
6783 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
6784 if (!beacon)
6785 return -ENOMEM;
6786 rc = iwl3945_mac_beacon_update(hw, beacon);
6787 if (rc)
6788 return rc;
6789 }
6790
4150c572
JB		 6791 /* XXX: this MUST use conf->mac_addr */
6792
05c914fe 6793 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
9d139c81 6794 (!conf->ssid_len)) {
b481de9c
ZY		 6795 IWL_DEBUG_MAC80211
6796 ("Leaving in AP mode because HostAPD is not ready.\n");
6797 return 0;
6798 }
6799
5a66926a
ZY		 6800 if (!iwl3945_is_alive(priv))
6801 return -EAGAIN;
6802
b481de9c
ZY		 6803 mutex_lock(&priv->mutex);
6804
b481de9c 6805 if (conf->bssid)
e174961c 6806 IWL_DEBUG_MAC80211("bssid: %pM\n", conf->bssid);
b481de9c 6807
4150c572
JB		 6808/*
6809 * very dubious code was here; the probe filtering flag is never set:
6810 *
b481de9c
ZY		 6811 if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
6812 !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
4150c572 6813 */
b481de9c 6814
05c914fe 6815 if (priv->iw_mode == NL80211_IFTYPE_AP) {
b481de9c
ZY		 6816 if (!conf->bssid) {
6817 conf->bssid = priv->mac_addr;
6818 memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
e174961c
JB		 6819 IWL_DEBUG_MAC80211("bssid was set to: %pM\n",
6820 conf->bssid);
b481de9c
ZY		 6821 }
6822 if (priv->ibss_beacon)
6823 dev_kfree_skb(priv->ibss_beacon);
6824
9d139c81 6825 priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
b481de9c
ZY		 6826 }
6827
fde3571f
MA		 6828 if (iwl3945_is_rfkill(priv))
6829 goto done;
6830
b481de9c
ZY		 6831 if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
6832 !is_multicast_ether_addr(conf->bssid)) {
6833 /* If there is currently a HW scan going on in the background
6834 * then we need to cancel it else the RXON below will fail. */
bb8c093b 6835 if (iwl3945_scan_cancel_timeout(priv, 100)) {
b481de9c
ZY		 6836 IWL_WARNING("Aborted scan still in progress "
6837 "after 100ms\n");
6838 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
6839 mutex_unlock(&priv->mutex);
6840 return -EAGAIN;
6841 }
6842 memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
6843
6844 /* TODO: Audit driver for usage of these members and see
6845 * if mac80211 deprecates them (priv->bssid looks like it
6846 * shouldn't be there, but I haven't scanned the IBSS code
6847 * to verify) - jpk */
6848 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
6849
05c914fe 6850 if (priv->iw_mode == NL80211_IFTYPE_AP)
bb8c093b 6851 iwl3945_config_ap(priv);
b481de9c 6852 else {
bb8c093b 6853 rc = iwl3945_commit_rxon(priv);
05c914fe 6854 if ((priv->iw_mode == NL80211_IFTYPE_STATION) && rc)
bb8c093b 6855 iwl3945_add_station(priv,
556f8db7 6856 priv->active_rxon.bssid_addr, 1, 0);
b481de9c
ZY		 6857 }
6858
6859 } else {
bb8c093b 6860 iwl3945_scan_cancel_timeout(priv, 100);
b481de9c 6861 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6862 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6863 }
6864
fde3571f 6865 done:
b481de9c
ZY		 6866 spin_lock_irqsave(&priv->lock, flags);
6867 if (!conf->ssid_len)
6868 memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
6869 else
6870 memcpy(priv->essid, conf->ssid, conf->ssid_len);
6871
6872 priv->essid_len = conf->ssid_len;
6873 spin_unlock_irqrestore(&priv->lock, flags);
6874
6875 IWL_DEBUG_MAC80211("leave\n");
6876 mutex_unlock(&priv->mutex);
6877
6878 return 0;
6879}
6880
bb8c093b 6881static void iwl3945_configure_filter(struct ieee80211_hw *hw,
4150c572
JB		 6882 unsigned int changed_flags,
6883 unsigned int *total_flags,
6884 int mc_count, struct dev_addr_list *mc_list)
6885{
5ec03976 6886 struct iwl3945_priv *priv = hw->priv;
25b3f57c
RF		 6887
6888 if (changed_flags & (*total_flags) & FIF_OTHER_BSS) {
6889 IWL_DEBUG_MAC80211("Enter: type %d (0x%x, 0x%x)\n",
05c914fe 6890 NL80211_IFTYPE_MONITOR,
25b3f57c
RF		 6891 changed_flags, *total_flags);
6892 /* queue work 'cuz mac80211 is holding a lock which
6893 * prevents us from issuing (synchronous) f/w cmds */
6894 queue_work(priv->workqueue, &priv->set_monitor);
5ec03976 6895 }
25b3f57c
RF		 6896 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI |
6897 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
4150c572
JB		 6898}
6899
bb8c093b 6900static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
b481de9c
ZY		 6901 struct ieee80211_if_init_conf *conf)
6902{
bb8c093b 6903 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6904
6905 IWL_DEBUG_MAC80211("enter\n");
6906
6907 mutex_lock(&priv->mutex);
6ef89d0a 6908
fde3571f
MA		 6909 if (iwl3945_is_ready_rf(priv)) {
6910 iwl3945_scan_cancel_timeout(priv, 100);
fde3571f
MA		 6911 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
6912 iwl3945_commit_rxon(priv);
6913 }
32bfd35d
JB		 6914 if (priv->vif == conf->vif) {
6915 priv->vif = NULL;
b481de9c
ZY		 6916 memset(priv->bssid, 0, ETH_ALEN);
6917 memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
6918 priv->essid_len = 0;
6919 }
6920 mutex_unlock(&priv->mutex);
6921
6922 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 6923}
6924
cd56d331
AK		 6925#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
6926
6927static void iwl3945_bss_info_changed(struct ieee80211_hw *hw,
6928 struct ieee80211_vif *vif,
6929 struct ieee80211_bss_conf *bss_conf,
6930 u32 changes)
6931{
6932 struct iwl3945_priv *priv = hw->priv;
6933
6934 IWL_DEBUG_MAC80211("changes = 0x%X\n", changes);
6935
6936 if (changes & BSS_CHANGED_ERP_PREAMBLE) {
6937 IWL_DEBUG_MAC80211("ERP_PREAMBLE %d\n",
6938 bss_conf->use_short_preamble);
6939 if (bss_conf->use_short_preamble)
6940 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
6941 else
6942 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
6943 }
6944
6945 if (changes & BSS_CHANGED_ERP_CTS_PROT) {
6946 IWL_DEBUG_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
6947 if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
6948 priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
6949 else
6950 priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
6951 }
6952
6953 if (changes & BSS_CHANGED_ASSOC) {
6954 IWL_DEBUG_MAC80211("ASSOC %d\n", bss_conf->assoc);
6955 /* This should never happen as this function should
6956 * never be called from interrupt context. */
6957 if (WARN_ON_ONCE(in_interrupt()))
6958 return;
6959 if (bss_conf->assoc) {
6960 priv->assoc_id = bss_conf->aid;
6961 priv->beacon_int = bss_conf->beacon_int;
6962 priv->timestamp0 = bss_conf->timestamp & 0xFFFFFFFF;
6963 priv->timestamp1 = (bss_conf->timestamp >> 32) &
6964 0xFFFFFFFF;
6965 priv->assoc_capability = bss_conf->assoc_capability;
6966 priv->next_scan_jiffies = jiffies +
6967 IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
6968 mutex_lock(&priv->mutex);
6969 iwl3945_post_associate(priv);
6970 mutex_unlock(&priv->mutex);
6971 } else {
6972 priv->assoc_id = 0;
6973 IWL_DEBUG_MAC80211("DISASSOC %d\n", bss_conf->assoc);
6974 }
6975 } else if (changes && iwl3945_is_associated(priv) && priv->assoc_id) {
6976 IWL_DEBUG_MAC80211("Associated Changes %d\n", changes);
6977 iwl3945_send_rxon_assoc(priv);
6978 }
6979
6980}
6981
bb8c093b 6982static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
b481de9c
ZY		 6983{
6984 int rc = 0;
6985 unsigned long flags;
bb8c093b 6986 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6987
6988 IWL_DEBUG_MAC80211("enter\n");
6989
15e869d8 6990 mutex_lock(&priv->mutex);
b481de9c
ZY		 6991 spin_lock_irqsave(&priv->lock, flags);
6992
bb8c093b 6993 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 6994 rc = -EIO;
6995 IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
6996 goto out_unlock;
6997 }
6998
05c914fe 6999 if (priv->iw_mode == NL80211_IFTYPE_AP) { /* APs don't scan */
b481de9c
ZY		 7000 rc = -EIO;
7001 IWL_ERROR("ERROR: APs don't scan\n");
7002 goto out_unlock;
7003 }
7004
7878a5a4
MA		 7005 /* we don't schedule scan within next_scan_jiffies period */
7006 if (priv->next_scan_jiffies &&
7007 time_after(priv->next_scan_jiffies, jiffies)) {
7008 rc = -EAGAIN;
7009 goto out_unlock;
7010 }
15dbf1b7
BM		 7011 /* if we just finished scan ask for delay for a broadcast scan */
7012 if ((len == 0) && priv->last_scan_jiffies &&
7013 time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN,
7014 jiffies)) {
b481de9c
ZY		 7015 rc = -EAGAIN;
7016 goto out_unlock;
7017 }
7018 if (len) {
7878a5a4 7019 IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
bb8c093b 7020 iwl3945_escape_essid(ssid, len), (int)len);
b481de9c
ZY		 7021
7022 priv->one_direct_scan = 1;
7023 priv->direct_ssid_len = (u8)
7024 min((u8) len, (u8) IW_ESSID_MAX_SIZE);
7025 memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
6ef89d0a
MA		 7026 } else
7027 priv->one_direct_scan = 0;
b481de9c 7028
bb8c093b 7029 rc = iwl3945_scan_initiate(priv);
b481de9c
ZY		 7030
7031 IWL_DEBUG_MAC80211("leave\n");
7032
7033out_unlock:
7034 spin_unlock_irqrestore(&priv->lock, flags);
15e869d8 7035 mutex_unlock(&priv->mutex);
b481de9c
ZY		 7036
7037 return rc;
7038}
7039
bb8c093b 7040static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
b481de9c
ZY		 7041 const u8 *local_addr, const u8 *addr,
7042 struct ieee80211_key_conf *key)
7043{
bb8c093b 7044 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7045 int rc = 0;
7046 u8 sta_id;
7047
7048 IWL_DEBUG_MAC80211("enter\n");
7049
bb8c093b 7050 if (!iwl3945_param_hwcrypto) {
b481de9c
ZY		 7051 IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
7052 return -EOPNOTSUPP;
7053 }
7054
7055 if (is_zero_ether_addr(addr))
7056 /* only support pairwise keys */
7057 return -EOPNOTSUPP;
7058
bb8c093b 7059 sta_id = iwl3945_hw_find_station(priv, addr);
b481de9c 7060 if (sta_id == IWL_INVALID_STATION) {
e174961c
JB		 7061 IWL_DEBUG_MAC80211("leave - %pM not in station map.\n",
7062 addr);
b481de9c
ZY		 7063 return -EINVAL;
7064 }
7065
7066 mutex_lock(&priv->mutex);
7067
bb8c093b 7068 iwl3945_scan_cancel_timeout(priv, 100);
15e869d8 7069
b481de9c
ZY		 7070 switch (cmd) {
7071 case SET_KEY:
bb8c093b 7072 rc = iwl3945_update_sta_key_info(priv, key, sta_id);
b481de9c 7073 if (!rc) {
bb8c093b
CH		 7074 iwl3945_set_rxon_hwcrypto(priv, 1);
7075 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7076 key->hw_key_idx = sta_id;
7077 IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
7078 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
7079 }
7080 break;
7081 case DISABLE_KEY:
bb8c093b 7082 rc = iwl3945_clear_sta_key_info(priv, sta_id);
b481de9c 7083 if (!rc) {
bb8c093b
CH		 7084 iwl3945_set_rxon_hwcrypto(priv, 0);
7085 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7086 IWL_DEBUG_MAC80211("disable hwcrypto key\n");
7087 }
7088 break;
7089 default:
7090 rc = -EINVAL;
7091 }
7092
7093 IWL_DEBUG_MAC80211("leave\n");
7094 mutex_unlock(&priv->mutex);
7095
7096 return rc;
7097}
7098
e100bb64 7099static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
b481de9c
ZY		 7100 const struct ieee80211_tx_queue_params *params)
7101{
bb8c093b 7102 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7103 unsigned long flags;
7104 int q;
b481de9c
ZY		 7105
7106 IWL_DEBUG_MAC80211("enter\n");
7107
bb8c093b 7108 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7109 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7110 return -EIO;
7111 }
7112
7113 if (queue >= AC_NUM) {
7114 IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
7115 return 0;
7116 }
7117
b481de9c
ZY		 7118 if (!priv->qos_data.qos_enable) {
7119 priv->qos_data.qos_active = 0;
7120 IWL_DEBUG_MAC80211("leave - qos not enabled\n");
7121 return 0;
7122 }
7123 q = AC_NUM - 1 - queue;
7124
7125 spin_lock_irqsave(&priv->lock, flags);
7126
7127 priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
7128 priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
7129 priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
7130 priv->qos_data.def_qos_parm.ac[q].edca_txop =
3330d7be 7131 cpu_to_le16((params->txop * 32));
b481de9c
ZY		 7132
7133 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
7134 priv->qos_data.qos_active = 1;
7135
7136 spin_unlock_irqrestore(&priv->lock, flags);
7137
7138 mutex_lock(&priv->mutex);
05c914fe 7139 if (priv->iw_mode == NL80211_IFTYPE_AP)
bb8c093b
CH		 7140 iwl3945_activate_qos(priv, 1);
7141 else if (priv->assoc_id && iwl3945_is_associated(priv))
7142 iwl3945_activate_qos(priv, 0);
b481de9c
ZY		 7143
7144 mutex_unlock(&priv->mutex);
7145
b481de9c
ZY		 7146 IWL_DEBUG_MAC80211("leave\n");
7147 return 0;
7148}
7149
bb8c093b 7150static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
b481de9c
ZY		 7151 struct ieee80211_tx_queue_stats *stats)
7152{
bb8c093b 7153 struct iwl3945_priv *priv = hw->priv;
b481de9c 7154 int i, avail;
bb8c093b
CH		 7155 struct iwl3945_tx_queue *txq;
7156 struct iwl3945_queue *q;
b481de9c
ZY		 7157 unsigned long flags;
7158
7159 IWL_DEBUG_MAC80211("enter\n");
7160
bb8c093b 7161 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7162 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7163 return -EIO;
7164 }
7165
7166 spin_lock_irqsave(&priv->lock, flags);
7167
7168 for (i = 0; i < AC_NUM; i++) {
7169 txq = &priv->txq[i];
7170 q = &txq->q;
bb8c093b 7171 avail = iwl3945_queue_space(q);
b481de9c 7172
57ffc589
JB		 7173 stats[i].len = q->n_window - avail;
7174 stats[i].limit = q->n_window - q->high_mark;
7175 stats[i].count = q->n_window;
b481de9c
ZY		 7176
7177 }
7178 spin_unlock_irqrestore(&priv->lock, flags);
7179
7180 IWL_DEBUG_MAC80211("leave\n");
7181
7182 return 0;
7183}
7184
bb8c093b 7185static int iwl3945_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY		 7186 struct ieee80211_low_level_stats *stats)
7187{
7188 IWL_DEBUG_MAC80211("enter\n");
7189 IWL_DEBUG_MAC80211("leave\n");
7190
7191 return 0;
7192}
7193
bb8c093b 7194static u64 iwl3945_mac_get_tsf(struct ieee80211_hw *hw)
b481de9c
ZY		 7195{
7196 IWL_DEBUG_MAC80211("enter\n");
7197 IWL_DEBUG_MAC80211("leave\n");
7198
7199 return 0;
7200}
7201
bb8c093b 7202static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
b481de9c 7203{
bb8c093b 7204 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7205 unsigned long flags;
7206
7207 mutex_lock(&priv->mutex);
7208 IWL_DEBUG_MAC80211("enter\n");
7209
bb8c093b 7210 iwl3945_reset_qos(priv);
292ae174 7211
b481de9c
ZY		 7212 spin_lock_irqsave(&priv->lock, flags);
7213 priv->assoc_id = 0;
7214 priv->assoc_capability = 0;
7215 priv->call_post_assoc_from_beacon = 0;
7216
7217 /* new association get rid of ibss beacon skb */
7218 if (priv->ibss_beacon)
7219 dev_kfree_skb(priv->ibss_beacon);
7220
7221 priv->ibss_beacon = NULL;
7222
7223 priv->beacon_int = priv->hw->conf.beacon_int;
7224 priv->timestamp1 = 0;
7225 priv->timestamp0 = 0;
05c914fe 7226 if ((priv->iw_mode == NL80211_IFTYPE_STATION))
b481de9c
ZY		 7227 priv->beacon_int = 0;
7228
7229 spin_unlock_irqrestore(&priv->lock, flags);
7230
fde3571f
MA		 7231 if (!iwl3945_is_ready_rf(priv)) {
7232 IWL_DEBUG_MAC80211("leave - not ready\n");
7233 mutex_unlock(&priv->mutex);
7234 return;
7235 }
7236
15e869d8
MA		 7237 /* we are restarting association process
7238 * clear RXON_FILTER_ASSOC_MSK bit
7239 */
05c914fe 7240 if (priv->iw_mode != NL80211_IFTYPE_AP) {
bb8c093b 7241 iwl3945_scan_cancel_timeout(priv, 100);
15e869d8 7242 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 7243 iwl3945_commit_rxon(priv);
15e869d8
MA		 7244 }
7245
b481de9c 7246 /* Per mac80211.h: This is only used in IBSS mode... */
05c914fe 7247 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
15e869d8 7248
b481de9c
ZY		 7249 IWL_DEBUG_MAC80211("leave - not in IBSS\n");
7250 mutex_unlock(&priv->mutex);
7251 return;
b481de9c
ZY		 7252 }
7253
bb8c093b 7254 iwl3945_set_rate(priv);
b481de9c
ZY		 7255
7256 mutex_unlock(&priv->mutex);
7257
7258 IWL_DEBUG_MAC80211("leave\n");
7259
7260}
7261
e039fa4a 7262static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 7263{
bb8c093b 7264 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7265 unsigned long flags;
7266
7267 mutex_lock(&priv->mutex);
7268 IWL_DEBUG_MAC80211("enter\n");
7269
bb8c093b 7270 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7271 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7272 mutex_unlock(&priv->mutex);
7273 return -EIO;
7274 }
7275
05c914fe 7276 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
b481de9c
ZY		 7277 IWL_DEBUG_MAC80211("leave - not IBSS\n");
7278 mutex_unlock(&priv->mutex);
7279 return -EIO;
7280 }
7281
7282 spin_lock_irqsave(&priv->lock, flags);
7283
7284 if (priv->ibss_beacon)
7285 dev_kfree_skb(priv->ibss_beacon);
7286
7287 priv->ibss_beacon = skb;
7288
7289 priv->assoc_id = 0;
7290
7291 IWL_DEBUG_MAC80211("leave\n");
7292 spin_unlock_irqrestore(&priv->lock, flags);
7293
bb8c093b 7294 iwl3945_reset_qos(priv);
b481de9c 7295
dc4b1e7d 7296 iwl3945_post_associate(priv);
b481de9c
ZY		 7297
7298 mutex_unlock(&priv->mutex);
7299
7300 return 0;
7301}
7302
7303/*****************************************************************************
7304 *
7305 * sysfs attributes
7306 *
7307 *****************************************************************************/
7308
c8b0e6e1 7309#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 7310
7311/*
7312 * The following adds a new attribute to the sysfs representation
7313 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
7314 * used for controlling the debug level.
7315 *
7316 * See the level definitions in iwl for details.
7317 */
7318
7319static ssize_t show_debug_level(struct device_driver *d, char *buf)
7320{
bb8c093b 7321 return sprintf(buf, "0x%08X\n", iwl3945_debug_level);
b481de9c
ZY		 7322}
7323static ssize_t store_debug_level(struct device_driver *d,
7324 const char *buf, size_t count)
7325{
7326 char *p = (char *)buf;
7327 u32 val;
7328
7329 val = simple_strtoul(p, &p, 0);
7330 if (p == buf)
7331 printk(KERN_INFO DRV_NAME
7332 ": %s is not in hex or decimal form.\n", buf);
7333 else
bb8c093b 7334 iwl3945_debug_level = val;
b481de9c
ZY		 7335
7336 return strnlen(buf, count);
7337}
7338
7339static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
7340 show_debug_level, store_debug_level);
7341
c8b0e6e1 7342#endif /* CONFIG_IWL3945_DEBUG */
b481de9c 7343
b481de9c
ZY		 7344static ssize_t show_temperature(struct device *d,
7345 struct device_attribute *attr, char *buf)
7346{
bb8c093b 7347 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c 7348
bb8c093b 7349 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7350 return -EAGAIN;
7351
bb8c093b 7352 return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
b481de9c
ZY		 7353}
7354
7355static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
7356
b481de9c
ZY		 7357static ssize_t show_tx_power(struct device *d,
7358 struct device_attribute *attr, char *buf)
7359{
bb8c093b 7360 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7361 return sprintf(buf, "%d\n", priv->user_txpower_limit);
7362}
7363
7364static ssize_t store_tx_power(struct device *d,
7365 struct device_attribute *attr,
7366 const char *buf, size_t count)
7367{
bb8c093b 7368 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7369 char *p = (char *)buf;
7370 u32 val;
7371
7372 val = simple_strtoul(p, &p, 10);
7373 if (p == buf)
7374 printk(KERN_INFO DRV_NAME
7375 ": %s is not in decimal form.\n", buf);
7376 else
bb8c093b 7377 iwl3945_hw_reg_set_txpower(priv, val);
b481de9c
ZY		 7378
7379 return count;
7380}
7381
7382static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
7383
7384static ssize_t show_flags(struct device *d,
7385 struct device_attribute *attr, char *buf)
7386{
bb8c093b 7387 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7388
7389 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
7390}
7391
7392static ssize_t store_flags(struct device *d,
7393 struct device_attribute *attr,
7394 const char *buf, size_t count)
7395{
bb8c093b 7396 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7397 u32 flags = simple_strtoul(buf, NULL, 0);
7398
7399 mutex_lock(&priv->mutex);
7400 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
7401 /* Cancel any currently running scans... */
bb8c093b 7402 if (iwl3945_scan_cancel_timeout(priv, 100))
b481de9c
ZY		 7403 IWL_WARNING("Could not cancel scan.\n");
7404 else {
7405 IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
7406 flags);
7407 priv->staging_rxon.flags = cpu_to_le32(flags);
bb8c093b 7408 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7409 }
7410 }
7411 mutex_unlock(&priv->mutex);
7412
7413 return count;
7414}
7415
7416static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
7417
7418static ssize_t show_filter_flags(struct device *d,
7419 struct device_attribute *attr, char *buf)
7420{
bb8c093b 7421 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7422
7423 return sprintf(buf, "0x%04X\n",
7424 le32_to_cpu(priv->active_rxon.filter_flags));
7425}
7426
7427static ssize_t store_filter_flags(struct device *d,
7428 struct device_attribute *attr,
7429 const char *buf, size_t count)
7430{
bb8c093b 7431 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7432 u32 filter_flags = simple_strtoul(buf, NULL, 0);
7433
7434 mutex_lock(&priv->mutex);
7435 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
7436 /* Cancel any currently running scans... */
bb8c093b 7437 if (iwl3945_scan_cancel_timeout(priv, 100))
b481de9c
ZY		 7438 IWL_WARNING("Could not cancel scan.\n");
7439 else {
7440 IWL_DEBUG_INFO("Committing rxon.filter_flags = "
7441 "0x%04X\n", filter_flags);
7442 priv->staging_rxon.filter_flags =
7443 cpu_to_le32(filter_flags);
bb8c093b 7444 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7445 }
7446 }
7447 mutex_unlock(&priv->mutex);
7448
7449 return count;
7450}
7451
7452static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
7453 store_filter_flags);
7454
c8b0e6e1 7455#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 7456
7457static ssize_t show_measurement(struct device *d,
7458 struct device_attribute *attr, char *buf)
7459{
bb8c093b
CH		 7460 struct iwl3945_priv *priv = dev_get_drvdata(d);
7461 struct iwl3945_spectrum_notification measure_report;
b481de9c 7462 u32 size = sizeof(measure_report), len = 0, ofs = 0;
3ac7f146 7463 u8 *data = (u8 *)&measure_report;
b481de9c
ZY		 7464 unsigned long flags;
7465
7466 spin_lock_irqsave(&priv->lock, flags);
7467 if (!(priv->measurement_status & MEASUREMENT_READY)) {
7468 spin_unlock_irqrestore(&priv->lock, flags);
7469 return 0;
7470 }
7471 memcpy(&measure_report, &priv->measure_report, size);
7472 priv->measurement_status = 0;
7473 spin_unlock_irqrestore(&priv->lock, flags);
7474
7475 while (size && (PAGE_SIZE - len)) {
7476 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
7477 PAGE_SIZE - len, 1);
7478 len = strlen(buf);
7479 if (PAGE_SIZE - len)
7480 buf[len++] = '\n';
7481
7482 ofs += 16;
7483 size -= min(size, 16U);
7484 }
7485
7486 return len;
7487}
7488
7489static ssize_t store_measurement(struct device *d,
7490 struct device_attribute *attr,
7491 const char *buf, size_t count)
7492{
bb8c093b 7493 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7494 struct ieee80211_measurement_params params = {
7495 .channel = le16_to_cpu(priv->active_rxon.channel),
7496 .start_time = cpu_to_le64(priv->last_tsf),
7497 .duration = cpu_to_le16(1),
7498 };
7499 u8 type = IWL_MEASURE_BASIC;
7500 u8 buffer[32];
7501 u8 channel;
7502
7503 if (count) {
7504 char *p = buffer;
7505 strncpy(buffer, buf, min(sizeof(buffer), count));
7506 channel = simple_strtoul(p, NULL, 0);
7507 if (channel)
7508 params.channel = channel;
7509
7510 p = buffer;
7511 while (*p && *p != ' ')
7512 p++;
7513 if (*p)
7514 type = simple_strtoul(p + 1, NULL, 0);
7515 }
7516
7517 IWL_DEBUG_INFO("Invoking measurement of type %d on "
7518 "channel %d (for '%s')\n", type, params.channel, buf);
bb8c093b 7519 iwl3945_get_measurement(priv, &params, type);
b481de9c
ZY		 7520
7521 return count;
7522}
7523
7524static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
7525 show_measurement, store_measurement);
c8b0e6e1 7526#endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
b481de9c 7527
b481de9c
ZY		 7528static ssize_t store_retry_rate(struct device *d,
7529 struct device_attribute *attr,
7530 const char *buf, size_t count)
7531{
bb8c093b 7532 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7533
7534 priv->retry_rate = simple_strtoul(buf, NULL, 0);
7535 if (priv->retry_rate <= 0)
7536 priv->retry_rate = 1;
7537
7538 return count;
7539}
7540
7541static ssize_t show_retry_rate(struct device *d,
7542 struct device_attribute *attr, char *buf)
7543{
bb8c093b 7544 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7545 return sprintf(buf, "%d", priv->retry_rate);
7546}
7547
7548static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
7549 store_retry_rate);
7550
7551static ssize_t store_power_level(struct device *d,
7552 struct device_attribute *attr,
7553 const char *buf, size_t count)
7554{
bb8c093b 7555 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7556 int rc;
7557 int mode;
7558
7559 mode = simple_strtoul(buf, NULL, 0);
7560 mutex_lock(&priv->mutex);
7561
bb8c093b 7562 if (!iwl3945_is_ready(priv)) {
b481de9c
ZY		 7563 rc = -EAGAIN;
7564 goto out;
7565 }
7566
7567 if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
7568 mode = IWL_POWER_AC;
7569 else
7570 mode |= IWL_POWER_ENABLED;
7571
7572 if (mode != priv->power_mode) {
bb8c093b 7573 rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
b481de9c
ZY		 7574 if (rc) {
7575 IWL_DEBUG_MAC80211("failed setting power mode.\n");
7576 goto out;
7577 }
7578 priv->power_mode = mode;
7579 }
7580
7581 rc = count;
7582
7583 out:
7584 mutex_unlock(&priv->mutex);
7585 return rc;
7586}
7587
7588#define MAX_WX_STRING 80
7589
7590/* Values are in microsecond */
7591static const s32 timeout_duration[] = {
7592 350000,
7593 250000,
7594 75000,
7595 37000,
7596 25000,
7597};
7598static const s32 period_duration[] = {
7599 400000,
7600 700000,
7601 1000000,
7602 1000000,
7603 1000000
7604};
7605
7606static ssize_t show_power_level(struct device *d,
7607 struct device_attribute *attr, char *buf)
7608{
bb8c093b 7609 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7610 int level = IWL_POWER_LEVEL(priv->power_mode);
7611 char *p = buf;
7612
7613 p += sprintf(p, "%d ", level);
7614 switch (level) {
7615 case IWL_POWER_MODE_CAM:
7616 case IWL_POWER_AC:
7617 p += sprintf(p, "(AC)");
7618 break;
7619 case IWL_POWER_BATTERY:
7620 p += sprintf(p, "(BATTERY)");
7621 break;
7622 default:
7623 p += sprintf(p,
7624 "(Timeout %dms, Period %dms)",
7625 timeout_duration[level - 1] / 1000,
7626 period_duration[level - 1] / 1000);
7627 }
7628
7629 if (!(priv->power_mode & IWL_POWER_ENABLED))
7630 p += sprintf(p, " OFF\n");
7631 else
7632 p += sprintf(p, " \n");
7633
3ac7f146 7634 return p - buf + 1;
b481de9c
ZY		 7635
7636}
7637
7638static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
7639 store_power_level);
7640
7641static ssize_t show_channels(struct device *d,
7642 struct device_attribute *attr, char *buf)
7643{
8318d78a
JB		 7644 /* all this shit doesn't belong into sysfs anyway */
7645 return 0;
b481de9c
ZY		 7646}
7647
7648static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
7649
7650static ssize_t show_statistics(struct device *d,
7651 struct device_attribute *attr, char *buf)
7652{
bb8c093b
CH		 7653 struct iwl3945_priv *priv = dev_get_drvdata(d);
7654 u32 size = sizeof(struct iwl3945_notif_statistics);
b481de9c 7655 u32 len = 0, ofs = 0;
3ac7f146 7656 u8 *data = (u8 *)&priv->statistics;
b481de9c
ZY		 7657 int rc = 0;
7658
bb8c093b 7659 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7660 return -EAGAIN;
7661
7662 mutex_lock(&priv->mutex);
bb8c093b 7663 rc = iwl3945_send_statistics_request(priv);
b481de9c
ZY		 7664 mutex_unlock(&priv->mutex);
7665
7666 if (rc) {
7667 len = sprintf(buf,
7668 "Error sending statistics request: 0x%08X\n", rc);
7669 return len;
7670 }
7671
7672 while (size && (PAGE_SIZE - len)) {
7673 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
7674 PAGE_SIZE - len, 1);
7675 len = strlen(buf);
7676 if (PAGE_SIZE - len)
7677 buf[len++] = '\n';
7678
7679 ofs += 16;
7680 size -= min(size, 16U);
7681 }
7682
7683 return len;
7684}
7685
7686static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
7687
7688static ssize_t show_antenna(struct device *d,
7689 struct device_attribute *attr, char *buf)
7690{
bb8c093b 7691 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c 7692
bb8c093b 7693 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7694 return -EAGAIN;
7695
7696 return sprintf(buf, "%d\n", priv->antenna);
7697}
7698
7699static ssize_t store_antenna(struct device *d,
7700 struct device_attribute *attr,
7701 const char *buf, size_t count)
7702{
7703 int ant;
bb8c093b 7704 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7705
7706 if (count == 0)
7707 return 0;
7708
7709 if (sscanf(buf, "%1i", &ant) != 1) {
7710 IWL_DEBUG_INFO("not in hex or decimal form.\n");
7711 return count;
7712 }
7713
7714 if ((ant >= 0) && (ant <= 2)) {
7715 IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
bb8c093b 7716 priv->antenna = (enum iwl3945_antenna)ant;
b481de9c
ZY		 7717 } else
7718 IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
7719
7720
7721 return count;
7722}
7723
7724static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
7725
7726static ssize_t show_status(struct device *d,
7727 struct device_attribute *attr, char *buf)
7728{
bb8c093b
CH		 7729 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
7730 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7731 return -EAGAIN;
7732 return sprintf(buf, "0x%08x\n", (int)priv->status);
7733}
7734
7735static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
7736
7737static ssize_t dump_error_log(struct device *d,
7738 struct device_attribute *attr,
7739 const char *buf, size_t count)
7740{
7741 char *p = (char *)buf;
7742
7743 if (p[0] == '1')
bb8c093b 7744 iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data);
b481de9c
ZY		 7745
7746 return strnlen(buf, count);
7747}
7748
7749static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
7750
7751static ssize_t dump_event_log(struct device *d,
7752 struct device_attribute *attr,
7753 const char *buf, size_t count)
7754{
7755 char *p = (char *)buf;
7756
7757 if (p[0] == '1')
bb8c093b 7758 iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data);
b481de9c
ZY		 7759
7760 return strnlen(buf, count);
7761}
7762
7763static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
7764
7765/*****************************************************************************
7766 *
7767 * driver setup and teardown
7768 *
7769 *****************************************************************************/
7770
bb8c093b 7771static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv)
b481de9c
ZY		 7772{
7773 priv->workqueue = create_workqueue(DRV_NAME);
7774
7775 init_waitqueue_head(&priv->wait_command_queue);
7776
bb8c093b
CH		 7777 INIT_WORK(&priv->up, iwl3945_bg_up);
7778 INIT_WORK(&priv->restart, iwl3945_bg_restart);
7779 INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
7780 INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
7781 INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
7782 INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
7783 INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
7784 INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
5ec03976 7785 INIT_WORK(&priv->set_monitor, iwl3945_bg_set_monitor);
bb8c093b
CH		 7786 INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
7787 INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
7788 INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
7789
7790 iwl3945_hw_setup_deferred_work(priv);
b481de9c
ZY		 7791
7792 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
bb8c093b 7793 iwl3945_irq_tasklet, (unsigned long)priv);
b481de9c
ZY		 7794}
7795
bb8c093b 7796static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv)
b481de9c 7797{
bb8c093b 7798 iwl3945_hw_cancel_deferred_work(priv);
b481de9c 7799
e47eb6ad 7800 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY		 7801 cancel_delayed_work(&priv->scan_check);
7802 cancel_delayed_work(&priv->alive_start);
b481de9c
ZY		 7803 cancel_work_sync(&priv->beacon_update);
7804}
7805
bb8c093b 7806static struct attribute *iwl3945_sysfs_entries[] = {
b481de9c
ZY		 7807 &dev_attr_antenna.attr,
7808 &dev_attr_channels.attr,
7809 &dev_attr_dump_errors.attr,
7810 &dev_attr_dump_events.attr,
7811 &dev_attr_flags.attr,
7812 &dev_attr_filter_flags.attr,
c8b0e6e1 7813#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 7814 &dev_attr_measurement.attr,
7815#endif
7816 &dev_attr_power_level.attr,
b481de9c 7817 &dev_attr_retry_rate.attr,
b481de9c
ZY		 7818 &dev_attr_statistics.attr,
7819 &dev_attr_status.attr,
7820 &dev_attr_temperature.attr,
b481de9c
ZY		 7821 &dev_attr_tx_power.attr,
7822
7823 NULL
7824};
7825
bb8c093b 7826static struct attribute_group iwl3945_attribute_group = {
b481de9c 7827 .name = NULL, /* put in device directory */
bb8c093b 7828 .attrs = iwl3945_sysfs_entries,
b481de9c
ZY		 7829};
7830
bb8c093b
CH		 7831static struct ieee80211_ops iwl3945_hw_ops = {
7832 .tx = iwl3945_mac_tx,
7833 .start = iwl3945_mac_start,
7834 .stop = iwl3945_mac_stop,
7835 .add_interface = iwl3945_mac_add_interface,
7836 .remove_interface = iwl3945_mac_remove_interface,
7837 .config = iwl3945_mac_config,
7838 .config_interface = iwl3945_mac_config_interface,
7839 .configure_filter = iwl3945_configure_filter,
7840 .set_key = iwl3945_mac_set_key,
7841 .get_stats = iwl3945_mac_get_stats,
7842 .get_tx_stats = iwl3945_mac_get_tx_stats,
7843 .conf_tx = iwl3945_mac_conf_tx,
7844 .get_tsf = iwl3945_mac_get_tsf,
7845 .reset_tsf = iwl3945_mac_reset_tsf,
cd56d331 7846 .bss_info_changed = iwl3945_bss_info_changed,
bb8c093b 7847 .hw_scan = iwl3945_mac_hw_scan
b481de9c
ZY		 7848};
7849
bb8c093b 7850static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY		 7851{
7852 int err = 0;
bb8c093b 7853 struct iwl3945_priv *priv;
b481de9c 7854 struct ieee80211_hw *hw;
82b9a121 7855 struct iwl_3945_cfg *cfg = (struct iwl_3945_cfg *)(ent->driver_data);
0359facc 7856 unsigned long flags;
b481de9c 7857
6440adb5
CB		 7858 /* Disabling hardware scan means that mac80211 will perform scans
7859 * "the hard way", rather than using device's scan. */
bb8c093b 7860 if (iwl3945_param_disable_hw_scan) {
b481de9c 7861 IWL_DEBUG_INFO("Disabling hw_scan\n");
bb8c093b 7862 iwl3945_hw_ops.hw_scan = NULL;
b481de9c
ZY		 7863 }
7864
dfe7d458 7865 if ((iwl3945_param_queues_num > IWL39_MAX_NUM_QUEUES) ||
bb8c093b 7866 (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) {
b481de9c 7867 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
dfe7d458 7868 IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES);
b481de9c
ZY		 7869 err = -EINVAL;
7870 goto out;
7871 }
7872
7873 /* mac80211 allocates memory for this device instance, including
7874 * space for this driver's private structure */
bb8c093b 7875 hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops);
b481de9c
ZY		 7876 if (hw == NULL) {
7877 IWL_ERROR("Can not allocate network device\n");
7878 err = -ENOMEM;
7879 goto out;
7880 }
7881 SET_IEEE80211_DEV(hw, &pdev->dev);
7882
f51359a8 7883 hw->rate_control_algorithm = "iwl-3945-rs";
4b7679a5 7884 hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
f51359a8 7885
b481de9c
ZY		 7886 IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
7887 priv = hw->priv;
7888 priv->hw = hw;
7889
7890 priv->pci_dev = pdev;
82b9a121 7891 priv->cfg = cfg;
6440adb5
CB		 7892
7893 /* Select antenna (may be helpful if only one antenna is connected) */
bb8c093b 7894 priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna;
c8b0e6e1 7895#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 7896 iwl3945_debug_level = iwl3945_param_debug;
b481de9c
ZY		 7897 atomic_set(&priv->restrict_refcnt, 0);
7898#endif
7899 priv->retry_rate = 1;
7900
7901 priv->ibss_beacon = NULL;
7902
566bfe5a 7903 /* Tell mac80211 our characteristics */
605a0bd6 7904 hw->flags = IEEE80211_HW_SIGNAL_DBM |
566bfe5a 7905 IEEE80211_HW_NOISE_DBM;
b481de9c 7906
f59ac048
LR		 7907 hw->wiphy->interface_modes =
7908 BIT(NL80211_IFTYPE_AP) |
7909 BIT(NL80211_IFTYPE_STATION) |
7910 BIT(NL80211_IFTYPE_ADHOC);
7911
6440adb5 7912 /* 4 EDCA QOS priorities */
b481de9c
ZY		 7913 hw->queues = 4;
7914
7915 spin_lock_init(&priv->lock);
7916 spin_lock_init(&priv->power_data.lock);
7917 spin_lock_init(&priv->sta_lock);
7918 spin_lock_init(&priv->hcmd_lock);
7919
b481de9c
ZY		 7920 INIT_LIST_HEAD(&priv->free_frames);
7921
7922 mutex_init(&priv->mutex);
7923 if (pci_enable_device(pdev)) {
7924 err = -ENODEV;
7925 goto out_ieee80211_free_hw;
7926 }
7927
7928 pci_set_master(pdev);
7929
6440adb5 7930 /* Clear the driver's (not device's) station table */
bb8c093b 7931 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 7932
7933 priv->data_retry_limit = -1;
7934 priv->ieee_channels = NULL;
7935 priv->ieee_rates = NULL;
8318d78a 7936 priv->band = IEEE80211_BAND_2GHZ;
b481de9c
ZY		 7937
7938 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
7939 if (!err)
7940 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
7941 if (err) {
7942 printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
7943 goto out_pci_disable_device;
7944 }
7945
7946 pci_set_drvdata(pdev, priv);
7947 err = pci_request_regions(pdev, DRV_NAME);
7948 if (err)
7949 goto out_pci_disable_device;
6440adb5 7950
b481de9c
ZY		 7951 /* We disable the RETRY_TIMEOUT register (0x41) to keep
7952 * PCI Tx retries from interfering with C3 CPU state */
7953 pci_write_config_byte(pdev, 0x41, 0x00);
6440adb5 7954
b481de9c
ZY		 7955 priv->hw_base = pci_iomap(pdev, 0, 0);
7956 if (!priv->hw_base) {
7957 err = -ENODEV;
7958 goto out_pci_release_regions;
7959 }
7960
7961 IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
7962 (unsigned long long) pci_resource_len(pdev, 0));
7963 IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
7964
7965 /* Initialize module parameter values here */
7966
6440adb5 7967 /* Disable radio (SW RF KILL) via parameter when loading driver */
bb8c093b 7968 if (iwl3945_param_disable) {
b481de9c
ZY		 7969 set_bit(STATUS_RF_KILL_SW, &priv->status);
7970 IWL_DEBUG_INFO("Radio disabled.\n");
7971 }
7972
05c914fe 7973 priv->iw_mode = NL80211_IFTYPE_STATION;
b481de9c 7974
b481de9c 7975 printk(KERN_INFO DRV_NAME
82b9a121 7976 ": Detected Intel Wireless WiFi Link %s\n", priv->cfg->name);
b481de9c
ZY		 7977
7978 /* Device-specific setup */
bb8c093b 7979 if (iwl3945_hw_set_hw_setting(priv)) {
b481de9c 7980 IWL_ERROR("failed to set hw settings\n");
b481de9c
ZY		 7981 goto out_iounmap;
7982 }
7983
bb8c093b 7984 if (iwl3945_param_qos_enable)
b481de9c
ZY		 7985 priv->qos_data.qos_enable = 1;
7986
bb8c093b 7987 iwl3945_reset_qos(priv);
b481de9c
ZY		 7988
7989 priv->qos_data.qos_active = 0;
7990 priv->qos_data.qos_cap.val = 0;
b481de9c 7991
8318d78a 7992 iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
bb8c093b
CH		 7993 iwl3945_setup_deferred_work(priv);
7994 iwl3945_setup_rx_handlers(priv);
b481de9c
ZY		 7995
7996 priv->rates_mask = IWL_RATES_MASK;
7997 /* If power management is turned on, default to AC mode */
7998 priv->power_mode = IWL_POWER_AC;
7999 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
8000
0359facc 8001 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 8002 iwl3945_disable_interrupts(priv);
0359facc 8003 spin_unlock_irqrestore(&priv->lock, flags);
49df2b33 8004
bb8c093b 8005 err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c
ZY		 8006 if (err) {
8007 IWL_ERROR("failed to create sysfs device attributes\n");
b481de9c
ZY		 8008 goto out_release_irq;
8009 }
8010
5a66926a
ZY		 8011 /* nic init */
8012 iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
3ac7f146
TW		 8013 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
8014
8015 iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
8016 err = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
8017 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
8018 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
8019 if (err < 0) {
8020 IWL_DEBUG_INFO("Failed to init the card\n");
5a66926a 8021 goto out_remove_sysfs;
3ac7f146 8022 }
5a66926a
ZY		 8023 /* Read the EEPROM */
8024 err = iwl3945_eeprom_init(priv);
b481de9c 8025 if (err) {
5a66926a
ZY		 8026 IWL_ERROR("Unable to init EEPROM\n");
8027 goto out_remove_sysfs;
b481de9c 8028 }
5a66926a
ZY		 8029 /* MAC Address location in EEPROM same for 3945/4965 */
8030 get_eeprom_mac(priv, priv->mac_addr);
e174961c 8031 IWL_DEBUG_INFO("MAC address: %pM\n", priv->mac_addr);
5a66926a 8032 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
b481de9c 8033
849e0dce
RC		 8034 err = iwl3945_init_channel_map(priv);
8035 if (err) {
8036 IWL_ERROR("initializing regulatory failed: %d\n", err);
8037 goto out_remove_sysfs;
8038 }
8039
8040 err = iwl3945_init_geos(priv);
8041 if (err) {
8042 IWL_ERROR("initializing geos failed: %d\n", err);
8043 goto out_free_channel_map;
8044 }
849e0dce 8045
5a66926a
ZY		 8046 err = ieee80211_register_hw(priv->hw);
8047 if (err) {
8048 IWL_ERROR("Failed to register network device (error %d)\n", err);
849e0dce 8049 goto out_free_geos;
5a66926a 8050 }
b481de9c 8051
5a66926a
ZY		 8052 priv->hw->conf.beacon_int = 100;
8053 priv->mac80211_registered = 1;
8054 pci_save_state(pdev);
8055 pci_disable_device(pdev);
b481de9c 8056
ebef2008
AK		 8057 err = iwl3945_rfkill_init(priv);
8058 if (err)
8059 IWL_ERROR("Unable to initialize RFKILL system. "
8060 "Ignoring error: %d\n", err);
8061
b481de9c
ZY		 8062 return 0;
8063
849e0dce
RC		 8064 out_free_geos:
8065 iwl3945_free_geos(priv);
8066 out_free_channel_map:
8067 iwl3945_free_channel_map(priv);
5a66926a 8068 out_remove_sysfs:
bb8c093b 8069 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c
ZY		 8070
8071 out_release_irq:
b481de9c
ZY		 8072 destroy_workqueue(priv->workqueue);
8073 priv->workqueue = NULL;
bb8c093b 8074 iwl3945_unset_hw_setting(priv);
b481de9c
ZY		 8075
8076 out_iounmap:
8077 pci_iounmap(pdev, priv->hw_base);
8078 out_pci_release_regions:
8079 pci_release_regions(pdev);
8080 out_pci_disable_device:
8081 pci_disable_device(pdev);
8082 pci_set_drvdata(pdev, NULL);
8083 out_ieee80211_free_hw:
8084 ieee80211_free_hw(priv->hw);
8085 out:
8086 return err;
8087}
8088
c83dbf68 8089static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
b481de9c 8090{
bb8c093b 8091 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
0359facc 8092 unsigned long flags;
b481de9c
ZY		 8093
8094 if (!priv)
8095 return;
8096
8097 IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
8098
b481de9c 8099 set_bit(STATUS_EXIT_PENDING, &priv->status);
b24d22b1 8100
bb8c093b 8101 iwl3945_down(priv);
b481de9c 8102
0359facc
MA		 8103 /* make sure we flush any pending irq or
8104 * tasklet for the driver
8105 */
8106 spin_lock_irqsave(&priv->lock, flags);
8107 iwl3945_disable_interrupts(priv);
8108 spin_unlock_irqrestore(&priv->lock, flags);
8109
8110 iwl_synchronize_irq(priv);
8111
bb8c093b 8112 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 8113
ebef2008 8114 iwl3945_rfkill_unregister(priv);
bb8c093b 8115 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY		 8116
8117 if (priv->rxq.bd)
bb8c093b
CH		 8118 iwl3945_rx_queue_free(priv, &priv->rxq);
8119 iwl3945_hw_txq_ctx_free(priv);
b481de9c 8120
bb8c093b
CH		 8121 iwl3945_unset_hw_setting(priv);
8122 iwl3945_clear_stations_table(priv);
b481de9c 8123
3ac7f146 8124 if (priv->mac80211_registered)
b481de9c 8125 ieee80211_unregister_hw(priv->hw);
b481de9c 8126
6ef89d0a
MA		 8127 /*netif_stop_queue(dev); */
8128 flush_workqueue(priv->workqueue);
8129
bb8c093b 8130 /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
b481de9c
ZY		 8131 * priv->workqueue... so we can't take down the workqueue
8132 * until now... */
8133 destroy_workqueue(priv->workqueue);
8134 priv->workqueue = NULL;
8135
b481de9c
ZY		 8136 pci_iounmap(pdev, priv->hw_base);
8137 pci_release_regions(pdev);
8138 pci_disable_device(pdev);
8139 pci_set_drvdata(pdev, NULL);
8140
849e0dce
RC		 8141 iwl3945_free_channel_map(priv);
8142 iwl3945_free_geos(priv);
261415f7 8143 kfree(priv->scan);
b481de9c
ZY		 8144 if (priv->ibss_beacon)
8145 dev_kfree_skb(priv->ibss_beacon);
8146
8147 ieee80211_free_hw(priv->hw);
8148}
8149
8150#ifdef CONFIG_PM
8151
bb8c093b 8152static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
b481de9c 8153{
bb8c093b 8154 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c 8155
e655b9f0
ZY		 8156 if (priv->is_open) {
8157 set_bit(STATUS_IN_SUSPEND, &priv->status);
8158 iwl3945_mac_stop(priv->hw);
8159 priv->is_open = 1;
8160 }
b481de9c 8161
b481de9c
ZY		 8162 pci_set_power_state(pdev, PCI_D3hot);
8163
b481de9c
ZY		 8164 return 0;
8165}
8166
bb8c093b 8167static int iwl3945_pci_resume(struct pci_dev *pdev)
b481de9c 8168{
bb8c093b 8169 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c 8170
b481de9c 8171 pci_set_power_state(pdev, PCI_D0);
b481de9c 8172
e655b9f0
ZY		 8173 if (priv->is_open)
8174 iwl3945_mac_start(priv->hw);
b481de9c 8175
e655b9f0 8176 clear_bit(STATUS_IN_SUSPEND, &priv->status);
b481de9c
ZY		 8177 return 0;
8178}
8179
8180#endif /* CONFIG_PM */
8181
ebef2008 8182/*************** RFKILL FUNCTIONS **********/
80fcc9e2 8183#ifdef CONFIG_IWL3945_RFKILL
ebef2008
AK		 8184/* software rf-kill from user */
8185static int iwl3945_rfkill_soft_rf_kill(void *data, enum rfkill_state state)
8186{
8187 struct iwl3945_priv *priv = data;
8188 int err = 0;
8189
80fcc9e2 8190 if (!priv->rfkill)
ebef2008
AK		 8191 return 0;
8192
8193 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
8194 return 0;
8195
8196 IWL_DEBUG_RF_KILL("we recieved soft RFKILL set to state %d\n", state);
8197 mutex_lock(&priv->mutex);
8198
8199 switch (state) {
acdfe9b4 8200 case RFKILL_STATE_UNBLOCKED:
80fcc9e2 8201 if (iwl3945_is_rfkill_hw(priv)) {
ebef2008 8202 err = -EBUSY;
80fcc9e2
AG		 8203 goto out_unlock;
8204 }
8205 iwl3945_radio_kill_sw(priv, 0);
ebef2008 8206 break;
acdfe9b4 8207 case RFKILL_STATE_SOFT_BLOCKED:
ebef2008 8208 iwl3945_radio_kill_sw(priv, 1);
ebef2008 8209 break;
acdfe9b4
ZY		 8210 default:
8211 IWL_WARNING("we recieved unexpected RFKILL state %d\n", state);
8212 break;
ebef2008 8213 }
80fcc9e2 8214out_unlock:
ebef2008
AK		 8215 mutex_unlock(&priv->mutex);
8216
8217 return err;
8218}
8219
8220int iwl3945_rfkill_init(struct iwl3945_priv *priv)
8221{
8222 struct device *device = wiphy_dev(priv->hw->wiphy);
8223 int ret = 0;
8224
8225 BUG_ON(device == NULL);
8226
8227 IWL_DEBUG_RF_KILL("Initializing RFKILL.\n");
80fcc9e2
AG		 8228 priv->rfkill = rfkill_allocate(device, RFKILL_TYPE_WLAN);
8229 if (!priv->rfkill) {
ebef2008
AK		 8230 IWL_ERROR("Unable to allocate rfkill device.\n");
8231 ret = -ENOMEM;
8232 goto error;
8233 }
8234
80fcc9e2
AG		 8235 priv->rfkill->name = priv->cfg->name;
8236 priv->rfkill->data = priv;
8237 priv->rfkill->state = RFKILL_STATE_UNBLOCKED;
8238 priv->rfkill->toggle_radio = iwl3945_rfkill_soft_rf_kill;
8239 priv->rfkill->user_claim_unsupported = 1;
ebef2008 8240
80fcc9e2
AG		 8241 priv->rfkill->dev.class->suspend = NULL;
8242 priv->rfkill->dev.class->resume = NULL;
ebef2008 8243
80fcc9e2 8244 ret = rfkill_register(priv->rfkill);
ebef2008
AK		 8245 if (ret) {
8246 IWL_ERROR("Unable to register rfkill: %d\n", ret);
80fcc9e2 8247 goto freed_rfkill;
ebef2008
AK		 8248 }
8249
8250 IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
8251 return ret;
8252
ebef2008 8253freed_rfkill:
80fcc9e2
AG		 8254 if (priv->rfkill != NULL)
8255 rfkill_free(priv->rfkill);
8256 priv->rfkill = NULL;
ebef2008
AK		 8257
8258error:
8259 IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
8260 return ret;
8261}
8262
8263void iwl3945_rfkill_unregister(struct iwl3945_priv *priv)
8264{
80fcc9e2
AG		 8265 if (priv->rfkill)
8266 rfkill_unregister(priv->rfkill);
ebef2008 8267
80fcc9e2 8268 priv->rfkill = NULL;
ebef2008
AK		 8269}
8270
8271/* set rf-kill to the right state. */
8272void iwl3945_rfkill_set_hw_state(struct iwl3945_priv *priv)
8273{
8274
80fcc9e2
AG		 8275 if (!priv->rfkill)
8276 return;
8277
8278 if (iwl3945_is_rfkill_hw(priv)) {
8279 rfkill_force_state(priv->rfkill, RFKILL_STATE_HARD_BLOCKED);
ebef2008 8280 return;
80fcc9e2 8281 }
ebef2008 8282
80fcc9e2
AG		 8283 if (!iwl3945_is_rfkill_sw(priv))
8284 rfkill_force_state(priv->rfkill, RFKILL_STATE_UNBLOCKED);
ebef2008 8285 else
80fcc9e2 8286 rfkill_force_state(priv->rfkill, RFKILL_STATE_SOFT_BLOCKED);
ebef2008
AK		 8287}
8288#endif
8289
b481de9c
ZY		 8290/*****************************************************************************
8291 *
8292 * driver and module entry point
8293 *
8294 *****************************************************************************/
8295
bb8c093b 8296static struct pci_driver iwl3945_driver = {
b481de9c 8297 .name = DRV_NAME,
bb8c093b
CH		 8298 .id_table = iwl3945_hw_card_ids,
8299 .probe = iwl3945_pci_probe,
8300 .remove = __devexit_p(iwl3945_pci_remove),
b481de9c 8301#ifdef CONFIG_PM
bb8c093b
CH		 8302 .suspend = iwl3945_pci_suspend,
8303 .resume = iwl3945_pci_resume,
b481de9c
ZY		 8304#endif
8305};
8306
bb8c093b 8307static int __init iwl3945_init(void)
b481de9c
ZY		 8308{
8309
8310 int ret;
8311 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
8312 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2
RC		 8313
8314 ret = iwl3945_rate_control_register();
8315 if (ret) {
8316 IWL_ERROR("Unable to register rate control algorithm: %d\n", ret);
8317 return ret;
8318 }
8319
bb8c093b 8320 ret = pci_register_driver(&iwl3945_driver);
b481de9c
ZY		 8321 if (ret) {
8322 IWL_ERROR("Unable to initialize PCI module\n");
897e1cf2 8323 goto error_register;
b481de9c 8324 }
c8b0e6e1 8325#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8326 ret = driver_create_file(&iwl3945_driver.driver, &driver_attr_debug_level);
b481de9c
ZY		 8327 if (ret) {
8328 IWL_ERROR("Unable to create driver sysfs file\n");
897e1cf2 8329 goto error_debug;
b481de9c
ZY		 8330 }
8331#endif
8332
8333 return ret;
897e1cf2
RC		 8334
8335#ifdef CONFIG_IWL3945_DEBUG
8336error_debug:
8337 pci_unregister_driver(&iwl3945_driver);
8338#endif
8339error_register:
8340 iwl3945_rate_control_unregister();
8341 return ret;
b481de9c
ZY		 8342}
8343
bb8c093b 8344static void __exit iwl3945_exit(void)
b481de9c 8345{
c8b0e6e1 8346#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8347 driver_remove_file(&iwl3945_driver.driver, &driver_attr_debug_level);
b481de9c 8348#endif
bb8c093b 8349 pci_unregister_driver(&iwl3945_driver);
897e1cf2 8350 iwl3945_rate_control_unregister();
b481de9c
ZY		 8351}
8352
25cb6cad
ZY		 8353MODULE_FIRMWARE("iwlwifi-3945" IWL3945_UCODE_API ".ucode");
8354
bb8c093b 8355module_param_named(antenna, iwl3945_param_antenna, int, 0444);
b481de9c 8356MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
bb8c093b 8357module_param_named(disable, iwl3945_param_disable, int, 0444);
b481de9c 8358MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
bb8c093b 8359module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444);
b481de9c
ZY		 8360MODULE_PARM_DESC(hwcrypto,
8361 "using hardware crypto engine (default 0 [software])\n");
bb8c093b 8362module_param_named(debug, iwl3945_param_debug, int, 0444);
b481de9c 8363MODULE_PARM_DESC(debug, "debug output mask");
bb8c093b 8364module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444);
b481de9c
ZY		 8365MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
8366
bb8c093b 8367module_param_named(queues_num, iwl3945_param_queues_num, int, 0444);
b481de9c
ZY		 8368MODULE_PARM_DESC(queues_num, "number of hw queues.");
8369
8370/* QoS */
bb8c093b 8371module_param_named(qos_enable, iwl3945_param_qos_enable, int, 0444);
b481de9c
ZY		 8372MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
8373
bb8c093b
CH		 8374module_exit(iwl3945_exit);
8375module_init(iwl3945_init);
Linux kernel - Deliverables
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