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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
eb7ae89c | 3 | * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
25 | * James P. Ketrenos <ipw2100-admin@linux.intel.com> | |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
b481de9c ZY |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/version.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/pci.h> | |
35 | #include <linux/dma-mapping.h> | |
36 | #include <linux/delay.h> | |
37 | #include <linux/skbuff.h> | |
38 | #include <linux/netdevice.h> | |
39 | #include <linux/wireless.h> | |
40 | #include <linux/firmware.h> | |
b481de9c ZY |
41 | #include <linux/etherdevice.h> |
42 | #include <linux/if_arp.h> | |
43 | ||
b481de9c ZY |
44 | #include <net/mac80211.h> |
45 | ||
46 | #include <asm/div64.h> | |
47 | ||
6bc913bd | 48 | #include "iwl-eeprom.h" |
b481de9c | 49 | #include "iwl-4965.h" |
fee1247a | 50 | #include "iwl-core.h" |
3395f6e9 | 51 | #include "iwl-io.h" |
b481de9c | 52 | #include "iwl-helpers.h" |
6974e363 | 53 | #include "iwl-sta.h" |
b481de9c | 54 | |
c79dd5b5 | 55 | static int iwl4965_tx_queue_update_write_ptr(struct iwl_priv *priv, |
bb8c093b | 56 | struct iwl4965_tx_queue *txq); |
416e1438 | 57 | |
b481de9c ZY |
58 | /****************************************************************************** |
59 | * | |
60 | * module boiler plate | |
61 | * | |
62 | ******************************************************************************/ | |
63 | ||
b481de9c ZY |
64 | /* |
65 | * module name, copyright, version, etc. | |
66 | * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk | |
67 | */ | |
68 | ||
69 | #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link 4965AGN driver for Linux" | |
70 | ||
0a6857e7 | 71 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
72 | #define VD "d" |
73 | #else | |
74 | #define VD | |
75 | #endif | |
76 | ||
c8b0e6e1 | 77 | #ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT |
b481de9c ZY |
78 | #define VS "s" |
79 | #else | |
80 | #define VS | |
81 | #endif | |
82 | ||
df48c323 | 83 | #define DRV_VERSION IWLWIFI_VERSION VD VS |
b481de9c | 84 | |
b481de9c ZY |
85 | |
86 | MODULE_DESCRIPTION(DRV_DESCRIPTION); | |
87 | MODULE_VERSION(DRV_VERSION); | |
88 | MODULE_AUTHOR(DRV_COPYRIGHT); | |
89 | MODULE_LICENSE("GPL"); | |
90 | ||
91 | __le16 *ieee80211_get_qos_ctrl(struct ieee80211_hdr *hdr) | |
92 | { | |
93 | u16 fc = le16_to_cpu(hdr->frame_control); | |
94 | int hdr_len = ieee80211_get_hdrlen(fc); | |
95 | ||
96 | if ((fc & 0x00cc) == (IEEE80211_STYPE_QOS_DATA | IEEE80211_FTYPE_DATA)) | |
97 | return (__le16 *) ((u8 *) hdr + hdr_len - QOS_CONTROL_LEN); | |
98 | return NULL; | |
99 | } | |
100 | ||
8318d78a | 101 | static const struct ieee80211_supported_band *iwl4965_get_hw_mode( |
c79dd5b5 | 102 | struct iwl_priv *priv, enum ieee80211_band band) |
b481de9c | 103 | { |
8318d78a | 104 | return priv->hw->wiphy->bands[band]; |
b481de9c ZY |
105 | } |
106 | ||
bb8c093b | 107 | static int iwl4965_is_empty_essid(const char *essid, int essid_len) |
b481de9c ZY |
108 | { |
109 | /* Single white space is for Linksys APs */ | |
110 | if (essid_len == 1 && essid[0] == ' ') | |
111 | return 1; | |
112 | ||
113 | /* Otherwise, if the entire essid is 0, we assume it is hidden */ | |
114 | while (essid_len) { | |
115 | essid_len--; | |
116 | if (essid[essid_len] != '\0') | |
117 | return 0; | |
118 | } | |
119 | ||
120 | return 1; | |
121 | } | |
122 | ||
bb8c093b | 123 | static const char *iwl4965_escape_essid(const char *essid, u8 essid_len) |
b481de9c ZY |
124 | { |
125 | static char escaped[IW_ESSID_MAX_SIZE * 2 + 1]; | |
126 | const char *s = essid; | |
127 | char *d = escaped; | |
128 | ||
bb8c093b | 129 | if (iwl4965_is_empty_essid(essid, essid_len)) { |
b481de9c ZY |
130 | memcpy(escaped, "<hidden>", sizeof("<hidden>")); |
131 | return escaped; | |
132 | } | |
133 | ||
134 | essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE); | |
135 | while (essid_len--) { | |
136 | if (*s == '\0') { | |
137 | *d++ = '\\'; | |
138 | *d++ = '0'; | |
139 | s++; | |
140 | } else | |
141 | *d++ = *s++; | |
142 | } | |
143 | *d = '\0'; | |
144 | return escaped; | |
145 | } | |
146 | ||
b481de9c ZY |
147 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
148 | * DMA services | |
149 | * | |
150 | * Theory of operation | |
151 | * | |
6440adb5 CB |
152 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer |
153 | * of buffer descriptors, each of which points to one or more data buffers for | |
154 | * the device to read from or fill. Driver and device exchange status of each | |
155 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
156 | * entries in each circular buffer, to protect against confusing empty and full | |
157 | * queue states. | |
158 | * | |
159 | * The device reads or writes the data in the queues via the device's several | |
160 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
b481de9c ZY |
161 | * |
162 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
163 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
164 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
165 | * Tx queue resumed. | |
166 | * | |
6440adb5 CB |
167 | * The 4965 operates with up to 17 queues: One receive queue, one transmit |
168 | * queue (#4) for sending commands to the device firmware, and 15 other | |
169 | * Tx queues that may be mapped to prioritized Tx DMA/FIFO channels. | |
e3851447 BC |
170 | * |
171 | * See more detailed info in iwl-4965-hw.h. | |
b481de9c ZY |
172 | ***************************************************/ |
173 | ||
fe01b477 | 174 | int iwl4965_queue_space(const struct iwl4965_queue *q) |
b481de9c | 175 | { |
fc4b6853 | 176 | int s = q->read_ptr - q->write_ptr; |
b481de9c | 177 | |
fc4b6853 | 178 | if (q->read_ptr > q->write_ptr) |
b481de9c ZY |
179 | s -= q->n_bd; |
180 | ||
181 | if (s <= 0) | |
182 | s += q->n_window; | |
183 | /* keep some reserve to not confuse empty and full situations */ | |
184 | s -= 2; | |
185 | if (s < 0) | |
186 | s = 0; | |
187 | return s; | |
188 | } | |
189 | ||
b481de9c | 190 | |
bb8c093b | 191 | static inline int x2_queue_used(const struct iwl4965_queue *q, int i) |
b481de9c | 192 | { |
fc4b6853 TW |
193 | return q->write_ptr > q->read_ptr ? |
194 | (i >= q->read_ptr && i < q->write_ptr) : | |
195 | !(i < q->read_ptr && i >= q->write_ptr); | |
b481de9c ZY |
196 | } |
197 | ||
bb8c093b | 198 | static inline u8 get_cmd_index(struct iwl4965_queue *q, u32 index, int is_huge) |
b481de9c | 199 | { |
6440adb5 | 200 | /* This is for scan command, the big buffer at end of command array */ |
b481de9c | 201 | if (is_huge) |
6440adb5 | 202 | return q->n_window; /* must be power of 2 */ |
b481de9c | 203 | |
6440adb5 | 204 | /* Otherwise, use normal size buffers */ |
b481de9c ZY |
205 | return index & (q->n_window - 1); |
206 | } | |
207 | ||
6440adb5 CB |
208 | /** |
209 | * iwl4965_queue_init - Initialize queue's high/low-water and read/write indexes | |
210 | */ | |
c79dd5b5 | 211 | static int iwl4965_queue_init(struct iwl_priv *priv, struct iwl4965_queue *q, |
b481de9c ZY |
212 | int count, int slots_num, u32 id) |
213 | { | |
214 | q->n_bd = count; | |
215 | q->n_window = slots_num; | |
216 | q->id = id; | |
217 | ||
c54b679d TW |
218 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap |
219 | * and iwl_queue_dec_wrap are broken. */ | |
b481de9c ZY |
220 | BUG_ON(!is_power_of_2(count)); |
221 | ||
222 | /* slots_num must be power-of-two size, otherwise | |
223 | * get_cmd_index is broken. */ | |
224 | BUG_ON(!is_power_of_2(slots_num)); | |
225 | ||
226 | q->low_mark = q->n_window / 4; | |
227 | if (q->low_mark < 4) | |
228 | q->low_mark = 4; | |
229 | ||
230 | q->high_mark = q->n_window / 8; | |
231 | if (q->high_mark < 2) | |
232 | q->high_mark = 2; | |
233 | ||
fc4b6853 | 234 | q->write_ptr = q->read_ptr = 0; |
b481de9c ZY |
235 | |
236 | return 0; | |
237 | } | |
238 | ||
6440adb5 CB |
239 | /** |
240 | * iwl4965_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue | |
241 | */ | |
c79dd5b5 | 242 | static int iwl4965_tx_queue_alloc(struct iwl_priv *priv, |
bb8c093b | 243 | struct iwl4965_tx_queue *txq, u32 id) |
b481de9c ZY |
244 | { |
245 | struct pci_dev *dev = priv->pci_dev; | |
246 | ||
6440adb5 CB |
247 | /* Driver private data, only for Tx (not command) queues, |
248 | * not shared with device. */ | |
b481de9c ZY |
249 | if (id != IWL_CMD_QUEUE_NUM) { |
250 | txq->txb = kmalloc(sizeof(txq->txb[0]) * | |
251 | TFD_QUEUE_SIZE_MAX, GFP_KERNEL); | |
252 | if (!txq->txb) { | |
01ebd063 | 253 | IWL_ERROR("kmalloc for auxiliary BD " |
b481de9c ZY |
254 | "structures failed\n"); |
255 | goto error; | |
256 | } | |
257 | } else | |
258 | txq->txb = NULL; | |
259 | ||
6440adb5 CB |
260 | /* Circular buffer of transmit frame descriptors (TFDs), |
261 | * shared with device */ | |
b481de9c ZY |
262 | txq->bd = pci_alloc_consistent(dev, |
263 | sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX, | |
264 | &txq->q.dma_addr); | |
265 | ||
266 | if (!txq->bd) { | |
267 | IWL_ERROR("pci_alloc_consistent(%zd) failed\n", | |
268 | sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX); | |
269 | goto error; | |
270 | } | |
271 | txq->q.id = id; | |
272 | ||
273 | return 0; | |
274 | ||
275 | error: | |
276 | if (txq->txb) { | |
277 | kfree(txq->txb); | |
278 | txq->txb = NULL; | |
279 | } | |
280 | ||
281 | return -ENOMEM; | |
282 | } | |
283 | ||
8b6eaea8 CB |
284 | /** |
285 | * iwl4965_tx_queue_init - Allocate and initialize one tx/cmd queue | |
286 | */ | |
c79dd5b5 | 287 | int iwl4965_tx_queue_init(struct iwl_priv *priv, |
bb8c093b | 288 | struct iwl4965_tx_queue *txq, int slots_num, u32 txq_id) |
b481de9c ZY |
289 | { |
290 | struct pci_dev *dev = priv->pci_dev; | |
291 | int len; | |
292 | int rc = 0; | |
293 | ||
8b6eaea8 CB |
294 | /* |
295 | * Alloc buffer array for commands (Tx or other types of commands). | |
296 | * For the command queue (#4), allocate command space + one big | |
297 | * command for scan, since scan command is very huge; the system will | |
298 | * not have two scans at the same time, so only one is needed. | |
bb54244b | 299 | * For normal Tx queues (all other queues), no super-size command |
8b6eaea8 CB |
300 | * space is needed. |
301 | */ | |
857485c0 | 302 | len = sizeof(struct iwl_cmd) * slots_num; |
b481de9c ZY |
303 | if (txq_id == IWL_CMD_QUEUE_NUM) |
304 | len += IWL_MAX_SCAN_SIZE; | |
305 | txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd); | |
306 | if (!txq->cmd) | |
307 | return -ENOMEM; | |
308 | ||
8b6eaea8 | 309 | /* Alloc driver data array and TFD circular buffer */ |
bb8c093b | 310 | rc = iwl4965_tx_queue_alloc(priv, txq, txq_id); |
b481de9c ZY |
311 | if (rc) { |
312 | pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd); | |
313 | ||
314 | return -ENOMEM; | |
315 | } | |
316 | txq->need_update = 0; | |
317 | ||
318 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise | |
c54b679d | 319 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ |
b481de9c | 320 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); |
8b6eaea8 CB |
321 | |
322 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
bb8c093b | 323 | iwl4965_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id); |
b481de9c | 324 | |
8b6eaea8 | 325 | /* Tell device where to find queue */ |
bb8c093b | 326 | iwl4965_hw_tx_queue_init(priv, txq); |
b481de9c ZY |
327 | |
328 | return 0; | |
329 | } | |
330 | ||
331 | /** | |
bb8c093b | 332 | * iwl4965_tx_queue_free - Deallocate DMA queue. |
b481de9c ZY |
333 | * @txq: Transmit queue to deallocate. |
334 | * | |
335 | * Empty queue by removing and destroying all BD's. | |
6440adb5 CB |
336 | * Free all buffers. |
337 | * 0-fill, but do not free "txq" descriptor structure. | |
b481de9c | 338 | */ |
c79dd5b5 | 339 | void iwl4965_tx_queue_free(struct iwl_priv *priv, struct iwl4965_tx_queue *txq) |
b481de9c | 340 | { |
bb8c093b | 341 | struct iwl4965_queue *q = &txq->q; |
b481de9c ZY |
342 | struct pci_dev *dev = priv->pci_dev; |
343 | int len; | |
344 | ||
345 | if (q->n_bd == 0) | |
346 | return; | |
347 | ||
348 | /* first, empty all BD's */ | |
fc4b6853 | 349 | for (; q->write_ptr != q->read_ptr; |
c54b679d | 350 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) |
bb8c093b | 351 | iwl4965_hw_txq_free_tfd(priv, txq); |
b481de9c | 352 | |
857485c0 | 353 | len = sizeof(struct iwl_cmd) * q->n_window; |
b481de9c ZY |
354 | if (q->id == IWL_CMD_QUEUE_NUM) |
355 | len += IWL_MAX_SCAN_SIZE; | |
356 | ||
6440adb5 | 357 | /* De-alloc array of command/tx buffers */ |
b481de9c ZY |
358 | pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd); |
359 | ||
6440adb5 | 360 | /* De-alloc circular buffer of TFDs */ |
b481de9c | 361 | if (txq->q.n_bd) |
bb8c093b | 362 | pci_free_consistent(dev, sizeof(struct iwl4965_tfd_frame) * |
b481de9c ZY |
363 | txq->q.n_bd, txq->bd, txq->q.dma_addr); |
364 | ||
6440adb5 | 365 | /* De-alloc array of per-TFD driver data */ |
b481de9c ZY |
366 | if (txq->txb) { |
367 | kfree(txq->txb); | |
368 | txq->txb = NULL; | |
369 | } | |
370 | ||
6440adb5 | 371 | /* 0-fill queue descriptor structure */ |
b481de9c ZY |
372 | memset(txq, 0, sizeof(*txq)); |
373 | } | |
374 | ||
bb8c093b | 375 | const u8 iwl4965_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; |
b481de9c ZY |
376 | |
377 | /*************** STATION TABLE MANAGEMENT **** | |
9fbab516 | 378 | * mac80211 should be examined to determine if sta_info is duplicating |
b481de9c ZY |
379 | * the functionality provided here |
380 | */ | |
381 | ||
382 | /**************************************************************/ | |
383 | ||
01ebd063 | 384 | #if 0 /* temporary disable till we add real remove station */ |
6440adb5 CB |
385 | /** |
386 | * iwl4965_remove_station - Remove driver's knowledge of station. | |
387 | * | |
388 | * NOTE: This does not remove station from device's station table. | |
389 | */ | |
c79dd5b5 | 390 | static u8 iwl4965_remove_station(struct iwl_priv *priv, const u8 *addr, int is_ap) |
b481de9c ZY |
391 | { |
392 | int index = IWL_INVALID_STATION; | |
393 | int i; | |
394 | unsigned long flags; | |
395 | ||
396 | spin_lock_irqsave(&priv->sta_lock, flags); | |
397 | ||
398 | if (is_ap) | |
399 | index = IWL_AP_ID; | |
400 | else if (is_broadcast_ether_addr(addr)) | |
401 | index = priv->hw_setting.bcast_sta_id; | |
402 | else | |
403 | for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) | |
404 | if (priv->stations[i].used && | |
405 | !compare_ether_addr(priv->stations[i].sta.sta.addr, | |
406 | addr)) { | |
407 | index = i; | |
408 | break; | |
409 | } | |
410 | ||
411 | if (unlikely(index == IWL_INVALID_STATION)) | |
412 | goto out; | |
413 | ||
414 | if (priv->stations[index].used) { | |
415 | priv->stations[index].used = 0; | |
416 | priv->num_stations--; | |
417 | } | |
418 | ||
419 | BUG_ON(priv->num_stations < 0); | |
420 | ||
421 | out: | |
422 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
423 | return 0; | |
424 | } | |
556f8db7 | 425 | #endif |
b481de9c | 426 | |
6440adb5 CB |
427 | /** |
428 | * iwl4965_add_station_flags - Add station to tables in driver and device | |
429 | */ | |
c79dd5b5 | 430 | u8 iwl4965_add_station_flags(struct iwl_priv *priv, const u8 *addr, |
67d62035 | 431 | int is_ap, u8 flags, void *ht_data) |
b481de9c ZY |
432 | { |
433 | int i; | |
434 | int index = IWL_INVALID_STATION; | |
bb8c093b | 435 | struct iwl4965_station_entry *station; |
b481de9c | 436 | unsigned long flags_spin; |
0795af57 | 437 | DECLARE_MAC_BUF(mac); |
b481de9c ZY |
438 | |
439 | spin_lock_irqsave(&priv->sta_lock, flags_spin); | |
440 | if (is_ap) | |
441 | index = IWL_AP_ID; | |
442 | else if (is_broadcast_ether_addr(addr)) | |
443 | index = priv->hw_setting.bcast_sta_id; | |
444 | else | |
445 | for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) { | |
446 | if (!compare_ether_addr(priv->stations[i].sta.sta.addr, | |
447 | addr)) { | |
448 | index = i; | |
449 | break; | |
450 | } | |
451 | ||
452 | if (!priv->stations[i].used && | |
453 | index == IWL_INVALID_STATION) | |
454 | index = i; | |
455 | } | |
456 | ||
457 | ||
9fbab516 BC |
458 | /* These two conditions have the same outcome, but keep them separate |
459 | since they have different meanings */ | |
b481de9c ZY |
460 | if (unlikely(index == IWL_INVALID_STATION)) { |
461 | spin_unlock_irqrestore(&priv->sta_lock, flags_spin); | |
462 | return index; | |
463 | } | |
464 | ||
465 | if (priv->stations[index].used && | |
466 | !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) { | |
467 | spin_unlock_irqrestore(&priv->sta_lock, flags_spin); | |
468 | return index; | |
469 | } | |
470 | ||
471 | ||
0795af57 | 472 | IWL_DEBUG_ASSOC("Add STA ID %d: %s\n", index, print_mac(mac, addr)); |
b481de9c ZY |
473 | station = &priv->stations[index]; |
474 | station->used = 1; | |
475 | priv->num_stations++; | |
476 | ||
6440adb5 | 477 | /* Set up the REPLY_ADD_STA command to send to device */ |
bb8c093b | 478 | memset(&station->sta, 0, sizeof(struct iwl4965_addsta_cmd)); |
b481de9c ZY |
479 | memcpy(station->sta.sta.addr, addr, ETH_ALEN); |
480 | station->sta.mode = 0; | |
481 | station->sta.sta.sta_id = index; | |
482 | station->sta.station_flags = 0; | |
483 | ||
c8b0e6e1 | 484 | #ifdef CONFIG_IWL4965_HT |
b481de9c ZY |
485 | /* BCAST station and IBSS stations do not work in HT mode */ |
486 | if (index != priv->hw_setting.bcast_sta_id && | |
487 | priv->iw_mode != IEEE80211_IF_TYPE_IBSS) | |
67d62035 RR |
488 | iwl4965_set_ht_add_station(priv, index, |
489 | (struct ieee80211_ht_info *) ht_data); | |
c8b0e6e1 | 490 | #endif /*CONFIG_IWL4965_HT*/ |
b481de9c ZY |
491 | |
492 | spin_unlock_irqrestore(&priv->sta_lock, flags_spin); | |
6440adb5 CB |
493 | |
494 | /* Add station to device's station table */ | |
bb8c093b | 495 | iwl4965_send_add_station(priv, &station->sta, flags); |
b481de9c ZY |
496 | return index; |
497 | ||
498 | } | |
499 | ||
b481de9c | 500 | |
b481de9c ZY |
501 | |
502 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ | |
503 | ||
b481de9c | 504 | /** |
bb8c093b | 505 | * iwl4965_enqueue_hcmd - enqueue a uCode command |
b481de9c ZY |
506 | * @priv: device private data point |
507 | * @cmd: a point to the ucode command structure | |
508 | * | |
509 | * The function returns < 0 values to indicate the operation is | |
510 | * failed. On success, it turns the index (> 0) of command in the | |
511 | * command queue. | |
512 | */ | |
857485c0 | 513 | int iwl4965_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd) |
b481de9c | 514 | { |
bb8c093b CH |
515 | struct iwl4965_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM]; |
516 | struct iwl4965_queue *q = &txq->q; | |
517 | struct iwl4965_tfd_frame *tfd; | |
b481de9c | 518 | u32 *control_flags; |
857485c0 | 519 | struct iwl_cmd *out_cmd; |
b481de9c ZY |
520 | u32 idx; |
521 | u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr)); | |
522 | dma_addr_t phys_addr; | |
523 | int ret; | |
524 | unsigned long flags; | |
525 | ||
526 | /* If any of the command structures end up being larger than | |
527 | * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then | |
528 | * we will need to increase the size of the TFD entries */ | |
529 | BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) && | |
530 | !(cmd->meta.flags & CMD_SIZE_HUGE)); | |
531 | ||
fee1247a | 532 | if (iwl_is_rfkill(priv)) { |
c342a1b9 GG |
533 | IWL_DEBUG_INFO("Not sending command - RF KILL"); |
534 | return -EIO; | |
535 | } | |
536 | ||
bb8c093b | 537 | if (iwl4965_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) { |
b481de9c ZY |
538 | IWL_ERROR("No space for Tx\n"); |
539 | return -ENOSPC; | |
540 | } | |
541 | ||
542 | spin_lock_irqsave(&priv->hcmd_lock, flags); | |
543 | ||
fc4b6853 | 544 | tfd = &txq->bd[q->write_ptr]; |
b481de9c ZY |
545 | memset(tfd, 0, sizeof(*tfd)); |
546 | ||
547 | control_flags = (u32 *) tfd; | |
548 | ||
fc4b6853 | 549 | idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE); |
b481de9c ZY |
550 | out_cmd = &txq->cmd[idx]; |
551 | ||
552 | out_cmd->hdr.cmd = cmd->id; | |
553 | memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta)); | |
554 | memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len); | |
555 | ||
556 | /* At this point, the out_cmd now has all of the incoming cmd | |
557 | * information */ | |
558 | ||
559 | out_cmd->hdr.flags = 0; | |
560 | out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) | | |
fc4b6853 | 561 | INDEX_TO_SEQ(q->write_ptr)); |
b481de9c ZY |
562 | if (out_cmd->meta.flags & CMD_SIZE_HUGE) |
563 | out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME); | |
564 | ||
565 | phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx + | |
857485c0 | 566 | offsetof(struct iwl_cmd, hdr); |
bb8c093b | 567 | iwl4965_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size); |
b481de9c ZY |
568 | |
569 | IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, " | |
570 | "%d bytes at %d[%d]:%d\n", | |
571 | get_cmd_string(out_cmd->hdr.cmd), | |
572 | out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence), | |
fc4b6853 | 573 | fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM); |
b481de9c ZY |
574 | |
575 | txq->need_update = 1; | |
6440adb5 CB |
576 | |
577 | /* Set up entry in queue's byte count circular buffer */ | |
e2a722eb | 578 | priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0); |
6440adb5 CB |
579 | |
580 | /* Increment and update queue's write index */ | |
c54b679d | 581 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); |
e2a722eb | 582 | ret = iwl4965_tx_queue_update_write_ptr(priv, txq); |
b481de9c ZY |
583 | |
584 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); | |
585 | return ret ? ret : idx; | |
586 | } | |
587 | ||
deb09c43 EG |
588 | static void iwl4965_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt) |
589 | { | |
590 | struct iwl4965_rxon_cmd *rxon = &priv->staging_rxon; | |
591 | ||
592 | if (hw_decrypt) | |
593 | rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK; | |
594 | else | |
595 | rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK; | |
596 | ||
597 | } | |
598 | ||
b481de9c | 599 | /** |
bb8c093b | 600 | * iwl4965_rxon_add_station - add station into station table. |
b481de9c ZY |
601 | * |
602 | * there is only one AP station with id= IWL_AP_ID | |
9fbab516 BC |
603 | * NOTE: mutex must be held before calling this fnction |
604 | */ | |
c79dd5b5 | 605 | static int iwl4965_rxon_add_station(struct iwl_priv *priv, |
b481de9c ZY |
606 | const u8 *addr, int is_ap) |
607 | { | |
556f8db7 | 608 | u8 sta_id; |
b481de9c | 609 | |
6440adb5 | 610 | /* Add station to device's station table */ |
67d62035 RR |
611 | #ifdef CONFIG_IWL4965_HT |
612 | struct ieee80211_conf *conf = &priv->hw->conf; | |
613 | struct ieee80211_ht_info *cur_ht_config = &conf->ht_conf; | |
614 | ||
615 | if ((is_ap) && | |
616 | (conf->flags & IEEE80211_CONF_SUPPORT_HT_MODE) && | |
617 | (priv->iw_mode == IEEE80211_IF_TYPE_STA)) | |
618 | sta_id = iwl4965_add_station_flags(priv, addr, is_ap, | |
619 | 0, cur_ht_config); | |
620 | else | |
621 | #endif /* CONFIG_IWL4965_HT */ | |
622 | sta_id = iwl4965_add_station_flags(priv, addr, is_ap, | |
623 | 0, NULL); | |
6440adb5 CB |
624 | |
625 | /* Set up default rate scaling table in device's station table */ | |
b481de9c ZY |
626 | iwl4965_add_station(priv, addr, is_ap); |
627 | ||
556f8db7 | 628 | return sta_id; |
b481de9c ZY |
629 | } |
630 | ||
b481de9c | 631 | /** |
bb8c093b | 632 | * iwl4965_check_rxon_cmd - validate RXON structure is valid |
b481de9c ZY |
633 | * |
634 | * NOTE: This is really only useful during development and can eventually | |
635 | * be #ifdef'd out once the driver is stable and folks aren't actively | |
636 | * making changes | |
637 | */ | |
bb8c093b | 638 | static int iwl4965_check_rxon_cmd(struct iwl4965_rxon_cmd *rxon) |
b481de9c ZY |
639 | { |
640 | int error = 0; | |
641 | int counter = 1; | |
642 | ||
643 | if (rxon->flags & RXON_FLG_BAND_24G_MSK) { | |
644 | error |= le32_to_cpu(rxon->flags & | |
645 | (RXON_FLG_TGJ_NARROW_BAND_MSK | | |
646 | RXON_FLG_RADAR_DETECT_MSK)); | |
647 | if (error) | |
648 | IWL_WARNING("check 24G fields %d | %d\n", | |
649 | counter++, error); | |
650 | } else { | |
651 | error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ? | |
652 | 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK); | |
653 | if (error) | |
654 | IWL_WARNING("check 52 fields %d | %d\n", | |
655 | counter++, error); | |
656 | error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK); | |
657 | if (error) | |
658 | IWL_WARNING("check 52 CCK %d | %d\n", | |
659 | counter++, error); | |
660 | } | |
661 | error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1; | |
662 | if (error) | |
663 | IWL_WARNING("check mac addr %d | %d\n", counter++, error); | |
664 | ||
665 | /* make sure basic rates 6Mbps and 1Mbps are supported */ | |
666 | error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) && | |
667 | ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0)); | |
668 | if (error) | |
669 | IWL_WARNING("check basic rate %d | %d\n", counter++, error); | |
670 | ||
671 | error |= (le16_to_cpu(rxon->assoc_id) > 2007); | |
672 | if (error) | |
673 | IWL_WARNING("check assoc id %d | %d\n", counter++, error); | |
674 | ||
675 | error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) | |
676 | == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)); | |
677 | if (error) | |
678 | IWL_WARNING("check CCK and short slot %d | %d\n", | |
679 | counter++, error); | |
680 | ||
681 | error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) | |
682 | == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)); | |
683 | if (error) | |
684 | IWL_WARNING("check CCK & auto detect %d | %d\n", | |
685 | counter++, error); | |
686 | ||
687 | error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK | | |
688 | RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK); | |
689 | if (error) | |
690 | IWL_WARNING("check TGG and auto detect %d | %d\n", | |
691 | counter++, error); | |
692 | ||
693 | if (error) | |
694 | IWL_WARNING("Tuning to channel %d\n", | |
695 | le16_to_cpu(rxon->channel)); | |
696 | ||
697 | if (error) { | |
bb8c093b | 698 | IWL_ERROR("Not a valid iwl4965_rxon_assoc_cmd field values\n"); |
b481de9c ZY |
699 | return -1; |
700 | } | |
701 | return 0; | |
702 | } | |
703 | ||
704 | /** | |
9fbab516 | 705 | * iwl4965_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed |
01ebd063 | 706 | * @priv: staging_rxon is compared to active_rxon |
b481de9c | 707 | * |
9fbab516 BC |
708 | * If the RXON structure is changing enough to require a new tune, |
709 | * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that | |
710 | * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required. | |
b481de9c | 711 | */ |
c79dd5b5 | 712 | static int iwl4965_full_rxon_required(struct iwl_priv *priv) |
b481de9c ZY |
713 | { |
714 | ||
715 | /* These items are only settable from the full RXON command */ | |
716 | if (!(priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) || | |
717 | compare_ether_addr(priv->staging_rxon.bssid_addr, | |
718 | priv->active_rxon.bssid_addr) || | |
719 | compare_ether_addr(priv->staging_rxon.node_addr, | |
720 | priv->active_rxon.node_addr) || | |
721 | compare_ether_addr(priv->staging_rxon.wlap_bssid_addr, | |
722 | priv->active_rxon.wlap_bssid_addr) || | |
723 | (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) || | |
724 | (priv->staging_rxon.channel != priv->active_rxon.channel) || | |
725 | (priv->staging_rxon.air_propagation != | |
726 | priv->active_rxon.air_propagation) || | |
727 | (priv->staging_rxon.ofdm_ht_single_stream_basic_rates != | |
728 | priv->active_rxon.ofdm_ht_single_stream_basic_rates) || | |
729 | (priv->staging_rxon.ofdm_ht_dual_stream_basic_rates != | |
730 | priv->active_rxon.ofdm_ht_dual_stream_basic_rates) || | |
731 | (priv->staging_rxon.rx_chain != priv->active_rxon.rx_chain) || | |
732 | (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id)) | |
733 | return 1; | |
734 | ||
735 | /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can | |
736 | * be updated with the RXON_ASSOC command -- however only some | |
737 | * flag transitions are allowed using RXON_ASSOC */ | |
738 | ||
739 | /* Check if we are not switching bands */ | |
740 | if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) != | |
741 | (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)) | |
742 | return 1; | |
743 | ||
744 | /* Check if we are switching association toggle */ | |
745 | if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) != | |
746 | (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) | |
747 | return 1; | |
748 | ||
749 | return 0; | |
750 | } | |
751 | ||
c79dd5b5 | 752 | static int iwl4965_send_rxon_assoc(struct iwl_priv *priv) |
b481de9c | 753 | { |
51dbfd1d | 754 | int ret = 0; |
bb8c093b | 755 | struct iwl4965_rxon_assoc_cmd rxon_assoc; |
bb8c093b CH |
756 | const struct iwl4965_rxon_cmd *rxon1 = &priv->staging_rxon; |
757 | const struct iwl4965_rxon_cmd *rxon2 = &priv->active_rxon; | |
b481de9c ZY |
758 | |
759 | if ((rxon1->flags == rxon2->flags) && | |
760 | (rxon1->filter_flags == rxon2->filter_flags) && | |
761 | (rxon1->cck_basic_rates == rxon2->cck_basic_rates) && | |
762 | (rxon1->ofdm_ht_single_stream_basic_rates == | |
763 | rxon2->ofdm_ht_single_stream_basic_rates) && | |
764 | (rxon1->ofdm_ht_dual_stream_basic_rates == | |
765 | rxon2->ofdm_ht_dual_stream_basic_rates) && | |
766 | (rxon1->rx_chain == rxon2->rx_chain) && | |
767 | (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) { | |
768 | IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n"); | |
769 | return 0; | |
770 | } | |
771 | ||
772 | rxon_assoc.flags = priv->staging_rxon.flags; | |
773 | rxon_assoc.filter_flags = priv->staging_rxon.filter_flags; | |
774 | rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates; | |
775 | rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates; | |
776 | rxon_assoc.reserved = 0; | |
777 | rxon_assoc.ofdm_ht_single_stream_basic_rates = | |
778 | priv->staging_rxon.ofdm_ht_single_stream_basic_rates; | |
779 | rxon_assoc.ofdm_ht_dual_stream_basic_rates = | |
780 | priv->staging_rxon.ofdm_ht_dual_stream_basic_rates; | |
781 | rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain; | |
782 | ||
51dbfd1d RC |
783 | ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC, |
784 | sizeof(rxon_assoc), &rxon_assoc, NULL); | |
785 | if (ret) | |
786 | return ret; | |
b481de9c | 787 | |
51dbfd1d | 788 | return ret; |
b481de9c ZY |
789 | } |
790 | ||
791 | /** | |
bb8c093b | 792 | * iwl4965_commit_rxon - commit staging_rxon to hardware |
b481de9c | 793 | * |
01ebd063 | 794 | * The RXON command in staging_rxon is committed to the hardware and |
b481de9c ZY |
795 | * the active_rxon structure is updated with the new data. This |
796 | * function correctly transitions out of the RXON_ASSOC_MSK state if | |
797 | * a HW tune is required based on the RXON structure changes. | |
798 | */ | |
c79dd5b5 | 799 | static int iwl4965_commit_rxon(struct iwl_priv *priv) |
b481de9c ZY |
800 | { |
801 | /* cast away the const for active_rxon in this function */ | |
bb8c093b | 802 | struct iwl4965_rxon_cmd *active_rxon = (void *)&priv->active_rxon; |
0795af57 | 803 | DECLARE_MAC_BUF(mac); |
b481de9c ZY |
804 | int rc = 0; |
805 | ||
fee1247a | 806 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
807 | return -1; |
808 | ||
809 | /* always get timestamp with Rx frame */ | |
810 | priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK; | |
811 | ||
bb8c093b | 812 | rc = iwl4965_check_rxon_cmd(&priv->staging_rxon); |
b481de9c ZY |
813 | if (rc) { |
814 | IWL_ERROR("Invalid RXON configuration. Not committing.\n"); | |
815 | return -EINVAL; | |
816 | } | |
817 | ||
818 | /* If we don't need to send a full RXON, we can use | |
bb8c093b | 819 | * iwl4965_rxon_assoc_cmd which is used to reconfigure filter |
b481de9c | 820 | * and other flags for the current radio configuration. */ |
bb8c093b CH |
821 | if (!iwl4965_full_rxon_required(priv)) { |
822 | rc = iwl4965_send_rxon_assoc(priv); | |
b481de9c ZY |
823 | if (rc) { |
824 | IWL_ERROR("Error setting RXON_ASSOC " | |
825 | "configuration (%d).\n", rc); | |
826 | return rc; | |
827 | } | |
828 | ||
829 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
830 | ||
831 | return 0; | |
832 | } | |
833 | ||
834 | /* station table will be cleared */ | |
835 | priv->assoc_station_added = 0; | |
836 | ||
c8b0e6e1 | 837 | #ifdef CONFIG_IWL4965_SENSITIVITY |
b481de9c ZY |
838 | priv->sensitivity_data.state = IWL_SENS_CALIB_NEED_REINIT; |
839 | if (!priv->error_recovering) | |
840 | priv->start_calib = 0; | |
841 | ||
842 | iwl4965_init_sensitivity(priv, CMD_ASYNC, 1); | |
c8b0e6e1 | 843 | #endif /* CONFIG_IWL4965_SENSITIVITY */ |
b481de9c ZY |
844 | |
845 | /* If we are currently associated and the new config requires | |
846 | * an RXON_ASSOC and the new config wants the associated mask enabled, | |
847 | * we must clear the associated from the active configuration | |
848 | * before we apply the new config */ | |
3109ece1 | 849 | if (iwl_is_associated(priv) && |
b481de9c ZY |
850 | (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) { |
851 | IWL_DEBUG_INFO("Toggling associated bit on current RXON\n"); | |
852 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
853 | ||
857485c0 | 854 | rc = iwl_send_cmd_pdu(priv, REPLY_RXON, |
bb8c093b | 855 | sizeof(struct iwl4965_rxon_cmd), |
b481de9c ZY |
856 | &priv->active_rxon); |
857 | ||
858 | /* If the mask clearing failed then we set | |
859 | * active_rxon back to what it was previously */ | |
860 | if (rc) { | |
861 | active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK; | |
862 | IWL_ERROR("Error clearing ASSOC_MSK on current " | |
863 | "configuration (%d).\n", rc); | |
864 | return rc; | |
865 | } | |
b481de9c ZY |
866 | } |
867 | ||
868 | IWL_DEBUG_INFO("Sending RXON\n" | |
869 | "* with%s RXON_FILTER_ASSOC_MSK\n" | |
870 | "* channel = %d\n" | |
0795af57 | 871 | "* bssid = %s\n", |
b481de9c ZY |
872 | ((priv->staging_rxon.filter_flags & |
873 | RXON_FILTER_ASSOC_MSK) ? "" : "out"), | |
874 | le16_to_cpu(priv->staging_rxon.channel), | |
0795af57 | 875 | print_mac(mac, priv->staging_rxon.bssid_addr)); |
b481de9c | 876 | |
deb09c43 | 877 | iwl4965_set_rxon_hwcrypto(priv, priv->cfg->mod_params->hw_crypto); |
b481de9c | 878 | /* Apply the new configuration */ |
857485c0 | 879 | rc = iwl_send_cmd_pdu(priv, REPLY_RXON, |
bb8c093b | 880 | sizeof(struct iwl4965_rxon_cmd), &priv->staging_rxon); |
b481de9c ZY |
881 | if (rc) { |
882 | IWL_ERROR("Error setting new configuration (%d).\n", rc); | |
883 | return rc; | |
884 | } | |
885 | ||
bf85ea4f | 886 | iwlcore_clear_stations_table(priv); |
556f8db7 | 887 | |
c8b0e6e1 | 888 | #ifdef CONFIG_IWL4965_SENSITIVITY |
b481de9c ZY |
889 | if (!priv->error_recovering) |
890 | priv->start_calib = 0; | |
891 | ||
892 | priv->sensitivity_data.state = IWL_SENS_CALIB_NEED_REINIT; | |
893 | iwl4965_init_sensitivity(priv, CMD_ASYNC, 1); | |
c8b0e6e1 | 894 | #endif /* CONFIG_IWL4965_SENSITIVITY */ |
b481de9c ZY |
895 | |
896 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
897 | ||
898 | /* If we issue a new RXON command which required a tune then we must | |
899 | * send a new TXPOWER command or we won't be able to Tx any frames */ | |
bb8c093b | 900 | rc = iwl4965_hw_reg_send_txpower(priv); |
b481de9c ZY |
901 | if (rc) { |
902 | IWL_ERROR("Error setting Tx power (%d).\n", rc); | |
903 | return rc; | |
904 | } | |
905 | ||
906 | /* Add the broadcast address so we can send broadcast frames */ | |
bb8c093b | 907 | if (iwl4965_rxon_add_station(priv, iwl4965_broadcast_addr, 0) == |
b481de9c ZY |
908 | IWL_INVALID_STATION) { |
909 | IWL_ERROR("Error adding BROADCAST address for transmit.\n"); | |
910 | return -EIO; | |
911 | } | |
912 | ||
913 | /* If we have set the ASSOC_MSK and we are in BSS mode then | |
914 | * add the IWL_AP_ID to the station rate table */ | |
3109ece1 | 915 | if (iwl_is_associated(priv) && |
b481de9c | 916 | (priv->iw_mode == IEEE80211_IF_TYPE_STA)) { |
bb8c093b | 917 | if (iwl4965_rxon_add_station(priv, priv->active_rxon.bssid_addr, 1) |
b481de9c ZY |
918 | == IWL_INVALID_STATION) { |
919 | IWL_ERROR("Error adding AP address for transmit.\n"); | |
920 | return -EIO; | |
921 | } | |
922 | priv->assoc_station_added = 1; | |
6974e363 EG |
923 | if (priv->default_wep_key && |
924 | iwl_send_static_wepkey_cmd(priv, 0)) | |
925 | IWL_ERROR("Could not send WEP static key.\n"); | |
b481de9c ZY |
926 | } |
927 | ||
928 | return 0; | |
929 | } | |
930 | ||
c79dd5b5 | 931 | static int iwl4965_send_bt_config(struct iwl_priv *priv) |
b481de9c | 932 | { |
bb8c093b | 933 | struct iwl4965_bt_cmd bt_cmd = { |
b481de9c ZY |
934 | .flags = 3, |
935 | .lead_time = 0xAA, | |
936 | .max_kill = 1, | |
937 | .kill_ack_mask = 0, | |
938 | .kill_cts_mask = 0, | |
939 | }; | |
940 | ||
857485c0 | 941 | return iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG, |
bb8c093b | 942 | sizeof(struct iwl4965_bt_cmd), &bt_cmd); |
b481de9c ZY |
943 | } |
944 | ||
c79dd5b5 | 945 | static int iwl4965_send_scan_abort(struct iwl_priv *priv) |
b481de9c ZY |
946 | { |
947 | int rc = 0; | |
bb8c093b | 948 | struct iwl4965_rx_packet *res; |
857485c0 | 949 | struct iwl_host_cmd cmd = { |
b481de9c ZY |
950 | .id = REPLY_SCAN_ABORT_CMD, |
951 | .meta.flags = CMD_WANT_SKB, | |
952 | }; | |
953 | ||
954 | /* If there isn't a scan actively going on in the hardware | |
955 | * then we are in between scan bands and not actually | |
956 | * actively scanning, so don't send the abort command */ | |
957 | if (!test_bit(STATUS_SCAN_HW, &priv->status)) { | |
958 | clear_bit(STATUS_SCAN_ABORTING, &priv->status); | |
959 | return 0; | |
960 | } | |
961 | ||
857485c0 | 962 | rc = iwl_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
963 | if (rc) { |
964 | clear_bit(STATUS_SCAN_ABORTING, &priv->status); | |
965 | return rc; | |
966 | } | |
967 | ||
bb8c093b | 968 | res = (struct iwl4965_rx_packet *)cmd.meta.u.skb->data; |
b481de9c ZY |
969 | if (res->u.status != CAN_ABORT_STATUS) { |
970 | /* The scan abort will return 1 for success or | |
971 | * 2 for "failure". A failure condition can be | |
972 | * due to simply not being in an active scan which | |
973 | * can occur if we send the scan abort before we | |
974 | * the microcode has notified us that a scan is | |
975 | * completed. */ | |
976 | IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status); | |
977 | clear_bit(STATUS_SCAN_ABORTING, &priv->status); | |
978 | clear_bit(STATUS_SCAN_HW, &priv->status); | |
979 | } | |
980 | ||
981 | dev_kfree_skb_any(cmd.meta.u.skb); | |
982 | ||
983 | return rc; | |
984 | } | |
985 | ||
c79dd5b5 | 986 | static int iwl4965_card_state_sync_callback(struct iwl_priv *priv, |
857485c0 | 987 | struct iwl_cmd *cmd, |
b481de9c ZY |
988 | struct sk_buff *skb) |
989 | { | |
990 | return 1; | |
991 | } | |
992 | ||
993 | /* | |
994 | * CARD_STATE_CMD | |
995 | * | |
9fbab516 | 996 | * Use: Sets the device's internal card state to enable, disable, or halt |
b481de9c ZY |
997 | * |
998 | * When in the 'enable' state the card operates as normal. | |
999 | * When in the 'disable' state, the card enters into a low power mode. | |
1000 | * When in the 'halt' state, the card is shut down and must be fully | |
1001 | * restarted to come back on. | |
1002 | */ | |
c79dd5b5 | 1003 | static int iwl4965_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag) |
b481de9c | 1004 | { |
857485c0 | 1005 | struct iwl_host_cmd cmd = { |
b481de9c ZY |
1006 | .id = REPLY_CARD_STATE_CMD, |
1007 | .len = sizeof(u32), | |
1008 | .data = &flags, | |
1009 | .meta.flags = meta_flag, | |
1010 | }; | |
1011 | ||
1012 | if (meta_flag & CMD_ASYNC) | |
bb8c093b | 1013 | cmd.meta.u.callback = iwl4965_card_state_sync_callback; |
b481de9c | 1014 | |
857485c0 | 1015 | return iwl_send_cmd(priv, &cmd); |
b481de9c ZY |
1016 | } |
1017 | ||
c79dd5b5 | 1018 | static int iwl4965_add_sta_sync_callback(struct iwl_priv *priv, |
857485c0 | 1019 | struct iwl_cmd *cmd, struct sk_buff *skb) |
b481de9c | 1020 | { |
bb8c093b | 1021 | struct iwl4965_rx_packet *res = NULL; |
b481de9c ZY |
1022 | |
1023 | if (!skb) { | |
1024 | IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n"); | |
1025 | return 1; | |
1026 | } | |
1027 | ||
bb8c093b | 1028 | res = (struct iwl4965_rx_packet *)skb->data; |
b481de9c ZY |
1029 | if (res->hdr.flags & IWL_CMD_FAILED_MSK) { |
1030 | IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n", | |
1031 | res->hdr.flags); | |
1032 | return 1; | |
1033 | } | |
1034 | ||
1035 | switch (res->u.add_sta.status) { | |
1036 | case ADD_STA_SUCCESS_MSK: | |
1037 | break; | |
1038 | default: | |
1039 | break; | |
1040 | } | |
1041 | ||
1042 | /* We didn't cache the SKB; let the caller free it */ | |
1043 | return 1; | |
1044 | } | |
1045 | ||
c79dd5b5 | 1046 | int iwl4965_send_add_station(struct iwl_priv *priv, |
bb8c093b | 1047 | struct iwl4965_addsta_cmd *sta, u8 flags) |
b481de9c | 1048 | { |
bb8c093b | 1049 | struct iwl4965_rx_packet *res = NULL; |
b481de9c | 1050 | int rc = 0; |
857485c0 | 1051 | struct iwl_host_cmd cmd = { |
b481de9c | 1052 | .id = REPLY_ADD_STA, |
bb8c093b | 1053 | .len = sizeof(struct iwl4965_addsta_cmd), |
b481de9c ZY |
1054 | .meta.flags = flags, |
1055 | .data = sta, | |
1056 | }; | |
1057 | ||
1058 | if (flags & CMD_ASYNC) | |
bb8c093b | 1059 | cmd.meta.u.callback = iwl4965_add_sta_sync_callback; |
b481de9c ZY |
1060 | else |
1061 | cmd.meta.flags |= CMD_WANT_SKB; | |
1062 | ||
857485c0 | 1063 | rc = iwl_send_cmd(priv, &cmd); |
b481de9c ZY |
1064 | |
1065 | if (rc || (flags & CMD_ASYNC)) | |
1066 | return rc; | |
1067 | ||
bb8c093b | 1068 | res = (struct iwl4965_rx_packet *)cmd.meta.u.skb->data; |
b481de9c ZY |
1069 | if (res->hdr.flags & IWL_CMD_FAILED_MSK) { |
1070 | IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n", | |
1071 | res->hdr.flags); | |
1072 | rc = -EIO; | |
1073 | } | |
1074 | ||
1075 | if (rc == 0) { | |
1076 | switch (res->u.add_sta.status) { | |
1077 | case ADD_STA_SUCCESS_MSK: | |
1078 | IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n"); | |
1079 | break; | |
1080 | default: | |
1081 | rc = -EIO; | |
1082 | IWL_WARNING("REPLY_ADD_STA failed\n"); | |
1083 | break; | |
1084 | } | |
1085 | } | |
1086 | ||
1087 | priv->alloc_rxb_skb--; | |
1088 | dev_kfree_skb_any(cmd.meta.u.skb); | |
1089 | ||
1090 | return rc; | |
1091 | } | |
1092 | ||
c79dd5b5 | 1093 | static void iwl4965_clear_free_frames(struct iwl_priv *priv) |
b481de9c ZY |
1094 | { |
1095 | struct list_head *element; | |
1096 | ||
1097 | IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n", | |
1098 | priv->frames_count); | |
1099 | ||
1100 | while (!list_empty(&priv->free_frames)) { | |
1101 | element = priv->free_frames.next; | |
1102 | list_del(element); | |
bb8c093b | 1103 | kfree(list_entry(element, struct iwl4965_frame, list)); |
b481de9c ZY |
1104 | priv->frames_count--; |
1105 | } | |
1106 | ||
1107 | if (priv->frames_count) { | |
1108 | IWL_WARNING("%d frames still in use. Did we lose one?\n", | |
1109 | priv->frames_count); | |
1110 | priv->frames_count = 0; | |
1111 | } | |
1112 | } | |
1113 | ||
c79dd5b5 | 1114 | static struct iwl4965_frame *iwl4965_get_free_frame(struct iwl_priv *priv) |
b481de9c | 1115 | { |
bb8c093b | 1116 | struct iwl4965_frame *frame; |
b481de9c ZY |
1117 | struct list_head *element; |
1118 | if (list_empty(&priv->free_frames)) { | |
1119 | frame = kzalloc(sizeof(*frame), GFP_KERNEL); | |
1120 | if (!frame) { | |
1121 | IWL_ERROR("Could not allocate frame!\n"); | |
1122 | return NULL; | |
1123 | } | |
1124 | ||
1125 | priv->frames_count++; | |
1126 | return frame; | |
1127 | } | |
1128 | ||
1129 | element = priv->free_frames.next; | |
1130 | list_del(element); | |
bb8c093b | 1131 | return list_entry(element, struct iwl4965_frame, list); |
b481de9c ZY |
1132 | } |
1133 | ||
c79dd5b5 | 1134 | static void iwl4965_free_frame(struct iwl_priv *priv, struct iwl4965_frame *frame) |
b481de9c ZY |
1135 | { |
1136 | memset(frame, 0, sizeof(*frame)); | |
1137 | list_add(&frame->list, &priv->free_frames); | |
1138 | } | |
1139 | ||
c79dd5b5 | 1140 | unsigned int iwl4965_fill_beacon_frame(struct iwl_priv *priv, |
b481de9c ZY |
1141 | struct ieee80211_hdr *hdr, |
1142 | const u8 *dest, int left) | |
1143 | { | |
1144 | ||
3109ece1 | 1145 | if (!iwl_is_associated(priv) || !priv->ibss_beacon || |
b481de9c ZY |
1146 | ((priv->iw_mode != IEEE80211_IF_TYPE_IBSS) && |
1147 | (priv->iw_mode != IEEE80211_IF_TYPE_AP))) | |
1148 | return 0; | |
1149 | ||
1150 | if (priv->ibss_beacon->len > left) | |
1151 | return 0; | |
1152 | ||
1153 | memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len); | |
1154 | ||
1155 | return priv->ibss_beacon->len; | |
1156 | } | |
1157 | ||
bb8c093b | 1158 | static u8 iwl4965_rate_get_lowest_plcp(int rate_mask) |
b481de9c ZY |
1159 | { |
1160 | u8 i; | |
1161 | ||
1162 | for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID; | |
bb8c093b | 1163 | i = iwl4965_rates[i].next_ieee) { |
b481de9c | 1164 | if (rate_mask & (1 << i)) |
bb8c093b | 1165 | return iwl4965_rates[i].plcp; |
b481de9c ZY |
1166 | } |
1167 | ||
1168 | return IWL_RATE_INVALID; | |
1169 | } | |
1170 | ||
c79dd5b5 | 1171 | static int iwl4965_send_beacon_cmd(struct iwl_priv *priv) |
b481de9c | 1172 | { |
bb8c093b | 1173 | struct iwl4965_frame *frame; |
b481de9c ZY |
1174 | unsigned int frame_size; |
1175 | int rc; | |
1176 | u8 rate; | |
1177 | ||
bb8c093b | 1178 | frame = iwl4965_get_free_frame(priv); |
b481de9c ZY |
1179 | |
1180 | if (!frame) { | |
1181 | IWL_ERROR("Could not obtain free frame buffer for beacon " | |
1182 | "command.\n"); | |
1183 | return -ENOMEM; | |
1184 | } | |
1185 | ||
1186 | if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) { | |
bb8c093b | 1187 | rate = iwl4965_rate_get_lowest_plcp(priv->active_rate_basic & |
b481de9c ZY |
1188 | 0xFF0); |
1189 | if (rate == IWL_INVALID_RATE) | |
1190 | rate = IWL_RATE_6M_PLCP; | |
1191 | } else { | |
bb8c093b | 1192 | rate = iwl4965_rate_get_lowest_plcp(priv->active_rate_basic & 0xF); |
b481de9c ZY |
1193 | if (rate == IWL_INVALID_RATE) |
1194 | rate = IWL_RATE_1M_PLCP; | |
1195 | } | |
1196 | ||
bb8c093b | 1197 | frame_size = iwl4965_hw_get_beacon_cmd(priv, frame, rate); |
b481de9c | 1198 | |
857485c0 | 1199 | rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size, |
b481de9c ZY |
1200 | &frame->u.cmd[0]); |
1201 | ||
bb8c093b | 1202 | iwl4965_free_frame(priv, frame); |
b481de9c ZY |
1203 | |
1204 | return rc; | |
1205 | } | |
1206 | ||
b481de9c ZY |
1207 | /****************************************************************************** |
1208 | * | |
1209 | * Misc. internal state and helper functions | |
1210 | * | |
1211 | ******************************************************************************/ | |
b481de9c | 1212 | |
c79dd5b5 | 1213 | static void iwl4965_unset_hw_setting(struct iwl_priv *priv) |
b481de9c | 1214 | { |
059ff826 | 1215 | if (priv->shared_virt) |
b481de9c | 1216 | pci_free_consistent(priv->pci_dev, |
bb8c093b | 1217 | sizeof(struct iwl4965_shared), |
059ff826 TW |
1218 | priv->shared_virt, |
1219 | priv->shared_phys); | |
b481de9c ZY |
1220 | } |
1221 | ||
1222 | /** | |
bb8c093b | 1223 | * iwl4965_supported_rate_to_ie - fill in the supported rate in IE field |
b481de9c ZY |
1224 | * |
1225 | * return : set the bit for each supported rate insert in ie | |
1226 | */ | |
bb8c093b | 1227 | static u16 iwl4965_supported_rate_to_ie(u8 *ie, u16 supported_rate, |
c7c46676 | 1228 | u16 basic_rate, int *left) |
b481de9c ZY |
1229 | { |
1230 | u16 ret_rates = 0, bit; | |
1231 | int i; | |
c7c46676 TW |
1232 | u8 *cnt = ie; |
1233 | u8 *rates = ie + 1; | |
b481de9c ZY |
1234 | |
1235 | for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) { | |
1236 | if (bit & supported_rate) { | |
1237 | ret_rates |= bit; | |
bb8c093b | 1238 | rates[*cnt] = iwl4965_rates[i].ieee | |
c7c46676 TW |
1239 | ((bit & basic_rate) ? 0x80 : 0x00); |
1240 | (*cnt)++; | |
1241 | (*left)--; | |
1242 | if ((*left <= 0) || | |
1243 | (*cnt >= IWL_SUPPORTED_RATES_IE_LEN)) | |
b481de9c ZY |
1244 | break; |
1245 | } | |
1246 | } | |
1247 | ||
1248 | return ret_rates; | |
1249 | } | |
1250 | ||
b481de9c | 1251 | /** |
bb8c093b | 1252 | * iwl4965_fill_probe_req - fill in all required fields and IE for probe request |
b481de9c | 1253 | */ |
c79dd5b5 | 1254 | static u16 iwl4965_fill_probe_req(struct iwl_priv *priv, |
78330fdd TW |
1255 | enum ieee80211_band band, |
1256 | struct ieee80211_mgmt *frame, | |
1257 | int left, int is_direct) | |
b481de9c ZY |
1258 | { |
1259 | int len = 0; | |
1260 | u8 *pos = NULL; | |
bee488db | 1261 | u16 active_rates, ret_rates, cck_rates, active_rate_basic; |
8fb88032 | 1262 | #ifdef CONFIG_IWL4965_HT |
78330fdd TW |
1263 | const struct ieee80211_supported_band *sband = |
1264 | iwl4965_get_hw_mode(priv, band); | |
8fb88032 | 1265 | #endif /* CONFIG_IWL4965_HT */ |
b481de9c ZY |
1266 | |
1267 | /* Make sure there is enough space for the probe request, | |
1268 | * two mandatory IEs and the data */ | |
1269 | left -= 24; | |
1270 | if (left < 0) | |
1271 | return 0; | |
1272 | len += 24; | |
1273 | ||
1274 | frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ); | |
bb8c093b | 1275 | memcpy(frame->da, iwl4965_broadcast_addr, ETH_ALEN); |
b481de9c | 1276 | memcpy(frame->sa, priv->mac_addr, ETH_ALEN); |
bb8c093b | 1277 | memcpy(frame->bssid, iwl4965_broadcast_addr, ETH_ALEN); |
b481de9c ZY |
1278 | frame->seq_ctrl = 0; |
1279 | ||
1280 | /* fill in our indirect SSID IE */ | |
1281 | /* ...next IE... */ | |
1282 | ||
1283 | left -= 2; | |
1284 | if (left < 0) | |
1285 | return 0; | |
1286 | len += 2; | |
1287 | pos = &(frame->u.probe_req.variable[0]); | |
1288 | *pos++ = WLAN_EID_SSID; | |
1289 | *pos++ = 0; | |
1290 | ||
1291 | /* fill in our direct SSID IE... */ | |
1292 | if (is_direct) { | |
1293 | /* ...next IE... */ | |
1294 | left -= 2 + priv->essid_len; | |
1295 | if (left < 0) | |
1296 | return 0; | |
1297 | /* ... fill it in... */ | |
1298 | *pos++ = WLAN_EID_SSID; | |
1299 | *pos++ = priv->essid_len; | |
1300 | memcpy(pos, priv->essid, priv->essid_len); | |
1301 | pos += priv->essid_len; | |
1302 | len += 2 + priv->essid_len; | |
1303 | } | |
1304 | ||
1305 | /* fill in supported rate */ | |
1306 | /* ...next IE... */ | |
1307 | left -= 2; | |
1308 | if (left < 0) | |
1309 | return 0; | |
c7c46676 | 1310 | |
b481de9c ZY |
1311 | /* ... fill it in... */ |
1312 | *pos++ = WLAN_EID_SUPP_RATES; | |
1313 | *pos = 0; | |
c7c46676 | 1314 | |
bee488db | 1315 | /* exclude 60M rate */ |
1316 | active_rates = priv->rates_mask; | |
1317 | active_rates &= ~IWL_RATE_60M_MASK; | |
1318 | ||
1319 | active_rate_basic = active_rates & IWL_BASIC_RATES_MASK; | |
b481de9c | 1320 | |
c7c46676 | 1321 | cck_rates = IWL_CCK_RATES_MASK & active_rates; |
bb8c093b | 1322 | ret_rates = iwl4965_supported_rate_to_ie(pos, cck_rates, |
bee488db | 1323 | active_rate_basic, &left); |
c7c46676 TW |
1324 | active_rates &= ~ret_rates; |
1325 | ||
bb8c093b | 1326 | ret_rates = iwl4965_supported_rate_to_ie(pos, active_rates, |
bee488db | 1327 | active_rate_basic, &left); |
c7c46676 TW |
1328 | active_rates &= ~ret_rates; |
1329 | ||
b481de9c ZY |
1330 | len += 2 + *pos; |
1331 | pos += (*pos) + 1; | |
c7c46676 | 1332 | if (active_rates == 0) |
b481de9c ZY |
1333 | goto fill_end; |
1334 | ||
1335 | /* fill in supported extended rate */ | |
1336 | /* ...next IE... */ | |
1337 | left -= 2; | |
1338 | if (left < 0) | |
1339 | return 0; | |
1340 | /* ... fill it in... */ | |
1341 | *pos++ = WLAN_EID_EXT_SUPP_RATES; | |
1342 | *pos = 0; | |
bb8c093b | 1343 | iwl4965_supported_rate_to_ie(pos, active_rates, |
bee488db | 1344 | active_rate_basic, &left); |
b481de9c ZY |
1345 | if (*pos > 0) |
1346 | len += 2 + *pos; | |
1347 | ||
c8b0e6e1 | 1348 | #ifdef CONFIG_IWL4965_HT |
78330fdd TW |
1349 | if (sband && sband->ht_info.ht_supported) { |
1350 | struct ieee80211_ht_cap *ht_cap; | |
b481de9c ZY |
1351 | pos += (*pos) + 1; |
1352 | *pos++ = WLAN_EID_HT_CAPABILITY; | |
8fb88032 | 1353 | *pos++ = sizeof(struct ieee80211_ht_cap); |
78330fdd TW |
1354 | ht_cap = (struct ieee80211_ht_cap *)pos; |
1355 | ht_cap->cap_info = cpu_to_le16(sband->ht_info.cap); | |
1356 | memcpy(ht_cap->supp_mcs_set, sband->ht_info.supp_mcs_set, 16); | |
1357 | ht_cap->ampdu_params_info =(sband->ht_info.ampdu_factor & | |
1358 | IEEE80211_HT_CAP_AMPDU_FACTOR) | | |
1359 | ((sband->ht_info.ampdu_density << 2) & | |
1360 | IEEE80211_HT_CAP_AMPDU_DENSITY); | |
8fb88032 | 1361 | len += 2 + sizeof(struct ieee80211_ht_cap); |
b481de9c | 1362 | } |
c8b0e6e1 | 1363 | #endif /*CONFIG_IWL4965_HT */ |
b481de9c ZY |
1364 | |
1365 | fill_end: | |
1366 | return (u16)len; | |
1367 | } | |
1368 | ||
1369 | /* | |
1370 | * QoS support | |
1371 | */ | |
c79dd5b5 | 1372 | static int iwl4965_send_qos_params_command(struct iwl_priv *priv, |
bb8c093b | 1373 | struct iwl4965_qosparam_cmd *qos) |
b481de9c ZY |
1374 | { |
1375 | ||
857485c0 | 1376 | return iwl_send_cmd_pdu(priv, REPLY_QOS_PARAM, |
bb8c093b | 1377 | sizeof(struct iwl4965_qosparam_cmd), qos); |
b481de9c ZY |
1378 | } |
1379 | ||
c79dd5b5 | 1380 | static void iwl4965_activate_qos(struct iwl_priv *priv, u8 force) |
b481de9c ZY |
1381 | { |
1382 | unsigned long flags; | |
1383 | ||
b481de9c ZY |
1384 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
1385 | return; | |
1386 | ||
1387 | if (!priv->qos_data.qos_enable) | |
1388 | return; | |
1389 | ||
1390 | spin_lock_irqsave(&priv->lock, flags); | |
1391 | priv->qos_data.def_qos_parm.qos_flags = 0; | |
1392 | ||
1393 | if (priv->qos_data.qos_cap.q_AP.queue_request && | |
1394 | !priv->qos_data.qos_cap.q_AP.txop_request) | |
1395 | priv->qos_data.def_qos_parm.qos_flags |= | |
1396 | QOS_PARAM_FLG_TXOP_TYPE_MSK; | |
b481de9c ZY |
1397 | if (priv->qos_data.qos_active) |
1398 | priv->qos_data.def_qos_parm.qos_flags |= | |
1399 | QOS_PARAM_FLG_UPDATE_EDCA_MSK; | |
1400 | ||
c8b0e6e1 | 1401 | #ifdef CONFIG_IWL4965_HT |
fd105e79 | 1402 | if (priv->current_ht_config.is_ht) |
f1f1f5c7 | 1403 | priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK; |
c8b0e6e1 | 1404 | #endif /* CONFIG_IWL4965_HT */ |
f1f1f5c7 | 1405 | |
b481de9c ZY |
1406 | spin_unlock_irqrestore(&priv->lock, flags); |
1407 | ||
3109ece1 | 1408 | if (force || iwl_is_associated(priv)) { |
f1f1f5c7 TW |
1409 | IWL_DEBUG_QOS("send QoS cmd with Qos active=%d FLAGS=0x%X\n", |
1410 | priv->qos_data.qos_active, | |
1411 | priv->qos_data.def_qos_parm.qos_flags); | |
b481de9c | 1412 | |
bb8c093b | 1413 | iwl4965_send_qos_params_command(priv, |
b481de9c ZY |
1414 | &(priv->qos_data.def_qos_parm)); |
1415 | } | |
1416 | } | |
1417 | ||
b481de9c ZY |
1418 | /* |
1419 | * Power management (not Tx power!) functions | |
1420 | */ | |
1421 | #define MSEC_TO_USEC 1024 | |
1422 | ||
1423 | #define NOSLP __constant_cpu_to_le16(0), 0, 0 | |
1424 | #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0 | |
1425 | #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC) | |
1426 | #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \ | |
1427 | __constant_cpu_to_le32(X1), \ | |
1428 | __constant_cpu_to_le32(X2), \ | |
1429 | __constant_cpu_to_le32(X3), \ | |
1430 | __constant_cpu_to_le32(X4)} | |
1431 | ||
1432 | ||
1433 | /* default power management (not Tx power) table values */ | |
1434 | /* for tim 0-10 */ | |
bb8c093b | 1435 | static struct iwl4965_power_vec_entry range_0[IWL_POWER_AC] = { |
b481de9c ZY |
1436 | {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0}, |
1437 | {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0}, | |
1438 | {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0}, | |
1439 | {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0}, | |
1440 | {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1}, | |
1441 | {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1} | |
1442 | }; | |
1443 | ||
1444 | /* for tim > 10 */ | |
bb8c093b | 1445 | static struct iwl4965_power_vec_entry range_1[IWL_POWER_AC] = { |
b481de9c ZY |
1446 | {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0}, |
1447 | {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), | |
1448 | SLP_VEC(1, 2, 3, 4, 0xFF)}, 0}, | |
1449 | {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), | |
1450 | SLP_VEC(2, 4, 6, 7, 0xFF)}, 0}, | |
1451 | {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), | |
1452 | SLP_VEC(2, 6, 9, 9, 0xFF)}, 0}, | |
1453 | {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0}, | |
1454 | {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), | |
1455 | SLP_VEC(4, 7, 10, 10, 0xFF)}, 0} | |
1456 | }; | |
1457 | ||
c79dd5b5 | 1458 | int iwl4965_power_init_handle(struct iwl_priv *priv) |
b481de9c ZY |
1459 | { |
1460 | int rc = 0, i; | |
bb8c093b CH |
1461 | struct iwl4965_power_mgr *pow_data; |
1462 | int size = sizeof(struct iwl4965_power_vec_entry) * IWL_POWER_AC; | |
b481de9c ZY |
1463 | u16 pci_pm; |
1464 | ||
1465 | IWL_DEBUG_POWER("Initialize power \n"); | |
1466 | ||
1467 | pow_data = &(priv->power_data); | |
1468 | ||
1469 | memset(pow_data, 0, sizeof(*pow_data)); | |
1470 | ||
1471 | pow_data->active_index = IWL_POWER_RANGE_0; | |
1472 | pow_data->dtim_val = 0xffff; | |
1473 | ||
1474 | memcpy(&pow_data->pwr_range_0[0], &range_0[0], size); | |
1475 | memcpy(&pow_data->pwr_range_1[0], &range_1[0], size); | |
1476 | ||
1477 | rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm); | |
1478 | if (rc != 0) | |
1479 | return 0; | |
1480 | else { | |
bb8c093b | 1481 | struct iwl4965_powertable_cmd *cmd; |
b481de9c ZY |
1482 | |
1483 | IWL_DEBUG_POWER("adjust power command flags\n"); | |
1484 | ||
1485 | for (i = 0; i < IWL_POWER_AC; i++) { | |
1486 | cmd = &pow_data->pwr_range_0[i].cmd; | |
1487 | ||
1488 | if (pci_pm & 0x1) | |
1489 | cmd->flags &= ~IWL_POWER_PCI_PM_MSK; | |
1490 | else | |
1491 | cmd->flags |= IWL_POWER_PCI_PM_MSK; | |
1492 | } | |
1493 | } | |
1494 | return rc; | |
1495 | } | |
1496 | ||
c79dd5b5 | 1497 | static int iwl4965_update_power_cmd(struct iwl_priv *priv, |
bb8c093b | 1498 | struct iwl4965_powertable_cmd *cmd, u32 mode) |
b481de9c ZY |
1499 | { |
1500 | int rc = 0, i; | |
1501 | u8 skip; | |
1502 | u32 max_sleep = 0; | |
bb8c093b | 1503 | struct iwl4965_power_vec_entry *range; |
b481de9c | 1504 | u8 period = 0; |
bb8c093b | 1505 | struct iwl4965_power_mgr *pow_data; |
b481de9c ZY |
1506 | |
1507 | if (mode > IWL_POWER_INDEX_5) { | |
1508 | IWL_DEBUG_POWER("Error invalid power mode \n"); | |
1509 | return -1; | |
1510 | } | |
1511 | pow_data = &(priv->power_data); | |
1512 | ||
1513 | if (pow_data->active_index == IWL_POWER_RANGE_0) | |
1514 | range = &pow_data->pwr_range_0[0]; | |
1515 | else | |
1516 | range = &pow_data->pwr_range_1[1]; | |
1517 | ||
bb8c093b | 1518 | memcpy(cmd, &range[mode].cmd, sizeof(struct iwl4965_powertable_cmd)); |
b481de9c ZY |
1519 | |
1520 | #ifdef IWL_MAC80211_DISABLE | |
1521 | if (priv->assoc_network != NULL) { | |
1522 | unsigned long flags; | |
1523 | ||
1524 | period = priv->assoc_network->tim.tim_period; | |
1525 | } | |
1526 | #endif /*IWL_MAC80211_DISABLE */ | |
1527 | skip = range[mode].no_dtim; | |
1528 | ||
1529 | if (period == 0) { | |
1530 | period = 1; | |
1531 | skip = 0; | |
1532 | } | |
1533 | ||
1534 | if (skip == 0) { | |
1535 | max_sleep = period; | |
1536 | cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK; | |
1537 | } else { | |
1538 | __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]; | |
1539 | max_sleep = (le32_to_cpu(slp_itrvl) / period) * period; | |
1540 | cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK; | |
1541 | } | |
1542 | ||
1543 | for (i = 0; i < IWL_POWER_VEC_SIZE; i++) { | |
1544 | if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep) | |
1545 | cmd->sleep_interval[i] = cpu_to_le32(max_sleep); | |
1546 | } | |
1547 | ||
1548 | IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags); | |
1549 | IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout)); | |
1550 | IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout)); | |
1551 | IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n", | |
1552 | le32_to_cpu(cmd->sleep_interval[0]), | |
1553 | le32_to_cpu(cmd->sleep_interval[1]), | |
1554 | le32_to_cpu(cmd->sleep_interval[2]), | |
1555 | le32_to_cpu(cmd->sleep_interval[3]), | |
1556 | le32_to_cpu(cmd->sleep_interval[4])); | |
1557 | ||
1558 | return rc; | |
1559 | } | |
1560 | ||
c79dd5b5 | 1561 | static int iwl4965_send_power_mode(struct iwl_priv *priv, u32 mode) |
b481de9c | 1562 | { |
9a62f73b | 1563 | u32 uninitialized_var(final_mode); |
b481de9c | 1564 | int rc; |
bb8c093b | 1565 | struct iwl4965_powertable_cmd cmd; |
b481de9c ZY |
1566 | |
1567 | /* If on battery, set to 3, | |
01ebd063 | 1568 | * if plugged into AC power, set to CAM ("continuously aware mode"), |
b481de9c ZY |
1569 | * else user level */ |
1570 | switch (mode) { | |
1571 | case IWL_POWER_BATTERY: | |
1572 | final_mode = IWL_POWER_INDEX_3; | |
1573 | break; | |
1574 | case IWL_POWER_AC: | |
1575 | final_mode = IWL_POWER_MODE_CAM; | |
1576 | break; | |
1577 | default: | |
1578 | final_mode = mode; | |
1579 | break; | |
1580 | } | |
1581 | ||
1582 | cmd.keep_alive_beacons = 0; | |
1583 | ||
bb8c093b | 1584 | iwl4965_update_power_cmd(priv, &cmd, final_mode); |
b481de9c | 1585 | |
857485c0 | 1586 | rc = iwl_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd); |
b481de9c ZY |
1587 | |
1588 | if (final_mode == IWL_POWER_MODE_CAM) | |
1589 | clear_bit(STATUS_POWER_PMI, &priv->status); | |
1590 | else | |
1591 | set_bit(STATUS_POWER_PMI, &priv->status); | |
1592 | ||
1593 | return rc; | |
1594 | } | |
1595 | ||
c79dd5b5 | 1596 | int iwl4965_is_network_packet(struct iwl_priv *priv, struct ieee80211_hdr *header) |
b481de9c ZY |
1597 | { |
1598 | /* Filter incoming packets to determine if they are targeted toward | |
1599 | * this network, discarding packets coming from ourselves */ | |
1600 | switch (priv->iw_mode) { | |
1601 | case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */ | |
1602 | /* packets from our adapter are dropped (echo) */ | |
1603 | if (!compare_ether_addr(header->addr2, priv->mac_addr)) | |
1604 | return 0; | |
1605 | /* {broad,multi}cast packets to our IBSS go through */ | |
1606 | if (is_multicast_ether_addr(header->addr1)) | |
1607 | return !compare_ether_addr(header->addr3, priv->bssid); | |
1608 | /* packets to our adapter go through */ | |
1609 | return !compare_ether_addr(header->addr1, priv->mac_addr); | |
1610 | case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */ | |
1611 | /* packets from our adapter are dropped (echo) */ | |
1612 | if (!compare_ether_addr(header->addr3, priv->mac_addr)) | |
1613 | return 0; | |
1614 | /* {broad,multi}cast packets to our BSS go through */ | |
1615 | if (is_multicast_ether_addr(header->addr1)) | |
1616 | return !compare_ether_addr(header->addr2, priv->bssid); | |
1617 | /* packets to our adapter go through */ | |
1618 | return !compare_ether_addr(header->addr1, priv->mac_addr); | |
69dc5d9d TW |
1619 | default: |
1620 | break; | |
b481de9c ZY |
1621 | } |
1622 | ||
1623 | return 1; | |
1624 | } | |
1625 | ||
1626 | #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x | |
1627 | ||
bb8c093b | 1628 | static const char *iwl4965_get_tx_fail_reason(u32 status) |
b481de9c ZY |
1629 | { |
1630 | switch (status & TX_STATUS_MSK) { | |
1631 | case TX_STATUS_SUCCESS: | |
1632 | return "SUCCESS"; | |
1633 | TX_STATUS_ENTRY(SHORT_LIMIT); | |
1634 | TX_STATUS_ENTRY(LONG_LIMIT); | |
1635 | TX_STATUS_ENTRY(FIFO_UNDERRUN); | |
1636 | TX_STATUS_ENTRY(MGMNT_ABORT); | |
1637 | TX_STATUS_ENTRY(NEXT_FRAG); | |
1638 | TX_STATUS_ENTRY(LIFE_EXPIRE); | |
1639 | TX_STATUS_ENTRY(DEST_PS); | |
1640 | TX_STATUS_ENTRY(ABORTED); | |
1641 | TX_STATUS_ENTRY(BT_RETRY); | |
1642 | TX_STATUS_ENTRY(STA_INVALID); | |
1643 | TX_STATUS_ENTRY(FRAG_DROPPED); | |
1644 | TX_STATUS_ENTRY(TID_DISABLE); | |
1645 | TX_STATUS_ENTRY(FRAME_FLUSHED); | |
1646 | TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL); | |
1647 | TX_STATUS_ENTRY(TX_LOCKED); | |
1648 | TX_STATUS_ENTRY(NO_BEACON_ON_RADAR); | |
1649 | } | |
1650 | ||
1651 | return "UNKNOWN"; | |
1652 | } | |
1653 | ||
1654 | /** | |
bb8c093b | 1655 | * iwl4965_scan_cancel - Cancel any currently executing HW scan |
b481de9c ZY |
1656 | * |
1657 | * NOTE: priv->mutex is not required before calling this function | |
1658 | */ | |
c79dd5b5 | 1659 | static int iwl4965_scan_cancel(struct iwl_priv *priv) |
b481de9c ZY |
1660 | { |
1661 | if (!test_bit(STATUS_SCAN_HW, &priv->status)) { | |
1662 | clear_bit(STATUS_SCANNING, &priv->status); | |
1663 | return 0; | |
1664 | } | |
1665 | ||
1666 | if (test_bit(STATUS_SCANNING, &priv->status)) { | |
1667 | if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
1668 | IWL_DEBUG_SCAN("Queuing scan abort.\n"); | |
1669 | set_bit(STATUS_SCAN_ABORTING, &priv->status); | |
1670 | queue_work(priv->workqueue, &priv->abort_scan); | |
1671 | ||
1672 | } else | |
1673 | IWL_DEBUG_SCAN("Scan abort already in progress.\n"); | |
1674 | ||
1675 | return test_bit(STATUS_SCANNING, &priv->status); | |
1676 | } | |
1677 | ||
1678 | return 0; | |
1679 | } | |
1680 | ||
1681 | /** | |
bb8c093b | 1682 | * iwl4965_scan_cancel_timeout - Cancel any currently executing HW scan |
b481de9c ZY |
1683 | * @ms: amount of time to wait (in milliseconds) for scan to abort |
1684 | * | |
1685 | * NOTE: priv->mutex must be held before calling this function | |
1686 | */ | |
c79dd5b5 | 1687 | static int iwl4965_scan_cancel_timeout(struct iwl_priv *priv, unsigned long ms) |
b481de9c ZY |
1688 | { |
1689 | unsigned long now = jiffies; | |
1690 | int ret; | |
1691 | ||
bb8c093b | 1692 | ret = iwl4965_scan_cancel(priv); |
b481de9c ZY |
1693 | if (ret && ms) { |
1694 | mutex_unlock(&priv->mutex); | |
1695 | while (!time_after(jiffies, now + msecs_to_jiffies(ms)) && | |
1696 | test_bit(STATUS_SCANNING, &priv->status)) | |
1697 | msleep(1); | |
1698 | mutex_lock(&priv->mutex); | |
1699 | ||
1700 | return test_bit(STATUS_SCANNING, &priv->status); | |
1701 | } | |
1702 | ||
1703 | return ret; | |
1704 | } | |
1705 | ||
c79dd5b5 | 1706 | static void iwl4965_sequence_reset(struct iwl_priv *priv) |
b481de9c ZY |
1707 | { |
1708 | /* Reset ieee stats */ | |
1709 | ||
1710 | /* We don't reset the net_device_stats (ieee->stats) on | |
1711 | * re-association */ | |
1712 | ||
1713 | priv->last_seq_num = -1; | |
1714 | priv->last_frag_num = -1; | |
1715 | priv->last_packet_time = 0; | |
1716 | ||
bb8c093b | 1717 | iwl4965_scan_cancel(priv); |
b481de9c ZY |
1718 | } |
1719 | ||
1720 | #define MAX_UCODE_BEACON_INTERVAL 4096 | |
1721 | #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA) | |
1722 | ||
bb8c093b | 1723 | static __le16 iwl4965_adjust_beacon_interval(u16 beacon_val) |
b481de9c ZY |
1724 | { |
1725 | u16 new_val = 0; | |
1726 | u16 beacon_factor = 0; | |
1727 | ||
1728 | beacon_factor = | |
1729 | (beacon_val + MAX_UCODE_BEACON_INTERVAL) | |
1730 | / MAX_UCODE_BEACON_INTERVAL; | |
1731 | new_val = beacon_val / beacon_factor; | |
1732 | ||
1733 | return cpu_to_le16(new_val); | |
1734 | } | |
1735 | ||
c79dd5b5 | 1736 | static void iwl4965_setup_rxon_timing(struct iwl_priv *priv) |
b481de9c ZY |
1737 | { |
1738 | u64 interval_tm_unit; | |
1739 | u64 tsf, result; | |
1740 | unsigned long flags; | |
1741 | struct ieee80211_conf *conf = NULL; | |
1742 | u16 beacon_int = 0; | |
1743 | ||
1744 | conf = ieee80211_get_hw_conf(priv->hw); | |
1745 | ||
1746 | spin_lock_irqsave(&priv->lock, flags); | |
3109ece1 TW |
1747 | priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp >> 32); |
1748 | priv->rxon_timing.timestamp.dw[0] = | |
1749 | cpu_to_le32(priv->timestamp & 0xFFFFFFFF); | |
b481de9c ZY |
1750 | |
1751 | priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL; | |
1752 | ||
3109ece1 | 1753 | tsf = priv->timestamp; |
b481de9c ZY |
1754 | |
1755 | beacon_int = priv->beacon_int; | |
1756 | spin_unlock_irqrestore(&priv->lock, flags); | |
1757 | ||
1758 | if (priv->iw_mode == IEEE80211_IF_TYPE_STA) { | |
1759 | if (beacon_int == 0) { | |
1760 | priv->rxon_timing.beacon_interval = cpu_to_le16(100); | |
1761 | priv->rxon_timing.beacon_init_val = cpu_to_le32(102400); | |
1762 | } else { | |
1763 | priv->rxon_timing.beacon_interval = | |
1764 | cpu_to_le16(beacon_int); | |
1765 | priv->rxon_timing.beacon_interval = | |
bb8c093b | 1766 | iwl4965_adjust_beacon_interval( |
b481de9c ZY |
1767 | le16_to_cpu(priv->rxon_timing.beacon_interval)); |
1768 | } | |
1769 | ||
1770 | priv->rxon_timing.atim_window = 0; | |
1771 | } else { | |
1772 | priv->rxon_timing.beacon_interval = | |
bb8c093b | 1773 | iwl4965_adjust_beacon_interval(conf->beacon_int); |
b481de9c ZY |
1774 | /* TODO: we need to get atim_window from upper stack |
1775 | * for now we set to 0 */ | |
1776 | priv->rxon_timing.atim_window = 0; | |
1777 | } | |
1778 | ||
1779 | interval_tm_unit = | |
1780 | (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024); | |
1781 | result = do_div(tsf, interval_tm_unit); | |
1782 | priv->rxon_timing.beacon_init_val = | |
1783 | cpu_to_le32((u32) ((u64) interval_tm_unit - result)); | |
1784 | ||
1785 | IWL_DEBUG_ASSOC | |
1786 | ("beacon interval %d beacon timer %d beacon tim %d\n", | |
1787 | le16_to_cpu(priv->rxon_timing.beacon_interval), | |
1788 | le32_to_cpu(priv->rxon_timing.beacon_init_val), | |
1789 | le16_to_cpu(priv->rxon_timing.atim_window)); | |
1790 | } | |
1791 | ||
c79dd5b5 | 1792 | static int iwl4965_scan_initiate(struct iwl_priv *priv) |
b481de9c ZY |
1793 | { |
1794 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { | |
1795 | IWL_ERROR("APs don't scan.\n"); | |
1796 | return 0; | |
1797 | } | |
1798 | ||
fee1247a | 1799 | if (!iwl_is_ready_rf(priv)) { |
b481de9c ZY |
1800 | IWL_DEBUG_SCAN("Aborting scan due to not ready.\n"); |
1801 | return -EIO; | |
1802 | } | |
1803 | ||
1804 | if (test_bit(STATUS_SCANNING, &priv->status)) { | |
1805 | IWL_DEBUG_SCAN("Scan already in progress.\n"); | |
1806 | return -EAGAIN; | |
1807 | } | |
1808 | ||
1809 | if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
1810 | IWL_DEBUG_SCAN("Scan request while abort pending. " | |
1811 | "Queuing.\n"); | |
1812 | return -EAGAIN; | |
1813 | } | |
1814 | ||
1815 | IWL_DEBUG_INFO("Starting scan...\n"); | |
1816 | priv->scan_bands = 2; | |
1817 | set_bit(STATUS_SCANNING, &priv->status); | |
1818 | priv->scan_start = jiffies; | |
1819 | priv->scan_pass_start = priv->scan_start; | |
1820 | ||
1821 | queue_work(priv->workqueue, &priv->request_scan); | |
1822 | ||
1823 | return 0; | |
1824 | } | |
1825 | ||
b481de9c | 1826 | |
c79dd5b5 | 1827 | static void iwl4965_set_flags_for_phymode(struct iwl_priv *priv, |
8318d78a | 1828 | enum ieee80211_band band) |
b481de9c | 1829 | { |
8318d78a | 1830 | if (band == IEEE80211_BAND_5GHZ) { |
b481de9c ZY |
1831 | priv->staging_rxon.flags &= |
1832 | ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK | |
1833 | | RXON_FLG_CCK_MSK); | |
1834 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; | |
1835 | } else { | |
508e32e1 | 1836 | /* Copied from iwl4965_post_associate() */ |
b481de9c ZY |
1837 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME) |
1838 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; | |
1839 | else | |
1840 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
1841 | ||
1842 | if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) | |
1843 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
1844 | ||
1845 | priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK; | |
1846 | priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK; | |
1847 | priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK; | |
1848 | } | |
1849 | } | |
1850 | ||
1851 | /* | |
01ebd063 | 1852 | * initialize rxon structure with default values from eeprom |
b481de9c | 1853 | */ |
c79dd5b5 | 1854 | static void iwl4965_connection_init_rx_config(struct iwl_priv *priv) |
b481de9c | 1855 | { |
bf85ea4f | 1856 | const struct iwl_channel_info *ch_info; |
b481de9c ZY |
1857 | |
1858 | memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon)); | |
1859 | ||
1860 | switch (priv->iw_mode) { | |
1861 | case IEEE80211_IF_TYPE_AP: | |
1862 | priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP; | |
1863 | break; | |
1864 | ||
1865 | case IEEE80211_IF_TYPE_STA: | |
1866 | priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS; | |
1867 | priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK; | |
1868 | break; | |
1869 | ||
1870 | case IEEE80211_IF_TYPE_IBSS: | |
1871 | priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS; | |
1872 | priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK; | |
1873 | priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK | | |
1874 | RXON_FILTER_ACCEPT_GRP_MSK; | |
1875 | break; | |
1876 | ||
1877 | case IEEE80211_IF_TYPE_MNTR: | |
1878 | priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER; | |
1879 | priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK | | |
1880 | RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK; | |
1881 | break; | |
69dc5d9d TW |
1882 | default: |
1883 | IWL_ERROR("Unsupported interface type %d\n", priv->iw_mode); | |
1884 | break; | |
b481de9c ZY |
1885 | } |
1886 | ||
1887 | #if 0 | |
1888 | /* TODO: Figure out when short_preamble would be set and cache from | |
1889 | * that */ | |
1890 | if (!hw_to_local(priv->hw)->short_preamble) | |
1891 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
1892 | else | |
1893 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; | |
1894 | #endif | |
1895 | ||
8622e705 | 1896 | ch_info = iwl_get_channel_info(priv, priv->band, |
b481de9c ZY |
1897 | le16_to_cpu(priv->staging_rxon.channel)); |
1898 | ||
1899 | if (!ch_info) | |
1900 | ch_info = &priv->channel_info[0]; | |
1901 | ||
1902 | /* | |
1903 | * in some case A channels are all non IBSS | |
1904 | * in this case force B/G channel | |
1905 | */ | |
1906 | if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) && | |
1907 | !(is_channel_ibss(ch_info))) | |
1908 | ch_info = &priv->channel_info[0]; | |
1909 | ||
1910 | priv->staging_rxon.channel = cpu_to_le16(ch_info->channel); | |
8318d78a | 1911 | priv->band = ch_info->band; |
b481de9c | 1912 | |
8318d78a | 1913 | iwl4965_set_flags_for_phymode(priv, priv->band); |
b481de9c ZY |
1914 | |
1915 | priv->staging_rxon.ofdm_basic_rates = | |
1916 | (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; | |
1917 | priv->staging_rxon.cck_basic_rates = | |
1918 | (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF; | |
1919 | ||
1920 | priv->staging_rxon.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK | | |
1921 | RXON_FLG_CHANNEL_MODE_PURE_40_MSK); | |
1922 | memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN); | |
1923 | memcpy(priv->staging_rxon.wlap_bssid_addr, priv->mac_addr, ETH_ALEN); | |
1924 | priv->staging_rxon.ofdm_ht_single_stream_basic_rates = 0xff; | |
1925 | priv->staging_rxon.ofdm_ht_dual_stream_basic_rates = 0xff; | |
1926 | iwl4965_set_rxon_chain(priv); | |
1927 | } | |
1928 | ||
c79dd5b5 | 1929 | static int iwl4965_set_mode(struct iwl_priv *priv, int mode) |
b481de9c | 1930 | { |
b481de9c | 1931 | if (mode == IEEE80211_IF_TYPE_IBSS) { |
bf85ea4f | 1932 | const struct iwl_channel_info *ch_info; |
b481de9c | 1933 | |
8622e705 | 1934 | ch_info = iwl_get_channel_info(priv, |
8318d78a | 1935 | priv->band, |
b481de9c ZY |
1936 | le16_to_cpu(priv->staging_rxon.channel)); |
1937 | ||
1938 | if (!ch_info || !is_channel_ibss(ch_info)) { | |
1939 | IWL_ERROR("channel %d not IBSS channel\n", | |
1940 | le16_to_cpu(priv->staging_rxon.channel)); | |
1941 | return -EINVAL; | |
1942 | } | |
1943 | } | |
1944 | ||
b481de9c ZY |
1945 | priv->iw_mode = mode; |
1946 | ||
bb8c093b | 1947 | iwl4965_connection_init_rx_config(priv); |
b481de9c ZY |
1948 | memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN); |
1949 | ||
bf85ea4f | 1950 | iwlcore_clear_stations_table(priv); |
b481de9c | 1951 | |
fde3571f | 1952 | /* dont commit rxon if rf-kill is on*/ |
fee1247a | 1953 | if (!iwl_is_ready_rf(priv)) |
fde3571f MA |
1954 | return -EAGAIN; |
1955 | ||
1956 | cancel_delayed_work(&priv->scan_check); | |
1957 | if (iwl4965_scan_cancel_timeout(priv, 100)) { | |
1958 | IWL_WARNING("Aborted scan still in progress after 100ms\n"); | |
1959 | IWL_DEBUG_MAC80211("leaving - scan abort failed.\n"); | |
1960 | return -EAGAIN; | |
1961 | } | |
1962 | ||
bb8c093b | 1963 | iwl4965_commit_rxon(priv); |
b481de9c ZY |
1964 | |
1965 | return 0; | |
1966 | } | |
1967 | ||
c79dd5b5 | 1968 | static void iwl4965_build_tx_cmd_hwcrypto(struct iwl_priv *priv, |
b481de9c | 1969 | struct ieee80211_tx_control *ctl, |
857485c0 | 1970 | struct iwl_cmd *cmd, |
b481de9c | 1971 | struct sk_buff *skb_frag, |
deb09c43 | 1972 | int sta_id) |
b481de9c | 1973 | { |
deb09c43 | 1974 | struct iwl4965_hw_key *keyinfo = &priv->stations[sta_id].keyinfo; |
6974e363 EG |
1975 | struct iwl_wep_key *wepkey; |
1976 | int keyidx = 0; | |
1977 | ||
1978 | BUG_ON(ctl->key_idx > 3); | |
b481de9c ZY |
1979 | |
1980 | switch (keyinfo->alg) { | |
1981 | case ALG_CCMP: | |
1982 | cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM; | |
1983 | memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen); | |
8236e183 MS |
1984 | if (ctl->flags & IEEE80211_TXCTL_AMPDU) |
1985 | cmd->cmd.tx.tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK; | |
b481de9c ZY |
1986 | IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n"); |
1987 | break; | |
1988 | ||
1989 | case ALG_TKIP: | |
b481de9c | 1990 | cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP; |
2bc75089 EG |
1991 | ieee80211_get_tkip_key(keyinfo->conf, skb_frag, |
1992 | IEEE80211_TKIP_P2_KEY, cmd->cmd.tx.key); | |
1993 | IWL_DEBUG_TX("tx_cmd with tkip hwcrypto\n"); | |
b481de9c ZY |
1994 | break; |
1995 | ||
1996 | case ALG_WEP: | |
6974e363 EG |
1997 | wepkey = &priv->wep_keys[ctl->key_idx]; |
1998 | cmd->cmd.tx.sec_ctl = 0; | |
1999 | if (priv->default_wep_key) { | |
2000 | /* the WEP key was sent as static */ | |
2001 | keyidx = ctl->key_idx; | |
2002 | memcpy(&cmd->cmd.tx.key[3], wepkey->key, | |
2003 | wepkey->key_size); | |
2004 | if (wepkey->key_size == WEP_KEY_LEN_128) | |
2005 | cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128; | |
2006 | } else { | |
0211ddda EG |
2007 | /* the WEP key was sent as dynamic */ |
2008 | keyidx = keyinfo->keyidx; | |
2009 | memcpy(&cmd->cmd.tx.key[3], keyinfo->key, | |
2010 | keyinfo->keylen); | |
2011 | if (keyinfo->keylen == WEP_KEY_LEN_128) | |
2012 | cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128; | |
6974e363 | 2013 | } |
b481de9c | 2014 | |
6974e363 EG |
2015 | cmd->cmd.tx.sec_ctl |= (TX_CMD_SEC_WEP | |
2016 | (keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT); | |
b481de9c ZY |
2017 | |
2018 | IWL_DEBUG_TX("Configuring packet for WEP encryption " | |
6974e363 | 2019 | "with key %d\n", keyidx); |
b481de9c ZY |
2020 | break; |
2021 | ||
b481de9c ZY |
2022 | default: |
2023 | printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg); | |
2024 | break; | |
2025 | } | |
2026 | } | |
2027 | ||
2028 | /* | |
2029 | * handle build REPLY_TX command notification. | |
2030 | */ | |
c79dd5b5 | 2031 | static void iwl4965_build_tx_cmd_basic(struct iwl_priv *priv, |
857485c0 | 2032 | struct iwl_cmd *cmd, |
b481de9c ZY |
2033 | struct ieee80211_tx_control *ctrl, |
2034 | struct ieee80211_hdr *hdr, | |
2035 | int is_unicast, u8 std_id) | |
2036 | { | |
2037 | __le16 *qc; | |
2038 | u16 fc = le16_to_cpu(hdr->frame_control); | |
2039 | __le32 tx_flags = cmd->cmd.tx.tx_flags; | |
2040 | ||
2041 | cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
2042 | if (!(ctrl->flags & IEEE80211_TXCTL_NO_ACK)) { | |
2043 | tx_flags |= TX_CMD_FLG_ACK_MSK; | |
2044 | if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) | |
2045 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
2046 | if (ieee80211_is_probe_response(fc) && | |
2047 | !(le16_to_cpu(hdr->seq_ctrl) & 0xf)) | |
2048 | tx_flags |= TX_CMD_FLG_TSF_MSK; | |
2049 | } else { | |
2050 | tx_flags &= (~TX_CMD_FLG_ACK_MSK); | |
2051 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
2052 | } | |
2053 | ||
87e4f7df TW |
2054 | if (ieee80211_is_back_request(fc)) |
2055 | tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK; | |
2056 | ||
2057 | ||
b481de9c ZY |
2058 | cmd->cmd.tx.sta_id = std_id; |
2059 | if (ieee80211_get_morefrag(hdr)) | |
2060 | tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK; | |
2061 | ||
2062 | qc = ieee80211_get_qos_ctrl(hdr); | |
2063 | if (qc) { | |
2064 | cmd->cmd.tx.tid_tspec = (u8) (le16_to_cpu(*qc) & 0xf); | |
2065 | tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK; | |
2066 | } else | |
2067 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
2068 | ||
2069 | if (ctrl->flags & IEEE80211_TXCTL_USE_RTS_CTS) { | |
2070 | tx_flags |= TX_CMD_FLG_RTS_MSK; | |
2071 | tx_flags &= ~TX_CMD_FLG_CTS_MSK; | |
2072 | } else if (ctrl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) { | |
2073 | tx_flags &= ~TX_CMD_FLG_RTS_MSK; | |
2074 | tx_flags |= TX_CMD_FLG_CTS_MSK; | |
2075 | } | |
2076 | ||
2077 | if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK)) | |
2078 | tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK; | |
2079 | ||
2080 | tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK); | |
2081 | if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) { | |
2082 | if ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_REQ || | |
2083 | (fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_REASSOC_REQ) | |
bc434dd2 | 2084 | cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3); |
b481de9c | 2085 | else |
bc434dd2 | 2086 | cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2); |
ab53d8af | 2087 | } else { |
b481de9c | 2088 | cmd->cmd.tx.timeout.pm_frame_timeout = 0; |
ab53d8af | 2089 | } |
b481de9c ZY |
2090 | |
2091 | cmd->cmd.tx.driver_txop = 0; | |
2092 | cmd->cmd.tx.tx_flags = tx_flags; | |
2093 | cmd->cmd.tx.next_frame_len = 0; | |
2094 | } | |
19758bef TW |
2095 | static void iwl_update_tx_stats(struct iwl_priv *priv, u16 fc, u16 len) |
2096 | { | |
2097 | /* 0 - mgmt, 1 - cnt, 2 - data */ | |
2098 | int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2; | |
2099 | priv->tx_stats[idx].cnt++; | |
2100 | priv->tx_stats[idx].bytes += len; | |
2101 | } | |
6440adb5 CB |
2102 | /** |
2103 | * iwl4965_get_sta_id - Find station's index within station table | |
2104 | * | |
2105 | * If new IBSS station, create new entry in station table | |
2106 | */ | |
c79dd5b5 | 2107 | static int iwl4965_get_sta_id(struct iwl_priv *priv, |
9fbab516 | 2108 | struct ieee80211_hdr *hdr) |
b481de9c ZY |
2109 | { |
2110 | int sta_id; | |
2111 | u16 fc = le16_to_cpu(hdr->frame_control); | |
0795af57 | 2112 | DECLARE_MAC_BUF(mac); |
b481de9c | 2113 | |
6440adb5 | 2114 | /* If this frame is broadcast or management, use broadcast station id */ |
b481de9c ZY |
2115 | if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) || |
2116 | is_multicast_ether_addr(hdr->addr1)) | |
2117 | return priv->hw_setting.bcast_sta_id; | |
2118 | ||
2119 | switch (priv->iw_mode) { | |
2120 | ||
6440adb5 CB |
2121 | /* If we are a client station in a BSS network, use the special |
2122 | * AP station entry (that's the only station we communicate with) */ | |
b481de9c ZY |
2123 | case IEEE80211_IF_TYPE_STA: |
2124 | return IWL_AP_ID; | |
2125 | ||
2126 | /* If we are an AP, then find the station, or use BCAST */ | |
2127 | case IEEE80211_IF_TYPE_AP: | |
bb8c093b | 2128 | sta_id = iwl4965_hw_find_station(priv, hdr->addr1); |
b481de9c ZY |
2129 | if (sta_id != IWL_INVALID_STATION) |
2130 | return sta_id; | |
2131 | return priv->hw_setting.bcast_sta_id; | |
2132 | ||
6440adb5 CB |
2133 | /* If this frame is going out to an IBSS network, find the station, |
2134 | * or create a new station table entry */ | |
b481de9c | 2135 | case IEEE80211_IF_TYPE_IBSS: |
bb8c093b | 2136 | sta_id = iwl4965_hw_find_station(priv, hdr->addr1); |
b481de9c ZY |
2137 | if (sta_id != IWL_INVALID_STATION) |
2138 | return sta_id; | |
2139 | ||
6440adb5 | 2140 | /* Create new station table entry */ |
67d62035 RR |
2141 | sta_id = iwl4965_add_station_flags(priv, hdr->addr1, |
2142 | 0, CMD_ASYNC, NULL); | |
b481de9c ZY |
2143 | |
2144 | if (sta_id != IWL_INVALID_STATION) | |
2145 | return sta_id; | |
2146 | ||
0795af57 | 2147 | IWL_DEBUG_DROP("Station %s not in station map. " |
b481de9c | 2148 | "Defaulting to broadcast...\n", |
0795af57 | 2149 | print_mac(mac, hdr->addr1)); |
0a6857e7 | 2150 | iwl_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr)); |
b481de9c ZY |
2151 | return priv->hw_setting.bcast_sta_id; |
2152 | ||
2153 | default: | |
01ebd063 | 2154 | IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode); |
b481de9c ZY |
2155 | return priv->hw_setting.bcast_sta_id; |
2156 | } | |
2157 | } | |
2158 | ||
2159 | /* | |
2160 | * start REPLY_TX command process | |
2161 | */ | |
c79dd5b5 | 2162 | static int iwl4965_tx_skb(struct iwl_priv *priv, |
b481de9c ZY |
2163 | struct sk_buff *skb, struct ieee80211_tx_control *ctl) |
2164 | { | |
2165 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
bb8c093b | 2166 | struct iwl4965_tfd_frame *tfd; |
b481de9c ZY |
2167 | u32 *control_flags; |
2168 | int txq_id = ctl->queue; | |
bb8c093b CH |
2169 | struct iwl4965_tx_queue *txq = NULL; |
2170 | struct iwl4965_queue *q = NULL; | |
b481de9c ZY |
2171 | dma_addr_t phys_addr; |
2172 | dma_addr_t txcmd_phys; | |
87e4f7df | 2173 | dma_addr_t scratch_phys; |
857485c0 | 2174 | struct iwl_cmd *out_cmd = NULL; |
b481de9c ZY |
2175 | u16 len, idx, len_org; |
2176 | u8 id, hdr_len, unicast; | |
2177 | u8 sta_id; | |
2178 | u16 seq_number = 0; | |
2179 | u16 fc; | |
2180 | __le16 *qc; | |
2181 | u8 wait_write_ptr = 0; | |
2182 | unsigned long flags; | |
2183 | int rc; | |
2184 | ||
2185 | spin_lock_irqsave(&priv->lock, flags); | |
fee1247a | 2186 | if (iwl_is_rfkill(priv)) { |
b481de9c ZY |
2187 | IWL_DEBUG_DROP("Dropping - RF KILL\n"); |
2188 | goto drop_unlock; | |
2189 | } | |
2190 | ||
32bfd35d JB |
2191 | if (!priv->vif) { |
2192 | IWL_DEBUG_DROP("Dropping - !priv->vif\n"); | |
b481de9c ZY |
2193 | goto drop_unlock; |
2194 | } | |
2195 | ||
8318d78a | 2196 | if ((ctl->tx_rate->hw_value & 0xFF) == IWL_INVALID_RATE) { |
b481de9c ZY |
2197 | IWL_ERROR("ERROR: No TX rate available.\n"); |
2198 | goto drop_unlock; | |
2199 | } | |
2200 | ||
2201 | unicast = !is_multicast_ether_addr(hdr->addr1); | |
2202 | id = 0; | |
2203 | ||
2204 | fc = le16_to_cpu(hdr->frame_control); | |
2205 | ||
0a6857e7 | 2206 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
2207 | if (ieee80211_is_auth(fc)) |
2208 | IWL_DEBUG_TX("Sending AUTH frame\n"); | |
2209 | else if (ieee80211_is_assoc_request(fc)) | |
2210 | IWL_DEBUG_TX("Sending ASSOC frame\n"); | |
2211 | else if (ieee80211_is_reassoc_request(fc)) | |
2212 | IWL_DEBUG_TX("Sending REASSOC frame\n"); | |
2213 | #endif | |
2214 | ||
7878a5a4 | 2215 | /* drop all data frame if we are not associated */ |
76f3915b | 2216 | if (((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA) && |
3109ece1 | 2217 | (!iwl_is_associated(priv) || |
a6477249 | 2218 | ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && !priv->assoc_id) || |
76f3915b | 2219 | !priv->assoc_station_added)) { |
3109ece1 | 2220 | IWL_DEBUG_DROP("Dropping - !iwl_is_associated\n"); |
b481de9c ZY |
2221 | goto drop_unlock; |
2222 | } | |
2223 | ||
2224 | spin_unlock_irqrestore(&priv->lock, flags); | |
2225 | ||
2226 | hdr_len = ieee80211_get_hdrlen(fc); | |
6440adb5 CB |
2227 | |
2228 | /* Find (or create) index into station table for destination station */ | |
bb8c093b | 2229 | sta_id = iwl4965_get_sta_id(priv, hdr); |
b481de9c | 2230 | if (sta_id == IWL_INVALID_STATION) { |
0795af57 JP |
2231 | DECLARE_MAC_BUF(mac); |
2232 | ||
2233 | IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n", | |
2234 | print_mac(mac, hdr->addr1)); | |
b481de9c ZY |
2235 | goto drop; |
2236 | } | |
2237 | ||
2238 | IWL_DEBUG_RATE("station Id %d\n", sta_id); | |
2239 | ||
2240 | qc = ieee80211_get_qos_ctrl(hdr); | |
2241 | if (qc) { | |
2242 | u8 tid = (u8)(le16_to_cpu(*qc) & 0xf); | |
2243 | seq_number = priv->stations[sta_id].tid[tid].seq_number & | |
2244 | IEEE80211_SCTL_SEQ; | |
2245 | hdr->seq_ctrl = cpu_to_le16(seq_number) | | |
2246 | (hdr->seq_ctrl & | |
2247 | __constant_cpu_to_le16(IEEE80211_SCTL_FRAG)); | |
2248 | seq_number += 0x10; | |
c8b0e6e1 | 2249 | #ifdef CONFIG_IWL4965_HT |
b481de9c | 2250 | /* aggregation is on for this <sta,tid> */ |
fe01b477 | 2251 | if (ctl->flags & IEEE80211_TXCTL_AMPDU) |
b481de9c | 2252 | txq_id = priv->stations[sta_id].tid[tid].agg.txq_id; |
fe01b477 | 2253 | priv->stations[sta_id].tid[tid].tfds_in_queue++; |
c8b0e6e1 | 2254 | #endif /* CONFIG_IWL4965_HT */ |
b481de9c | 2255 | } |
6440adb5 CB |
2256 | |
2257 | /* Descriptor for chosen Tx queue */ | |
b481de9c ZY |
2258 | txq = &priv->txq[txq_id]; |
2259 | q = &txq->q; | |
2260 | ||
2261 | spin_lock_irqsave(&priv->lock, flags); | |
2262 | ||
6440adb5 | 2263 | /* Set up first empty TFD within this queue's circular TFD buffer */ |
fc4b6853 | 2264 | tfd = &txq->bd[q->write_ptr]; |
b481de9c ZY |
2265 | memset(tfd, 0, sizeof(*tfd)); |
2266 | control_flags = (u32 *) tfd; | |
fc4b6853 | 2267 | idx = get_cmd_index(q, q->write_ptr, 0); |
b481de9c | 2268 | |
6440adb5 | 2269 | /* Set up driver data for this TFD */ |
bb8c093b | 2270 | memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl4965_tx_info)); |
fc4b6853 TW |
2271 | txq->txb[q->write_ptr].skb[0] = skb; |
2272 | memcpy(&(txq->txb[q->write_ptr].status.control), | |
b481de9c | 2273 | ctl, sizeof(struct ieee80211_tx_control)); |
6440adb5 CB |
2274 | |
2275 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ | |
b481de9c ZY |
2276 | out_cmd = &txq->cmd[idx]; |
2277 | memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr)); | |
2278 | memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx)); | |
6440adb5 CB |
2279 | |
2280 | /* | |
2281 | * Set up the Tx-command (not MAC!) header. | |
2282 | * Store the chosen Tx queue and TFD index within the sequence field; | |
2283 | * after Tx, uCode's Tx response will return this value so driver can | |
2284 | * locate the frame within the tx queue and do post-tx processing. | |
2285 | */ | |
b481de9c ZY |
2286 | out_cmd->hdr.cmd = REPLY_TX; |
2287 | out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
fc4b6853 | 2288 | INDEX_TO_SEQ(q->write_ptr))); |
6440adb5 CB |
2289 | |
2290 | /* Copy MAC header from skb into command buffer */ | |
b481de9c ZY |
2291 | memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len); |
2292 | ||
6440adb5 CB |
2293 | /* |
2294 | * Use the first empty entry in this queue's command buffer array | |
2295 | * to contain the Tx command and MAC header concatenated together | |
2296 | * (payload data will be in another buffer). | |
2297 | * Size of this varies, due to varying MAC header length. | |
2298 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
2299 | * of the MAC header (device reads on dword boundaries). | |
2300 | * We'll tell device about this padding later. | |
2301 | */ | |
b481de9c | 2302 | len = priv->hw_setting.tx_cmd_len + |
857485c0 | 2303 | sizeof(struct iwl_cmd_header) + hdr_len; |
b481de9c ZY |
2304 | |
2305 | len_org = len; | |
2306 | len = (len + 3) & ~3; | |
2307 | ||
2308 | if (len_org != len) | |
2309 | len_org = 1; | |
2310 | else | |
2311 | len_org = 0; | |
2312 | ||
6440adb5 CB |
2313 | /* Physical address of this Tx command's header (not MAC header!), |
2314 | * within command buffer array. */ | |
857485c0 TW |
2315 | txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl_cmd) * idx + |
2316 | offsetof(struct iwl_cmd, hdr); | |
b481de9c | 2317 | |
6440adb5 CB |
2318 | /* Add buffer containing Tx command and MAC(!) header to TFD's |
2319 | * first entry */ | |
bb8c093b | 2320 | iwl4965_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len); |
b481de9c ZY |
2321 | |
2322 | if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT)) | |
deb09c43 | 2323 | iwl4965_build_tx_cmd_hwcrypto(priv, ctl, out_cmd, skb, sta_id); |
b481de9c | 2324 | |
6440adb5 CB |
2325 | /* Set up TFD's 2nd entry to point directly to remainder of skb, |
2326 | * if any (802.11 null frames have no payload). */ | |
b481de9c ZY |
2327 | len = skb->len - hdr_len; |
2328 | if (len) { | |
2329 | phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len, | |
2330 | len, PCI_DMA_TODEVICE); | |
bb8c093b | 2331 | iwl4965_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len); |
b481de9c ZY |
2332 | } |
2333 | ||
6440adb5 | 2334 | /* Tell 4965 about any 2-byte padding after MAC header */ |
b481de9c ZY |
2335 | if (len_org) |
2336 | out_cmd->cmd.tx.tx_flags |= TX_CMD_FLG_MH_PAD_MSK; | |
2337 | ||
6440adb5 | 2338 | /* Total # bytes to be transmitted */ |
b481de9c ZY |
2339 | len = (u16)skb->len; |
2340 | out_cmd->cmd.tx.len = cpu_to_le16(len); | |
2341 | ||
2342 | /* TODO need this for burst mode later on */ | |
bb8c093b | 2343 | iwl4965_build_tx_cmd_basic(priv, out_cmd, ctl, hdr, unicast, sta_id); |
b481de9c ZY |
2344 | |
2345 | /* set is_hcca to 0; it probably will never be implemented */ | |
bb8c093b | 2346 | iwl4965_hw_build_tx_cmd_rate(priv, out_cmd, ctl, hdr, sta_id, 0); |
b481de9c | 2347 | |
19758bef TW |
2348 | iwl_update_tx_stats(priv, fc, len); |
2349 | ||
857485c0 | 2350 | scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) + |
87e4f7df TW |
2351 | offsetof(struct iwl4965_tx_cmd, scratch); |
2352 | out_cmd->cmd.tx.dram_lsb_ptr = cpu_to_le32(scratch_phys); | |
2353 | out_cmd->cmd.tx.dram_msb_ptr = iwl_get_dma_hi_address(scratch_phys); | |
2354 | ||
b481de9c ZY |
2355 | if (!ieee80211_get_morefrag(hdr)) { |
2356 | txq->need_update = 1; | |
2357 | if (qc) { | |
2358 | u8 tid = (u8)(le16_to_cpu(*qc) & 0xf); | |
2359 | priv->stations[sta_id].tid[tid].seq_number = seq_number; | |
2360 | } | |
2361 | } else { | |
2362 | wait_write_ptr = 1; | |
2363 | txq->need_update = 0; | |
2364 | } | |
2365 | ||
0a6857e7 | 2366 | iwl_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload, |
b481de9c ZY |
2367 | sizeof(out_cmd->cmd.tx)); |
2368 | ||
0a6857e7 | 2369 | iwl_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr, |
b481de9c ZY |
2370 | ieee80211_get_hdrlen(fc)); |
2371 | ||
6440adb5 | 2372 | /* Set up entry for this TFD in Tx byte-count array */ |
e2a722eb | 2373 | priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, len); |
b481de9c | 2374 | |
6440adb5 | 2375 | /* Tell device the write index *just past* this latest filled TFD */ |
c54b679d | 2376 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); |
bb8c093b | 2377 | rc = iwl4965_tx_queue_update_write_ptr(priv, txq); |
b481de9c ZY |
2378 | spin_unlock_irqrestore(&priv->lock, flags); |
2379 | ||
2380 | if (rc) | |
2381 | return rc; | |
2382 | ||
bb8c093b | 2383 | if ((iwl4965_queue_space(q) < q->high_mark) |
b481de9c ZY |
2384 | && priv->mac80211_registered) { |
2385 | if (wait_write_ptr) { | |
2386 | spin_lock_irqsave(&priv->lock, flags); | |
2387 | txq->need_update = 1; | |
bb8c093b | 2388 | iwl4965_tx_queue_update_write_ptr(priv, txq); |
b481de9c ZY |
2389 | spin_unlock_irqrestore(&priv->lock, flags); |
2390 | } | |
2391 | ||
2392 | ieee80211_stop_queue(priv->hw, ctl->queue); | |
2393 | } | |
2394 | ||
2395 | return 0; | |
2396 | ||
2397 | drop_unlock: | |
2398 | spin_unlock_irqrestore(&priv->lock, flags); | |
2399 | drop: | |
2400 | return -1; | |
2401 | } | |
2402 | ||
c79dd5b5 | 2403 | static void iwl4965_set_rate(struct iwl_priv *priv) |
b481de9c | 2404 | { |
8318d78a | 2405 | const struct ieee80211_supported_band *hw = NULL; |
b481de9c ZY |
2406 | struct ieee80211_rate *rate; |
2407 | int i; | |
2408 | ||
8318d78a | 2409 | hw = iwl4965_get_hw_mode(priv, priv->band); |
c4ba9621 SA |
2410 | if (!hw) { |
2411 | IWL_ERROR("Failed to set rate: unable to get hw mode\n"); | |
2412 | return; | |
2413 | } | |
b481de9c ZY |
2414 | |
2415 | priv->active_rate = 0; | |
2416 | priv->active_rate_basic = 0; | |
2417 | ||
8318d78a JB |
2418 | for (i = 0; i < hw->n_bitrates; i++) { |
2419 | rate = &(hw->bitrates[i]); | |
2420 | if (rate->hw_value < IWL_RATE_COUNT) | |
2421 | priv->active_rate |= (1 << rate->hw_value); | |
b481de9c ZY |
2422 | } |
2423 | ||
2424 | IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n", | |
2425 | priv->active_rate, priv->active_rate_basic); | |
2426 | ||
2427 | /* | |
2428 | * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK) | |
2429 | * otherwise set it to the default of all CCK rates and 6, 12, 24 for | |
2430 | * OFDM | |
2431 | */ | |
2432 | if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK) | |
2433 | priv->staging_rxon.cck_basic_rates = | |
2434 | ((priv->active_rate_basic & | |
2435 | IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF; | |
2436 | else | |
2437 | priv->staging_rxon.cck_basic_rates = | |
2438 | (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF; | |
2439 | ||
2440 | if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK) | |
2441 | priv->staging_rxon.ofdm_basic_rates = | |
2442 | ((priv->active_rate_basic & | |
2443 | (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >> | |
2444 | IWL_FIRST_OFDM_RATE) & 0xFF; | |
2445 | else | |
2446 | priv->staging_rxon.ofdm_basic_rates = | |
2447 | (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; | |
2448 | } | |
2449 | ||
ad97edd2 | 2450 | void iwl4965_radio_kill_sw(struct iwl_priv *priv, int disable_radio) |
b481de9c ZY |
2451 | { |
2452 | unsigned long flags; | |
2453 | ||
2454 | if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status)) | |
2455 | return; | |
2456 | ||
2457 | IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n", | |
2458 | disable_radio ? "OFF" : "ON"); | |
2459 | ||
2460 | if (disable_radio) { | |
bb8c093b | 2461 | iwl4965_scan_cancel(priv); |
b481de9c ZY |
2462 | /* FIXME: This is a workaround for AP */ |
2463 | if (priv->iw_mode != IEEE80211_IF_TYPE_AP) { | |
2464 | spin_lock_irqsave(&priv->lock, flags); | |
3395f6e9 | 2465 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c ZY |
2466 | CSR_UCODE_SW_BIT_RFKILL); |
2467 | spin_unlock_irqrestore(&priv->lock, flags); | |
ad97edd2 MA |
2468 | /* call the host command only if no hw rf-kill set */ |
2469 | if (!test_bit(STATUS_RF_KILL_HW, &priv->status)) | |
2470 | iwl4965_send_card_state(priv, | |
2471 | CARD_STATE_CMD_DISABLE, | |
2472 | 0); | |
b481de9c | 2473 | set_bit(STATUS_RF_KILL_SW, &priv->status); |
ad97edd2 MA |
2474 | |
2475 | /* make sure mac80211 stop sending Tx frame */ | |
2476 | if (priv->mac80211_registered) | |
2477 | ieee80211_stop_queues(priv->hw); | |
b481de9c ZY |
2478 | } |
2479 | return; | |
2480 | } | |
2481 | ||
2482 | spin_lock_irqsave(&priv->lock, flags); | |
3395f6e9 | 2483 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
b481de9c ZY |
2484 | |
2485 | clear_bit(STATUS_RF_KILL_SW, &priv->status); | |
2486 | spin_unlock_irqrestore(&priv->lock, flags); | |
2487 | ||
2488 | /* wake up ucode */ | |
2489 | msleep(10); | |
2490 | ||
2491 | spin_lock_irqsave(&priv->lock, flags); | |
3395f6e9 TW |
2492 | iwl_read32(priv, CSR_UCODE_DRV_GP1); |
2493 | if (!iwl_grab_nic_access(priv)) | |
2494 | iwl_release_nic_access(priv); | |
b481de9c ZY |
2495 | spin_unlock_irqrestore(&priv->lock, flags); |
2496 | ||
2497 | if (test_bit(STATUS_RF_KILL_HW, &priv->status)) { | |
2498 | IWL_DEBUG_RF_KILL("Can not turn radio back on - " | |
2499 | "disabled by HW switch\n"); | |
2500 | return; | |
2501 | } | |
2502 | ||
2503 | queue_work(priv->workqueue, &priv->restart); | |
2504 | return; | |
2505 | } | |
2506 | ||
c79dd5b5 | 2507 | void iwl4965_set_decrypted_flag(struct iwl_priv *priv, struct sk_buff *skb, |
b481de9c ZY |
2508 | u32 decrypt_res, struct ieee80211_rx_status *stats) |
2509 | { | |
2510 | u16 fc = | |
2511 | le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control); | |
2512 | ||
2513 | if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK) | |
2514 | return; | |
2515 | ||
2516 | if (!(fc & IEEE80211_FCTL_PROTECTED)) | |
2517 | return; | |
2518 | ||
2519 | IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res); | |
2520 | switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) { | |
2521 | case RX_RES_STATUS_SEC_TYPE_TKIP: | |
17e476b8 EG |
2522 | /* The uCode has got a bad phase 1 Key, pushes the packet. |
2523 | * Decryption will be done in SW. */ | |
2524 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
2525 | RX_RES_STATUS_BAD_KEY_TTAK) | |
2526 | break; | |
2527 | ||
b481de9c ZY |
2528 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == |
2529 | RX_RES_STATUS_BAD_ICV_MIC) | |
2530 | stats->flag |= RX_FLAG_MMIC_ERROR; | |
2531 | case RX_RES_STATUS_SEC_TYPE_WEP: | |
2532 | case RX_RES_STATUS_SEC_TYPE_CCMP: | |
2533 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
2534 | RX_RES_STATUS_DECRYPT_OK) { | |
2535 | IWL_DEBUG_RX("hw decrypt successfully!!!\n"); | |
2536 | stats->flag |= RX_FLAG_DECRYPTED; | |
2537 | } | |
2538 | break; | |
2539 | ||
2540 | default: | |
2541 | break; | |
2542 | } | |
2543 | } | |
2544 | ||
b481de9c ZY |
2545 | |
2546 | #define IWL_PACKET_RETRY_TIME HZ | |
2547 | ||
c79dd5b5 | 2548 | int iwl4965_is_duplicate_packet(struct iwl_priv *priv, struct ieee80211_hdr *header) |
b481de9c ZY |
2549 | { |
2550 | u16 sc = le16_to_cpu(header->seq_ctrl); | |
2551 | u16 seq = (sc & IEEE80211_SCTL_SEQ) >> 4; | |
2552 | u16 frag = sc & IEEE80211_SCTL_FRAG; | |
2553 | u16 *last_seq, *last_frag; | |
2554 | unsigned long *last_time; | |
2555 | ||
2556 | switch (priv->iw_mode) { | |
2557 | case IEEE80211_IF_TYPE_IBSS:{ | |
2558 | struct list_head *p; | |
bb8c093b | 2559 | struct iwl4965_ibss_seq *entry = NULL; |
b481de9c ZY |
2560 | u8 *mac = header->addr2; |
2561 | int index = mac[5] & (IWL_IBSS_MAC_HASH_SIZE - 1); | |
2562 | ||
2563 | __list_for_each(p, &priv->ibss_mac_hash[index]) { | |
bb8c093b | 2564 | entry = list_entry(p, struct iwl4965_ibss_seq, list); |
b481de9c ZY |
2565 | if (!compare_ether_addr(entry->mac, mac)) |
2566 | break; | |
2567 | } | |
2568 | if (p == &priv->ibss_mac_hash[index]) { | |
2569 | entry = kzalloc(sizeof(*entry), GFP_ATOMIC); | |
2570 | if (!entry) { | |
bc434dd2 | 2571 | IWL_ERROR("Cannot malloc new mac entry\n"); |
b481de9c ZY |
2572 | return 0; |
2573 | } | |
2574 | memcpy(entry->mac, mac, ETH_ALEN); | |
2575 | entry->seq_num = seq; | |
2576 | entry->frag_num = frag; | |
2577 | entry->packet_time = jiffies; | |
bc434dd2 | 2578 | list_add(&entry->list, &priv->ibss_mac_hash[index]); |
b481de9c ZY |
2579 | return 0; |
2580 | } | |
2581 | last_seq = &entry->seq_num; | |
2582 | last_frag = &entry->frag_num; | |
2583 | last_time = &entry->packet_time; | |
2584 | break; | |
2585 | } | |
2586 | case IEEE80211_IF_TYPE_STA: | |
2587 | last_seq = &priv->last_seq_num; | |
2588 | last_frag = &priv->last_frag_num; | |
2589 | last_time = &priv->last_packet_time; | |
2590 | break; | |
2591 | default: | |
2592 | return 0; | |
2593 | } | |
2594 | if ((*last_seq == seq) && | |
2595 | time_after(*last_time + IWL_PACKET_RETRY_TIME, jiffies)) { | |
2596 | if (*last_frag == frag) | |
2597 | goto drop; | |
2598 | if (*last_frag + 1 != frag) | |
2599 | /* out-of-order fragment */ | |
2600 | goto drop; | |
2601 | } else | |
2602 | *last_seq = seq; | |
2603 | ||
2604 | *last_frag = frag; | |
2605 | *last_time = jiffies; | |
2606 | return 0; | |
2607 | ||
2608 | drop: | |
2609 | return 1; | |
2610 | } | |
2611 | ||
c8b0e6e1 | 2612 | #ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT |
b481de9c ZY |
2613 | |
2614 | #include "iwl-spectrum.h" | |
2615 | ||
2616 | #define BEACON_TIME_MASK_LOW 0x00FFFFFF | |
2617 | #define BEACON_TIME_MASK_HIGH 0xFF000000 | |
2618 | #define TIME_UNIT 1024 | |
2619 | ||
2620 | /* | |
2621 | * extended beacon time format | |
2622 | * time in usec will be changed into a 32-bit value in 8:24 format | |
2623 | * the high 1 byte is the beacon counts | |
2624 | * the lower 3 bytes is the time in usec within one beacon interval | |
2625 | */ | |
2626 | ||
bb8c093b | 2627 | static u32 iwl4965_usecs_to_beacons(u32 usec, u32 beacon_interval) |
b481de9c ZY |
2628 | { |
2629 | u32 quot; | |
2630 | u32 rem; | |
2631 | u32 interval = beacon_interval * 1024; | |
2632 | ||
2633 | if (!interval || !usec) | |
2634 | return 0; | |
2635 | ||
2636 | quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24); | |
2637 | rem = (usec % interval) & BEACON_TIME_MASK_LOW; | |
2638 | ||
2639 | return (quot << 24) + rem; | |
2640 | } | |
2641 | ||
2642 | /* base is usually what we get from ucode with each received frame, | |
2643 | * the same as HW timer counter counting down | |
2644 | */ | |
2645 | ||
bb8c093b | 2646 | static __le32 iwl4965_add_beacon_time(u32 base, u32 addon, u32 beacon_interval) |
b481de9c ZY |
2647 | { |
2648 | u32 base_low = base & BEACON_TIME_MASK_LOW; | |
2649 | u32 addon_low = addon & BEACON_TIME_MASK_LOW; | |
2650 | u32 interval = beacon_interval * TIME_UNIT; | |
2651 | u32 res = (base & BEACON_TIME_MASK_HIGH) + | |
2652 | (addon & BEACON_TIME_MASK_HIGH); | |
2653 | ||
2654 | if (base_low > addon_low) | |
2655 | res += base_low - addon_low; | |
2656 | else if (base_low < addon_low) { | |
2657 | res += interval + base_low - addon_low; | |
2658 | res += (1 << 24); | |
2659 | } else | |
2660 | res += (1 << 24); | |
2661 | ||
2662 | return cpu_to_le32(res); | |
2663 | } | |
2664 | ||
c79dd5b5 | 2665 | static int iwl4965_get_measurement(struct iwl_priv *priv, |
b481de9c ZY |
2666 | struct ieee80211_measurement_params *params, |
2667 | u8 type) | |
2668 | { | |
bb8c093b CH |
2669 | struct iwl4965_spectrum_cmd spectrum; |
2670 | struct iwl4965_rx_packet *res; | |
857485c0 | 2671 | struct iwl_host_cmd cmd = { |
b481de9c ZY |
2672 | .id = REPLY_SPECTRUM_MEASUREMENT_CMD, |
2673 | .data = (void *)&spectrum, | |
2674 | .meta.flags = CMD_WANT_SKB, | |
2675 | }; | |
2676 | u32 add_time = le64_to_cpu(params->start_time); | |
2677 | int rc; | |
2678 | int spectrum_resp_status; | |
2679 | int duration = le16_to_cpu(params->duration); | |
2680 | ||
3109ece1 | 2681 | if (iwl_is_associated(priv)) |
b481de9c | 2682 | add_time = |
bb8c093b | 2683 | iwl4965_usecs_to_beacons( |
b481de9c ZY |
2684 | le64_to_cpu(params->start_time) - priv->last_tsf, |
2685 | le16_to_cpu(priv->rxon_timing.beacon_interval)); | |
2686 | ||
2687 | memset(&spectrum, 0, sizeof(spectrum)); | |
2688 | ||
2689 | spectrum.channel_count = cpu_to_le16(1); | |
2690 | spectrum.flags = | |
2691 | RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK; | |
2692 | spectrum.filter_flags = MEASUREMENT_FILTER_FLAG; | |
2693 | cmd.len = sizeof(spectrum); | |
2694 | spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len)); | |
2695 | ||
3109ece1 | 2696 | if (iwl_is_associated(priv)) |
b481de9c | 2697 | spectrum.start_time = |
bb8c093b | 2698 | iwl4965_add_beacon_time(priv->last_beacon_time, |
b481de9c ZY |
2699 | add_time, |
2700 | le16_to_cpu(priv->rxon_timing.beacon_interval)); | |
2701 | else | |
2702 | spectrum.start_time = 0; | |
2703 | ||
2704 | spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT); | |
2705 | spectrum.channels[0].channel = params->channel; | |
2706 | spectrum.channels[0].type = type; | |
2707 | if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK) | |
2708 | spectrum.flags |= RXON_FLG_BAND_24G_MSK | | |
2709 | RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK; | |
2710 | ||
857485c0 | 2711 | rc = iwl_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
2712 | if (rc) |
2713 | return rc; | |
2714 | ||
bb8c093b | 2715 | res = (struct iwl4965_rx_packet *)cmd.meta.u.skb->data; |
b481de9c ZY |
2716 | if (res->hdr.flags & IWL_CMD_FAILED_MSK) { |
2717 | IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n"); | |
2718 | rc = -EIO; | |
2719 | } | |
2720 | ||
2721 | spectrum_resp_status = le16_to_cpu(res->u.spectrum.status); | |
2722 | switch (spectrum_resp_status) { | |
2723 | case 0: /* Command will be handled */ | |
2724 | if (res->u.spectrum.id != 0xff) { | |
2725 | IWL_DEBUG_INFO | |
2726 | ("Replaced existing measurement: %d\n", | |
2727 | res->u.spectrum.id); | |
2728 | priv->measurement_status &= ~MEASUREMENT_READY; | |
2729 | } | |
2730 | priv->measurement_status |= MEASUREMENT_ACTIVE; | |
2731 | rc = 0; | |
2732 | break; | |
2733 | ||
2734 | case 1: /* Command will not be handled */ | |
2735 | rc = -EAGAIN; | |
2736 | break; | |
2737 | } | |
2738 | ||
2739 | dev_kfree_skb_any(cmd.meta.u.skb); | |
2740 | ||
2741 | return rc; | |
2742 | } | |
2743 | #endif | |
2744 | ||
c79dd5b5 | 2745 | static void iwl4965_txstatus_to_ieee(struct iwl_priv *priv, |
bb8c093b | 2746 | struct iwl4965_tx_info *tx_sta) |
b481de9c ZY |
2747 | { |
2748 | ||
2749 | tx_sta->status.ack_signal = 0; | |
2750 | tx_sta->status.excessive_retries = 0; | |
2751 | tx_sta->status.queue_length = 0; | |
2752 | tx_sta->status.queue_number = 0; | |
2753 | ||
2754 | if (in_interrupt()) | |
2755 | ieee80211_tx_status_irqsafe(priv->hw, | |
2756 | tx_sta->skb[0], &(tx_sta->status)); | |
2757 | else | |
2758 | ieee80211_tx_status(priv->hw, | |
2759 | tx_sta->skb[0], &(tx_sta->status)); | |
2760 | ||
2761 | tx_sta->skb[0] = NULL; | |
2762 | } | |
2763 | ||
2764 | /** | |
6440adb5 | 2765 | * iwl4965_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd |
b481de9c | 2766 | * |
6440adb5 CB |
2767 | * When FW advances 'R' index, all entries between old and new 'R' index |
2768 | * need to be reclaimed. As result, some free space forms. If there is | |
2769 | * enough free space (> low mark), wake the stack that feeds us. | |
b481de9c | 2770 | */ |
c79dd5b5 | 2771 | int iwl4965_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index) |
b481de9c | 2772 | { |
bb8c093b CH |
2773 | struct iwl4965_tx_queue *txq = &priv->txq[txq_id]; |
2774 | struct iwl4965_queue *q = &txq->q; | |
b481de9c ZY |
2775 | int nfreed = 0; |
2776 | ||
2777 | if ((index >= q->n_bd) || (x2_queue_used(q, index) == 0)) { | |
2778 | IWL_ERROR("Read index for DMA queue txq id (%d), index %d, " | |
2779 | "is out of range [0-%d] %d %d.\n", txq_id, | |
fc4b6853 | 2780 | index, q->n_bd, q->write_ptr, q->read_ptr); |
b481de9c ZY |
2781 | return 0; |
2782 | } | |
2783 | ||
c54b679d | 2784 | for (index = iwl_queue_inc_wrap(index, q->n_bd); |
fc4b6853 | 2785 | q->read_ptr != index; |
c54b679d | 2786 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { |
b481de9c | 2787 | if (txq_id != IWL_CMD_QUEUE_NUM) { |
bb8c093b | 2788 | iwl4965_txstatus_to_ieee(priv, |
fc4b6853 | 2789 | &(txq->txb[txq->q.read_ptr])); |
bb8c093b | 2790 | iwl4965_hw_txq_free_tfd(priv, txq); |
b481de9c ZY |
2791 | } else if (nfreed > 1) { |
2792 | IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index, | |
fc4b6853 | 2793 | q->write_ptr, q->read_ptr); |
b481de9c ZY |
2794 | queue_work(priv->workqueue, &priv->restart); |
2795 | } | |
2796 | nfreed++; | |
2797 | } | |
2798 | ||
fe01b477 | 2799 | /* if (iwl4965_queue_space(q) > q->low_mark && (txq_id >= 0) && |
b481de9c ZY |
2800 | (txq_id != IWL_CMD_QUEUE_NUM) && |
2801 | priv->mac80211_registered) | |
fe01b477 | 2802 | ieee80211_wake_queue(priv->hw, txq_id); */ |
b481de9c ZY |
2803 | |
2804 | ||
2805 | return nfreed; | |
2806 | } | |
2807 | ||
bb8c093b | 2808 | static int iwl4965_is_tx_success(u32 status) |
b481de9c ZY |
2809 | { |
2810 | status &= TX_STATUS_MSK; | |
2811 | return (status == TX_STATUS_SUCCESS) | |
2812 | || (status == TX_STATUS_DIRECT_DONE); | |
2813 | } | |
2814 | ||
2815 | /****************************************************************************** | |
2816 | * | |
2817 | * Generic RX handler implementations | |
2818 | * | |
2819 | ******************************************************************************/ | |
c8b0e6e1 | 2820 | #ifdef CONFIG_IWL4965_HT |
b481de9c | 2821 | |
c79dd5b5 | 2822 | static inline int iwl4965_get_ra_sta_id(struct iwl_priv *priv, |
b481de9c ZY |
2823 | struct ieee80211_hdr *hdr) |
2824 | { | |
2825 | if (priv->iw_mode == IEEE80211_IF_TYPE_STA) | |
2826 | return IWL_AP_ID; | |
2827 | else { | |
2828 | u8 *da = ieee80211_get_DA(hdr); | |
bb8c093b | 2829 | return iwl4965_hw_find_station(priv, da); |
b481de9c ZY |
2830 | } |
2831 | } | |
2832 | ||
bb8c093b | 2833 | static struct ieee80211_hdr *iwl4965_tx_queue_get_hdr( |
c79dd5b5 | 2834 | struct iwl_priv *priv, int txq_id, int idx) |
b481de9c ZY |
2835 | { |
2836 | if (priv->txq[txq_id].txb[idx].skb[0]) | |
2837 | return (struct ieee80211_hdr *)priv->txq[txq_id]. | |
2838 | txb[idx].skb[0]->data; | |
2839 | return NULL; | |
2840 | } | |
2841 | ||
bb8c093b | 2842 | static inline u32 iwl4965_get_scd_ssn(struct iwl4965_tx_resp *tx_resp) |
b481de9c ZY |
2843 | { |
2844 | __le32 *scd_ssn = (__le32 *)((u32 *)&tx_resp->status + | |
2845 | tx_resp->frame_count); | |
2846 | return le32_to_cpu(*scd_ssn) & MAX_SN; | |
2847 | ||
2848 | } | |
6440adb5 CB |
2849 | |
2850 | /** | |
2851 | * iwl4965_tx_status_reply_tx - Handle Tx rspnse for frames in aggregation queue | |
2852 | */ | |
c79dd5b5 | 2853 | static int iwl4965_tx_status_reply_tx(struct iwl_priv *priv, |
bb8c093b | 2854 | struct iwl4965_ht_agg *agg, |
fe01b477 | 2855 | struct iwl4965_tx_resp_agg *tx_resp, |
b481de9c ZY |
2856 | u16 start_idx) |
2857 | { | |
fe01b477 RR |
2858 | u16 status; |
2859 | struct agg_tx_status *frame_status = &tx_resp->status; | |
b481de9c ZY |
2860 | struct ieee80211_tx_status *tx_status = NULL; |
2861 | struct ieee80211_hdr *hdr = NULL; | |
2862 | int i, sh; | |
2863 | int txq_id, idx; | |
2864 | u16 seq; | |
2865 | ||
2866 | if (agg->wait_for_ba) | |
6440adb5 | 2867 | IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n"); |
b481de9c ZY |
2868 | |
2869 | agg->frame_count = tx_resp->frame_count; | |
2870 | agg->start_idx = start_idx; | |
2871 | agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags); | |
fe01b477 | 2872 | agg->bitmap = 0; |
b481de9c | 2873 | |
6440adb5 | 2874 | /* # frames attempted by Tx command */ |
b481de9c | 2875 | if (agg->frame_count == 1) { |
6440adb5 | 2876 | /* Only one frame was attempted; no block-ack will arrive */ |
fe01b477 RR |
2877 | status = le16_to_cpu(frame_status[0].status); |
2878 | seq = le16_to_cpu(frame_status[0].sequence); | |
2879 | idx = SEQ_TO_INDEX(seq); | |
2880 | txq_id = SEQ_TO_QUEUE(seq); | |
b481de9c | 2881 | |
b481de9c | 2882 | /* FIXME: code repetition */ |
fe01b477 RR |
2883 | IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n", |
2884 | agg->frame_count, agg->start_idx, idx); | |
b481de9c | 2885 | |
fe01b477 | 2886 | tx_status = &(priv->txq[txq_id].txb[idx].status); |
b481de9c ZY |
2887 | tx_status->retry_count = tx_resp->failure_frame; |
2888 | tx_status->queue_number = status & 0xff; | |
fe01b477 RR |
2889 | tx_status->queue_length = tx_resp->failure_rts; |
2890 | tx_status->control.flags &= ~IEEE80211_TXCTL_AMPDU; | |
bb8c093b | 2891 | tx_status->flags = iwl4965_is_tx_success(status)? |
b481de9c | 2892 | IEEE80211_TX_STATUS_ACK : 0; |
4c424e4c RR |
2893 | iwl4965_hwrate_to_tx_control(priv, |
2894 | le32_to_cpu(tx_resp->rate_n_flags), | |
2895 | &tx_status->control); | |
b481de9c ZY |
2896 | /* FIXME: code repetition end */ |
2897 | ||
2898 | IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n", | |
2899 | status & 0xff, tx_resp->failure_frame); | |
2900 | IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", | |
bb8c093b | 2901 | iwl4965_hw_get_rate_n_flags(tx_resp->rate_n_flags)); |
b481de9c ZY |
2902 | |
2903 | agg->wait_for_ba = 0; | |
2904 | } else { | |
6440adb5 | 2905 | /* Two or more frames were attempted; expect block-ack */ |
b481de9c ZY |
2906 | u64 bitmap = 0; |
2907 | int start = agg->start_idx; | |
2908 | ||
6440adb5 | 2909 | /* Construct bit-map of pending frames within Tx window */ |
b481de9c ZY |
2910 | for (i = 0; i < agg->frame_count; i++) { |
2911 | u16 sc; | |
fe01b477 RR |
2912 | status = le16_to_cpu(frame_status[i].status); |
2913 | seq = le16_to_cpu(frame_status[i].sequence); | |
b481de9c ZY |
2914 | idx = SEQ_TO_INDEX(seq); |
2915 | txq_id = SEQ_TO_QUEUE(seq); | |
2916 | ||
2917 | if (status & (AGG_TX_STATE_FEW_BYTES_MSK | | |
2918 | AGG_TX_STATE_ABORT_MSK)) | |
2919 | continue; | |
2920 | ||
2921 | IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n", | |
2922 | agg->frame_count, txq_id, idx); | |
2923 | ||
bb8c093b | 2924 | hdr = iwl4965_tx_queue_get_hdr(priv, txq_id, idx); |
b481de9c ZY |
2925 | |
2926 | sc = le16_to_cpu(hdr->seq_ctrl); | |
2927 | if (idx != (SEQ_TO_SN(sc) & 0xff)) { | |
2928 | IWL_ERROR("BUG_ON idx doesn't match seq control" | |
2929 | " idx=%d, seq_idx=%d, seq=%d\n", | |
2930 | idx, SEQ_TO_SN(sc), | |
2931 | hdr->seq_ctrl); | |
2932 | return -1; | |
2933 | } | |
2934 | ||
2935 | IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n", | |
2936 | i, idx, SEQ_TO_SN(sc)); | |
2937 | ||
2938 | sh = idx - start; | |
2939 | if (sh > 64) { | |
2940 | sh = (start - idx) + 0xff; | |
2941 | bitmap = bitmap << sh; | |
2942 | sh = 0; | |
2943 | start = idx; | |
2944 | } else if (sh < -64) | |
2945 | sh = 0xff - (start - idx); | |
2946 | else if (sh < 0) { | |
2947 | sh = start - idx; | |
2948 | start = idx; | |
2949 | bitmap = bitmap << sh; | |
2950 | sh = 0; | |
2951 | } | |
2952 | bitmap |= (1 << sh); | |
2953 | IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%x\n", | |
2954 | start, (u32)(bitmap & 0xFFFFFFFF)); | |
2955 | } | |
2956 | ||
fe01b477 | 2957 | agg->bitmap = bitmap; |
b481de9c ZY |
2958 | agg->start_idx = start; |
2959 | agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags); | |
fe01b477 | 2960 | IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n", |
b481de9c | 2961 | agg->frame_count, agg->start_idx, |
06501d29 | 2962 | (unsigned long long)agg->bitmap); |
b481de9c ZY |
2963 | |
2964 | if (bitmap) | |
2965 | agg->wait_for_ba = 1; | |
2966 | } | |
2967 | return 0; | |
2968 | } | |
2969 | #endif | |
b481de9c | 2970 | |
6440adb5 CB |
2971 | /** |
2972 | * iwl4965_rx_reply_tx - Handle standard (non-aggregation) Tx response | |
2973 | */ | |
c79dd5b5 | 2974 | static void iwl4965_rx_reply_tx(struct iwl_priv *priv, |
bb8c093b | 2975 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 2976 | { |
bb8c093b | 2977 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
2978 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
2979 | int txq_id = SEQ_TO_QUEUE(sequence); | |
2980 | int index = SEQ_TO_INDEX(sequence); | |
bb8c093b | 2981 | struct iwl4965_tx_queue *txq = &priv->txq[txq_id]; |
b481de9c | 2982 | struct ieee80211_tx_status *tx_status; |
bb8c093b | 2983 | struct iwl4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; |
b481de9c | 2984 | u32 status = le32_to_cpu(tx_resp->status); |
c8b0e6e1 | 2985 | #ifdef CONFIG_IWL4965_HT |
fe01b477 RR |
2986 | int tid = MAX_TID_COUNT, sta_id = IWL_INVALID_STATION; |
2987 | struct ieee80211_hdr *hdr; | |
2988 | __le16 *qc; | |
b481de9c ZY |
2989 | #endif |
2990 | ||
2991 | if ((index >= txq->q.n_bd) || (x2_queue_used(&txq->q, index) == 0)) { | |
2992 | IWL_ERROR("Read index for DMA queue txq_id (%d) index %d " | |
2993 | "is out of range [0-%d] %d %d\n", txq_id, | |
fc4b6853 TW |
2994 | index, txq->q.n_bd, txq->q.write_ptr, |
2995 | txq->q.read_ptr); | |
b481de9c ZY |
2996 | return; |
2997 | } | |
2998 | ||
c8b0e6e1 | 2999 | #ifdef CONFIG_IWL4965_HT |
fe01b477 RR |
3000 | hdr = iwl4965_tx_queue_get_hdr(priv, txq_id, index); |
3001 | qc = ieee80211_get_qos_ctrl(hdr); | |
3002 | ||
3003 | if (qc) | |
3004 | tid = le16_to_cpu(*qc) & 0xf; | |
3005 | ||
3006 | sta_id = iwl4965_get_ra_sta_id(priv, hdr); | |
3007 | if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) { | |
3008 | IWL_ERROR("Station not known\n"); | |
3009 | return; | |
3010 | } | |
3011 | ||
b481de9c | 3012 | if (txq->sched_retry) { |
bb8c093b | 3013 | const u32 scd_ssn = iwl4965_get_scd_ssn(tx_resp); |
bb8c093b | 3014 | struct iwl4965_ht_agg *agg = NULL; |
b481de9c | 3015 | |
fe01b477 | 3016 | if (!qc) |
b481de9c | 3017 | return; |
b481de9c ZY |
3018 | |
3019 | agg = &priv->stations[sta_id].tid[tid].agg; | |
3020 | ||
fe01b477 RR |
3021 | iwl4965_tx_status_reply_tx(priv, agg, |
3022 | (struct iwl4965_tx_resp_agg *)tx_resp, index); | |
b481de9c ZY |
3023 | |
3024 | if ((tx_resp->frame_count == 1) && | |
bb8c093b | 3025 | !iwl4965_is_tx_success(status)) { |
b481de9c ZY |
3026 | /* TODO: send BAR */ |
3027 | } | |
3028 | ||
fe01b477 RR |
3029 | if (txq->q.read_ptr != (scd_ssn & 0xff)) { |
3030 | int freed; | |
c54b679d | 3031 | index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd); |
b481de9c ZY |
3032 | IWL_DEBUG_TX_REPLY("Retry scheduler reclaim scd_ssn " |
3033 | "%d index %d\n", scd_ssn , index); | |
fe01b477 RR |
3034 | freed = iwl4965_tx_queue_reclaim(priv, txq_id, index); |
3035 | priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; | |
3036 | ||
3037 | if (iwl4965_queue_space(&txq->q) > txq->q.low_mark && | |
3038 | txq_id >= 0 && priv->mac80211_registered && | |
3039 | agg->state != IWL_EMPTYING_HW_QUEUE_DELBA) | |
3040 | ieee80211_wake_queue(priv->hw, txq_id); | |
3041 | ||
3042 | iwl4965_check_empty_hw_queue(priv, sta_id, tid, txq_id); | |
b481de9c ZY |
3043 | } |
3044 | } else { | |
c8b0e6e1 | 3045 | #endif /* CONFIG_IWL4965_HT */ |
fc4b6853 | 3046 | tx_status = &(txq->txb[txq->q.read_ptr].status); |
b481de9c ZY |
3047 | |
3048 | tx_status->retry_count = tx_resp->failure_frame; | |
3049 | tx_status->queue_number = status; | |
3050 | tx_status->queue_length = tx_resp->bt_kill_count; | |
3051 | tx_status->queue_length |= tx_resp->failure_rts; | |
b481de9c | 3052 | tx_status->flags = |
bb8c093b | 3053 | iwl4965_is_tx_success(status) ? IEEE80211_TX_STATUS_ACK : 0; |
4c424e4c RR |
3054 | iwl4965_hwrate_to_tx_control(priv, le32_to_cpu(tx_resp->rate_n_flags), |
3055 | &tx_status->control); | |
b481de9c | 3056 | |
b481de9c | 3057 | IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) rate_n_flags 0x%x " |
bb8c093b | 3058 | "retries %d\n", txq_id, iwl4965_get_tx_fail_reason(status), |
b481de9c ZY |
3059 | status, le32_to_cpu(tx_resp->rate_n_flags), |
3060 | tx_resp->failure_frame); | |
3061 | ||
3062 | IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index); | |
fe01b477 RR |
3063 | if (index != -1) { |
3064 | int freed = iwl4965_tx_queue_reclaim(priv, txq_id, index); | |
3065 | #ifdef CONFIG_IWL4965_HT | |
3066 | if (tid != MAX_TID_COUNT) | |
3067 | priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; | |
3068 | if (iwl4965_queue_space(&txq->q) > txq->q.low_mark && | |
3069 | (txq_id >= 0) && | |
3070 | priv->mac80211_registered) | |
3071 | ieee80211_wake_queue(priv->hw, txq_id); | |
3072 | if (tid != MAX_TID_COUNT) | |
3073 | iwl4965_check_empty_hw_queue(priv, sta_id, tid, txq_id); | |
3074 | #endif | |
3075 | } | |
c8b0e6e1 | 3076 | #ifdef CONFIG_IWL4965_HT |
b481de9c | 3077 | } |
c8b0e6e1 | 3078 | #endif /* CONFIG_IWL4965_HT */ |
b481de9c ZY |
3079 | |
3080 | if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK)) | |
3081 | IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n"); | |
3082 | } | |
3083 | ||
3084 | ||
c79dd5b5 | 3085 | static void iwl4965_rx_reply_alive(struct iwl_priv *priv, |
bb8c093b | 3086 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3087 | { |
bb8c093b CH |
3088 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
3089 | struct iwl4965_alive_resp *palive; | |
b481de9c ZY |
3090 | struct delayed_work *pwork; |
3091 | ||
3092 | palive = &pkt->u.alive_frame; | |
3093 | ||
3094 | IWL_DEBUG_INFO("Alive ucode status 0x%08X revision " | |
3095 | "0x%01X 0x%01X\n", | |
3096 | palive->is_valid, palive->ver_type, | |
3097 | palive->ver_subtype); | |
3098 | ||
3099 | if (palive->ver_subtype == INITIALIZE_SUBTYPE) { | |
3100 | IWL_DEBUG_INFO("Initialization Alive received.\n"); | |
3101 | memcpy(&priv->card_alive_init, | |
3102 | &pkt->u.alive_frame, | |
bb8c093b | 3103 | sizeof(struct iwl4965_init_alive_resp)); |
b481de9c ZY |
3104 | pwork = &priv->init_alive_start; |
3105 | } else { | |
3106 | IWL_DEBUG_INFO("Runtime Alive received.\n"); | |
3107 | memcpy(&priv->card_alive, &pkt->u.alive_frame, | |
bb8c093b | 3108 | sizeof(struct iwl4965_alive_resp)); |
b481de9c ZY |
3109 | pwork = &priv->alive_start; |
3110 | } | |
3111 | ||
3112 | /* We delay the ALIVE response by 5ms to | |
3113 | * give the HW RF Kill time to activate... */ | |
3114 | if (palive->is_valid == UCODE_VALID_OK) | |
3115 | queue_delayed_work(priv->workqueue, pwork, | |
3116 | msecs_to_jiffies(5)); | |
3117 | else | |
3118 | IWL_WARNING("uCode did not respond OK.\n"); | |
3119 | } | |
3120 | ||
c79dd5b5 | 3121 | static void iwl4965_rx_reply_add_sta(struct iwl_priv *priv, |
bb8c093b | 3122 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3123 | { |
bb8c093b | 3124 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
3125 | |
3126 | IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status); | |
3127 | return; | |
3128 | } | |
3129 | ||
c79dd5b5 | 3130 | static void iwl4965_rx_reply_error(struct iwl_priv *priv, |
bb8c093b | 3131 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3132 | { |
bb8c093b | 3133 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
3134 | |
3135 | IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) " | |
3136 | "seq 0x%04X ser 0x%08X\n", | |
3137 | le32_to_cpu(pkt->u.err_resp.error_type), | |
3138 | get_cmd_string(pkt->u.err_resp.cmd_id), | |
3139 | pkt->u.err_resp.cmd_id, | |
3140 | le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num), | |
3141 | le32_to_cpu(pkt->u.err_resp.error_info)); | |
3142 | } | |
3143 | ||
3144 | #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x | |
3145 | ||
c79dd5b5 | 3146 | static void iwl4965_rx_csa(struct iwl_priv *priv, struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3147 | { |
bb8c093b CH |
3148 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
3149 | struct iwl4965_rxon_cmd *rxon = (void *)&priv->active_rxon; | |
3150 | struct iwl4965_csa_notification *csa = &(pkt->u.csa_notif); | |
b481de9c ZY |
3151 | IWL_DEBUG_11H("CSA notif: channel %d, status %d\n", |
3152 | le16_to_cpu(csa->channel), le32_to_cpu(csa->status)); | |
3153 | rxon->channel = csa->channel; | |
3154 | priv->staging_rxon.channel = csa->channel; | |
3155 | } | |
3156 | ||
c79dd5b5 | 3157 | static void iwl4965_rx_spectrum_measure_notif(struct iwl_priv *priv, |
bb8c093b | 3158 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3159 | { |
c8b0e6e1 | 3160 | #ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT |
bb8c093b CH |
3161 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
3162 | struct iwl4965_spectrum_notification *report = &(pkt->u.spectrum_notif); | |
b481de9c ZY |
3163 | |
3164 | if (!report->state) { | |
3165 | IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO, | |
3166 | "Spectrum Measure Notification: Start\n"); | |
3167 | return; | |
3168 | } | |
3169 | ||
3170 | memcpy(&priv->measure_report, report, sizeof(*report)); | |
3171 | priv->measurement_status |= MEASUREMENT_READY; | |
3172 | #endif | |
3173 | } | |
3174 | ||
c79dd5b5 | 3175 | static void iwl4965_rx_pm_sleep_notif(struct iwl_priv *priv, |
bb8c093b | 3176 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3177 | { |
0a6857e7 | 3178 | #ifdef CONFIG_IWLWIFI_DEBUG |
bb8c093b CH |
3179 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
3180 | struct iwl4965_sleep_notification *sleep = &(pkt->u.sleep_notif); | |
b481de9c ZY |
3181 | IWL_DEBUG_RX("sleep mode: %d, src: %d\n", |
3182 | sleep->pm_sleep_mode, sleep->pm_wakeup_src); | |
3183 | #endif | |
3184 | } | |
3185 | ||
c79dd5b5 | 3186 | static void iwl4965_rx_pm_debug_statistics_notif(struct iwl_priv *priv, |
bb8c093b | 3187 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3188 | { |
bb8c093b | 3189 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
3190 | IWL_DEBUG_RADIO("Dumping %d bytes of unhandled " |
3191 | "notification for %s:\n", | |
3192 | le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd)); | |
0a6857e7 | 3193 | iwl_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len)); |
b481de9c ZY |
3194 | } |
3195 | ||
bb8c093b | 3196 | static void iwl4965_bg_beacon_update(struct work_struct *work) |
b481de9c | 3197 | { |
c79dd5b5 TW |
3198 | struct iwl_priv *priv = |
3199 | container_of(work, struct iwl_priv, beacon_update); | |
b481de9c ZY |
3200 | struct sk_buff *beacon; |
3201 | ||
3202 | /* Pull updated AP beacon from mac80211. will fail if not in AP mode */ | |
32bfd35d | 3203 | beacon = ieee80211_beacon_get(priv->hw, priv->vif, NULL); |
b481de9c ZY |
3204 | |
3205 | if (!beacon) { | |
3206 | IWL_ERROR("update beacon failed\n"); | |
3207 | return; | |
3208 | } | |
3209 | ||
3210 | mutex_lock(&priv->mutex); | |
3211 | /* new beacon skb is allocated every time; dispose previous.*/ | |
3212 | if (priv->ibss_beacon) | |
3213 | dev_kfree_skb(priv->ibss_beacon); | |
3214 | ||
3215 | priv->ibss_beacon = beacon; | |
3216 | mutex_unlock(&priv->mutex); | |
3217 | ||
bb8c093b | 3218 | iwl4965_send_beacon_cmd(priv); |
b481de9c ZY |
3219 | } |
3220 | ||
c79dd5b5 | 3221 | static void iwl4965_rx_beacon_notif(struct iwl_priv *priv, |
bb8c093b | 3222 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3223 | { |
0a6857e7 | 3224 | #ifdef CONFIG_IWLWIFI_DEBUG |
bb8c093b CH |
3225 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
3226 | struct iwl4965_beacon_notif *beacon = &(pkt->u.beacon_status); | |
3227 | u8 rate = iwl4965_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags); | |
b481de9c ZY |
3228 | |
3229 | IWL_DEBUG_RX("beacon status %x retries %d iss %d " | |
3230 | "tsf %d %d rate %d\n", | |
3231 | le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK, | |
3232 | beacon->beacon_notify_hdr.failure_frame, | |
3233 | le32_to_cpu(beacon->ibss_mgr_status), | |
3234 | le32_to_cpu(beacon->high_tsf), | |
3235 | le32_to_cpu(beacon->low_tsf), rate); | |
3236 | #endif | |
3237 | ||
3238 | if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) && | |
3239 | (!test_bit(STATUS_EXIT_PENDING, &priv->status))) | |
3240 | queue_work(priv->workqueue, &priv->beacon_update); | |
3241 | } | |
3242 | ||
3243 | /* Service response to REPLY_SCAN_CMD (0x80) */ | |
c79dd5b5 | 3244 | static void iwl4965_rx_reply_scan(struct iwl_priv *priv, |
bb8c093b | 3245 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3246 | { |
0a6857e7 | 3247 | #ifdef CONFIG_IWLWIFI_DEBUG |
bb8c093b CH |
3248 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
3249 | struct iwl4965_scanreq_notification *notif = | |
3250 | (struct iwl4965_scanreq_notification *)pkt->u.raw; | |
b481de9c ZY |
3251 | |
3252 | IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status); | |
3253 | #endif | |
3254 | } | |
3255 | ||
3256 | /* Service SCAN_START_NOTIFICATION (0x82) */ | |
c79dd5b5 | 3257 | static void iwl4965_rx_scan_start_notif(struct iwl_priv *priv, |
bb8c093b | 3258 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3259 | { |
bb8c093b CH |
3260 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
3261 | struct iwl4965_scanstart_notification *notif = | |
3262 | (struct iwl4965_scanstart_notification *)pkt->u.raw; | |
b481de9c ZY |
3263 | priv->scan_start_tsf = le32_to_cpu(notif->tsf_low); |
3264 | IWL_DEBUG_SCAN("Scan start: " | |
3265 | "%d [802.11%s] " | |
3266 | "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n", | |
3267 | notif->channel, | |
3268 | notif->band ? "bg" : "a", | |
3269 | notif->tsf_high, | |
3270 | notif->tsf_low, notif->status, notif->beacon_timer); | |
3271 | } | |
3272 | ||
3273 | /* Service SCAN_RESULTS_NOTIFICATION (0x83) */ | |
c79dd5b5 | 3274 | static void iwl4965_rx_scan_results_notif(struct iwl_priv *priv, |
bb8c093b | 3275 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3276 | { |
bb8c093b CH |
3277 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
3278 | struct iwl4965_scanresults_notification *notif = | |
3279 | (struct iwl4965_scanresults_notification *)pkt->u.raw; | |
b481de9c ZY |
3280 | |
3281 | IWL_DEBUG_SCAN("Scan ch.res: " | |
3282 | "%d [802.11%s] " | |
3283 | "(TSF: 0x%08X:%08X) - %d " | |
3284 | "elapsed=%lu usec (%dms since last)\n", | |
3285 | notif->channel, | |
3286 | notif->band ? "bg" : "a", | |
3287 | le32_to_cpu(notif->tsf_high), | |
3288 | le32_to_cpu(notif->tsf_low), | |
3289 | le32_to_cpu(notif->statistics[0]), | |
3290 | le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf, | |
3291 | jiffies_to_msecs(elapsed_jiffies | |
3292 | (priv->last_scan_jiffies, jiffies))); | |
3293 | ||
3294 | priv->last_scan_jiffies = jiffies; | |
7878a5a4 | 3295 | priv->next_scan_jiffies = 0; |
b481de9c ZY |
3296 | } |
3297 | ||
3298 | /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */ | |
c79dd5b5 | 3299 | static void iwl4965_rx_scan_complete_notif(struct iwl_priv *priv, |
bb8c093b | 3300 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3301 | { |
bb8c093b CH |
3302 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
3303 | struct iwl4965_scancomplete_notification *scan_notif = (void *)pkt->u.raw; | |
b481de9c ZY |
3304 | |
3305 | IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n", | |
3306 | scan_notif->scanned_channels, | |
3307 | scan_notif->tsf_low, | |
3308 | scan_notif->tsf_high, scan_notif->status); | |
3309 | ||
3310 | /* The HW is no longer scanning */ | |
3311 | clear_bit(STATUS_SCAN_HW, &priv->status); | |
3312 | ||
3313 | /* The scan completion notification came in, so kill that timer... */ | |
3314 | cancel_delayed_work(&priv->scan_check); | |
3315 | ||
3316 | IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n", | |
3317 | (priv->scan_bands == 2) ? "2.4" : "5.2", | |
3318 | jiffies_to_msecs(elapsed_jiffies | |
3319 | (priv->scan_pass_start, jiffies))); | |
3320 | ||
3321 | /* Remove this scanned band from the list | |
3322 | * of pending bands to scan */ | |
3323 | priv->scan_bands--; | |
3324 | ||
3325 | /* If a request to abort was given, or the scan did not succeed | |
3326 | * then we reset the scan state machine and terminate, | |
3327 | * re-queuing another scan if one has been requested */ | |
3328 | if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
3329 | IWL_DEBUG_INFO("Aborted scan completed.\n"); | |
3330 | clear_bit(STATUS_SCAN_ABORTING, &priv->status); | |
3331 | } else { | |
3332 | /* If there are more bands on this scan pass reschedule */ | |
3333 | if (priv->scan_bands > 0) | |
3334 | goto reschedule; | |
3335 | } | |
3336 | ||
3337 | priv->last_scan_jiffies = jiffies; | |
7878a5a4 | 3338 | priv->next_scan_jiffies = 0; |
b481de9c ZY |
3339 | IWL_DEBUG_INFO("Setting scan to off\n"); |
3340 | ||
3341 | clear_bit(STATUS_SCANNING, &priv->status); | |
3342 | ||
3343 | IWL_DEBUG_INFO("Scan took %dms\n", | |
3344 | jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies))); | |
3345 | ||
3346 | queue_work(priv->workqueue, &priv->scan_completed); | |
3347 | ||
3348 | return; | |
3349 | ||
3350 | reschedule: | |
3351 | priv->scan_pass_start = jiffies; | |
3352 | queue_work(priv->workqueue, &priv->request_scan); | |
3353 | } | |
3354 | ||
3355 | /* Handle notification from uCode that card's power state is changing | |
3356 | * due to software, hardware, or critical temperature RFKILL */ | |
c79dd5b5 | 3357 | static void iwl4965_rx_card_state_notif(struct iwl_priv *priv, |
bb8c093b | 3358 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3359 | { |
bb8c093b | 3360 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
3361 | u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); |
3362 | unsigned long status = priv->status; | |
3363 | ||
3364 | IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n", | |
3365 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", | |
3366 | (flags & SW_CARD_DISABLED) ? "Kill" : "On"); | |
3367 | ||
3368 | if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | | |
3369 | RF_CARD_DISABLED)) { | |
3370 | ||
3395f6e9 | 3371 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c ZY |
3372 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
3373 | ||
3395f6e9 TW |
3374 | if (!iwl_grab_nic_access(priv)) { |
3375 | iwl_write_direct32( | |
b481de9c ZY |
3376 | priv, HBUS_TARG_MBX_C, |
3377 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); | |
3378 | ||
3395f6e9 | 3379 | iwl_release_nic_access(priv); |
b481de9c ZY |
3380 | } |
3381 | ||
3382 | if (!(flags & RXON_CARD_DISABLED)) { | |
3395f6e9 | 3383 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, |
b481de9c | 3384 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
3395f6e9 TW |
3385 | if (!iwl_grab_nic_access(priv)) { |
3386 | iwl_write_direct32( | |
b481de9c ZY |
3387 | priv, HBUS_TARG_MBX_C, |
3388 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); | |
3389 | ||
3395f6e9 | 3390 | iwl_release_nic_access(priv); |
b481de9c ZY |
3391 | } |
3392 | } | |
3393 | ||
3394 | if (flags & RF_CARD_DISABLED) { | |
3395f6e9 | 3395 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c | 3396 | CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); |
3395f6e9 TW |
3397 | iwl_read32(priv, CSR_UCODE_DRV_GP1); |
3398 | if (!iwl_grab_nic_access(priv)) | |
3399 | iwl_release_nic_access(priv); | |
b481de9c ZY |
3400 | } |
3401 | } | |
3402 | ||
3403 | if (flags & HW_CARD_DISABLED) | |
3404 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
3405 | else | |
3406 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
3407 | ||
3408 | ||
3409 | if (flags & SW_CARD_DISABLED) | |
3410 | set_bit(STATUS_RF_KILL_SW, &priv->status); | |
3411 | else | |
3412 | clear_bit(STATUS_RF_KILL_SW, &priv->status); | |
3413 | ||
3414 | if (!(flags & RXON_CARD_DISABLED)) | |
bb8c093b | 3415 | iwl4965_scan_cancel(priv); |
b481de9c ZY |
3416 | |
3417 | if ((test_bit(STATUS_RF_KILL_HW, &status) != | |
3418 | test_bit(STATUS_RF_KILL_HW, &priv->status)) || | |
3419 | (test_bit(STATUS_RF_KILL_SW, &status) != | |
3420 | test_bit(STATUS_RF_KILL_SW, &priv->status))) | |
3421 | queue_work(priv->workqueue, &priv->rf_kill); | |
3422 | else | |
3423 | wake_up_interruptible(&priv->wait_command_queue); | |
3424 | } | |
3425 | ||
3426 | /** | |
bb8c093b | 3427 | * iwl4965_setup_rx_handlers - Initialize Rx handler callbacks |
b481de9c ZY |
3428 | * |
3429 | * Setup the RX handlers for each of the reply types sent from the uCode | |
3430 | * to the host. | |
3431 | * | |
3432 | * This function chains into the hardware specific files for them to setup | |
3433 | * any hardware specific handlers as well. | |
3434 | */ | |
c79dd5b5 | 3435 | static void iwl4965_setup_rx_handlers(struct iwl_priv *priv) |
b481de9c | 3436 | { |
bb8c093b CH |
3437 | priv->rx_handlers[REPLY_ALIVE] = iwl4965_rx_reply_alive; |
3438 | priv->rx_handlers[REPLY_ADD_STA] = iwl4965_rx_reply_add_sta; | |
3439 | priv->rx_handlers[REPLY_ERROR] = iwl4965_rx_reply_error; | |
3440 | priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl4965_rx_csa; | |
b481de9c | 3441 | priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] = |
bb8c093b CH |
3442 | iwl4965_rx_spectrum_measure_notif; |
3443 | priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl4965_rx_pm_sleep_notif; | |
b481de9c | 3444 | priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] = |
bb8c093b CH |
3445 | iwl4965_rx_pm_debug_statistics_notif; |
3446 | priv->rx_handlers[BEACON_NOTIFICATION] = iwl4965_rx_beacon_notif; | |
b481de9c | 3447 | |
9fbab516 BC |
3448 | /* |
3449 | * The same handler is used for both the REPLY to a discrete | |
3450 | * statistics request from the host as well as for the periodic | |
3451 | * statistics notifications (after received beacons) from the uCode. | |
b481de9c | 3452 | */ |
bb8c093b CH |
3453 | priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl4965_hw_rx_statistics; |
3454 | priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl4965_hw_rx_statistics; | |
b481de9c | 3455 | |
bb8c093b CH |
3456 | priv->rx_handlers[REPLY_SCAN_CMD] = iwl4965_rx_reply_scan; |
3457 | priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl4965_rx_scan_start_notif; | |
b481de9c | 3458 | priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] = |
bb8c093b | 3459 | iwl4965_rx_scan_results_notif; |
b481de9c | 3460 | priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] = |
bb8c093b CH |
3461 | iwl4965_rx_scan_complete_notif; |
3462 | priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl4965_rx_card_state_notif; | |
3463 | priv->rx_handlers[REPLY_TX] = iwl4965_rx_reply_tx; | |
b481de9c | 3464 | |
9fbab516 | 3465 | /* Set up hardware specific Rx handlers */ |
bb8c093b | 3466 | iwl4965_hw_rx_handler_setup(priv); |
b481de9c ZY |
3467 | } |
3468 | ||
3469 | /** | |
bb8c093b | 3470 | * iwl4965_tx_cmd_complete - Pull unused buffers off the queue and reclaim them |
b481de9c ZY |
3471 | * @rxb: Rx buffer to reclaim |
3472 | * | |
3473 | * If an Rx buffer has an async callback associated with it the callback | |
3474 | * will be executed. The attached skb (if present) will only be freed | |
3475 | * if the callback returns 1 | |
3476 | */ | |
c79dd5b5 | 3477 | static void iwl4965_tx_cmd_complete(struct iwl_priv *priv, |
bb8c093b | 3478 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3479 | { |
bb8c093b | 3480 | struct iwl4965_rx_packet *pkt = (struct iwl4965_rx_packet *)rxb->skb->data; |
b481de9c ZY |
3481 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
3482 | int txq_id = SEQ_TO_QUEUE(sequence); | |
3483 | int index = SEQ_TO_INDEX(sequence); | |
3484 | int huge = sequence & SEQ_HUGE_FRAME; | |
3485 | int cmd_index; | |
857485c0 | 3486 | struct iwl_cmd *cmd; |
b481de9c ZY |
3487 | |
3488 | /* If a Tx command is being handled and it isn't in the actual | |
3489 | * command queue then there a command routing bug has been introduced | |
3490 | * in the queue management code. */ | |
3491 | if (txq_id != IWL_CMD_QUEUE_NUM) | |
3492 | IWL_ERROR("Error wrong command queue %d command id 0x%X\n", | |
3493 | txq_id, pkt->hdr.cmd); | |
3494 | BUG_ON(txq_id != IWL_CMD_QUEUE_NUM); | |
3495 | ||
3496 | cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge); | |
3497 | cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index]; | |
3498 | ||
3499 | /* Input error checking is done when commands are added to queue. */ | |
3500 | if (cmd->meta.flags & CMD_WANT_SKB) { | |
3501 | cmd->meta.source->u.skb = rxb->skb; | |
3502 | rxb->skb = NULL; | |
3503 | } else if (cmd->meta.u.callback && | |
3504 | !cmd->meta.u.callback(priv, cmd, rxb->skb)) | |
3505 | rxb->skb = NULL; | |
3506 | ||
bb8c093b | 3507 | iwl4965_tx_queue_reclaim(priv, txq_id, index); |
b481de9c ZY |
3508 | |
3509 | if (!(cmd->meta.flags & CMD_ASYNC)) { | |
3510 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
3511 | wake_up_interruptible(&priv->wait_command_queue); | |
3512 | } | |
3513 | } | |
3514 | ||
3515 | /************************** RX-FUNCTIONS ****************************/ | |
3516 | /* | |
3517 | * Rx theory of operation | |
3518 | * | |
9fbab516 BC |
3519 | * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs), |
3520 | * each of which point to Receive Buffers to be filled by 4965. These get | |
3521 | * used not only for Rx frames, but for any command response or notification | |
3522 | * from the 4965. The driver and 4965 manage the Rx buffers by means | |
3523 | * of indexes into the circular buffer. | |
b481de9c ZY |
3524 | * |
3525 | * Rx Queue Indexes | |
3526 | * The host/firmware share two index registers for managing the Rx buffers. | |
3527 | * | |
3528 | * The READ index maps to the first position that the firmware may be writing | |
3529 | * to -- the driver can read up to (but not including) this position and get | |
3530 | * good data. | |
3531 | * The READ index is managed by the firmware once the card is enabled. | |
3532 | * | |
3533 | * The WRITE index maps to the last position the driver has read from -- the | |
3534 | * position preceding WRITE is the last slot the firmware can place a packet. | |
3535 | * | |
3536 | * The queue is empty (no good data) if WRITE = READ - 1, and is full if | |
3537 | * WRITE = READ. | |
3538 | * | |
9fbab516 | 3539 | * During initialization, the host sets up the READ queue position to the first |
b481de9c ZY |
3540 | * INDEX position, and WRITE to the last (READ - 1 wrapped) |
3541 | * | |
9fbab516 | 3542 | * When the firmware places a packet in a buffer, it will advance the READ index |
b481de9c ZY |
3543 | * and fire the RX interrupt. The driver can then query the READ index and |
3544 | * process as many packets as possible, moving the WRITE index forward as it | |
3545 | * resets the Rx queue buffers with new memory. | |
3546 | * | |
3547 | * The management in the driver is as follows: | |
3548 | * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When | |
3549 | * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled | |
01ebd063 | 3550 | * to replenish the iwl->rxq->rx_free. |
bb8c093b | 3551 | * + In iwl4965_rx_replenish (scheduled) if 'processed' != 'read' then the |
b481de9c ZY |
3552 | * iwl->rxq is replenished and the READ INDEX is updated (updating the |
3553 | * 'processed' and 'read' driver indexes as well) | |
3554 | * + A received packet is processed and handed to the kernel network stack, | |
3555 | * detached from the iwl->rxq. The driver 'processed' index is updated. | |
3556 | * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free | |
3557 | * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ | |
3558 | * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there | |
3559 | * were enough free buffers and RX_STALLED is set it is cleared. | |
3560 | * | |
3561 | * | |
3562 | * Driver sequence: | |
3563 | * | |
9fbab516 BC |
3564 | * iwl4965_rx_queue_alloc() Allocates rx_free |
3565 | * iwl4965_rx_replenish() Replenishes rx_free list from rx_used, and calls | |
bb8c093b | 3566 | * iwl4965_rx_queue_restock |
9fbab516 | 3567 | * iwl4965_rx_queue_restock() Moves available buffers from rx_free into Rx |
b481de9c ZY |
3568 | * queue, updates firmware pointers, and updates |
3569 | * the WRITE index. If insufficient rx_free buffers | |
bb8c093b | 3570 | * are available, schedules iwl4965_rx_replenish |
b481de9c ZY |
3571 | * |
3572 | * -- enable interrupts -- | |
9fbab516 | 3573 | * ISR - iwl4965_rx() Detach iwl4965_rx_mem_buffers from pool up to the |
b481de9c ZY |
3574 | * READ INDEX, detaching the SKB from the pool. |
3575 | * Moves the packet buffer from queue to rx_used. | |
bb8c093b | 3576 | * Calls iwl4965_rx_queue_restock to refill any empty |
b481de9c ZY |
3577 | * slots. |
3578 | * ... | |
3579 | * | |
3580 | */ | |
3581 | ||
3582 | /** | |
bb8c093b | 3583 | * iwl4965_rx_queue_space - Return number of free slots available in queue. |
b481de9c | 3584 | */ |
bb8c093b | 3585 | static int iwl4965_rx_queue_space(const struct iwl4965_rx_queue *q) |
b481de9c ZY |
3586 | { |
3587 | int s = q->read - q->write; | |
3588 | if (s <= 0) | |
3589 | s += RX_QUEUE_SIZE; | |
3590 | /* keep some buffer to not confuse full and empty queue */ | |
3591 | s -= 2; | |
3592 | if (s < 0) | |
3593 | s = 0; | |
3594 | return s; | |
3595 | } | |
3596 | ||
3597 | /** | |
bb8c093b | 3598 | * iwl4965_rx_queue_update_write_ptr - Update the write pointer for the RX queue |
b481de9c | 3599 | */ |
c79dd5b5 | 3600 | int iwl4965_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl4965_rx_queue *q) |
b481de9c ZY |
3601 | { |
3602 | u32 reg = 0; | |
3603 | int rc = 0; | |
3604 | unsigned long flags; | |
3605 | ||
3606 | spin_lock_irqsave(&q->lock, flags); | |
3607 | ||
3608 | if (q->need_update == 0) | |
3609 | goto exit_unlock; | |
3610 | ||
6440adb5 | 3611 | /* If power-saving is in use, make sure device is awake */ |
b481de9c | 3612 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { |
3395f6e9 | 3613 | reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); |
b481de9c ZY |
3614 | |
3615 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
3395f6e9 | 3616 | iwl_set_bit(priv, CSR_GP_CNTRL, |
b481de9c ZY |
3617 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
3618 | goto exit_unlock; | |
3619 | } | |
3620 | ||
3395f6e9 | 3621 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
3622 | if (rc) |
3623 | goto exit_unlock; | |
3624 | ||
6440adb5 | 3625 | /* Device expects a multiple of 8 */ |
3395f6e9 | 3626 | iwl_write_direct32(priv, FH_RSCSR_CHNL0_WPTR, |
b481de9c | 3627 | q->write & ~0x7); |
3395f6e9 | 3628 | iwl_release_nic_access(priv); |
6440adb5 CB |
3629 | |
3630 | /* Else device is assumed to be awake */ | |
b481de9c | 3631 | } else |
6440adb5 | 3632 | /* Device expects a multiple of 8 */ |
3395f6e9 | 3633 | iwl_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7); |
b481de9c ZY |
3634 | |
3635 | ||
3636 | q->need_update = 0; | |
3637 | ||
3638 | exit_unlock: | |
3639 | spin_unlock_irqrestore(&q->lock, flags); | |
3640 | return rc; | |
3641 | } | |
3642 | ||
3643 | /** | |
9fbab516 | 3644 | * iwl4965_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr |
b481de9c | 3645 | */ |
c79dd5b5 | 3646 | static inline __le32 iwl4965_dma_addr2rbd_ptr(struct iwl_priv *priv, |
b481de9c ZY |
3647 | dma_addr_t dma_addr) |
3648 | { | |
3649 | return cpu_to_le32((u32)(dma_addr >> 8)); | |
3650 | } | |
3651 | ||
3652 | ||
3653 | /** | |
bb8c093b | 3654 | * iwl4965_rx_queue_restock - refill RX queue from pre-allocated pool |
b481de9c | 3655 | * |
9fbab516 | 3656 | * If there are slots in the RX queue that need to be restocked, |
b481de9c | 3657 | * and we have free pre-allocated buffers, fill the ranks as much |
9fbab516 | 3658 | * as we can, pulling from rx_free. |
b481de9c ZY |
3659 | * |
3660 | * This moves the 'write' index forward to catch up with 'processed', and | |
3661 | * also updates the memory address in the firmware to reference the new | |
3662 | * target buffer. | |
3663 | */ | |
c79dd5b5 | 3664 | static int iwl4965_rx_queue_restock(struct iwl_priv *priv) |
b481de9c | 3665 | { |
bb8c093b | 3666 | struct iwl4965_rx_queue *rxq = &priv->rxq; |
b481de9c | 3667 | struct list_head *element; |
bb8c093b | 3668 | struct iwl4965_rx_mem_buffer *rxb; |
b481de9c ZY |
3669 | unsigned long flags; |
3670 | int write, rc; | |
3671 | ||
3672 | spin_lock_irqsave(&rxq->lock, flags); | |
3673 | write = rxq->write & ~0x7; | |
bb8c093b | 3674 | while ((iwl4965_rx_queue_space(rxq) > 0) && (rxq->free_count)) { |
6440adb5 | 3675 | /* Get next free Rx buffer, remove from free list */ |
b481de9c | 3676 | element = rxq->rx_free.next; |
bb8c093b | 3677 | rxb = list_entry(element, struct iwl4965_rx_mem_buffer, list); |
b481de9c | 3678 | list_del(element); |
6440adb5 CB |
3679 | |
3680 | /* Point to Rx buffer via next RBD in circular buffer */ | |
bb8c093b | 3681 | rxq->bd[rxq->write] = iwl4965_dma_addr2rbd_ptr(priv, rxb->dma_addr); |
b481de9c ZY |
3682 | rxq->queue[rxq->write] = rxb; |
3683 | rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; | |
3684 | rxq->free_count--; | |
3685 | } | |
3686 | spin_unlock_irqrestore(&rxq->lock, flags); | |
3687 | /* If the pre-allocated buffer pool is dropping low, schedule to | |
3688 | * refill it */ | |
3689 | if (rxq->free_count <= RX_LOW_WATERMARK) | |
3690 | queue_work(priv->workqueue, &priv->rx_replenish); | |
3691 | ||
3692 | ||
6440adb5 CB |
3693 | /* If we've added more space for the firmware to place data, tell it. |
3694 | * Increment device's write pointer in multiples of 8. */ | |
b481de9c ZY |
3695 | if ((write != (rxq->write & ~0x7)) |
3696 | || (abs(rxq->write - rxq->read) > 7)) { | |
3697 | spin_lock_irqsave(&rxq->lock, flags); | |
3698 | rxq->need_update = 1; | |
3699 | spin_unlock_irqrestore(&rxq->lock, flags); | |
bb8c093b | 3700 | rc = iwl4965_rx_queue_update_write_ptr(priv, rxq); |
b481de9c ZY |
3701 | if (rc) |
3702 | return rc; | |
3703 | } | |
3704 | ||
3705 | return 0; | |
3706 | } | |
3707 | ||
3708 | /** | |
bb8c093b | 3709 | * iwl4965_rx_replenish - Move all used packet from rx_used to rx_free |
b481de9c ZY |
3710 | * |
3711 | * When moving to rx_free an SKB is allocated for the slot. | |
3712 | * | |
bb8c093b | 3713 | * Also restock the Rx queue via iwl4965_rx_queue_restock. |
01ebd063 | 3714 | * This is called as a scheduled work item (except for during initialization) |
b481de9c | 3715 | */ |
c79dd5b5 | 3716 | static void iwl4965_rx_allocate(struct iwl_priv *priv) |
b481de9c | 3717 | { |
bb8c093b | 3718 | struct iwl4965_rx_queue *rxq = &priv->rxq; |
b481de9c | 3719 | struct list_head *element; |
bb8c093b | 3720 | struct iwl4965_rx_mem_buffer *rxb; |
b481de9c ZY |
3721 | unsigned long flags; |
3722 | spin_lock_irqsave(&rxq->lock, flags); | |
3723 | while (!list_empty(&rxq->rx_used)) { | |
3724 | element = rxq->rx_used.next; | |
bb8c093b | 3725 | rxb = list_entry(element, struct iwl4965_rx_mem_buffer, list); |
6440adb5 CB |
3726 | |
3727 | /* Alloc a new receive buffer */ | |
b481de9c | 3728 | rxb->skb = |
9ee1ba47 RR |
3729 | alloc_skb(priv->hw_setting.rx_buf_size, |
3730 | __GFP_NOWARN | GFP_ATOMIC); | |
b481de9c ZY |
3731 | if (!rxb->skb) { |
3732 | if (net_ratelimit()) | |
3733 | printk(KERN_CRIT DRV_NAME | |
3734 | ": Can not allocate SKB buffers\n"); | |
3735 | /* We don't reschedule replenish work here -- we will | |
3736 | * call the restock method and if it still needs | |
3737 | * more buffers it will schedule replenish */ | |
3738 | break; | |
3739 | } | |
3740 | priv->alloc_rxb_skb++; | |
3741 | list_del(element); | |
6440adb5 CB |
3742 | |
3743 | /* Get physical address of RB/SKB */ | |
b481de9c ZY |
3744 | rxb->dma_addr = |
3745 | pci_map_single(priv->pci_dev, rxb->skb->data, | |
9ee1ba47 | 3746 | priv->hw_setting.rx_buf_size, PCI_DMA_FROMDEVICE); |
b481de9c ZY |
3747 | list_add_tail(&rxb->list, &rxq->rx_free); |
3748 | rxq->free_count++; | |
3749 | } | |
3750 | spin_unlock_irqrestore(&rxq->lock, flags); | |
5c0eef96 MA |
3751 | } |
3752 | ||
3753 | /* | |
3754 | * this should be called while priv->lock is locked | |
3755 | */ | |
4fd1f841 | 3756 | static void __iwl4965_rx_replenish(void *data) |
5c0eef96 | 3757 | { |
c79dd5b5 | 3758 | struct iwl_priv *priv = data; |
5c0eef96 MA |
3759 | |
3760 | iwl4965_rx_allocate(priv); | |
3761 | iwl4965_rx_queue_restock(priv); | |
3762 | } | |
3763 | ||
3764 | ||
3765 | void iwl4965_rx_replenish(void *data) | |
3766 | { | |
c79dd5b5 | 3767 | struct iwl_priv *priv = data; |
5c0eef96 MA |
3768 | unsigned long flags; |
3769 | ||
3770 | iwl4965_rx_allocate(priv); | |
b481de9c ZY |
3771 | |
3772 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 3773 | iwl4965_rx_queue_restock(priv); |
b481de9c ZY |
3774 | spin_unlock_irqrestore(&priv->lock, flags); |
3775 | } | |
3776 | ||
3777 | /* Assumes that the skb field of the buffers in 'pool' is kept accurate. | |
9fbab516 | 3778 | * If an SKB has been detached, the POOL needs to have its SKB set to NULL |
b481de9c ZY |
3779 | * This free routine walks the list of POOL entries and if SKB is set to |
3780 | * non NULL it is unmapped and freed | |
3781 | */ | |
c79dd5b5 | 3782 | static void iwl4965_rx_queue_free(struct iwl_priv *priv, struct iwl4965_rx_queue *rxq) |
b481de9c ZY |
3783 | { |
3784 | int i; | |
3785 | for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) { | |
3786 | if (rxq->pool[i].skb != NULL) { | |
3787 | pci_unmap_single(priv->pci_dev, | |
3788 | rxq->pool[i].dma_addr, | |
9ee1ba47 RR |
3789 | priv->hw_setting.rx_buf_size, |
3790 | PCI_DMA_FROMDEVICE); | |
b481de9c ZY |
3791 | dev_kfree_skb(rxq->pool[i].skb); |
3792 | } | |
3793 | } | |
3794 | ||
3795 | pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd, | |
3796 | rxq->dma_addr); | |
3797 | rxq->bd = NULL; | |
3798 | } | |
3799 | ||
c79dd5b5 | 3800 | int iwl4965_rx_queue_alloc(struct iwl_priv *priv) |
b481de9c | 3801 | { |
bb8c093b | 3802 | struct iwl4965_rx_queue *rxq = &priv->rxq; |
b481de9c ZY |
3803 | struct pci_dev *dev = priv->pci_dev; |
3804 | int i; | |
3805 | ||
3806 | spin_lock_init(&rxq->lock); | |
3807 | INIT_LIST_HEAD(&rxq->rx_free); | |
3808 | INIT_LIST_HEAD(&rxq->rx_used); | |
6440adb5 CB |
3809 | |
3810 | /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */ | |
b481de9c ZY |
3811 | rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr); |
3812 | if (!rxq->bd) | |
3813 | return -ENOMEM; | |
6440adb5 | 3814 | |
b481de9c ZY |
3815 | /* Fill the rx_used queue with _all_ of the Rx buffers */ |
3816 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) | |
3817 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
6440adb5 | 3818 | |
b481de9c ZY |
3819 | /* Set us so that we have processed and used all buffers, but have |
3820 | * not restocked the Rx queue with fresh buffers */ | |
3821 | rxq->read = rxq->write = 0; | |
3822 | rxq->free_count = 0; | |
3823 | rxq->need_update = 0; | |
3824 | return 0; | |
3825 | } | |
3826 | ||
c79dd5b5 | 3827 | void iwl4965_rx_queue_reset(struct iwl_priv *priv, struct iwl4965_rx_queue *rxq) |
b481de9c ZY |
3828 | { |
3829 | unsigned long flags; | |
3830 | int i; | |
3831 | spin_lock_irqsave(&rxq->lock, flags); | |
3832 | INIT_LIST_HEAD(&rxq->rx_free); | |
3833 | INIT_LIST_HEAD(&rxq->rx_used); | |
3834 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
3835 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { | |
3836 | /* In the reset function, these buffers may have been allocated | |
3837 | * to an SKB, so we need to unmap and free potential storage */ | |
3838 | if (rxq->pool[i].skb != NULL) { | |
3839 | pci_unmap_single(priv->pci_dev, | |
3840 | rxq->pool[i].dma_addr, | |
9ee1ba47 RR |
3841 | priv->hw_setting.rx_buf_size, |
3842 | PCI_DMA_FROMDEVICE); | |
b481de9c ZY |
3843 | priv->alloc_rxb_skb--; |
3844 | dev_kfree_skb(rxq->pool[i].skb); | |
3845 | rxq->pool[i].skb = NULL; | |
3846 | } | |
3847 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
3848 | } | |
3849 | ||
3850 | /* Set us so that we have processed and used all buffers, but have | |
3851 | * not restocked the Rx queue with fresh buffers */ | |
3852 | rxq->read = rxq->write = 0; | |
3853 | rxq->free_count = 0; | |
3854 | spin_unlock_irqrestore(&rxq->lock, flags); | |
3855 | } | |
3856 | ||
3857 | /* Convert linear signal-to-noise ratio into dB */ | |
3858 | static u8 ratio2dB[100] = { | |
3859 | /* 0 1 2 3 4 5 6 7 8 9 */ | |
3860 | 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */ | |
3861 | 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */ | |
3862 | 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */ | |
3863 | 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */ | |
3864 | 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */ | |
3865 | 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */ | |
3866 | 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */ | |
3867 | 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */ | |
3868 | 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */ | |
3869 | 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */ | |
3870 | }; | |
3871 | ||
3872 | /* Calculates a relative dB value from a ratio of linear | |
3873 | * (i.e. not dB) signal levels. | |
3874 | * Conversion assumes that levels are voltages (20*log), not powers (10*log). */ | |
bb8c093b | 3875 | int iwl4965_calc_db_from_ratio(int sig_ratio) |
b481de9c | 3876 | { |
c899a575 AB |
3877 | /* 1000:1 or higher just report as 60 dB */ |
3878 | if (sig_ratio >= 1000) | |
b481de9c ZY |
3879 | return 60; |
3880 | ||
c899a575 | 3881 | /* 100:1 or higher, divide by 10 and use table, |
b481de9c | 3882 | * add 20 dB to make up for divide by 10 */ |
c899a575 | 3883 | if (sig_ratio >= 100) |
b481de9c ZY |
3884 | return (20 + (int)ratio2dB[sig_ratio/10]); |
3885 | ||
3886 | /* We shouldn't see this */ | |
3887 | if (sig_ratio < 1) | |
3888 | return 0; | |
3889 | ||
3890 | /* Use table for ratios 1:1 - 99:1 */ | |
3891 | return (int)ratio2dB[sig_ratio]; | |
3892 | } | |
3893 | ||
3894 | #define PERFECT_RSSI (-20) /* dBm */ | |
3895 | #define WORST_RSSI (-95) /* dBm */ | |
3896 | #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI) | |
3897 | ||
3898 | /* Calculate an indication of rx signal quality (a percentage, not dBm!). | |
3899 | * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info | |
3900 | * about formulas used below. */ | |
bb8c093b | 3901 | int iwl4965_calc_sig_qual(int rssi_dbm, int noise_dbm) |
b481de9c ZY |
3902 | { |
3903 | int sig_qual; | |
3904 | int degradation = PERFECT_RSSI - rssi_dbm; | |
3905 | ||
3906 | /* If we get a noise measurement, use signal-to-noise ratio (SNR) | |
3907 | * as indicator; formula is (signal dbm - noise dbm). | |
3908 | * SNR at or above 40 is a great signal (100%). | |
3909 | * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator. | |
3910 | * Weakest usable signal is usually 10 - 15 dB SNR. */ | |
3911 | if (noise_dbm) { | |
3912 | if (rssi_dbm - noise_dbm >= 40) | |
3913 | return 100; | |
3914 | else if (rssi_dbm < noise_dbm) | |
3915 | return 0; | |
3916 | sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2; | |
3917 | ||
3918 | /* Else use just the signal level. | |
3919 | * This formula is a least squares fit of data points collected and | |
3920 | * compared with a reference system that had a percentage (%) display | |
3921 | * for signal quality. */ | |
3922 | } else | |
3923 | sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation * | |
3924 | (15 * RSSI_RANGE + 62 * degradation)) / | |
3925 | (RSSI_RANGE * RSSI_RANGE); | |
3926 | ||
3927 | if (sig_qual > 100) | |
3928 | sig_qual = 100; | |
3929 | else if (sig_qual < 1) | |
3930 | sig_qual = 0; | |
3931 | ||
3932 | return sig_qual; | |
3933 | } | |
3934 | ||
3935 | /** | |
9fbab516 | 3936 | * iwl4965_rx_handle - Main entry function for receiving responses from uCode |
b481de9c ZY |
3937 | * |
3938 | * Uses the priv->rx_handlers callback function array to invoke | |
3939 | * the appropriate handlers, including command responses, | |
3940 | * frame-received notifications, and other notifications. | |
3941 | */ | |
c79dd5b5 | 3942 | static void iwl4965_rx_handle(struct iwl_priv *priv) |
b481de9c | 3943 | { |
bb8c093b CH |
3944 | struct iwl4965_rx_mem_buffer *rxb; |
3945 | struct iwl4965_rx_packet *pkt; | |
3946 | struct iwl4965_rx_queue *rxq = &priv->rxq; | |
b481de9c ZY |
3947 | u32 r, i; |
3948 | int reclaim; | |
3949 | unsigned long flags; | |
5c0eef96 | 3950 | u8 fill_rx = 0; |
d68ab680 | 3951 | u32 count = 8; |
b481de9c | 3952 | |
6440adb5 CB |
3953 | /* uCode's read index (stored in shared DRAM) indicates the last Rx |
3954 | * buffer that the driver may process (last buffer filled by ucode). */ | |
bb8c093b | 3955 | r = iwl4965_hw_get_rx_read(priv); |
b481de9c ZY |
3956 | i = rxq->read; |
3957 | ||
3958 | /* Rx interrupt, but nothing sent from uCode */ | |
3959 | if (i == r) | |
3960 | IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i); | |
3961 | ||
5c0eef96 MA |
3962 | if (iwl4965_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2)) |
3963 | fill_rx = 1; | |
3964 | ||
b481de9c ZY |
3965 | while (i != r) { |
3966 | rxb = rxq->queue[i]; | |
3967 | ||
9fbab516 | 3968 | /* If an RXB doesn't have a Rx queue slot associated with it, |
b481de9c ZY |
3969 | * then a bug has been introduced in the queue refilling |
3970 | * routines -- catch it here */ | |
3971 | BUG_ON(rxb == NULL); | |
3972 | ||
3973 | rxq->queue[i] = NULL; | |
3974 | ||
3975 | pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr, | |
9ee1ba47 | 3976 | priv->hw_setting.rx_buf_size, |
b481de9c | 3977 | PCI_DMA_FROMDEVICE); |
bb8c093b | 3978 | pkt = (struct iwl4965_rx_packet *)rxb->skb->data; |
b481de9c ZY |
3979 | |
3980 | /* Reclaim a command buffer only if this packet is a response | |
3981 | * to a (driver-originated) command. | |
3982 | * If the packet (e.g. Rx frame) originated from uCode, | |
3983 | * there is no command buffer to reclaim. | |
3984 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
3985 | * but apparently a few don't get set; catch them here. */ | |
3986 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
3987 | (pkt->hdr.cmd != REPLY_RX_PHY_CMD) && | |
857485c0 | 3988 | (pkt->hdr.cmd != REPLY_RX) && |
cfe01709 | 3989 | (pkt->hdr.cmd != REPLY_COMPRESSED_BA) && |
b481de9c ZY |
3990 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && |
3991 | (pkt->hdr.cmd != REPLY_TX); | |
3992 | ||
3993 | /* Based on type of command response or notification, | |
3994 | * handle those that need handling via function in | |
bb8c093b | 3995 | * rx_handlers table. See iwl4965_setup_rx_handlers() */ |
b481de9c ZY |
3996 | if (priv->rx_handlers[pkt->hdr.cmd]) { |
3997 | IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR, | |
3998 | "r = %d, i = %d, %s, 0x%02x\n", r, i, | |
3999 | get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); | |
4000 | priv->rx_handlers[pkt->hdr.cmd] (priv, rxb); | |
4001 | } else { | |
4002 | /* No handling needed */ | |
4003 | IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR, | |
4004 | "r %d i %d No handler needed for %s, 0x%02x\n", | |
4005 | r, i, get_cmd_string(pkt->hdr.cmd), | |
4006 | pkt->hdr.cmd); | |
4007 | } | |
4008 | ||
4009 | if (reclaim) { | |
9fbab516 | 4010 | /* Invoke any callbacks, transfer the skb to caller, and |
857485c0 | 4011 | * fire off the (possibly) blocking iwl_send_cmd() |
b481de9c ZY |
4012 | * as we reclaim the driver command queue */ |
4013 | if (rxb && rxb->skb) | |
bb8c093b | 4014 | iwl4965_tx_cmd_complete(priv, rxb); |
b481de9c ZY |
4015 | else |
4016 | IWL_WARNING("Claim null rxb?\n"); | |
4017 | } | |
4018 | ||
4019 | /* For now we just don't re-use anything. We can tweak this | |
4020 | * later to try and re-use notification packets and SKBs that | |
4021 | * fail to Rx correctly */ | |
4022 | if (rxb->skb != NULL) { | |
4023 | priv->alloc_rxb_skb--; | |
4024 | dev_kfree_skb_any(rxb->skb); | |
4025 | rxb->skb = NULL; | |
4026 | } | |
4027 | ||
4028 | pci_unmap_single(priv->pci_dev, rxb->dma_addr, | |
9ee1ba47 RR |
4029 | priv->hw_setting.rx_buf_size, |
4030 | PCI_DMA_FROMDEVICE); | |
b481de9c ZY |
4031 | spin_lock_irqsave(&rxq->lock, flags); |
4032 | list_add_tail(&rxb->list, &priv->rxq.rx_used); | |
4033 | spin_unlock_irqrestore(&rxq->lock, flags); | |
4034 | i = (i + 1) & RX_QUEUE_MASK; | |
5c0eef96 MA |
4035 | /* If there are a lot of unused frames, |
4036 | * restock the Rx queue so ucode wont assert. */ | |
4037 | if (fill_rx) { | |
4038 | count++; | |
4039 | if (count >= 8) { | |
4040 | priv->rxq.read = i; | |
4041 | __iwl4965_rx_replenish(priv); | |
4042 | count = 0; | |
4043 | } | |
4044 | } | |
b481de9c ZY |
4045 | } |
4046 | ||
4047 | /* Backtrack one entry */ | |
4048 | priv->rxq.read = i; | |
bb8c093b | 4049 | iwl4965_rx_queue_restock(priv); |
b481de9c ZY |
4050 | } |
4051 | ||
6440adb5 CB |
4052 | /** |
4053 | * iwl4965_tx_queue_update_write_ptr - Send new write index to hardware | |
4054 | */ | |
c79dd5b5 | 4055 | static int iwl4965_tx_queue_update_write_ptr(struct iwl_priv *priv, |
bb8c093b | 4056 | struct iwl4965_tx_queue *txq) |
b481de9c ZY |
4057 | { |
4058 | u32 reg = 0; | |
4059 | int rc = 0; | |
4060 | int txq_id = txq->q.id; | |
4061 | ||
4062 | if (txq->need_update == 0) | |
4063 | return rc; | |
4064 | ||
4065 | /* if we're trying to save power */ | |
4066 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { | |
4067 | /* wake up nic if it's powered down ... | |
4068 | * uCode will wake up, and interrupt us again, so next | |
4069 | * time we'll skip this part. */ | |
3395f6e9 | 4070 | reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); |
b481de9c ZY |
4071 | |
4072 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
4073 | IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg); | |
3395f6e9 | 4074 | iwl_set_bit(priv, CSR_GP_CNTRL, |
b481de9c ZY |
4075 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
4076 | return rc; | |
4077 | } | |
4078 | ||
4079 | /* restore this queue's parameters in nic hardware. */ | |
3395f6e9 | 4080 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
4081 | if (rc) |
4082 | return rc; | |
3395f6e9 | 4083 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, |
fc4b6853 | 4084 | txq->q.write_ptr | (txq_id << 8)); |
3395f6e9 | 4085 | iwl_release_nic_access(priv); |
b481de9c ZY |
4086 | |
4087 | /* else not in power-save mode, uCode will never sleep when we're | |
4088 | * trying to tx (during RFKILL, we're not trying to tx). */ | |
4089 | } else | |
3395f6e9 | 4090 | iwl_write32(priv, HBUS_TARG_WRPTR, |
fc4b6853 | 4091 | txq->q.write_ptr | (txq_id << 8)); |
b481de9c ZY |
4092 | |
4093 | txq->need_update = 0; | |
4094 | ||
4095 | return rc; | |
4096 | } | |
4097 | ||
0a6857e7 | 4098 | #ifdef CONFIG_IWLWIFI_DEBUG |
bb8c093b | 4099 | static void iwl4965_print_rx_config_cmd(struct iwl4965_rxon_cmd *rxon) |
b481de9c | 4100 | { |
0795af57 JP |
4101 | DECLARE_MAC_BUF(mac); |
4102 | ||
b481de9c | 4103 | IWL_DEBUG_RADIO("RX CONFIG:\n"); |
0a6857e7 | 4104 | iwl_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon)); |
b481de9c ZY |
4105 | IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel)); |
4106 | IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags)); | |
4107 | IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n", | |
4108 | le32_to_cpu(rxon->filter_flags)); | |
4109 | IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type); | |
4110 | IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n", | |
4111 | rxon->ofdm_basic_rates); | |
4112 | IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates); | |
0795af57 JP |
4113 | IWL_DEBUG_RADIO("u8[6] node_addr: %s\n", |
4114 | print_mac(mac, rxon->node_addr)); | |
4115 | IWL_DEBUG_RADIO("u8[6] bssid_addr: %s\n", | |
4116 | print_mac(mac, rxon->bssid_addr)); | |
b481de9c ZY |
4117 | IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id)); |
4118 | } | |
4119 | #endif | |
4120 | ||
c79dd5b5 | 4121 | static void iwl4965_enable_interrupts(struct iwl_priv *priv) |
b481de9c ZY |
4122 | { |
4123 | IWL_DEBUG_ISR("Enabling interrupts\n"); | |
4124 | set_bit(STATUS_INT_ENABLED, &priv->status); | |
3395f6e9 | 4125 | iwl_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK); |
b481de9c ZY |
4126 | } |
4127 | ||
0359facc MA |
4128 | /* call this function to flush any scheduled tasklet */ |
4129 | static inline void iwl_synchronize_irq(struct iwl_priv *priv) | |
4130 | { | |
4131 | /* wait to make sure we flush pedding tasklet*/ | |
4132 | synchronize_irq(priv->pci_dev->irq); | |
4133 | tasklet_kill(&priv->irq_tasklet); | |
4134 | } | |
4135 | ||
c79dd5b5 | 4136 | static inline void iwl4965_disable_interrupts(struct iwl_priv *priv) |
b481de9c ZY |
4137 | { |
4138 | clear_bit(STATUS_INT_ENABLED, &priv->status); | |
4139 | ||
4140 | /* disable interrupts from uCode/NIC to host */ | |
3395f6e9 | 4141 | iwl_write32(priv, CSR_INT_MASK, 0x00000000); |
b481de9c ZY |
4142 | |
4143 | /* acknowledge/clear/reset any interrupts still pending | |
4144 | * from uCode or flow handler (Rx/Tx DMA) */ | |
3395f6e9 TW |
4145 | iwl_write32(priv, CSR_INT, 0xffffffff); |
4146 | iwl_write32(priv, CSR_FH_INT_STATUS, 0xffffffff); | |
b481de9c ZY |
4147 | IWL_DEBUG_ISR("Disabled interrupts\n"); |
4148 | } | |
4149 | ||
4150 | static const char *desc_lookup(int i) | |
4151 | { | |
4152 | switch (i) { | |
4153 | case 1: | |
4154 | return "FAIL"; | |
4155 | case 2: | |
4156 | return "BAD_PARAM"; | |
4157 | case 3: | |
4158 | return "BAD_CHECKSUM"; | |
4159 | case 4: | |
4160 | return "NMI_INTERRUPT"; | |
4161 | case 5: | |
4162 | return "SYSASSERT"; | |
4163 | case 6: | |
4164 | return "FATAL_ERROR"; | |
4165 | } | |
4166 | ||
4167 | return "UNKNOWN"; | |
4168 | } | |
4169 | ||
4170 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | |
4171 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | |
4172 | ||
c79dd5b5 | 4173 | static void iwl4965_dump_nic_error_log(struct iwl_priv *priv) |
b481de9c ZY |
4174 | { |
4175 | u32 data2, line; | |
4176 | u32 desc, time, count, base, data1; | |
4177 | u32 blink1, blink2, ilink1, ilink2; | |
4178 | int rc; | |
4179 | ||
4180 | base = le32_to_cpu(priv->card_alive.error_event_table_ptr); | |
4181 | ||
57aab75a | 4182 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { |
b481de9c ZY |
4183 | IWL_ERROR("Not valid error log pointer 0x%08X\n", base); |
4184 | return; | |
4185 | } | |
4186 | ||
3395f6e9 | 4187 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
4188 | if (rc) { |
4189 | IWL_WARNING("Can not read from adapter at this time.\n"); | |
4190 | return; | |
4191 | } | |
4192 | ||
3395f6e9 | 4193 | count = iwl_read_targ_mem(priv, base); |
b481de9c ZY |
4194 | |
4195 | if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { | |
4196 | IWL_ERROR("Start IWL Error Log Dump:\n"); | |
2acae16e | 4197 | IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count); |
b481de9c ZY |
4198 | } |
4199 | ||
3395f6e9 TW |
4200 | desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32)); |
4201 | blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32)); | |
4202 | blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32)); | |
4203 | ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32)); | |
4204 | ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32)); | |
4205 | data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32)); | |
4206 | data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32)); | |
4207 | line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32)); | |
4208 | time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32)); | |
b481de9c ZY |
4209 | |
4210 | IWL_ERROR("Desc Time " | |
4211 | "data1 data2 line\n"); | |
4212 | IWL_ERROR("%-13s (#%d) %010u 0x%08X 0x%08X %u\n", | |
4213 | desc_lookup(desc), desc, time, data1, data2, line); | |
4214 | IWL_ERROR("blink1 blink2 ilink1 ilink2\n"); | |
4215 | IWL_ERROR("0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2, | |
4216 | ilink1, ilink2); | |
4217 | ||
3395f6e9 | 4218 | iwl_release_nic_access(priv); |
b481de9c ZY |
4219 | } |
4220 | ||
4221 | #define EVENT_START_OFFSET (4 * sizeof(u32)) | |
4222 | ||
4223 | /** | |
bb8c093b | 4224 | * iwl4965_print_event_log - Dump error event log to syslog |
b481de9c | 4225 | * |
3395f6e9 | 4226 | * NOTE: Must be called with iwl_grab_nic_access() already obtained! |
b481de9c | 4227 | */ |
c79dd5b5 | 4228 | static void iwl4965_print_event_log(struct iwl_priv *priv, u32 start_idx, |
b481de9c ZY |
4229 | u32 num_events, u32 mode) |
4230 | { | |
4231 | u32 i; | |
4232 | u32 base; /* SRAM byte address of event log header */ | |
4233 | u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */ | |
4234 | u32 ptr; /* SRAM byte address of log data */ | |
4235 | u32 ev, time, data; /* event log data */ | |
4236 | ||
4237 | if (num_events == 0) | |
4238 | return; | |
4239 | ||
4240 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
4241 | ||
4242 | if (mode == 0) | |
4243 | event_size = 2 * sizeof(u32); | |
4244 | else | |
4245 | event_size = 3 * sizeof(u32); | |
4246 | ||
4247 | ptr = base + EVENT_START_OFFSET + (start_idx * event_size); | |
4248 | ||
4249 | /* "time" is actually "data" for mode 0 (no timestamp). | |
4250 | * place event id # at far right for easier visual parsing. */ | |
4251 | for (i = 0; i < num_events; i++) { | |
3395f6e9 | 4252 | ev = iwl_read_targ_mem(priv, ptr); |
b481de9c | 4253 | ptr += sizeof(u32); |
3395f6e9 | 4254 | time = iwl_read_targ_mem(priv, ptr); |
b481de9c ZY |
4255 | ptr += sizeof(u32); |
4256 | if (mode == 0) | |
4257 | IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */ | |
4258 | else { | |
3395f6e9 | 4259 | data = iwl_read_targ_mem(priv, ptr); |
b481de9c ZY |
4260 | ptr += sizeof(u32); |
4261 | IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev); | |
4262 | } | |
4263 | } | |
4264 | } | |
4265 | ||
c79dd5b5 | 4266 | static void iwl4965_dump_nic_event_log(struct iwl_priv *priv) |
b481de9c ZY |
4267 | { |
4268 | int rc; | |
4269 | u32 base; /* SRAM byte address of event log header */ | |
4270 | u32 capacity; /* event log capacity in # entries */ | |
4271 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
4272 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
4273 | u32 next_entry; /* index of next entry to be written by uCode */ | |
4274 | u32 size; /* # entries that we'll print */ | |
4275 | ||
4276 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
57aab75a | 4277 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { |
b481de9c ZY |
4278 | IWL_ERROR("Invalid event log pointer 0x%08X\n", base); |
4279 | return; | |
4280 | } | |
4281 | ||
3395f6e9 | 4282 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
4283 | if (rc) { |
4284 | IWL_WARNING("Can not read from adapter at this time.\n"); | |
4285 | return; | |
4286 | } | |
4287 | ||
4288 | /* event log header */ | |
3395f6e9 TW |
4289 | capacity = iwl_read_targ_mem(priv, base); |
4290 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
4291 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
4292 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
b481de9c ZY |
4293 | |
4294 | size = num_wraps ? capacity : next_entry; | |
4295 | ||
4296 | /* bail out if nothing in log */ | |
4297 | if (size == 0) { | |
583fab37 | 4298 | IWL_ERROR("Start IWL Event Log Dump: nothing in log\n"); |
3395f6e9 | 4299 | iwl_release_nic_access(priv); |
b481de9c ZY |
4300 | return; |
4301 | } | |
4302 | ||
583fab37 | 4303 | IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n", |
b481de9c ZY |
4304 | size, num_wraps); |
4305 | ||
4306 | /* if uCode has wrapped back to top of log, start at the oldest entry, | |
4307 | * i.e the next one that uCode would fill. */ | |
4308 | if (num_wraps) | |
bb8c093b | 4309 | iwl4965_print_event_log(priv, next_entry, |
b481de9c ZY |
4310 | capacity - next_entry, mode); |
4311 | ||
4312 | /* (then/else) start at top of log */ | |
bb8c093b | 4313 | iwl4965_print_event_log(priv, 0, next_entry, mode); |
b481de9c | 4314 | |
3395f6e9 | 4315 | iwl_release_nic_access(priv); |
b481de9c ZY |
4316 | } |
4317 | ||
4318 | /** | |
bb8c093b | 4319 | * iwl4965_irq_handle_error - called for HW or SW error interrupt from card |
b481de9c | 4320 | */ |
c79dd5b5 | 4321 | static void iwl4965_irq_handle_error(struct iwl_priv *priv) |
b481de9c | 4322 | { |
bb8c093b | 4323 | /* Set the FW error flag -- cleared on iwl4965_down */ |
b481de9c ZY |
4324 | set_bit(STATUS_FW_ERROR, &priv->status); |
4325 | ||
4326 | /* Cancel currently queued command. */ | |
4327 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
4328 | ||
0a6857e7 TW |
4329 | #ifdef CONFIG_IWLWIFI_DEBUG |
4330 | if (iwl_debug_level & IWL_DL_FW_ERRORS) { | |
bb8c093b CH |
4331 | iwl4965_dump_nic_error_log(priv); |
4332 | iwl4965_dump_nic_event_log(priv); | |
4333 | iwl4965_print_rx_config_cmd(&priv->staging_rxon); | |
b481de9c ZY |
4334 | } |
4335 | #endif | |
4336 | ||
4337 | wake_up_interruptible(&priv->wait_command_queue); | |
4338 | ||
4339 | /* Keep the restart process from trying to send host | |
4340 | * commands by clearing the INIT status bit */ | |
4341 | clear_bit(STATUS_READY, &priv->status); | |
4342 | ||
4343 | if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
4344 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS, | |
4345 | "Restarting adapter due to uCode error.\n"); | |
4346 | ||
3109ece1 | 4347 | if (iwl_is_associated(priv)) { |
b481de9c ZY |
4348 | memcpy(&priv->recovery_rxon, &priv->active_rxon, |
4349 | sizeof(priv->recovery_rxon)); | |
4350 | priv->error_recovering = 1; | |
4351 | } | |
4352 | queue_work(priv->workqueue, &priv->restart); | |
4353 | } | |
4354 | } | |
4355 | ||
c79dd5b5 | 4356 | static void iwl4965_error_recovery(struct iwl_priv *priv) |
b481de9c ZY |
4357 | { |
4358 | unsigned long flags; | |
4359 | ||
4360 | memcpy(&priv->staging_rxon, &priv->recovery_rxon, | |
4361 | sizeof(priv->staging_rxon)); | |
4362 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
bb8c093b | 4363 | iwl4965_commit_rxon(priv); |
b481de9c | 4364 | |
bb8c093b | 4365 | iwl4965_rxon_add_station(priv, priv->bssid, 1); |
b481de9c ZY |
4366 | |
4367 | spin_lock_irqsave(&priv->lock, flags); | |
4368 | priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id); | |
4369 | priv->error_recovering = 0; | |
4370 | spin_unlock_irqrestore(&priv->lock, flags); | |
4371 | } | |
4372 | ||
c79dd5b5 | 4373 | static void iwl4965_irq_tasklet(struct iwl_priv *priv) |
b481de9c ZY |
4374 | { |
4375 | u32 inta, handled = 0; | |
4376 | u32 inta_fh; | |
4377 | unsigned long flags; | |
0a6857e7 | 4378 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
4379 | u32 inta_mask; |
4380 | #endif | |
4381 | ||
4382 | spin_lock_irqsave(&priv->lock, flags); | |
4383 | ||
4384 | /* Ack/clear/reset pending uCode interrupts. | |
4385 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
4386 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ | |
3395f6e9 TW |
4387 | inta = iwl_read32(priv, CSR_INT); |
4388 | iwl_write32(priv, CSR_INT, inta); | |
b481de9c ZY |
4389 | |
4390 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. | |
4391 | * Any new interrupts that happen after this, either while we're | |
4392 | * in this tasklet, or later, will show up in next ISR/tasklet. */ | |
3395f6e9 TW |
4393 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); |
4394 | iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh); | |
b481de9c | 4395 | |
0a6857e7 TW |
4396 | #ifdef CONFIG_IWLWIFI_DEBUG |
4397 | if (iwl_debug_level & IWL_DL_ISR) { | |
9fbab516 | 4398 | /* just for debug */ |
3395f6e9 | 4399 | inta_mask = iwl_read32(priv, CSR_INT_MASK); |
b481de9c ZY |
4400 | IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", |
4401 | inta, inta_mask, inta_fh); | |
4402 | } | |
4403 | #endif | |
4404 | ||
4405 | /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not | |
4406 | * atomic, make sure that inta covers all the interrupts that | |
4407 | * we've discovered, even if FH interrupt came in just after | |
4408 | * reading CSR_INT. */ | |
6f83eaa1 | 4409 | if (inta_fh & CSR49_FH_INT_RX_MASK) |
b481de9c | 4410 | inta |= CSR_INT_BIT_FH_RX; |
6f83eaa1 | 4411 | if (inta_fh & CSR49_FH_INT_TX_MASK) |
b481de9c ZY |
4412 | inta |= CSR_INT_BIT_FH_TX; |
4413 | ||
4414 | /* Now service all interrupt bits discovered above. */ | |
4415 | if (inta & CSR_INT_BIT_HW_ERR) { | |
4416 | IWL_ERROR("Microcode HW error detected. Restarting.\n"); | |
4417 | ||
4418 | /* Tell the device to stop sending interrupts */ | |
bb8c093b | 4419 | iwl4965_disable_interrupts(priv); |
b481de9c | 4420 | |
bb8c093b | 4421 | iwl4965_irq_handle_error(priv); |
b481de9c ZY |
4422 | |
4423 | handled |= CSR_INT_BIT_HW_ERR; | |
4424 | ||
4425 | spin_unlock_irqrestore(&priv->lock, flags); | |
4426 | ||
4427 | return; | |
4428 | } | |
4429 | ||
0a6857e7 TW |
4430 | #ifdef CONFIG_IWLWIFI_DEBUG |
4431 | if (iwl_debug_level & (IWL_DL_ISR)) { | |
b481de9c | 4432 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
25c03d8e JP |
4433 | if (inta & CSR_INT_BIT_SCD) |
4434 | IWL_DEBUG_ISR("Scheduler finished to transmit " | |
4435 | "the frame/frames.\n"); | |
b481de9c ZY |
4436 | |
4437 | /* Alive notification via Rx interrupt will do the real work */ | |
4438 | if (inta & CSR_INT_BIT_ALIVE) | |
4439 | IWL_DEBUG_ISR("Alive interrupt\n"); | |
4440 | } | |
4441 | #endif | |
4442 | /* Safely ignore these bits for debug checks below */ | |
25c03d8e | 4443 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); |
b481de9c | 4444 | |
9fbab516 | 4445 | /* HW RF KILL switch toggled */ |
b481de9c ZY |
4446 | if (inta & CSR_INT_BIT_RF_KILL) { |
4447 | int hw_rf_kill = 0; | |
3395f6e9 | 4448 | if (!(iwl_read32(priv, CSR_GP_CNTRL) & |
b481de9c ZY |
4449 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) |
4450 | hw_rf_kill = 1; | |
4451 | ||
4452 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR, | |
4453 | "RF_KILL bit toggled to %s.\n", | |
4454 | hw_rf_kill ? "disable radio":"enable radio"); | |
4455 | ||
4456 | /* Queue restart only if RF_KILL switch was set to "kill" | |
4457 | * when we loaded driver, and is now set to "enable". | |
4458 | * After we're Alive, RF_KILL gets handled by | |
3230455d | 4459 | * iwl4965_rx_card_state_notif() */ |
53e49093 ZY |
4460 | if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) { |
4461 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
b481de9c | 4462 | queue_work(priv->workqueue, &priv->restart); |
53e49093 | 4463 | } |
b481de9c ZY |
4464 | |
4465 | handled |= CSR_INT_BIT_RF_KILL; | |
4466 | } | |
4467 | ||
9fbab516 | 4468 | /* Chip got too hot and stopped itself */ |
b481de9c ZY |
4469 | if (inta & CSR_INT_BIT_CT_KILL) { |
4470 | IWL_ERROR("Microcode CT kill error detected.\n"); | |
4471 | handled |= CSR_INT_BIT_CT_KILL; | |
4472 | } | |
4473 | ||
4474 | /* Error detected by uCode */ | |
4475 | if (inta & CSR_INT_BIT_SW_ERR) { | |
4476 | IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n", | |
4477 | inta); | |
bb8c093b | 4478 | iwl4965_irq_handle_error(priv); |
b481de9c ZY |
4479 | handled |= CSR_INT_BIT_SW_ERR; |
4480 | } | |
4481 | ||
4482 | /* uCode wakes up after power-down sleep */ | |
4483 | if (inta & CSR_INT_BIT_WAKEUP) { | |
4484 | IWL_DEBUG_ISR("Wakeup interrupt\n"); | |
bb8c093b CH |
4485 | iwl4965_rx_queue_update_write_ptr(priv, &priv->rxq); |
4486 | iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[0]); | |
4487 | iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[1]); | |
4488 | iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[2]); | |
4489 | iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[3]); | |
4490 | iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[4]); | |
4491 | iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[5]); | |
b481de9c ZY |
4492 | |
4493 | handled |= CSR_INT_BIT_WAKEUP; | |
4494 | } | |
4495 | ||
4496 | /* All uCode command responses, including Tx command responses, | |
4497 | * Rx "responses" (frame-received notification), and other | |
4498 | * notifications from uCode come through here*/ | |
4499 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | |
bb8c093b | 4500 | iwl4965_rx_handle(priv); |
b481de9c ZY |
4501 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); |
4502 | } | |
4503 | ||
4504 | if (inta & CSR_INT_BIT_FH_TX) { | |
4505 | IWL_DEBUG_ISR("Tx interrupt\n"); | |
4506 | handled |= CSR_INT_BIT_FH_TX; | |
4507 | } | |
4508 | ||
4509 | if (inta & ~handled) | |
4510 | IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled); | |
4511 | ||
4512 | if (inta & ~CSR_INI_SET_MASK) { | |
4513 | IWL_WARNING("Disabled INTA bits 0x%08x were pending\n", | |
4514 | inta & ~CSR_INI_SET_MASK); | |
4515 | IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh); | |
4516 | } | |
4517 | ||
4518 | /* Re-enable all interrupts */ | |
0359facc MA |
4519 | /* only Re-enable if diabled by irq */ |
4520 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
4521 | iwl4965_enable_interrupts(priv); | |
b481de9c | 4522 | |
0a6857e7 TW |
4523 | #ifdef CONFIG_IWLWIFI_DEBUG |
4524 | if (iwl_debug_level & (IWL_DL_ISR)) { | |
3395f6e9 TW |
4525 | inta = iwl_read32(priv, CSR_INT); |
4526 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
4527 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | |
b481de9c ZY |
4528 | IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " |
4529 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); | |
4530 | } | |
4531 | #endif | |
4532 | spin_unlock_irqrestore(&priv->lock, flags); | |
4533 | } | |
4534 | ||
bb8c093b | 4535 | static irqreturn_t iwl4965_isr(int irq, void *data) |
b481de9c | 4536 | { |
c79dd5b5 | 4537 | struct iwl_priv *priv = data; |
b481de9c ZY |
4538 | u32 inta, inta_mask; |
4539 | u32 inta_fh; | |
4540 | if (!priv) | |
4541 | return IRQ_NONE; | |
4542 | ||
4543 | spin_lock(&priv->lock); | |
4544 | ||
4545 | /* Disable (but don't clear!) interrupts here to avoid | |
4546 | * back-to-back ISRs and sporadic interrupts from our NIC. | |
4547 | * If we have something to service, the tasklet will re-enable ints. | |
4548 | * If we *don't* have something, we'll re-enable before leaving here. */ | |
3395f6e9 TW |
4549 | inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */ |
4550 | iwl_write32(priv, CSR_INT_MASK, 0x00000000); | |
b481de9c ZY |
4551 | |
4552 | /* Discover which interrupts are active/pending */ | |
3395f6e9 TW |
4553 | inta = iwl_read32(priv, CSR_INT); |
4554 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | |
b481de9c ZY |
4555 | |
4556 | /* Ignore interrupt if there's nothing in NIC to service. | |
4557 | * This may be due to IRQ shared with another device, | |
4558 | * or due to sporadic interrupts thrown from our NIC. */ | |
4559 | if (!inta && !inta_fh) { | |
4560 | IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n"); | |
4561 | goto none; | |
4562 | } | |
4563 | ||
4564 | if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { | |
66fbb541 ON |
4565 | /* Hardware disappeared. It might have already raised |
4566 | * an interrupt */ | |
b481de9c | 4567 | IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta); |
66fbb541 | 4568 | goto unplugged; |
b481de9c ZY |
4569 | } |
4570 | ||
4571 | IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", | |
4572 | inta, inta_mask, inta_fh); | |
4573 | ||
25c03d8e JP |
4574 | inta &= ~CSR_INT_BIT_SCD; |
4575 | ||
bb8c093b | 4576 | /* iwl4965_irq_tasklet() will service interrupts and re-enable them */ |
25c03d8e JP |
4577 | if (likely(inta || inta_fh)) |
4578 | tasklet_schedule(&priv->irq_tasklet); | |
b481de9c | 4579 | |
66fbb541 ON |
4580 | unplugged: |
4581 | spin_unlock(&priv->lock); | |
b481de9c ZY |
4582 | return IRQ_HANDLED; |
4583 | ||
4584 | none: | |
4585 | /* re-enable interrupts here since we don't have anything to service. */ | |
0359facc MA |
4586 | /* only Re-enable if diabled by irq */ |
4587 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
4588 | iwl4965_enable_interrupts(priv); | |
b481de9c ZY |
4589 | spin_unlock(&priv->lock); |
4590 | return IRQ_NONE; | |
4591 | } | |
4592 | ||
b481de9c ZY |
4593 | /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after |
4594 | * sending probe req. This should be set long enough to hear probe responses | |
4595 | * from more than one AP. */ | |
4596 | #define IWL_ACTIVE_DWELL_TIME_24 (20) /* all times in msec */ | |
4597 | #define IWL_ACTIVE_DWELL_TIME_52 (10) | |
4598 | ||
4599 | /* For faster active scanning, scan will move to the next channel if fewer than | |
4600 | * PLCP_QUIET_THRESH packets are heard on this channel within | |
4601 | * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell | |
4602 | * time if it's a quiet channel (nothing responded to our probe, and there's | |
4603 | * no other traffic). | |
4604 | * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */ | |
4605 | #define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */ | |
4606 | #define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(5) /* msec */ | |
4607 | ||
4608 | /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel. | |
4609 | * Must be set longer than active dwell time. | |
4610 | * For the most reliable scan, set > AP beacon interval (typically 100msec). */ | |
4611 | #define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */ | |
4612 | #define IWL_PASSIVE_DWELL_TIME_52 (10) | |
4613 | #define IWL_PASSIVE_DWELL_BASE (100) | |
4614 | #define IWL_CHANNEL_TUNE_TIME 5 | |
4615 | ||
c79dd5b5 | 4616 | static inline u16 iwl4965_get_active_dwell_time(struct iwl_priv *priv, |
8318d78a | 4617 | enum ieee80211_band band) |
b481de9c | 4618 | { |
8318d78a | 4619 | if (band == IEEE80211_BAND_5GHZ) |
b481de9c ZY |
4620 | return IWL_ACTIVE_DWELL_TIME_52; |
4621 | else | |
4622 | return IWL_ACTIVE_DWELL_TIME_24; | |
4623 | } | |
4624 | ||
c79dd5b5 | 4625 | static u16 iwl4965_get_passive_dwell_time(struct iwl_priv *priv, |
8318d78a | 4626 | enum ieee80211_band band) |
b481de9c | 4627 | { |
8318d78a JB |
4628 | u16 active = iwl4965_get_active_dwell_time(priv, band); |
4629 | u16 passive = (band != IEEE80211_BAND_5GHZ) ? | |
b481de9c ZY |
4630 | IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 : |
4631 | IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52; | |
4632 | ||
3109ece1 | 4633 | if (iwl_is_associated(priv)) { |
b481de9c ZY |
4634 | /* If we're associated, we clamp the maximum passive |
4635 | * dwell time to be 98% of the beacon interval (minus | |
4636 | * 2 * channel tune time) */ | |
4637 | passive = priv->beacon_int; | |
4638 | if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive) | |
4639 | passive = IWL_PASSIVE_DWELL_BASE; | |
4640 | passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2; | |
4641 | } | |
4642 | ||
4643 | if (passive <= active) | |
4644 | passive = active + 1; | |
4645 | ||
4646 | return passive; | |
4647 | } | |
4648 | ||
c79dd5b5 | 4649 | static int iwl4965_get_channels_for_scan(struct iwl_priv *priv, |
8318d78a | 4650 | enum ieee80211_band band, |
b481de9c | 4651 | u8 is_active, u8 direct_mask, |
bb8c093b | 4652 | struct iwl4965_scan_channel *scan_ch) |
b481de9c ZY |
4653 | { |
4654 | const struct ieee80211_channel *channels = NULL; | |
8318d78a | 4655 | const struct ieee80211_supported_band *sband; |
bf85ea4f | 4656 | const struct iwl_channel_info *ch_info; |
b481de9c ZY |
4657 | u16 passive_dwell = 0; |
4658 | u16 active_dwell = 0; | |
4659 | int added, i; | |
4660 | ||
8318d78a JB |
4661 | sband = iwl4965_get_hw_mode(priv, band); |
4662 | if (!sband) | |
b481de9c ZY |
4663 | return 0; |
4664 | ||
8318d78a | 4665 | channels = sband->channels; |
b481de9c | 4666 | |
8318d78a JB |
4667 | active_dwell = iwl4965_get_active_dwell_time(priv, band); |
4668 | passive_dwell = iwl4965_get_passive_dwell_time(priv, band); | |
b481de9c | 4669 | |
8318d78a | 4670 | for (i = 0, added = 0; i < sband->n_channels; i++) { |
182e2e66 JB |
4671 | if (channels[i].flags & IEEE80211_CHAN_DISABLED) |
4672 | continue; | |
4673 | ||
8318d78a | 4674 | if (ieee80211_frequency_to_channel(channels[i].center_freq) == |
b481de9c | 4675 | le16_to_cpu(priv->active_rxon.channel)) { |
3109ece1 | 4676 | if (iwl_is_associated(priv)) { |
b481de9c ZY |
4677 | IWL_DEBUG_SCAN |
4678 | ("Skipping current channel %d\n", | |
4679 | le16_to_cpu(priv->active_rxon.channel)); | |
4680 | continue; | |
4681 | } | |
4682 | } else if (priv->only_active_channel) | |
4683 | continue; | |
4684 | ||
8318d78a | 4685 | scan_ch->channel = ieee80211_frequency_to_channel(channels[i].center_freq); |
b481de9c | 4686 | |
8622e705 | 4687 | ch_info = iwl_get_channel_info(priv, band, |
9fbab516 | 4688 | scan_ch->channel); |
b481de9c ZY |
4689 | if (!is_channel_valid(ch_info)) { |
4690 | IWL_DEBUG_SCAN("Channel %d is INVALID for this SKU.\n", | |
4691 | scan_ch->channel); | |
4692 | continue; | |
4693 | } | |
4694 | ||
4695 | if (!is_active || is_channel_passive(ch_info) || | |
8318d78a | 4696 | (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN)) |
b481de9c ZY |
4697 | scan_ch->type = 0; /* passive */ |
4698 | else | |
4699 | scan_ch->type = 1; /* active */ | |
4700 | ||
4701 | if (scan_ch->type & 1) | |
4702 | scan_ch->type |= (direct_mask << 1); | |
4703 | ||
4704 | if (is_channel_narrow(ch_info)) | |
4705 | scan_ch->type |= (1 << 7); | |
4706 | ||
4707 | scan_ch->active_dwell = cpu_to_le16(active_dwell); | |
4708 | scan_ch->passive_dwell = cpu_to_le16(passive_dwell); | |
4709 | ||
9fbab516 | 4710 | /* Set txpower levels to defaults */ |
b481de9c ZY |
4711 | scan_ch->tpc.dsp_atten = 110; |
4712 | /* scan_pwr_info->tpc.dsp_atten; */ | |
4713 | ||
4714 | /*scan_pwr_info->tpc.tx_gain; */ | |
8318d78a | 4715 | if (band == IEEE80211_BAND_5GHZ) |
b481de9c ZY |
4716 | scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3; |
4717 | else { | |
4718 | scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3)); | |
4719 | /* NOTE: if we were doing 6Mb OFDM for scans we'd use | |
9fbab516 | 4720 | * power level: |
8a1b0245 | 4721 | * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3; |
b481de9c ZY |
4722 | */ |
4723 | } | |
4724 | ||
4725 | IWL_DEBUG_SCAN("Scanning %d [%s %d]\n", | |
4726 | scan_ch->channel, | |
4727 | (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE", | |
4728 | (scan_ch->type & 1) ? | |
4729 | active_dwell : passive_dwell); | |
4730 | ||
4731 | scan_ch++; | |
4732 | added++; | |
4733 | } | |
4734 | ||
4735 | IWL_DEBUG_SCAN("total channels to scan %d \n", added); | |
4736 | return added; | |
4737 | } | |
4738 | ||
c79dd5b5 | 4739 | static void iwl4965_init_hw_rates(struct iwl_priv *priv, |
b481de9c ZY |
4740 | struct ieee80211_rate *rates) |
4741 | { | |
4742 | int i; | |
4743 | ||
4744 | for (i = 0; i < IWL_RATE_COUNT; i++) { | |
8318d78a JB |
4745 | rates[i].bitrate = iwl4965_rates[i].ieee * 5; |
4746 | rates[i].hw_value = i; /* Rate scaling will work on indexes */ | |
4747 | rates[i].hw_value_short = i; | |
4748 | rates[i].flags = 0; | |
4749 | if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) { | |
b481de9c | 4750 | /* |
8318d78a | 4751 | * If CCK != 1M then set short preamble rate flag. |
b481de9c | 4752 | */ |
35cdeaf4 TW |
4753 | rates[i].flags |= |
4754 | (iwl4965_rates[i].plcp == IWL_RATE_1M_PLCP) ? | |
4755 | 0 : IEEE80211_RATE_SHORT_PREAMBLE; | |
b481de9c | 4756 | } |
b481de9c | 4757 | } |
b481de9c ZY |
4758 | } |
4759 | ||
4760 | /** | |
bb8c093b | 4761 | * iwl4965_init_geos - Initialize mac80211's geo/channel info based from eeprom |
b481de9c | 4762 | */ |
bf85ea4f | 4763 | int iwl4965_init_geos(struct iwl_priv *priv) |
b481de9c | 4764 | { |
bf85ea4f | 4765 | struct iwl_channel_info *ch; |
8211ef78 | 4766 | struct ieee80211_supported_band *sband; |
b481de9c ZY |
4767 | struct ieee80211_channel *channels; |
4768 | struct ieee80211_channel *geo_ch; | |
4769 | struct ieee80211_rate *rates; | |
4770 | int i = 0; | |
b481de9c | 4771 | |
8318d78a JB |
4772 | if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates || |
4773 | priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) { | |
b481de9c ZY |
4774 | IWL_DEBUG_INFO("Geography modes already initialized.\n"); |
4775 | set_bit(STATUS_GEO_CONFIGURED, &priv->status); | |
4776 | return 0; | |
4777 | } | |
4778 | ||
b481de9c ZY |
4779 | channels = kzalloc(sizeof(struct ieee80211_channel) * |
4780 | priv->channel_count, GFP_KERNEL); | |
8318d78a | 4781 | if (!channels) |
b481de9c | 4782 | return -ENOMEM; |
b481de9c | 4783 | |
8211ef78 | 4784 | rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)), |
b481de9c ZY |
4785 | GFP_KERNEL); |
4786 | if (!rates) { | |
b481de9c ZY |
4787 | kfree(channels); |
4788 | return -ENOMEM; | |
4789 | } | |
4790 | ||
b481de9c | 4791 | /* 5.2GHz channels start after the 2.4GHz channels */ |
8211ef78 | 4792 | sband = &priv->bands[IEEE80211_BAND_5GHZ]; |
bf85ea4f | 4793 | sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)]; |
8211ef78 TW |
4794 | /* just OFDM */ |
4795 | sband->bitrates = &rates[IWL_FIRST_OFDM_RATE]; | |
4796 | sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE; | |
8318d78a | 4797 | |
1ea87396 | 4798 | iwl4965_init_ht_hw_capab(priv, &sband->ht_info, IEEE80211_BAND_5GHZ); |
78330fdd | 4799 | |
8211ef78 TW |
4800 | sband = &priv->bands[IEEE80211_BAND_2GHZ]; |
4801 | sband->channels = channels; | |
4802 | /* OFDM & CCK */ | |
4803 | sband->bitrates = rates; | |
4804 | sband->n_bitrates = IWL_RATE_COUNT; | |
b481de9c | 4805 | |
1ea87396 | 4806 | iwl4965_init_ht_hw_capab(priv, &sband->ht_info, IEEE80211_BAND_2GHZ); |
78330fdd | 4807 | |
b481de9c ZY |
4808 | priv->ieee_channels = channels; |
4809 | priv->ieee_rates = rates; | |
4810 | ||
bb8c093b | 4811 | iwl4965_init_hw_rates(priv, rates); |
b481de9c | 4812 | |
8211ef78 | 4813 | for (i = 0; i < priv->channel_count; i++) { |
b481de9c ZY |
4814 | ch = &priv->channel_info[i]; |
4815 | ||
8211ef78 TW |
4816 | /* FIXME: might be removed if scan is OK */ |
4817 | if (!is_channel_valid(ch)) | |
b481de9c | 4818 | continue; |
b481de9c | 4819 | |
8211ef78 TW |
4820 | if (is_channel_a_band(ch)) |
4821 | sband = &priv->bands[IEEE80211_BAND_5GHZ]; | |
4822 | else | |
4823 | sband = &priv->bands[IEEE80211_BAND_2GHZ]; | |
b481de9c | 4824 | |
8211ef78 TW |
4825 | geo_ch = &sband->channels[sband->n_channels++]; |
4826 | ||
4827 | geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel); | |
8318d78a JB |
4828 | geo_ch->max_power = ch->max_power_avg; |
4829 | geo_ch->max_antenna_gain = 0xff; | |
7b72304d | 4830 | geo_ch->hw_value = ch->channel; |
b481de9c ZY |
4831 | |
4832 | if (is_channel_valid(ch)) { | |
8318d78a JB |
4833 | if (!(ch->flags & EEPROM_CHANNEL_IBSS)) |
4834 | geo_ch->flags |= IEEE80211_CHAN_NO_IBSS; | |
b481de9c | 4835 | |
8318d78a JB |
4836 | if (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) |
4837 | geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN; | |
b481de9c ZY |
4838 | |
4839 | if (ch->flags & EEPROM_CHANNEL_RADAR) | |
8318d78a | 4840 | geo_ch->flags |= IEEE80211_CHAN_RADAR; |
b481de9c ZY |
4841 | |
4842 | if (ch->max_power_avg > priv->max_channel_txpower_limit) | |
4843 | priv->max_channel_txpower_limit = | |
4844 | ch->max_power_avg; | |
8211ef78 | 4845 | } else { |
8318d78a | 4846 | geo_ch->flags |= IEEE80211_CHAN_DISABLED; |
8211ef78 TW |
4847 | } |
4848 | ||
4849 | /* Save flags for reg domain usage */ | |
4850 | geo_ch->orig_flags = geo_ch->flags; | |
4851 | ||
4852 | IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n", | |
4853 | ch->channel, geo_ch->center_freq, | |
4854 | is_channel_a_band(ch) ? "5.2" : "2.4", | |
4855 | geo_ch->flags & IEEE80211_CHAN_DISABLED ? | |
4856 | "restricted" : "valid", | |
4857 | geo_ch->flags); | |
b481de9c ZY |
4858 | } |
4859 | ||
82b9a121 TW |
4860 | if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) && |
4861 | priv->cfg->sku & IWL_SKU_A) { | |
b481de9c ZY |
4862 | printk(KERN_INFO DRV_NAME |
4863 | ": Incorrectly detected BG card as ABG. Please send " | |
4864 | "your PCI ID 0x%04X:0x%04X to maintainer.\n", | |
4865 | priv->pci_dev->device, priv->pci_dev->subsystem_device); | |
82b9a121 | 4866 | priv->cfg->sku &= ~IWL_SKU_A; |
b481de9c ZY |
4867 | } |
4868 | ||
4869 | printk(KERN_INFO DRV_NAME | |
4870 | ": Tunable channels: %d 802.11bg, %d 802.11a channels\n", | |
8318d78a JB |
4871 | priv->bands[IEEE80211_BAND_2GHZ].n_channels, |
4872 | priv->bands[IEEE80211_BAND_5GHZ].n_channels); | |
b481de9c | 4873 | |
e0e0a67e JL |
4874 | if (priv->bands[IEEE80211_BAND_2GHZ].n_channels) |
4875 | priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = | |
4876 | &priv->bands[IEEE80211_BAND_2GHZ]; | |
4877 | if (priv->bands[IEEE80211_BAND_5GHZ].n_channels) | |
4878 | priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
4879 | &priv->bands[IEEE80211_BAND_5GHZ]; | |
b481de9c | 4880 | |
b481de9c ZY |
4881 | set_bit(STATUS_GEO_CONFIGURED, &priv->status); |
4882 | ||
4883 | return 0; | |
4884 | } | |
4885 | ||
849e0dce RC |
4886 | /* |
4887 | * iwl4965_free_geos - undo allocations in iwl4965_init_geos | |
4888 | */ | |
bf85ea4f | 4889 | void iwl4965_free_geos(struct iwl_priv *priv) |
849e0dce | 4890 | { |
849e0dce RC |
4891 | kfree(priv->ieee_channels); |
4892 | kfree(priv->ieee_rates); | |
4893 | clear_bit(STATUS_GEO_CONFIGURED, &priv->status); | |
4894 | } | |
4895 | ||
b481de9c ZY |
4896 | /****************************************************************************** |
4897 | * | |
4898 | * uCode download functions | |
4899 | * | |
4900 | ******************************************************************************/ | |
4901 | ||
c79dd5b5 | 4902 | static void iwl4965_dealloc_ucode_pci(struct iwl_priv *priv) |
b481de9c | 4903 | { |
98c92211 TW |
4904 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code); |
4905 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data); | |
4906 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup); | |
4907 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init); | |
4908 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data); | |
4909 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot); | |
b481de9c ZY |
4910 | } |
4911 | ||
4912 | /** | |
bb8c093b | 4913 | * iwl4965_verify_inst_full - verify runtime uCode image in card vs. host, |
b481de9c ZY |
4914 | * looking at all data. |
4915 | */ | |
c79dd5b5 | 4916 | static int iwl4965_verify_inst_full(struct iwl_priv *priv, __le32 *image, |
9fbab516 | 4917 | u32 len) |
b481de9c ZY |
4918 | { |
4919 | u32 val; | |
4920 | u32 save_len = len; | |
4921 | int rc = 0; | |
4922 | u32 errcnt; | |
4923 | ||
4924 | IWL_DEBUG_INFO("ucode inst image size is %u\n", len); | |
4925 | ||
3395f6e9 | 4926 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
4927 | if (rc) |
4928 | return rc; | |
4929 | ||
3395f6e9 | 4930 | iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND); |
b481de9c ZY |
4931 | |
4932 | errcnt = 0; | |
4933 | for (; len > 0; len -= sizeof(u32), image++) { | |
4934 | /* read data comes through single port, auto-incr addr */ | |
4935 | /* NOTE: Use the debugless read so we don't flood kernel log | |
4936 | * if IWL_DL_IO is set */ | |
3395f6e9 | 4937 | val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b481de9c ZY |
4938 | if (val != le32_to_cpu(*image)) { |
4939 | IWL_ERROR("uCode INST section is invalid at " | |
4940 | "offset 0x%x, is 0x%x, s/b 0x%x\n", | |
4941 | save_len - len, val, le32_to_cpu(*image)); | |
4942 | rc = -EIO; | |
4943 | errcnt++; | |
4944 | if (errcnt >= 20) | |
4945 | break; | |
4946 | } | |
4947 | } | |
4948 | ||
3395f6e9 | 4949 | iwl_release_nic_access(priv); |
b481de9c ZY |
4950 | |
4951 | if (!errcnt) | |
4952 | IWL_DEBUG_INFO | |
4953 | ("ucode image in INSTRUCTION memory is good\n"); | |
4954 | ||
4955 | return rc; | |
4956 | } | |
4957 | ||
4958 | ||
4959 | /** | |
bb8c093b | 4960 | * iwl4965_verify_inst_sparse - verify runtime uCode image in card vs. host, |
b481de9c ZY |
4961 | * using sample data 100 bytes apart. If these sample points are good, |
4962 | * it's a pretty good bet that everything between them is good, too. | |
4963 | */ | |
c79dd5b5 | 4964 | static int iwl4965_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len) |
b481de9c ZY |
4965 | { |
4966 | u32 val; | |
4967 | int rc = 0; | |
4968 | u32 errcnt = 0; | |
4969 | u32 i; | |
4970 | ||
4971 | IWL_DEBUG_INFO("ucode inst image size is %u\n", len); | |
4972 | ||
3395f6e9 | 4973 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
4974 | if (rc) |
4975 | return rc; | |
4976 | ||
4977 | for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) { | |
4978 | /* read data comes through single port, auto-incr addr */ | |
4979 | /* NOTE: Use the debugless read so we don't flood kernel log | |
4980 | * if IWL_DL_IO is set */ | |
3395f6e9 | 4981 | iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, |
b481de9c | 4982 | i + RTC_INST_LOWER_BOUND); |
3395f6e9 | 4983 | val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b481de9c ZY |
4984 | if (val != le32_to_cpu(*image)) { |
4985 | #if 0 /* Enable this if you want to see details */ | |
4986 | IWL_ERROR("uCode INST section is invalid at " | |
4987 | "offset 0x%x, is 0x%x, s/b 0x%x\n", | |
4988 | i, val, *image); | |
4989 | #endif | |
4990 | rc = -EIO; | |
4991 | errcnt++; | |
4992 | if (errcnt >= 3) | |
4993 | break; | |
4994 | } | |
4995 | } | |
4996 | ||
3395f6e9 | 4997 | iwl_release_nic_access(priv); |
b481de9c ZY |
4998 | |
4999 | return rc; | |
5000 | } | |
5001 | ||
5002 | ||
5003 | /** | |
bb8c093b | 5004 | * iwl4965_verify_ucode - determine which instruction image is in SRAM, |
b481de9c ZY |
5005 | * and verify its contents |
5006 | */ | |
c79dd5b5 | 5007 | static int iwl4965_verify_ucode(struct iwl_priv *priv) |
b481de9c ZY |
5008 | { |
5009 | __le32 *image; | |
5010 | u32 len; | |
5011 | int rc = 0; | |
5012 | ||
5013 | /* Try bootstrap */ | |
5014 | image = (__le32 *)priv->ucode_boot.v_addr; | |
5015 | len = priv->ucode_boot.len; | |
bb8c093b | 5016 | rc = iwl4965_verify_inst_sparse(priv, image, len); |
b481de9c ZY |
5017 | if (rc == 0) { |
5018 | IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n"); | |
5019 | return 0; | |
5020 | } | |
5021 | ||
5022 | /* Try initialize */ | |
5023 | image = (__le32 *)priv->ucode_init.v_addr; | |
5024 | len = priv->ucode_init.len; | |
bb8c093b | 5025 | rc = iwl4965_verify_inst_sparse(priv, image, len); |
b481de9c ZY |
5026 | if (rc == 0) { |
5027 | IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n"); | |
5028 | return 0; | |
5029 | } | |
5030 | ||
5031 | /* Try runtime/protocol */ | |
5032 | image = (__le32 *)priv->ucode_code.v_addr; | |
5033 | len = priv->ucode_code.len; | |
bb8c093b | 5034 | rc = iwl4965_verify_inst_sparse(priv, image, len); |
b481de9c ZY |
5035 | if (rc == 0) { |
5036 | IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n"); | |
5037 | return 0; | |
5038 | } | |
5039 | ||
5040 | IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n"); | |
5041 | ||
9fbab516 BC |
5042 | /* Since nothing seems to match, show first several data entries in |
5043 | * instruction SRAM, so maybe visual inspection will give a clue. | |
5044 | * Selection of bootstrap image (vs. other images) is arbitrary. */ | |
b481de9c ZY |
5045 | image = (__le32 *)priv->ucode_boot.v_addr; |
5046 | len = priv->ucode_boot.len; | |
bb8c093b | 5047 | rc = iwl4965_verify_inst_full(priv, image, len); |
b481de9c ZY |
5048 | |
5049 | return rc; | |
5050 | } | |
5051 | ||
c79dd5b5 | 5052 | static void iwl4965_nic_start(struct iwl_priv *priv) |
b481de9c ZY |
5053 | { |
5054 | /* Remove all resets to allow NIC to operate */ | |
3395f6e9 | 5055 | iwl_write32(priv, CSR_RESET, 0); |
b481de9c ZY |
5056 | } |
5057 | ||
90e759d1 | 5058 | |
b481de9c | 5059 | /** |
bb8c093b | 5060 | * iwl4965_read_ucode - Read uCode images from disk file. |
b481de9c ZY |
5061 | * |
5062 | * Copy into buffers for card to fetch via bus-mastering | |
5063 | */ | |
c79dd5b5 | 5064 | static int iwl4965_read_ucode(struct iwl_priv *priv) |
b481de9c | 5065 | { |
bb8c093b | 5066 | struct iwl4965_ucode *ucode; |
90e759d1 | 5067 | int ret; |
b481de9c | 5068 | const struct firmware *ucode_raw; |
4bf775cd | 5069 | const char *name = priv->cfg->fw_name; |
b481de9c ZY |
5070 | u8 *src; |
5071 | size_t len; | |
5072 | u32 ver, inst_size, data_size, init_size, init_data_size, boot_size; | |
5073 | ||
5074 | /* Ask kernel firmware_class module to get the boot firmware off disk. | |
5075 | * request_firmware() is synchronous, file is in memory on return. */ | |
90e759d1 TW |
5076 | ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev); |
5077 | if (ret < 0) { | |
5078 | IWL_ERROR("%s firmware file req failed: Reason %d\n", | |
5079 | name, ret); | |
b481de9c ZY |
5080 | goto error; |
5081 | } | |
5082 | ||
5083 | IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n", | |
5084 | name, ucode_raw->size); | |
5085 | ||
5086 | /* Make sure that we got at least our header! */ | |
5087 | if (ucode_raw->size < sizeof(*ucode)) { | |
5088 | IWL_ERROR("File size way too small!\n"); | |
90e759d1 | 5089 | ret = -EINVAL; |
b481de9c ZY |
5090 | goto err_release; |
5091 | } | |
5092 | ||
5093 | /* Data from ucode file: header followed by uCode images */ | |
5094 | ucode = (void *)ucode_raw->data; | |
5095 | ||
5096 | ver = le32_to_cpu(ucode->ver); | |
5097 | inst_size = le32_to_cpu(ucode->inst_size); | |
5098 | data_size = le32_to_cpu(ucode->data_size); | |
5099 | init_size = le32_to_cpu(ucode->init_size); | |
5100 | init_data_size = le32_to_cpu(ucode->init_data_size); | |
5101 | boot_size = le32_to_cpu(ucode->boot_size); | |
5102 | ||
5103 | IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver); | |
5104 | IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", | |
5105 | inst_size); | |
5106 | IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", | |
5107 | data_size); | |
5108 | IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", | |
5109 | init_size); | |
5110 | IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", | |
5111 | init_data_size); | |
5112 | IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", | |
5113 | boot_size); | |
5114 | ||
5115 | /* Verify size of file vs. image size info in file's header */ | |
5116 | if (ucode_raw->size < sizeof(*ucode) + | |
5117 | inst_size + data_size + init_size + | |
5118 | init_data_size + boot_size) { | |
5119 | ||
5120 | IWL_DEBUG_INFO("uCode file size %d too small\n", | |
5121 | (int)ucode_raw->size); | |
90e759d1 | 5122 | ret = -EINVAL; |
b481de9c ZY |
5123 | goto err_release; |
5124 | } | |
5125 | ||
5126 | /* Verify that uCode images will fit in card's SRAM */ | |
5127 | if (inst_size > IWL_MAX_INST_SIZE) { | |
90e759d1 TW |
5128 | IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n", |
5129 | inst_size); | |
5130 | ret = -EINVAL; | |
b481de9c ZY |
5131 | goto err_release; |
5132 | } | |
5133 | ||
5134 | if (data_size > IWL_MAX_DATA_SIZE) { | |
90e759d1 TW |
5135 | IWL_DEBUG_INFO("uCode data len %d too large to fit in\n", |
5136 | data_size); | |
5137 | ret = -EINVAL; | |
b481de9c ZY |
5138 | goto err_release; |
5139 | } | |
5140 | if (init_size > IWL_MAX_INST_SIZE) { | |
5141 | IWL_DEBUG_INFO | |
90e759d1 TW |
5142 | ("uCode init instr len %d too large to fit in\n", |
5143 | init_size); | |
5144 | ret = -EINVAL; | |
b481de9c ZY |
5145 | goto err_release; |
5146 | } | |
5147 | if (init_data_size > IWL_MAX_DATA_SIZE) { | |
5148 | IWL_DEBUG_INFO | |
90e759d1 TW |
5149 | ("uCode init data len %d too large to fit in\n", |
5150 | init_data_size); | |
5151 | ret = -EINVAL; | |
b481de9c ZY |
5152 | goto err_release; |
5153 | } | |
5154 | if (boot_size > IWL_MAX_BSM_SIZE) { | |
5155 | IWL_DEBUG_INFO | |
90e759d1 TW |
5156 | ("uCode boot instr len %d too large to fit in\n", |
5157 | boot_size); | |
5158 | ret = -EINVAL; | |
b481de9c ZY |
5159 | goto err_release; |
5160 | } | |
5161 | ||
5162 | /* Allocate ucode buffers for card's bus-master loading ... */ | |
5163 | ||
5164 | /* Runtime instructions and 2 copies of data: | |
5165 | * 1) unmodified from disk | |
5166 | * 2) backup cache for save/restore during power-downs */ | |
5167 | priv->ucode_code.len = inst_size; | |
98c92211 | 5168 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code); |
b481de9c ZY |
5169 | |
5170 | priv->ucode_data.len = data_size; | |
98c92211 | 5171 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data); |
b481de9c ZY |
5172 | |
5173 | priv->ucode_data_backup.len = data_size; | |
98c92211 | 5174 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup); |
b481de9c ZY |
5175 | |
5176 | /* Initialization instructions and data */ | |
90e759d1 TW |
5177 | if (init_size && init_data_size) { |
5178 | priv->ucode_init.len = init_size; | |
98c92211 | 5179 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init); |
90e759d1 TW |
5180 | |
5181 | priv->ucode_init_data.len = init_data_size; | |
98c92211 | 5182 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data); |
90e759d1 TW |
5183 | |
5184 | if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr) | |
5185 | goto err_pci_alloc; | |
5186 | } | |
b481de9c ZY |
5187 | |
5188 | /* Bootstrap (instructions only, no data) */ | |
90e759d1 TW |
5189 | if (boot_size) { |
5190 | priv->ucode_boot.len = boot_size; | |
98c92211 | 5191 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot); |
b481de9c | 5192 | |
90e759d1 TW |
5193 | if (!priv->ucode_boot.v_addr) |
5194 | goto err_pci_alloc; | |
5195 | } | |
b481de9c ZY |
5196 | |
5197 | /* Copy images into buffers for card's bus-master reads ... */ | |
5198 | ||
5199 | /* Runtime instructions (first block of data in file) */ | |
5200 | src = &ucode->data[0]; | |
5201 | len = priv->ucode_code.len; | |
90e759d1 | 5202 | IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len); |
b481de9c ZY |
5203 | memcpy(priv->ucode_code.v_addr, src, len); |
5204 | IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n", | |
5205 | priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr); | |
5206 | ||
5207 | /* Runtime data (2nd block) | |
bb8c093b | 5208 | * NOTE: Copy into backup buffer will be done in iwl4965_up() */ |
b481de9c ZY |
5209 | src = &ucode->data[inst_size]; |
5210 | len = priv->ucode_data.len; | |
90e759d1 | 5211 | IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len); |
b481de9c ZY |
5212 | memcpy(priv->ucode_data.v_addr, src, len); |
5213 | memcpy(priv->ucode_data_backup.v_addr, src, len); | |
5214 | ||
5215 | /* Initialization instructions (3rd block) */ | |
5216 | if (init_size) { | |
5217 | src = &ucode->data[inst_size + data_size]; | |
5218 | len = priv->ucode_init.len; | |
90e759d1 TW |
5219 | IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n", |
5220 | len); | |
b481de9c ZY |
5221 | memcpy(priv->ucode_init.v_addr, src, len); |
5222 | } | |
5223 | ||
5224 | /* Initialization data (4th block) */ | |
5225 | if (init_data_size) { | |
5226 | src = &ucode->data[inst_size + data_size + init_size]; | |
5227 | len = priv->ucode_init_data.len; | |
90e759d1 TW |
5228 | IWL_DEBUG_INFO("Copying (but not loading) init data len %Zd\n", |
5229 | len); | |
b481de9c ZY |
5230 | memcpy(priv->ucode_init_data.v_addr, src, len); |
5231 | } | |
5232 | ||
5233 | /* Bootstrap instructions (5th block) */ | |
5234 | src = &ucode->data[inst_size + data_size + init_size + init_data_size]; | |
5235 | len = priv->ucode_boot.len; | |
90e759d1 | 5236 | IWL_DEBUG_INFO("Copying (but not loading) boot instr len %Zd\n", len); |
b481de9c ZY |
5237 | memcpy(priv->ucode_boot.v_addr, src, len); |
5238 | ||
5239 | /* We have our copies now, allow OS release its copies */ | |
5240 | release_firmware(ucode_raw); | |
5241 | return 0; | |
5242 | ||
5243 | err_pci_alloc: | |
5244 | IWL_ERROR("failed to allocate pci memory\n"); | |
90e759d1 | 5245 | ret = -ENOMEM; |
bb8c093b | 5246 | iwl4965_dealloc_ucode_pci(priv); |
b481de9c ZY |
5247 | |
5248 | err_release: | |
5249 | release_firmware(ucode_raw); | |
5250 | ||
5251 | error: | |
90e759d1 | 5252 | return ret; |
b481de9c ZY |
5253 | } |
5254 | ||
5255 | ||
5256 | /** | |
bb8c093b | 5257 | * iwl4965_set_ucode_ptrs - Set uCode address location |
b481de9c ZY |
5258 | * |
5259 | * Tell initialization uCode where to find runtime uCode. | |
5260 | * | |
5261 | * BSM registers initially contain pointers to initialization uCode. | |
5262 | * We need to replace them to load runtime uCode inst and data, | |
5263 | * and to save runtime data when powering down. | |
5264 | */ | |
c79dd5b5 | 5265 | static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv) |
b481de9c ZY |
5266 | { |
5267 | dma_addr_t pinst; | |
5268 | dma_addr_t pdata; | |
5269 | int rc = 0; | |
5270 | unsigned long flags; | |
5271 | ||
5272 | /* bits 35:4 for 4965 */ | |
5273 | pinst = priv->ucode_code.p_addr >> 4; | |
5274 | pdata = priv->ucode_data_backup.p_addr >> 4; | |
5275 | ||
5276 | spin_lock_irqsave(&priv->lock, flags); | |
3395f6e9 | 5277 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
5278 | if (rc) { |
5279 | spin_unlock_irqrestore(&priv->lock, flags); | |
5280 | return rc; | |
5281 | } | |
5282 | ||
5283 | /* Tell bootstrap uCode where to find image to load */ | |
3395f6e9 TW |
5284 | iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); |
5285 | iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); | |
5286 | iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, | |
b481de9c ZY |
5287 | priv->ucode_data.len); |
5288 | ||
5289 | /* Inst bytecount must be last to set up, bit 31 signals uCode | |
5290 | * that all new ptr/size info is in place */ | |
3395f6e9 | 5291 | iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, |
b481de9c ZY |
5292 | priv->ucode_code.len | BSM_DRAM_INST_LOAD); |
5293 | ||
3395f6e9 | 5294 | iwl_release_nic_access(priv); |
b481de9c ZY |
5295 | |
5296 | spin_unlock_irqrestore(&priv->lock, flags); | |
5297 | ||
5298 | IWL_DEBUG_INFO("Runtime uCode pointers are set.\n"); | |
5299 | ||
5300 | return rc; | |
5301 | } | |
5302 | ||
5303 | /** | |
bb8c093b | 5304 | * iwl4965_init_alive_start - Called after REPLY_ALIVE notification received |
b481de9c ZY |
5305 | * |
5306 | * Called after REPLY_ALIVE notification received from "initialize" uCode. | |
5307 | * | |
5308 | * The 4965 "initialize" ALIVE reply contains calibration data for: | |
5309 | * Voltage, temperature, and MIMO tx gain correction, now stored in priv | |
5310 | * (3945 does not contain this data). | |
5311 | * | |
5312 | * Tell "initialize" uCode to go ahead and load the runtime uCode. | |
5313 | */ | |
c79dd5b5 | 5314 | static void iwl4965_init_alive_start(struct iwl_priv *priv) |
b481de9c ZY |
5315 | { |
5316 | /* Check alive response for "valid" sign from uCode */ | |
5317 | if (priv->card_alive_init.is_valid != UCODE_VALID_OK) { | |
5318 | /* We had an error bringing up the hardware, so take it | |
5319 | * all the way back down so we can try again */ | |
5320 | IWL_DEBUG_INFO("Initialize Alive failed.\n"); | |
5321 | goto restart; | |
5322 | } | |
5323 | ||
5324 | /* Bootstrap uCode has loaded initialize uCode ... verify inst image. | |
5325 | * This is a paranoid check, because we would not have gotten the | |
5326 | * "initialize" alive if code weren't properly loaded. */ | |
bb8c093b | 5327 | if (iwl4965_verify_ucode(priv)) { |
b481de9c ZY |
5328 | /* Runtime instruction load was bad; |
5329 | * take it all the way back down so we can try again */ | |
5330 | IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n"); | |
5331 | goto restart; | |
5332 | } | |
5333 | ||
5334 | /* Calculate temperature */ | |
5335 | priv->temperature = iwl4965_get_temperature(priv); | |
5336 | ||
5337 | /* Send pointers to protocol/runtime uCode image ... init code will | |
5338 | * load and launch runtime uCode, which will send us another "Alive" | |
5339 | * notification. */ | |
5340 | IWL_DEBUG_INFO("Initialization Alive received.\n"); | |
bb8c093b | 5341 | if (iwl4965_set_ucode_ptrs(priv)) { |
b481de9c ZY |
5342 | /* Runtime instruction load won't happen; |
5343 | * take it all the way back down so we can try again */ | |
5344 | IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n"); | |
5345 | goto restart; | |
5346 | } | |
5347 | return; | |
5348 | ||
5349 | restart: | |
5350 | queue_work(priv->workqueue, &priv->restart); | |
5351 | } | |
5352 | ||
5353 | ||
5354 | /** | |
bb8c093b | 5355 | * iwl4965_alive_start - called after REPLY_ALIVE notification received |
b481de9c | 5356 | * from protocol/runtime uCode (initialization uCode's |
bb8c093b | 5357 | * Alive gets handled by iwl4965_init_alive_start()). |
b481de9c | 5358 | */ |
c79dd5b5 | 5359 | static void iwl4965_alive_start(struct iwl_priv *priv) |
b481de9c | 5360 | { |
57aab75a | 5361 | int ret = 0; |
b481de9c ZY |
5362 | |
5363 | IWL_DEBUG_INFO("Runtime Alive received.\n"); | |
5364 | ||
5365 | if (priv->card_alive.is_valid != UCODE_VALID_OK) { | |
5366 | /* We had an error bringing up the hardware, so take it | |
5367 | * all the way back down so we can try again */ | |
5368 | IWL_DEBUG_INFO("Alive failed.\n"); | |
5369 | goto restart; | |
5370 | } | |
5371 | ||
5372 | /* Initialize uCode has loaded Runtime uCode ... verify inst image. | |
5373 | * This is a paranoid check, because we would not have gotten the | |
5374 | * "runtime" alive if code weren't properly loaded. */ | |
bb8c093b | 5375 | if (iwl4965_verify_ucode(priv)) { |
b481de9c ZY |
5376 | /* Runtime instruction load was bad; |
5377 | * take it all the way back down so we can try again */ | |
5378 | IWL_DEBUG_INFO("Bad runtime uCode load.\n"); | |
5379 | goto restart; | |
5380 | } | |
5381 | ||
bf85ea4f | 5382 | iwlcore_clear_stations_table(priv); |
b481de9c | 5383 | |
57aab75a TW |
5384 | ret = priv->cfg->ops->lib->alive_notify(priv); |
5385 | if (ret) { | |
b481de9c | 5386 | IWL_WARNING("Could not complete ALIVE transition [ntf]: %d\n", |
57aab75a | 5387 | ret); |
b481de9c ZY |
5388 | goto restart; |
5389 | } | |
5390 | ||
9fbab516 | 5391 | /* After the ALIVE response, we can send host commands to 4965 uCode */ |
b481de9c ZY |
5392 | set_bit(STATUS_ALIVE, &priv->status); |
5393 | ||
5394 | /* Clear out the uCode error bit if it is set */ | |
5395 | clear_bit(STATUS_FW_ERROR, &priv->status); | |
5396 | ||
fee1247a | 5397 | if (iwl_is_rfkill(priv)) |
b481de9c ZY |
5398 | return; |
5399 | ||
5a66926a | 5400 | ieee80211_start_queues(priv->hw); |
b481de9c ZY |
5401 | |
5402 | priv->active_rate = priv->rates_mask; | |
5403 | priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK; | |
5404 | ||
bb8c093b | 5405 | iwl4965_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode)); |
b481de9c | 5406 | |
3109ece1 | 5407 | if (iwl_is_associated(priv)) { |
bb8c093b CH |
5408 | struct iwl4965_rxon_cmd *active_rxon = |
5409 | (struct iwl4965_rxon_cmd *)(&priv->active_rxon); | |
b481de9c ZY |
5410 | |
5411 | memcpy(&priv->staging_rxon, &priv->active_rxon, | |
5412 | sizeof(priv->staging_rxon)); | |
5413 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
5414 | } else { | |
5415 | /* Initialize our rx_config data */ | |
bb8c093b | 5416 | iwl4965_connection_init_rx_config(priv); |
b481de9c ZY |
5417 | memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN); |
5418 | } | |
5419 | ||
9fbab516 | 5420 | /* Configure Bluetooth device coexistence support */ |
bb8c093b | 5421 | iwl4965_send_bt_config(priv); |
b481de9c ZY |
5422 | |
5423 | /* Configure the adapter for unassociated operation */ | |
bb8c093b | 5424 | iwl4965_commit_rxon(priv); |
b481de9c ZY |
5425 | |
5426 | /* At this point, the NIC is initialized and operational */ | |
5427 | priv->notif_missed_beacons = 0; | |
b481de9c ZY |
5428 | |
5429 | iwl4965_rf_kill_ct_config(priv); | |
5a66926a | 5430 | |
fe00b5a5 RC |
5431 | iwl_leds_register(priv); |
5432 | ||
b481de9c | 5433 | IWL_DEBUG_INFO("ALIVE processing complete.\n"); |
a9f46786 | 5434 | set_bit(STATUS_READY, &priv->status); |
5a66926a | 5435 | wake_up_interruptible(&priv->wait_command_queue); |
b481de9c ZY |
5436 | |
5437 | if (priv->error_recovering) | |
bb8c093b | 5438 | iwl4965_error_recovery(priv); |
b481de9c | 5439 | |
c8381fdc | 5440 | iwlcore_low_level_notify(priv, IWLCORE_START_EVT); |
84363e6e | 5441 | ieee80211_notify_mac(priv->hw, IEEE80211_NOTIFY_RE_ASSOC); |
b481de9c ZY |
5442 | return; |
5443 | ||
5444 | restart: | |
5445 | queue_work(priv->workqueue, &priv->restart); | |
5446 | } | |
5447 | ||
c79dd5b5 | 5448 | static void iwl4965_cancel_deferred_work(struct iwl_priv *priv); |
b481de9c | 5449 | |
c79dd5b5 | 5450 | static void __iwl4965_down(struct iwl_priv *priv) |
b481de9c ZY |
5451 | { |
5452 | unsigned long flags; | |
5453 | int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status); | |
5454 | struct ieee80211_conf *conf = NULL; | |
5455 | ||
5456 | IWL_DEBUG_INFO(DRV_NAME " is going down\n"); | |
5457 | ||
5458 | conf = ieee80211_get_hw_conf(priv->hw); | |
5459 | ||
5460 | if (!exit_pending) | |
5461 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
5462 | ||
ab53d8af MA |
5463 | iwl_leds_unregister(priv); |
5464 | ||
c8381fdc MA |
5465 | iwlcore_low_level_notify(priv, IWLCORE_STOP_EVT); |
5466 | ||
bf85ea4f | 5467 | iwlcore_clear_stations_table(priv); |
b481de9c ZY |
5468 | |
5469 | /* Unblock any waiting calls */ | |
5470 | wake_up_interruptible_all(&priv->wait_command_queue); | |
5471 | ||
b481de9c ZY |
5472 | /* Wipe out the EXIT_PENDING status bit if we are not actually |
5473 | * exiting the module */ | |
5474 | if (!exit_pending) | |
5475 | clear_bit(STATUS_EXIT_PENDING, &priv->status); | |
5476 | ||
5477 | /* stop and reset the on-board processor */ | |
3395f6e9 | 5478 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
b481de9c ZY |
5479 | |
5480 | /* tell the device to stop sending interrupts */ | |
0359facc | 5481 | spin_lock_irqsave(&priv->lock, flags); |
bb8c093b | 5482 | iwl4965_disable_interrupts(priv); |
0359facc MA |
5483 | spin_unlock_irqrestore(&priv->lock, flags); |
5484 | iwl_synchronize_irq(priv); | |
b481de9c ZY |
5485 | |
5486 | if (priv->mac80211_registered) | |
5487 | ieee80211_stop_queues(priv->hw); | |
5488 | ||
bb8c093b | 5489 | /* If we have not previously called iwl4965_init() then |
b481de9c | 5490 | * clear all bits but the RF Kill and SUSPEND bits and return */ |
fee1247a | 5491 | if (!iwl_is_init(priv)) { |
b481de9c ZY |
5492 | priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) << |
5493 | STATUS_RF_KILL_HW | | |
5494 | test_bit(STATUS_RF_KILL_SW, &priv->status) << | |
5495 | STATUS_RF_KILL_SW | | |
9788864e RC |
5496 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
5497 | STATUS_GEO_CONFIGURED | | |
b481de9c ZY |
5498 | test_bit(STATUS_IN_SUSPEND, &priv->status) << |
5499 | STATUS_IN_SUSPEND; | |
5500 | goto exit; | |
5501 | } | |
5502 | ||
5503 | /* ...otherwise clear out all the status bits but the RF Kill and | |
5504 | * SUSPEND bits and continue taking the NIC down. */ | |
5505 | priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) << | |
5506 | STATUS_RF_KILL_HW | | |
5507 | test_bit(STATUS_RF_KILL_SW, &priv->status) << | |
5508 | STATUS_RF_KILL_SW | | |
9788864e RC |
5509 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
5510 | STATUS_GEO_CONFIGURED | | |
b481de9c ZY |
5511 | test_bit(STATUS_IN_SUSPEND, &priv->status) << |
5512 | STATUS_IN_SUSPEND | | |
5513 | test_bit(STATUS_FW_ERROR, &priv->status) << | |
5514 | STATUS_FW_ERROR; | |
5515 | ||
5516 | spin_lock_irqsave(&priv->lock, flags); | |
3395f6e9 | 5517 | iwl_clear_bit(priv, CSR_GP_CNTRL, |
9fbab516 | 5518 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
b481de9c ZY |
5519 | spin_unlock_irqrestore(&priv->lock, flags); |
5520 | ||
bb8c093b CH |
5521 | iwl4965_hw_txq_ctx_stop(priv); |
5522 | iwl4965_hw_rxq_stop(priv); | |
b481de9c ZY |
5523 | |
5524 | spin_lock_irqsave(&priv->lock, flags); | |
3395f6e9 TW |
5525 | if (!iwl_grab_nic_access(priv)) { |
5526 | iwl_write_prph(priv, APMG_CLK_DIS_REG, | |
b481de9c | 5527 | APMG_CLK_VAL_DMA_CLK_RQT); |
3395f6e9 | 5528 | iwl_release_nic_access(priv); |
b481de9c ZY |
5529 | } |
5530 | spin_unlock_irqrestore(&priv->lock, flags); | |
5531 | ||
5532 | udelay(5); | |
5533 | ||
bb8c093b | 5534 | iwl4965_hw_nic_stop_master(priv); |
3395f6e9 | 5535 | iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); |
bb8c093b | 5536 | iwl4965_hw_nic_reset(priv); |
b481de9c ZY |
5537 | |
5538 | exit: | |
bb8c093b | 5539 | memset(&priv->card_alive, 0, sizeof(struct iwl4965_alive_resp)); |
b481de9c ZY |
5540 | |
5541 | if (priv->ibss_beacon) | |
5542 | dev_kfree_skb(priv->ibss_beacon); | |
5543 | priv->ibss_beacon = NULL; | |
5544 | ||
5545 | /* clear out any free frames */ | |
bb8c093b | 5546 | iwl4965_clear_free_frames(priv); |
b481de9c ZY |
5547 | } |
5548 | ||
c79dd5b5 | 5549 | static void iwl4965_down(struct iwl_priv *priv) |
b481de9c ZY |
5550 | { |
5551 | mutex_lock(&priv->mutex); | |
bb8c093b | 5552 | __iwl4965_down(priv); |
b481de9c | 5553 | mutex_unlock(&priv->mutex); |
b24d22b1 | 5554 | |
bb8c093b | 5555 | iwl4965_cancel_deferred_work(priv); |
b481de9c ZY |
5556 | } |
5557 | ||
5558 | #define MAX_HW_RESTARTS 5 | |
5559 | ||
c79dd5b5 | 5560 | static int __iwl4965_up(struct iwl_priv *priv) |
b481de9c | 5561 | { |
57aab75a TW |
5562 | int i; |
5563 | int ret; | |
b481de9c ZY |
5564 | |
5565 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
5566 | IWL_WARNING("Exit pending; will not bring the NIC up\n"); | |
5567 | return -EIO; | |
5568 | } | |
5569 | ||
5570 | if (test_bit(STATUS_RF_KILL_SW, &priv->status)) { | |
5571 | IWL_WARNING("Radio disabled by SW RF kill (module " | |
5572 | "parameter)\n"); | |
ad97edd2 | 5573 | iwl_rfkill_set_hw_state(priv); |
e655b9f0 ZY |
5574 | return -ENODEV; |
5575 | } | |
5576 | ||
e903fbd4 RC |
5577 | if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) { |
5578 | IWL_ERROR("ucode not available for device bringup\n"); | |
5579 | return -EIO; | |
5580 | } | |
5581 | ||
e655b9f0 | 5582 | /* If platform's RF_KILL switch is NOT set to KILL */ |
3395f6e9 | 5583 | if (iwl_read32(priv, CSR_GP_CNTRL) & |
e655b9f0 ZY |
5584 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
5585 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
5586 | else { | |
5587 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
5588 | if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) { | |
ad97edd2 | 5589 | iwl_rfkill_set_hw_state(priv); |
e655b9f0 ZY |
5590 | IWL_WARNING("Radio disabled by HW RF Kill switch\n"); |
5591 | return -ENODEV; | |
5592 | } | |
b481de9c ZY |
5593 | } |
5594 | ||
ad97edd2 | 5595 | iwl_rfkill_set_hw_state(priv); |
3395f6e9 | 5596 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
b481de9c | 5597 | |
57aab75a TW |
5598 | ret = priv->cfg->ops->lib->hw_nic_init(priv); |
5599 | if (ret) { | |
5600 | IWL_ERROR("Unable to init nic\n"); | |
5601 | return ret; | |
b481de9c ZY |
5602 | } |
5603 | ||
5604 | /* make sure rfkill handshake bits are cleared */ | |
3395f6e9 TW |
5605 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
5606 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
b481de9c ZY |
5607 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
5608 | ||
5609 | /* clear (again), then enable host interrupts */ | |
3395f6e9 | 5610 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
bb8c093b | 5611 | iwl4965_enable_interrupts(priv); |
b481de9c ZY |
5612 | |
5613 | /* really make sure rfkill handshake bits are cleared */ | |
3395f6e9 TW |
5614 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
5615 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
b481de9c ZY |
5616 | |
5617 | /* Copy original ucode data image from disk into backup cache. | |
5618 | * This will be used to initialize the on-board processor's | |
5619 | * data SRAM for a clean start when the runtime program first loads. */ | |
5620 | memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr, | |
5a66926a | 5621 | priv->ucode_data.len); |
b481de9c | 5622 | |
e655b9f0 ZY |
5623 | /* We return success when we resume from suspend and rf_kill is on. */ |
5624 | if (test_bit(STATUS_RF_KILL_HW, &priv->status)) | |
b481de9c | 5625 | return 0; |
b481de9c ZY |
5626 | |
5627 | for (i = 0; i < MAX_HW_RESTARTS; i++) { | |
5628 | ||
bf85ea4f | 5629 | iwlcore_clear_stations_table(priv); |
b481de9c ZY |
5630 | |
5631 | /* load bootstrap state machine, | |
5632 | * load bootstrap program into processor's memory, | |
5633 | * prepare to load the "initialize" uCode */ | |
57aab75a | 5634 | ret = priv->cfg->ops->lib->load_ucode(priv); |
b481de9c | 5635 | |
57aab75a TW |
5636 | if (ret) { |
5637 | IWL_ERROR("Unable to set up bootstrap uCode: %d\n", ret); | |
b481de9c ZY |
5638 | continue; |
5639 | } | |
5640 | ||
5641 | /* start card; "initialize" will load runtime ucode */ | |
bb8c093b | 5642 | iwl4965_nic_start(priv); |
b481de9c | 5643 | |
b481de9c ZY |
5644 | IWL_DEBUG_INFO(DRV_NAME " is coming up\n"); |
5645 | ||
5646 | return 0; | |
5647 | } | |
5648 | ||
5649 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
bb8c093b | 5650 | __iwl4965_down(priv); |
b481de9c ZY |
5651 | |
5652 | /* tried to restart and config the device for as long as our | |
5653 | * patience could withstand */ | |
5654 | IWL_ERROR("Unable to initialize device after %d attempts.\n", i); | |
5655 | return -EIO; | |
5656 | } | |
5657 | ||
5658 | ||
5659 | /***************************************************************************** | |
5660 | * | |
5661 | * Workqueue callbacks | |
5662 | * | |
5663 | *****************************************************************************/ | |
5664 | ||
bb8c093b | 5665 | static void iwl4965_bg_init_alive_start(struct work_struct *data) |
b481de9c | 5666 | { |
c79dd5b5 TW |
5667 | struct iwl_priv *priv = |
5668 | container_of(data, struct iwl_priv, init_alive_start.work); | |
b481de9c ZY |
5669 | |
5670 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5671 | return; | |
5672 | ||
5673 | mutex_lock(&priv->mutex); | |
bb8c093b | 5674 | iwl4965_init_alive_start(priv); |
b481de9c ZY |
5675 | mutex_unlock(&priv->mutex); |
5676 | } | |
5677 | ||
bb8c093b | 5678 | static void iwl4965_bg_alive_start(struct work_struct *data) |
b481de9c | 5679 | { |
c79dd5b5 TW |
5680 | struct iwl_priv *priv = |
5681 | container_of(data, struct iwl_priv, alive_start.work); | |
b481de9c ZY |
5682 | |
5683 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5684 | return; | |
5685 | ||
5686 | mutex_lock(&priv->mutex); | |
bb8c093b | 5687 | iwl4965_alive_start(priv); |
b481de9c ZY |
5688 | mutex_unlock(&priv->mutex); |
5689 | } | |
5690 | ||
bb8c093b | 5691 | static void iwl4965_bg_rf_kill(struct work_struct *work) |
b481de9c | 5692 | { |
c79dd5b5 | 5693 | struct iwl_priv *priv = container_of(work, struct iwl_priv, rf_kill); |
b481de9c ZY |
5694 | |
5695 | wake_up_interruptible(&priv->wait_command_queue); | |
5696 | ||
5697 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5698 | return; | |
5699 | ||
5700 | mutex_lock(&priv->mutex); | |
5701 | ||
fee1247a | 5702 | if (!iwl_is_rfkill(priv)) { |
b481de9c ZY |
5703 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL, |
5704 | "HW and/or SW RF Kill no longer active, restarting " | |
5705 | "device\n"); | |
5706 | if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5707 | queue_work(priv->workqueue, &priv->restart); | |
5708 | } else { | |
ad97edd2 MA |
5709 | /* make sure mac80211 stop sending Tx frame */ |
5710 | if (priv->mac80211_registered) | |
5711 | ieee80211_stop_queues(priv->hw); | |
b481de9c ZY |
5712 | |
5713 | if (!test_bit(STATUS_RF_KILL_HW, &priv->status)) | |
5714 | IWL_DEBUG_RF_KILL("Can not turn radio back on - " | |
5715 | "disabled by SW switch\n"); | |
5716 | else | |
5717 | IWL_WARNING("Radio Frequency Kill Switch is On:\n" | |
5718 | "Kill switch must be turned off for " | |
5719 | "wireless networking to work.\n"); | |
5720 | } | |
ad97edd2 MA |
5721 | iwl_rfkill_set_hw_state(priv); |
5722 | ||
b481de9c ZY |
5723 | mutex_unlock(&priv->mutex); |
5724 | } | |
5725 | ||
5726 | #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ) | |
5727 | ||
bb8c093b | 5728 | static void iwl4965_bg_scan_check(struct work_struct *data) |
b481de9c | 5729 | { |
c79dd5b5 TW |
5730 | struct iwl_priv *priv = |
5731 | container_of(data, struct iwl_priv, scan_check.work); | |
b481de9c ZY |
5732 | |
5733 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5734 | return; | |
5735 | ||
5736 | mutex_lock(&priv->mutex); | |
5737 | if (test_bit(STATUS_SCANNING, &priv->status) || | |
5738 | test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
5739 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, | |
5740 | "Scan completion watchdog resetting adapter (%dms)\n", | |
5741 | jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG)); | |
052c4b9f | 5742 | |
b481de9c | 5743 | if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) |
bb8c093b | 5744 | iwl4965_send_scan_abort(priv); |
b481de9c ZY |
5745 | } |
5746 | mutex_unlock(&priv->mutex); | |
5747 | } | |
5748 | ||
bb8c093b | 5749 | static void iwl4965_bg_request_scan(struct work_struct *data) |
b481de9c | 5750 | { |
c79dd5b5 TW |
5751 | struct iwl_priv *priv = |
5752 | container_of(data, struct iwl_priv, request_scan); | |
857485c0 | 5753 | struct iwl_host_cmd cmd = { |
b481de9c | 5754 | .id = REPLY_SCAN_CMD, |
bb8c093b | 5755 | .len = sizeof(struct iwl4965_scan_cmd), |
b481de9c ZY |
5756 | .meta.flags = CMD_SIZE_HUGE, |
5757 | }; | |
bb8c093b | 5758 | struct iwl4965_scan_cmd *scan; |
b481de9c | 5759 | struct ieee80211_conf *conf = NULL; |
78330fdd | 5760 | u16 cmd_len; |
8318d78a | 5761 | enum ieee80211_band band; |
78330fdd | 5762 | u8 direct_mask; |
857485c0 | 5763 | int ret = 0; |
b481de9c ZY |
5764 | |
5765 | conf = ieee80211_get_hw_conf(priv->hw); | |
5766 | ||
5767 | mutex_lock(&priv->mutex); | |
5768 | ||
fee1247a | 5769 | if (!iwl_is_ready(priv)) { |
b481de9c ZY |
5770 | IWL_WARNING("request scan called when driver not ready.\n"); |
5771 | goto done; | |
5772 | } | |
5773 | ||
5774 | /* Make sure the scan wasn't cancelled before this queued work | |
5775 | * was given the chance to run... */ | |
5776 | if (!test_bit(STATUS_SCANNING, &priv->status)) | |
5777 | goto done; | |
5778 | ||
5779 | /* This should never be called or scheduled if there is currently | |
5780 | * a scan active in the hardware. */ | |
5781 | if (test_bit(STATUS_SCAN_HW, &priv->status)) { | |
5782 | IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. " | |
5783 | "Ignoring second request.\n"); | |
857485c0 | 5784 | ret = -EIO; |
b481de9c ZY |
5785 | goto done; |
5786 | } | |
5787 | ||
5788 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
5789 | IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n"); | |
5790 | goto done; | |
5791 | } | |
5792 | ||
5793 | if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
5794 | IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n"); | |
5795 | goto done; | |
5796 | } | |
5797 | ||
fee1247a | 5798 | if (iwl_is_rfkill(priv)) { |
b481de9c ZY |
5799 | IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n"); |
5800 | goto done; | |
5801 | } | |
5802 | ||
5803 | if (!test_bit(STATUS_READY, &priv->status)) { | |
5804 | IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n"); | |
5805 | goto done; | |
5806 | } | |
5807 | ||
5808 | if (!priv->scan_bands) { | |
5809 | IWL_DEBUG_HC("Aborting scan due to no requested bands\n"); | |
5810 | goto done; | |
5811 | } | |
5812 | ||
5813 | if (!priv->scan) { | |
bb8c093b | 5814 | priv->scan = kmalloc(sizeof(struct iwl4965_scan_cmd) + |
b481de9c ZY |
5815 | IWL_MAX_SCAN_SIZE, GFP_KERNEL); |
5816 | if (!priv->scan) { | |
857485c0 | 5817 | ret = -ENOMEM; |
b481de9c ZY |
5818 | goto done; |
5819 | } | |
5820 | } | |
5821 | scan = priv->scan; | |
bb8c093b | 5822 | memset(scan, 0, sizeof(struct iwl4965_scan_cmd) + IWL_MAX_SCAN_SIZE); |
b481de9c ZY |
5823 | |
5824 | scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH; | |
5825 | scan->quiet_time = IWL_ACTIVE_QUIET_TIME; | |
5826 | ||
3109ece1 | 5827 | if (iwl_is_associated(priv)) { |
b481de9c ZY |
5828 | u16 interval = 0; |
5829 | u32 extra; | |
5830 | u32 suspend_time = 100; | |
5831 | u32 scan_suspend_time = 100; | |
5832 | unsigned long flags; | |
5833 | ||
5834 | IWL_DEBUG_INFO("Scanning while associated...\n"); | |
5835 | ||
5836 | spin_lock_irqsave(&priv->lock, flags); | |
5837 | interval = priv->beacon_int; | |
5838 | spin_unlock_irqrestore(&priv->lock, flags); | |
5839 | ||
5840 | scan->suspend_time = 0; | |
052c4b9f | 5841 | scan->max_out_time = cpu_to_le32(200 * 1024); |
b481de9c ZY |
5842 | if (!interval) |
5843 | interval = suspend_time; | |
5844 | ||
5845 | extra = (suspend_time / interval) << 22; | |
5846 | scan_suspend_time = (extra | | |
5847 | ((suspend_time % interval) * 1024)); | |
5848 | scan->suspend_time = cpu_to_le32(scan_suspend_time); | |
5849 | IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n", | |
5850 | scan_suspend_time, interval); | |
5851 | } | |
5852 | ||
5853 | /* We should add the ability for user to lock to PASSIVE ONLY */ | |
5854 | if (priv->one_direct_scan) { | |
5855 | IWL_DEBUG_SCAN | |
5856 | ("Kicking off one direct scan for '%s'\n", | |
bb8c093b | 5857 | iwl4965_escape_essid(priv->direct_ssid, |
b481de9c ZY |
5858 | priv->direct_ssid_len)); |
5859 | scan->direct_scan[0].id = WLAN_EID_SSID; | |
5860 | scan->direct_scan[0].len = priv->direct_ssid_len; | |
5861 | memcpy(scan->direct_scan[0].ssid, | |
5862 | priv->direct_ssid, priv->direct_ssid_len); | |
5863 | direct_mask = 1; | |
3109ece1 | 5864 | } else if (!iwl_is_associated(priv) && priv->essid_len) { |
b481de9c ZY |
5865 | scan->direct_scan[0].id = WLAN_EID_SSID; |
5866 | scan->direct_scan[0].len = priv->essid_len; | |
5867 | memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len); | |
5868 | direct_mask = 1; | |
857485c0 | 5869 | } else { |
b481de9c | 5870 | direct_mask = 0; |
857485c0 | 5871 | } |
b481de9c | 5872 | |
b481de9c ZY |
5873 | scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK; |
5874 | scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id; | |
5875 | scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
5876 | ||
b481de9c ZY |
5877 | |
5878 | switch (priv->scan_bands) { | |
5879 | case 2: | |
5880 | scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK; | |
5881 | scan->tx_cmd.rate_n_flags = | |
bb8c093b | 5882 | iwl4965_hw_set_rate_n_flags(IWL_RATE_1M_PLCP, |
b481de9c ZY |
5883 | RATE_MCS_ANT_B_MSK|RATE_MCS_CCK_MSK); |
5884 | ||
5885 | scan->good_CRC_th = 0; | |
8318d78a | 5886 | band = IEEE80211_BAND_2GHZ; |
b481de9c ZY |
5887 | break; |
5888 | ||
5889 | case 1: | |
5890 | scan->tx_cmd.rate_n_flags = | |
bb8c093b | 5891 | iwl4965_hw_set_rate_n_flags(IWL_RATE_6M_PLCP, |
b481de9c ZY |
5892 | RATE_MCS_ANT_B_MSK); |
5893 | scan->good_CRC_th = IWL_GOOD_CRC_TH; | |
8318d78a | 5894 | band = IEEE80211_BAND_5GHZ; |
b481de9c ZY |
5895 | break; |
5896 | ||
5897 | default: | |
5898 | IWL_WARNING("Invalid scan band count\n"); | |
5899 | goto done; | |
5900 | } | |
5901 | ||
78330fdd TW |
5902 | /* We don't build a direct scan probe request; the uCode will do |
5903 | * that based on the direct_mask added to each channel entry */ | |
5904 | cmd_len = iwl4965_fill_probe_req(priv, band, | |
5905 | (struct ieee80211_mgmt *)scan->data, | |
5906 | IWL_MAX_SCAN_SIZE - sizeof(*scan), 0); | |
5907 | ||
5908 | scan->tx_cmd.len = cpu_to_le16(cmd_len); | |
b481de9c ZY |
5909 | /* select Rx chains */ |
5910 | ||
5911 | /* Force use of chains B and C (0x6) for scan Rx. | |
5912 | * Avoid A (0x1) because of its off-channel reception on A-band. | |
5913 | * MIMO is not used here, but value is required to make uCode happy. */ | |
5914 | scan->rx_chain = RXON_RX_CHAIN_DRIVER_FORCE_MSK | | |
5915 | cpu_to_le16((0x7 << RXON_RX_CHAIN_VALID_POS) | | |
5916 | (0x6 << RXON_RX_CHAIN_FORCE_SEL_POS) | | |
5917 | (0x7 << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS)); | |
5918 | ||
5919 | if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) | |
5920 | scan->filter_flags = RXON_FILTER_PROMISC_MSK; | |
5921 | ||
26c0f03f | 5922 | if (direct_mask) { |
b481de9c ZY |
5923 | IWL_DEBUG_SCAN |
5924 | ("Initiating direct scan for %s.\n", | |
bb8c093b | 5925 | iwl4965_escape_essid(priv->essid, priv->essid_len)); |
26c0f03f RC |
5926 | scan->channel_count = |
5927 | iwl4965_get_channels_for_scan( | |
5928 | priv, band, 1, /* active */ | |
5929 | direct_mask, | |
5930 | (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]); | |
5931 | } else { | |
b481de9c | 5932 | IWL_DEBUG_SCAN("Initiating indirect scan.\n"); |
26c0f03f RC |
5933 | scan->channel_count = |
5934 | iwl4965_get_channels_for_scan( | |
5935 | priv, band, 0, /* passive */ | |
5936 | direct_mask, | |
5937 | (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]); | |
5938 | } | |
b481de9c ZY |
5939 | |
5940 | cmd.len += le16_to_cpu(scan->tx_cmd.len) + | |
bb8c093b | 5941 | scan->channel_count * sizeof(struct iwl4965_scan_channel); |
b481de9c ZY |
5942 | cmd.data = scan; |
5943 | scan->len = cpu_to_le16(cmd.len); | |
5944 | ||
5945 | set_bit(STATUS_SCAN_HW, &priv->status); | |
857485c0 TW |
5946 | ret = iwl_send_cmd_sync(priv, &cmd); |
5947 | if (ret) | |
b481de9c ZY |
5948 | goto done; |
5949 | ||
5950 | queue_delayed_work(priv->workqueue, &priv->scan_check, | |
5951 | IWL_SCAN_CHECK_WATCHDOG); | |
5952 | ||
5953 | mutex_unlock(&priv->mutex); | |
5954 | return; | |
5955 | ||
5956 | done: | |
01ebd063 | 5957 | /* inform mac80211 scan aborted */ |
b481de9c ZY |
5958 | queue_work(priv->workqueue, &priv->scan_completed); |
5959 | mutex_unlock(&priv->mutex); | |
5960 | } | |
5961 | ||
bb8c093b | 5962 | static void iwl4965_bg_up(struct work_struct *data) |
b481de9c | 5963 | { |
c79dd5b5 | 5964 | struct iwl_priv *priv = container_of(data, struct iwl_priv, up); |
b481de9c ZY |
5965 | |
5966 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5967 | return; | |
5968 | ||
5969 | mutex_lock(&priv->mutex); | |
bb8c093b | 5970 | __iwl4965_up(priv); |
b481de9c ZY |
5971 | mutex_unlock(&priv->mutex); |
5972 | } | |
5973 | ||
bb8c093b | 5974 | static void iwl4965_bg_restart(struct work_struct *data) |
b481de9c | 5975 | { |
c79dd5b5 | 5976 | struct iwl_priv *priv = container_of(data, struct iwl_priv, restart); |
b481de9c ZY |
5977 | |
5978 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5979 | return; | |
5980 | ||
bb8c093b | 5981 | iwl4965_down(priv); |
b481de9c ZY |
5982 | queue_work(priv->workqueue, &priv->up); |
5983 | } | |
5984 | ||
bb8c093b | 5985 | static void iwl4965_bg_rx_replenish(struct work_struct *data) |
b481de9c | 5986 | { |
c79dd5b5 TW |
5987 | struct iwl_priv *priv = |
5988 | container_of(data, struct iwl_priv, rx_replenish); | |
b481de9c ZY |
5989 | |
5990 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5991 | return; | |
5992 | ||
5993 | mutex_lock(&priv->mutex); | |
bb8c093b | 5994 | iwl4965_rx_replenish(priv); |
b481de9c ZY |
5995 | mutex_unlock(&priv->mutex); |
5996 | } | |
5997 | ||
7878a5a4 MA |
5998 | #define IWL_DELAY_NEXT_SCAN (HZ*2) |
5999 | ||
508e32e1 | 6000 | static void iwl4965_post_associate(struct iwl_priv *priv) |
b481de9c | 6001 | { |
b481de9c | 6002 | struct ieee80211_conf *conf = NULL; |
857485c0 | 6003 | int ret = 0; |
0795af57 | 6004 | DECLARE_MAC_BUF(mac); |
b481de9c ZY |
6005 | |
6006 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { | |
6007 | IWL_ERROR("%s Should not be called in AP mode\n", __FUNCTION__); | |
6008 | return; | |
6009 | } | |
6010 | ||
0795af57 JP |
6011 | IWL_DEBUG_ASSOC("Associated as %d to: %s\n", |
6012 | priv->assoc_id, | |
6013 | print_mac(mac, priv->active_rxon.bssid_addr)); | |
b481de9c ZY |
6014 | |
6015 | ||
6016 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6017 | return; | |
6018 | ||
b481de9c | 6019 | |
508e32e1 | 6020 | if (!priv->vif || !priv->is_open) |
948c171c | 6021 | return; |
508e32e1 | 6022 | |
bb8c093b | 6023 | iwl4965_scan_cancel_timeout(priv, 200); |
052c4b9f | 6024 | |
b481de9c ZY |
6025 | conf = ieee80211_get_hw_conf(priv->hw); |
6026 | ||
6027 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
bb8c093b | 6028 | iwl4965_commit_rxon(priv); |
b481de9c | 6029 | |
bb8c093b CH |
6030 | memset(&priv->rxon_timing, 0, sizeof(struct iwl4965_rxon_time_cmd)); |
6031 | iwl4965_setup_rxon_timing(priv); | |
857485c0 | 6032 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
b481de9c | 6033 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
857485c0 | 6034 | if (ret) |
b481de9c ZY |
6035 | IWL_WARNING("REPLY_RXON_TIMING failed - " |
6036 | "Attempting to continue.\n"); | |
6037 | ||
6038 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
6039 | ||
c8b0e6e1 | 6040 | #ifdef CONFIG_IWL4965_HT |
fd105e79 RR |
6041 | if (priv->current_ht_config.is_ht) |
6042 | iwl4965_set_rxon_ht(priv, &priv->current_ht_config); | |
c8b0e6e1 | 6043 | #endif /* CONFIG_IWL4965_HT*/ |
b481de9c ZY |
6044 | iwl4965_set_rxon_chain(priv); |
6045 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); | |
6046 | ||
6047 | IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n", | |
6048 | priv->assoc_id, priv->beacon_int); | |
6049 | ||
6050 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) | |
6051 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; | |
6052 | else | |
6053 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
6054 | ||
6055 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { | |
6056 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
6057 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; | |
6058 | else | |
6059 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
6060 | ||
6061 | if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) | |
6062 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
6063 | ||
6064 | } | |
6065 | ||
bb8c093b | 6066 | iwl4965_commit_rxon(priv); |
b481de9c ZY |
6067 | |
6068 | switch (priv->iw_mode) { | |
6069 | case IEEE80211_IF_TYPE_STA: | |
bb8c093b | 6070 | iwl4965_rate_scale_init(priv->hw, IWL_AP_ID); |
b481de9c ZY |
6071 | break; |
6072 | ||
6073 | case IEEE80211_IF_TYPE_IBSS: | |
6074 | ||
6075 | /* clear out the station table */ | |
bf85ea4f | 6076 | iwlcore_clear_stations_table(priv); |
b481de9c | 6077 | |
bb8c093b CH |
6078 | iwl4965_rxon_add_station(priv, iwl4965_broadcast_addr, 0); |
6079 | iwl4965_rxon_add_station(priv, priv->bssid, 0); | |
6080 | iwl4965_rate_scale_init(priv->hw, IWL_STA_ID); | |
6081 | iwl4965_send_beacon_cmd(priv); | |
b481de9c ZY |
6082 | |
6083 | break; | |
6084 | ||
6085 | default: | |
6086 | IWL_ERROR("%s Should not be called in %d mode\n", | |
6087 | __FUNCTION__, priv->iw_mode); | |
6088 | break; | |
6089 | } | |
6090 | ||
bb8c093b | 6091 | iwl4965_sequence_reset(priv); |
b481de9c | 6092 | |
c8b0e6e1 | 6093 | #ifdef CONFIG_IWL4965_SENSITIVITY |
b481de9c ZY |
6094 | /* Enable Rx differential gain and sensitivity calibrations */ |
6095 | iwl4965_chain_noise_reset(priv); | |
6096 | priv->start_calib = 1; | |
c8b0e6e1 | 6097 | #endif /* CONFIG_IWL4965_SENSITIVITY */ |
b481de9c ZY |
6098 | |
6099 | if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) | |
6100 | priv->assoc_station_added = 1; | |
6101 | ||
bb8c093b | 6102 | iwl4965_activate_qos(priv, 0); |
292ae174 | 6103 | |
7878a5a4 MA |
6104 | /* we have just associated, don't start scan too early */ |
6105 | priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN; | |
508e32e1 RC |
6106 | } |
6107 | ||
6108 | ||
6109 | static void iwl4965_bg_post_associate(struct work_struct *data) | |
6110 | { | |
6111 | struct iwl_priv *priv = container_of(data, struct iwl_priv, | |
6112 | post_associate.work); | |
6113 | ||
6114 | mutex_lock(&priv->mutex); | |
6115 | iwl4965_post_associate(priv); | |
b481de9c | 6116 | mutex_unlock(&priv->mutex); |
508e32e1 | 6117 | |
b481de9c ZY |
6118 | } |
6119 | ||
bb8c093b | 6120 | static void iwl4965_bg_abort_scan(struct work_struct *work) |
b481de9c | 6121 | { |
c79dd5b5 | 6122 | struct iwl_priv *priv = container_of(work, struct iwl_priv, abort_scan); |
b481de9c | 6123 | |
fee1247a | 6124 | if (!iwl_is_ready(priv)) |
b481de9c ZY |
6125 | return; |
6126 | ||
6127 | mutex_lock(&priv->mutex); | |
6128 | ||
6129 | set_bit(STATUS_SCAN_ABORTING, &priv->status); | |
bb8c093b | 6130 | iwl4965_send_scan_abort(priv); |
b481de9c ZY |
6131 | |
6132 | mutex_unlock(&priv->mutex); | |
6133 | } | |
6134 | ||
76bb77e0 ZY |
6135 | static int iwl4965_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf); |
6136 | ||
bb8c093b | 6137 | static void iwl4965_bg_scan_completed(struct work_struct *work) |
b481de9c | 6138 | { |
c79dd5b5 TW |
6139 | struct iwl_priv *priv = |
6140 | container_of(work, struct iwl_priv, scan_completed); | |
b481de9c ZY |
6141 | |
6142 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n"); | |
6143 | ||
6144 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6145 | return; | |
6146 | ||
a0646470 ZY |
6147 | if (test_bit(STATUS_CONF_PENDING, &priv->status)) |
6148 | iwl4965_mac_config(priv->hw, ieee80211_get_hw_conf(priv->hw)); | |
76bb77e0 | 6149 | |
b481de9c ZY |
6150 | ieee80211_scan_completed(priv->hw); |
6151 | ||
6152 | /* Since setting the TXPOWER may have been deferred while | |
6153 | * performing the scan, fire one off */ | |
6154 | mutex_lock(&priv->mutex); | |
bb8c093b | 6155 | iwl4965_hw_reg_send_txpower(priv); |
b481de9c ZY |
6156 | mutex_unlock(&priv->mutex); |
6157 | } | |
6158 | ||
6159 | /***************************************************************************** | |
6160 | * | |
6161 | * mac80211 entry point functions | |
6162 | * | |
6163 | *****************************************************************************/ | |
6164 | ||
5a66926a ZY |
6165 | #define UCODE_READY_TIMEOUT (2 * HZ) |
6166 | ||
bb8c093b | 6167 | static int iwl4965_mac_start(struct ieee80211_hw *hw) |
b481de9c | 6168 | { |
c79dd5b5 | 6169 | struct iwl_priv *priv = hw->priv; |
5a66926a | 6170 | int ret; |
b481de9c ZY |
6171 | |
6172 | IWL_DEBUG_MAC80211("enter\n"); | |
6173 | ||
5a66926a ZY |
6174 | if (pci_enable_device(priv->pci_dev)) { |
6175 | IWL_ERROR("Fail to pci_enable_device\n"); | |
6176 | return -ENODEV; | |
6177 | } | |
6178 | pci_restore_state(priv->pci_dev); | |
6179 | pci_enable_msi(priv->pci_dev); | |
6180 | ||
6181 | ret = request_irq(priv->pci_dev->irq, iwl4965_isr, IRQF_SHARED, | |
6182 | DRV_NAME, priv); | |
6183 | if (ret) { | |
6184 | IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq); | |
6185 | goto out_disable_msi; | |
6186 | } | |
6187 | ||
b481de9c ZY |
6188 | /* we should be verifying the device is ready to be opened */ |
6189 | mutex_lock(&priv->mutex); | |
6190 | ||
5a66926a ZY |
6191 | memset(&priv->staging_rxon, 0, sizeof(struct iwl4965_rxon_cmd)); |
6192 | /* fetch ucode file from disk, alloc and copy to bus-master buffers ... | |
6193 | * ucode filename and max sizes are card-specific. */ | |
b481de9c | 6194 | |
5a66926a ZY |
6195 | if (!priv->ucode_code.len) { |
6196 | ret = iwl4965_read_ucode(priv); | |
6197 | if (ret) { | |
6198 | IWL_ERROR("Could not read microcode: %d\n", ret); | |
6199 | mutex_unlock(&priv->mutex); | |
6200 | goto out_release_irq; | |
6201 | } | |
6202 | } | |
b481de9c | 6203 | |
e655b9f0 | 6204 | ret = __iwl4965_up(priv); |
5a66926a | 6205 | |
b481de9c | 6206 | mutex_unlock(&priv->mutex); |
5a66926a | 6207 | |
e655b9f0 ZY |
6208 | if (ret) |
6209 | goto out_release_irq; | |
6210 | ||
6211 | IWL_DEBUG_INFO("Start UP work done.\n"); | |
6212 | ||
6213 | if (test_bit(STATUS_IN_SUSPEND, &priv->status)) | |
6214 | return 0; | |
6215 | ||
5a66926a ZY |
6216 | /* Wait for START_ALIVE from ucode. Otherwise callbacks from |
6217 | * mac80211 will not be run successfully. */ | |
6218 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, | |
6219 | test_bit(STATUS_READY, &priv->status), | |
6220 | UCODE_READY_TIMEOUT); | |
6221 | if (!ret) { | |
6222 | if (!test_bit(STATUS_READY, &priv->status)) { | |
6223 | IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n", | |
6224 | jiffies_to_msecs(UCODE_READY_TIMEOUT)); | |
6225 | ret = -ETIMEDOUT; | |
6226 | goto out_release_irq; | |
6227 | } | |
6228 | } | |
6229 | ||
e655b9f0 | 6230 | priv->is_open = 1; |
b481de9c ZY |
6231 | IWL_DEBUG_MAC80211("leave\n"); |
6232 | return 0; | |
5a66926a ZY |
6233 | |
6234 | out_release_irq: | |
6235 | free_irq(priv->pci_dev->irq, priv); | |
6236 | out_disable_msi: | |
6237 | pci_disable_msi(priv->pci_dev); | |
e655b9f0 ZY |
6238 | pci_disable_device(priv->pci_dev); |
6239 | priv->is_open = 0; | |
6240 | IWL_DEBUG_MAC80211("leave - failed\n"); | |
5a66926a | 6241 | return ret; |
b481de9c ZY |
6242 | } |
6243 | ||
bb8c093b | 6244 | static void iwl4965_mac_stop(struct ieee80211_hw *hw) |
b481de9c | 6245 | { |
c79dd5b5 | 6246 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
6247 | |
6248 | IWL_DEBUG_MAC80211("enter\n"); | |
948c171c | 6249 | |
e655b9f0 ZY |
6250 | if (!priv->is_open) { |
6251 | IWL_DEBUG_MAC80211("leave - skip\n"); | |
6252 | return; | |
6253 | } | |
6254 | ||
b481de9c | 6255 | priv->is_open = 0; |
5a66926a | 6256 | |
fee1247a | 6257 | if (iwl_is_ready_rf(priv)) { |
e655b9f0 ZY |
6258 | /* stop mac, cancel any scan request and clear |
6259 | * RXON_FILTER_ASSOC_MSK BIT | |
6260 | */ | |
5a66926a ZY |
6261 | mutex_lock(&priv->mutex); |
6262 | iwl4965_scan_cancel_timeout(priv, 100); | |
6263 | cancel_delayed_work(&priv->post_associate); | |
fde3571f | 6264 | mutex_unlock(&priv->mutex); |
fde3571f MA |
6265 | } |
6266 | ||
5a66926a ZY |
6267 | iwl4965_down(priv); |
6268 | ||
6269 | flush_workqueue(priv->workqueue); | |
6270 | free_irq(priv->pci_dev->irq, priv); | |
6271 | pci_disable_msi(priv->pci_dev); | |
6272 | pci_save_state(priv->pci_dev); | |
6273 | pci_disable_device(priv->pci_dev); | |
948c171c | 6274 | |
b481de9c | 6275 | IWL_DEBUG_MAC80211("leave\n"); |
b481de9c ZY |
6276 | } |
6277 | ||
bb8c093b | 6278 | static int iwl4965_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb, |
b481de9c ZY |
6279 | struct ieee80211_tx_control *ctl) |
6280 | { | |
c79dd5b5 | 6281 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
6282 | |
6283 | IWL_DEBUG_MAC80211("enter\n"); | |
6284 | ||
6285 | if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) { | |
6286 | IWL_DEBUG_MAC80211("leave - monitor\n"); | |
6287 | return -1; | |
6288 | } | |
6289 | ||
6290 | IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, | |
8318d78a | 6291 | ctl->tx_rate->bitrate); |
b481de9c | 6292 | |
bb8c093b | 6293 | if (iwl4965_tx_skb(priv, skb, ctl)) |
b481de9c ZY |
6294 | dev_kfree_skb_any(skb); |
6295 | ||
6296 | IWL_DEBUG_MAC80211("leave\n"); | |
6297 | return 0; | |
6298 | } | |
6299 | ||
bb8c093b | 6300 | static int iwl4965_mac_add_interface(struct ieee80211_hw *hw, |
b481de9c ZY |
6301 | struct ieee80211_if_init_conf *conf) |
6302 | { | |
c79dd5b5 | 6303 | struct iwl_priv *priv = hw->priv; |
b481de9c | 6304 | unsigned long flags; |
0795af57 | 6305 | DECLARE_MAC_BUF(mac); |
b481de9c | 6306 | |
32bfd35d | 6307 | IWL_DEBUG_MAC80211("enter: type %d\n", conf->type); |
b481de9c | 6308 | |
32bfd35d JB |
6309 | if (priv->vif) { |
6310 | IWL_DEBUG_MAC80211("leave - vif != NULL\n"); | |
75849d28 | 6311 | return -EOPNOTSUPP; |
b481de9c ZY |
6312 | } |
6313 | ||
6314 | spin_lock_irqsave(&priv->lock, flags); | |
32bfd35d | 6315 | priv->vif = conf->vif; |
b481de9c ZY |
6316 | |
6317 | spin_unlock_irqrestore(&priv->lock, flags); | |
6318 | ||
6319 | mutex_lock(&priv->mutex); | |
864792e3 TW |
6320 | |
6321 | if (conf->mac_addr) { | |
6322 | IWL_DEBUG_MAC80211("Set %s\n", print_mac(mac, conf->mac_addr)); | |
6323 | memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN); | |
6324 | } | |
b481de9c | 6325 | |
fee1247a | 6326 | if (iwl_is_ready(priv)) |
5a66926a ZY |
6327 | iwl4965_set_mode(priv, conf->type); |
6328 | ||
b481de9c ZY |
6329 | mutex_unlock(&priv->mutex); |
6330 | ||
5a66926a | 6331 | IWL_DEBUG_MAC80211("leave\n"); |
b481de9c ZY |
6332 | return 0; |
6333 | } | |
6334 | ||
6335 | /** | |
bb8c093b | 6336 | * iwl4965_mac_config - mac80211 config callback |
b481de9c ZY |
6337 | * |
6338 | * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to | |
6339 | * be set inappropriately and the driver currently sets the hardware up to | |
6340 | * use it whenever needed. | |
6341 | */ | |
bb8c093b | 6342 | static int iwl4965_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf) |
b481de9c | 6343 | { |
c79dd5b5 | 6344 | struct iwl_priv *priv = hw->priv; |
bf85ea4f | 6345 | const struct iwl_channel_info *ch_info; |
b481de9c | 6346 | unsigned long flags; |
76bb77e0 | 6347 | int ret = 0; |
b481de9c ZY |
6348 | |
6349 | mutex_lock(&priv->mutex); | |
8318d78a | 6350 | IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value); |
b481de9c | 6351 | |
12342c47 ZY |
6352 | priv->add_radiotap = !!(conf->flags & IEEE80211_CONF_RADIOTAP); |
6353 | ||
fee1247a | 6354 | if (!iwl_is_ready(priv)) { |
b481de9c | 6355 | IWL_DEBUG_MAC80211("leave - not ready\n"); |
76bb77e0 ZY |
6356 | ret = -EIO; |
6357 | goto out; | |
b481de9c ZY |
6358 | } |
6359 | ||
1ea87396 | 6360 | if (unlikely(!priv->cfg->mod_params->disable_hw_scan && |
b481de9c | 6361 | test_bit(STATUS_SCANNING, &priv->status))) { |
a0646470 ZY |
6362 | IWL_DEBUG_MAC80211("leave - scanning\n"); |
6363 | set_bit(STATUS_CONF_PENDING, &priv->status); | |
b481de9c | 6364 | mutex_unlock(&priv->mutex); |
a0646470 | 6365 | return 0; |
b481de9c ZY |
6366 | } |
6367 | ||
6368 | spin_lock_irqsave(&priv->lock, flags); | |
6369 | ||
8622e705 | 6370 | ch_info = iwl_get_channel_info(priv, conf->channel->band, |
8318d78a | 6371 | ieee80211_frequency_to_channel(conf->channel->center_freq)); |
b481de9c | 6372 | if (!is_channel_valid(ch_info)) { |
b481de9c ZY |
6373 | IWL_DEBUG_MAC80211("leave - invalid channel\n"); |
6374 | spin_unlock_irqrestore(&priv->lock, flags); | |
76bb77e0 ZY |
6375 | ret = -EINVAL; |
6376 | goto out; | |
b481de9c ZY |
6377 | } |
6378 | ||
c8b0e6e1 | 6379 | #ifdef CONFIG_IWL4965_HT |
78330fdd | 6380 | /* if we are switching from ht to 2.4 clear flags |
b481de9c ZY |
6381 | * from any ht related info since 2.4 does not |
6382 | * support ht */ | |
78330fdd | 6383 | if ((le16_to_cpu(priv->staging_rxon.channel) != conf->channel->hw_value) |
b481de9c ZY |
6384 | #ifdef IEEE80211_CONF_CHANNEL_SWITCH |
6385 | && !(conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) | |
6386 | #endif | |
6387 | ) | |
6388 | priv->staging_rxon.flags = 0; | |
c8b0e6e1 | 6389 | #endif /* CONFIG_IWL4965_HT */ |
b481de9c | 6390 | |
bf85ea4f | 6391 | iwlcore_set_rxon_channel(priv, conf->channel->band, |
8318d78a | 6392 | ieee80211_frequency_to_channel(conf->channel->center_freq)); |
b481de9c | 6393 | |
8318d78a | 6394 | iwl4965_set_flags_for_phymode(priv, conf->channel->band); |
b481de9c ZY |
6395 | |
6396 | /* The list of supported rates and rate mask can be different | |
8318d78a | 6397 | * for each band; since the band may have changed, reset |
b481de9c | 6398 | * the rate mask to what mac80211 lists */ |
bb8c093b | 6399 | iwl4965_set_rate(priv); |
b481de9c ZY |
6400 | |
6401 | spin_unlock_irqrestore(&priv->lock, flags); | |
6402 | ||
6403 | #ifdef IEEE80211_CONF_CHANNEL_SWITCH | |
6404 | if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) { | |
bb8c093b | 6405 | iwl4965_hw_channel_switch(priv, conf->channel); |
76bb77e0 | 6406 | goto out; |
b481de9c ZY |
6407 | } |
6408 | #endif | |
6409 | ||
ad97edd2 MA |
6410 | if (priv->cfg->ops->lib->radio_kill_sw) |
6411 | priv->cfg->ops->lib->radio_kill_sw(priv, !conf->radio_enabled); | |
b481de9c ZY |
6412 | |
6413 | if (!conf->radio_enabled) { | |
6414 | IWL_DEBUG_MAC80211("leave - radio disabled\n"); | |
76bb77e0 | 6415 | goto out; |
b481de9c ZY |
6416 | } |
6417 | ||
fee1247a | 6418 | if (iwl_is_rfkill(priv)) { |
b481de9c | 6419 | IWL_DEBUG_MAC80211("leave - RF kill\n"); |
76bb77e0 ZY |
6420 | ret = -EIO; |
6421 | goto out; | |
b481de9c ZY |
6422 | } |
6423 | ||
bb8c093b | 6424 | iwl4965_set_rate(priv); |
b481de9c ZY |
6425 | |
6426 | if (memcmp(&priv->active_rxon, | |
6427 | &priv->staging_rxon, sizeof(priv->staging_rxon))) | |
bb8c093b | 6428 | iwl4965_commit_rxon(priv); |
b481de9c ZY |
6429 | else |
6430 | IWL_DEBUG_INFO("No re-sending same RXON configuration.\n"); | |
6431 | ||
6432 | IWL_DEBUG_MAC80211("leave\n"); | |
6433 | ||
a0646470 ZY |
6434 | out: |
6435 | clear_bit(STATUS_CONF_PENDING, &priv->status); | |
5a66926a | 6436 | mutex_unlock(&priv->mutex); |
76bb77e0 | 6437 | return ret; |
b481de9c ZY |
6438 | } |
6439 | ||
c79dd5b5 | 6440 | static void iwl4965_config_ap(struct iwl_priv *priv) |
b481de9c | 6441 | { |
857485c0 | 6442 | int ret = 0; |
b481de9c | 6443 | |
d986bcd1 | 6444 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
b481de9c ZY |
6445 | return; |
6446 | ||
6447 | /* The following should be done only at AP bring up */ | |
6448 | if ((priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) == 0) { | |
6449 | ||
6450 | /* RXON - unassoc (to set timing command) */ | |
6451 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
bb8c093b | 6452 | iwl4965_commit_rxon(priv); |
b481de9c ZY |
6453 | |
6454 | /* RXON Timing */ | |
bb8c093b CH |
6455 | memset(&priv->rxon_timing, 0, sizeof(struct iwl4965_rxon_time_cmd)); |
6456 | iwl4965_setup_rxon_timing(priv); | |
857485c0 | 6457 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
b481de9c | 6458 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
857485c0 | 6459 | if (ret) |
b481de9c ZY |
6460 | IWL_WARNING("REPLY_RXON_TIMING failed - " |
6461 | "Attempting to continue.\n"); | |
6462 | ||
6463 | iwl4965_set_rxon_chain(priv); | |
6464 | ||
6465 | /* FIXME: what should be the assoc_id for AP? */ | |
6466 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); | |
6467 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) | |
6468 | priv->staging_rxon.flags |= | |
6469 | RXON_FLG_SHORT_PREAMBLE_MSK; | |
6470 | else | |
6471 | priv->staging_rxon.flags &= | |
6472 | ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
6473 | ||
6474 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { | |
6475 | if (priv->assoc_capability & | |
6476 | WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
6477 | priv->staging_rxon.flags |= | |
6478 | RXON_FLG_SHORT_SLOT_MSK; | |
6479 | else | |
6480 | priv->staging_rxon.flags &= | |
6481 | ~RXON_FLG_SHORT_SLOT_MSK; | |
6482 | ||
6483 | if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) | |
6484 | priv->staging_rxon.flags &= | |
6485 | ~RXON_FLG_SHORT_SLOT_MSK; | |
6486 | } | |
6487 | /* restore RXON assoc */ | |
6488 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
bb8c093b | 6489 | iwl4965_commit_rxon(priv); |
bb8c093b | 6490 | iwl4965_activate_qos(priv, 1); |
bb8c093b | 6491 | iwl4965_rxon_add_station(priv, iwl4965_broadcast_addr, 0); |
e1493deb | 6492 | } |
bb8c093b | 6493 | iwl4965_send_beacon_cmd(priv); |
b481de9c ZY |
6494 | |
6495 | /* FIXME - we need to add code here to detect a totally new | |
6496 | * configuration, reset the AP, unassoc, rxon timing, assoc, | |
6497 | * clear sta table, add BCAST sta... */ | |
6498 | } | |
6499 | ||
32bfd35d JB |
6500 | static int iwl4965_mac_config_interface(struct ieee80211_hw *hw, |
6501 | struct ieee80211_vif *vif, | |
b481de9c ZY |
6502 | struct ieee80211_if_conf *conf) |
6503 | { | |
c79dd5b5 | 6504 | struct iwl_priv *priv = hw->priv; |
0795af57 | 6505 | DECLARE_MAC_BUF(mac); |
b481de9c ZY |
6506 | unsigned long flags; |
6507 | int rc; | |
6508 | ||
6509 | if (conf == NULL) | |
6510 | return -EIO; | |
6511 | ||
b716bb91 EG |
6512 | if (priv->vif != vif) { |
6513 | IWL_DEBUG_MAC80211("leave - priv->vif != vif\n"); | |
6514 | mutex_unlock(&priv->mutex); | |
6515 | return 0; | |
6516 | } | |
6517 | ||
b481de9c ZY |
6518 | if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) && |
6519 | (!conf->beacon || !conf->ssid_len)) { | |
6520 | IWL_DEBUG_MAC80211 | |
6521 | ("Leaving in AP mode because HostAPD is not ready.\n"); | |
6522 | return 0; | |
6523 | } | |
6524 | ||
fee1247a | 6525 | if (!iwl_is_alive(priv)) |
5a66926a ZY |
6526 | return -EAGAIN; |
6527 | ||
b481de9c ZY |
6528 | mutex_lock(&priv->mutex); |
6529 | ||
b481de9c | 6530 | if (conf->bssid) |
0795af57 JP |
6531 | IWL_DEBUG_MAC80211("bssid: %s\n", |
6532 | print_mac(mac, conf->bssid)); | |
b481de9c | 6533 | |
4150c572 JB |
6534 | /* |
6535 | * very dubious code was here; the probe filtering flag is never set: | |
6536 | * | |
b481de9c ZY |
6537 | if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) && |
6538 | !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) { | |
4150c572 | 6539 | */ |
b481de9c ZY |
6540 | |
6541 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { | |
6542 | if (!conf->bssid) { | |
6543 | conf->bssid = priv->mac_addr; | |
6544 | memcpy(priv->bssid, priv->mac_addr, ETH_ALEN); | |
0795af57 JP |
6545 | IWL_DEBUG_MAC80211("bssid was set to: %s\n", |
6546 | print_mac(mac, conf->bssid)); | |
b481de9c ZY |
6547 | } |
6548 | if (priv->ibss_beacon) | |
6549 | dev_kfree_skb(priv->ibss_beacon); | |
6550 | ||
6551 | priv->ibss_beacon = conf->beacon; | |
6552 | } | |
6553 | ||
fee1247a | 6554 | if (iwl_is_rfkill(priv)) |
fde3571f MA |
6555 | goto done; |
6556 | ||
b481de9c ZY |
6557 | if (conf->bssid && !is_zero_ether_addr(conf->bssid) && |
6558 | !is_multicast_ether_addr(conf->bssid)) { | |
6559 | /* If there is currently a HW scan going on in the background | |
6560 | * then we need to cancel it else the RXON below will fail. */ | |
bb8c093b | 6561 | if (iwl4965_scan_cancel_timeout(priv, 100)) { |
b481de9c ZY |
6562 | IWL_WARNING("Aborted scan still in progress " |
6563 | "after 100ms\n"); | |
6564 | IWL_DEBUG_MAC80211("leaving - scan abort failed.\n"); | |
6565 | mutex_unlock(&priv->mutex); | |
6566 | return -EAGAIN; | |
6567 | } | |
6568 | memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN); | |
6569 | ||
6570 | /* TODO: Audit driver for usage of these members and see | |
6571 | * if mac80211 deprecates them (priv->bssid looks like it | |
6572 | * shouldn't be there, but I haven't scanned the IBSS code | |
6573 | * to verify) - jpk */ | |
6574 | memcpy(priv->bssid, conf->bssid, ETH_ALEN); | |
6575 | ||
6576 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) | |
bb8c093b | 6577 | iwl4965_config_ap(priv); |
b481de9c | 6578 | else { |
bb8c093b | 6579 | rc = iwl4965_commit_rxon(priv); |
b481de9c | 6580 | if ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && rc) |
bb8c093b | 6581 | iwl4965_rxon_add_station( |
b481de9c ZY |
6582 | priv, priv->active_rxon.bssid_addr, 1); |
6583 | } | |
6584 | ||
6585 | } else { | |
bb8c093b | 6586 | iwl4965_scan_cancel_timeout(priv, 100); |
b481de9c | 6587 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
bb8c093b | 6588 | iwl4965_commit_rxon(priv); |
b481de9c ZY |
6589 | } |
6590 | ||
fde3571f | 6591 | done: |
b481de9c ZY |
6592 | spin_lock_irqsave(&priv->lock, flags); |
6593 | if (!conf->ssid_len) | |
6594 | memset(priv->essid, 0, IW_ESSID_MAX_SIZE); | |
6595 | else | |
6596 | memcpy(priv->essid, conf->ssid, conf->ssid_len); | |
6597 | ||
6598 | priv->essid_len = conf->ssid_len; | |
6599 | spin_unlock_irqrestore(&priv->lock, flags); | |
6600 | ||
6601 | IWL_DEBUG_MAC80211("leave\n"); | |
6602 | mutex_unlock(&priv->mutex); | |
6603 | ||
6604 | return 0; | |
6605 | } | |
6606 | ||
bb8c093b | 6607 | static void iwl4965_configure_filter(struct ieee80211_hw *hw, |
4150c572 JB |
6608 | unsigned int changed_flags, |
6609 | unsigned int *total_flags, | |
6610 | int mc_count, struct dev_addr_list *mc_list) | |
6611 | { | |
6612 | /* | |
6613 | * XXX: dummy | |
bb8c093b | 6614 | * see also iwl4965_connection_init_rx_config |
4150c572 JB |
6615 | */ |
6616 | *total_flags = 0; | |
6617 | } | |
6618 | ||
bb8c093b | 6619 | static void iwl4965_mac_remove_interface(struct ieee80211_hw *hw, |
b481de9c ZY |
6620 | struct ieee80211_if_init_conf *conf) |
6621 | { | |
c79dd5b5 | 6622 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
6623 | |
6624 | IWL_DEBUG_MAC80211("enter\n"); | |
6625 | ||
6626 | mutex_lock(&priv->mutex); | |
948c171c | 6627 | |
fee1247a | 6628 | if (iwl_is_ready_rf(priv)) { |
fde3571f MA |
6629 | iwl4965_scan_cancel_timeout(priv, 100); |
6630 | cancel_delayed_work(&priv->post_associate); | |
6631 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
6632 | iwl4965_commit_rxon(priv); | |
6633 | } | |
32bfd35d JB |
6634 | if (priv->vif == conf->vif) { |
6635 | priv->vif = NULL; | |
b481de9c ZY |
6636 | memset(priv->bssid, 0, ETH_ALEN); |
6637 | memset(priv->essid, 0, IW_ESSID_MAX_SIZE); | |
6638 | priv->essid_len = 0; | |
6639 | } | |
6640 | mutex_unlock(&priv->mutex); | |
6641 | ||
6642 | IWL_DEBUG_MAC80211("leave\n"); | |
6643 | ||
6644 | } | |
471b3efd | 6645 | |
98952d5d TW |
6646 | |
6647 | #ifdef CONFIG_IWL4965_HT | |
6648 | static void iwl4965_ht_conf(struct iwl_priv *priv, | |
6649 | struct ieee80211_bss_conf *bss_conf) | |
6650 | { | |
6651 | struct ieee80211_ht_info *ht_conf = bss_conf->ht_conf; | |
6652 | struct ieee80211_ht_bss_info *ht_bss_conf = bss_conf->ht_bss_conf; | |
6653 | struct iwl_ht_info *iwl_conf = &priv->current_ht_config; | |
6654 | ||
6655 | IWL_DEBUG_MAC80211("enter: \n"); | |
6656 | ||
6657 | iwl_conf->is_ht = bss_conf->assoc_ht; | |
6658 | ||
6659 | if (!iwl_conf->is_ht) | |
6660 | return; | |
6661 | ||
6662 | priv->ps_mode = (u8)((ht_conf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2); | |
6663 | ||
6664 | if (ht_conf->cap & IEEE80211_HT_CAP_SGI_20) | |
6665 | iwl_conf->sgf |= 0x1; | |
6666 | if (ht_conf->cap & IEEE80211_HT_CAP_SGI_40) | |
6667 | iwl_conf->sgf |= 0x2; | |
6668 | ||
6669 | iwl_conf->is_green_field = !!(ht_conf->cap & IEEE80211_HT_CAP_GRN_FLD); | |
6670 | iwl_conf->max_amsdu_size = | |
6671 | !!(ht_conf->cap & IEEE80211_HT_CAP_MAX_AMSDU); | |
6672 | ||
6673 | iwl_conf->supported_chan_width = | |
6674 | !!(ht_conf->cap & IEEE80211_HT_CAP_SUP_WIDTH); | |
6675 | iwl_conf->extension_chan_offset = | |
6676 | ht_bss_conf->bss_cap & IEEE80211_HT_IE_CHA_SEC_OFFSET; | |
6677 | /* If no above or below channel supplied disable FAT channel */ | |
6678 | if (iwl_conf->extension_chan_offset != IWL_EXT_CHANNEL_OFFSET_ABOVE && | |
6679 | iwl_conf->extension_chan_offset != IWL_EXT_CHANNEL_OFFSET_BELOW) | |
6680 | iwl_conf->supported_chan_width = 0; | |
6681 | ||
6682 | iwl_conf->tx_mimo_ps_mode = | |
6683 | (u8)((ht_conf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2); | |
6684 | memcpy(iwl_conf->supp_mcs_set, ht_conf->supp_mcs_set, 16); | |
6685 | ||
6686 | iwl_conf->control_channel = ht_bss_conf->primary_channel; | |
6687 | iwl_conf->tx_chan_width = | |
6688 | !!(ht_bss_conf->bss_cap & IEEE80211_HT_IE_CHA_WIDTH); | |
6689 | iwl_conf->ht_protection = | |
6690 | ht_bss_conf->bss_op_mode & IEEE80211_HT_IE_HT_PROTECTION; | |
6691 | iwl_conf->non_GF_STA_present = | |
6692 | !!(ht_bss_conf->bss_op_mode & IEEE80211_HT_IE_NON_GF_STA_PRSNT); | |
6693 | ||
6694 | IWL_DEBUG_MAC80211("control channel %d\n", iwl_conf->control_channel); | |
6695 | IWL_DEBUG_MAC80211("leave\n"); | |
6696 | } | |
6697 | #else | |
6698 | static inline void iwl4965_ht_conf(struct iwl_priv *priv, | |
6699 | struct ieee80211_bss_conf *bss_conf) | |
6700 | { | |
6701 | } | |
6702 | #endif | |
6703 | ||
3109ece1 | 6704 | #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6) |
471b3efd JB |
6705 | static void iwl4965_bss_info_changed(struct ieee80211_hw *hw, |
6706 | struct ieee80211_vif *vif, | |
6707 | struct ieee80211_bss_conf *bss_conf, | |
6708 | u32 changes) | |
220173b0 | 6709 | { |
c79dd5b5 | 6710 | struct iwl_priv *priv = hw->priv; |
220173b0 | 6711 | |
3109ece1 TW |
6712 | IWL_DEBUG_MAC80211("changes = 0x%X\n", changes); |
6713 | ||
471b3efd | 6714 | if (changes & BSS_CHANGED_ERP_PREAMBLE) { |
3109ece1 TW |
6715 | IWL_DEBUG_MAC80211("ERP_PREAMBLE %d\n", |
6716 | bss_conf->use_short_preamble); | |
471b3efd | 6717 | if (bss_conf->use_short_preamble) |
220173b0 TW |
6718 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; |
6719 | else | |
6720 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
6721 | } | |
6722 | ||
471b3efd | 6723 | if (changes & BSS_CHANGED_ERP_CTS_PROT) { |
3109ece1 | 6724 | IWL_DEBUG_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot); |
8318d78a | 6725 | if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ)) |
220173b0 TW |
6726 | priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK; |
6727 | else | |
6728 | priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK; | |
6729 | } | |
6730 | ||
98952d5d | 6731 | if (changes & BSS_CHANGED_HT) { |
3109ece1 | 6732 | IWL_DEBUG_MAC80211("HT %d\n", bss_conf->assoc_ht); |
98952d5d TW |
6733 | iwl4965_ht_conf(priv, bss_conf); |
6734 | iwl4965_set_rxon_chain(priv); | |
6735 | } | |
6736 | ||
471b3efd | 6737 | if (changes & BSS_CHANGED_ASSOC) { |
3109ece1 | 6738 | IWL_DEBUG_MAC80211("ASSOC %d\n", bss_conf->assoc); |
508e32e1 RC |
6739 | /* This should never happen as this function should |
6740 | * never be called from interrupt context. */ | |
6741 | if (WARN_ON_ONCE(in_interrupt())) | |
6742 | return; | |
3109ece1 TW |
6743 | if (bss_conf->assoc) { |
6744 | priv->assoc_id = bss_conf->aid; | |
6745 | priv->beacon_int = bss_conf->beacon_int; | |
6746 | priv->timestamp = bss_conf->timestamp; | |
6747 | priv->assoc_capability = bss_conf->assoc_capability; | |
6748 | priv->next_scan_jiffies = jiffies + | |
6749 | IWL_DELAY_NEXT_SCAN_AFTER_ASSOC; | |
508e32e1 RC |
6750 | mutex_lock(&priv->mutex); |
6751 | iwl4965_post_associate(priv); | |
6752 | mutex_unlock(&priv->mutex); | |
3109ece1 TW |
6753 | } else { |
6754 | priv->assoc_id = 0; | |
6755 | IWL_DEBUG_MAC80211("DISASSOC %d\n", bss_conf->assoc); | |
6756 | } | |
6757 | } else if (changes && iwl_is_associated(priv) && priv->assoc_id) { | |
6758 | IWL_DEBUG_MAC80211("Associated Changes %d\n", changes); | |
6759 | iwl4965_send_rxon_assoc(priv); | |
471b3efd JB |
6760 | } |
6761 | ||
220173b0 | 6762 | } |
b481de9c | 6763 | |
bb8c093b | 6764 | static int iwl4965_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len) |
b481de9c ZY |
6765 | { |
6766 | int rc = 0; | |
6767 | unsigned long flags; | |
c79dd5b5 | 6768 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
6769 | |
6770 | IWL_DEBUG_MAC80211("enter\n"); | |
6771 | ||
052c4b9f | 6772 | mutex_lock(&priv->mutex); |
b481de9c ZY |
6773 | spin_lock_irqsave(&priv->lock, flags); |
6774 | ||
fee1247a | 6775 | if (!iwl_is_ready_rf(priv)) { |
b481de9c ZY |
6776 | rc = -EIO; |
6777 | IWL_DEBUG_MAC80211("leave - not ready or exit pending\n"); | |
6778 | goto out_unlock; | |
6779 | } | |
6780 | ||
6781 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { /* APs don't scan */ | |
6782 | rc = -EIO; | |
6783 | IWL_ERROR("ERROR: APs don't scan\n"); | |
6784 | goto out_unlock; | |
6785 | } | |
6786 | ||
7878a5a4 MA |
6787 | /* we don't schedule scan within next_scan_jiffies period */ |
6788 | if (priv->next_scan_jiffies && | |
6789 | time_after(priv->next_scan_jiffies, jiffies)) { | |
6790 | rc = -EAGAIN; | |
6791 | goto out_unlock; | |
6792 | } | |
b481de9c | 6793 | /* if we just finished scan ask for delay */ |
7878a5a4 MA |
6794 | if (priv->last_scan_jiffies && time_after(priv->last_scan_jiffies + |
6795 | IWL_DELAY_NEXT_SCAN, jiffies)) { | |
b481de9c ZY |
6796 | rc = -EAGAIN; |
6797 | goto out_unlock; | |
6798 | } | |
6799 | if (len) { | |
7878a5a4 | 6800 | IWL_DEBUG_SCAN("direct scan for %s [%d]\n ", |
bb8c093b | 6801 | iwl4965_escape_essid(ssid, len), (int)len); |
b481de9c ZY |
6802 | |
6803 | priv->one_direct_scan = 1; | |
6804 | priv->direct_ssid_len = (u8) | |
6805 | min((u8) len, (u8) IW_ESSID_MAX_SIZE); | |
6806 | memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len); | |
948c171c MA |
6807 | } else |
6808 | priv->one_direct_scan = 0; | |
b481de9c | 6809 | |
bb8c093b | 6810 | rc = iwl4965_scan_initiate(priv); |
b481de9c ZY |
6811 | |
6812 | IWL_DEBUG_MAC80211("leave\n"); | |
6813 | ||
6814 | out_unlock: | |
6815 | spin_unlock_irqrestore(&priv->lock, flags); | |
052c4b9f | 6816 | mutex_unlock(&priv->mutex); |
b481de9c ZY |
6817 | |
6818 | return rc; | |
6819 | } | |
6820 | ||
ab885f8c EG |
6821 | static void iwl4965_mac_update_tkip_key(struct ieee80211_hw *hw, |
6822 | struct ieee80211_key_conf *keyconf, const u8 *addr, | |
6823 | u32 iv32, u16 *phase1key) | |
6824 | { | |
6825 | struct iwl_priv *priv = hw->priv; | |
6826 | u8 sta_id = IWL_INVALID_STATION; | |
6827 | unsigned long flags; | |
6828 | __le16 key_flags = 0; | |
6829 | int i; | |
6830 | DECLARE_MAC_BUF(mac); | |
6831 | ||
6832 | IWL_DEBUG_MAC80211("enter\n"); | |
6833 | ||
6834 | sta_id = iwl4965_hw_find_station(priv, addr); | |
6835 | if (sta_id == IWL_INVALID_STATION) { | |
6836 | IWL_DEBUG_MAC80211("leave - %s not in station map.\n", | |
6837 | print_mac(mac, addr)); | |
6838 | return; | |
6839 | } | |
6840 | ||
6841 | iwl4965_scan_cancel_timeout(priv, 100); | |
6842 | ||
6843 | key_flags |= (STA_KEY_FLG_TKIP | STA_KEY_FLG_MAP_KEY_MSK); | |
6844 | key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS); | |
6845 | key_flags &= ~STA_KEY_FLG_INVALID; | |
6846 | ||
6847 | if (sta_id == priv->hw_setting.bcast_sta_id) | |
6848 | key_flags |= STA_KEY_MULTICAST_MSK; | |
6849 | ||
6850 | spin_lock_irqsave(&priv->sta_lock, flags); | |
6851 | ||
6852 | priv->stations[sta_id].sta.key.key_offset = | |
80fb47a1 | 6853 | iwl_get_free_ucode_key_index(priv); |
ab885f8c EG |
6854 | priv->stations[sta_id].sta.key.key_flags = key_flags; |
6855 | priv->stations[sta_id].sta.key.tkip_rx_tsc_byte2 = (u8) iv32; | |
6856 | ||
6857 | for (i = 0; i < 5; i++) | |
6858 | priv->stations[sta_id].sta.key.tkip_rx_ttak[i] = | |
6859 | cpu_to_le16(phase1key[i]); | |
6860 | ||
6861 | priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; | |
6862 | priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
6863 | ||
6864 | iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC); | |
6865 | ||
6866 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
6867 | ||
6868 | IWL_DEBUG_MAC80211("leave\n"); | |
6869 | } | |
6870 | ||
bb8c093b | 6871 | static int iwl4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
b481de9c ZY |
6872 | const u8 *local_addr, const u8 *addr, |
6873 | struct ieee80211_key_conf *key) | |
6874 | { | |
c79dd5b5 | 6875 | struct iwl_priv *priv = hw->priv; |
0795af57 | 6876 | DECLARE_MAC_BUF(mac); |
deb09c43 EG |
6877 | int ret = 0; |
6878 | u8 sta_id = IWL_INVALID_STATION; | |
6974e363 | 6879 | u8 is_default_wep_key = 0; |
b481de9c ZY |
6880 | |
6881 | IWL_DEBUG_MAC80211("enter\n"); | |
6882 | ||
1ea87396 | 6883 | if (!priv->cfg->mod_params->hw_crypto) { |
b481de9c ZY |
6884 | IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n"); |
6885 | return -EOPNOTSUPP; | |
6886 | } | |
6887 | ||
6888 | if (is_zero_ether_addr(addr)) | |
6889 | /* only support pairwise keys */ | |
6890 | return -EOPNOTSUPP; | |
6891 | ||
6974e363 EG |
6892 | sta_id = iwl4965_hw_find_station(priv, addr); |
6893 | if (sta_id == IWL_INVALID_STATION) { | |
6894 | IWL_DEBUG_MAC80211("leave - %s not in station map.\n", | |
6895 | print_mac(mac, addr)); | |
6896 | return -EINVAL; | |
b481de9c | 6897 | |
deb09c43 | 6898 | } |
b481de9c | 6899 | |
6974e363 | 6900 | mutex_lock(&priv->mutex); |
bb8c093b | 6901 | iwl4965_scan_cancel_timeout(priv, 100); |
6974e363 EG |
6902 | mutex_unlock(&priv->mutex); |
6903 | ||
6904 | /* If we are getting WEP group key and we didn't receive any key mapping | |
6905 | * so far, we are in legacy wep mode (group key only), otherwise we are | |
6906 | * in 1X mode. | |
6907 | * In legacy wep mode, we use another host command to the uCode */ | |
6908 | if (key->alg == ALG_WEP && sta_id == priv->hw_setting.bcast_sta_id && | |
6909 | priv->iw_mode != IEEE80211_IF_TYPE_AP) { | |
6910 | if (cmd == SET_KEY) | |
6911 | is_default_wep_key = !priv->key_mapping_key; | |
6912 | else | |
6913 | is_default_wep_key = priv->default_wep_key; | |
6914 | } | |
052c4b9f | 6915 | |
b481de9c | 6916 | switch (cmd) { |
deb09c43 | 6917 | case SET_KEY: |
6974e363 EG |
6918 | if (is_default_wep_key) |
6919 | ret = iwl_set_default_wep_key(priv, key); | |
deb09c43 | 6920 | else |
7480513f | 6921 | ret = iwl_set_dynamic_key(priv, key, sta_id); |
deb09c43 EG |
6922 | |
6923 | IWL_DEBUG_MAC80211("enable hwcrypto key\n"); | |
b481de9c ZY |
6924 | break; |
6925 | case DISABLE_KEY: | |
6974e363 EG |
6926 | if (is_default_wep_key) |
6927 | ret = iwl_remove_default_wep_key(priv, key); | |
deb09c43 | 6928 | else |
7480513f | 6929 | ret = iwl_remove_dynamic_key(priv, sta_id); |
deb09c43 EG |
6930 | |
6931 | IWL_DEBUG_MAC80211("disable hwcrypto key\n"); | |
b481de9c ZY |
6932 | break; |
6933 | default: | |
deb09c43 | 6934 | ret = -EINVAL; |
b481de9c ZY |
6935 | } |
6936 | ||
6937 | IWL_DEBUG_MAC80211("leave\n"); | |
b481de9c | 6938 | |
deb09c43 | 6939 | return ret; |
b481de9c ZY |
6940 | } |
6941 | ||
bb8c093b | 6942 | static int iwl4965_mac_conf_tx(struct ieee80211_hw *hw, int queue, |
b481de9c ZY |
6943 | const struct ieee80211_tx_queue_params *params) |
6944 | { | |
c79dd5b5 | 6945 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
6946 | unsigned long flags; |
6947 | int q; | |
b481de9c ZY |
6948 | |
6949 | IWL_DEBUG_MAC80211("enter\n"); | |
6950 | ||
fee1247a | 6951 | if (!iwl_is_ready_rf(priv)) { |
b481de9c ZY |
6952 | IWL_DEBUG_MAC80211("leave - RF not ready\n"); |
6953 | return -EIO; | |
6954 | } | |
6955 | ||
6956 | if (queue >= AC_NUM) { | |
6957 | IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue); | |
6958 | return 0; | |
6959 | } | |
6960 | ||
b481de9c ZY |
6961 | if (!priv->qos_data.qos_enable) { |
6962 | priv->qos_data.qos_active = 0; | |
6963 | IWL_DEBUG_MAC80211("leave - qos not enabled\n"); | |
6964 | return 0; | |
6965 | } | |
6966 | q = AC_NUM - 1 - queue; | |
6967 | ||
6968 | spin_lock_irqsave(&priv->lock, flags); | |
6969 | ||
6970 | priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min); | |
6971 | priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max); | |
6972 | priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs; | |
6973 | priv->qos_data.def_qos_parm.ac[q].edca_txop = | |
3330d7be | 6974 | cpu_to_le16((params->txop * 32)); |
b481de9c ZY |
6975 | |
6976 | priv->qos_data.def_qos_parm.ac[q].reserved1 = 0; | |
6977 | priv->qos_data.qos_active = 1; | |
6978 | ||
6979 | spin_unlock_irqrestore(&priv->lock, flags); | |
6980 | ||
6981 | mutex_lock(&priv->mutex); | |
6982 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) | |
bb8c093b | 6983 | iwl4965_activate_qos(priv, 1); |
3109ece1 | 6984 | else if (priv->assoc_id && iwl_is_associated(priv)) |
bb8c093b | 6985 | iwl4965_activate_qos(priv, 0); |
b481de9c ZY |
6986 | |
6987 | mutex_unlock(&priv->mutex); | |
6988 | ||
b481de9c ZY |
6989 | IWL_DEBUG_MAC80211("leave\n"); |
6990 | return 0; | |
6991 | } | |
6992 | ||
bb8c093b | 6993 | static int iwl4965_mac_get_tx_stats(struct ieee80211_hw *hw, |
b481de9c ZY |
6994 | struct ieee80211_tx_queue_stats *stats) |
6995 | { | |
c79dd5b5 | 6996 | struct iwl_priv *priv = hw->priv; |
b481de9c | 6997 | int i, avail; |
bb8c093b CH |
6998 | struct iwl4965_tx_queue *txq; |
6999 | struct iwl4965_queue *q; | |
b481de9c ZY |
7000 | unsigned long flags; |
7001 | ||
7002 | IWL_DEBUG_MAC80211("enter\n"); | |
7003 | ||
fee1247a | 7004 | if (!iwl_is_ready_rf(priv)) { |
b481de9c ZY |
7005 | IWL_DEBUG_MAC80211("leave - RF not ready\n"); |
7006 | return -EIO; | |
7007 | } | |
7008 | ||
7009 | spin_lock_irqsave(&priv->lock, flags); | |
7010 | ||
7011 | for (i = 0; i < AC_NUM; i++) { | |
7012 | txq = &priv->txq[i]; | |
7013 | q = &txq->q; | |
bb8c093b | 7014 | avail = iwl4965_queue_space(q); |
b481de9c ZY |
7015 | |
7016 | stats->data[i].len = q->n_window - avail; | |
7017 | stats->data[i].limit = q->n_window - q->high_mark; | |
7018 | stats->data[i].count = q->n_window; | |
7019 | ||
7020 | } | |
7021 | spin_unlock_irqrestore(&priv->lock, flags); | |
7022 | ||
7023 | IWL_DEBUG_MAC80211("leave\n"); | |
7024 | ||
7025 | return 0; | |
7026 | } | |
7027 | ||
bb8c093b | 7028 | static int iwl4965_mac_get_stats(struct ieee80211_hw *hw, |
b481de9c ZY |
7029 | struct ieee80211_low_level_stats *stats) |
7030 | { | |
7031 | IWL_DEBUG_MAC80211("enter\n"); | |
7032 | IWL_DEBUG_MAC80211("leave\n"); | |
7033 | ||
7034 | return 0; | |
7035 | } | |
7036 | ||
bb8c093b | 7037 | static u64 iwl4965_mac_get_tsf(struct ieee80211_hw *hw) |
b481de9c ZY |
7038 | { |
7039 | IWL_DEBUG_MAC80211("enter\n"); | |
7040 | IWL_DEBUG_MAC80211("leave\n"); | |
7041 | ||
7042 | return 0; | |
7043 | } | |
7044 | ||
bb8c093b | 7045 | static void iwl4965_mac_reset_tsf(struct ieee80211_hw *hw) |
b481de9c | 7046 | { |
c79dd5b5 | 7047 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
7048 | unsigned long flags; |
7049 | ||
7050 | mutex_lock(&priv->mutex); | |
7051 | IWL_DEBUG_MAC80211("enter\n"); | |
7052 | ||
7053 | priv->lq_mngr.lq_ready = 0; | |
c8b0e6e1 | 7054 | #ifdef CONFIG_IWL4965_HT |
b481de9c | 7055 | spin_lock_irqsave(&priv->lock, flags); |
fd105e79 | 7056 | memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_info)); |
b481de9c | 7057 | spin_unlock_irqrestore(&priv->lock, flags); |
c8b0e6e1 | 7058 | #endif /* CONFIG_IWL4965_HT */ |
b481de9c | 7059 | |
bf85ea4f | 7060 | iwlcore_reset_qos(priv); |
b481de9c ZY |
7061 | |
7062 | cancel_delayed_work(&priv->post_associate); | |
7063 | ||
7064 | spin_lock_irqsave(&priv->lock, flags); | |
7065 | priv->assoc_id = 0; | |
7066 | priv->assoc_capability = 0; | |
b481de9c ZY |
7067 | priv->assoc_station_added = 0; |
7068 | ||
7069 | /* new association get rid of ibss beacon skb */ | |
7070 | if (priv->ibss_beacon) | |
7071 | dev_kfree_skb(priv->ibss_beacon); | |
7072 | ||
7073 | priv->ibss_beacon = NULL; | |
7074 | ||
7075 | priv->beacon_int = priv->hw->conf.beacon_int; | |
3109ece1 | 7076 | priv->timestamp = 0; |
b481de9c ZY |
7077 | if ((priv->iw_mode == IEEE80211_IF_TYPE_STA)) |
7078 | priv->beacon_int = 0; | |
7079 | ||
7080 | spin_unlock_irqrestore(&priv->lock, flags); | |
7081 | ||
fee1247a | 7082 | if (!iwl_is_ready_rf(priv)) { |
fde3571f MA |
7083 | IWL_DEBUG_MAC80211("leave - not ready\n"); |
7084 | mutex_unlock(&priv->mutex); | |
7085 | return; | |
7086 | } | |
7087 | ||
052c4b9f | 7088 | /* we are restarting association process |
7089 | * clear RXON_FILTER_ASSOC_MSK bit | |
7090 | */ | |
7091 | if (priv->iw_mode != IEEE80211_IF_TYPE_AP) { | |
bb8c093b | 7092 | iwl4965_scan_cancel_timeout(priv, 100); |
052c4b9f | 7093 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
bb8c093b | 7094 | iwl4965_commit_rxon(priv); |
052c4b9f | 7095 | } |
7096 | ||
b481de9c ZY |
7097 | /* Per mac80211.h: This is only used in IBSS mode... */ |
7098 | if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) { | |
052c4b9f | 7099 | |
b481de9c ZY |
7100 | IWL_DEBUG_MAC80211("leave - not in IBSS\n"); |
7101 | mutex_unlock(&priv->mutex); | |
7102 | return; | |
7103 | } | |
7104 | ||
b481de9c ZY |
7105 | priv->only_active_channel = 0; |
7106 | ||
bb8c093b | 7107 | iwl4965_set_rate(priv); |
b481de9c ZY |
7108 | |
7109 | mutex_unlock(&priv->mutex); | |
7110 | ||
7111 | IWL_DEBUG_MAC80211("leave\n"); | |
b481de9c ZY |
7112 | } |
7113 | ||
bb8c093b | 7114 | static int iwl4965_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb, |
b481de9c ZY |
7115 | struct ieee80211_tx_control *control) |
7116 | { | |
c79dd5b5 | 7117 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
7118 | unsigned long flags; |
7119 | ||
7120 | mutex_lock(&priv->mutex); | |
7121 | IWL_DEBUG_MAC80211("enter\n"); | |
7122 | ||
fee1247a | 7123 | if (!iwl_is_ready_rf(priv)) { |
b481de9c ZY |
7124 | IWL_DEBUG_MAC80211("leave - RF not ready\n"); |
7125 | mutex_unlock(&priv->mutex); | |
7126 | return -EIO; | |
7127 | } | |
7128 | ||
7129 | if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) { | |
7130 | IWL_DEBUG_MAC80211("leave - not IBSS\n"); | |
7131 | mutex_unlock(&priv->mutex); | |
7132 | return -EIO; | |
7133 | } | |
7134 | ||
7135 | spin_lock_irqsave(&priv->lock, flags); | |
7136 | ||
7137 | if (priv->ibss_beacon) | |
7138 | dev_kfree_skb(priv->ibss_beacon); | |
7139 | ||
7140 | priv->ibss_beacon = skb; | |
7141 | ||
7142 | priv->assoc_id = 0; | |
7143 | ||
7144 | IWL_DEBUG_MAC80211("leave\n"); | |
7145 | spin_unlock_irqrestore(&priv->lock, flags); | |
7146 | ||
bf85ea4f | 7147 | iwlcore_reset_qos(priv); |
b481de9c ZY |
7148 | |
7149 | queue_work(priv->workqueue, &priv->post_associate.work); | |
7150 | ||
7151 | mutex_unlock(&priv->mutex); | |
7152 | ||
7153 | return 0; | |
7154 | } | |
7155 | ||
b481de9c ZY |
7156 | /***************************************************************************** |
7157 | * | |
7158 | * sysfs attributes | |
7159 | * | |
7160 | *****************************************************************************/ | |
7161 | ||
0a6857e7 | 7162 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
7163 | |
7164 | /* | |
7165 | * The following adds a new attribute to the sysfs representation | |
7166 | * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/) | |
7167 | * used for controlling the debug level. | |
7168 | * | |
7169 | * See the level definitions in iwl for details. | |
7170 | */ | |
7171 | ||
7172 | static ssize_t show_debug_level(struct device_driver *d, char *buf) | |
7173 | { | |
0a6857e7 | 7174 | return sprintf(buf, "0x%08X\n", iwl_debug_level); |
b481de9c ZY |
7175 | } |
7176 | static ssize_t store_debug_level(struct device_driver *d, | |
7177 | const char *buf, size_t count) | |
7178 | { | |
7179 | char *p = (char *)buf; | |
7180 | u32 val; | |
7181 | ||
7182 | val = simple_strtoul(p, &p, 0); | |
7183 | if (p == buf) | |
7184 | printk(KERN_INFO DRV_NAME | |
7185 | ": %s is not in hex or decimal form.\n", buf); | |
7186 | else | |
0a6857e7 | 7187 | iwl_debug_level = val; |
b481de9c ZY |
7188 | |
7189 | return strnlen(buf, count); | |
7190 | } | |
7191 | ||
7192 | static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO, | |
7193 | show_debug_level, store_debug_level); | |
7194 | ||
0a6857e7 | 7195 | #endif /* CONFIG_IWLWIFI_DEBUG */ |
b481de9c | 7196 | |
b481de9c ZY |
7197 | |
7198 | static ssize_t show_temperature(struct device *d, | |
7199 | struct device_attribute *attr, char *buf) | |
7200 | { | |
c79dd5b5 | 7201 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c | 7202 | |
fee1247a | 7203 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
7204 | return -EAGAIN; |
7205 | ||
bb8c093b | 7206 | return sprintf(buf, "%d\n", iwl4965_hw_get_temperature(priv)); |
b481de9c ZY |
7207 | } |
7208 | ||
7209 | static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL); | |
7210 | ||
7211 | static ssize_t show_rs_window(struct device *d, | |
7212 | struct device_attribute *attr, | |
7213 | char *buf) | |
7214 | { | |
c79dd5b5 | 7215 | struct iwl_priv *priv = d->driver_data; |
bb8c093b | 7216 | return iwl4965_fill_rs_info(priv->hw, buf, IWL_AP_ID); |
b481de9c ZY |
7217 | } |
7218 | static DEVICE_ATTR(rs_window, S_IRUGO, show_rs_window, NULL); | |
7219 | ||
7220 | static ssize_t show_tx_power(struct device *d, | |
7221 | struct device_attribute *attr, char *buf) | |
7222 | { | |
c79dd5b5 | 7223 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
7224 | return sprintf(buf, "%d\n", priv->user_txpower_limit); |
7225 | } | |
7226 | ||
7227 | static ssize_t store_tx_power(struct device *d, | |
7228 | struct device_attribute *attr, | |
7229 | const char *buf, size_t count) | |
7230 | { | |
c79dd5b5 | 7231 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
7232 | char *p = (char *)buf; |
7233 | u32 val; | |
7234 | ||
7235 | val = simple_strtoul(p, &p, 10); | |
7236 | if (p == buf) | |
7237 | printk(KERN_INFO DRV_NAME | |
7238 | ": %s is not in decimal form.\n", buf); | |
7239 | else | |
bb8c093b | 7240 | iwl4965_hw_reg_set_txpower(priv, val); |
b481de9c ZY |
7241 | |
7242 | return count; | |
7243 | } | |
7244 | ||
7245 | static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power); | |
7246 | ||
7247 | static ssize_t show_flags(struct device *d, | |
7248 | struct device_attribute *attr, char *buf) | |
7249 | { | |
c79dd5b5 | 7250 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
7251 | |
7252 | return sprintf(buf, "0x%04X\n", priv->active_rxon.flags); | |
7253 | } | |
7254 | ||
7255 | static ssize_t store_flags(struct device *d, | |
7256 | struct device_attribute *attr, | |
7257 | const char *buf, size_t count) | |
7258 | { | |
c79dd5b5 | 7259 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
7260 | u32 flags = simple_strtoul(buf, NULL, 0); |
7261 | ||
7262 | mutex_lock(&priv->mutex); | |
7263 | if (le32_to_cpu(priv->staging_rxon.flags) != flags) { | |
7264 | /* Cancel any currently running scans... */ | |
bb8c093b | 7265 | if (iwl4965_scan_cancel_timeout(priv, 100)) |
b481de9c ZY |
7266 | IWL_WARNING("Could not cancel scan.\n"); |
7267 | else { | |
7268 | IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n", | |
7269 | flags); | |
7270 | priv->staging_rxon.flags = cpu_to_le32(flags); | |
bb8c093b | 7271 | iwl4965_commit_rxon(priv); |
b481de9c ZY |
7272 | } |
7273 | } | |
7274 | mutex_unlock(&priv->mutex); | |
7275 | ||
7276 | return count; | |
7277 | } | |
7278 | ||
7279 | static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags); | |
7280 | ||
7281 | static ssize_t show_filter_flags(struct device *d, | |
7282 | struct device_attribute *attr, char *buf) | |
7283 | { | |
c79dd5b5 | 7284 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
7285 | |
7286 | return sprintf(buf, "0x%04X\n", | |
7287 | le32_to_cpu(priv->active_rxon.filter_flags)); | |
7288 | } | |
7289 | ||
7290 | static ssize_t store_filter_flags(struct device *d, | |
7291 | struct device_attribute *attr, | |
7292 | const char *buf, size_t count) | |
7293 | { | |
c79dd5b5 | 7294 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
7295 | u32 filter_flags = simple_strtoul(buf, NULL, 0); |
7296 | ||
7297 | mutex_lock(&priv->mutex); | |
7298 | if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) { | |
7299 | /* Cancel any currently running scans... */ | |
bb8c093b | 7300 | if (iwl4965_scan_cancel_timeout(priv, 100)) |
b481de9c ZY |
7301 | IWL_WARNING("Could not cancel scan.\n"); |
7302 | else { | |
7303 | IWL_DEBUG_INFO("Committing rxon.filter_flags = " | |
7304 | "0x%04X\n", filter_flags); | |
7305 | priv->staging_rxon.filter_flags = | |
7306 | cpu_to_le32(filter_flags); | |
bb8c093b | 7307 | iwl4965_commit_rxon(priv); |
b481de9c ZY |
7308 | } |
7309 | } | |
7310 | mutex_unlock(&priv->mutex); | |
7311 | ||
7312 | return count; | |
7313 | } | |
7314 | ||
7315 | static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags, | |
7316 | store_filter_flags); | |
7317 | ||
c8b0e6e1 | 7318 | #ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT |
b481de9c ZY |
7319 | |
7320 | static ssize_t show_measurement(struct device *d, | |
7321 | struct device_attribute *attr, char *buf) | |
7322 | { | |
c79dd5b5 | 7323 | struct iwl_priv *priv = dev_get_drvdata(d); |
bb8c093b | 7324 | struct iwl4965_spectrum_notification measure_report; |
b481de9c ZY |
7325 | u32 size = sizeof(measure_report), len = 0, ofs = 0; |
7326 | u8 *data = (u8 *) & measure_report; | |
7327 | unsigned long flags; | |
7328 | ||
7329 | spin_lock_irqsave(&priv->lock, flags); | |
7330 | if (!(priv->measurement_status & MEASUREMENT_READY)) { | |
7331 | spin_unlock_irqrestore(&priv->lock, flags); | |
7332 | return 0; | |
7333 | } | |
7334 | memcpy(&measure_report, &priv->measure_report, size); | |
7335 | priv->measurement_status = 0; | |
7336 | spin_unlock_irqrestore(&priv->lock, flags); | |
7337 | ||
7338 | while (size && (PAGE_SIZE - len)) { | |
7339 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
7340 | PAGE_SIZE - len, 1); | |
7341 | len = strlen(buf); | |
7342 | if (PAGE_SIZE - len) | |
7343 | buf[len++] = '\n'; | |
7344 | ||
7345 | ofs += 16; | |
7346 | size -= min(size, 16U); | |
7347 | } | |
7348 | ||
7349 | return len; | |
7350 | } | |
7351 | ||
7352 | static ssize_t store_measurement(struct device *d, | |
7353 | struct device_attribute *attr, | |
7354 | const char *buf, size_t count) | |
7355 | { | |
c79dd5b5 | 7356 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7357 | struct ieee80211_measurement_params params = { |
7358 | .channel = le16_to_cpu(priv->active_rxon.channel), | |
7359 | .start_time = cpu_to_le64(priv->last_tsf), | |
7360 | .duration = cpu_to_le16(1), | |
7361 | }; | |
7362 | u8 type = IWL_MEASURE_BASIC; | |
7363 | u8 buffer[32]; | |
7364 | u8 channel; | |
7365 | ||
7366 | if (count) { | |
7367 | char *p = buffer; | |
7368 | strncpy(buffer, buf, min(sizeof(buffer), count)); | |
7369 | channel = simple_strtoul(p, NULL, 0); | |
7370 | if (channel) | |
7371 | params.channel = channel; | |
7372 | ||
7373 | p = buffer; | |
7374 | while (*p && *p != ' ') | |
7375 | p++; | |
7376 | if (*p) | |
7377 | type = simple_strtoul(p + 1, NULL, 0); | |
7378 | } | |
7379 | ||
7380 | IWL_DEBUG_INFO("Invoking measurement of type %d on " | |
7381 | "channel %d (for '%s')\n", type, params.channel, buf); | |
bb8c093b | 7382 | iwl4965_get_measurement(priv, ¶ms, type); |
b481de9c ZY |
7383 | |
7384 | return count; | |
7385 | } | |
7386 | ||
7387 | static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR, | |
7388 | show_measurement, store_measurement); | |
c8b0e6e1 | 7389 | #endif /* CONFIG_IWL4965_SPECTRUM_MEASUREMENT */ |
b481de9c ZY |
7390 | |
7391 | static ssize_t store_retry_rate(struct device *d, | |
7392 | struct device_attribute *attr, | |
7393 | const char *buf, size_t count) | |
7394 | { | |
c79dd5b5 | 7395 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7396 | |
7397 | priv->retry_rate = simple_strtoul(buf, NULL, 0); | |
7398 | if (priv->retry_rate <= 0) | |
7399 | priv->retry_rate = 1; | |
7400 | ||
7401 | return count; | |
7402 | } | |
7403 | ||
7404 | static ssize_t show_retry_rate(struct device *d, | |
7405 | struct device_attribute *attr, char *buf) | |
7406 | { | |
c79dd5b5 | 7407 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7408 | return sprintf(buf, "%d", priv->retry_rate); |
7409 | } | |
7410 | ||
7411 | static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate, | |
7412 | store_retry_rate); | |
7413 | ||
7414 | static ssize_t store_power_level(struct device *d, | |
7415 | struct device_attribute *attr, | |
7416 | const char *buf, size_t count) | |
7417 | { | |
c79dd5b5 | 7418 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7419 | int rc; |
7420 | int mode; | |
7421 | ||
7422 | mode = simple_strtoul(buf, NULL, 0); | |
7423 | mutex_lock(&priv->mutex); | |
7424 | ||
fee1247a | 7425 | if (!iwl_is_ready(priv)) { |
b481de9c ZY |
7426 | rc = -EAGAIN; |
7427 | goto out; | |
7428 | } | |
7429 | ||
7430 | if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC)) | |
7431 | mode = IWL_POWER_AC; | |
7432 | else | |
7433 | mode |= IWL_POWER_ENABLED; | |
7434 | ||
7435 | if (mode != priv->power_mode) { | |
bb8c093b | 7436 | rc = iwl4965_send_power_mode(priv, IWL_POWER_LEVEL(mode)); |
b481de9c ZY |
7437 | if (rc) { |
7438 | IWL_DEBUG_MAC80211("failed setting power mode.\n"); | |
7439 | goto out; | |
7440 | } | |
7441 | priv->power_mode = mode; | |
7442 | } | |
7443 | ||
7444 | rc = count; | |
7445 | ||
7446 | out: | |
7447 | mutex_unlock(&priv->mutex); | |
7448 | return rc; | |
7449 | } | |
7450 | ||
7451 | #define MAX_WX_STRING 80 | |
7452 | ||
7453 | /* Values are in microsecond */ | |
7454 | static const s32 timeout_duration[] = { | |
7455 | 350000, | |
7456 | 250000, | |
7457 | 75000, | |
7458 | 37000, | |
7459 | 25000, | |
7460 | }; | |
7461 | static const s32 period_duration[] = { | |
7462 | 400000, | |
7463 | 700000, | |
7464 | 1000000, | |
7465 | 1000000, | |
7466 | 1000000 | |
7467 | }; | |
7468 | ||
7469 | static ssize_t show_power_level(struct device *d, | |
7470 | struct device_attribute *attr, char *buf) | |
7471 | { | |
c79dd5b5 | 7472 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7473 | int level = IWL_POWER_LEVEL(priv->power_mode); |
7474 | char *p = buf; | |
7475 | ||
7476 | p += sprintf(p, "%d ", level); | |
7477 | switch (level) { | |
7478 | case IWL_POWER_MODE_CAM: | |
7479 | case IWL_POWER_AC: | |
7480 | p += sprintf(p, "(AC)"); | |
7481 | break; | |
7482 | case IWL_POWER_BATTERY: | |
7483 | p += sprintf(p, "(BATTERY)"); | |
7484 | break; | |
7485 | default: | |
7486 | p += sprintf(p, | |
7487 | "(Timeout %dms, Period %dms)", | |
7488 | timeout_duration[level - 1] / 1000, | |
7489 | period_duration[level - 1] / 1000); | |
7490 | } | |
7491 | ||
7492 | if (!(priv->power_mode & IWL_POWER_ENABLED)) | |
7493 | p += sprintf(p, " OFF\n"); | |
7494 | else | |
7495 | p += sprintf(p, " \n"); | |
7496 | ||
7497 | return (p - buf + 1); | |
7498 | ||
7499 | } | |
7500 | ||
7501 | static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level, | |
7502 | store_power_level); | |
7503 | ||
7504 | static ssize_t show_channels(struct device *d, | |
7505 | struct device_attribute *attr, char *buf) | |
7506 | { | |
8318d78a JB |
7507 | /* all this shit doesn't belong into sysfs anyway */ |
7508 | return 0; | |
b481de9c ZY |
7509 | } |
7510 | ||
7511 | static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL); | |
7512 | ||
7513 | static ssize_t show_statistics(struct device *d, | |
7514 | struct device_attribute *attr, char *buf) | |
7515 | { | |
c79dd5b5 | 7516 | struct iwl_priv *priv = dev_get_drvdata(d); |
bb8c093b | 7517 | u32 size = sizeof(struct iwl4965_notif_statistics); |
b481de9c ZY |
7518 | u32 len = 0, ofs = 0; |
7519 | u8 *data = (u8 *) & priv->statistics; | |
7520 | int rc = 0; | |
7521 | ||
fee1247a | 7522 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
7523 | return -EAGAIN; |
7524 | ||
7525 | mutex_lock(&priv->mutex); | |
49ea8596 | 7526 | rc = iwl_send_statistics_request(priv, 0); |
b481de9c ZY |
7527 | mutex_unlock(&priv->mutex); |
7528 | ||
7529 | if (rc) { | |
7530 | len = sprintf(buf, | |
7531 | "Error sending statistics request: 0x%08X\n", rc); | |
7532 | return len; | |
7533 | } | |
7534 | ||
7535 | while (size && (PAGE_SIZE - len)) { | |
7536 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
7537 | PAGE_SIZE - len, 1); | |
7538 | len = strlen(buf); | |
7539 | if (PAGE_SIZE - len) | |
7540 | buf[len++] = '\n'; | |
7541 | ||
7542 | ofs += 16; | |
7543 | size -= min(size, 16U); | |
7544 | } | |
7545 | ||
7546 | return len; | |
7547 | } | |
7548 | ||
7549 | static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL); | |
7550 | ||
7551 | static ssize_t show_antenna(struct device *d, | |
7552 | struct device_attribute *attr, char *buf) | |
7553 | { | |
c79dd5b5 | 7554 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 7555 | |
fee1247a | 7556 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
7557 | return -EAGAIN; |
7558 | ||
7559 | return sprintf(buf, "%d\n", priv->antenna); | |
7560 | } | |
7561 | ||
7562 | static ssize_t store_antenna(struct device *d, | |
7563 | struct device_attribute *attr, | |
7564 | const char *buf, size_t count) | |
7565 | { | |
7566 | int ant; | |
c79dd5b5 | 7567 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7568 | |
7569 | if (count == 0) | |
7570 | return 0; | |
7571 | ||
7572 | if (sscanf(buf, "%1i", &ant) != 1) { | |
7573 | IWL_DEBUG_INFO("not in hex or decimal form.\n"); | |
7574 | return count; | |
7575 | } | |
7576 | ||
7577 | if ((ant >= 0) && (ant <= 2)) { | |
7578 | IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant); | |
bb8c093b | 7579 | priv->antenna = (enum iwl4965_antenna)ant; |
b481de9c ZY |
7580 | } else |
7581 | IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant); | |
7582 | ||
7583 | ||
7584 | return count; | |
7585 | } | |
7586 | ||
7587 | static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna); | |
7588 | ||
7589 | static ssize_t show_status(struct device *d, | |
7590 | struct device_attribute *attr, char *buf) | |
7591 | { | |
c79dd5b5 | 7592 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
fee1247a | 7593 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
7594 | return -EAGAIN; |
7595 | return sprintf(buf, "0x%08x\n", (int)priv->status); | |
7596 | } | |
7597 | ||
7598 | static DEVICE_ATTR(status, S_IRUGO, show_status, NULL); | |
7599 | ||
7600 | static ssize_t dump_error_log(struct device *d, | |
7601 | struct device_attribute *attr, | |
7602 | const char *buf, size_t count) | |
7603 | { | |
7604 | char *p = (char *)buf; | |
7605 | ||
7606 | if (p[0] == '1') | |
c79dd5b5 | 7607 | iwl4965_dump_nic_error_log((struct iwl_priv *)d->driver_data); |
b481de9c ZY |
7608 | |
7609 | return strnlen(buf, count); | |
7610 | } | |
7611 | ||
7612 | static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log); | |
7613 | ||
7614 | static ssize_t dump_event_log(struct device *d, | |
7615 | struct device_attribute *attr, | |
7616 | const char *buf, size_t count) | |
7617 | { | |
7618 | char *p = (char *)buf; | |
7619 | ||
7620 | if (p[0] == '1') | |
c79dd5b5 | 7621 | iwl4965_dump_nic_event_log((struct iwl_priv *)d->driver_data); |
b481de9c ZY |
7622 | |
7623 | return strnlen(buf, count); | |
7624 | } | |
7625 | ||
7626 | static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log); | |
7627 | ||
7628 | /***************************************************************************** | |
7629 | * | |
7630 | * driver setup and teardown | |
7631 | * | |
7632 | *****************************************************************************/ | |
7633 | ||
c79dd5b5 | 7634 | static void iwl4965_setup_deferred_work(struct iwl_priv *priv) |
b481de9c ZY |
7635 | { |
7636 | priv->workqueue = create_workqueue(DRV_NAME); | |
7637 | ||
7638 | init_waitqueue_head(&priv->wait_command_queue); | |
7639 | ||
bb8c093b CH |
7640 | INIT_WORK(&priv->up, iwl4965_bg_up); |
7641 | INIT_WORK(&priv->restart, iwl4965_bg_restart); | |
7642 | INIT_WORK(&priv->rx_replenish, iwl4965_bg_rx_replenish); | |
7643 | INIT_WORK(&priv->scan_completed, iwl4965_bg_scan_completed); | |
7644 | INIT_WORK(&priv->request_scan, iwl4965_bg_request_scan); | |
7645 | INIT_WORK(&priv->abort_scan, iwl4965_bg_abort_scan); | |
7646 | INIT_WORK(&priv->rf_kill, iwl4965_bg_rf_kill); | |
7647 | INIT_WORK(&priv->beacon_update, iwl4965_bg_beacon_update); | |
7648 | INIT_DELAYED_WORK(&priv->post_associate, iwl4965_bg_post_associate); | |
7649 | INIT_DELAYED_WORK(&priv->init_alive_start, iwl4965_bg_init_alive_start); | |
7650 | INIT_DELAYED_WORK(&priv->alive_start, iwl4965_bg_alive_start); | |
7651 | INIT_DELAYED_WORK(&priv->scan_check, iwl4965_bg_scan_check); | |
7652 | ||
7653 | iwl4965_hw_setup_deferred_work(priv); | |
b481de9c ZY |
7654 | |
7655 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | |
bb8c093b | 7656 | iwl4965_irq_tasklet, (unsigned long)priv); |
b481de9c ZY |
7657 | } |
7658 | ||
c79dd5b5 | 7659 | static void iwl4965_cancel_deferred_work(struct iwl_priv *priv) |
b481de9c | 7660 | { |
bb8c093b | 7661 | iwl4965_hw_cancel_deferred_work(priv); |
b481de9c | 7662 | |
3ae6a054 | 7663 | cancel_delayed_work_sync(&priv->init_alive_start); |
b481de9c ZY |
7664 | cancel_delayed_work(&priv->scan_check); |
7665 | cancel_delayed_work(&priv->alive_start); | |
7666 | cancel_delayed_work(&priv->post_associate); | |
7667 | cancel_work_sync(&priv->beacon_update); | |
7668 | } | |
7669 | ||
bb8c093b | 7670 | static struct attribute *iwl4965_sysfs_entries[] = { |
b481de9c ZY |
7671 | &dev_attr_antenna.attr, |
7672 | &dev_attr_channels.attr, | |
7673 | &dev_attr_dump_errors.attr, | |
7674 | &dev_attr_dump_events.attr, | |
7675 | &dev_attr_flags.attr, | |
7676 | &dev_attr_filter_flags.attr, | |
c8b0e6e1 | 7677 | #ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT |
b481de9c ZY |
7678 | &dev_attr_measurement.attr, |
7679 | #endif | |
7680 | &dev_attr_power_level.attr, | |
7681 | &dev_attr_retry_rate.attr, | |
b481de9c ZY |
7682 | &dev_attr_rs_window.attr, |
7683 | &dev_attr_statistics.attr, | |
7684 | &dev_attr_status.attr, | |
7685 | &dev_attr_temperature.attr, | |
b481de9c ZY |
7686 | &dev_attr_tx_power.attr, |
7687 | ||
7688 | NULL | |
7689 | }; | |
7690 | ||
bb8c093b | 7691 | static struct attribute_group iwl4965_attribute_group = { |
b481de9c | 7692 | .name = NULL, /* put in device directory */ |
bb8c093b | 7693 | .attrs = iwl4965_sysfs_entries, |
b481de9c ZY |
7694 | }; |
7695 | ||
bb8c093b CH |
7696 | static struct ieee80211_ops iwl4965_hw_ops = { |
7697 | .tx = iwl4965_mac_tx, | |
7698 | .start = iwl4965_mac_start, | |
7699 | .stop = iwl4965_mac_stop, | |
7700 | .add_interface = iwl4965_mac_add_interface, | |
7701 | .remove_interface = iwl4965_mac_remove_interface, | |
7702 | .config = iwl4965_mac_config, | |
7703 | .config_interface = iwl4965_mac_config_interface, | |
7704 | .configure_filter = iwl4965_configure_filter, | |
7705 | .set_key = iwl4965_mac_set_key, | |
ab885f8c | 7706 | .update_tkip_key = iwl4965_mac_update_tkip_key, |
bb8c093b CH |
7707 | .get_stats = iwl4965_mac_get_stats, |
7708 | .get_tx_stats = iwl4965_mac_get_tx_stats, | |
7709 | .conf_tx = iwl4965_mac_conf_tx, | |
7710 | .get_tsf = iwl4965_mac_get_tsf, | |
7711 | .reset_tsf = iwl4965_mac_reset_tsf, | |
7712 | .beacon_update = iwl4965_mac_beacon_update, | |
471b3efd | 7713 | .bss_info_changed = iwl4965_bss_info_changed, |
c8b0e6e1 | 7714 | #ifdef CONFIG_IWL4965_HT |
9ab46173 | 7715 | .ampdu_action = iwl4965_mac_ampdu_action, |
c8b0e6e1 | 7716 | #endif /* CONFIG_IWL4965_HT */ |
bb8c093b | 7717 | .hw_scan = iwl4965_mac_hw_scan |
b481de9c ZY |
7718 | }; |
7719 | ||
bb8c093b | 7720 | static int iwl4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
b481de9c ZY |
7721 | { |
7722 | int err = 0; | |
c79dd5b5 | 7723 | struct iwl_priv *priv; |
b481de9c | 7724 | struct ieee80211_hw *hw; |
82b9a121 | 7725 | struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data); |
0359facc | 7726 | unsigned long flags; |
5a66926a | 7727 | DECLARE_MAC_BUF(mac); |
b481de9c | 7728 | |
316c30d9 AK |
7729 | /************************ |
7730 | * 1. Allocating HW data | |
7731 | ************************/ | |
7732 | ||
6440adb5 CB |
7733 | /* Disabling hardware scan means that mac80211 will perform scans |
7734 | * "the hard way", rather than using device's scan. */ | |
1ea87396 | 7735 | if (cfg->mod_params->disable_hw_scan) { |
b481de9c | 7736 | IWL_DEBUG_INFO("Disabling hw_scan\n"); |
bb8c093b | 7737 | iwl4965_hw_ops.hw_scan = NULL; |
b481de9c ZY |
7738 | } |
7739 | ||
1d0a082d AK |
7740 | hw = iwl_alloc_all(cfg, &iwl4965_hw_ops); |
7741 | if (!hw) { | |
b481de9c ZY |
7742 | err = -ENOMEM; |
7743 | goto out; | |
7744 | } | |
1d0a082d AK |
7745 | priv = hw->priv; |
7746 | /* At this point both hw and priv are allocated. */ | |
7747 | ||
b481de9c ZY |
7748 | SET_IEEE80211_DEV(hw, &pdev->dev); |
7749 | ||
7750 | IWL_DEBUG_INFO("*** LOAD DRIVER ***\n"); | |
82b9a121 | 7751 | priv->cfg = cfg; |
b481de9c | 7752 | priv->pci_dev = pdev; |
316c30d9 | 7753 | |
0a6857e7 | 7754 | #ifdef CONFIG_IWLWIFI_DEBUG |
1ea87396 | 7755 | iwl_debug_level = priv->cfg->mod_params->debug; |
b481de9c ZY |
7756 | atomic_set(&priv->restrict_refcnt, 0); |
7757 | #endif | |
b481de9c | 7758 | |
316c30d9 AK |
7759 | /************************** |
7760 | * 2. Initializing PCI bus | |
7761 | **************************/ | |
7762 | if (pci_enable_device(pdev)) { | |
7763 | err = -ENODEV; | |
7764 | goto out_ieee80211_free_hw; | |
7765 | } | |
7766 | ||
7767 | pci_set_master(pdev); | |
7768 | ||
7769 | err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
7770 | if (!err) | |
7771 | err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
7772 | if (err) { | |
7773 | printk(KERN_WARNING DRV_NAME | |
7774 | ": No suitable DMA available.\n"); | |
7775 | goto out_pci_disable_device; | |
7776 | } | |
7777 | ||
7778 | err = pci_request_regions(pdev, DRV_NAME); | |
7779 | if (err) | |
7780 | goto out_pci_disable_device; | |
7781 | ||
7782 | pci_set_drvdata(pdev, priv); | |
7783 | ||
7784 | /* We disable the RETRY_TIMEOUT register (0x41) to keep | |
7785 | * PCI Tx retries from interfering with C3 CPU state */ | |
7786 | pci_write_config_byte(pdev, 0x41, 0x00); | |
7787 | ||
7788 | /*********************** | |
7789 | * 3. Read REV register | |
7790 | ***********************/ | |
7791 | priv->hw_base = pci_iomap(pdev, 0, 0); | |
7792 | if (!priv->hw_base) { | |
7793 | err = -ENODEV; | |
7794 | goto out_pci_release_regions; | |
7795 | } | |
7796 | ||
7797 | IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n", | |
7798 | (unsigned long long) pci_resource_len(pdev, 0)); | |
7799 | IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base); | |
7800 | ||
7801 | printk(KERN_INFO DRV_NAME | |
7802 | ": Detected Intel Wireless WiFi Link %s\n", priv->cfg->name); | |
7803 | ||
7804 | /***************** | |
7805 | * 4. Read EEPROM | |
7806 | *****************/ | |
7807 | /* nic init */ | |
3395f6e9 | 7808 | iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, |
316c30d9 AK |
7809 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); |
7810 | ||
3395f6e9 TW |
7811 | iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); |
7812 | err = iwl_poll_bit(priv, CSR_GP_CNTRL, | |
316c30d9 AK |
7813 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, |
7814 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
7815 | if (err < 0) { | |
7816 | IWL_DEBUG_INFO("Failed to init the card\n"); | |
7817 | goto out_iounmap; | |
7818 | } | |
7819 | /* Read the EEPROM */ | |
7820 | err = iwl_eeprom_init(priv); | |
7821 | if (err) { | |
7822 | IWL_ERROR("Unable to init EEPROM\n"); | |
7823 | goto out_iounmap; | |
7824 | } | |
7825 | /* MAC Address location in EEPROM same for 3945/4965 */ | |
7826 | iwl_eeprom_get_mac(priv, priv->mac_addr); | |
7827 | IWL_DEBUG_INFO("MAC address: %s\n", print_mac(mac, priv->mac_addr)); | |
7828 | SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr); | |
7829 | ||
7830 | /************************ | |
7831 | * 5. Setup HW constants | |
7832 | ************************/ | |
7833 | /* Device-specific setup */ | |
7834 | if (iwl4965_hw_set_hw_setting(priv)) { | |
7835 | IWL_ERROR("failed to set hw settings\n"); | |
7836 | goto out_iounmap; | |
7837 | } | |
7838 | ||
7839 | /******************* | |
7840 | * 6. Setup hw/priv | |
7841 | *******************/ | |
b481de9c | 7842 | |
bf85ea4f AK |
7843 | err = iwl_setup(priv); |
7844 | if (err) | |
316c30d9 | 7845 | goto out_unset_hw_settings; |
bf85ea4f | 7846 | /* At this point both hw and priv are initialized. */ |
316c30d9 AK |
7847 | |
7848 | /********************************** | |
7849 | * 7. Initialize module parameters | |
7850 | **********************************/ | |
7851 | ||
7852 | /* Disable radio (SW RF KILL) via parameter when loading driver */ | |
1ea87396 | 7853 | if (priv->cfg->mod_params->disable) { |
316c30d9 AK |
7854 | set_bit(STATUS_RF_KILL_SW, &priv->status); |
7855 | IWL_DEBUG_INFO("Radio disabled.\n"); | |
7856 | } | |
7857 | ||
1ea87396 | 7858 | if (priv->cfg->mod_params->enable_qos) |
316c30d9 AK |
7859 | priv->qos_data.qos_enable = 1; |
7860 | ||
7861 | /******************** | |
7862 | * 8. Setup services | |
7863 | ********************/ | |
0359facc | 7864 | spin_lock_irqsave(&priv->lock, flags); |
316c30d9 | 7865 | iwl4965_disable_interrupts(priv); |
0359facc | 7866 | spin_unlock_irqrestore(&priv->lock, flags); |
316c30d9 AK |
7867 | |
7868 | err = sysfs_create_group(&pdev->dev.kobj, &iwl4965_attribute_group); | |
7869 | if (err) { | |
7870 | IWL_ERROR("failed to create sysfs device attributes\n"); | |
bf85ea4f | 7871 | goto out_unset_hw_settings; |
316c30d9 AK |
7872 | } |
7873 | ||
7874 | err = iwl_dbgfs_register(priv, DRV_NAME); | |
7875 | if (err) { | |
7876 | IWL_ERROR("failed to create debugfs files\n"); | |
7877 | goto out_remove_sysfs; | |
7878 | } | |
7879 | ||
7880 | iwl4965_setup_deferred_work(priv); | |
7881 | iwl4965_setup_rx_handlers(priv); | |
7882 | ||
7883 | /******************** | |
7884 | * 9. Conclude | |
7885 | ********************/ | |
5a66926a ZY |
7886 | pci_save_state(pdev); |
7887 | pci_disable_device(pdev); | |
b481de9c | 7888 | |
c8381fdc MA |
7889 | /* notify iwlcore to init */ |
7890 | iwlcore_low_level_notify(priv, IWLCORE_INIT_EVT); | |
b481de9c ZY |
7891 | return 0; |
7892 | ||
316c30d9 AK |
7893 | out_remove_sysfs: |
7894 | sysfs_remove_group(&pdev->dev.kobj, &iwl4965_attribute_group); | |
316c30d9 | 7895 | out_unset_hw_settings: |
bb8c093b | 7896 | iwl4965_unset_hw_setting(priv); |
b481de9c ZY |
7897 | out_iounmap: |
7898 | pci_iounmap(pdev, priv->hw_base); | |
7899 | out_pci_release_regions: | |
7900 | pci_release_regions(pdev); | |
316c30d9 | 7901 | pci_set_drvdata(pdev, NULL); |
b481de9c ZY |
7902 | out_pci_disable_device: |
7903 | pci_disable_device(pdev); | |
b481de9c ZY |
7904 | out_ieee80211_free_hw: |
7905 | ieee80211_free_hw(priv->hw); | |
7906 | out: | |
7907 | return err; | |
7908 | } | |
7909 | ||
c83dbf68 | 7910 | static void __devexit iwl4965_pci_remove(struct pci_dev *pdev) |
b481de9c | 7911 | { |
c79dd5b5 | 7912 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
b481de9c ZY |
7913 | struct list_head *p, *q; |
7914 | int i; | |
0359facc | 7915 | unsigned long flags; |
b481de9c ZY |
7916 | |
7917 | if (!priv) | |
7918 | return; | |
7919 | ||
7920 | IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n"); | |
7921 | ||
c4f55232 RR |
7922 | if (priv->mac80211_registered) { |
7923 | ieee80211_unregister_hw(priv->hw); | |
7924 | priv->mac80211_registered = 0; | |
7925 | } | |
7926 | ||
b481de9c | 7927 | set_bit(STATUS_EXIT_PENDING, &priv->status); |
b24d22b1 | 7928 | |
bb8c093b | 7929 | iwl4965_down(priv); |
b481de9c | 7930 | |
0359facc MA |
7931 | /* make sure we flush any pending irq or |
7932 | * tasklet for the driver | |
7933 | */ | |
7934 | spin_lock_irqsave(&priv->lock, flags); | |
7935 | iwl4965_disable_interrupts(priv); | |
7936 | spin_unlock_irqrestore(&priv->lock, flags); | |
7937 | ||
7938 | iwl_synchronize_irq(priv); | |
7939 | ||
b481de9c ZY |
7940 | /* Free MAC hash list for ADHOC */ |
7941 | for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) { | |
7942 | list_for_each_safe(p, q, &priv->ibss_mac_hash[i]) { | |
7943 | list_del(p); | |
bb8c093b | 7944 | kfree(list_entry(p, struct iwl4965_ibss_seq, list)); |
b481de9c ZY |
7945 | } |
7946 | } | |
7947 | ||
c8381fdc | 7948 | iwlcore_low_level_notify(priv, IWLCORE_REMOVE_EVT); |
712b6cf5 | 7949 | iwl_dbgfs_unregister(priv); |
bb8c093b | 7950 | sysfs_remove_group(&pdev->dev.kobj, &iwl4965_attribute_group); |
b481de9c | 7951 | |
bb8c093b | 7952 | iwl4965_dealloc_ucode_pci(priv); |
b481de9c ZY |
7953 | |
7954 | if (priv->rxq.bd) | |
bb8c093b CH |
7955 | iwl4965_rx_queue_free(priv, &priv->rxq); |
7956 | iwl4965_hw_txq_ctx_free(priv); | |
b481de9c | 7957 | |
bb8c093b | 7958 | iwl4965_unset_hw_setting(priv); |
bf85ea4f | 7959 | iwlcore_clear_stations_table(priv); |
b481de9c | 7960 | |
b481de9c | 7961 | |
948c171c MA |
7962 | /*netif_stop_queue(dev); */ |
7963 | flush_workqueue(priv->workqueue); | |
7964 | ||
bb8c093b | 7965 | /* ieee80211_unregister_hw calls iwl4965_mac_stop, which flushes |
b481de9c ZY |
7966 | * priv->workqueue... so we can't take down the workqueue |
7967 | * until now... */ | |
7968 | destroy_workqueue(priv->workqueue); | |
7969 | priv->workqueue = NULL; | |
7970 | ||
b481de9c ZY |
7971 | pci_iounmap(pdev, priv->hw_base); |
7972 | pci_release_regions(pdev); | |
7973 | pci_disable_device(pdev); | |
7974 | pci_set_drvdata(pdev, NULL); | |
7975 | ||
bf85ea4f | 7976 | iwl_free_channel_map(priv); |
849e0dce | 7977 | iwl4965_free_geos(priv); |
b481de9c ZY |
7978 | |
7979 | if (priv->ibss_beacon) | |
7980 | dev_kfree_skb(priv->ibss_beacon); | |
7981 | ||
7982 | ieee80211_free_hw(priv->hw); | |
7983 | } | |
7984 | ||
7985 | #ifdef CONFIG_PM | |
7986 | ||
bb8c093b | 7987 | static int iwl4965_pci_suspend(struct pci_dev *pdev, pm_message_t state) |
b481de9c | 7988 | { |
c79dd5b5 | 7989 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
b481de9c | 7990 | |
e655b9f0 ZY |
7991 | if (priv->is_open) { |
7992 | set_bit(STATUS_IN_SUSPEND, &priv->status); | |
7993 | iwl4965_mac_stop(priv->hw); | |
7994 | priv->is_open = 1; | |
7995 | } | |
b481de9c | 7996 | |
b481de9c ZY |
7997 | pci_set_power_state(pdev, PCI_D3hot); |
7998 | ||
b481de9c ZY |
7999 | return 0; |
8000 | } | |
8001 | ||
bb8c093b | 8002 | static int iwl4965_pci_resume(struct pci_dev *pdev) |
b481de9c | 8003 | { |
c79dd5b5 | 8004 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
b481de9c | 8005 | |
b481de9c | 8006 | pci_set_power_state(pdev, PCI_D0); |
b481de9c | 8007 | |
e655b9f0 ZY |
8008 | if (priv->is_open) |
8009 | iwl4965_mac_start(priv->hw); | |
b481de9c | 8010 | |
e655b9f0 | 8011 | clear_bit(STATUS_IN_SUSPEND, &priv->status); |
b481de9c ZY |
8012 | return 0; |
8013 | } | |
8014 | ||
8015 | #endif /* CONFIG_PM */ | |
8016 | ||
8017 | /***************************************************************************** | |
8018 | * | |
8019 | * driver and module entry point | |
8020 | * | |
8021 | *****************************************************************************/ | |
8022 | ||
bb8c093b | 8023 | static struct pci_driver iwl4965_driver = { |
b481de9c | 8024 | .name = DRV_NAME, |
bb8c093b CH |
8025 | .id_table = iwl4965_hw_card_ids, |
8026 | .probe = iwl4965_pci_probe, | |
8027 | .remove = __devexit_p(iwl4965_pci_remove), | |
b481de9c | 8028 | #ifdef CONFIG_PM |
bb8c093b CH |
8029 | .suspend = iwl4965_pci_suspend, |
8030 | .resume = iwl4965_pci_resume, | |
b481de9c ZY |
8031 | #endif |
8032 | }; | |
8033 | ||
bb8c093b | 8034 | static int __init iwl4965_init(void) |
b481de9c ZY |
8035 | { |
8036 | ||
8037 | int ret; | |
8038 | printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n"); | |
8039 | printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n"); | |
897e1cf2 RC |
8040 | |
8041 | ret = iwl4965_rate_control_register(); | |
8042 | if (ret) { | |
8043 | IWL_ERROR("Unable to register rate control algorithm: %d\n", ret); | |
8044 | return ret; | |
8045 | } | |
8046 | ||
bb8c093b | 8047 | ret = pci_register_driver(&iwl4965_driver); |
b481de9c ZY |
8048 | if (ret) { |
8049 | IWL_ERROR("Unable to initialize PCI module\n"); | |
897e1cf2 | 8050 | goto error_register; |
b481de9c | 8051 | } |
0a6857e7 | 8052 | #ifdef CONFIG_IWLWIFI_DEBUG |
bb8c093b | 8053 | ret = driver_create_file(&iwl4965_driver.driver, &driver_attr_debug_level); |
b481de9c ZY |
8054 | if (ret) { |
8055 | IWL_ERROR("Unable to create driver sysfs file\n"); | |
897e1cf2 | 8056 | goto error_debug; |
b481de9c ZY |
8057 | } |
8058 | #endif | |
8059 | ||
8060 | return ret; | |
897e1cf2 RC |
8061 | |
8062 | #ifdef CONFIG_IWLWIFI_DEBUG | |
8063 | error_debug: | |
8064 | pci_unregister_driver(&iwl4965_driver); | |
8065 | #endif | |
8066 | error_register: | |
8067 | iwl4965_rate_control_unregister(); | |
8068 | return ret; | |
b481de9c ZY |
8069 | } |
8070 | ||
bb8c093b | 8071 | static void __exit iwl4965_exit(void) |
b481de9c | 8072 | { |
0a6857e7 | 8073 | #ifdef CONFIG_IWLWIFI_DEBUG |
bb8c093b | 8074 | driver_remove_file(&iwl4965_driver.driver, &driver_attr_debug_level); |
b481de9c | 8075 | #endif |
bb8c093b | 8076 | pci_unregister_driver(&iwl4965_driver); |
897e1cf2 | 8077 | iwl4965_rate_control_unregister(); |
b481de9c ZY |
8078 | } |
8079 | ||
bb8c093b CH |
8080 | module_exit(iwl4965_exit); |
8081 | module_init(iwl4965_init); |