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iwlwifi: cleanup usage of inline functions
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl4965-base.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2007 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
b481de9c
ZY		 30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/version.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/dma-mapping.h>
36#include <linux/delay.h>
37#include <linux/skbuff.h>
38#include <linux/netdevice.h>
39#include <linux/wireless.h>
40#include <linux/firmware.h>
b481de9c
ZY		 41#include <linux/etherdevice.h>
42#include <linux/if_arp.h>
43
b481de9c
ZY		 44#include <net/mac80211.h>
45
46#include <asm/div64.h>
47
b481de9c
ZY		 48#include "iwl-4965.h"
49#include "iwl-helpers.h"
50
c8b0e6e1 51#ifdef CONFIG_IWL4965_DEBUG
bb8c093b 52u32 iwl4965_debug_level;
b481de9c
ZY		 53#endif
54
bb8c093b
CH		 55static int iwl4965_tx_queue_update_write_ptr(struct iwl4965_priv *priv,
56 struct iwl4965_tx_queue *txq);
416e1438 57
b481de9c
ZY		 58/******************************************************************************
59 *
60 * module boiler plate
61 *
62 ******************************************************************************/
63
64/* module parameters */
6440adb5
CB		 65static int iwl4965_param_disable_hw_scan; /* def: 0 = use 4965's h/w scan */
66static int iwl4965_param_debug; /* def: 0 = minimal debug log messages */
9fbab516
BC		 67static int iwl4965_param_disable; /* def: enable radio */
68static int iwl4965_param_antenna; /* def: 0 = both antennas (use diversity) */
69int iwl4965_param_hwcrypto; /* def: using software encryption */
6440adb5
CB		 70static int iwl4965_param_qos_enable = 1; /* def: 1 = use quality of service */
71int iwl4965_param_queues_num = IWL_MAX_NUM_QUEUES; /* def: 16 Tx queues */
9ee1ba47 72int iwl4965_param_amsdu_size_8K; /* def: enable 8K amsdu size */
b481de9c
ZY		 73
74/*
75 * module name, copyright, version, etc.
76 * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
77 */
78
79#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link 4965AGN driver for Linux"
80
c8b0e6e1 81#ifdef CONFIG_IWL4965_DEBUG
b481de9c
ZY		 82#define VD "d"
83#else
84#define VD
85#endif
86
c8b0e6e1 87#ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT
b481de9c
ZY		 88#define VS "s"
89#else
90#define VS
91#endif
92
71972664 93#define IWLWIFI_VERSION "1.2.23k" VD VS
b481de9c
ZY		 94#define DRV_COPYRIGHT "Copyright(c) 2003-2007 Intel Corporation"
95#define DRV_VERSION IWLWIFI_VERSION
96
97/* Change firmware file name, using "-" and incrementing number,
98 * *only* when uCode interface or architecture changes so that it
99 * is not compatible with earlier drivers.
100 * This number will also appear in << 8 position of 1st dword of uCode file */
101#define IWL4965_UCODE_API "-1"
102
103MODULE_DESCRIPTION(DRV_DESCRIPTION);
104MODULE_VERSION(DRV_VERSION);
105MODULE_AUTHOR(DRV_COPYRIGHT);
106MODULE_LICENSE("GPL");
107
108__le16 *ieee80211_get_qos_ctrl(struct ieee80211_hdr *hdr)
109{
110 u16 fc = le16_to_cpu(hdr->frame_control);
111 int hdr_len = ieee80211_get_hdrlen(fc);
112
113 if ((fc & 0x00cc) == (IEEE80211_STYPE_QOS_DATA | IEEE80211_FTYPE_DATA))
114 return (__le16 *) ((u8 *) hdr + hdr_len - QOS_CONTROL_LEN);
115 return NULL;
116}
117
bb8c093b
CH		 118static const struct ieee80211_hw_mode *iwl4965_get_hw_mode(
119 struct iwl4965_priv *priv, int mode)
b481de9c
ZY		 120{
121 int i;
122
123 for (i = 0; i < 3; i++)
124 if (priv->modes[i].mode == mode)
125 return &priv->modes[i];
126
127 return NULL;
128}
129
bb8c093b 130static int iwl4965_is_empty_essid(const char *essid, int essid_len)
b481de9c
ZY		 131{
132 /* Single white space is for Linksys APs */
133 if (essid_len == 1 && essid[0] == ' ')
134 return 1;
135
136 /* Otherwise, if the entire essid is 0, we assume it is hidden */
137 while (essid_len) {
138 essid_len--;
139 if (essid[essid_len] != '\0')
140 return 0;
141 }
142
143 return 1;
144}
145
bb8c093b 146static const char *iwl4965_escape_essid(const char *essid, u8 essid_len)
b481de9c
ZY		 147{
148 static char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
149 const char *s = essid;
150 char *d = escaped;
151
bb8c093b 152 if (iwl4965_is_empty_essid(essid, essid_len)) {
b481de9c
ZY		 153 memcpy(escaped, "<hidden>", sizeof("<hidden>"));
154 return escaped;
155 }
156
157 essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE);
158 while (essid_len--) {
159 if (*s == '\0') {
160 *d++ = '\\';
161 *d++ = '0';
162 s++;
163 } else
164 *d++ = *s++;
165 }
166 *d = '\0';
167 return escaped;
168}
169
bb8c093b 170static void iwl4965_print_hex_dump(int level, void *p, u32 len)
b481de9c 171{
c8b0e6e1 172#ifdef CONFIG_IWL4965_DEBUG
bb8c093b 173 if (!(iwl4965_debug_level & level))
b481de9c
ZY		 174 return;
175
176 print_hex_dump(KERN_DEBUG, "iwl data: ", DUMP_PREFIX_OFFSET, 16, 1,
177 p, len, 1);
178#endif
179}
180
181/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
182 * DMA services
183 *
184 * Theory of operation
185 *
6440adb5
CB		 186 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
187 * of buffer descriptors, each of which points to one or more data buffers for
188 * the device to read from or fill. Driver and device exchange status of each
189 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
190 * entries in each circular buffer, to protect against confusing empty and full
191 * queue states.
192 *
193 * The device reads or writes the data in the queues via the device's several
194 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
b481de9c
ZY		 195 *
196 * For Tx queue, there are low mark and high mark limits. If, after queuing
197 * the packet for Tx, free space become < low mark, Tx queue stopped. When
198 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
199 * Tx queue resumed.
200 *
6440adb5
CB		 201 * The 4965 operates with up to 17 queues: One receive queue, one transmit
202 * queue (#4) for sending commands to the device firmware, and 15 other
203 * Tx queues that may be mapped to prioritized Tx DMA/FIFO channels.
e3851447
BC		 204 *
205 * See more detailed info in iwl-4965-hw.h.
b481de9c
ZY		 206 ***************************************************/
207
bb8c093b 208static int iwl4965_queue_space(const struct iwl4965_queue *q)
b481de9c 209{
fc4b6853 210 int s = q->read_ptr - q->write_ptr;
b481de9c 211
fc4b6853 212 if (q->read_ptr > q->write_ptr)
b481de9c
ZY		 213 s -= q->n_bd;
214
215 if (s <= 0)
216 s += q->n_window;
217 /* keep some reserve to not confuse empty and full situations */
218 s -= 2;
219 if (s < 0)
220 s = 0;
221 return s;
222}
223
6440adb5
CB		 224/**
225 * iwl4965_queue_inc_wrap - increment queue index, wrap back to beginning
226 * @index -- current index
227 * @n_bd -- total number of entries in queue (must be power of 2)
228 */
bb8c093b 229static inline int iwl4965_queue_inc_wrap(int index, int n_bd)
b481de9c
ZY		 230{
231 return ++index & (n_bd - 1);
232}
233
6440adb5
CB		 234/**
235 * iwl4965_queue_dec_wrap - decrement queue index, wrap back to end
236 * @index -- current index
237 * @n_bd -- total number of entries in queue (must be power of 2)
238 */
bb8c093b 239static inline int iwl4965_queue_dec_wrap(int index, int n_bd)
b481de9c
ZY		 240{
241 return --index & (n_bd - 1);
242}
243
bb8c093b 244static inline int x2_queue_used(const struct iwl4965_queue *q, int i)
b481de9c 245{
fc4b6853
TW		 246 return q->write_ptr > q->read_ptr ?
247 (i >= q->read_ptr && i < q->write_ptr) :
248 !(i < q->read_ptr && i >= q->write_ptr);
b481de9c
ZY		 249}
250
bb8c093b 251static inline u8 get_cmd_index(struct iwl4965_queue *q, u32 index, int is_huge)
b481de9c 252{
6440adb5 253 /* This is for scan command, the big buffer at end of command array */
b481de9c 254 if (is_huge)
6440adb5 255 return q->n_window; /* must be power of 2 */
b481de9c 256
6440adb5 257 /* Otherwise, use normal size buffers */
b481de9c
ZY		 258 return index & (q->n_window - 1);
259}
260
6440adb5
CB		 261/**
262 * iwl4965_queue_init - Initialize queue's high/low-water and read/write indexes
263 */
bb8c093b 264static int iwl4965_queue_init(struct iwl4965_priv *priv, struct iwl4965_queue *q,
b481de9c
ZY		 265 int count, int slots_num, u32 id)
266{
267 q->n_bd = count;
268 q->n_window = slots_num;
269 q->id = id;
270
bb8c093b
CH		 271 /* count must be power-of-two size, otherwise iwl4965_queue_inc_wrap
272 * and iwl4965_queue_dec_wrap are broken. */
b481de9c
ZY		 273 BUG_ON(!is_power_of_2(count));
274
275 /* slots_num must be power-of-two size, otherwise
276 * get_cmd_index is broken. */
277 BUG_ON(!is_power_of_2(slots_num));
278
279 q->low_mark = q->n_window / 4;
280 if (q->low_mark < 4)
281 q->low_mark = 4;
282
283 q->high_mark = q->n_window / 8;
284 if (q->high_mark < 2)
285 q->high_mark = 2;
286
fc4b6853 287 q->write_ptr = q->read_ptr = 0;
b481de9c
ZY		 288
289 return 0;
290}
291
6440adb5
CB		 292/**
293 * iwl4965_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
294 */
bb8c093b
CH		 295static int iwl4965_tx_queue_alloc(struct iwl4965_priv *priv,
296 struct iwl4965_tx_queue *txq, u32 id)
b481de9c
ZY		 297{
298 struct pci_dev *dev = priv->pci_dev;
299
6440adb5
CB		 300 /* Driver private data, only for Tx (not command) queues,
301 * not shared with device. */
b481de9c
ZY		 302 if (id != IWL_CMD_QUEUE_NUM) {
303 txq->txb = kmalloc(sizeof(txq->txb[0]) *
304 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
305 if (!txq->txb) {
01ebd063 306 IWL_ERROR("kmalloc for auxiliary BD "
b481de9c
ZY		 307 "structures failed\n");
308 goto error;
309 }
310 } else
311 txq->txb = NULL;
312
6440adb5
CB		 313 /* Circular buffer of transmit frame descriptors (TFDs),
314 * shared with device */
b481de9c
ZY		 315 txq->bd = pci_alloc_consistent(dev,
316 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
317 &txq->q.dma_addr);
318
319 if (!txq->bd) {
320 IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
321 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
322 goto error;
323 }
324 txq->q.id = id;
325
326 return 0;
327
328 error:
329 if (txq->txb) {
330 kfree(txq->txb);
331 txq->txb = NULL;
332 }
333
334 return -ENOMEM;
335}
336
8b6eaea8
CB		 337/**
338 * iwl4965_tx_queue_init - Allocate and initialize one tx/cmd queue
339 */
bb8c093b
CH		 340int iwl4965_tx_queue_init(struct iwl4965_priv *priv,
341 struct iwl4965_tx_queue *txq, int slots_num, u32 txq_id)
b481de9c
ZY		 342{
343 struct pci_dev *dev = priv->pci_dev;
344 int len;
345 int rc = 0;
346
8b6eaea8
CB		 347 /*
348 * Alloc buffer array for commands (Tx or other types of commands).
349 * For the command queue (#4), allocate command space + one big
350 * command for scan, since scan command is very huge; the system will
351 * not have two scans at the same time, so only one is needed.
bb54244b 352 * For normal Tx queues (all other queues), no super-size command
8b6eaea8
CB		 353 * space is needed.
354 */
bb8c093b 355 len = sizeof(struct iwl4965_cmd) * slots_num;
b481de9c
ZY		 356 if (txq_id == IWL_CMD_QUEUE_NUM)
357 len += IWL_MAX_SCAN_SIZE;
358 txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
359 if (!txq->cmd)
360 return -ENOMEM;
361
8b6eaea8 362 /* Alloc driver data array and TFD circular buffer */
bb8c093b 363 rc = iwl4965_tx_queue_alloc(priv, txq, txq_id);
b481de9c
ZY		 364 if (rc) {
365 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
366
367 return -ENOMEM;
368 }
369 txq->need_update = 0;
370
371 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
bb8c093b 372 * iwl4965_queue_inc_wrap and iwl4965_queue_dec_wrap are broken. */
b481de9c 373 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
8b6eaea8
CB		 374
375 /* Initialize queue's high/low-water marks, and head/tail indexes */
bb8c093b 376 iwl4965_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
b481de9c 377
8b6eaea8 378 /* Tell device where to find queue */
bb8c093b 379 iwl4965_hw_tx_queue_init(priv, txq);
b481de9c
ZY		 380
381 return 0;
382}
383
384/**
bb8c093b 385 * iwl4965_tx_queue_free - Deallocate DMA queue.
b481de9c
ZY		 386 * @txq: Transmit queue to deallocate.
387 *
388 * Empty queue by removing and destroying all BD's.
6440adb5
CB		 389 * Free all buffers.
390 * 0-fill, but do not free "txq" descriptor structure.
b481de9c 391 */
bb8c093b 392void iwl4965_tx_queue_free(struct iwl4965_priv *priv, struct iwl4965_tx_queue *txq)
b481de9c 393{
bb8c093b 394 struct iwl4965_queue *q = &txq->q;
b481de9c
ZY		 395 struct pci_dev *dev = priv->pci_dev;
396 int len;
397
398 if (q->n_bd == 0)
399 return;
400
401 /* first, empty all BD's */
fc4b6853 402 for (; q->write_ptr != q->read_ptr;
bb8c093b
CH		 403 q->read_ptr = iwl4965_queue_inc_wrap(q->read_ptr, q->n_bd))
404 iwl4965_hw_txq_free_tfd(priv, txq);
b481de9c 405
bb8c093b 406 len = sizeof(struct iwl4965_cmd) * q->n_window;
b481de9c
ZY		 407 if (q->id == IWL_CMD_QUEUE_NUM)
408 len += IWL_MAX_SCAN_SIZE;
409
6440adb5 410 /* De-alloc array of command/tx buffers */
b481de9c
ZY		 411 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
412
6440adb5 413 /* De-alloc circular buffer of TFDs */
b481de9c 414 if (txq->q.n_bd)
bb8c093b 415 pci_free_consistent(dev, sizeof(struct iwl4965_tfd_frame) *
b481de9c
ZY		 416 txq->q.n_bd, txq->bd, txq->q.dma_addr);
417
6440adb5 418 /* De-alloc array of per-TFD driver data */
b481de9c
ZY		 419 if (txq->txb) {
420 kfree(txq->txb);
421 txq->txb = NULL;
422 }
423
6440adb5 424 /* 0-fill queue descriptor structure */
b481de9c
ZY		 425 memset(txq, 0, sizeof(*txq));
426}
427
bb8c093b 428const u8 iwl4965_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
b481de9c
ZY		 429
430/*************** STATION TABLE MANAGEMENT ****
9fbab516 431 * mac80211 should be examined to determine if sta_info is duplicating
b481de9c
ZY		 432 * the functionality provided here
433 */
434
435/**************************************************************/
436
01ebd063 437#if 0 /* temporary disable till we add real remove station */
6440adb5
CB		 438/**
439 * iwl4965_remove_station - Remove driver's knowledge of station.
440 *
441 * NOTE: This does not remove station from device's station table.
442 */
bb8c093b 443static u8 iwl4965_remove_station(struct iwl4965_priv *priv, const u8 *addr, int is_ap)
b481de9c
ZY		 444{
445 int index = IWL_INVALID_STATION;
446 int i;
447 unsigned long flags;
448
449 spin_lock_irqsave(&priv->sta_lock, flags);
450
451 if (is_ap)
452 index = IWL_AP_ID;
453 else if (is_broadcast_ether_addr(addr))
454 index = priv->hw_setting.bcast_sta_id;
455 else
456 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
457 if (priv->stations[i].used &&
458 !compare_ether_addr(priv->stations[i].sta.sta.addr,
459 addr)) {
460 index = i;
461 break;
462 }
463
464 if (unlikely(index == IWL_INVALID_STATION))
465 goto out;
466
467 if (priv->stations[index].used) {
468 priv->stations[index].used = 0;
469 priv->num_stations--;
470 }
471
472 BUG_ON(priv->num_stations < 0);
473
474out:
475 spin_unlock_irqrestore(&priv->sta_lock, flags);
476 return 0;
477}
556f8db7 478#endif
b481de9c 479
6440adb5
CB		 480/**
481 * iwl4965_clear_stations_table - Clear the driver's station table
482 *
483 * NOTE: This does not clear or otherwise alter the device's station table.
484 */
bb8c093b 485static void iwl4965_clear_stations_table(struct iwl4965_priv *priv)
b481de9c
ZY		 486{
487 unsigned long flags;
488
489 spin_lock_irqsave(&priv->sta_lock, flags);
490
491 priv->num_stations = 0;
492 memset(priv->stations, 0, sizeof(priv->stations));
493
494 spin_unlock_irqrestore(&priv->sta_lock, flags);
495}
496
6440adb5
CB		 497/**
498 * iwl4965_add_station_flags - Add station to tables in driver and device
499 */
67d62035
RR		 500u8 iwl4965_add_station_flags(struct iwl4965_priv *priv, const u8 *addr,
501 int is_ap, u8 flags, void *ht_data)
b481de9c
ZY		 502{
503 int i;
504 int index = IWL_INVALID_STATION;
bb8c093b 505 struct iwl4965_station_entry *station;
b481de9c 506 unsigned long flags_spin;
0795af57 507 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 508
509 spin_lock_irqsave(&priv->sta_lock, flags_spin);
510 if (is_ap)
511 index = IWL_AP_ID;
512 else if (is_broadcast_ether_addr(addr))
513 index = priv->hw_setting.bcast_sta_id;
514 else
515 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
516 if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
517 addr)) {
518 index = i;
519 break;
520 }
521
522 if (!priv->stations[i].used &&
523 index == IWL_INVALID_STATION)
524 index = i;
525 }
526
527
9fbab516
BC		 528 /* These two conditions have the same outcome, but keep them separate
529 since they have different meanings */
b481de9c
ZY		 530 if (unlikely(index == IWL_INVALID_STATION)) {
531 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
532 return index;
533 }
534
535 if (priv->stations[index].used &&
536 !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
537 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
538 return index;
539 }
540
541
0795af57 542 IWL_DEBUG_ASSOC("Add STA ID %d: %s\n", index, print_mac(mac, addr));
b481de9c
ZY		 543 station = &priv->stations[index];
544 station->used = 1;
545 priv->num_stations++;
546
6440adb5 547 /* Set up the REPLY_ADD_STA command to send to device */
bb8c093b 548 memset(&station->sta, 0, sizeof(struct iwl4965_addsta_cmd));
b481de9c
ZY		 549 memcpy(station->sta.sta.addr, addr, ETH_ALEN);
550 station->sta.mode = 0;
551 station->sta.sta.sta_id = index;
552 station->sta.station_flags = 0;
553
c8b0e6e1 554#ifdef CONFIG_IWL4965_HT
b481de9c
ZY		 555 /* BCAST station and IBSS stations do not work in HT mode */
556 if (index != priv->hw_setting.bcast_sta_id &&
557 priv->iw_mode != IEEE80211_IF_TYPE_IBSS)
67d62035
RR		 558 iwl4965_set_ht_add_station(priv, index,
559 (struct ieee80211_ht_info *) ht_data);
c8b0e6e1 560#endif /*CONFIG_IWL4965_HT*/
b481de9c
ZY		 561
562 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
6440adb5
CB		 563
564 /* Add station to device's station table */
bb8c093b 565 iwl4965_send_add_station(priv, &station->sta, flags);
b481de9c
ZY		 566 return index;
567
568}
569
570/*************** DRIVER STATUS FUNCTIONS *****/
571
bb8c093b 572static inline int iwl4965_is_ready(struct iwl4965_priv *priv)
b481de9c
ZY		 573{
574 /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
575 * set but EXIT_PENDING is not */
576 return test_bit(STATUS_READY, &priv->status) &&
577 test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
578 !test_bit(STATUS_EXIT_PENDING, &priv->status);
579}
580
bb8c093b 581static inline int iwl4965_is_alive(struct iwl4965_priv *priv)
b481de9c
ZY		 582{
583 return test_bit(STATUS_ALIVE, &priv->status);
584}
585
bb8c093b 586static inline int iwl4965_is_init(struct iwl4965_priv *priv)
b481de9c
ZY		 587{
588 return test_bit(STATUS_INIT, &priv->status);
589}
590
bb8c093b 591static inline int iwl4965_is_rfkill(struct iwl4965_priv *priv)
b481de9c
ZY		 592{
593 return test_bit(STATUS_RF_KILL_HW, &priv->status) ||
594 test_bit(STATUS_RF_KILL_SW, &priv->status);
595}
596
bb8c093b 597static inline int iwl4965_is_ready_rf(struct iwl4965_priv *priv)
b481de9c
ZY		 598{
599
bb8c093b 600 if (iwl4965_is_rfkill(priv))
b481de9c
ZY		 601 return 0;
602
bb8c093b 603 return iwl4965_is_ready(priv);
b481de9c
ZY		 604}
605
606/*************** HOST COMMAND QUEUE FUNCTIONS *****/
607
608#define IWL_CMD(x) case x : return #x
609
610static const char *get_cmd_string(u8 cmd)
611{
612 switch (cmd) {
613 IWL_CMD(REPLY_ALIVE);
614 IWL_CMD(REPLY_ERROR);
615 IWL_CMD(REPLY_RXON);
616 IWL_CMD(REPLY_RXON_ASSOC);
617 IWL_CMD(REPLY_QOS_PARAM);
618 IWL_CMD(REPLY_RXON_TIMING);
619 IWL_CMD(REPLY_ADD_STA);
620 IWL_CMD(REPLY_REMOVE_STA);
621 IWL_CMD(REPLY_REMOVE_ALL_STA);
622 IWL_CMD(REPLY_TX);
623 IWL_CMD(REPLY_RATE_SCALE);
624 IWL_CMD(REPLY_LEDS_CMD);
625 IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
626 IWL_CMD(RADAR_NOTIFICATION);
627 IWL_CMD(REPLY_QUIET_CMD);
628 IWL_CMD(REPLY_CHANNEL_SWITCH);
629 IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
630 IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
631 IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
632 IWL_CMD(POWER_TABLE_CMD);
633 IWL_CMD(PM_SLEEP_NOTIFICATION);
634 IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
635 IWL_CMD(REPLY_SCAN_CMD);
636 IWL_CMD(REPLY_SCAN_ABORT_CMD);
637 IWL_CMD(SCAN_START_NOTIFICATION);
638 IWL_CMD(SCAN_RESULTS_NOTIFICATION);
639 IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
640 IWL_CMD(BEACON_NOTIFICATION);
641 IWL_CMD(REPLY_TX_BEACON);
642 IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
643 IWL_CMD(QUIET_NOTIFICATION);
644 IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
645 IWL_CMD(MEASURE_ABORT_NOTIFICATION);
646 IWL_CMD(REPLY_BT_CONFIG);
647 IWL_CMD(REPLY_STATISTICS_CMD);
648 IWL_CMD(STATISTICS_NOTIFICATION);
649 IWL_CMD(REPLY_CARD_STATE_CMD);
650 IWL_CMD(CARD_STATE_NOTIFICATION);
651 IWL_CMD(MISSED_BEACONS_NOTIFICATION);
652 IWL_CMD(REPLY_CT_KILL_CONFIG_CMD);
653 IWL_CMD(SENSITIVITY_CMD);
654 IWL_CMD(REPLY_PHY_CALIBRATION_CMD);
655 IWL_CMD(REPLY_RX_PHY_CMD);
656 IWL_CMD(REPLY_RX_MPDU_CMD);
657 IWL_CMD(REPLY_4965_RX);
658 IWL_CMD(REPLY_COMPRESSED_BA);
659 default:
660 return "UNKNOWN";
661
662 }
663}
664
665#define HOST_COMPLETE_TIMEOUT (HZ / 2)
666
667/**
bb8c093b 668 * iwl4965_enqueue_hcmd - enqueue a uCode command
b481de9c
ZY		 669 * @priv: device private data point
670 * @cmd: a point to the ucode command structure
671 *
672 * The function returns < 0 values to indicate the operation is
673 * failed. On success, it turns the index (> 0) of command in the
674 * command queue.
675 */
bb8c093b 676static int iwl4965_enqueue_hcmd(struct iwl4965_priv *priv, struct iwl4965_host_cmd *cmd)
b481de9c 677{
bb8c093b
CH		 678 struct iwl4965_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
679 struct iwl4965_queue *q = &txq->q;
680 struct iwl4965_tfd_frame *tfd;
b481de9c 681 u32 *control_flags;
bb8c093b 682 struct iwl4965_cmd *out_cmd;
b481de9c
ZY		 683 u32 idx;
684 u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
685 dma_addr_t phys_addr;
686 int ret;
687 unsigned long flags;
688
689 /* If any of the command structures end up being larger than
690 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
691 * we will need to increase the size of the TFD entries */
692 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
693 !(cmd->meta.flags & CMD_SIZE_HUGE));
694
bb8c093b 695 if (iwl4965_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
b481de9c
ZY		 696 IWL_ERROR("No space for Tx\n");
697 return -ENOSPC;
698 }
699
700 spin_lock_irqsave(&priv->hcmd_lock, flags);
701
fc4b6853 702 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY		 703 memset(tfd, 0, sizeof(*tfd));
704
705 control_flags = (u32 *) tfd;
706
fc4b6853 707 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
b481de9c
ZY		 708 out_cmd = &txq->cmd[idx];
709
710 out_cmd->hdr.cmd = cmd->id;
711 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
712 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
713
714 /* At this point, the out_cmd now has all of the incoming cmd
715 * information */
716
717 out_cmd->hdr.flags = 0;
718 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
fc4b6853 719 INDEX_TO_SEQ(q->write_ptr));
b481de9c
ZY		 720 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
721 out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
722
723 phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
bb8c093b
CH		 724 offsetof(struct iwl4965_cmd, hdr);
725 iwl4965_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
b481de9c
ZY		 726
727 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
728 "%d bytes at %d[%d]:%d\n",
729 get_cmd_string(out_cmd->hdr.cmd),
730 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
fc4b6853 731 fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
b481de9c
ZY		 732
733 txq->need_update = 1;
6440adb5
CB		 734
735 /* Set up entry in queue's byte count circular buffer */
b481de9c 736 ret = iwl4965_tx_queue_update_wr_ptr(priv, txq, 0);
6440adb5
CB		 737
738 /* Increment and update queue's write index */
bb8c093b
CH		 739 q->write_ptr = iwl4965_queue_inc_wrap(q->write_ptr, q->n_bd);
740 iwl4965_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 741
742 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
743 return ret ? ret : idx;
744}
745
bb8c093b 746static int iwl4965_send_cmd_async(struct iwl4965_priv *priv, struct iwl4965_host_cmd *cmd)
b481de9c
ZY		 747{
748 int ret;
749
750 BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
751
752 /* An asynchronous command can not expect an SKB to be set. */
753 BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
754
755 /* An asynchronous command MUST have a callback. */
756 BUG_ON(!cmd->meta.u.callback);
757
758 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
759 return -EBUSY;
760
bb8c093b 761 ret = iwl4965_enqueue_hcmd(priv, cmd);
b481de9c 762 if (ret < 0) {
bb8c093b 763 IWL_ERROR("Error sending %s: iwl4965_enqueue_hcmd failed: %d\n",
b481de9c
ZY		 764 get_cmd_string(cmd->id), ret);
765 return ret;
766 }
767 return 0;
768}
769
bb8c093b 770static int iwl4965_send_cmd_sync(struct iwl4965_priv *priv, struct iwl4965_host_cmd *cmd)
b481de9c
ZY		 771{
772 int cmd_idx;
773 int ret;
774 static atomic_t entry = ATOMIC_INIT(0); /* reentrance protection */
775
776 BUG_ON(cmd->meta.flags & CMD_ASYNC);
777
778 /* A synchronous command can not have a callback set. */
779 BUG_ON(cmd->meta.u.callback != NULL);
780
781 if (atomic_xchg(&entry, 1)) {
782 IWL_ERROR("Error sending %s: Already sending a host command\n",
783 get_cmd_string(cmd->id));
784 return -EBUSY;
785 }
786
787 set_bit(STATUS_HCMD_ACTIVE, &priv->status);
788
789 if (cmd->meta.flags & CMD_WANT_SKB)
790 cmd->meta.source = &cmd->meta;
791
bb8c093b 792 cmd_idx = iwl4965_enqueue_hcmd(priv, cmd);
b481de9c
ZY		 793 if (cmd_idx < 0) {
794 ret = cmd_idx;
bb8c093b 795 IWL_ERROR("Error sending %s: iwl4965_enqueue_hcmd failed: %d\n",
b481de9c
ZY		 796 get_cmd_string(cmd->id), ret);
797 goto out;
798 }
799
800 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
801 !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
802 HOST_COMPLETE_TIMEOUT);
803 if (!ret) {
804 if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
805 IWL_ERROR("Error sending %s: time out after %dms.\n",
806 get_cmd_string(cmd->id),
807 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
808
809 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
810 ret = -ETIMEDOUT;
811 goto cancel;
812 }
813 }
814
815 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
816 IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
817 get_cmd_string(cmd->id));
818 ret = -ECANCELED;
819 goto fail;
820 }
821 if (test_bit(STATUS_FW_ERROR, &priv->status)) {
822 IWL_DEBUG_INFO("Command %s failed: FW Error\n",
823 get_cmd_string(cmd->id));
824 ret = -EIO;
825 goto fail;
826 }
827 if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
828 IWL_ERROR("Error: Response NULL in '%s'\n",
829 get_cmd_string(cmd->id));
830 ret = -EIO;
831 goto out;
832 }
833
834 ret = 0;
835 goto out;
836
837cancel:
838 if (cmd->meta.flags & CMD_WANT_SKB) {
bb8c093b 839 struct iwl4965_cmd *qcmd;
b481de9c
ZY		 840
841 /* Cancel the CMD_WANT_SKB flag for the cmd in the
842 * TX cmd queue. Otherwise in case the cmd comes
843 * in later, it will possibly set an invalid
844 * address (cmd->meta.source). */
845 qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
846 qcmd->meta.flags &= ~CMD_WANT_SKB;
847 }
848fail:
849 if (cmd->meta.u.skb) {
850 dev_kfree_skb_any(cmd->meta.u.skb);
851 cmd->meta.u.skb = NULL;
852 }
853out:
854 atomic_set(&entry, 0);
855 return ret;
856}
857
bb8c093b 858int iwl4965_send_cmd(struct iwl4965_priv *priv, struct iwl4965_host_cmd *cmd)
b481de9c 859{
b481de9c 860 if (cmd->meta.flags & CMD_ASYNC)
bb8c093b 861 return iwl4965_send_cmd_async(priv, cmd);
b481de9c 862
bb8c093b 863 return iwl4965_send_cmd_sync(priv, cmd);
b481de9c
ZY		 864}
865
bb8c093b 866int iwl4965_send_cmd_pdu(struct iwl4965_priv *priv, u8 id, u16 len, const void *data)
b481de9c 867{
bb8c093b 868 struct iwl4965_host_cmd cmd = {
b481de9c
ZY		 869 .id = id,
870 .len = len,
871 .data = data,
872 };
873
bb8c093b 874 return iwl4965_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 875}
876
bb8c093b 877static int __must_check iwl4965_send_cmd_u32(struct iwl4965_priv *priv, u8 id, u32 val)
b481de9c 878{
bb8c093b 879 struct iwl4965_host_cmd cmd = {
b481de9c
ZY		 880 .id = id,
881 .len = sizeof(val),
882 .data = &val,
883 };
884
bb8c093b 885 return iwl4965_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 886}
887
bb8c093b 888int iwl4965_send_statistics_request(struct iwl4965_priv *priv)
b481de9c 889{
bb8c093b 890 return iwl4965_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
b481de9c
ZY		 891}
892
893/**
bb8c093b 894 * iwl4965_rxon_add_station - add station into station table.
b481de9c
ZY		 895 *
896 * there is only one AP station with id= IWL_AP_ID
9fbab516
BC		 897 * NOTE: mutex must be held before calling this fnction
898 */
bb8c093b 899static int iwl4965_rxon_add_station(struct iwl4965_priv *priv,
b481de9c
ZY		 900 const u8 *addr, int is_ap)
901{
556f8db7 902 u8 sta_id;
b481de9c 903
6440adb5 904 /* Add station to device's station table */
67d62035
RR		 905#ifdef CONFIG_IWL4965_HT
906 struct ieee80211_conf *conf = &priv->hw->conf;
907 struct ieee80211_ht_info *cur_ht_config = &conf->ht_conf;
908
909 if ((is_ap) &&
910 (conf->flags & IEEE80211_CONF_SUPPORT_HT_MODE) &&
911 (priv->iw_mode == IEEE80211_IF_TYPE_STA))
912 sta_id = iwl4965_add_station_flags(priv, addr, is_ap,
913 0, cur_ht_config);
914 else
915#endif /* CONFIG_IWL4965_HT */
916 sta_id = iwl4965_add_station_flags(priv, addr, is_ap,
917 0, NULL);
6440adb5
CB		 918
919 /* Set up default rate scaling table in device's station table */
b481de9c
ZY		 920 iwl4965_add_station(priv, addr, is_ap);
921
556f8db7 922 return sta_id;
b481de9c
ZY		 923}
924
925/**
bb8c093b 926 * iwl4965_set_rxon_channel - Set the phymode and channel values in staging RXON
b481de9c
ZY		 927 * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
928 * @channel: Any channel valid for the requested phymode
929
930 * In addition to setting the staging RXON, priv->phymode is also set.
931 *
932 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
933 * in the staging RXON flag structure based on the phymode
934 */
9fbab516
BC		 935static int iwl4965_set_rxon_channel(struct iwl4965_priv *priv, u8 phymode,
936 u16 channel)
b481de9c 937{
bb8c093b 938 if (!iwl4965_get_channel_info(priv, phymode, channel)) {
b481de9c
ZY		 939 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
940 channel, phymode);
941 return -EINVAL;
942 }
943
944 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
945 (priv->phymode == phymode))
946 return 0;
947
948 priv->staging_rxon.channel = cpu_to_le16(channel);
949 if (phymode == MODE_IEEE80211A)
950 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
951 else
952 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
953
954 priv->phymode = phymode;
955
956 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, phymode);
957
958 return 0;
959}
960
961/**
bb8c093b 962 * iwl4965_check_rxon_cmd - validate RXON structure is valid
b481de9c
ZY		 963 *
964 * NOTE: This is really only useful during development and can eventually
965 * be #ifdef'd out once the driver is stable and folks aren't actively
966 * making changes
967 */
bb8c093b 968static int iwl4965_check_rxon_cmd(struct iwl4965_rxon_cmd *rxon)
b481de9c
ZY		 969{
970 int error = 0;
971 int counter = 1;
972
973 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
974 error |= le32_to_cpu(rxon->flags &
975 (RXON_FLG_TGJ_NARROW_BAND_MSK |
976 RXON_FLG_RADAR_DETECT_MSK));
977 if (error)
978 IWL_WARNING("check 24G fields %d | %d\n",
979 counter++, error);
980 } else {
981 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
982 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
983 if (error)
984 IWL_WARNING("check 52 fields %d | %d\n",
985 counter++, error);
986 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
987 if (error)
988 IWL_WARNING("check 52 CCK %d | %d\n",
989 counter++, error);
990 }
991 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
992 if (error)
993 IWL_WARNING("check mac addr %d | %d\n", counter++, error);
994
995 /* make sure basic rates 6Mbps and 1Mbps are supported */
996 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
997 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
998 if (error)
999 IWL_WARNING("check basic rate %d | %d\n", counter++, error);
1000
1001 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
1002 if (error)
1003 IWL_WARNING("check assoc id %d | %d\n", counter++, error);
1004
1005 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
1006 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
1007 if (error)
1008 IWL_WARNING("check CCK and short slot %d | %d\n",
1009 counter++, error);
1010
1011 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
1012 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
1013 if (error)
1014 IWL_WARNING("check CCK & auto detect %d | %d\n",
1015 counter++, error);
1016
1017 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
1018 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
1019 if (error)
1020 IWL_WARNING("check TGG and auto detect %d | %d\n",
1021 counter++, error);
1022
1023 if (error)
1024 IWL_WARNING("Tuning to channel %d\n",
1025 le16_to_cpu(rxon->channel));
1026
1027 if (error) {
bb8c093b 1028 IWL_ERROR("Not a valid iwl4965_rxon_assoc_cmd field values\n");
b481de9c
ZY		 1029 return -1;
1030 }
1031 return 0;
1032}
1033
1034/**
9fbab516 1035 * iwl4965_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
01ebd063 1036 * @priv: staging_rxon is compared to active_rxon
b481de9c 1037 *
9fbab516
BC		 1038 * If the RXON structure is changing enough to require a new tune,
1039 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
1040 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
b481de9c 1041 */
bb8c093b 1042static int iwl4965_full_rxon_required(struct iwl4965_priv *priv)
b481de9c
ZY		 1043{
1044
1045 /* These items are only settable from the full RXON command */
1046 if (!(priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ||
1047 compare_ether_addr(priv->staging_rxon.bssid_addr,
1048 priv->active_rxon.bssid_addr) ||
1049 compare_ether_addr(priv->staging_rxon.node_addr,
1050 priv->active_rxon.node_addr) ||
1051 compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
1052 priv->active_rxon.wlap_bssid_addr) ||
1053 (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
1054 (priv->staging_rxon.channel != priv->active_rxon.channel) ||
1055 (priv->staging_rxon.air_propagation !=
1056 priv->active_rxon.air_propagation) ||
1057 (priv->staging_rxon.ofdm_ht_single_stream_basic_rates !=
1058 priv->active_rxon.ofdm_ht_single_stream_basic_rates) ||
1059 (priv->staging_rxon.ofdm_ht_dual_stream_basic_rates !=
1060 priv->active_rxon.ofdm_ht_dual_stream_basic_rates) ||
1061 (priv->staging_rxon.rx_chain != priv->active_rxon.rx_chain) ||
1062 (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
1063 return 1;
1064
1065 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
1066 * be updated with the RXON_ASSOC command -- however only some
1067 * flag transitions are allowed using RXON_ASSOC */
1068
1069 /* Check if we are not switching bands */
1070 if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
1071 (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
1072 return 1;
1073
1074 /* Check if we are switching association toggle */
1075 if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
1076 (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
1077 return 1;
1078
1079 return 0;
1080}
1081
bb8c093b 1082static int iwl4965_send_rxon_assoc(struct iwl4965_priv *priv)
b481de9c
ZY		 1083{
1084 int rc = 0;
bb8c093b
CH		 1085 struct iwl4965_rx_packet *res = NULL;
1086 struct iwl4965_rxon_assoc_cmd rxon_assoc;
1087 struct iwl4965_host_cmd cmd = {
b481de9c
ZY		 1088 .id = REPLY_RXON_ASSOC,
1089 .len = sizeof(rxon_assoc),
1090 .meta.flags = CMD_WANT_SKB,
1091 .data = &rxon_assoc,
1092 };
bb8c093b
CH		 1093 const struct iwl4965_rxon_cmd *rxon1 = &priv->staging_rxon;
1094 const struct iwl4965_rxon_cmd *rxon2 = &priv->active_rxon;
b481de9c
ZY		 1095
1096 if ((rxon1->flags == rxon2->flags) &&
1097 (rxon1->filter_flags == rxon2->filter_flags) &&
1098 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1099 (rxon1->ofdm_ht_single_stream_basic_rates ==
1100 rxon2->ofdm_ht_single_stream_basic_rates) &&
1101 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1102 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1103 (rxon1->rx_chain == rxon2->rx_chain) &&
1104 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1105 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
1106 return 0;
1107 }
1108
1109 rxon_assoc.flags = priv->staging_rxon.flags;
1110 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1111 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1112 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1113 rxon_assoc.reserved = 0;
1114 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1115 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1116 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1117 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1118 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1119
bb8c093b 1120 rc = iwl4965_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 1121 if (rc)
1122 return rc;
1123
bb8c093b 1124 res = (struct iwl4965_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1125 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1126 IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
1127 rc = -EIO;
1128 }
1129
1130 priv->alloc_rxb_skb--;
1131 dev_kfree_skb_any(cmd.meta.u.skb);
1132
1133 return rc;
1134}
1135
1136/**
bb8c093b 1137 * iwl4965_commit_rxon - commit staging_rxon to hardware
b481de9c 1138 *
01ebd063 1139 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
ZY		 1140 * the active_rxon structure is updated with the new data. This
1141 * function correctly transitions out of the RXON_ASSOC_MSK state if
1142 * a HW tune is required based on the RXON structure changes.
1143 */
bb8c093b 1144static int iwl4965_commit_rxon(struct iwl4965_priv *priv)
b481de9c
ZY		 1145{
1146 /* cast away the const for active_rxon in this function */
bb8c093b 1147 struct iwl4965_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
0795af57 1148 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 1149 int rc = 0;
1150
bb8c093b 1151 if (!iwl4965_is_alive(priv))
b481de9c
ZY		 1152 return -1;
1153
1154 /* always get timestamp with Rx frame */
1155 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
1156
bb8c093b 1157 rc = iwl4965_check_rxon_cmd(&priv->staging_rxon);
b481de9c
ZY		 1158 if (rc) {
1159 IWL_ERROR("Invalid RXON configuration. Not committing.\n");
1160 return -EINVAL;
1161 }
1162
1163 /* If we don't need to send a full RXON, we can use
bb8c093b 1164 * iwl4965_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 1165 * and other flags for the current radio configuration. */
bb8c093b
CH		 1166 if (!iwl4965_full_rxon_required(priv)) {
1167 rc = iwl4965_send_rxon_assoc(priv);
b481de9c
ZY		 1168 if (rc) {
1169 IWL_ERROR("Error setting RXON_ASSOC "
1170 "configuration (%d).\n", rc);
1171 return rc;
1172 }
1173
1174 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1175
1176 return 0;
1177 }
1178
1179 /* station table will be cleared */
1180 priv->assoc_station_added = 0;
1181
c8b0e6e1 1182#ifdef CONFIG_IWL4965_SENSITIVITY
b481de9c
ZY		 1183 priv->sensitivity_data.state = IWL_SENS_CALIB_NEED_REINIT;
1184 if (!priv->error_recovering)
1185 priv->start_calib = 0;
1186
1187 iwl4965_init_sensitivity(priv, CMD_ASYNC, 1);
c8b0e6e1 1188#endif /* CONFIG_IWL4965_SENSITIVITY */
b481de9c
ZY		 1189
1190 /* If we are currently associated and the new config requires
1191 * an RXON_ASSOC and the new config wants the associated mask enabled,
1192 * we must clear the associated from the active configuration
1193 * before we apply the new config */
bb8c093b 1194 if (iwl4965_is_associated(priv) &&
b481de9c
ZY		 1195 (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
1196 IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
1197 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1198
bb8c093b
CH		 1199 rc = iwl4965_send_cmd_pdu(priv, REPLY_RXON,
1200 sizeof(struct iwl4965_rxon_cmd),
b481de9c
ZY		 1201 &priv->active_rxon);
1202
1203 /* If the mask clearing failed then we set
1204 * active_rxon back to what it was previously */
1205 if (rc) {
1206 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1207 IWL_ERROR("Error clearing ASSOC_MSK on current "
1208 "configuration (%d).\n", rc);
1209 return rc;
1210 }
b481de9c
ZY		 1211 }
1212
1213 IWL_DEBUG_INFO("Sending RXON\n"
1214 "* with%s RXON_FILTER_ASSOC_MSK\n"
1215 "* channel = %d\n"
0795af57 1216 "* bssid = %s\n",
b481de9c
ZY		 1217 ((priv->staging_rxon.filter_flags &
1218 RXON_FILTER_ASSOC_MSK) ? "" : "out"),
1219 le16_to_cpu(priv->staging_rxon.channel),
0795af57 1220 print_mac(mac, priv->staging_rxon.bssid_addr));
b481de9c
ZY		 1221
1222 /* Apply the new configuration */
bb8c093b
CH		 1223 rc = iwl4965_send_cmd_pdu(priv, REPLY_RXON,
1224 sizeof(struct iwl4965_rxon_cmd), &priv->staging_rxon);
b481de9c
ZY		 1225 if (rc) {
1226 IWL_ERROR("Error setting new configuration (%d).\n", rc);
1227 return rc;
1228 }
1229
bb8c093b 1230 iwl4965_clear_stations_table(priv);
556f8db7 1231
c8b0e6e1 1232#ifdef CONFIG_IWL4965_SENSITIVITY
b481de9c
ZY		 1233 if (!priv->error_recovering)
1234 priv->start_calib = 0;
1235
1236 priv->sensitivity_data.state = IWL_SENS_CALIB_NEED_REINIT;
1237 iwl4965_init_sensitivity(priv, CMD_ASYNC, 1);
c8b0e6e1 1238#endif /* CONFIG_IWL4965_SENSITIVITY */
b481de9c
ZY		 1239
1240 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1241
1242 /* If we issue a new RXON command which required a tune then we must
1243 * send a new TXPOWER command or we won't be able to Tx any frames */
bb8c093b 1244 rc = iwl4965_hw_reg_send_txpower(priv);
b481de9c
ZY		 1245 if (rc) {
1246 IWL_ERROR("Error setting Tx power (%d).\n", rc);
1247 return rc;
1248 }
1249
1250 /* Add the broadcast address so we can send broadcast frames */
bb8c093b 1251 if (iwl4965_rxon_add_station(priv, iwl4965_broadcast_addr, 0) ==
b481de9c
ZY		 1252 IWL_INVALID_STATION) {
1253 IWL_ERROR("Error adding BROADCAST address for transmit.\n");
1254 return -EIO;
1255 }
1256
1257 /* If we have set the ASSOC_MSK and we are in BSS mode then
1258 * add the IWL_AP_ID to the station rate table */
bb8c093b 1259 if (iwl4965_is_associated(priv) &&
b481de9c 1260 (priv->iw_mode == IEEE80211_IF_TYPE_STA)) {
bb8c093b 1261 if (iwl4965_rxon_add_station(priv, priv->active_rxon.bssid_addr, 1)
b481de9c
ZY		 1262 == IWL_INVALID_STATION) {
1263 IWL_ERROR("Error adding AP address for transmit.\n");
1264 return -EIO;
1265 }
1266 priv->assoc_station_added = 1;
1267 }
1268
1269 return 0;
1270}
1271
bb8c093b 1272static int iwl4965_send_bt_config(struct iwl4965_priv *priv)
b481de9c 1273{
bb8c093b 1274 struct iwl4965_bt_cmd bt_cmd = {
b481de9c
ZY		 1275 .flags = 3,
1276 .lead_time = 0xAA,
1277 .max_kill = 1,
1278 .kill_ack_mask = 0,
1279 .kill_cts_mask = 0,
1280 };
1281
bb8c093b
CH		 1282 return iwl4965_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1283 sizeof(struct iwl4965_bt_cmd), &bt_cmd);
b481de9c
ZY		 1284}
1285
bb8c093b 1286static int iwl4965_send_scan_abort(struct iwl4965_priv *priv)
b481de9c
ZY		 1287{
1288 int rc = 0;
bb8c093b
CH		 1289 struct iwl4965_rx_packet *res;
1290 struct iwl4965_host_cmd cmd = {
b481de9c
ZY		 1291 .id = REPLY_SCAN_ABORT_CMD,
1292 .meta.flags = CMD_WANT_SKB,
1293 };
1294
1295 /* If there isn't a scan actively going on in the hardware
1296 * then we are in between scan bands and not actually
1297 * actively scanning, so don't send the abort command */
1298 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
1299 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1300 return 0;
1301 }
1302
bb8c093b 1303 rc = iwl4965_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 1304 if (rc) {
1305 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1306 return rc;
1307 }
1308
bb8c093b 1309 res = (struct iwl4965_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1310 if (res->u.status != CAN_ABORT_STATUS) {
1311 /* The scan abort will return 1 for success or
1312 * 2 for "failure". A failure condition can be
1313 * due to simply not being in an active scan which
1314 * can occur if we send the scan abort before we
1315 * the microcode has notified us that a scan is
1316 * completed. */
1317 IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
1318 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1319 clear_bit(STATUS_SCAN_HW, &priv->status);
1320 }
1321
1322 dev_kfree_skb_any(cmd.meta.u.skb);
1323
1324 return rc;
1325}
1326
bb8c093b
CH		 1327static int iwl4965_card_state_sync_callback(struct iwl4965_priv *priv,
1328 struct iwl4965_cmd *cmd,
b481de9c
ZY		 1329 struct sk_buff *skb)
1330{
1331 return 1;
1332}
1333
1334/*
1335 * CARD_STATE_CMD
1336 *
9fbab516 1337 * Use: Sets the device's internal card state to enable, disable, or halt
b481de9c
ZY		 1338 *
1339 * When in the 'enable' state the card operates as normal.
1340 * When in the 'disable' state, the card enters into a low power mode.
1341 * When in the 'halt' state, the card is shut down and must be fully
1342 * restarted to come back on.
1343 */
bb8c093b 1344static int iwl4965_send_card_state(struct iwl4965_priv *priv, u32 flags, u8 meta_flag)
b481de9c 1345{
bb8c093b 1346 struct iwl4965_host_cmd cmd = {
b481de9c
ZY		 1347 .id = REPLY_CARD_STATE_CMD,
1348 .len = sizeof(u32),
1349 .data = &flags,
1350 .meta.flags = meta_flag,
1351 };
1352
1353 if (meta_flag & CMD_ASYNC)
bb8c093b 1354 cmd.meta.u.callback = iwl4965_card_state_sync_callback;
b481de9c 1355
bb8c093b 1356 return iwl4965_send_cmd(priv, &cmd);
b481de9c
ZY		 1357}
1358
bb8c093b
CH		 1359static int iwl4965_add_sta_sync_callback(struct iwl4965_priv *priv,
1360 struct iwl4965_cmd *cmd, struct sk_buff *skb)
b481de9c 1361{
bb8c093b 1362 struct iwl4965_rx_packet *res = NULL;
b481de9c
ZY		 1363
1364 if (!skb) {
1365 IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
1366 return 1;
1367 }
1368
bb8c093b 1369 res = (struct iwl4965_rx_packet *)skb->data;
b481de9c
ZY		 1370 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1371 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1372 res->hdr.flags);
1373 return 1;
1374 }
1375
1376 switch (res->u.add_sta.status) {
1377 case ADD_STA_SUCCESS_MSK:
1378 break;
1379 default:
1380 break;
1381 }
1382
1383 /* We didn't cache the SKB; let the caller free it */
1384 return 1;
1385}
1386
bb8c093b
CH		 1387int iwl4965_send_add_station(struct iwl4965_priv *priv,
1388 struct iwl4965_addsta_cmd *sta, u8 flags)
b481de9c 1389{
bb8c093b 1390 struct iwl4965_rx_packet *res = NULL;
b481de9c 1391 int rc = 0;
bb8c093b 1392 struct iwl4965_host_cmd cmd = {
b481de9c 1393 .id = REPLY_ADD_STA,
bb8c093b 1394 .len = sizeof(struct iwl4965_addsta_cmd),
b481de9c
ZY		 1395 .meta.flags = flags,
1396 .data = sta,
1397 };
1398
1399 if (flags & CMD_ASYNC)
bb8c093b 1400 cmd.meta.u.callback = iwl4965_add_sta_sync_callback;
b481de9c
ZY		 1401 else
1402 cmd.meta.flags |= CMD_WANT_SKB;
1403
bb8c093b 1404 rc = iwl4965_send_cmd(priv, &cmd);
b481de9c
ZY		 1405
1406 if (rc || (flags & CMD_ASYNC))
1407 return rc;
1408
bb8c093b 1409 res = (struct iwl4965_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1410 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1411 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1412 res->hdr.flags);
1413 rc = -EIO;
1414 }
1415
1416 if (rc == 0) {
1417 switch (res->u.add_sta.status) {
1418 case ADD_STA_SUCCESS_MSK:
1419 IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
1420 break;
1421 default:
1422 rc = -EIO;
1423 IWL_WARNING("REPLY_ADD_STA failed\n");
1424 break;
1425 }
1426 }
1427
1428 priv->alloc_rxb_skb--;
1429 dev_kfree_skb_any(cmd.meta.u.skb);
1430
1431 return rc;
1432}
1433
bb8c093b 1434static int iwl4965_update_sta_key_info(struct iwl4965_priv *priv,
b481de9c
ZY		 1435 struct ieee80211_key_conf *keyconf,
1436 u8 sta_id)
1437{
1438 unsigned long flags;
1439 __le16 key_flags = 0;
1440
1441 switch (keyconf->alg) {
1442 case ALG_CCMP:
1443 key_flags |= STA_KEY_FLG_CCMP;
1444 key_flags |= cpu_to_le16(
1445 keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
1446 key_flags &= ~STA_KEY_FLG_INVALID;
1447 break;
1448 case ALG_TKIP:
1449 case ALG_WEP:
b481de9c
ZY		 1450 default:
1451 return -EINVAL;
1452 }
1453 spin_lock_irqsave(&priv->sta_lock, flags);
1454 priv->stations[sta_id].keyinfo.alg = keyconf->alg;
1455 priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
1456 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
1457 keyconf->keylen);
1458
1459 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
1460 keyconf->keylen);
1461 priv->stations[sta_id].sta.key.key_flags = key_flags;
1462 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1463 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1464
1465 spin_unlock_irqrestore(&priv->sta_lock, flags);
1466
1467 IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
bb8c093b 1468 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY		 1469 return 0;
1470}
1471
bb8c093b 1472static int iwl4965_clear_sta_key_info(struct iwl4965_priv *priv, u8 sta_id)
b481de9c
ZY		 1473{
1474 unsigned long flags;
1475
1476 spin_lock_irqsave(&priv->sta_lock, flags);
bb8c093b
CH		 1477 memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl4965_hw_key));
1478 memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl4965_keyinfo));
b481de9c
ZY		 1479 priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
1480 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1481 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1482 spin_unlock_irqrestore(&priv->sta_lock, flags);
1483
1484 IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
bb8c093b 1485 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY		 1486 return 0;
1487}
1488
bb8c093b 1489static void iwl4965_clear_free_frames(struct iwl4965_priv *priv)
b481de9c
ZY		 1490{
1491 struct list_head *element;
1492
1493 IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
1494 priv->frames_count);
1495
1496 while (!list_empty(&priv->free_frames)) {
1497 element = priv->free_frames.next;
1498 list_del(element);
bb8c093b 1499 kfree(list_entry(element, struct iwl4965_frame, list));
b481de9c
ZY		 1500 priv->frames_count--;
1501 }
1502
1503 if (priv->frames_count) {
1504 IWL_WARNING("%d frames still in use. Did we lose one?\n",
1505 priv->frames_count);
1506 priv->frames_count = 0;
1507 }
1508}
1509
bb8c093b 1510static struct iwl4965_frame *iwl4965_get_free_frame(struct iwl4965_priv *priv)
b481de9c 1511{
bb8c093b 1512 struct iwl4965_frame *frame;
b481de9c
ZY		 1513 struct list_head *element;
1514 if (list_empty(&priv->free_frames)) {
1515 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
1516 if (!frame) {
1517 IWL_ERROR("Could not allocate frame!\n");
1518 return NULL;
1519 }
1520
1521 priv->frames_count++;
1522 return frame;
1523 }
1524
1525 element = priv->free_frames.next;
1526 list_del(element);
bb8c093b 1527 return list_entry(element, struct iwl4965_frame, list);
b481de9c
ZY		 1528}
1529
bb8c093b 1530static void iwl4965_free_frame(struct iwl4965_priv *priv, struct iwl4965_frame *frame)
b481de9c
ZY		 1531{
1532 memset(frame, 0, sizeof(*frame));
1533 list_add(&frame->list, &priv->free_frames);
1534}
1535
bb8c093b 1536unsigned int iwl4965_fill_beacon_frame(struct iwl4965_priv *priv,
b481de9c
ZY		 1537 struct ieee80211_hdr *hdr,
1538 const u8 *dest, int left)
1539{
1540
bb8c093b 1541 if (!iwl4965_is_associated(priv) || !priv->ibss_beacon ||
b481de9c
ZY		 1542 ((priv->iw_mode != IEEE80211_IF_TYPE_IBSS) &&
1543 (priv->iw_mode != IEEE80211_IF_TYPE_AP)))
1544 return 0;
1545
1546 if (priv->ibss_beacon->len > left)
1547 return 0;
1548
1549 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
1550
1551 return priv->ibss_beacon->len;
1552}
1553
bb8c093b 1554int iwl4965_rate_index_from_plcp(int plcp)
b481de9c
ZY		 1555{
1556 int i = 0;
1557
77626355 1558 /* 4965 HT rate format */
b481de9c
ZY		 1559 if (plcp & RATE_MCS_HT_MSK) {
1560 i = (plcp & 0xff);
1561
1562 if (i >= IWL_RATE_MIMO_6M_PLCP)
1563 i = i - IWL_RATE_MIMO_6M_PLCP;
1564
1565 i += IWL_FIRST_OFDM_RATE;
1566 /* skip 9M not supported in ht*/
1567 if (i >= IWL_RATE_9M_INDEX)
1568 i += 1;
1569 if ((i >= IWL_FIRST_OFDM_RATE) &&
1570 (i <= IWL_LAST_OFDM_RATE))
1571 return i;
77626355
BC		 1572
1573 /* 4965 legacy rate format, search for match in table */
b481de9c 1574 } else {
bb8c093b
CH		 1575 for (i = 0; i < ARRAY_SIZE(iwl4965_rates); i++)
1576 if (iwl4965_rates[i].plcp == (plcp &0xFF))
b481de9c
ZY		 1577 return i;
1578 }
1579 return -1;
1580}
1581
bb8c093b 1582static u8 iwl4965_rate_get_lowest_plcp(int rate_mask)
b481de9c
ZY		 1583{
1584 u8 i;
1585
1586 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
bb8c093b 1587 i = iwl4965_rates[i].next_ieee) {
b481de9c 1588 if (rate_mask & (1 << i))
bb8c093b 1589 return iwl4965_rates[i].plcp;
b481de9c
ZY		 1590 }
1591
1592 return IWL_RATE_INVALID;
1593}
1594
bb8c093b 1595static int iwl4965_send_beacon_cmd(struct iwl4965_priv *priv)
b481de9c 1596{
bb8c093b 1597 struct iwl4965_frame *frame;
b481de9c
ZY		 1598 unsigned int frame_size;
1599 int rc;
1600 u8 rate;
1601
bb8c093b 1602 frame = iwl4965_get_free_frame(priv);
b481de9c
ZY		 1603
1604 if (!frame) {
1605 IWL_ERROR("Could not obtain free frame buffer for beacon "
1606 "command.\n");
1607 return -ENOMEM;
1608 }
1609
1610 if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) {
bb8c093b 1611 rate = iwl4965_rate_get_lowest_plcp(priv->active_rate_basic &
b481de9c
ZY		 1612 0xFF0);
1613 if (rate == IWL_INVALID_RATE)
1614 rate = IWL_RATE_6M_PLCP;
1615 } else {
bb8c093b 1616 rate = iwl4965_rate_get_lowest_plcp(priv->active_rate_basic & 0xF);
b481de9c
ZY		 1617 if (rate == IWL_INVALID_RATE)
1618 rate = IWL_RATE_1M_PLCP;
1619 }
1620
bb8c093b 1621 frame_size = iwl4965_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 1622
bb8c093b 1623 rc = iwl4965_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY		 1624 &frame->u.cmd[0]);
1625
bb8c093b 1626 iwl4965_free_frame(priv, frame);
b481de9c
ZY		 1627
1628 return rc;
1629}
1630
1631/******************************************************************************
1632 *
1633 * EEPROM related functions
1634 *
1635 ******************************************************************************/
1636
bb8c093b 1637static void get_eeprom_mac(struct iwl4965_priv *priv, u8 *mac)
b481de9c
ZY		 1638{
1639 memcpy(mac, priv->eeprom.mac_address, 6);
1640}
1641
74a3a250
RC		 1642static inline void iwl4965_eeprom_release_semaphore(struct iwl4965_priv *priv)
1643{
1644 iwl4965_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1645 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
1646}
1647
b481de9c 1648/**
bb8c093b 1649 * iwl4965_eeprom_init - read EEPROM contents
b481de9c 1650 *
6440adb5 1651 * Load the EEPROM contents from adapter into priv->eeprom
b481de9c
ZY		 1652 *
1653 * NOTE: This routine uses the non-debug IO access functions.
1654 */
bb8c093b 1655int iwl4965_eeprom_init(struct iwl4965_priv *priv)
b481de9c 1656{
0e5ce1f3 1657 __le16 *e = (__le16 *)&priv->eeprom;
bb8c093b 1658 u32 gp = iwl4965_read32(priv, CSR_EEPROM_GP);
b481de9c
ZY		 1659 u32 r;
1660 int sz = sizeof(priv->eeprom);
1661 int rc;
1662 int i;
1663 u16 addr;
1664
1665 /* The EEPROM structure has several padding buffers within it
1666 * and when adding new EEPROM maps is subject to programmer errors
1667 * which may be very difficult to identify without explicitly
1668 * checking the resulting size of the eeprom map. */
1669 BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
1670
1671 if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
1672 IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp);
1673 return -ENOENT;
1674 }
1675
6440adb5 1676 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
bb8c093b 1677 rc = iwl4965_eeprom_acquire_semaphore(priv);
b481de9c 1678 if (rc < 0) {
91e17473 1679 IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
b481de9c
ZY		 1680 return -ENOENT;
1681 }
1682
1683 /* eeprom is an array of 16bit values */
1684 for (addr = 0; addr < sz; addr += sizeof(u16)) {
bb8c093b
CH		 1685 _iwl4965_write32(priv, CSR_EEPROM_REG, addr << 1);
1686 _iwl4965_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
b481de9c
ZY		 1687
1688 for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
1689 i += IWL_EEPROM_ACCESS_DELAY) {
bb8c093b 1690 r = _iwl4965_read_direct32(priv, CSR_EEPROM_REG);
b481de9c
ZY		 1691 if (r & CSR_EEPROM_REG_READ_VALID_MSK)
1692 break;
1693 udelay(IWL_EEPROM_ACCESS_DELAY);
1694 }
1695
1696 if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) {
1697 IWL_ERROR("Time out reading EEPROM[%d]", addr);
1698 rc = -ETIMEDOUT;
1699 goto done;
1700 }
0e5ce1f3 1701 e[addr / 2] = cpu_to_le16(r >> 16);
b481de9c
ZY		 1702 }
1703 rc = 0;
1704
1705done:
bb8c093b 1706 iwl4965_eeprom_release_semaphore(priv);
b481de9c
ZY		 1707 return rc;
1708}
1709
1710/******************************************************************************
1711 *
1712 * Misc. internal state and helper functions
1713 *
1714 ******************************************************************************/
c8b0e6e1 1715#ifdef CONFIG_IWL4965_DEBUG
b481de9c
ZY		 1716
1717/**
bb8c093b 1718 * iwl4965_report_frame - dump frame to syslog during debug sessions
b481de9c 1719 *
9fbab516 1720 * You may hack this function to show different aspects of received frames,
b481de9c
ZY		 1721 * including selective frame dumps.
1722 * group100 parameter selects whether to show 1 out of 100 good frames.
1723 *
9fbab516
BC		 1724 * TODO: This was originally written for 3945, need to audit for
1725 * proper operation with 4965.
b481de9c 1726 */
bb8c093b
CH		 1727void iwl4965_report_frame(struct iwl4965_priv *priv,
1728 struct iwl4965_rx_packet *pkt,
b481de9c
ZY		 1729 struct ieee80211_hdr *header, int group100)
1730{
1731 u32 to_us;
1732 u32 print_summary = 0;
1733 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
1734 u32 hundred = 0;
1735 u32 dataframe = 0;
1736 u16 fc;
1737 u16 seq_ctl;
1738 u16 channel;
1739 u16 phy_flags;
1740 int rate_sym;
1741 u16 length;
1742 u16 status;
1743 u16 bcn_tmr;
1744 u32 tsf_low;
1745 u64 tsf;
1746 u8 rssi;
1747 u8 agc;
1748 u16 sig_avg;
1749 u16 noise_diff;
bb8c093b
CH		 1750 struct iwl4965_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
1751 struct iwl4965_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
1752 struct iwl4965_rx_frame_end *rx_end = IWL_RX_END(pkt);
b481de9c
ZY		 1753 u8 *data = IWL_RX_DATA(pkt);
1754
1755 /* MAC header */
1756 fc = le16_to_cpu(header->frame_control);
1757 seq_ctl = le16_to_cpu(header->seq_ctrl);
1758
1759 /* metadata */
1760 channel = le16_to_cpu(rx_hdr->channel);
1761 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
1762 rate_sym = rx_hdr->rate;
1763 length = le16_to_cpu(rx_hdr->len);
1764
1765 /* end-of-frame status and timestamp */
1766 status = le32_to_cpu(rx_end->status);
1767 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
1768 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
1769 tsf = le64_to_cpu(rx_end->timestamp);
1770
1771 /* signal statistics */
1772 rssi = rx_stats->rssi;
1773 agc = rx_stats->agc;
1774 sig_avg = le16_to_cpu(rx_stats->sig_avg);
1775 noise_diff = le16_to_cpu(rx_stats->noise_diff);
1776
1777 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
1778
1779 /* if data frame is to us and all is good,
1780 * (optionally) print summary for only 1 out of every 100 */
1781 if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
1782 (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
1783 dataframe = 1;
1784 if (!group100)
1785 print_summary = 1; /* print each frame */
1786 else if (priv->framecnt_to_us < 100) {
1787 priv->framecnt_to_us++;
1788 print_summary = 0;
1789 } else {
1790 priv->framecnt_to_us = 0;
1791 print_summary = 1;
1792 hundred = 1;
1793 }
1794 } else {
1795 /* print summary for all other frames */
1796 print_summary = 1;
1797 }
1798
1799 if (print_summary) {
1800 char *title;
1801 u32 rate;
1802
1803 if (hundred)
1804 title = "100Frames";
1805 else if (fc & IEEE80211_FCTL_RETRY)
1806 title = "Retry";
1807 else if (ieee80211_is_assoc_response(fc))
1808 title = "AscRsp";
1809 else if (ieee80211_is_reassoc_response(fc))
1810 title = "RasRsp";
1811 else if (ieee80211_is_probe_response(fc)) {
1812 title = "PrbRsp";
1813 print_dump = 1; /* dump frame contents */
1814 } else if (ieee80211_is_beacon(fc)) {
1815 title = "Beacon";
1816 print_dump = 1; /* dump frame contents */
1817 } else if (ieee80211_is_atim(fc))
1818 title = "ATIM";
1819 else if (ieee80211_is_auth(fc))
1820 title = "Auth";
1821 else if (ieee80211_is_deauth(fc))
1822 title = "DeAuth";
1823 else if (ieee80211_is_disassoc(fc))
1824 title = "DisAssoc";
1825 else
1826 title = "Frame";
1827
bb8c093b 1828 rate = iwl4965_rate_index_from_plcp(rate_sym);
b481de9c
ZY		 1829 if (rate == -1)
1830 rate = 0;
1831 else
bb8c093b 1832 rate = iwl4965_rates[rate].ieee / 2;
b481de9c
ZY		 1833
1834 /* print frame summary.
1835 * MAC addresses show just the last byte (for brevity),
1836 * but you can hack it to show more, if you'd like to. */
1837 if (dataframe)
1838 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
1839 "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
1840 title, fc, header->addr1[5],
1841 length, rssi, channel, rate);
1842 else {
1843 /* src/dst addresses assume managed mode */
1844 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
1845 "src=0x%02x, rssi=%u, tim=%lu usec, "
1846 "phy=0x%02x, chnl=%d\n",
1847 title, fc, header->addr1[5],
1848 header->addr3[5], rssi,
1849 tsf_low - priv->scan_start_tsf,
1850 phy_flags, channel);
1851 }
1852 }
1853 if (print_dump)
bb8c093b 1854 iwl4965_print_hex_dump(IWL_DL_RX, data, length);
b481de9c
ZY		 1855}
1856#endif
1857
bb8c093b 1858static void iwl4965_unset_hw_setting(struct iwl4965_priv *priv)
b481de9c
ZY		 1859{
1860 if (priv->hw_setting.shared_virt)
1861 pci_free_consistent(priv->pci_dev,
bb8c093b 1862 sizeof(struct iwl4965_shared),
b481de9c
ZY		 1863 priv->hw_setting.shared_virt,
1864 priv->hw_setting.shared_phys);
1865}
1866
1867/**
bb8c093b 1868 * iwl4965_supported_rate_to_ie - fill in the supported rate in IE field
b481de9c
ZY		 1869 *
1870 * return : set the bit for each supported rate insert in ie
1871 */
bb8c093b 1872static u16 iwl4965_supported_rate_to_ie(u8 *ie, u16 supported_rate,
c7c46676 1873 u16 basic_rate, int *left)
b481de9c
ZY		 1874{
1875 u16 ret_rates = 0, bit;
1876 int i;
c7c46676
TW		 1877 u8 *cnt = ie;
1878 u8 *rates = ie + 1;
b481de9c
ZY		 1879
1880 for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
1881 if (bit & supported_rate) {
1882 ret_rates |= bit;
bb8c093b 1883 rates[*cnt] = iwl4965_rates[i].ieee |
c7c46676
TW		 1884 ((bit & basic_rate) ? 0x80 : 0x00);
1885 (*cnt)++;
1886 (*left)--;
1887 if ((*left <= 0) ||
1888 (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
b481de9c
ZY		 1889 break;
1890 }
1891 }
1892
1893 return ret_rates;
1894}
1895
c8b0e6e1 1896#ifdef CONFIG_IWL4965_HT
bb8c093b 1897void static iwl4965_set_ht_capab(struct ieee80211_hw *hw,
8fb88032
RR		 1898 struct ieee80211_ht_cap *ht_cap,
1899 u8 use_current_config);
b481de9c
ZY		 1900#endif
1901
1902/**
bb8c093b 1903 * iwl4965_fill_probe_req - fill in all required fields and IE for probe request
b481de9c 1904 */
bb8c093b 1905static u16 iwl4965_fill_probe_req(struct iwl4965_priv *priv,
b481de9c
ZY		 1906 struct ieee80211_mgmt *frame,
1907 int left, int is_direct)
1908{
1909 int len = 0;
1910 u8 *pos = NULL;
bee488db 1911 u16 active_rates, ret_rates, cck_rates, active_rate_basic;
8fb88032
RR		 1912#ifdef CONFIG_IWL4965_HT
1913 struct ieee80211_hw_mode *mode;
1914#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY		 1915
1916 /* Make sure there is enough space for the probe request,
1917 * two mandatory IEs and the data */
1918 left -= 24;
1919 if (left < 0)
1920 return 0;
1921 len += 24;
1922
1923 frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
bb8c093b 1924 memcpy(frame->da, iwl4965_broadcast_addr, ETH_ALEN);
b481de9c 1925 memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
bb8c093b 1926 memcpy(frame->bssid, iwl4965_broadcast_addr, ETH_ALEN);
b481de9c
ZY		 1927 frame->seq_ctrl = 0;
1928
1929 /* fill in our indirect SSID IE */
1930 /* ...next IE... */
1931
1932 left -= 2;
1933 if (left < 0)
1934 return 0;
1935 len += 2;
1936 pos = &(frame->u.probe_req.variable[0]);
1937 *pos++ = WLAN_EID_SSID;
1938 *pos++ = 0;
1939
1940 /* fill in our direct SSID IE... */
1941 if (is_direct) {
1942 /* ...next IE... */
1943 left -= 2 + priv->essid_len;
1944 if (left < 0)
1945 return 0;
1946 /* ... fill it in... */
1947 *pos++ = WLAN_EID_SSID;
1948 *pos++ = priv->essid_len;
1949 memcpy(pos, priv->essid, priv->essid_len);
1950 pos += priv->essid_len;
1951 len += 2 + priv->essid_len;
1952 }
1953
1954 /* fill in supported rate */
1955 /* ...next IE... */
1956 left -= 2;
1957 if (left < 0)
1958 return 0;
c7c46676 1959
b481de9c
ZY		 1960 /* ... fill it in... */
1961 *pos++ = WLAN_EID_SUPP_RATES;
1962 *pos = 0;
c7c46676 1963
bee488db 1964 /* exclude 60M rate */
1965 active_rates = priv->rates_mask;
1966 active_rates &= ~IWL_RATE_60M_MASK;
1967
1968 active_rate_basic = active_rates & IWL_BASIC_RATES_MASK;
b481de9c 1969
c7c46676 1970 cck_rates = IWL_CCK_RATES_MASK & active_rates;
bb8c093b 1971 ret_rates = iwl4965_supported_rate_to_ie(pos, cck_rates,
bee488db 1972 active_rate_basic, &left);
c7c46676
TW		 1973 active_rates &= ~ret_rates;
1974
bb8c093b 1975 ret_rates = iwl4965_supported_rate_to_ie(pos, active_rates,
bee488db 1976 active_rate_basic, &left);
c7c46676
TW		 1977 active_rates &= ~ret_rates;
1978
b481de9c
ZY		 1979 len += 2 + *pos;
1980 pos += (*pos) + 1;
c7c46676 1981 if (active_rates == 0)
b481de9c
ZY		 1982 goto fill_end;
1983
1984 /* fill in supported extended rate */
1985 /* ...next IE... */
1986 left -= 2;
1987 if (left < 0)
1988 return 0;
1989 /* ... fill it in... */
1990 *pos++ = WLAN_EID_EXT_SUPP_RATES;
1991 *pos = 0;
bb8c093b 1992 iwl4965_supported_rate_to_ie(pos, active_rates,
bee488db 1993 active_rate_basic, &left);
b481de9c
ZY		 1994 if (*pos > 0)
1995 len += 2 + *pos;
1996
c8b0e6e1 1997#ifdef CONFIG_IWL4965_HT
8fb88032
RR		 1998 mode = priv->hw->conf.mode;
1999 if (mode->ht_info.ht_supported) {
b481de9c
ZY		 2000 pos += (*pos) + 1;
2001 *pos++ = WLAN_EID_HT_CAPABILITY;
8fb88032
RR		 2002 *pos++ = sizeof(struct ieee80211_ht_cap);
2003 iwl4965_set_ht_capab(priv->hw,
2004 (struct ieee80211_ht_cap *)pos, 0);
2005 len += 2 + sizeof(struct ieee80211_ht_cap);
b481de9c 2006 }
c8b0e6e1 2007#endif /*CONFIG_IWL4965_HT */
b481de9c
ZY		 2008
2009 fill_end:
2010 return (u16)len;
2011}
2012
2013/*
2014 * QoS support
2015*/
c8b0e6e1 2016#ifdef CONFIG_IWL4965_QOS
bb8c093b
CH		 2017static int iwl4965_send_qos_params_command(struct iwl4965_priv *priv,
2018 struct iwl4965_qosparam_cmd *qos)
b481de9c
ZY		 2019{
2020
bb8c093b
CH		 2021 return iwl4965_send_cmd_pdu(priv, REPLY_QOS_PARAM,
2022 sizeof(struct iwl4965_qosparam_cmd), qos);
b481de9c
ZY		 2023}
2024
bb8c093b 2025static void iwl4965_reset_qos(struct iwl4965_priv *priv)
b481de9c
ZY		 2026{
2027 u16 cw_min = 15;
2028 u16 cw_max = 1023;
2029 u8 aifs = 2;
2030 u8 is_legacy = 0;
2031 unsigned long flags;
2032 int i;
2033
2034 spin_lock_irqsave(&priv->lock, flags);
2035 priv->qos_data.qos_active = 0;
2036
2037 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
2038 if (priv->qos_data.qos_enable)
2039 priv->qos_data.qos_active = 1;
2040 if (!(priv->active_rate & 0xfff0)) {
2041 cw_min = 31;
2042 is_legacy = 1;
2043 }
2044 } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
2045 if (priv->qos_data.qos_enable)
2046 priv->qos_data.qos_active = 1;
2047 } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
2048 cw_min = 31;
2049 is_legacy = 1;
2050 }
2051
2052 if (priv->qos_data.qos_active)
2053 aifs = 3;
2054
2055 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
2056 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
2057 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
2058 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
2059 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
2060
2061 if (priv->qos_data.qos_active) {
2062 i = 1;
2063 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
2064 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
2065 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
2066 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
2067 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
2068
2069 i = 2;
2070 priv->qos_data.def_qos_parm.ac[i].cw_min =
2071 cpu_to_le16((cw_min + 1) / 2 - 1);
2072 priv->qos_data.def_qos_parm.ac[i].cw_max =
2073 cpu_to_le16(cw_max);
2074 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
2075 if (is_legacy)
2076 priv->qos_data.def_qos_parm.ac[i].edca_txop =
2077 cpu_to_le16(6016);
2078 else
2079 priv->qos_data.def_qos_parm.ac[i].edca_txop =
2080 cpu_to_le16(3008);
2081 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
2082
2083 i = 3;
2084 priv->qos_data.def_qos_parm.ac[i].cw_min =
2085 cpu_to_le16((cw_min + 1) / 4 - 1);
2086 priv->qos_data.def_qos_parm.ac[i].cw_max =
2087 cpu_to_le16((cw_max + 1) / 2 - 1);
2088 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
2089 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
2090 if (is_legacy)
2091 priv->qos_data.def_qos_parm.ac[i].edca_txop =
2092 cpu_to_le16(3264);
2093 else
2094 priv->qos_data.def_qos_parm.ac[i].edca_txop =
2095 cpu_to_le16(1504);
2096 } else {
2097 for (i = 1; i < 4; i++) {
2098 priv->qos_data.def_qos_parm.ac[i].cw_min =
2099 cpu_to_le16(cw_min);
2100 priv->qos_data.def_qos_parm.ac[i].cw_max =
2101 cpu_to_le16(cw_max);
2102 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
2103 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
2104 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
2105 }
2106 }
2107 IWL_DEBUG_QOS("set QoS to default \n");
2108
2109 spin_unlock_irqrestore(&priv->lock, flags);
2110}
2111
bb8c093b 2112static void iwl4965_activate_qos(struct iwl4965_priv *priv, u8 force)
b481de9c
ZY		 2113{
2114 unsigned long flags;
2115
b481de9c
ZY		 2116 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2117 return;
2118
2119 if (!priv->qos_data.qos_enable)
2120 return;
2121
2122 spin_lock_irqsave(&priv->lock, flags);
2123 priv->qos_data.def_qos_parm.qos_flags = 0;
2124
2125 if (priv->qos_data.qos_cap.q_AP.queue_request &&
2126 !priv->qos_data.qos_cap.q_AP.txop_request)
2127 priv->qos_data.def_qos_parm.qos_flags |=
2128 QOS_PARAM_FLG_TXOP_TYPE_MSK;
b481de9c
ZY		 2129 if (priv->qos_data.qos_active)
2130 priv->qos_data.def_qos_parm.qos_flags |=
2131 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
2132
c8b0e6e1 2133#ifdef CONFIG_IWL4965_HT
fd105e79 2134 if (priv->current_ht_config.is_ht)
f1f1f5c7 2135 priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
c8b0e6e1 2136#endif /* CONFIG_IWL4965_HT */
f1f1f5c7 2137
b481de9c
ZY		 2138 spin_unlock_irqrestore(&priv->lock, flags);
2139
bb8c093b 2140 if (force || iwl4965_is_associated(priv)) {
f1f1f5c7
TW		 2141 IWL_DEBUG_QOS("send QoS cmd with Qos active=%d FLAGS=0x%X\n",
2142 priv->qos_data.qos_active,
2143 priv->qos_data.def_qos_parm.qos_flags);
b481de9c 2144
bb8c093b 2145 iwl4965_send_qos_params_command(priv,
b481de9c
ZY		 2146 &(priv->qos_data.def_qos_parm));
2147 }
2148}
2149
c8b0e6e1 2150#endif /* CONFIG_IWL4965_QOS */
b481de9c
ZY		 2151/*
2152 * Power management (not Tx power!) functions
2153 */
2154#define MSEC_TO_USEC 1024
2155
2156#define NOSLP __constant_cpu_to_le16(0), 0, 0
2157#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
2158#define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
2159#define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
2160 __constant_cpu_to_le32(X1), \
2161 __constant_cpu_to_le32(X2), \
2162 __constant_cpu_to_le32(X3), \
2163 __constant_cpu_to_le32(X4)}
2164
2165
2166/* default power management (not Tx power) table values */
2167/* for tim 0-10 */
bb8c093b 2168static struct iwl4965_power_vec_entry range_0[IWL_POWER_AC] = {
b481de9c
ZY		 2169 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
2170 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
2171 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
2172 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
2173 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
2174 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
2175};
2176
2177/* for tim > 10 */
bb8c093b 2178static struct iwl4965_power_vec_entry range_1[IWL_POWER_AC] = {
b481de9c
ZY		 2179 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
2180 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
2181 SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
2182 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
2183 SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
2184 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
2185 SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
2186 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
2187 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
2188 SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
2189};
2190
bb8c093b 2191int iwl4965_power_init_handle(struct iwl4965_priv *priv)
b481de9c
ZY		 2192{
2193 int rc = 0, i;
bb8c093b
CH		 2194 struct iwl4965_power_mgr *pow_data;
2195 int size = sizeof(struct iwl4965_power_vec_entry) * IWL_POWER_AC;
b481de9c
ZY		 2196 u16 pci_pm;
2197
2198 IWL_DEBUG_POWER("Initialize power \n");
2199
2200 pow_data = &(priv->power_data);
2201
2202 memset(pow_data, 0, sizeof(*pow_data));
2203
2204 pow_data->active_index = IWL_POWER_RANGE_0;
2205 pow_data->dtim_val = 0xffff;
2206
2207 memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
2208 memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
2209
2210 rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
2211 if (rc != 0)
2212 return 0;
2213 else {
bb8c093b 2214 struct iwl4965_powertable_cmd *cmd;
b481de9c
ZY		 2215
2216 IWL_DEBUG_POWER("adjust power command flags\n");
2217
2218 for (i = 0; i < IWL_POWER_AC; i++) {
2219 cmd = &pow_data->pwr_range_0[i].cmd;
2220
2221 if (pci_pm & 0x1)
2222 cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
2223 else
2224 cmd->flags |= IWL_POWER_PCI_PM_MSK;
2225 }
2226 }
2227 return rc;
2228}
2229
bb8c093b
CH		 2230static int iwl4965_update_power_cmd(struct iwl4965_priv *priv,
2231 struct iwl4965_powertable_cmd *cmd, u32 mode)
b481de9c
ZY		 2232{
2233 int rc = 0, i;
2234 u8 skip;
2235 u32 max_sleep = 0;
bb8c093b 2236 struct iwl4965_power_vec_entry *range;
b481de9c 2237 u8 period = 0;
bb8c093b 2238 struct iwl4965_power_mgr *pow_data;
b481de9c
ZY		 2239
2240 if (mode > IWL_POWER_INDEX_5) {
2241 IWL_DEBUG_POWER("Error invalid power mode \n");
2242 return -1;
2243 }
2244 pow_data = &(priv->power_data);
2245
2246 if (pow_data->active_index == IWL_POWER_RANGE_0)
2247 range = &pow_data->pwr_range_0[0];
2248 else
2249 range = &pow_data->pwr_range_1[1];
2250
bb8c093b 2251 memcpy(cmd, &range[mode].cmd, sizeof(struct iwl4965_powertable_cmd));
b481de9c
ZY		 2252
2253#ifdef IWL_MAC80211_DISABLE
2254 if (priv->assoc_network != NULL) {
2255 unsigned long flags;
2256
2257 period = priv->assoc_network->tim.tim_period;
2258 }
2259#endif /*IWL_MAC80211_DISABLE */
2260 skip = range[mode].no_dtim;
2261
2262 if (period == 0) {
2263 period = 1;
2264 skip = 0;
2265 }
2266
2267 if (skip == 0) {
2268 max_sleep = period;
2269 cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
2270 } else {
2271 __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
2272 max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
2273 cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
2274 }
2275
2276 for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
2277 if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
2278 cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
2279 }
2280
2281 IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
2282 IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
2283 IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
2284 IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
2285 le32_to_cpu(cmd->sleep_interval[0]),
2286 le32_to_cpu(cmd->sleep_interval[1]),
2287 le32_to_cpu(cmd->sleep_interval[2]),
2288 le32_to_cpu(cmd->sleep_interval[3]),
2289 le32_to_cpu(cmd->sleep_interval[4]));
2290
2291 return rc;
2292}
2293
bb8c093b 2294static int iwl4965_send_power_mode(struct iwl4965_priv *priv, u32 mode)
b481de9c 2295{
9a62f73b 2296 u32 uninitialized_var(final_mode);
b481de9c 2297 int rc;
bb8c093b 2298 struct iwl4965_powertable_cmd cmd;
b481de9c
ZY		 2299
2300 /* If on battery, set to 3,
01ebd063 2301 * if plugged into AC power, set to CAM ("continuously aware mode"),
b481de9c
ZY		 2302 * else user level */
2303 switch (mode) {
2304 case IWL_POWER_BATTERY:
2305 final_mode = IWL_POWER_INDEX_3;
2306 break;
2307 case IWL_POWER_AC:
2308 final_mode = IWL_POWER_MODE_CAM;
2309 break;
2310 default:
2311 final_mode = mode;
2312 break;
2313 }
2314
2315 cmd.keep_alive_beacons = 0;
2316
bb8c093b 2317 iwl4965_update_power_cmd(priv, &cmd, final_mode);
b481de9c 2318
bb8c093b 2319 rc = iwl4965_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
b481de9c
ZY		 2320
2321 if (final_mode == IWL_POWER_MODE_CAM)
2322 clear_bit(STATUS_POWER_PMI, &priv->status);
2323 else
2324 set_bit(STATUS_POWER_PMI, &priv->status);
2325
2326 return rc;
2327}
2328
bb8c093b 2329int iwl4965_is_network_packet(struct iwl4965_priv *priv, struct ieee80211_hdr *header)
b481de9c
ZY		 2330{
2331 /* Filter incoming packets to determine if they are targeted toward
2332 * this network, discarding packets coming from ourselves */
2333 switch (priv->iw_mode) {
2334 case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */
2335 /* packets from our adapter are dropped (echo) */
2336 if (!compare_ether_addr(header->addr2, priv->mac_addr))
2337 return 0;
2338 /* {broad,multi}cast packets to our IBSS go through */
2339 if (is_multicast_ether_addr(header->addr1))
2340 return !compare_ether_addr(header->addr3, priv->bssid);
2341 /* packets to our adapter go through */
2342 return !compare_ether_addr(header->addr1, priv->mac_addr);
2343 case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */
2344 /* packets from our adapter are dropped (echo) */
2345 if (!compare_ether_addr(header->addr3, priv->mac_addr))
2346 return 0;
2347 /* {broad,multi}cast packets to our BSS go through */
2348 if (is_multicast_ether_addr(header->addr1))
2349 return !compare_ether_addr(header->addr2, priv->bssid);
2350 /* packets to our adapter go through */
2351 return !compare_ether_addr(header->addr1, priv->mac_addr);
2352 }
2353
2354 return 1;
2355}
2356
2357#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
2358
bb8c093b 2359static const char *iwl4965_get_tx_fail_reason(u32 status)
b481de9c
ZY		 2360{
2361 switch (status & TX_STATUS_MSK) {
2362 case TX_STATUS_SUCCESS:
2363 return "SUCCESS";
2364 TX_STATUS_ENTRY(SHORT_LIMIT);
2365 TX_STATUS_ENTRY(LONG_LIMIT);
2366 TX_STATUS_ENTRY(FIFO_UNDERRUN);
2367 TX_STATUS_ENTRY(MGMNT_ABORT);
2368 TX_STATUS_ENTRY(NEXT_FRAG);
2369 TX_STATUS_ENTRY(LIFE_EXPIRE);
2370 TX_STATUS_ENTRY(DEST_PS);
2371 TX_STATUS_ENTRY(ABORTED);
2372 TX_STATUS_ENTRY(BT_RETRY);
2373 TX_STATUS_ENTRY(STA_INVALID);
2374 TX_STATUS_ENTRY(FRAG_DROPPED);
2375 TX_STATUS_ENTRY(TID_DISABLE);
2376 TX_STATUS_ENTRY(FRAME_FLUSHED);
2377 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
2378 TX_STATUS_ENTRY(TX_LOCKED);
2379 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
2380 }
2381
2382 return "UNKNOWN";
2383}
2384
2385/**
bb8c093b 2386 * iwl4965_scan_cancel - Cancel any currently executing HW scan
b481de9c
ZY		 2387 *
2388 * NOTE: priv->mutex is not required before calling this function
2389 */
bb8c093b 2390static int iwl4965_scan_cancel(struct iwl4965_priv *priv)
b481de9c
ZY		 2391{
2392 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
2393 clear_bit(STATUS_SCANNING, &priv->status);
2394 return 0;
2395 }
2396
2397 if (test_bit(STATUS_SCANNING, &priv->status)) {
2398 if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2399 IWL_DEBUG_SCAN("Queuing scan abort.\n");
2400 set_bit(STATUS_SCAN_ABORTING, &priv->status);
2401 queue_work(priv->workqueue, &priv->abort_scan);
2402
2403 } else
2404 IWL_DEBUG_SCAN("Scan abort already in progress.\n");
2405
2406 return test_bit(STATUS_SCANNING, &priv->status);
2407 }
2408
2409 return 0;
2410}
2411
2412/**
bb8c093b 2413 * iwl4965_scan_cancel_timeout - Cancel any currently executing HW scan
b481de9c
ZY		 2414 * @ms: amount of time to wait (in milliseconds) for scan to abort
2415 *
2416 * NOTE: priv->mutex must be held before calling this function
2417 */
bb8c093b 2418static int iwl4965_scan_cancel_timeout(struct iwl4965_priv *priv, unsigned long ms)
b481de9c
ZY		 2419{
2420 unsigned long now = jiffies;
2421 int ret;
2422
bb8c093b 2423 ret = iwl4965_scan_cancel(priv);
b481de9c
ZY		 2424 if (ret && ms) {
2425 mutex_unlock(&priv->mutex);
2426 while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
2427 test_bit(STATUS_SCANNING, &priv->status))
2428 msleep(1);
2429 mutex_lock(&priv->mutex);
2430
2431 return test_bit(STATUS_SCANNING, &priv->status);
2432 }
2433
2434 return ret;
2435}
2436
bb8c093b 2437static void iwl4965_sequence_reset(struct iwl4965_priv *priv)
b481de9c
ZY		 2438{
2439 /* Reset ieee stats */
2440
2441 /* We don't reset the net_device_stats (ieee->stats) on
2442 * re-association */
2443
2444 priv->last_seq_num = -1;
2445 priv->last_frag_num = -1;
2446 priv->last_packet_time = 0;
2447
bb8c093b 2448 iwl4965_scan_cancel(priv);
b481de9c
ZY		 2449}
2450
2451#define MAX_UCODE_BEACON_INTERVAL 4096
2452#define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
2453
bb8c093b 2454static __le16 iwl4965_adjust_beacon_interval(u16 beacon_val)
b481de9c
ZY		 2455{
2456 u16 new_val = 0;
2457 u16 beacon_factor = 0;
2458
2459 beacon_factor =
2460 (beacon_val + MAX_UCODE_BEACON_INTERVAL)
2461 / MAX_UCODE_BEACON_INTERVAL;
2462 new_val = beacon_val / beacon_factor;
2463
2464 return cpu_to_le16(new_val);
2465}
2466
bb8c093b 2467static void iwl4965_setup_rxon_timing(struct iwl4965_priv *priv)
b481de9c
ZY		 2468{
2469 u64 interval_tm_unit;
2470 u64 tsf, result;
2471 unsigned long flags;
2472 struct ieee80211_conf *conf = NULL;
2473 u16 beacon_int = 0;
2474
2475 conf = ieee80211_get_hw_conf(priv->hw);
2476
2477 spin_lock_irqsave(&priv->lock, flags);
2478 priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
2479 priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
2480
2481 priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
2482
2483 tsf = priv->timestamp1;
2484 tsf = ((tsf << 32) | priv->timestamp0);
2485
2486 beacon_int = priv->beacon_int;
2487 spin_unlock_irqrestore(&priv->lock, flags);
2488
2489 if (priv->iw_mode == IEEE80211_IF_TYPE_STA) {
2490 if (beacon_int == 0) {
2491 priv->rxon_timing.beacon_interval = cpu_to_le16(100);
2492 priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
2493 } else {
2494 priv->rxon_timing.beacon_interval =
2495 cpu_to_le16(beacon_int);
2496 priv->rxon_timing.beacon_interval =
bb8c093b 2497 iwl4965_adjust_beacon_interval(
b481de9c
ZY		 2498 le16_to_cpu(priv->rxon_timing.beacon_interval));
2499 }
2500
2501 priv->rxon_timing.atim_window = 0;
2502 } else {
2503 priv->rxon_timing.beacon_interval =
bb8c093b 2504 iwl4965_adjust_beacon_interval(conf->beacon_int);
b481de9c
ZY		 2505 /* TODO: we need to get atim_window from upper stack
2506 * for now we set to 0 */
2507 priv->rxon_timing.atim_window = 0;
2508 }
2509
2510 interval_tm_unit =
2511 (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
2512 result = do_div(tsf, interval_tm_unit);
2513 priv->rxon_timing.beacon_init_val =
2514 cpu_to_le32((u32) ((u64) interval_tm_unit - result));
2515
2516 IWL_DEBUG_ASSOC
2517 ("beacon interval %d beacon timer %d beacon tim %d\n",
2518 le16_to_cpu(priv->rxon_timing.beacon_interval),
2519 le32_to_cpu(priv->rxon_timing.beacon_init_val),
2520 le16_to_cpu(priv->rxon_timing.atim_window));
2521}
2522
bb8c093b 2523static int iwl4965_scan_initiate(struct iwl4965_priv *priv)
b481de9c
ZY		 2524{
2525 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
2526 IWL_ERROR("APs don't scan.\n");
2527 return 0;
2528 }
2529
bb8c093b 2530 if (!iwl4965_is_ready_rf(priv)) {
b481de9c
ZY		 2531 IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
2532 return -EIO;
2533 }
2534
2535 if (test_bit(STATUS_SCANNING, &priv->status)) {
2536 IWL_DEBUG_SCAN("Scan already in progress.\n");
2537 return -EAGAIN;
2538 }
2539
2540 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2541 IWL_DEBUG_SCAN("Scan request while abort pending. "
2542 "Queuing.\n");
2543 return -EAGAIN;
2544 }
2545
2546 IWL_DEBUG_INFO("Starting scan...\n");
2547 priv->scan_bands = 2;
2548 set_bit(STATUS_SCANNING, &priv->status);
2549 priv->scan_start = jiffies;
2550 priv->scan_pass_start = priv->scan_start;
2551
2552 queue_work(priv->workqueue, &priv->request_scan);
2553
2554 return 0;
2555}
2556
bb8c093b 2557static int iwl4965_set_rxon_hwcrypto(struct iwl4965_priv *priv, int hw_decrypt)
b481de9c 2558{
bb8c093b 2559 struct iwl4965_rxon_cmd *rxon = &priv->staging_rxon;
b481de9c
ZY		 2560
2561 if (hw_decrypt)
2562 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
2563 else
2564 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
2565
2566 return 0;
2567}
2568
bb8c093b 2569static void iwl4965_set_flags_for_phymode(struct iwl4965_priv *priv, u8 phymode)
b481de9c
ZY		 2570{
2571 if (phymode == MODE_IEEE80211A) {
2572 priv->staging_rxon.flags &=
2573 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
2574 | RXON_FLG_CCK_MSK);
2575 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2576 } else {
bb8c093b 2577 /* Copied from iwl4965_bg_post_associate() */
b481de9c
ZY		 2578 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2579 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2580 else
2581 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2582
2583 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
2584 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2585
2586 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
2587 priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
2588 priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
2589 }
2590}
2591
2592/*
01ebd063 2593 * initialize rxon structure with default values from eeprom
b481de9c 2594 */
bb8c093b 2595static void iwl4965_connection_init_rx_config(struct iwl4965_priv *priv)
b481de9c 2596{
bb8c093b 2597 const struct iwl4965_channel_info *ch_info;
b481de9c
ZY		 2598
2599 memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
2600
2601 switch (priv->iw_mode) {
2602 case IEEE80211_IF_TYPE_AP:
2603 priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
2604 break;
2605
2606 case IEEE80211_IF_TYPE_STA:
2607 priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
2608 priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
2609 break;
2610
2611 case IEEE80211_IF_TYPE_IBSS:
2612 priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
2613 priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
2614 priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
2615 RXON_FILTER_ACCEPT_GRP_MSK;
2616 break;
2617
2618 case IEEE80211_IF_TYPE_MNTR:
2619 priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
2620 priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
2621 RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
2622 break;
2623 }
2624
2625#if 0
2626 /* TODO: Figure out when short_preamble would be set and cache from
2627 * that */
2628 if (!hw_to_local(priv->hw)->short_preamble)
2629 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2630 else
2631 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2632#endif
2633
bb8c093b 2634 ch_info = iwl4965_get_channel_info(priv, priv->phymode,
b481de9c
ZY		 2635 le16_to_cpu(priv->staging_rxon.channel));
2636
2637 if (!ch_info)
2638 ch_info = &priv->channel_info[0];
2639
2640 /*
2641 * in some case A channels are all non IBSS
2642 * in this case force B/G channel
2643 */
2644 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
2645 !(is_channel_ibss(ch_info)))
2646 ch_info = &priv->channel_info[0];
2647
2648 priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
2649 if (is_channel_a_band(ch_info))
2650 priv->phymode = MODE_IEEE80211A;
2651 else
2652 priv->phymode = MODE_IEEE80211G;
2653
bb8c093b 2654 iwl4965_set_flags_for_phymode(priv, priv->phymode);
b481de9c
ZY		 2655
2656 priv->staging_rxon.ofdm_basic_rates =
2657 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2658 priv->staging_rxon.cck_basic_rates =
2659 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2660
2661 priv->staging_rxon.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
2662 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
2663 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2664 memcpy(priv->staging_rxon.wlap_bssid_addr, priv->mac_addr, ETH_ALEN);
2665 priv->staging_rxon.ofdm_ht_single_stream_basic_rates = 0xff;
2666 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates = 0xff;
2667 iwl4965_set_rxon_chain(priv);
2668}
2669
bb8c093b 2670static int iwl4965_set_mode(struct iwl4965_priv *priv, int mode)
b481de9c 2671{
b481de9c 2672 if (mode == IEEE80211_IF_TYPE_IBSS) {
bb8c093b 2673 const struct iwl4965_channel_info *ch_info;
b481de9c 2674
bb8c093b 2675 ch_info = iwl4965_get_channel_info(priv,
b481de9c
ZY		 2676 priv->phymode,
2677 le16_to_cpu(priv->staging_rxon.channel));
2678
2679 if (!ch_info || !is_channel_ibss(ch_info)) {
2680 IWL_ERROR("channel %d not IBSS channel\n",
2681 le16_to_cpu(priv->staging_rxon.channel));
2682 return -EINVAL;
2683 }
2684 }
2685
b481de9c
ZY		 2686 priv->iw_mode = mode;
2687
bb8c093b 2688 iwl4965_connection_init_rx_config(priv);
b481de9c
ZY		 2689 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2690
bb8c093b 2691 iwl4965_clear_stations_table(priv);
b481de9c 2692
fde3571f
MA		 2693 /* dont commit rxon if rf-kill is on*/
2694 if (!iwl4965_is_ready_rf(priv))
2695 return -EAGAIN;
2696
2697 cancel_delayed_work(&priv->scan_check);
2698 if (iwl4965_scan_cancel_timeout(priv, 100)) {
2699 IWL_WARNING("Aborted scan still in progress after 100ms\n");
2700 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
2701 return -EAGAIN;
2702 }
2703
bb8c093b 2704 iwl4965_commit_rxon(priv);
b481de9c
ZY		 2705
2706 return 0;
2707}
2708
bb8c093b 2709static void iwl4965_build_tx_cmd_hwcrypto(struct iwl4965_priv *priv,
b481de9c 2710 struct ieee80211_tx_control *ctl,
bb8c093b 2711 struct iwl4965_cmd *cmd,
b481de9c
ZY		 2712 struct sk_buff *skb_frag,
2713 int last_frag)
2714{
bb8c093b 2715 struct iwl4965_hw_key *keyinfo = &priv->stations[ctl->key_idx].keyinfo;
b481de9c
ZY		 2716
2717 switch (keyinfo->alg) {
2718 case ALG_CCMP:
2719 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
2720 memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
2721 IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
2722 break;
2723
2724 case ALG_TKIP:
2725#if 0
2726 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
2727
2728 if (last_frag)
2729 memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
2730 8);
2731 else
2732 memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
2733#endif
2734 break;
2735
2736 case ALG_WEP:
2737 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
2738 (ctl->key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
2739
2740 if (keyinfo->keylen == 13)
2741 cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
2742
2743 memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
2744
2745 IWL_DEBUG_TX("Configuring packet for WEP encryption "
2746 "with key %d\n", ctl->key_idx);
2747 break;
2748
b481de9c
ZY		 2749 default:
2750 printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
2751 break;
2752 }
2753}
2754
2755/*
2756 * handle build REPLY_TX command notification.
2757 */
bb8c093b
CH		 2758static void iwl4965_build_tx_cmd_basic(struct iwl4965_priv *priv,
2759 struct iwl4965_cmd *cmd,
b481de9c
ZY		 2760 struct ieee80211_tx_control *ctrl,
2761 struct ieee80211_hdr *hdr,
2762 int is_unicast, u8 std_id)
2763{
2764 __le16 *qc;
2765 u16 fc = le16_to_cpu(hdr->frame_control);
2766 __le32 tx_flags = cmd->cmd.tx.tx_flags;
2767
2768 cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2769 if (!(ctrl->flags & IEEE80211_TXCTL_NO_ACK)) {
2770 tx_flags |= TX_CMD_FLG_ACK_MSK;
2771 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
2772 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2773 if (ieee80211_is_probe_response(fc) &&
2774 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
2775 tx_flags |= TX_CMD_FLG_TSF_MSK;
2776 } else {
2777 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
2778 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2779 }
2780
87e4f7df
TW		 2781 if (ieee80211_is_back_request(fc))
2782 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
2783
2784
b481de9c
ZY		 2785 cmd->cmd.tx.sta_id = std_id;
2786 if (ieee80211_get_morefrag(hdr))
2787 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
2788
2789 qc = ieee80211_get_qos_ctrl(hdr);
2790 if (qc) {
2791 cmd->cmd.tx.tid_tspec = (u8) (le16_to_cpu(*qc) & 0xf);
2792 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
2793 } else
2794 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2795
2796 if (ctrl->flags & IEEE80211_TXCTL_USE_RTS_CTS) {
2797 tx_flags |= TX_CMD_FLG_RTS_MSK;
2798 tx_flags &= ~TX_CMD_FLG_CTS_MSK;
2799 } else if (ctrl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) {
2800 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2801 tx_flags |= TX_CMD_FLG_CTS_MSK;
2802 }
2803
2804 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
2805 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
2806
2807 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
2808 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) {
2809 if ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_REQ ||
2810 (fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_REASSOC_REQ)
bc434dd2 2811 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
b481de9c 2812 else
bc434dd2 2813 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
b481de9c
ZY		 2814 } else
2815 cmd->cmd.tx.timeout.pm_frame_timeout = 0;
2816
2817 cmd->cmd.tx.driver_txop = 0;
2818 cmd->cmd.tx.tx_flags = tx_flags;
2819 cmd->cmd.tx.next_frame_len = 0;
2820}
2821
6440adb5
CB		 2822/**
2823 * iwl4965_get_sta_id - Find station's index within station table
2824 *
2825 * If new IBSS station, create new entry in station table
2826 */
9fbab516
BC		 2827static int iwl4965_get_sta_id(struct iwl4965_priv *priv,
2828 struct ieee80211_hdr *hdr)
b481de9c
ZY		 2829{
2830 int sta_id;
2831 u16 fc = le16_to_cpu(hdr->frame_control);
0795af57 2832 DECLARE_MAC_BUF(mac);
b481de9c 2833
6440adb5 2834 /* If this frame is broadcast or management, use broadcast station id */
b481de9c
ZY		 2835 if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
2836 is_multicast_ether_addr(hdr->addr1))
2837 return priv->hw_setting.bcast_sta_id;
2838
2839 switch (priv->iw_mode) {
2840
6440adb5
CB		 2841 /* If we are a client station in a BSS network, use the special
2842 * AP station entry (that's the only station we communicate with) */
b481de9c
ZY		 2843 case IEEE80211_IF_TYPE_STA:
2844 return IWL_AP_ID;
2845
2846 /* If we are an AP, then find the station, or use BCAST */
2847 case IEEE80211_IF_TYPE_AP:
bb8c093b 2848 sta_id = iwl4965_hw_find_station(priv, hdr->addr1);
b481de9c
ZY		 2849 if (sta_id != IWL_INVALID_STATION)
2850 return sta_id;
2851 return priv->hw_setting.bcast_sta_id;
2852
6440adb5
CB		 2853 /* If this frame is going out to an IBSS network, find the station,
2854 * or create a new station table entry */
b481de9c 2855 case IEEE80211_IF_TYPE_IBSS:
bb8c093b 2856 sta_id = iwl4965_hw_find_station(priv, hdr->addr1);
b481de9c
ZY		 2857 if (sta_id != IWL_INVALID_STATION)
2858 return sta_id;
2859
6440adb5 2860 /* Create new station table entry */
67d62035
RR		 2861 sta_id = iwl4965_add_station_flags(priv, hdr->addr1,
2862 0, CMD_ASYNC, NULL);
b481de9c
ZY		 2863
2864 if (sta_id != IWL_INVALID_STATION)
2865 return sta_id;
2866
0795af57 2867 IWL_DEBUG_DROP("Station %s not in station map. "
b481de9c 2868 "Defaulting to broadcast...\n",
0795af57 2869 print_mac(mac, hdr->addr1));
bb8c093b 2870 iwl4965_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
b481de9c
ZY		 2871 return priv->hw_setting.bcast_sta_id;
2872
2873 default:
01ebd063 2874 IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode);
b481de9c
ZY		 2875 return priv->hw_setting.bcast_sta_id;
2876 }
2877}
2878
2879/*
2880 * start REPLY_TX command process
2881 */
bb8c093b 2882static int iwl4965_tx_skb(struct iwl4965_priv *priv,
b481de9c
ZY		 2883 struct sk_buff *skb, struct ieee80211_tx_control *ctl)
2884{
2885 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
bb8c093b 2886 struct iwl4965_tfd_frame *tfd;
b481de9c
ZY		 2887 u32 *control_flags;
2888 int txq_id = ctl->queue;
bb8c093b
CH		 2889 struct iwl4965_tx_queue *txq = NULL;
2890 struct iwl4965_queue *q = NULL;
b481de9c
ZY		 2891 dma_addr_t phys_addr;
2892 dma_addr_t txcmd_phys;
87e4f7df 2893 dma_addr_t scratch_phys;
bb8c093b 2894 struct iwl4965_cmd *out_cmd = NULL;
b481de9c
ZY		 2895 u16 len, idx, len_org;
2896 u8 id, hdr_len, unicast;
2897 u8 sta_id;
2898 u16 seq_number = 0;
2899 u16 fc;
2900 __le16 *qc;
2901 u8 wait_write_ptr = 0;
2902 unsigned long flags;
2903 int rc;
2904
2905 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2906 if (iwl4965_is_rfkill(priv)) {
b481de9c
ZY		 2907 IWL_DEBUG_DROP("Dropping - RF KILL\n");
2908 goto drop_unlock;
2909 }
2910
32bfd35d
JB		 2911 if (!priv->vif) {
2912 IWL_DEBUG_DROP("Dropping - !priv->vif\n");
b481de9c
ZY		 2913 goto drop_unlock;
2914 }
2915
2916 if ((ctl->tx_rate & 0xFF) == IWL_INVALID_RATE) {
2917 IWL_ERROR("ERROR: No TX rate available.\n");
2918 goto drop_unlock;
2919 }
2920
2921 unicast = !is_multicast_ether_addr(hdr->addr1);
2922 id = 0;
2923
2924 fc = le16_to_cpu(hdr->frame_control);
2925
c8b0e6e1 2926#ifdef CONFIG_IWL4965_DEBUG
b481de9c
ZY		 2927 if (ieee80211_is_auth(fc))
2928 IWL_DEBUG_TX("Sending AUTH frame\n");
2929 else if (ieee80211_is_assoc_request(fc))
2930 IWL_DEBUG_TX("Sending ASSOC frame\n");
2931 else if (ieee80211_is_reassoc_request(fc))
2932 IWL_DEBUG_TX("Sending REASSOC frame\n");
2933#endif
2934
7878a5a4
MA		 2935 /* drop all data frame if we are not associated */
2936 if (!iwl4965_is_associated(priv) && !priv->assoc_id &&
b481de9c 2937 ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA)) {
bb8c093b 2938 IWL_DEBUG_DROP("Dropping - !iwl4965_is_associated\n");
b481de9c
ZY		 2939 goto drop_unlock;
2940 }
2941
2942 spin_unlock_irqrestore(&priv->lock, flags);
2943
2944 hdr_len = ieee80211_get_hdrlen(fc);
6440adb5
CB		 2945
2946 /* Find (or create) index into station table for destination station */
bb8c093b 2947 sta_id = iwl4965_get_sta_id(priv, hdr);
b481de9c 2948 if (sta_id == IWL_INVALID_STATION) {
0795af57
JP		 2949 DECLARE_MAC_BUF(mac);
2950
2951 IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
2952 print_mac(mac, hdr->addr1));
b481de9c
ZY		 2953 goto drop;
2954 }
2955
2956 IWL_DEBUG_RATE("station Id %d\n", sta_id);
2957
2958 qc = ieee80211_get_qos_ctrl(hdr);
2959 if (qc) {
2960 u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
2961 seq_number = priv->stations[sta_id].tid[tid].seq_number &
2962 IEEE80211_SCTL_SEQ;
2963 hdr->seq_ctrl = cpu_to_le16(seq_number) |
2964 (hdr->seq_ctrl &
2965 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
2966 seq_number += 0x10;
c8b0e6e1
CH		 2967#ifdef CONFIG_IWL4965_HT
2968#ifdef CONFIG_IWL4965_HT_AGG
b481de9c
ZY		 2969 /* aggregation is on for this <sta,tid> */
2970 if (ctl->flags & IEEE80211_TXCTL_HT_MPDU_AGG)
2971 txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
c8b0e6e1
CH		 2972#endif /* CONFIG_IWL4965_HT_AGG */
2973#endif /* CONFIG_IWL4965_HT */
b481de9c 2974 }
6440adb5
CB		 2975
2976 /* Descriptor for chosen Tx queue */
b481de9c
ZY		 2977 txq = &priv->txq[txq_id];
2978 q = &txq->q;
2979
2980 spin_lock_irqsave(&priv->lock, flags);
2981
6440adb5 2982 /* Set up first empty TFD within this queue's circular TFD buffer */
fc4b6853 2983 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY		 2984 memset(tfd, 0, sizeof(*tfd));
2985 control_flags = (u32 *) tfd;
fc4b6853 2986 idx = get_cmd_index(q, q->write_ptr, 0);
b481de9c 2987
6440adb5 2988 /* Set up driver data for this TFD */
bb8c093b 2989 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl4965_tx_info));
fc4b6853
TW		 2990 txq->txb[q->write_ptr].skb[0] = skb;
2991 memcpy(&(txq->txb[q->write_ptr].status.control),
b481de9c 2992 ctl, sizeof(struct ieee80211_tx_control));
6440adb5
CB		 2993
2994 /* Set up first empty entry in queue's array of Tx/cmd buffers */
b481de9c
ZY		 2995 out_cmd = &txq->cmd[idx];
2996 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
2997 memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
6440adb5
CB		 2998
2999 /*
3000 * Set up the Tx-command (not MAC!) header.
3001 * Store the chosen Tx queue and TFD index within the sequence field;
3002 * after Tx, uCode's Tx response will return this value so driver can
3003 * locate the frame within the tx queue and do post-tx processing.
3004 */
b481de9c
ZY		 3005 out_cmd->hdr.cmd = REPLY_TX;
3006 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
fc4b6853 3007 INDEX_TO_SEQ(q->write_ptr)));
6440adb5
CB		 3008
3009 /* Copy MAC header from skb into command buffer */
b481de9c
ZY		 3010 memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
3011
6440adb5
CB		 3012 /*
3013 * Use the first empty entry in this queue's command buffer array
3014 * to contain the Tx command and MAC header concatenated together
3015 * (payload data will be in another buffer).
3016 * Size of this varies, due to varying MAC header length.
3017 * If end is not dword aligned, we'll have 2 extra bytes at the end
3018 * of the MAC header (device reads on dword boundaries).
3019 * We'll tell device about this padding later.
3020 */
b481de9c 3021 len = priv->hw_setting.tx_cmd_len +
bb8c093b 3022 sizeof(struct iwl4965_cmd_header) + hdr_len;
b481de9c
ZY		 3023
3024 len_org = len;
3025 len = (len + 3) & ~3;
3026
3027 if (len_org != len)
3028 len_org = 1;
3029 else
3030 len_org = 0;
3031
6440adb5
CB		 3032 /* Physical address of this Tx command's header (not MAC header!),
3033 * within command buffer array. */
bb8c093b
CH		 3034 txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl4965_cmd) * idx +
3035 offsetof(struct iwl4965_cmd, hdr);
b481de9c 3036
6440adb5
CB		 3037 /* Add buffer containing Tx command and MAC(!) header to TFD's
3038 * first entry */
bb8c093b 3039 iwl4965_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
b481de9c
ZY		 3040
3041 if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT))
bb8c093b 3042 iwl4965_build_tx_cmd_hwcrypto(priv, ctl, out_cmd, skb, 0);
b481de9c 3043
6440adb5
CB		 3044 /* Set up TFD's 2nd entry to point directly to remainder of skb,
3045 * if any (802.11 null frames have no payload). */
b481de9c
ZY		 3046 len = skb->len - hdr_len;
3047 if (len) {
3048 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
3049 len, PCI_DMA_TODEVICE);
bb8c093b 3050 iwl4965_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
b481de9c
ZY		 3051 }
3052
6440adb5 3053 /* Tell 4965 about any 2-byte padding after MAC header */
b481de9c
ZY		 3054 if (len_org)
3055 out_cmd->cmd.tx.tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
3056
6440adb5 3057 /* Total # bytes to be transmitted */
b481de9c
ZY		 3058 len = (u16)skb->len;
3059 out_cmd->cmd.tx.len = cpu_to_le16(len);
3060
3061 /* TODO need this for burst mode later on */
bb8c093b 3062 iwl4965_build_tx_cmd_basic(priv, out_cmd, ctl, hdr, unicast, sta_id);
b481de9c
ZY		 3063
3064 /* set is_hcca to 0; it probably will never be implemented */
bb8c093b 3065 iwl4965_hw_build_tx_cmd_rate(priv, out_cmd, ctl, hdr, sta_id, 0);
b481de9c 3066
87e4f7df
TW		 3067 scratch_phys = txcmd_phys + sizeof(struct iwl4965_cmd_header) +
3068 offsetof(struct iwl4965_tx_cmd, scratch);
3069 out_cmd->cmd.tx.dram_lsb_ptr = cpu_to_le32(scratch_phys);
3070 out_cmd->cmd.tx.dram_msb_ptr = iwl_get_dma_hi_address(scratch_phys);
3071
3072#ifdef CONFIG_IWL4965_HT_AGG
3073#ifdef CONFIG_IWL4965_HT
3074 /* TODO: move this functionality to rate scaling */
3075 iwl4965_tl_get_stats(priv, hdr);
3076#endif /* CONFIG_IWL4965_HT_AGG */
3077#endif /*CONFIG_IWL4965_HT */
3078
b481de9c
ZY		 3079
3080 if (!ieee80211_get_morefrag(hdr)) {
3081 txq->need_update = 1;
3082 if (qc) {
3083 u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
3084 priv->stations[sta_id].tid[tid].seq_number = seq_number;
3085 }
3086 } else {
3087 wait_write_ptr = 1;
3088 txq->need_update = 0;
3089 }
3090
bb8c093b 3091 iwl4965_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
b481de9c
ZY		 3092 sizeof(out_cmd->cmd.tx));
3093
bb8c093b 3094 iwl4965_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
b481de9c
ZY		 3095 ieee80211_get_hdrlen(fc));
3096
6440adb5 3097 /* Set up entry for this TFD in Tx byte-count array */
b481de9c
ZY		 3098 iwl4965_tx_queue_update_wr_ptr(priv, txq, len);
3099
6440adb5 3100 /* Tell device the write index *just past* this latest filled TFD */
bb8c093b
CH		 3101 q->write_ptr = iwl4965_queue_inc_wrap(q->write_ptr, q->n_bd);
3102 rc = iwl4965_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 3103 spin_unlock_irqrestore(&priv->lock, flags);
3104
3105 if (rc)
3106 return rc;
3107
bb8c093b 3108 if ((iwl4965_queue_space(q) < q->high_mark)
b481de9c
ZY		 3109 && priv->mac80211_registered) {
3110 if (wait_write_ptr) {
3111 spin_lock_irqsave(&priv->lock, flags);
3112 txq->need_update = 1;
bb8c093b 3113 iwl4965_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 3114 spin_unlock_irqrestore(&priv->lock, flags);
3115 }
3116
3117 ieee80211_stop_queue(priv->hw, ctl->queue);
3118 }
3119
3120 return 0;
3121
3122drop_unlock:
3123 spin_unlock_irqrestore(&priv->lock, flags);
3124drop:
3125 return -1;
3126}
3127
bb8c093b 3128static void iwl4965_set_rate(struct iwl4965_priv *priv)
b481de9c
ZY		 3129{
3130 const struct ieee80211_hw_mode *hw = NULL;
3131 struct ieee80211_rate *rate;
3132 int i;
3133
bb8c093b 3134 hw = iwl4965_get_hw_mode(priv, priv->phymode);
c4ba9621
SA		 3135 if (!hw) {
3136 IWL_ERROR("Failed to set rate: unable to get hw mode\n");
3137 return;
3138 }
b481de9c
ZY		 3139
3140 priv->active_rate = 0;
3141 priv->active_rate_basic = 0;
3142
3143 IWL_DEBUG_RATE("Setting rates for 802.11%c\n",
3144 hw->mode == MODE_IEEE80211A ?
3145 'a' : ((hw->mode == MODE_IEEE80211B) ? 'b' : 'g'));
3146
3147 for (i = 0; i < hw->num_rates; i++) {
3148 rate = &(hw->rates[i]);
3149 if ((rate->val < IWL_RATE_COUNT) &&
3150 (rate->flags & IEEE80211_RATE_SUPPORTED)) {
3151 IWL_DEBUG_RATE("Adding rate index %d (plcp %d)%s\n",
bb8c093b 3152 rate->val, iwl4965_rates[rate->val].plcp,
b481de9c
ZY		 3153 (rate->flags & IEEE80211_RATE_BASIC) ?
3154 "*" : "");
3155 priv->active_rate |= (1 << rate->val);
3156 if (rate->flags & IEEE80211_RATE_BASIC)
3157 priv->active_rate_basic |= (1 << rate->val);
3158 } else
3159 IWL_DEBUG_RATE("Not adding rate %d (plcp %d)\n",
bb8c093b 3160 rate->val, iwl4965_rates[rate->val].plcp);
b481de9c
ZY		 3161 }
3162
3163 IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
3164 priv->active_rate, priv->active_rate_basic);
3165
3166 /*
3167 * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
3168 * otherwise set it to the default of all CCK rates and 6, 12, 24 for
3169 * OFDM
3170 */
3171 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
3172 priv->staging_rxon.cck_basic_rates =
3173 ((priv->active_rate_basic &
3174 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
3175 else
3176 priv->staging_rxon.cck_basic_rates =
3177 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
3178
3179 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
3180 priv->staging_rxon.ofdm_basic_rates =
3181 ((priv->active_rate_basic &
3182 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
3183 IWL_FIRST_OFDM_RATE) & 0xFF;
3184 else
3185 priv->staging_rxon.ofdm_basic_rates =
3186 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
3187}
3188
bb8c093b 3189static void iwl4965_radio_kill_sw(struct iwl4965_priv *priv, int disable_radio)
b481de9c
ZY		 3190{
3191 unsigned long flags;
3192
3193 if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
3194 return;
3195
3196 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
3197 disable_radio ? "OFF" : "ON");
3198
3199 if (disable_radio) {
bb8c093b 3200 iwl4965_scan_cancel(priv);
b481de9c
ZY		 3201 /* FIXME: This is a workaround for AP */
3202 if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
3203 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 3204 iwl4965_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 3205 CSR_UCODE_SW_BIT_RFKILL);
3206 spin_unlock_irqrestore(&priv->lock, flags);
bb8c093b 3207 iwl4965_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
b481de9c
ZY		 3208 set_bit(STATUS_RF_KILL_SW, &priv->status);
3209 }
3210 return;
3211 }
3212
3213 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 3214 iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 3215
3216 clear_bit(STATUS_RF_KILL_SW, &priv->status);
3217 spin_unlock_irqrestore(&priv->lock, flags);
3218
3219 /* wake up ucode */
3220 msleep(10);
3221
3222 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH		 3223 iwl4965_read32(priv, CSR_UCODE_DRV_GP1);
3224 if (!iwl4965_grab_nic_access(priv))
3225 iwl4965_release_nic_access(priv);
b481de9c
ZY		 3226 spin_unlock_irqrestore(&priv->lock, flags);
3227
3228 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
3229 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
3230 "disabled by HW switch\n");
3231 return;
3232 }
3233
3234 queue_work(priv->workqueue, &priv->restart);
3235 return;
3236}
3237
bb8c093b 3238void iwl4965_set_decrypted_flag(struct iwl4965_priv *priv, struct sk_buff *skb,
b481de9c
ZY		 3239 u32 decrypt_res, struct ieee80211_rx_status *stats)
3240{
3241 u16 fc =
3242 le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
3243
3244 if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
3245 return;
3246
3247 if (!(fc & IEEE80211_FCTL_PROTECTED))
3248 return;
3249
3250 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
3251 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
3252 case RX_RES_STATUS_SEC_TYPE_TKIP:
3253 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
3254 RX_RES_STATUS_BAD_ICV_MIC)
3255 stats->flag |= RX_FLAG_MMIC_ERROR;
3256 case RX_RES_STATUS_SEC_TYPE_WEP:
3257 case RX_RES_STATUS_SEC_TYPE_CCMP:
3258 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
3259 RX_RES_STATUS_DECRYPT_OK) {
3260 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
3261 stats->flag |= RX_FLAG_DECRYPTED;
3262 }
3263 break;
3264
3265 default:
3266 break;
3267 }
3268}
3269
b481de9c
ZY		 3270
3271#define IWL_PACKET_RETRY_TIME HZ
3272
bb8c093b 3273int iwl4965_is_duplicate_packet(struct iwl4965_priv *priv, struct ieee80211_hdr *header)
b481de9c
ZY		 3274{
3275 u16 sc = le16_to_cpu(header->seq_ctrl);
3276 u16 seq = (sc & IEEE80211_SCTL_SEQ) >> 4;
3277 u16 frag = sc & IEEE80211_SCTL_FRAG;
3278 u16 *last_seq, *last_frag;
3279 unsigned long *last_time;
3280
3281 switch (priv->iw_mode) {
3282 case IEEE80211_IF_TYPE_IBSS:{
3283 struct list_head *p;
bb8c093b 3284 struct iwl4965_ibss_seq *entry = NULL;
b481de9c
ZY		 3285 u8 *mac = header->addr2;
3286 int index = mac[5] & (IWL_IBSS_MAC_HASH_SIZE - 1);
3287
3288 __list_for_each(p, &priv->ibss_mac_hash[index]) {
bb8c093b 3289 entry = list_entry(p, struct iwl4965_ibss_seq, list);
b481de9c
ZY		 3290 if (!compare_ether_addr(entry->mac, mac))
3291 break;
3292 }
3293 if (p == &priv->ibss_mac_hash[index]) {
3294 entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
3295 if (!entry) {
bc434dd2 3296 IWL_ERROR("Cannot malloc new mac entry\n");
b481de9c
ZY		 3297 return 0;
3298 }
3299 memcpy(entry->mac, mac, ETH_ALEN);
3300 entry->seq_num = seq;
3301 entry->frag_num = frag;
3302 entry->packet_time = jiffies;
bc434dd2 3303 list_add(&entry->list, &priv->ibss_mac_hash[index]);
b481de9c
ZY		 3304 return 0;
3305 }
3306 last_seq = &entry->seq_num;
3307 last_frag = &entry->frag_num;
3308 last_time = &entry->packet_time;
3309 break;
3310 }
3311 case IEEE80211_IF_TYPE_STA:
3312 last_seq = &priv->last_seq_num;
3313 last_frag = &priv->last_frag_num;
3314 last_time = &priv->last_packet_time;
3315 break;
3316 default:
3317 return 0;
3318 }
3319 if ((*last_seq == seq) &&
3320 time_after(*last_time + IWL_PACKET_RETRY_TIME, jiffies)) {
3321 if (*last_frag == frag)
3322 goto drop;
3323 if (*last_frag + 1 != frag)
3324 /* out-of-order fragment */
3325 goto drop;
3326 } else
3327 *last_seq = seq;
3328
3329 *last_frag = frag;
3330 *last_time = jiffies;
3331 return 0;
3332
3333 drop:
3334 return 1;
3335}
3336
c8b0e6e1 3337#ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT
b481de9c
ZY		 3338
3339#include "iwl-spectrum.h"
3340
3341#define BEACON_TIME_MASK_LOW 0x00FFFFFF
3342#define BEACON_TIME_MASK_HIGH 0xFF000000
3343#define TIME_UNIT 1024
3344
3345/*
3346 * extended beacon time format
3347 * time in usec will be changed into a 32-bit value in 8:24 format
3348 * the high 1 byte is the beacon counts
3349 * the lower 3 bytes is the time in usec within one beacon interval
3350 */
3351
bb8c093b 3352static u32 iwl4965_usecs_to_beacons(u32 usec, u32 beacon_interval)
b481de9c
ZY		 3353{
3354 u32 quot;
3355 u32 rem;
3356 u32 interval = beacon_interval * 1024;
3357
3358 if (!interval || !usec)
3359 return 0;
3360
3361 quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
3362 rem = (usec % interval) & BEACON_TIME_MASK_LOW;
3363
3364 return (quot << 24) + rem;
3365}
3366
3367/* base is usually what we get from ucode with each received frame,
3368 * the same as HW timer counter counting down
3369 */
3370
bb8c093b 3371static __le32 iwl4965_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
b481de9c
ZY		 3372{
3373 u32 base_low = base & BEACON_TIME_MASK_LOW;
3374 u32 addon_low = addon & BEACON_TIME_MASK_LOW;
3375 u32 interval = beacon_interval * TIME_UNIT;
3376 u32 res = (base & BEACON_TIME_MASK_HIGH) +
3377 (addon & BEACON_TIME_MASK_HIGH);
3378
3379 if (base_low > addon_low)
3380 res += base_low - addon_low;
3381 else if (base_low < addon_low) {
3382 res += interval + base_low - addon_low;
3383 res += (1 << 24);
3384 } else
3385 res += (1 << 24);
3386
3387 return cpu_to_le32(res);
3388}
3389
bb8c093b 3390static int iwl4965_get_measurement(struct iwl4965_priv *priv,
b481de9c
ZY		 3391 struct ieee80211_measurement_params *params,
3392 u8 type)
3393{
bb8c093b
CH		 3394 struct iwl4965_spectrum_cmd spectrum;
3395 struct iwl4965_rx_packet *res;
3396 struct iwl4965_host_cmd cmd = {
b481de9c
ZY		 3397 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
3398 .data = (void *)&spectrum,
3399 .meta.flags = CMD_WANT_SKB,
3400 };
3401 u32 add_time = le64_to_cpu(params->start_time);
3402 int rc;
3403 int spectrum_resp_status;
3404 int duration = le16_to_cpu(params->duration);
3405
bb8c093b 3406 if (iwl4965_is_associated(priv))
b481de9c 3407 add_time =
bb8c093b 3408 iwl4965_usecs_to_beacons(
b481de9c
ZY		 3409 le64_to_cpu(params->start_time) - priv->last_tsf,
3410 le16_to_cpu(priv->rxon_timing.beacon_interval));
3411
3412 memset(&spectrum, 0, sizeof(spectrum));
3413
3414 spectrum.channel_count = cpu_to_le16(1);
3415 spectrum.flags =
3416 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
3417 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
3418 cmd.len = sizeof(spectrum);
3419 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
3420
bb8c093b 3421 if (iwl4965_is_associated(priv))
b481de9c 3422 spectrum.start_time =
bb8c093b 3423 iwl4965_add_beacon_time(priv->last_beacon_time,
b481de9c
ZY		 3424 add_time,
3425 le16_to_cpu(priv->rxon_timing.beacon_interval));
3426 else
3427 spectrum.start_time = 0;
3428
3429 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
3430 spectrum.channels[0].channel = params->channel;
3431 spectrum.channels[0].type = type;
3432 if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
3433 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
3434 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
3435
bb8c093b 3436 rc = iwl4965_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 3437 if (rc)
3438 return rc;
3439
bb8c093b 3440 res = (struct iwl4965_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 3441 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
3442 IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
3443 rc = -EIO;
3444 }
3445
3446 spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
3447 switch (spectrum_resp_status) {
3448 case 0: /* Command will be handled */
3449 if (res->u.spectrum.id != 0xff) {
3450 IWL_DEBUG_INFO
3451 ("Replaced existing measurement: %d\n",
3452 res->u.spectrum.id);
3453 priv->measurement_status &= ~MEASUREMENT_READY;
3454 }
3455 priv->measurement_status |= MEASUREMENT_ACTIVE;
3456 rc = 0;
3457 break;
3458
3459 case 1: /* Command will not be handled */
3460 rc = -EAGAIN;
3461 break;
3462 }
3463
3464 dev_kfree_skb_any(cmd.meta.u.skb);
3465
3466 return rc;
3467}
3468#endif
3469
bb8c093b
CH		 3470static void iwl4965_txstatus_to_ieee(struct iwl4965_priv *priv,
3471 struct iwl4965_tx_info *tx_sta)
b481de9c
ZY		 3472{
3473
3474 tx_sta->status.ack_signal = 0;
3475 tx_sta->status.excessive_retries = 0;
3476 tx_sta->status.queue_length = 0;
3477 tx_sta->status.queue_number = 0;
3478
3479 if (in_interrupt())
3480 ieee80211_tx_status_irqsafe(priv->hw,
3481 tx_sta->skb[0], &(tx_sta->status));
3482 else
3483 ieee80211_tx_status(priv->hw,
3484 tx_sta->skb[0], &(tx_sta->status));
3485
3486 tx_sta->skb[0] = NULL;
3487}
3488
3489/**
6440adb5 3490 * iwl4965_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
b481de9c 3491 *
6440adb5
CB		 3492 * When FW advances 'R' index, all entries between old and new 'R' index
3493 * need to be reclaimed. As result, some free space forms. If there is
3494 * enough free space (> low mark), wake the stack that feeds us.
b481de9c 3495 */
bb8c093b 3496int iwl4965_tx_queue_reclaim(struct iwl4965_priv *priv, int txq_id, int index)
b481de9c 3497{
bb8c093b
CH		 3498 struct iwl4965_tx_queue *txq = &priv->txq[txq_id];
3499 struct iwl4965_queue *q = &txq->q;
b481de9c
ZY		 3500 int nfreed = 0;
3501
3502 if ((index >= q->n_bd) || (x2_queue_used(q, index) == 0)) {
3503 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
3504 "is out of range [0-%d] %d %d.\n", txq_id,
fc4b6853 3505 index, q->n_bd, q->write_ptr, q->read_ptr);
b481de9c
ZY		 3506 return 0;
3507 }
3508
bb8c093b 3509 for (index = iwl4965_queue_inc_wrap(index, q->n_bd);
fc4b6853 3510 q->read_ptr != index;
bb8c093b 3511 q->read_ptr = iwl4965_queue_inc_wrap(q->read_ptr, q->n_bd)) {
b481de9c 3512 if (txq_id != IWL_CMD_QUEUE_NUM) {
bb8c093b 3513 iwl4965_txstatus_to_ieee(priv,
fc4b6853 3514 &(txq->txb[txq->q.read_ptr]));
bb8c093b 3515 iwl4965_hw_txq_free_tfd(priv, txq);
b481de9c
ZY		 3516 } else if (nfreed > 1) {
3517 IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
fc4b6853 3518 q->write_ptr, q->read_ptr);
b481de9c
ZY		 3519 queue_work(priv->workqueue, &priv->restart);
3520 }
3521 nfreed++;
3522 }
3523
bb8c093b 3524 if (iwl4965_queue_space(q) > q->low_mark && (txq_id >= 0) &&
b481de9c
ZY		 3525 (txq_id != IWL_CMD_QUEUE_NUM) &&
3526 priv->mac80211_registered)
3527 ieee80211_wake_queue(priv->hw, txq_id);
3528
3529
3530 return nfreed;
3531}
3532
bb8c093b 3533static int iwl4965_is_tx_success(u32 status)
b481de9c
ZY		 3534{
3535 status &= TX_STATUS_MSK;
3536 return (status == TX_STATUS_SUCCESS)
3537 || (status == TX_STATUS_DIRECT_DONE);
3538}
3539
3540/******************************************************************************
3541 *
3542 * Generic RX handler implementations
3543 *
3544 ******************************************************************************/
c8b0e6e1
CH		 3545#ifdef CONFIG_IWL4965_HT
3546#ifdef CONFIG_IWL4965_HT_AGG
b481de9c 3547
bb8c093b 3548static inline int iwl4965_get_ra_sta_id(struct iwl4965_priv *priv,
b481de9c
ZY		 3549 struct ieee80211_hdr *hdr)
3550{
3551 if (priv->iw_mode == IEEE80211_IF_TYPE_STA)
3552 return IWL_AP_ID;
3553 else {
3554 u8 *da = ieee80211_get_DA(hdr);
bb8c093b 3555 return iwl4965_hw_find_station(priv, da);
b481de9c
ZY		 3556 }
3557}
3558
bb8c093b
CH		 3559static struct ieee80211_hdr *iwl4965_tx_queue_get_hdr(
3560 struct iwl4965_priv *priv, int txq_id, int idx)
b481de9c
ZY		 3561{
3562 if (priv->txq[txq_id].txb[idx].skb[0])
3563 return (struct ieee80211_hdr *)priv->txq[txq_id].
3564 txb[idx].skb[0]->data;
3565 return NULL;
3566}
3567
bb8c093b 3568static inline u32 iwl4965_get_scd_ssn(struct iwl4965_tx_resp *tx_resp)
b481de9c
ZY		 3569{
3570 __le32 *scd_ssn = (__le32 *)((u32 *)&tx_resp->status +
3571 tx_resp->frame_count);
3572 return le32_to_cpu(*scd_ssn) & MAX_SN;
3573
3574}
6440adb5
CB		 3575
3576/**
3577 * iwl4965_tx_status_reply_tx - Handle Tx rspnse for frames in aggregation queue
3578 */
bb8c093b
CH		 3579static int iwl4965_tx_status_reply_tx(struct iwl4965_priv *priv,
3580 struct iwl4965_ht_agg *agg,
3581 struct iwl4965_tx_resp *tx_resp,
b481de9c
ZY		 3582 u16 start_idx)
3583{
3584 u32 status;
3585 __le32 *frame_status = &tx_resp->status;
3586 struct ieee80211_tx_status *tx_status = NULL;
3587 struct ieee80211_hdr *hdr = NULL;
3588 int i, sh;
3589 int txq_id, idx;
3590 u16 seq;
3591
3592 if (agg->wait_for_ba)
6440adb5 3593 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
b481de9c
ZY		 3594
3595 agg->frame_count = tx_resp->frame_count;
3596 agg->start_idx = start_idx;
3597 agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
3598 agg->bitmap0 = agg->bitmap1 = 0;
3599
6440adb5 3600 /* # frames attempted by Tx command */
b481de9c 3601 if (agg->frame_count == 1) {
6440adb5 3602 /* Only one frame was attempted; no block-ack will arrive */
bb8c093b 3603 struct iwl4965_tx_queue *txq ;
b481de9c
ZY		 3604 status = le32_to_cpu(frame_status[0]);
3605
3606 txq_id = agg->txq_id;
3607 txq = &priv->txq[txq_id];
3608 /* FIXME: code repetition */
3609 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d \n",
3610 agg->frame_count, agg->start_idx);
3611
fc4b6853 3612 tx_status = &(priv->txq[txq_id].txb[txq->q.read_ptr].status);
b481de9c
ZY		 3613 tx_status->retry_count = tx_resp->failure_frame;
3614 tx_status->queue_number = status & 0xff;
3615 tx_status->queue_length = tx_resp->bt_kill_count;
3616 tx_status->queue_length |= tx_resp->failure_rts;
3617
bb8c093b 3618 tx_status->flags = iwl4965_is_tx_success(status)?
b481de9c
ZY		 3619 IEEE80211_TX_STATUS_ACK : 0;
3620 tx_status->control.tx_rate =
bb8c093b 3621 iwl4965_hw_get_rate_n_flags(tx_resp->rate_n_flags);
b481de9c
ZY		 3622 /* FIXME: code repetition end */
3623
3624 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
3625 status & 0xff, tx_resp->failure_frame);
3626 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n",
bb8c093b 3627 iwl4965_hw_get_rate_n_flags(tx_resp->rate_n_flags));
b481de9c
ZY		 3628
3629 agg->wait_for_ba = 0;
3630 } else {
6440adb5 3631 /* Two or more frames were attempted; expect block-ack */
b481de9c
ZY		 3632 u64 bitmap = 0;
3633 int start = agg->start_idx;
3634
6440adb5 3635 /* Construct bit-map of pending frames within Tx window */
b481de9c
ZY		 3636 for (i = 0; i < agg->frame_count; i++) {
3637 u16 sc;
3638 status = le32_to_cpu(frame_status[i]);
3639 seq = status >> 16;
3640 idx = SEQ_TO_INDEX(seq);
3641 txq_id = SEQ_TO_QUEUE(seq);
3642
3643 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
3644 AGG_TX_STATE_ABORT_MSK))
3645 continue;
3646
3647 IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
3648 agg->frame_count, txq_id, idx);
3649
bb8c093b 3650 hdr = iwl4965_tx_queue_get_hdr(priv, txq_id, idx);
b481de9c
ZY		 3651
3652 sc = le16_to_cpu(hdr->seq_ctrl);
3653 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
3654 IWL_ERROR("BUG_ON idx doesn't match seq control"
3655 " idx=%d, seq_idx=%d, seq=%d\n",
3656 idx, SEQ_TO_SN(sc),
3657 hdr->seq_ctrl);
3658 return -1;
3659 }
3660
3661 IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
3662 i, idx, SEQ_TO_SN(sc));
3663
3664 sh = idx - start;
3665 if (sh > 64) {
3666 sh = (start - idx) + 0xff;
3667 bitmap = bitmap << sh;
3668 sh = 0;
3669 start = idx;
3670 } else if (sh < -64)
3671 sh = 0xff - (start - idx);
3672 else if (sh < 0) {
3673 sh = start - idx;
3674 start = idx;
3675 bitmap = bitmap << sh;
3676 sh = 0;
3677 }
3678 bitmap |= (1 << sh);
3679 IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%x\n",
3680 start, (u32)(bitmap & 0xFFFFFFFF));
3681 }
3682
3683 agg->bitmap0 = bitmap & 0xFFFFFFFF;
3684 agg->bitmap1 = bitmap >> 32;
3685 agg->start_idx = start;
3686 agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
3687 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%x\n",
3688 agg->frame_count, agg->start_idx,
3689 agg->bitmap0);
3690
3691 if (bitmap)
3692 agg->wait_for_ba = 1;
3693 }
3694 return 0;
3695}
3696#endif
3697#endif
3698
6440adb5
CB		 3699/**
3700 * iwl4965_rx_reply_tx - Handle standard (non-aggregation) Tx response
3701 */
bb8c093b
CH		 3702static void iwl4965_rx_reply_tx(struct iwl4965_priv *priv,
3703 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3704{
bb8c093b 3705 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3706 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3707 int txq_id = SEQ_TO_QUEUE(sequence);
3708 int index = SEQ_TO_INDEX(sequence);
bb8c093b 3709 struct iwl4965_tx_queue *txq = &priv->txq[txq_id];
b481de9c 3710 struct ieee80211_tx_status *tx_status;
bb8c093b 3711 struct iwl4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
b481de9c 3712 u32 status = le32_to_cpu(tx_resp->status);
c8b0e6e1
CH		 3713#ifdef CONFIG_IWL4965_HT
3714#ifdef CONFIG_IWL4965_HT_AGG
b481de9c
ZY		 3715 int tid, sta_id;
3716#endif
3717#endif
3718
3719 if ((index >= txq->q.n_bd) || (x2_queue_used(&txq->q, index) == 0)) {
3720 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
3721 "is out of range [0-%d] %d %d\n", txq_id,
fc4b6853
TW		 3722 index, txq->q.n_bd, txq->q.write_ptr,
3723 txq->q.read_ptr);
b481de9c
ZY		 3724 return;
3725 }
3726
c8b0e6e1
CH		 3727#ifdef CONFIG_IWL4965_HT
3728#ifdef CONFIG_IWL4965_HT_AGG
b481de9c 3729 if (txq->sched_retry) {
bb8c093b 3730 const u32 scd_ssn = iwl4965_get_scd_ssn(tx_resp);
b481de9c 3731 struct ieee80211_hdr *hdr =
bb8c093b
CH		 3732 iwl4965_tx_queue_get_hdr(priv, txq_id, index);
3733 struct iwl4965_ht_agg *agg = NULL;
b481de9c
ZY		 3734 __le16 *qc = ieee80211_get_qos_ctrl(hdr);
3735
3736 if (qc == NULL) {
3737 IWL_ERROR("BUG_ON qc is null!!!!\n");
3738 return;
3739 }
3740
3741 tid = le16_to_cpu(*qc) & 0xf;
3742
bb8c093b 3743 sta_id = iwl4965_get_ra_sta_id(priv, hdr);
b481de9c
ZY		 3744 if (unlikely(sta_id == IWL_INVALID_STATION)) {
3745 IWL_ERROR("Station not known for\n");
3746 return;
3747 }
3748
3749 agg = &priv->stations[sta_id].tid[tid].agg;
3750
3751 iwl4965_tx_status_reply_tx(priv, agg, tx_resp, index);
3752
3753 if ((tx_resp->frame_count == 1) &&
bb8c093b 3754 !iwl4965_is_tx_success(status)) {
b481de9c
ZY		 3755 /* TODO: send BAR */
3756 }
3757
fc4b6853 3758 if ((txq->q.read_ptr != (scd_ssn & 0xff))) {
bb8c093b 3759 index = iwl4965_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
b481de9c
ZY		 3760 IWL_DEBUG_TX_REPLY("Retry scheduler reclaim scd_ssn "
3761 "%d index %d\n", scd_ssn , index);
bb8c093b 3762 iwl4965_tx_queue_reclaim(priv, txq_id, index);
b481de9c
ZY		 3763 }
3764 } else {
c8b0e6e1
CH		 3765#endif /* CONFIG_IWL4965_HT_AGG */
3766#endif /* CONFIG_IWL4965_HT */
fc4b6853 3767 tx_status = &(txq->txb[txq->q.read_ptr].status);
b481de9c
ZY		 3768
3769 tx_status->retry_count = tx_resp->failure_frame;
3770 tx_status->queue_number = status;
3771 tx_status->queue_length = tx_resp->bt_kill_count;
3772 tx_status->queue_length |= tx_resp->failure_rts;
3773
3774 tx_status->flags =
bb8c093b 3775 iwl4965_is_tx_success(status) ? IEEE80211_TX_STATUS_ACK : 0;
b481de9c
ZY		 3776
3777 tx_status->control.tx_rate =
bb8c093b 3778 iwl4965_hw_get_rate_n_flags(tx_resp->rate_n_flags);
b481de9c
ZY		 3779
3780 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) rate_n_flags 0x%x "
bb8c093b 3781 "retries %d\n", txq_id, iwl4965_get_tx_fail_reason(status),
b481de9c
ZY		 3782 status, le32_to_cpu(tx_resp->rate_n_flags),
3783 tx_resp->failure_frame);
3784
3785 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
3786 if (index != -1)
bb8c093b 3787 iwl4965_tx_queue_reclaim(priv, txq_id, index);
c8b0e6e1
CH		 3788#ifdef CONFIG_IWL4965_HT
3789#ifdef CONFIG_IWL4965_HT_AGG
b481de9c 3790 }
c8b0e6e1
CH		 3791#endif /* CONFIG_IWL4965_HT_AGG */
3792#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY		 3793
3794 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
3795 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
3796}
3797
3798
bb8c093b
CH		 3799static void iwl4965_rx_reply_alive(struct iwl4965_priv *priv,
3800 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3801{
bb8c093b
CH		 3802 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3803 struct iwl4965_alive_resp *palive;
b481de9c
ZY		 3804 struct delayed_work *pwork;
3805
3806 palive = &pkt->u.alive_frame;
3807
3808 IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
3809 "0x%01X 0x%01X\n",
3810 palive->is_valid, palive->ver_type,
3811 palive->ver_subtype);
3812
3813 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
3814 IWL_DEBUG_INFO("Initialization Alive received.\n");
3815 memcpy(&priv->card_alive_init,
3816 &pkt->u.alive_frame,
bb8c093b 3817 sizeof(struct iwl4965_init_alive_resp));
b481de9c
ZY		 3818 pwork = &priv->init_alive_start;
3819 } else {
3820 IWL_DEBUG_INFO("Runtime Alive received.\n");
3821 memcpy(&priv->card_alive, &pkt->u.alive_frame,
bb8c093b 3822 sizeof(struct iwl4965_alive_resp));
b481de9c
ZY		 3823 pwork = &priv->alive_start;
3824 }
3825
3826 /* We delay the ALIVE response by 5ms to
3827 * give the HW RF Kill time to activate... */
3828 if (palive->is_valid == UCODE_VALID_OK)
3829 queue_delayed_work(priv->workqueue, pwork,
3830 msecs_to_jiffies(5));
3831 else
3832 IWL_WARNING("uCode did not respond OK.\n");
3833}
3834
bb8c093b
CH		 3835static void iwl4965_rx_reply_add_sta(struct iwl4965_priv *priv,
3836 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3837{
bb8c093b 3838 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3839
3840 IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
3841 return;
3842}
3843
bb8c093b
CH		 3844static void iwl4965_rx_reply_error(struct iwl4965_priv *priv,
3845 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3846{
bb8c093b 3847 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3848
3849 IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
3850 "seq 0x%04X ser 0x%08X\n",
3851 le32_to_cpu(pkt->u.err_resp.error_type),
3852 get_cmd_string(pkt->u.err_resp.cmd_id),
3853 pkt->u.err_resp.cmd_id,
3854 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
3855 le32_to_cpu(pkt->u.err_resp.error_info));
3856}
3857
3858#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
3859
bb8c093b 3860static void iwl4965_rx_csa(struct iwl4965_priv *priv, struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3861{
bb8c093b
CH		 3862 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3863 struct iwl4965_rxon_cmd *rxon = (void *)&priv->active_rxon;
3864 struct iwl4965_csa_notification *csa = &(pkt->u.csa_notif);
b481de9c
ZY		 3865 IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
3866 le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
3867 rxon->channel = csa->channel;
3868 priv->staging_rxon.channel = csa->channel;
3869}
3870
bb8c093b
CH		 3871static void iwl4965_rx_spectrum_measure_notif(struct iwl4965_priv *priv,
3872 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3873{
c8b0e6e1 3874#ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT
bb8c093b
CH		 3875 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3876 struct iwl4965_spectrum_notification *report = &(pkt->u.spectrum_notif);
b481de9c
ZY		 3877
3878 if (!report->state) {
3879 IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
3880 "Spectrum Measure Notification: Start\n");
3881 return;
3882 }
3883
3884 memcpy(&priv->measure_report, report, sizeof(*report));
3885 priv->measurement_status |= MEASUREMENT_READY;
3886#endif
3887}
3888
bb8c093b
CH		 3889static void iwl4965_rx_pm_sleep_notif(struct iwl4965_priv *priv,
3890 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3891{
c8b0e6e1 3892#ifdef CONFIG_IWL4965_DEBUG
bb8c093b
CH		 3893 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3894 struct iwl4965_sleep_notification *sleep = &(pkt->u.sleep_notif);
b481de9c
ZY		 3895 IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
3896 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
3897#endif
3898}
3899
bb8c093b
CH		 3900static void iwl4965_rx_pm_debug_statistics_notif(struct iwl4965_priv *priv,
3901 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3902{
bb8c093b 3903 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3904 IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
3905 "notification for %s:\n",
3906 le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
bb8c093b 3907 iwl4965_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
b481de9c
ZY		 3908}
3909
bb8c093b 3910static void iwl4965_bg_beacon_update(struct work_struct *work)
b481de9c 3911{
bb8c093b
CH		 3912 struct iwl4965_priv *priv =
3913 container_of(work, struct iwl4965_priv, beacon_update);
b481de9c
ZY		 3914 struct sk_buff *beacon;
3915
3916 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
32bfd35d 3917 beacon = ieee80211_beacon_get(priv->hw, priv->vif, NULL);
b481de9c
ZY		 3918
3919 if (!beacon) {
3920 IWL_ERROR("update beacon failed\n");
3921 return;
3922 }
3923
3924 mutex_lock(&priv->mutex);
3925 /* new beacon skb is allocated every time; dispose previous.*/
3926 if (priv->ibss_beacon)
3927 dev_kfree_skb(priv->ibss_beacon);
3928
3929 priv->ibss_beacon = beacon;
3930 mutex_unlock(&priv->mutex);
3931
bb8c093b 3932 iwl4965_send_beacon_cmd(priv);
b481de9c
ZY		 3933}
3934
bb8c093b
CH		 3935static void iwl4965_rx_beacon_notif(struct iwl4965_priv *priv,
3936 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3937{
c8b0e6e1 3938#ifdef CONFIG_IWL4965_DEBUG
bb8c093b
CH		 3939 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3940 struct iwl4965_beacon_notif *beacon = &(pkt->u.beacon_status);
3941 u8 rate = iwl4965_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
b481de9c
ZY		 3942
3943 IWL_DEBUG_RX("beacon status %x retries %d iss %d "
3944 "tsf %d %d rate %d\n",
3945 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
3946 beacon->beacon_notify_hdr.failure_frame,
3947 le32_to_cpu(beacon->ibss_mgr_status),
3948 le32_to_cpu(beacon->high_tsf),
3949 le32_to_cpu(beacon->low_tsf), rate);
3950#endif
3951
3952 if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
3953 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
3954 queue_work(priv->workqueue, &priv->beacon_update);
3955}
3956
3957/* Service response to REPLY_SCAN_CMD (0x80) */
bb8c093b
CH		 3958static void iwl4965_rx_reply_scan(struct iwl4965_priv *priv,
3959 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3960{
c8b0e6e1 3961#ifdef CONFIG_IWL4965_DEBUG
bb8c093b
CH		 3962 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3963 struct iwl4965_scanreq_notification *notif =
3964 (struct iwl4965_scanreq_notification *)pkt->u.raw;
b481de9c
ZY		 3965
3966 IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
3967#endif
3968}
3969
3970/* Service SCAN_START_NOTIFICATION (0x82) */
bb8c093b
CH		 3971static void iwl4965_rx_scan_start_notif(struct iwl4965_priv *priv,
3972 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3973{
bb8c093b
CH		 3974 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3975 struct iwl4965_scanstart_notification *notif =
3976 (struct iwl4965_scanstart_notification *)pkt->u.raw;
b481de9c
ZY		 3977 priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
3978 IWL_DEBUG_SCAN("Scan start: "
3979 "%d [802.11%s] "
3980 "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
3981 notif->channel,
3982 notif->band ? "bg" : "a",
3983 notif->tsf_high,
3984 notif->tsf_low, notif->status, notif->beacon_timer);
3985}
3986
3987/* Service SCAN_RESULTS_NOTIFICATION (0x83) */
bb8c093b
CH		 3988static void iwl4965_rx_scan_results_notif(struct iwl4965_priv *priv,
3989 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3990{
bb8c093b
CH		 3991 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3992 struct iwl4965_scanresults_notification *notif =
3993 (struct iwl4965_scanresults_notification *)pkt->u.raw;
b481de9c
ZY		 3994
3995 IWL_DEBUG_SCAN("Scan ch.res: "
3996 "%d [802.11%s] "
3997 "(TSF: 0x%08X:%08X) - %d "
3998 "elapsed=%lu usec (%dms since last)\n",
3999 notif->channel,
4000 notif->band ? "bg" : "a",
4001 le32_to_cpu(notif->tsf_high),
4002 le32_to_cpu(notif->tsf_low),
4003 le32_to_cpu(notif->statistics[0]),
4004 le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
4005 jiffies_to_msecs(elapsed_jiffies
4006 (priv->last_scan_jiffies, jiffies)));
4007
4008 priv->last_scan_jiffies = jiffies;
7878a5a4 4009 priv->next_scan_jiffies = 0;
b481de9c
ZY		 4010}
4011
4012/* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
bb8c093b
CH		 4013static void iwl4965_rx_scan_complete_notif(struct iwl4965_priv *priv,
4014 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 4015{
bb8c093b
CH		 4016 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
4017 struct iwl4965_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
b481de9c
ZY		 4018
4019 IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
4020 scan_notif->scanned_channels,
4021 scan_notif->tsf_low,
4022 scan_notif->tsf_high, scan_notif->status);
4023
4024 /* The HW is no longer scanning */
4025 clear_bit(STATUS_SCAN_HW, &priv->status);
4026
4027 /* The scan completion notification came in, so kill that timer... */
4028 cancel_delayed_work(&priv->scan_check);
4029
4030 IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
4031 (priv->scan_bands == 2) ? "2.4" : "5.2",
4032 jiffies_to_msecs(elapsed_jiffies
4033 (priv->scan_pass_start, jiffies)));
4034
4035 /* Remove this scanned band from the list
4036 * of pending bands to scan */
4037 priv->scan_bands--;
4038
4039 /* If a request to abort was given, or the scan did not succeed
4040 * then we reset the scan state machine and terminate,
4041 * re-queuing another scan if one has been requested */
4042 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
4043 IWL_DEBUG_INFO("Aborted scan completed.\n");
4044 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
4045 } else {
4046 /* If there are more bands on this scan pass reschedule */
4047 if (priv->scan_bands > 0)
4048 goto reschedule;
4049 }
4050
4051 priv->last_scan_jiffies = jiffies;
7878a5a4 4052 priv->next_scan_jiffies = 0;
b481de9c
ZY		 4053 IWL_DEBUG_INFO("Setting scan to off\n");
4054
4055 clear_bit(STATUS_SCANNING, &priv->status);
4056
4057 IWL_DEBUG_INFO("Scan took %dms\n",
4058 jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
4059
4060 queue_work(priv->workqueue, &priv->scan_completed);
4061
4062 return;
4063
4064reschedule:
4065 priv->scan_pass_start = jiffies;
4066 queue_work(priv->workqueue, &priv->request_scan);
4067}
4068
4069/* Handle notification from uCode that card's power state is changing
4070 * due to software, hardware, or critical temperature RFKILL */
bb8c093b
CH		 4071static void iwl4965_rx_card_state_notif(struct iwl4965_priv *priv,
4072 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 4073{
bb8c093b 4074 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 4075 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
4076 unsigned long status = priv->status;
4077
4078 IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
4079 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
4080 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
4081
4082 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
4083 RF_CARD_DISABLED)) {
4084
bb8c093b 4085 iwl4965_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 4086 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
4087
bb8c093b
CH		 4088 if (!iwl4965_grab_nic_access(priv)) {
4089 iwl4965_write_direct32(
b481de9c
ZY		 4090 priv, HBUS_TARG_MBX_C,
4091 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
4092
bb8c093b 4093 iwl4965_release_nic_access(priv);
b481de9c
ZY		 4094 }
4095
4096 if (!(flags & RXON_CARD_DISABLED)) {
bb8c093b 4097 iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c 4098 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
bb8c093b
CH		 4099 if (!iwl4965_grab_nic_access(priv)) {
4100 iwl4965_write_direct32(
b481de9c
ZY		 4101 priv, HBUS_TARG_MBX_C,
4102 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
4103
bb8c093b 4104 iwl4965_release_nic_access(priv);
b481de9c
ZY		 4105 }
4106 }
4107
4108 if (flags & RF_CARD_DISABLED) {
bb8c093b 4109 iwl4965_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c 4110 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
bb8c093b
CH		 4111 iwl4965_read32(priv, CSR_UCODE_DRV_GP1);
4112 if (!iwl4965_grab_nic_access(priv))
4113 iwl4965_release_nic_access(priv);
b481de9c
ZY		 4114 }
4115 }
4116
4117 if (flags & HW_CARD_DISABLED)
4118 set_bit(STATUS_RF_KILL_HW, &priv->status);
4119 else
4120 clear_bit(STATUS_RF_KILL_HW, &priv->status);
4121
4122
4123 if (flags & SW_CARD_DISABLED)
4124 set_bit(STATUS_RF_KILL_SW, &priv->status);
4125 else
4126 clear_bit(STATUS_RF_KILL_SW, &priv->status);
4127
4128 if (!(flags & RXON_CARD_DISABLED))
bb8c093b 4129 iwl4965_scan_cancel(priv);
b481de9c
ZY		 4130
4131 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
4132 test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
4133 (test_bit(STATUS_RF_KILL_SW, &status) !=
4134 test_bit(STATUS_RF_KILL_SW, &priv->status)))
4135 queue_work(priv->workqueue, &priv->rf_kill);
4136 else
4137 wake_up_interruptible(&priv->wait_command_queue);
4138}
4139
4140/**
bb8c093b 4141 * iwl4965_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY		 4142 *
4143 * Setup the RX handlers for each of the reply types sent from the uCode
4144 * to the host.
4145 *
4146 * This function chains into the hardware specific files for them to setup
4147 * any hardware specific handlers as well.
4148 */
bb8c093b 4149static void iwl4965_setup_rx_handlers(struct iwl4965_priv *priv)
b481de9c 4150{
bb8c093b
CH		 4151 priv->rx_handlers[REPLY_ALIVE] = iwl4965_rx_reply_alive;
4152 priv->rx_handlers[REPLY_ADD_STA] = iwl4965_rx_reply_add_sta;
4153 priv->rx_handlers[REPLY_ERROR] = iwl4965_rx_reply_error;
4154 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl4965_rx_csa;
b481de9c 4155 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
bb8c093b
CH		 4156 iwl4965_rx_spectrum_measure_notif;
4157 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl4965_rx_pm_sleep_notif;
b481de9c 4158 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
bb8c093b
CH		 4159 iwl4965_rx_pm_debug_statistics_notif;
4160 priv->rx_handlers[BEACON_NOTIFICATION] = iwl4965_rx_beacon_notif;
b481de9c 4161
9fbab516
BC		 4162 /*
4163 * The same handler is used for both the REPLY to a discrete
4164 * statistics request from the host as well as for the periodic
4165 * statistics notifications (after received beacons) from the uCode.
b481de9c 4166 */
bb8c093b
CH		 4167 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl4965_hw_rx_statistics;
4168 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl4965_hw_rx_statistics;
b481de9c 4169
bb8c093b
CH		 4170 priv->rx_handlers[REPLY_SCAN_CMD] = iwl4965_rx_reply_scan;
4171 priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl4965_rx_scan_start_notif;
b481de9c 4172 priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
bb8c093b 4173 iwl4965_rx_scan_results_notif;
b481de9c 4174 priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
bb8c093b
CH		 4175 iwl4965_rx_scan_complete_notif;
4176 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl4965_rx_card_state_notif;
4177 priv->rx_handlers[REPLY_TX] = iwl4965_rx_reply_tx;
b481de9c 4178
9fbab516 4179 /* Set up hardware specific Rx handlers */
bb8c093b 4180 iwl4965_hw_rx_handler_setup(priv);
b481de9c
ZY		 4181}
4182
4183/**
bb8c093b 4184 * iwl4965_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
b481de9c
ZY		 4185 * @rxb: Rx buffer to reclaim
4186 *
4187 * If an Rx buffer has an async callback associated with it the callback
4188 * will be executed. The attached skb (if present) will only be freed
4189 * if the callback returns 1
4190 */
bb8c093b
CH		 4191static void iwl4965_tx_cmd_complete(struct iwl4965_priv *priv,
4192 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 4193{
bb8c093b 4194 struct iwl4965_rx_packet *pkt = (struct iwl4965_rx_packet *)rxb->skb->data;
b481de9c
ZY		 4195 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
4196 int txq_id = SEQ_TO_QUEUE(sequence);
4197 int index = SEQ_TO_INDEX(sequence);
4198 int huge = sequence & SEQ_HUGE_FRAME;
4199 int cmd_index;
bb8c093b 4200 struct iwl4965_cmd *cmd;
b481de9c
ZY		 4201
4202 /* If a Tx command is being handled and it isn't in the actual
4203 * command queue then there a command routing bug has been introduced
4204 * in the queue management code. */
4205 if (txq_id != IWL_CMD_QUEUE_NUM)
4206 IWL_ERROR("Error wrong command queue %d command id 0x%X\n",
4207 txq_id, pkt->hdr.cmd);
4208 BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
4209
4210 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
4211 cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
4212
4213 /* Input error checking is done when commands are added to queue. */
4214 if (cmd->meta.flags & CMD_WANT_SKB) {
4215 cmd->meta.source->u.skb = rxb->skb;
4216 rxb->skb = NULL;
4217 } else if (cmd->meta.u.callback &&
4218 !cmd->meta.u.callback(priv, cmd, rxb->skb))
4219 rxb->skb = NULL;
4220
bb8c093b 4221 iwl4965_tx_queue_reclaim(priv, txq_id, index);
b481de9c
ZY		 4222
4223 if (!(cmd->meta.flags & CMD_ASYNC)) {
4224 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
4225 wake_up_interruptible(&priv->wait_command_queue);
4226 }
4227}
4228
4229/************************** RX-FUNCTIONS ****************************/
4230/*
4231 * Rx theory of operation
4232 *
9fbab516
BC		 4233 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
4234 * each of which point to Receive Buffers to be filled by 4965. These get
4235 * used not only for Rx frames, but for any command response or notification
4236 * from the 4965. The driver and 4965 manage the Rx buffers by means
4237 * of indexes into the circular buffer.
b481de9c
ZY		 4238 *
4239 * Rx Queue Indexes
4240 * The host/firmware share two index registers for managing the Rx buffers.
4241 *
4242 * The READ index maps to the first position that the firmware may be writing
4243 * to -- the driver can read up to (but not including) this position and get
4244 * good data.
4245 * The READ index is managed by the firmware once the card is enabled.
4246 *
4247 * The WRITE index maps to the last position the driver has read from -- the
4248 * position preceding WRITE is the last slot the firmware can place a packet.
4249 *
4250 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
4251 * WRITE = READ.
4252 *
9fbab516 4253 * During initialization, the host sets up the READ queue position to the first
b481de9c
ZY		 4254 * INDEX position, and WRITE to the last (READ - 1 wrapped)
4255 *
9fbab516 4256 * When the firmware places a packet in a buffer, it will advance the READ index
b481de9c
ZY		 4257 * and fire the RX interrupt. The driver can then query the READ index and
4258 * process as many packets as possible, moving the WRITE index forward as it
4259 * resets the Rx queue buffers with new memory.
4260 *
4261 * The management in the driver is as follows:
4262 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
4263 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
01ebd063 4264 * to replenish the iwl->rxq->rx_free.
bb8c093b 4265 * + In iwl4965_rx_replenish (scheduled) if 'processed' != 'read' then the
b481de9c
ZY		 4266 * iwl->rxq is replenished and the READ INDEX is updated (updating the
4267 * 'processed' and 'read' driver indexes as well)
4268 * + A received packet is processed and handed to the kernel network stack,
4269 * detached from the iwl->rxq. The driver 'processed' index is updated.
4270 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
4271 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
4272 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
4273 * were enough free buffers and RX_STALLED is set it is cleared.
4274 *
4275 *
4276 * Driver sequence:
4277 *
9fbab516
BC		 4278 * iwl4965_rx_queue_alloc() Allocates rx_free
4279 * iwl4965_rx_replenish() Replenishes rx_free list from rx_used, and calls
bb8c093b 4280 * iwl4965_rx_queue_restock
9fbab516 4281 * iwl4965_rx_queue_restock() Moves available buffers from rx_free into Rx
b481de9c
ZY		 4282 * queue, updates firmware pointers, and updates
4283 * the WRITE index. If insufficient rx_free buffers
bb8c093b 4284 * are available, schedules iwl4965_rx_replenish
b481de9c
ZY		 4285 *
4286 * -- enable interrupts --
9fbab516 4287 * ISR - iwl4965_rx() Detach iwl4965_rx_mem_buffers from pool up to the
b481de9c
ZY		 4288 * READ INDEX, detaching the SKB from the pool.
4289 * Moves the packet buffer from queue to rx_used.
bb8c093b 4290 * Calls iwl4965_rx_queue_restock to refill any empty
b481de9c
ZY		 4291 * slots.
4292 * ...
4293 *
4294 */
4295
4296/**
bb8c093b 4297 * iwl4965_rx_queue_space - Return number of free slots available in queue.
b481de9c 4298 */
bb8c093b 4299static int iwl4965_rx_queue_space(const struct iwl4965_rx_queue *q)
b481de9c
ZY		 4300{
4301 int s = q->read - q->write;
4302 if (s <= 0)
4303 s += RX_QUEUE_SIZE;
4304 /* keep some buffer to not confuse full and empty queue */
4305 s -= 2;
4306 if (s < 0)
4307 s = 0;
4308 return s;
4309}
4310
4311/**
bb8c093b 4312 * iwl4965_rx_queue_update_write_ptr - Update the write pointer for the RX queue
b481de9c 4313 */
bb8c093b 4314int iwl4965_rx_queue_update_write_ptr(struct iwl4965_priv *priv, struct iwl4965_rx_queue *q)
b481de9c
ZY		 4315{
4316 u32 reg = 0;
4317 int rc = 0;
4318 unsigned long flags;
4319
4320 spin_lock_irqsave(&q->lock, flags);
4321
4322 if (q->need_update == 0)
4323 goto exit_unlock;
4324
6440adb5 4325 /* If power-saving is in use, make sure device is awake */
b481de9c 4326 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
bb8c093b 4327 reg = iwl4965_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY		 4328
4329 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
bb8c093b 4330 iwl4965_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 4331 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
4332 goto exit_unlock;
4333 }
4334
bb8c093b 4335 rc = iwl4965_grab_nic_access(priv);
b481de9c
ZY		 4336 if (rc)
4337 goto exit_unlock;
4338
6440adb5 4339 /* Device expects a multiple of 8 */
bb8c093b 4340 iwl4965_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
b481de9c 4341 q->write & ~0x7);
bb8c093b 4342 iwl4965_release_nic_access(priv);
6440adb5
CB		 4343
4344 /* Else device is assumed to be awake */
b481de9c 4345 } else
6440adb5 4346 /* Device expects a multiple of 8 */
bb8c093b 4347 iwl4965_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
b481de9c
ZY		 4348
4349
4350 q->need_update = 0;
4351
4352 exit_unlock:
4353 spin_unlock_irqrestore(&q->lock, flags);
4354 return rc;
4355}
4356
4357/**
9fbab516 4358 * iwl4965_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
b481de9c 4359 */
bb8c093b 4360static inline __le32 iwl4965_dma_addr2rbd_ptr(struct iwl4965_priv *priv,
b481de9c
ZY		 4361 dma_addr_t dma_addr)
4362{
4363 return cpu_to_le32((u32)(dma_addr >> 8));
4364}
4365
4366
4367/**
bb8c093b 4368 * iwl4965_rx_queue_restock - refill RX queue from pre-allocated pool
b481de9c 4369 *
9fbab516 4370 * If there are slots in the RX queue that need to be restocked,
b481de9c 4371 * and we have free pre-allocated buffers, fill the ranks as much
9fbab516 4372 * as we can, pulling from rx_free.
b481de9c
ZY		 4373 *
4374 * This moves the 'write' index forward to catch up with 'processed', and
4375 * also updates the memory address in the firmware to reference the new
4376 * target buffer.
4377 */
bb8c093b 4378static int iwl4965_rx_queue_restock(struct iwl4965_priv *priv)
b481de9c 4379{
bb8c093b 4380 struct iwl4965_rx_queue *rxq = &priv->rxq;
b481de9c 4381 struct list_head *element;
bb8c093b 4382 struct iwl4965_rx_mem_buffer *rxb;
b481de9c
ZY		 4383 unsigned long flags;
4384 int write, rc;
4385
4386 spin_lock_irqsave(&rxq->lock, flags);
4387 write = rxq->write & ~0x7;
bb8c093b 4388 while ((iwl4965_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
6440adb5 4389 /* Get next free Rx buffer, remove from free list */
b481de9c 4390 element = rxq->rx_free.next;
bb8c093b 4391 rxb = list_entry(element, struct iwl4965_rx_mem_buffer, list);
b481de9c 4392 list_del(element);
6440adb5
CB		 4393
4394 /* Point to Rx buffer via next RBD in circular buffer */
bb8c093b 4395 rxq->bd[rxq->write] = iwl4965_dma_addr2rbd_ptr(priv, rxb->dma_addr);
b481de9c
ZY		 4396 rxq->queue[rxq->write] = rxb;
4397 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
4398 rxq->free_count--;
4399 }
4400 spin_unlock_irqrestore(&rxq->lock, flags);
4401 /* If the pre-allocated buffer pool is dropping low, schedule to
4402 * refill it */
4403 if (rxq->free_count <= RX_LOW_WATERMARK)
4404 queue_work(priv->workqueue, &priv->rx_replenish);
4405
4406
6440adb5
CB		 4407 /* If we've added more space for the firmware to place data, tell it.
4408 * Increment device's write pointer in multiples of 8. */
b481de9c
ZY		 4409 if ((write != (rxq->write & ~0x7))
4410 || (abs(rxq->write - rxq->read) > 7)) {
4411 spin_lock_irqsave(&rxq->lock, flags);
4412 rxq->need_update = 1;
4413 spin_unlock_irqrestore(&rxq->lock, flags);
bb8c093b 4414 rc = iwl4965_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 4415 if (rc)
4416 return rc;
4417 }
4418
4419 return 0;
4420}
4421
4422/**
bb8c093b 4423 * iwl4965_rx_replenish - Move all used packet from rx_used to rx_free
b481de9c
ZY		 4424 *
4425 * When moving to rx_free an SKB is allocated for the slot.
4426 *
bb8c093b 4427 * Also restock the Rx queue via iwl4965_rx_queue_restock.
01ebd063 4428 * This is called as a scheduled work item (except for during initialization)
b481de9c 4429 */
5c0eef96 4430static void iwl4965_rx_allocate(struct iwl4965_priv *priv)
b481de9c 4431{
bb8c093b 4432 struct iwl4965_rx_queue *rxq = &priv->rxq;
b481de9c 4433 struct list_head *element;
bb8c093b 4434 struct iwl4965_rx_mem_buffer *rxb;
b481de9c
ZY		 4435 unsigned long flags;
4436 spin_lock_irqsave(&rxq->lock, flags);
4437 while (!list_empty(&rxq->rx_used)) {
4438 element = rxq->rx_used.next;
bb8c093b 4439 rxb = list_entry(element, struct iwl4965_rx_mem_buffer, list);
6440adb5
CB		 4440
4441 /* Alloc a new receive buffer */
b481de9c 4442 rxb->skb =
9ee1ba47
RR		 4443 alloc_skb(priv->hw_setting.rx_buf_size,
4444 __GFP_NOWARN | GFP_ATOMIC);
b481de9c
ZY		 4445 if (!rxb->skb) {
4446 if (net_ratelimit())
4447 printk(KERN_CRIT DRV_NAME
4448 ": Can not allocate SKB buffers\n");
4449 /* We don't reschedule replenish work here -- we will
4450 * call the restock method and if it still needs
4451 * more buffers it will schedule replenish */
4452 break;
4453 }
4454 priv->alloc_rxb_skb++;
4455 list_del(element);
6440adb5
CB		 4456
4457 /* Get physical address of RB/SKB */
b481de9c
ZY		 4458 rxb->dma_addr =
4459 pci_map_single(priv->pci_dev, rxb->skb->data,
9ee1ba47 4460 priv->hw_setting.rx_buf_size, PCI_DMA_FROMDEVICE);
b481de9c
ZY		 4461 list_add_tail(&rxb->list, &rxq->rx_free);
4462 rxq->free_count++;
4463 }
4464 spin_unlock_irqrestore(&rxq->lock, flags);
5c0eef96
MA		 4465}
4466
4467/*
4468 * this should be called while priv->lock is locked
4469*/
4fd1f841 4470static void __iwl4965_rx_replenish(void *data)
5c0eef96
MA		 4471{
4472 struct iwl4965_priv *priv = data;
4473
4474 iwl4965_rx_allocate(priv);
4475 iwl4965_rx_queue_restock(priv);
4476}
4477
4478
4479void iwl4965_rx_replenish(void *data)
4480{
4481 struct iwl4965_priv *priv = data;
4482 unsigned long flags;
4483
4484 iwl4965_rx_allocate(priv);
b481de9c
ZY		 4485
4486 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 4487 iwl4965_rx_queue_restock(priv);
b481de9c
ZY		 4488 spin_unlock_irqrestore(&priv->lock, flags);
4489}
4490
4491/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
9fbab516 4492 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
b481de9c
ZY		 4493 * This free routine walks the list of POOL entries and if SKB is set to
4494 * non NULL it is unmapped and freed
4495 */
bb8c093b 4496static void iwl4965_rx_queue_free(struct iwl4965_priv *priv, struct iwl4965_rx_queue *rxq)
b481de9c
ZY		 4497{
4498 int i;
4499 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
4500 if (rxq->pool[i].skb != NULL) {
4501 pci_unmap_single(priv->pci_dev,
4502 rxq->pool[i].dma_addr,
9ee1ba47
RR		 4503 priv->hw_setting.rx_buf_size,
4504 PCI_DMA_FROMDEVICE);
b481de9c
ZY		 4505 dev_kfree_skb(rxq->pool[i].skb);
4506 }
4507 }
4508
4509 pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
4510 rxq->dma_addr);
4511 rxq->bd = NULL;
4512}
4513
bb8c093b 4514int iwl4965_rx_queue_alloc(struct iwl4965_priv *priv)
b481de9c 4515{
bb8c093b 4516 struct iwl4965_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 4517 struct pci_dev *dev = priv->pci_dev;
4518 int i;
4519
4520 spin_lock_init(&rxq->lock);
4521 INIT_LIST_HEAD(&rxq->rx_free);
4522 INIT_LIST_HEAD(&rxq->rx_used);
6440adb5
CB		 4523
4524 /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
b481de9c
ZY		 4525 rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
4526 if (!rxq->bd)
4527 return -ENOMEM;
6440adb5 4528
b481de9c
ZY		 4529 /* Fill the rx_used queue with _all_ of the Rx buffers */
4530 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
4531 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
6440adb5 4532
b481de9c
ZY		 4533 /* Set us so that we have processed and used all buffers, but have
4534 * not restocked the Rx queue with fresh buffers */
4535 rxq->read = rxq->write = 0;
4536 rxq->free_count = 0;
4537 rxq->need_update = 0;
4538 return 0;
4539}
4540
bb8c093b 4541void iwl4965_rx_queue_reset(struct iwl4965_priv *priv, struct iwl4965_rx_queue *rxq)
b481de9c
ZY		 4542{
4543 unsigned long flags;
4544 int i;
4545 spin_lock_irqsave(&rxq->lock, flags);
4546 INIT_LIST_HEAD(&rxq->rx_free);
4547 INIT_LIST_HEAD(&rxq->rx_used);
4548 /* Fill the rx_used queue with _all_ of the Rx buffers */
4549 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
4550 /* In the reset function, these buffers may have been allocated
4551 * to an SKB, so we need to unmap and free potential storage */
4552 if (rxq->pool[i].skb != NULL) {
4553 pci_unmap_single(priv->pci_dev,
4554 rxq->pool[i].dma_addr,
9ee1ba47
RR		 4555 priv->hw_setting.rx_buf_size,
4556 PCI_DMA_FROMDEVICE);
b481de9c
ZY		 4557 priv->alloc_rxb_skb--;
4558 dev_kfree_skb(rxq->pool[i].skb);
4559 rxq->pool[i].skb = NULL;
4560 }
4561 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
4562 }
4563
4564 /* Set us so that we have processed and used all buffers, but have
4565 * not restocked the Rx queue with fresh buffers */
4566 rxq->read = rxq->write = 0;
4567 rxq->free_count = 0;
4568 spin_unlock_irqrestore(&rxq->lock, flags);
4569}
4570
4571/* Convert linear signal-to-noise ratio into dB */
4572static u8 ratio2dB[100] = {
4573/* 0 1 2 3 4 5 6 7 8 9 */
4574 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
4575 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
4576 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
4577 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
4578 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
4579 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
4580 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
4581 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
4582 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
4583 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
4584};
4585
4586/* Calculates a relative dB value from a ratio of linear
4587 * (i.e. not dB) signal levels.
4588 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
bb8c093b 4589int iwl4965_calc_db_from_ratio(int sig_ratio)
b481de9c 4590{
c899a575
AB		 4591 /* 1000:1 or higher just report as 60 dB */
4592 if (sig_ratio >= 1000)
b481de9c
ZY		 4593 return 60;
4594
c899a575 4595 /* 100:1 or higher, divide by 10 and use table,
b481de9c 4596 * add 20 dB to make up for divide by 10 */
c899a575 4597 if (sig_ratio >= 100)
b481de9c
ZY		 4598 return (20 + (int)ratio2dB[sig_ratio/10]);
4599
4600 /* We shouldn't see this */
4601 if (sig_ratio < 1)
4602 return 0;
4603
4604 /* Use table for ratios 1:1 - 99:1 */
4605 return (int)ratio2dB[sig_ratio];
4606}
4607
4608#define PERFECT_RSSI (-20) /* dBm */
4609#define WORST_RSSI (-95) /* dBm */
4610#define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
4611
4612/* Calculate an indication of rx signal quality (a percentage, not dBm!).
4613 * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
4614 * about formulas used below. */
bb8c093b 4615int iwl4965_calc_sig_qual(int rssi_dbm, int noise_dbm)
b481de9c
ZY		 4616{
4617 int sig_qual;
4618 int degradation = PERFECT_RSSI - rssi_dbm;
4619
4620 /* If we get a noise measurement, use signal-to-noise ratio (SNR)
4621 * as indicator; formula is (signal dbm - noise dbm).
4622 * SNR at or above 40 is a great signal (100%).
4623 * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
4624 * Weakest usable signal is usually 10 - 15 dB SNR. */
4625 if (noise_dbm) {
4626 if (rssi_dbm - noise_dbm >= 40)
4627 return 100;
4628 else if (rssi_dbm < noise_dbm)
4629 return 0;
4630 sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
4631
4632 /* Else use just the signal level.
4633 * This formula is a least squares fit of data points collected and
4634 * compared with a reference system that had a percentage (%) display
4635 * for signal quality. */
4636 } else
4637 sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
4638 (15 * RSSI_RANGE + 62 * degradation)) /
4639 (RSSI_RANGE * RSSI_RANGE);
4640
4641 if (sig_qual > 100)
4642 sig_qual = 100;
4643 else if (sig_qual < 1)
4644 sig_qual = 0;
4645
4646 return sig_qual;
4647}
4648
4649/**
9fbab516 4650 * iwl4965_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY		 4651 *
4652 * Uses the priv->rx_handlers callback function array to invoke
4653 * the appropriate handlers, including command responses,
4654 * frame-received notifications, and other notifications.
4655 */
bb8c093b 4656static void iwl4965_rx_handle(struct iwl4965_priv *priv)
b481de9c 4657{
bb8c093b
CH		 4658 struct iwl4965_rx_mem_buffer *rxb;
4659 struct iwl4965_rx_packet *pkt;
4660 struct iwl4965_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 4661 u32 r, i;
4662 int reclaim;
4663 unsigned long flags;
5c0eef96
MA		 4664 u8 fill_rx = 0;
4665 u32 count = 0;
b481de9c 4666
6440adb5
CB		 4667 /* uCode's read index (stored in shared DRAM) indicates the last Rx
4668 * buffer that the driver may process (last buffer filled by ucode). */
bb8c093b 4669 r = iwl4965_hw_get_rx_read(priv);
b481de9c
ZY		 4670 i = rxq->read;
4671
4672 /* Rx interrupt, but nothing sent from uCode */
4673 if (i == r)
4674 IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
4675
5c0eef96
MA		 4676 if (iwl4965_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
4677 fill_rx = 1;
4678
b481de9c
ZY		 4679 while (i != r) {
4680 rxb = rxq->queue[i];
4681
9fbab516 4682 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY		 4683 * then a bug has been introduced in the queue refilling
4684 * routines -- catch it here */
4685 BUG_ON(rxb == NULL);
4686
4687 rxq->queue[i] = NULL;
4688
4689 pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
9ee1ba47 4690 priv->hw_setting.rx_buf_size,
b481de9c 4691 PCI_DMA_FROMDEVICE);
bb8c093b 4692 pkt = (struct iwl4965_rx_packet *)rxb->skb->data;
b481de9c
ZY		 4693
4694 /* Reclaim a command buffer only if this packet is a response
4695 * to a (driver-originated) command.
4696 * If the packet (e.g. Rx frame) originated from uCode,
4697 * there is no command buffer to reclaim.
4698 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
4699 * but apparently a few don't get set; catch them here. */
4700 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
4701 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
4702 (pkt->hdr.cmd != REPLY_4965_RX) &&
cfe01709 4703 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY		 4704 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
4705 (pkt->hdr.cmd != REPLY_TX);
4706
4707 /* Based on type of command response or notification,
4708 * handle those that need handling via function in
bb8c093b 4709 * rx_handlers table. See iwl4965_setup_rx_handlers() */
b481de9c
ZY		 4710 if (priv->rx_handlers[pkt->hdr.cmd]) {
4711 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
4712 "r = %d, i = %d, %s, 0x%02x\n", r, i,
4713 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
4714 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
4715 } else {
4716 /* No handling needed */
4717 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
4718 "r %d i %d No handler needed for %s, 0x%02x\n",
4719 r, i, get_cmd_string(pkt->hdr.cmd),
4720 pkt->hdr.cmd);
4721 }
4722
4723 if (reclaim) {
9fbab516
BC		 4724 /* Invoke any callbacks, transfer the skb to caller, and
4725 * fire off the (possibly) blocking iwl4965_send_cmd()
b481de9c
ZY		 4726 * as we reclaim the driver command queue */
4727 if (rxb && rxb->skb)
bb8c093b 4728 iwl4965_tx_cmd_complete(priv, rxb);
b481de9c
ZY		 4729 else
4730 IWL_WARNING("Claim null rxb?\n");
4731 }
4732
4733 /* For now we just don't re-use anything. We can tweak this
4734 * later to try and re-use notification packets and SKBs that
4735 * fail to Rx correctly */
4736 if (rxb->skb != NULL) {
4737 priv->alloc_rxb_skb--;
4738 dev_kfree_skb_any(rxb->skb);
4739 rxb->skb = NULL;
4740 }
4741
4742 pci_unmap_single(priv->pci_dev, rxb->dma_addr,
9ee1ba47
RR		 4743 priv->hw_setting.rx_buf_size,
4744 PCI_DMA_FROMDEVICE);
b481de9c
ZY		 4745 spin_lock_irqsave(&rxq->lock, flags);
4746 list_add_tail(&rxb->list, &priv->rxq.rx_used);
4747 spin_unlock_irqrestore(&rxq->lock, flags);
4748 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA		 4749 /* If there are a lot of unused frames,
4750 * restock the Rx queue so ucode wont assert. */
4751 if (fill_rx) {
4752 count++;
4753 if (count >= 8) {
4754 priv->rxq.read = i;
4755 __iwl4965_rx_replenish(priv);
4756 count = 0;
4757 }
4758 }
b481de9c
ZY		 4759 }
4760
4761 /* Backtrack one entry */
4762 priv->rxq.read = i;
bb8c093b 4763 iwl4965_rx_queue_restock(priv);
b481de9c
ZY		 4764}
4765
6440adb5
CB		 4766/**
4767 * iwl4965_tx_queue_update_write_ptr - Send new write index to hardware
4768 */
bb8c093b
CH		 4769static int iwl4965_tx_queue_update_write_ptr(struct iwl4965_priv *priv,
4770 struct iwl4965_tx_queue *txq)
b481de9c
ZY		 4771{
4772 u32 reg = 0;
4773 int rc = 0;
4774 int txq_id = txq->q.id;
4775
4776 if (txq->need_update == 0)
4777 return rc;
4778
4779 /* if we're trying to save power */
4780 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
4781 /* wake up nic if it's powered down ...
4782 * uCode will wake up, and interrupt us again, so next
4783 * time we'll skip this part. */
bb8c093b 4784 reg = iwl4965_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY		 4785
4786 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
4787 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
bb8c093b 4788 iwl4965_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 4789 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
4790 return rc;
4791 }
4792
4793 /* restore this queue's parameters in nic hardware. */
bb8c093b 4794 rc = iwl4965_grab_nic_access(priv);
b481de9c
ZY		 4795 if (rc)
4796 return rc;
bb8c093b 4797 iwl4965_write_direct32(priv, HBUS_TARG_WRPTR,
fc4b6853 4798 txq->q.write_ptr | (txq_id << 8));
bb8c093b 4799 iwl4965_release_nic_access(priv);
b481de9c
ZY		 4800
4801 /* else not in power-save mode, uCode will never sleep when we're
4802 * trying to tx (during RFKILL, we're not trying to tx). */
4803 } else
bb8c093b 4804 iwl4965_write32(priv, HBUS_TARG_WRPTR,
fc4b6853 4805 txq->q.write_ptr | (txq_id << 8));
b481de9c
ZY		 4806
4807 txq->need_update = 0;
4808
4809 return rc;
4810}
4811
c8b0e6e1 4812#ifdef CONFIG_IWL4965_DEBUG
bb8c093b 4813static void iwl4965_print_rx_config_cmd(struct iwl4965_rxon_cmd *rxon)
b481de9c 4814{
0795af57
JP		 4815 DECLARE_MAC_BUF(mac);
4816
b481de9c 4817 IWL_DEBUG_RADIO("RX CONFIG:\n");
bb8c093b 4818 iwl4965_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
b481de9c
ZY		 4819 IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
4820 IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
4821 IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
4822 le32_to_cpu(rxon->filter_flags));
4823 IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
4824 IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
4825 rxon->ofdm_basic_rates);
4826 IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
0795af57
JP		 4827 IWL_DEBUG_RADIO("u8[6] node_addr: %s\n",
4828 print_mac(mac, rxon->node_addr));
4829 IWL_DEBUG_RADIO("u8[6] bssid_addr: %s\n",
4830 print_mac(mac, rxon->bssid_addr));
b481de9c
ZY		 4831 IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
4832}
4833#endif
4834
bb8c093b 4835static void iwl4965_enable_interrupts(struct iwl4965_priv *priv)
b481de9c
ZY		 4836{
4837 IWL_DEBUG_ISR("Enabling interrupts\n");
4838 set_bit(STATUS_INT_ENABLED, &priv->status);
bb8c093b 4839 iwl4965_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
b481de9c
ZY		 4840}
4841
bb8c093b 4842static inline void iwl4965_disable_interrupts(struct iwl4965_priv *priv)
b481de9c
ZY		 4843{
4844 clear_bit(STATUS_INT_ENABLED, &priv->status);
4845
4846 /* disable interrupts from uCode/NIC to host */
bb8c093b 4847 iwl4965_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY		 4848
4849 /* acknowledge/clear/reset any interrupts still pending
4850 * from uCode or flow handler (Rx/Tx DMA) */
bb8c093b
CH		 4851 iwl4965_write32(priv, CSR_INT, 0xffffffff);
4852 iwl4965_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
b481de9c
ZY		 4853 IWL_DEBUG_ISR("Disabled interrupts\n");
4854}
4855
4856static const char *desc_lookup(int i)
4857{
4858 switch (i) {
4859 case 1:
4860 return "FAIL";
4861 case 2:
4862 return "BAD_PARAM";
4863 case 3:
4864 return "BAD_CHECKSUM";
4865 case 4:
4866 return "NMI_INTERRUPT";
4867 case 5:
4868 return "SYSASSERT";
4869 case 6:
4870 return "FATAL_ERROR";
4871 }
4872
4873 return "UNKNOWN";
4874}
4875
4876#define ERROR_START_OFFSET (1 * sizeof(u32))
4877#define ERROR_ELEM_SIZE (7 * sizeof(u32))
4878
bb8c093b 4879static void iwl4965_dump_nic_error_log(struct iwl4965_priv *priv)
b481de9c
ZY		 4880{
4881 u32 data2, line;
4882 u32 desc, time, count, base, data1;
4883 u32 blink1, blink2, ilink1, ilink2;
4884 int rc;
4885
4886 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
4887
bb8c093b 4888 if (!iwl4965_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 4889 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
4890 return;
4891 }
4892
bb8c093b 4893 rc = iwl4965_grab_nic_access(priv);
b481de9c
ZY		 4894 if (rc) {
4895 IWL_WARNING("Can not read from adapter at this time.\n");
4896 return;
4897 }
4898
bb8c093b 4899 count = iwl4965_read_targ_mem(priv, base);
b481de9c
ZY		 4900
4901 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
4902 IWL_ERROR("Start IWL Error Log Dump:\n");
4903 IWL_ERROR("Status: 0x%08lX, Config: %08X count: %d\n",
4904 priv->status, priv->config, count);
4905 }
4906
bb8c093b
CH		 4907 desc = iwl4965_read_targ_mem(priv, base + 1 * sizeof(u32));
4908 blink1 = iwl4965_read_targ_mem(priv, base + 3 * sizeof(u32));
4909 blink2 = iwl4965_read_targ_mem(priv, base + 4 * sizeof(u32));
4910 ilink1 = iwl4965_read_targ_mem(priv, base + 5 * sizeof(u32));
4911 ilink2 = iwl4965_read_targ_mem(priv, base + 6 * sizeof(u32));
4912 data1 = iwl4965_read_targ_mem(priv, base + 7 * sizeof(u32));
4913 data2 = iwl4965_read_targ_mem(priv, base + 8 * sizeof(u32));
4914 line = iwl4965_read_targ_mem(priv, base + 9 * sizeof(u32));
4915 time = iwl4965_read_targ_mem(priv, base + 11 * sizeof(u32));
b481de9c
ZY		 4916
4917 IWL_ERROR("Desc Time "
4918 "data1 data2 line\n");
4919 IWL_ERROR("%-13s (#%d) %010u 0x%08X 0x%08X %u\n",
4920 desc_lookup(desc), desc, time, data1, data2, line);
4921 IWL_ERROR("blink1 blink2 ilink1 ilink2\n");
4922 IWL_ERROR("0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
4923 ilink1, ilink2);
4924
bb8c093b 4925 iwl4965_release_nic_access(priv);
b481de9c
ZY		 4926}
4927
4928#define EVENT_START_OFFSET (4 * sizeof(u32))
4929
4930/**
bb8c093b 4931 * iwl4965_print_event_log - Dump error event log to syslog
b481de9c 4932 *
bb8c093b 4933 * NOTE: Must be called with iwl4965_grab_nic_access() already obtained!
b481de9c 4934 */
bb8c093b 4935static void iwl4965_print_event_log(struct iwl4965_priv *priv, u32 start_idx,
b481de9c
ZY		 4936 u32 num_events, u32 mode)
4937{
4938 u32 i;
4939 u32 base; /* SRAM byte address of event log header */
4940 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
4941 u32 ptr; /* SRAM byte address of log data */
4942 u32 ev, time, data; /* event log data */
4943
4944 if (num_events == 0)
4945 return;
4946
4947 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
4948
4949 if (mode == 0)
4950 event_size = 2 * sizeof(u32);
4951 else
4952 event_size = 3 * sizeof(u32);
4953
4954 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
4955
4956 /* "time" is actually "data" for mode 0 (no timestamp).
4957 * place event id # at far right for easier visual parsing. */
4958 for (i = 0; i < num_events; i++) {
bb8c093b 4959 ev = iwl4965_read_targ_mem(priv, ptr);
b481de9c 4960 ptr += sizeof(u32);
bb8c093b 4961 time = iwl4965_read_targ_mem(priv, ptr);
b481de9c
ZY		 4962 ptr += sizeof(u32);
4963 if (mode == 0)
4964 IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
4965 else {
bb8c093b 4966 data = iwl4965_read_targ_mem(priv, ptr);
b481de9c
ZY		 4967 ptr += sizeof(u32);
4968 IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
4969 }
4970 }
4971}
4972
bb8c093b 4973static void iwl4965_dump_nic_event_log(struct iwl4965_priv *priv)
b481de9c
ZY		 4974{
4975 int rc;
4976 u32 base; /* SRAM byte address of event log header */
4977 u32 capacity; /* event log capacity in # entries */
4978 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
4979 u32 num_wraps; /* # times uCode wrapped to top of log */
4980 u32 next_entry; /* index of next entry to be written by uCode */
4981 u32 size; /* # entries that we'll print */
4982
4983 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 4984 if (!iwl4965_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 4985 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
4986 return;
4987 }
4988
bb8c093b 4989 rc = iwl4965_grab_nic_access(priv);
b481de9c
ZY		 4990 if (rc) {
4991 IWL_WARNING("Can not read from adapter at this time.\n");
4992 return;
4993 }
4994
4995 /* event log header */
bb8c093b
CH		 4996 capacity = iwl4965_read_targ_mem(priv, base);
4997 mode = iwl4965_read_targ_mem(priv, base + (1 * sizeof(u32)));
4998 num_wraps = iwl4965_read_targ_mem(priv, base + (2 * sizeof(u32)));
4999 next_entry = iwl4965_read_targ_mem(priv, base + (3 * sizeof(u32)));
b481de9c
ZY		 5000
5001 size = num_wraps ? capacity : next_entry;
5002
5003 /* bail out if nothing in log */
5004 if (size == 0) {
583fab37 5005 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
bb8c093b 5006 iwl4965_release_nic_access(priv);
b481de9c
ZY		 5007 return;
5008 }
5009
583fab37 5010 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
b481de9c
ZY		 5011 size, num_wraps);
5012
5013 /* if uCode has wrapped back to top of log, start at the oldest entry,
5014 * i.e the next one that uCode would fill. */
5015 if (num_wraps)
bb8c093b 5016 iwl4965_print_event_log(priv, next_entry,
b481de9c
ZY		 5017 capacity - next_entry, mode);
5018
5019 /* (then/else) start at top of log */
bb8c093b 5020 iwl4965_print_event_log(priv, 0, next_entry, mode);
b481de9c 5021
bb8c093b 5022 iwl4965_release_nic_access(priv);
b481de9c
ZY		 5023}
5024
5025/**
bb8c093b 5026 * iwl4965_irq_handle_error - called for HW or SW error interrupt from card
b481de9c 5027 */
bb8c093b 5028static void iwl4965_irq_handle_error(struct iwl4965_priv *priv)
b481de9c 5029{
bb8c093b 5030 /* Set the FW error flag -- cleared on iwl4965_down */
b481de9c
ZY		 5031 set_bit(STATUS_FW_ERROR, &priv->status);
5032
5033 /* Cancel currently queued command. */
5034 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
5035
c8b0e6e1 5036#ifdef CONFIG_IWL4965_DEBUG
bb8c093b
CH		 5037 if (iwl4965_debug_level & IWL_DL_FW_ERRORS) {
5038 iwl4965_dump_nic_error_log(priv);
5039 iwl4965_dump_nic_event_log(priv);
5040 iwl4965_print_rx_config_cmd(&priv->staging_rxon);
b481de9c
ZY		 5041 }
5042#endif
5043
5044 wake_up_interruptible(&priv->wait_command_queue);
5045
5046 /* Keep the restart process from trying to send host
5047 * commands by clearing the INIT status bit */
5048 clear_bit(STATUS_READY, &priv->status);
5049
5050 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
5051 IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
5052 "Restarting adapter due to uCode error.\n");
5053
bb8c093b 5054 if (iwl4965_is_associated(priv)) {
b481de9c
ZY		 5055 memcpy(&priv->recovery_rxon, &priv->active_rxon,
5056 sizeof(priv->recovery_rxon));
5057 priv->error_recovering = 1;
5058 }
5059 queue_work(priv->workqueue, &priv->restart);
5060 }
5061}
5062
bb8c093b 5063static void iwl4965_error_recovery(struct iwl4965_priv *priv)
b481de9c
ZY		 5064{
5065 unsigned long flags;
5066
5067 memcpy(&priv->staging_rxon, &priv->recovery_rxon,
5068 sizeof(priv->staging_rxon));
5069 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 5070 iwl4965_commit_rxon(priv);
b481de9c 5071
bb8c093b 5072 iwl4965_rxon_add_station(priv, priv->bssid, 1);
b481de9c
ZY		 5073
5074 spin_lock_irqsave(&priv->lock, flags);
5075 priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
5076 priv->error_recovering = 0;
5077 spin_unlock_irqrestore(&priv->lock, flags);
5078}
5079
bb8c093b 5080static void iwl4965_irq_tasklet(struct iwl4965_priv *priv)
b481de9c
ZY		 5081{
5082 u32 inta, handled = 0;
5083 u32 inta_fh;
5084 unsigned long flags;
c8b0e6e1 5085#ifdef CONFIG_IWL4965_DEBUG
b481de9c
ZY		 5086 u32 inta_mask;
5087#endif
5088
5089 spin_lock_irqsave(&priv->lock, flags);
5090
5091 /* Ack/clear/reset pending uCode interrupts.
5092 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
5093 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
bb8c093b
CH		 5094 inta = iwl4965_read32(priv, CSR_INT);
5095 iwl4965_write32(priv, CSR_INT, inta);
b481de9c
ZY		 5096
5097 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
5098 * Any new interrupts that happen after this, either while we're
5099 * in this tasklet, or later, will show up in next ISR/tasklet. */
bb8c093b
CH		 5100 inta_fh = iwl4965_read32(priv, CSR_FH_INT_STATUS);
5101 iwl4965_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 5102
c8b0e6e1 5103#ifdef CONFIG_IWL4965_DEBUG
bb8c093b 5104 if (iwl4965_debug_level & IWL_DL_ISR) {
9fbab516
BC		 5105 /* just for debug */
5106 inta_mask = iwl4965_read32(priv, CSR_INT_MASK);
b481de9c
ZY		 5107 IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
5108 inta, inta_mask, inta_fh);
5109 }
5110#endif
5111
5112 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
5113 * atomic, make sure that inta covers all the interrupts that
5114 * we've discovered, even if FH interrupt came in just after
5115 * reading CSR_INT. */
5116 if (inta_fh & CSR_FH_INT_RX_MASK)
5117 inta |= CSR_INT_BIT_FH_RX;
5118 if (inta_fh & CSR_FH_INT_TX_MASK)
5119 inta |= CSR_INT_BIT_FH_TX;
5120
5121 /* Now service all interrupt bits discovered above. */
5122 if (inta & CSR_INT_BIT_HW_ERR) {
5123 IWL_ERROR("Microcode HW error detected. Restarting.\n");
5124
5125 /* Tell the device to stop sending interrupts */
bb8c093b 5126 iwl4965_disable_interrupts(priv);
b481de9c 5127
bb8c093b 5128 iwl4965_irq_handle_error(priv);
b481de9c
ZY		 5129
5130 handled |= CSR_INT_BIT_HW_ERR;
5131
5132 spin_unlock_irqrestore(&priv->lock, flags);
5133
5134 return;
5135 }
5136
c8b0e6e1 5137#ifdef CONFIG_IWL4965_DEBUG
bb8c093b 5138 if (iwl4965_debug_level & (IWL_DL_ISR)) {
b481de9c
ZY		 5139 /* NIC fires this, but we don't use it, redundant with WAKEUP */
5140 if (inta & CSR_INT_BIT_MAC_CLK_ACTV)
5141 IWL_DEBUG_ISR("Microcode started or stopped.\n");
5142
5143 /* Alive notification via Rx interrupt will do the real work */
5144 if (inta & CSR_INT_BIT_ALIVE)
5145 IWL_DEBUG_ISR("Alive interrupt\n");
5146 }
5147#endif
5148 /* Safely ignore these bits for debug checks below */
5149 inta &= ~(CSR_INT_BIT_MAC_CLK_ACTV | CSR_INT_BIT_ALIVE);
5150
9fbab516 5151 /* HW RF KILL switch toggled */
b481de9c
ZY		 5152 if (inta & CSR_INT_BIT_RF_KILL) {
5153 int hw_rf_kill = 0;
bb8c093b 5154 if (!(iwl4965_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY		 5155 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
5156 hw_rf_kill = 1;
5157
5158 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR,
5159 "RF_KILL bit toggled to %s.\n",
5160 hw_rf_kill ? "disable radio":"enable radio");
5161
5162 /* Queue restart only if RF_KILL switch was set to "kill"
5163 * when we loaded driver, and is now set to "enable".
5164 * After we're Alive, RF_KILL gets handled by
5165 * iwl_rx_card_state_notif() */
53e49093
ZY		 5166 if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) {
5167 clear_bit(STATUS_RF_KILL_HW, &priv->status);
b481de9c 5168 queue_work(priv->workqueue, &priv->restart);
53e49093 5169 }
b481de9c
ZY		 5170
5171 handled |= CSR_INT_BIT_RF_KILL;
5172 }
5173
9fbab516 5174 /* Chip got too hot and stopped itself */
b481de9c
ZY		 5175 if (inta & CSR_INT_BIT_CT_KILL) {
5176 IWL_ERROR("Microcode CT kill error detected.\n");
5177 handled |= CSR_INT_BIT_CT_KILL;
5178 }
5179
5180 /* Error detected by uCode */
5181 if (inta & CSR_INT_BIT_SW_ERR) {
5182 IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
5183 inta);
bb8c093b 5184 iwl4965_irq_handle_error(priv);
b481de9c
ZY		 5185 handled |= CSR_INT_BIT_SW_ERR;
5186 }
5187
5188 /* uCode wakes up after power-down sleep */
5189 if (inta & CSR_INT_BIT_WAKEUP) {
5190 IWL_DEBUG_ISR("Wakeup interrupt\n");
bb8c093b
CH		 5191 iwl4965_rx_queue_update_write_ptr(priv, &priv->rxq);
5192 iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[0]);
5193 iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[1]);
5194 iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[2]);
5195 iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[3]);
5196 iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[4]);
5197 iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[5]);
b481de9c
ZY		 5198
5199 handled |= CSR_INT_BIT_WAKEUP;
5200 }
5201
5202 /* All uCode command responses, including Tx command responses,
5203 * Rx "responses" (frame-received notification), and other
5204 * notifications from uCode come through here*/
5205 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
bb8c093b 5206 iwl4965_rx_handle(priv);
b481de9c
ZY		 5207 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
5208 }
5209
5210 if (inta & CSR_INT_BIT_FH_TX) {
5211 IWL_DEBUG_ISR("Tx interrupt\n");
5212 handled |= CSR_INT_BIT_FH_TX;
5213 }
5214
5215 if (inta & ~handled)
5216 IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
5217
5218 if (inta & ~CSR_INI_SET_MASK) {
5219 IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
5220 inta & ~CSR_INI_SET_MASK);
5221 IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
5222 }
5223
5224 /* Re-enable all interrupts */
bb8c093b 5225 iwl4965_enable_interrupts(priv);
b481de9c 5226
c8b0e6e1 5227#ifdef CONFIG_IWL4965_DEBUG
bb8c093b
CH		 5228 if (iwl4965_debug_level & (IWL_DL_ISR)) {
5229 inta = iwl4965_read32(priv, CSR_INT);
5230 inta_mask = iwl4965_read32(priv, CSR_INT_MASK);
5231 inta_fh = iwl4965_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY		 5232 IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
5233 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
5234 }
5235#endif
5236 spin_unlock_irqrestore(&priv->lock, flags);
5237}
5238
bb8c093b 5239static irqreturn_t iwl4965_isr(int irq, void *data)
b481de9c 5240{
bb8c093b 5241 struct iwl4965_priv *priv = data;
b481de9c
ZY		 5242 u32 inta, inta_mask;
5243 u32 inta_fh;
5244 if (!priv)
5245 return IRQ_NONE;
5246
5247 spin_lock(&priv->lock);
5248
5249 /* Disable (but don't clear!) interrupts here to avoid
5250 * back-to-back ISRs and sporadic interrupts from our NIC.
5251 * If we have something to service, the tasklet will re-enable ints.
5252 * If we *don't* have something, we'll re-enable before leaving here. */
bb8c093b
CH		 5253 inta_mask = iwl4965_read32(priv, CSR_INT_MASK); /* just for debug */
5254 iwl4965_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY		 5255
5256 /* Discover which interrupts are active/pending */
bb8c093b
CH		 5257 inta = iwl4965_read32(priv, CSR_INT);
5258 inta_fh = iwl4965_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY		 5259
5260 /* Ignore interrupt if there's nothing in NIC to service.
5261 * This may be due to IRQ shared with another device,
5262 * or due to sporadic interrupts thrown from our NIC. */
5263 if (!inta && !inta_fh) {
5264 IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
5265 goto none;
5266 }
5267
5268 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
66fbb541
ON		 5269 /* Hardware disappeared. It might have already raised
5270 * an interrupt */
b481de9c 5271 IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta);
66fbb541 5272 goto unplugged;
b481de9c
ZY		 5273 }
5274
5275 IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
5276 inta, inta_mask, inta_fh);
5277
bb8c093b 5278 /* iwl4965_irq_tasklet() will service interrupts and re-enable them */
b481de9c 5279 tasklet_schedule(&priv->irq_tasklet);
b481de9c 5280
66fbb541
ON		 5281 unplugged:
5282 spin_unlock(&priv->lock);
b481de9c
ZY		 5283 return IRQ_HANDLED;
5284
5285 none:
5286 /* re-enable interrupts here since we don't have anything to service. */
bb8c093b 5287 iwl4965_enable_interrupts(priv);
b481de9c
ZY		 5288 spin_unlock(&priv->lock);
5289 return IRQ_NONE;
5290}
5291
5292/************************** EEPROM BANDS ****************************
5293 *
bb8c093b 5294 * The iwl4965_eeprom_band definitions below provide the mapping from the
b481de9c
ZY		 5295 * EEPROM contents to the specific channel number supported for each
5296 * band.
5297 *
bb8c093b 5298 * For example, iwl4965_priv->eeprom.band_3_channels[4] from the band_3
b481de9c
ZY		 5299 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
5300 * The specific geography and calibration information for that channel
5301 * is contained in the eeprom map itself.
5302 *
5303 * During init, we copy the eeprom information and channel map
5304 * information into priv->channel_info_24/52 and priv->channel_map_24/52
5305 *
5306 * channel_map_24/52 provides the index in the channel_info array for a
5307 * given channel. We have to have two separate maps as there is channel
5308 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
5309 * band_2
5310 *
5311 * A value of 0xff stored in the channel_map indicates that the channel
5312 * is not supported by the hardware at all.
5313 *
5314 * A value of 0xfe in the channel_map indicates that the channel is not
5315 * valid for Tx with the current hardware. This means that
5316 * while the system can tune and receive on a given channel, it may not
5317 * be able to associate or transmit any frames on that
5318 * channel. There is no corresponding channel information for that
5319 * entry.
5320 *
5321 *********************************************************************/
5322
5323/* 2.4 GHz */
bb8c093b 5324static const u8 iwl4965_eeprom_band_1[14] = {
b481de9c
ZY		 5325 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
5326};
5327
5328/* 5.2 GHz bands */
9fbab516 5329static const u8 iwl4965_eeprom_band_2[] = { /* 4915-5080MHz */
b481de9c
ZY		 5330 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
5331};
5332
9fbab516 5333static const u8 iwl4965_eeprom_band_3[] = { /* 5170-5320MHz */
b481de9c
ZY		 5334 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
5335};
5336
bb8c093b 5337static const u8 iwl4965_eeprom_band_4[] = { /* 5500-5700MHz */
b481de9c
ZY		 5338 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
5339};
5340
bb8c093b 5341static const u8 iwl4965_eeprom_band_5[] = { /* 5725-5825MHz */
b481de9c
ZY		 5342 145, 149, 153, 157, 161, 165
5343};
5344
bb8c093b 5345static u8 iwl4965_eeprom_band_6[] = { /* 2.4 FAT channel */
b481de9c
ZY		 5346 1, 2, 3, 4, 5, 6, 7
5347};
5348
bb8c093b 5349static u8 iwl4965_eeprom_band_7[] = { /* 5.2 FAT channel */
b481de9c
ZY		 5350 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157
5351};
5352
9fbab516
BC		 5353static void iwl4965_init_band_reference(const struct iwl4965_priv *priv,
5354 int band,
b481de9c 5355 int *eeprom_ch_count,
bb8c093b 5356 const struct iwl4965_eeprom_channel
b481de9c
ZY		 5357 **eeprom_ch_info,
5358 const u8 **eeprom_ch_index)
5359{
5360 switch (band) {
5361 case 1: /* 2.4GHz band */
bb8c093b 5362 *eeprom_ch_count = ARRAY_SIZE(iwl4965_eeprom_band_1);
b481de9c 5363 *eeprom_ch_info = priv->eeprom.band_1_channels;
bb8c093b 5364 *eeprom_ch_index = iwl4965_eeprom_band_1;
b481de9c 5365 break;
9fbab516 5366 case 2: /* 4.9GHz band */
bb8c093b 5367 *eeprom_ch_count = ARRAY_SIZE(iwl4965_eeprom_band_2);
b481de9c 5368 *eeprom_ch_info = priv->eeprom.band_2_channels;
bb8c093b 5369 *eeprom_ch_index = iwl4965_eeprom_band_2;
b481de9c
ZY		 5370 break;
5371 case 3: /* 5.2GHz band */
bb8c093b 5372 *eeprom_ch_count = ARRAY_SIZE(iwl4965_eeprom_band_3);
b481de9c 5373 *eeprom_ch_info = priv->eeprom.band_3_channels;
bb8c093b 5374 *eeprom_ch_index = iwl4965_eeprom_band_3;
b481de9c 5375 break;
9fbab516 5376 case 4: /* 5.5GHz band */
bb8c093b 5377 *eeprom_ch_count = ARRAY_SIZE(iwl4965_eeprom_band_4);
b481de9c 5378 *eeprom_ch_info = priv->eeprom.band_4_channels;
bb8c093b 5379 *eeprom_ch_index = iwl4965_eeprom_band_4;
b481de9c 5380 break;
9fbab516 5381 case 5: /* 5.7GHz band */
bb8c093b 5382 *eeprom_ch_count = ARRAY_SIZE(iwl4965_eeprom_band_5);
b481de9c 5383 *eeprom_ch_info = priv->eeprom.band_5_channels;
bb8c093b 5384 *eeprom_ch_index = iwl4965_eeprom_band_5;
b481de9c 5385 break;
9fbab516 5386 case 6: /* 2.4GHz FAT channels */
bb8c093b 5387 *eeprom_ch_count = ARRAY_SIZE(iwl4965_eeprom_band_6);
b481de9c 5388 *eeprom_ch_info = priv->eeprom.band_24_channels;
bb8c093b 5389 *eeprom_ch_index = iwl4965_eeprom_band_6;
b481de9c 5390 break;
9fbab516 5391 case 7: /* 5 GHz FAT channels */
bb8c093b 5392 *eeprom_ch_count = ARRAY_SIZE(iwl4965_eeprom_band_7);
b481de9c 5393 *eeprom_ch_info = priv->eeprom.band_52_channels;
bb8c093b 5394 *eeprom_ch_index = iwl4965_eeprom_band_7;
b481de9c
ZY		 5395 break;
5396 default:
5397 BUG();
5398 return;
5399 }
5400}
5401
6440adb5
CB		 5402/**
5403 * iwl4965_get_channel_info - Find driver's private channel info
5404 *
5405 * Based on band and channel number.
5406 */
bb8c093b 5407const struct iwl4965_channel_info *iwl4965_get_channel_info(const struct iwl4965_priv *priv,
b481de9c
ZY		 5408 int phymode, u16 channel)
5409{
5410 int i;
5411
5412 switch (phymode) {
5413 case MODE_IEEE80211A:
5414 for (i = 14; i < priv->channel_count; i++) {
5415 if (priv->channel_info[i].channel == channel)
5416 return &priv->channel_info[i];
5417 }
5418 break;
5419
5420 case MODE_IEEE80211B:
5421 case MODE_IEEE80211G:
5422 if (channel >= 1 && channel <= 14)
5423 return &priv->channel_info[channel - 1];
5424 break;
5425
5426 }
5427
5428 return NULL;
5429}
5430
5431#define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
5432 ? # x " " : "")
5433
6440adb5
CB		 5434/**
5435 * iwl4965_init_channel_map - Set up driver's info for all possible channels
5436 */
bb8c093b 5437static int iwl4965_init_channel_map(struct iwl4965_priv *priv)
b481de9c
ZY		 5438{
5439 int eeprom_ch_count = 0;
5440 const u8 *eeprom_ch_index = NULL;
bb8c093b 5441 const struct iwl4965_eeprom_channel *eeprom_ch_info = NULL;
b481de9c 5442 int band, ch;
bb8c093b 5443 struct iwl4965_channel_info *ch_info;
b481de9c
ZY		 5444
5445 if (priv->channel_count) {
5446 IWL_DEBUG_INFO("Channel map already initialized.\n");
5447 return 0;
5448 }
5449
5450 if (priv->eeprom.version < 0x2f) {
5451 IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
5452 priv->eeprom.version);
5453 return -EINVAL;
5454 }
5455
5456 IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
5457
5458 priv->channel_count =
bb8c093b
CH		 5459 ARRAY_SIZE(iwl4965_eeprom_band_1) +
5460 ARRAY_SIZE(iwl4965_eeprom_band_2) +
5461 ARRAY_SIZE(iwl4965_eeprom_band_3) +
5462 ARRAY_SIZE(iwl4965_eeprom_band_4) +
5463 ARRAY_SIZE(iwl4965_eeprom_band_5);
b481de9c
ZY		 5464
5465 IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
5466
bb8c093b 5467 priv->channel_info = kzalloc(sizeof(struct iwl4965_channel_info) *
b481de9c
ZY		 5468 priv->channel_count, GFP_KERNEL);
5469 if (!priv->channel_info) {
5470 IWL_ERROR("Could not allocate channel_info\n");
5471 priv->channel_count = 0;
5472 return -ENOMEM;
5473 }
5474
5475 ch_info = priv->channel_info;
5476
5477 /* Loop through the 5 EEPROM bands adding them in order to the
5478 * channel map we maintain (that contains additional information than
5479 * what just in the EEPROM) */
5480 for (band = 1; band <= 5; band++) {
5481
bb8c093b 5482 iwl4965_init_band_reference(priv, band, &eeprom_ch_count,
b481de9c
ZY		 5483 &eeprom_ch_info, &eeprom_ch_index);
5484
5485 /* Loop through each band adding each of the channels */
5486 for (ch = 0; ch < eeprom_ch_count; ch++) {
5487 ch_info->channel = eeprom_ch_index[ch];
5488 ch_info->phymode = (band == 1) ? MODE_IEEE80211B :
5489 MODE_IEEE80211A;
5490
5491 /* permanently store EEPROM's channel regulatory flags
5492 * and max power in channel info database. */
5493 ch_info->eeprom = eeprom_ch_info[ch];
5494
5495 /* Copy the run-time flags so they are there even on
5496 * invalid channels */
5497 ch_info->flags = eeprom_ch_info[ch].flags;
5498
5499 if (!(is_channel_valid(ch_info))) {
5500 IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
5501 "No traffic\n",
5502 ch_info->channel,
5503 ch_info->flags,
5504 is_channel_a_band(ch_info) ?
5505 "5.2" : "2.4");
5506 ch_info++;
5507 continue;
5508 }
5509
5510 /* Initialize regulatory-based run-time data */
5511 ch_info->max_power_avg = ch_info->curr_txpow =
5512 eeprom_ch_info[ch].max_power_avg;
5513 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
5514 ch_info->min_power = 0;
5515
5516 IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
5517 " %ddBm): Ad-Hoc %ssupported\n",
5518 ch_info->channel,
5519 is_channel_a_band(ch_info) ?
5520 "5.2" : "2.4",
5521 CHECK_AND_PRINT(IBSS),
5522 CHECK_AND_PRINT(ACTIVE),
5523 CHECK_AND_PRINT(RADAR),
5524 CHECK_AND_PRINT(WIDE),
5525 CHECK_AND_PRINT(NARROW),
5526 CHECK_AND_PRINT(DFS),
5527 eeprom_ch_info[ch].flags,
5528 eeprom_ch_info[ch].max_power_avg,
5529 ((eeprom_ch_info[ch].
5530 flags & EEPROM_CHANNEL_IBSS)
5531 && !(eeprom_ch_info[ch].
5532 flags & EEPROM_CHANNEL_RADAR))
5533 ? "" : "not ");
5534
5535 /* Set the user_txpower_limit to the highest power
5536 * supported by any channel */
5537 if (eeprom_ch_info[ch].max_power_avg >
5538 priv->user_txpower_limit)
5539 priv->user_txpower_limit =
5540 eeprom_ch_info[ch].max_power_avg;
5541
5542 ch_info++;
5543 }
5544 }
5545
6440adb5 5546 /* Two additional EEPROM bands for 2.4 and 5 GHz FAT channels */
b481de9c
ZY		 5547 for (band = 6; band <= 7; band++) {
5548 int phymode;
5549 u8 fat_extension_chan;
5550
bb8c093b 5551 iwl4965_init_band_reference(priv, band, &eeprom_ch_count,
b481de9c
ZY		 5552 &eeprom_ch_info, &eeprom_ch_index);
5553
6440adb5 5554 /* EEPROM band 6 is 2.4, band 7 is 5 GHz */
b481de9c 5555 phymode = (band == 6) ? MODE_IEEE80211B : MODE_IEEE80211A;
6440adb5 5556
b481de9c
ZY		 5557 /* Loop through each band adding each of the channels */
5558 for (ch = 0; ch < eeprom_ch_count; ch++) {
5559
5560 if ((band == 6) &&
5561 ((eeprom_ch_index[ch] == 5) ||
5562 (eeprom_ch_index[ch] == 6) ||
5563 (eeprom_ch_index[ch] == 7)))
5564 fat_extension_chan = HT_IE_EXT_CHANNEL_MAX;
5565 else
5566 fat_extension_chan = HT_IE_EXT_CHANNEL_ABOVE;
5567
6440adb5 5568 /* Set up driver's info for lower half */
b481de9c
ZY		 5569 iwl4965_set_fat_chan_info(priv, phymode,
5570 eeprom_ch_index[ch],
5571 &(eeprom_ch_info[ch]),
5572 fat_extension_chan);
5573
6440adb5 5574 /* Set up driver's info for upper half */
b481de9c
ZY		 5575 iwl4965_set_fat_chan_info(priv, phymode,
5576 (eeprom_ch_index[ch] + 4),
5577 &(eeprom_ch_info[ch]),
5578 HT_IE_EXT_CHANNEL_BELOW);
5579 }
5580 }
5581
5582 return 0;
5583}
5584
849e0dce
RC		 5585/*
5586 * iwl4965_free_channel_map - undo allocations in iwl4965_init_channel_map
5587 */
5588static void iwl4965_free_channel_map(struct iwl4965_priv *priv)
5589{
5590 kfree(priv->channel_info);
5591 priv->channel_count = 0;
5592}
5593
b481de9c
ZY		 5594/* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
5595 * sending probe req. This should be set long enough to hear probe responses
5596 * from more than one AP. */
5597#define IWL_ACTIVE_DWELL_TIME_24 (20) /* all times in msec */
5598#define IWL_ACTIVE_DWELL_TIME_52 (10)
5599
5600/* For faster active scanning, scan will move to the next channel if fewer than
5601 * PLCP_QUIET_THRESH packets are heard on this channel within
5602 * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
5603 * time if it's a quiet channel (nothing responded to our probe, and there's
5604 * no other traffic).
5605 * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
5606#define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
5607#define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(5) /* msec */
5608
5609/* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
5610 * Must be set longer than active dwell time.
5611 * For the most reliable scan, set > AP beacon interval (typically 100msec). */
5612#define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
5613#define IWL_PASSIVE_DWELL_TIME_52 (10)
5614#define IWL_PASSIVE_DWELL_BASE (100)
5615#define IWL_CHANNEL_TUNE_TIME 5
5616
bb8c093b 5617static inline u16 iwl4965_get_active_dwell_time(struct iwl4965_priv *priv, int phymode)
b481de9c
ZY		 5618{
5619 if (phymode == MODE_IEEE80211A)
5620 return IWL_ACTIVE_DWELL_TIME_52;
5621 else
5622 return IWL_ACTIVE_DWELL_TIME_24;
5623}
5624
bb8c093b 5625static u16 iwl4965_get_passive_dwell_time(struct iwl4965_priv *priv, int phymode)
b481de9c 5626{
bb8c093b 5627 u16 active = iwl4965_get_active_dwell_time(priv, phymode);
b481de9c
ZY		 5628 u16 passive = (phymode != MODE_IEEE80211A) ?
5629 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
5630 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
5631
bb8c093b 5632 if (iwl4965_is_associated(priv)) {
b481de9c
ZY		 5633 /* If we're associated, we clamp the maximum passive
5634 * dwell time to be 98% of the beacon interval (minus
5635 * 2 * channel tune time) */
5636 passive = priv->beacon_int;
5637 if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
5638 passive = IWL_PASSIVE_DWELL_BASE;
5639 passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
5640 }
5641
5642 if (passive <= active)
5643 passive = active + 1;
5644
5645 return passive;
5646}
5647
bb8c093b 5648static int iwl4965_get_channels_for_scan(struct iwl4965_priv *priv, int phymode,
b481de9c 5649 u8 is_active, u8 direct_mask,
bb8c093b 5650 struct iwl4965_scan_channel *scan_ch)
b481de9c
ZY		 5651{
5652 const struct ieee80211_channel *channels = NULL;
5653 const struct ieee80211_hw_mode *hw_mode;
bb8c093b 5654 const struct iwl4965_channel_info *ch_info;
b481de9c
ZY		 5655 u16 passive_dwell = 0;
5656 u16 active_dwell = 0;
5657 int added, i;
5658
bb8c093b 5659 hw_mode = iwl4965_get_hw_mode(priv, phymode);
b481de9c
ZY		 5660 if (!hw_mode)
5661 return 0;
5662
5663 channels = hw_mode->channels;
5664
bb8c093b
CH		 5665 active_dwell = iwl4965_get_active_dwell_time(priv, phymode);
5666 passive_dwell = iwl4965_get_passive_dwell_time(priv, phymode);
b481de9c
ZY		 5667
5668 for (i = 0, added = 0; i < hw_mode->num_channels; i++) {
5669 if (channels[i].chan ==
5670 le16_to_cpu(priv->active_rxon.channel)) {
bb8c093b 5671 if (iwl4965_is_associated(priv)) {
b481de9c
ZY		 5672 IWL_DEBUG_SCAN
5673 ("Skipping current channel %d\n",
5674 le16_to_cpu(priv->active_rxon.channel));
5675 continue;
5676 }
5677 } else if (priv->only_active_channel)
5678 continue;
5679
5680 scan_ch->channel = channels[i].chan;
5681
9fbab516
BC		 5682 ch_info = iwl4965_get_channel_info(priv, phymode,
5683 scan_ch->channel);
b481de9c
ZY		 5684 if (!is_channel_valid(ch_info)) {
5685 IWL_DEBUG_SCAN("Channel %d is INVALID for this SKU.\n",
5686 scan_ch->channel);
5687 continue;
5688 }
5689
5690 if (!is_active || is_channel_passive(ch_info) ||
5691 !(channels[i].flag & IEEE80211_CHAN_W_ACTIVE_SCAN))
5692 scan_ch->type = 0; /* passive */
5693 else
5694 scan_ch->type = 1; /* active */
5695
5696 if (scan_ch->type & 1)
5697 scan_ch->type |= (direct_mask << 1);
5698
5699 if (is_channel_narrow(ch_info))
5700 scan_ch->type |= (1 << 7);
5701
5702 scan_ch->active_dwell = cpu_to_le16(active_dwell);
5703 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
5704
9fbab516 5705 /* Set txpower levels to defaults */
b481de9c
ZY		 5706 scan_ch->tpc.dsp_atten = 110;
5707 /* scan_pwr_info->tpc.dsp_atten; */
5708
5709 /*scan_pwr_info->tpc.tx_gain; */
5710 if (phymode == MODE_IEEE80211A)
5711 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
5712 else {
5713 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
5714 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
9fbab516 5715 * power level:
8a1b0245 5716 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
b481de9c
ZY		 5717 */
5718 }
5719
5720 IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
5721 scan_ch->channel,
5722 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
5723 (scan_ch->type & 1) ?
5724 active_dwell : passive_dwell);
5725
5726 scan_ch++;
5727 added++;
5728 }
5729
5730 IWL_DEBUG_SCAN("total channels to scan %d \n", added);
5731 return added;
5732}
5733
bb8c093b 5734static void iwl4965_reset_channel_flag(struct iwl4965_priv *priv)
b481de9c
ZY		 5735{
5736 int i, j;
5737 for (i = 0; i < 3; i++) {
5738 struct ieee80211_hw_mode *hw_mode = (void *)&priv->modes[i];
5739 for (j = 0; j < hw_mode->num_channels; j++)
5740 hw_mode->channels[j].flag = hw_mode->channels[j].val;
5741 }
5742}
5743
bb8c093b 5744static void iwl4965_init_hw_rates(struct iwl4965_priv *priv,
b481de9c
ZY		 5745 struct ieee80211_rate *rates)
5746{
5747 int i;
5748
5749 for (i = 0; i < IWL_RATE_COUNT; i++) {
bb8c093b 5750 rates[i].rate = iwl4965_rates[i].ieee * 5;
b481de9c
ZY		 5751 rates[i].val = i; /* Rate scaling will work on indexes */
5752 rates[i].val2 = i;
5753 rates[i].flags = IEEE80211_RATE_SUPPORTED;
5754 /* Only OFDM have the bits-per-symbol set */
5755 if ((i <= IWL_LAST_OFDM_RATE) && (i >= IWL_FIRST_OFDM_RATE))
5756 rates[i].flags |= IEEE80211_RATE_OFDM;
5757 else {
5758 /*
5759 * If CCK 1M then set rate flag to CCK else CCK_2
5760 * which is CCK | PREAMBLE2
5761 */
bb8c093b 5762 rates[i].flags |= (iwl4965_rates[i].plcp == 10) ?
b481de9c
ZY		 5763 IEEE80211_RATE_CCK : IEEE80211_RATE_CCK_2;
5764 }
5765
5766 /* Set up which ones are basic rates... */
5767 if (IWL_BASIC_RATES_MASK & (1 << i))
5768 rates[i].flags |= IEEE80211_RATE_BASIC;
5769 }
b481de9c
ZY		 5770}
5771
5772/**
bb8c093b 5773 * iwl4965_init_geos - Initialize mac80211's geo/channel info based from eeprom
b481de9c 5774 */
bb8c093b 5775static int iwl4965_init_geos(struct iwl4965_priv *priv)
b481de9c 5776{
bb8c093b 5777 struct iwl4965_channel_info *ch;
b481de9c
ZY		 5778 struct ieee80211_hw_mode *modes;
5779 struct ieee80211_channel *channels;
5780 struct ieee80211_channel *geo_ch;
5781 struct ieee80211_rate *rates;
5782 int i = 0;
5783 enum {
5784 A = 0,
5785 B = 1,
5786 G = 2,
b481de9c 5787 };
326eeee8 5788 int mode_count = 3;
b481de9c
ZY		 5789
5790 if (priv->modes) {
5791 IWL_DEBUG_INFO("Geography modes already initialized.\n");
5792 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
5793 return 0;
5794 }
5795
5796 modes = kzalloc(sizeof(struct ieee80211_hw_mode) * mode_count,
5797 GFP_KERNEL);
5798 if (!modes)
5799 return -ENOMEM;
5800
5801 channels = kzalloc(sizeof(struct ieee80211_channel) *
5802 priv->channel_count, GFP_KERNEL);
5803 if (!channels) {
5804 kfree(modes);
5805 return -ENOMEM;
5806 }
5807
5808 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_MAX_RATES + 1)),
5809 GFP_KERNEL);
5810 if (!rates) {
5811 kfree(modes);
5812 kfree(channels);
5813 return -ENOMEM;
5814 }
5815
5816 /* 0 = 802.11a
5817 * 1 = 802.11b
5818 * 2 = 802.11g
5819 */
5820
5821 /* 5.2GHz channels start after the 2.4GHz channels */
5822 modes[A].mode = MODE_IEEE80211A;
bb8c093b 5823 modes[A].channels = &channels[ARRAY_SIZE(iwl4965_eeprom_band_1)];
b481de9c
ZY		 5824 modes[A].rates = rates;
5825 modes[A].num_rates = 8; /* just OFDM */
5826 modes[A].rates = &rates[4];
5827 modes[A].num_channels = 0;
326eeee8
RR		 5828#ifdef CONFIG_IWL4965_HT
5829 iwl4965_init_ht_hw_capab(&modes[A].ht_info, MODE_IEEE80211A);
5830#endif
b481de9c
ZY		 5831
5832 modes[B].mode = MODE_IEEE80211B;
5833 modes[B].channels = channels;
5834 modes[B].rates = rates;
5835 modes[B].num_rates = 4; /* just CCK */
5836 modes[B].num_channels = 0;
5837
5838 modes[G].mode = MODE_IEEE80211G;
5839 modes[G].channels = channels;
5840 modes[G].rates = rates;
5841 modes[G].num_rates = 12; /* OFDM & CCK */
5842 modes[G].num_channels = 0;
326eeee8
RR		 5843#ifdef CONFIG_IWL4965_HT
5844 iwl4965_init_ht_hw_capab(&modes[G].ht_info, MODE_IEEE80211G);
5845#endif
b481de9c
ZY		 5846
5847 priv->ieee_channels = channels;
5848 priv->ieee_rates = rates;
5849
bb8c093b 5850 iwl4965_init_hw_rates(priv, rates);
b481de9c
ZY		 5851
5852 for (i = 0, geo_ch = channels; i < priv->channel_count; i++) {
5853 ch = &priv->channel_info[i];
5854
5855 if (!is_channel_valid(ch)) {
5856 IWL_DEBUG_INFO("Channel %d [%sGHz] is restricted -- "
5857 "skipping.\n",
5858 ch->channel, is_channel_a_band(ch) ?
5859 "5.2" : "2.4");
5860 continue;
5861 }
5862
5863 if (is_channel_a_band(ch)) {
5864 geo_ch = &modes[A].channels[modes[A].num_channels++];
b481de9c
ZY		 5865 } else {
5866 geo_ch = &modes[B].channels[modes[B].num_channels++];
5867 modes[G].num_channels++;
b481de9c
ZY		 5868 }
5869
5870 geo_ch->freq = ieee80211chan2mhz(ch->channel);
5871 geo_ch->chan = ch->channel;
5872 geo_ch->power_level = ch->max_power_avg;
5873 geo_ch->antenna_max = 0xff;
5874
5875 if (is_channel_valid(ch)) {
5876 geo_ch->flag = IEEE80211_CHAN_W_SCAN;
5877 if (ch->flags & EEPROM_CHANNEL_IBSS)
5878 geo_ch->flag |= IEEE80211_CHAN_W_IBSS;
5879
5880 if (ch->flags & EEPROM_CHANNEL_ACTIVE)
5881 geo_ch->flag |= IEEE80211_CHAN_W_ACTIVE_SCAN;
5882
5883 if (ch->flags & EEPROM_CHANNEL_RADAR)
5884 geo_ch->flag |= IEEE80211_CHAN_W_RADAR_DETECT;
5885
5886 if (ch->max_power_avg > priv->max_channel_txpower_limit)
5887 priv->max_channel_txpower_limit =
5888 ch->max_power_avg;
5889 }
5890
5891 geo_ch->val = geo_ch->flag;
5892 }
5893
5894 if ((modes[A].num_channels == 0) && priv->is_abg) {
5895 printk(KERN_INFO DRV_NAME
5896 ": Incorrectly detected BG card as ABG. Please send "
5897 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
5898 priv->pci_dev->device, priv->pci_dev->subsystem_device);
5899 priv->is_abg = 0;
5900 }
5901
5902 printk(KERN_INFO DRV_NAME
5903 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
5904 modes[G].num_channels, modes[A].num_channels);
5905
5906 /*
5907 * NOTE: We register these in preference of order -- the
5908 * stack doesn't currently (as of 7.0.6 / Apr 24 '07) pick
5909 * a phymode based on rates or AP capabilities but seems to
5910 * configure it purely on if the channel being configured
5911 * is supported by a mode -- and the first match is taken
5912 */
5913
5914 if (modes[G].num_channels)
5915 ieee80211_register_hwmode(priv->hw, &modes[G]);
5916 if (modes[B].num_channels)
5917 ieee80211_register_hwmode(priv->hw, &modes[B]);
5918 if (modes[A].num_channels)
5919 ieee80211_register_hwmode(priv->hw, &modes[A]);
5920
5921 priv->modes = modes;
5922 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
5923
5924 return 0;
5925}
5926
849e0dce
RC		 5927/*
5928 * iwl4965_free_geos - undo allocations in iwl4965_init_geos
5929 */
5930static void iwl4965_free_geos(struct iwl4965_priv *priv)
5931{
5932 kfree(priv->modes);
5933 kfree(priv->ieee_channels);
5934 kfree(priv->ieee_rates);
5935 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
5936}
5937
b481de9c
ZY		 5938/******************************************************************************
5939 *
5940 * uCode download functions
5941 *
5942 ******************************************************************************/
5943
bb8c093b 5944static void iwl4965_dealloc_ucode_pci(struct iwl4965_priv *priv)
b481de9c 5945{
98c92211
TW		 5946 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
5947 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
5948 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
5949 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
5950 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
5951 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY		 5952}
5953
5954/**
bb8c093b 5955 * iwl4965_verify_inst_full - verify runtime uCode image in card vs. host,
b481de9c
ZY		 5956 * looking at all data.
5957 */
4fd1f841 5958static int iwl4965_verify_inst_full(struct iwl4965_priv *priv, __le32 *image,
9fbab516 5959 u32 len)
b481de9c
ZY		 5960{
5961 u32 val;
5962 u32 save_len = len;
5963 int rc = 0;
5964 u32 errcnt;
5965
5966 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5967
bb8c093b 5968 rc = iwl4965_grab_nic_access(priv);
b481de9c
ZY		 5969 if (rc)
5970 return rc;
5971
bb8c093b 5972 iwl4965_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
b481de9c
ZY		 5973
5974 errcnt = 0;
5975 for (; len > 0; len -= sizeof(u32), image++) {
5976 /* read data comes through single port, auto-incr addr */
5977 /* NOTE: Use the debugless read so we don't flood kernel log
5978 * if IWL_DL_IO is set */
bb8c093b 5979 val = _iwl4965_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY		 5980 if (val != le32_to_cpu(*image)) {
5981 IWL_ERROR("uCode INST section is invalid at "
5982 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5983 save_len - len, val, le32_to_cpu(*image));
5984 rc = -EIO;
5985 errcnt++;
5986 if (errcnt >= 20)
5987 break;
5988 }
5989 }
5990
bb8c093b 5991 iwl4965_release_nic_access(priv);
b481de9c
ZY		 5992
5993 if (!errcnt)
5994 IWL_DEBUG_INFO
5995 ("ucode image in INSTRUCTION memory is good\n");
5996
5997 return rc;
5998}
5999
6000
6001/**
bb8c093b 6002 * iwl4965_verify_inst_sparse - verify runtime uCode image in card vs. host,
b481de9c
ZY		 6003 * using sample data 100 bytes apart. If these sample points are good,
6004 * it's a pretty good bet that everything between them is good, too.
6005 */
bb8c093b 6006static int iwl4965_verify_inst_sparse(struct iwl4965_priv *priv, __le32 *image, u32 len)
b481de9c
ZY		 6007{
6008 u32 val;
6009 int rc = 0;
6010 u32 errcnt = 0;
6011 u32 i;
6012
6013 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
6014
bb8c093b 6015 rc = iwl4965_grab_nic_access(priv);
b481de9c
ZY		 6016 if (rc)
6017 return rc;
6018
6019 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
6020 /* read data comes through single port, auto-incr addr */
6021 /* NOTE: Use the debugless read so we don't flood kernel log
6022 * if IWL_DL_IO is set */
bb8c093b 6023 iwl4965_write_direct32(priv, HBUS_TARG_MEM_RADDR,
b481de9c 6024 i + RTC_INST_LOWER_BOUND);
bb8c093b 6025 val = _iwl4965_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY		 6026 if (val != le32_to_cpu(*image)) {
6027#if 0 /* Enable this if you want to see details */
6028 IWL_ERROR("uCode INST section is invalid at "
6029 "offset 0x%x, is 0x%x, s/b 0x%x\n",
6030 i, val, *image);
6031#endif
6032 rc = -EIO;
6033 errcnt++;
6034 if (errcnt >= 3)
6035 break;
6036 }
6037 }
6038
bb8c093b 6039 iwl4965_release_nic_access(priv);
b481de9c
ZY		 6040
6041 return rc;
6042}
6043
6044
6045/**
bb8c093b 6046 * iwl4965_verify_ucode - determine which instruction image is in SRAM,
b481de9c
ZY		 6047 * and verify its contents
6048 */
bb8c093b 6049static int iwl4965_verify_ucode(struct iwl4965_priv *priv)
b481de9c
ZY		 6050{
6051 __le32 *image;
6052 u32 len;
6053 int rc = 0;
6054
6055 /* Try bootstrap */
6056 image = (__le32 *)priv->ucode_boot.v_addr;
6057 len = priv->ucode_boot.len;
bb8c093b 6058 rc = iwl4965_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 6059 if (rc == 0) {
6060 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
6061 return 0;
6062 }
6063
6064 /* Try initialize */
6065 image = (__le32 *)priv->ucode_init.v_addr;
6066 len = priv->ucode_init.len;
bb8c093b 6067 rc = iwl4965_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 6068 if (rc == 0) {
6069 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
6070 return 0;
6071 }
6072
6073 /* Try runtime/protocol */
6074 image = (__le32 *)priv->ucode_code.v_addr;
6075 len = priv->ucode_code.len;
bb8c093b 6076 rc = iwl4965_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 6077 if (rc == 0) {
6078 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
6079 return 0;
6080 }
6081
6082 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
6083
9fbab516
BC		 6084 /* Since nothing seems to match, show first several data entries in
6085 * instruction SRAM, so maybe visual inspection will give a clue.
6086 * Selection of bootstrap image (vs. other images) is arbitrary. */
b481de9c
ZY		 6087 image = (__le32 *)priv->ucode_boot.v_addr;
6088 len = priv->ucode_boot.len;
bb8c093b 6089 rc = iwl4965_verify_inst_full(priv, image, len);
b481de9c
ZY		 6090
6091 return rc;
6092}
6093
6094
6095/* check contents of special bootstrap uCode SRAM */
bb8c093b 6096static int iwl4965_verify_bsm(struct iwl4965_priv *priv)
b481de9c
ZY		 6097{
6098 __le32 *image = priv->ucode_boot.v_addr;
6099 u32 len = priv->ucode_boot.len;
6100 u32 reg;
6101 u32 val;
6102
6103 IWL_DEBUG_INFO("Begin verify bsm\n");
6104
6105 /* verify BSM SRAM contents */
bb8c093b 6106 val = iwl4965_read_prph(priv, BSM_WR_DWCOUNT_REG);
b481de9c
ZY		 6107 for (reg = BSM_SRAM_LOWER_BOUND;
6108 reg < BSM_SRAM_LOWER_BOUND + len;
6109 reg += sizeof(u32), image ++) {
bb8c093b 6110 val = iwl4965_read_prph(priv, reg);
b481de9c
ZY		 6111 if (val != le32_to_cpu(*image)) {
6112 IWL_ERROR("BSM uCode verification failed at "
6113 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
6114 BSM_SRAM_LOWER_BOUND,
6115 reg - BSM_SRAM_LOWER_BOUND, len,
6116 val, le32_to_cpu(*image));
6117 return -EIO;
6118 }
6119 }
6120
6121 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
6122
6123 return 0;
6124}
6125
6126/**
bb8c093b 6127 * iwl4965_load_bsm - Load bootstrap instructions
b481de9c
ZY		 6128 *
6129 * BSM operation:
6130 *
6131 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
6132 * in special SRAM that does not power down during RFKILL. When powering back
6133 * up after power-saving sleeps (or during initial uCode load), the BSM loads
6134 * the bootstrap program into the on-board processor, and starts it.
6135 *
6136 * The bootstrap program loads (via DMA) instructions and data for a new
6137 * program from host DRAM locations indicated by the host driver in the
6138 * BSM_DRAM_* registers. Once the new program is loaded, it starts
6139 * automatically.
6140 *
6141 * When initializing the NIC, the host driver points the BSM to the
6142 * "initialize" uCode image. This uCode sets up some internal data, then
6143 * notifies host via "initialize alive" that it is complete.
6144 *
6145 * The host then replaces the BSM_DRAM_* pointer values to point to the
6146 * normal runtime uCode instructions and a backup uCode data cache buffer
6147 * (filled initially with starting data values for the on-board processor),
6148 * then triggers the "initialize" uCode to load and launch the runtime uCode,
6149 * which begins normal operation.
6150 *
6151 * When doing a power-save shutdown, runtime uCode saves data SRAM into
6152 * the backup data cache in DRAM before SRAM is powered down.
6153 *
6154 * When powering back up, the BSM loads the bootstrap program. This reloads
6155 * the runtime uCode instructions and the backup data cache into SRAM,
6156 * and re-launches the runtime uCode from where it left off.
6157 */
bb8c093b 6158static int iwl4965_load_bsm(struct iwl4965_priv *priv)
b481de9c
ZY		 6159{
6160 __le32 *image = priv->ucode_boot.v_addr;
6161 u32 len = priv->ucode_boot.len;
6162 dma_addr_t pinst;
6163 dma_addr_t pdata;
6164 u32 inst_len;
6165 u32 data_len;
6166 int rc;
6167 int i;
6168 u32 done;
6169 u32 reg_offset;
6170
6171 IWL_DEBUG_INFO("Begin load bsm\n");
6172
6173 /* make sure bootstrap program is no larger than BSM's SRAM size */
6174 if (len > IWL_MAX_BSM_SIZE)
6175 return -EINVAL;
6176
6177 /* Tell bootstrap uCode where to find the "Initialize" uCode
9fbab516 6178 * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
bb8c093b 6179 * NOTE: iwl4965_initialize_alive_start() will replace these values,
b481de9c
ZY		 6180 * after the "initialize" uCode has run, to point to
6181 * runtime/protocol instructions and backup data cache. */
6182 pinst = priv->ucode_init.p_addr >> 4;
6183 pdata = priv->ucode_init_data.p_addr >> 4;
6184 inst_len = priv->ucode_init.len;
6185 data_len = priv->ucode_init_data.len;
6186
bb8c093b 6187 rc = iwl4965_grab_nic_access(priv);
b481de9c
ZY		 6188 if (rc)
6189 return rc;
6190
bb8c093b
CH		 6191 iwl4965_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
6192 iwl4965_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
6193 iwl4965_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
6194 iwl4965_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
b481de9c
ZY		 6195
6196 /* Fill BSM memory with bootstrap instructions */
6197 for (reg_offset = BSM_SRAM_LOWER_BOUND;
6198 reg_offset < BSM_SRAM_LOWER_BOUND + len;
6199 reg_offset += sizeof(u32), image++)
bb8c093b 6200 _iwl4965_write_prph(priv, reg_offset,
b481de9c
ZY		 6201 le32_to_cpu(*image));
6202
bb8c093b 6203 rc = iwl4965_verify_bsm(priv);
b481de9c 6204 if (rc) {
bb8c093b 6205 iwl4965_release_nic_access(priv);
b481de9c
ZY		 6206 return rc;
6207 }
6208
6209 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
bb8c093b
CH		 6210 iwl4965_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
6211 iwl4965_write_prph(priv, BSM_WR_MEM_DST_REG,
b481de9c 6212 RTC_INST_LOWER_BOUND);
bb8c093b 6213 iwl4965_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
b481de9c
ZY		 6214
6215 /* Load bootstrap code into instruction SRAM now,
6216 * to prepare to load "initialize" uCode */
bb8c093b 6217 iwl4965_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY		 6218 BSM_WR_CTRL_REG_BIT_START);
6219
6220 /* Wait for load of bootstrap uCode to finish */
6221 for (i = 0; i < 100; i++) {
bb8c093b 6222 done = iwl4965_read_prph(priv, BSM_WR_CTRL_REG);
b481de9c
ZY		 6223 if (!(done & BSM_WR_CTRL_REG_BIT_START))
6224 break;
6225 udelay(10);
6226 }
6227 if (i < 100)
6228 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
6229 else {
6230 IWL_ERROR("BSM write did not complete!\n");
6231 return -EIO;
6232 }
6233
6234 /* Enable future boot loads whenever power management unit triggers it
6235 * (e.g. when powering back up after power-save shutdown) */
bb8c093b 6236 iwl4965_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY		 6237 BSM_WR_CTRL_REG_BIT_START_EN);
6238
bb8c093b 6239 iwl4965_release_nic_access(priv);
b481de9c
ZY		 6240
6241 return 0;
6242}
6243
bb8c093b 6244static void iwl4965_nic_start(struct iwl4965_priv *priv)
b481de9c
ZY		 6245{
6246 /* Remove all resets to allow NIC to operate */
bb8c093b 6247 iwl4965_write32(priv, CSR_RESET, 0);
b481de9c
ZY		 6248}
6249
90e759d1 6250
b481de9c 6251/**
bb8c093b 6252 * iwl4965_read_ucode - Read uCode images from disk file.
b481de9c
ZY		 6253 *
6254 * Copy into buffers for card to fetch via bus-mastering
6255 */
bb8c093b 6256static int iwl4965_read_ucode(struct iwl4965_priv *priv)
b481de9c 6257{
bb8c093b 6258 struct iwl4965_ucode *ucode;
90e759d1 6259 int ret;
b481de9c
ZY		 6260 const struct firmware *ucode_raw;
6261 const char *name = "iwlwifi-4965" IWL4965_UCODE_API ".ucode";
6262 u8 *src;
6263 size_t len;
6264 u32 ver, inst_size, data_size, init_size, init_data_size, boot_size;
6265
6266 /* Ask kernel firmware_class module to get the boot firmware off disk.
6267 * request_firmware() is synchronous, file is in memory on return. */
90e759d1
TW		 6268 ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev);
6269 if (ret < 0) {
6270 IWL_ERROR("%s firmware file req failed: Reason %d\n",
6271 name, ret);
b481de9c
ZY		 6272 goto error;
6273 }
6274
6275 IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
6276 name, ucode_raw->size);
6277
6278 /* Make sure that we got at least our header! */
6279 if (ucode_raw->size < sizeof(*ucode)) {
6280 IWL_ERROR("File size way too small!\n");
90e759d1 6281 ret = -EINVAL;
b481de9c
ZY		 6282 goto err_release;
6283 }
6284
6285 /* Data from ucode file: header followed by uCode images */
6286 ucode = (void *)ucode_raw->data;
6287
6288 ver = le32_to_cpu(ucode->ver);
6289 inst_size = le32_to_cpu(ucode->inst_size);
6290 data_size = le32_to_cpu(ucode->data_size);
6291 init_size = le32_to_cpu(ucode->init_size);
6292 init_data_size = le32_to_cpu(ucode->init_data_size);
6293 boot_size = le32_to_cpu(ucode->boot_size);
6294
6295 IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver);
6296 IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n",
6297 inst_size);
6298 IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n",
6299 data_size);
6300 IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n",
6301 init_size);
6302 IWL_DEBUG_INFO("f/w package hdr init data size = %u\n",
6303 init_data_size);
6304 IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n",
6305 boot_size);
6306
6307 /* Verify size of file vs. image size info in file's header */
6308 if (ucode_raw->size < sizeof(*ucode) +
6309 inst_size + data_size + init_size +
6310 init_data_size + boot_size) {
6311
6312 IWL_DEBUG_INFO("uCode file size %d too small\n",
6313 (int)ucode_raw->size);
90e759d1 6314 ret = -EINVAL;
b481de9c
ZY		 6315 goto err_release;
6316 }
6317
6318 /* Verify that uCode images will fit in card's SRAM */
6319 if (inst_size > IWL_MAX_INST_SIZE) {
90e759d1
TW		 6320 IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
6321 inst_size);
6322 ret = -EINVAL;
b481de9c
ZY		 6323 goto err_release;
6324 }
6325
6326 if (data_size > IWL_MAX_DATA_SIZE) {
90e759d1
TW		 6327 IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
6328 data_size);
6329 ret = -EINVAL;
b481de9c
ZY		 6330 goto err_release;
6331 }
6332 if (init_size > IWL_MAX_INST_SIZE) {
6333 IWL_DEBUG_INFO
90e759d1
TW		 6334 ("uCode init instr len %d too large to fit in\n",
6335 init_size);
6336 ret = -EINVAL;
b481de9c
ZY		 6337 goto err_release;
6338 }
6339 if (init_data_size > IWL_MAX_DATA_SIZE) {
6340 IWL_DEBUG_INFO
90e759d1
TW		 6341 ("uCode init data len %d too large to fit in\n",
6342 init_data_size);
6343 ret = -EINVAL;
b481de9c
ZY		 6344 goto err_release;
6345 }
6346 if (boot_size > IWL_MAX_BSM_SIZE) {
6347 IWL_DEBUG_INFO
90e759d1
TW		 6348 ("uCode boot instr len %d too large to fit in\n",
6349 boot_size);
6350 ret = -EINVAL;
b481de9c
ZY		 6351 goto err_release;
6352 }
6353
6354 /* Allocate ucode buffers for card's bus-master loading ... */
6355
6356 /* Runtime instructions and 2 copies of data:
6357 * 1) unmodified from disk
6358 * 2) backup cache for save/restore during power-downs */
6359 priv->ucode_code.len = inst_size;
98c92211 6360 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY		 6361
6362 priv->ucode_data.len = data_size;
98c92211 6363 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY		 6364
6365 priv->ucode_data_backup.len = data_size;
98c92211 6366 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c
ZY		 6367
6368 /* Initialization instructions and data */
90e759d1
TW		 6369 if (init_size && init_data_size) {
6370 priv->ucode_init.len = init_size;
98c92211 6371 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW		 6372
6373 priv->ucode_init_data.len = init_data_size;
98c92211 6374 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW		 6375
6376 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
6377 goto err_pci_alloc;
6378 }
b481de9c
ZY		 6379
6380 /* Bootstrap (instructions only, no data) */
90e759d1
TW		 6381 if (boot_size) {
6382 priv->ucode_boot.len = boot_size;
98c92211 6383 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 6384
90e759d1
TW		 6385 if (!priv->ucode_boot.v_addr)
6386 goto err_pci_alloc;
6387 }
b481de9c
ZY		 6388
6389 /* Copy images into buffers for card's bus-master reads ... */
6390
6391 /* Runtime instructions (first block of data in file) */
6392 src = &ucode->data[0];
6393 len = priv->ucode_code.len;
90e759d1 6394 IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c
ZY		 6395 memcpy(priv->ucode_code.v_addr, src, len);
6396 IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
6397 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
6398
6399 /* Runtime data (2nd block)
bb8c093b 6400 * NOTE: Copy into backup buffer will be done in iwl4965_up() */
b481de9c
ZY		 6401 src = &ucode->data[inst_size];
6402 len = priv->ucode_data.len;
90e759d1 6403 IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY		 6404 memcpy(priv->ucode_data.v_addr, src, len);
6405 memcpy(priv->ucode_data_backup.v_addr, src, len);
6406
6407 /* Initialization instructions (3rd block) */
6408 if (init_size) {
6409 src = &ucode->data[inst_size + data_size];
6410 len = priv->ucode_init.len;
90e759d1
TW		 6411 IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
6412 len);
b481de9c
ZY		 6413 memcpy(priv->ucode_init.v_addr, src, len);
6414 }
6415
6416 /* Initialization data (4th block) */
6417 if (init_data_size) {
6418 src = &ucode->data[inst_size + data_size + init_size];
6419 len = priv->ucode_init_data.len;
90e759d1
TW		 6420 IWL_DEBUG_INFO("Copying (but not loading) init data len %Zd\n",
6421 len);
b481de9c
ZY		 6422 memcpy(priv->ucode_init_data.v_addr, src, len);
6423 }
6424
6425 /* Bootstrap instructions (5th block) */
6426 src = &ucode->data[inst_size + data_size + init_size + init_data_size];
6427 len = priv->ucode_boot.len;
90e759d1 6428 IWL_DEBUG_INFO("Copying (but not loading) boot instr len %Zd\n", len);
b481de9c
ZY		 6429 memcpy(priv->ucode_boot.v_addr, src, len);
6430
6431 /* We have our copies now, allow OS release its copies */
6432 release_firmware(ucode_raw);
6433 return 0;
6434
6435 err_pci_alloc:
6436 IWL_ERROR("failed to allocate pci memory\n");
90e759d1 6437 ret = -ENOMEM;
bb8c093b 6438 iwl4965_dealloc_ucode_pci(priv);
b481de9c
ZY		 6439
6440 err_release:
6441 release_firmware(ucode_raw);
6442
6443 error:
90e759d1 6444 return ret;
b481de9c
ZY		 6445}
6446
6447
6448/**
bb8c093b 6449 * iwl4965_set_ucode_ptrs - Set uCode address location
b481de9c
ZY		 6450 *
6451 * Tell initialization uCode where to find runtime uCode.
6452 *
6453 * BSM registers initially contain pointers to initialization uCode.
6454 * We need to replace them to load runtime uCode inst and data,
6455 * and to save runtime data when powering down.
6456 */
bb8c093b 6457static int iwl4965_set_ucode_ptrs(struct iwl4965_priv *priv)
b481de9c
ZY		 6458{
6459 dma_addr_t pinst;
6460 dma_addr_t pdata;
6461 int rc = 0;
6462 unsigned long flags;
6463
6464 /* bits 35:4 for 4965 */
6465 pinst = priv->ucode_code.p_addr >> 4;
6466 pdata = priv->ucode_data_backup.p_addr >> 4;
6467
6468 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 6469 rc = iwl4965_grab_nic_access(priv);
b481de9c
ZY		 6470 if (rc) {
6471 spin_unlock_irqrestore(&priv->lock, flags);
6472 return rc;
6473 }
6474
6475 /* Tell bootstrap uCode where to find image to load */
bb8c093b
CH		 6476 iwl4965_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
6477 iwl4965_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
6478 iwl4965_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
b481de9c
ZY		 6479 priv->ucode_data.len);
6480
6481 /* Inst bytecount must be last to set up, bit 31 signals uCode
6482 * that all new ptr/size info is in place */
bb8c093b 6483 iwl4965_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
b481de9c
ZY		 6484 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
6485
bb8c093b 6486 iwl4965_release_nic_access(priv);
b481de9c
ZY		 6487
6488 spin_unlock_irqrestore(&priv->lock, flags);
6489
6490 IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
6491
6492 return rc;
6493}
6494
6495/**
bb8c093b 6496 * iwl4965_init_alive_start - Called after REPLY_ALIVE notification received
b481de9c
ZY		 6497 *
6498 * Called after REPLY_ALIVE notification received from "initialize" uCode.
6499 *
6500 * The 4965 "initialize" ALIVE reply contains calibration data for:
6501 * Voltage, temperature, and MIMO tx gain correction, now stored in priv
6502 * (3945 does not contain this data).
6503 *
6504 * Tell "initialize" uCode to go ahead and load the runtime uCode.
6505*/
bb8c093b 6506static void iwl4965_init_alive_start(struct iwl4965_priv *priv)
b481de9c
ZY		 6507{
6508 /* Check alive response for "valid" sign from uCode */
6509 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
6510 /* We had an error bringing up the hardware, so take it
6511 * all the way back down so we can try again */
6512 IWL_DEBUG_INFO("Initialize Alive failed.\n");
6513 goto restart;
6514 }
6515
6516 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
6517 * This is a paranoid check, because we would not have gotten the
6518 * "initialize" alive if code weren't properly loaded. */
bb8c093b 6519 if (iwl4965_verify_ucode(priv)) {
b481de9c
ZY		 6520 /* Runtime instruction load was bad;
6521 * take it all the way back down so we can try again */
6522 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
6523 goto restart;
6524 }
6525
6526 /* Calculate temperature */
6527 priv->temperature = iwl4965_get_temperature(priv);
6528
6529 /* Send pointers to protocol/runtime uCode image ... init code will
6530 * load and launch runtime uCode, which will send us another "Alive"
6531 * notification. */
6532 IWL_DEBUG_INFO("Initialization Alive received.\n");
bb8c093b 6533 if (iwl4965_set_ucode_ptrs(priv)) {
b481de9c
ZY		 6534 /* Runtime instruction load won't happen;
6535 * take it all the way back down so we can try again */
6536 IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
6537 goto restart;
6538 }
6539 return;
6540
6541 restart:
6542 queue_work(priv->workqueue, &priv->restart);
6543}
6544
6545
6546/**
bb8c093b 6547 * iwl4965_alive_start - called after REPLY_ALIVE notification received
b481de9c 6548 * from protocol/runtime uCode (initialization uCode's
bb8c093b 6549 * Alive gets handled by iwl4965_init_alive_start()).
b481de9c 6550 */
bb8c093b 6551static void iwl4965_alive_start(struct iwl4965_priv *priv)
b481de9c
ZY		 6552{
6553 int rc = 0;
6554
6555 IWL_DEBUG_INFO("Runtime Alive received.\n");
6556
6557 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
6558 /* We had an error bringing up the hardware, so take it
6559 * all the way back down so we can try again */
6560 IWL_DEBUG_INFO("Alive failed.\n");
6561 goto restart;
6562 }
6563
6564 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
6565 * This is a paranoid check, because we would not have gotten the
6566 * "runtime" alive if code weren't properly loaded. */
bb8c093b 6567 if (iwl4965_verify_ucode(priv)) {
b481de9c
ZY		 6568 /* Runtime instruction load was bad;
6569 * take it all the way back down so we can try again */
6570 IWL_DEBUG_INFO("Bad runtime uCode load.\n");
6571 goto restart;
6572 }
6573
bb8c093b 6574 iwl4965_clear_stations_table(priv);
b481de9c
ZY		 6575
6576 rc = iwl4965_alive_notify(priv);
6577 if (rc) {
6578 IWL_WARNING("Could not complete ALIVE transition [ntf]: %d\n",
6579 rc);
6580 goto restart;
6581 }
6582
9fbab516 6583 /* After the ALIVE response, we can send host commands to 4965 uCode */
b481de9c
ZY		 6584 set_bit(STATUS_ALIVE, &priv->status);
6585
6586 /* Clear out the uCode error bit if it is set */
6587 clear_bit(STATUS_FW_ERROR, &priv->status);
6588
bb8c093b 6589 if (iwl4965_is_rfkill(priv))
b481de9c
ZY		 6590 return;
6591
5a66926a 6592 ieee80211_start_queues(priv->hw);
b481de9c
ZY		 6593
6594 priv->active_rate = priv->rates_mask;
6595 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
6596
bb8c093b 6597 iwl4965_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
b481de9c 6598
bb8c093b
CH		 6599 if (iwl4965_is_associated(priv)) {
6600 struct iwl4965_rxon_cmd *active_rxon =
6601 (struct iwl4965_rxon_cmd *)(&priv->active_rxon);
b481de9c
ZY		 6602
6603 memcpy(&priv->staging_rxon, &priv->active_rxon,
6604 sizeof(priv->staging_rxon));
6605 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
6606 } else {
6607 /* Initialize our rx_config data */
bb8c093b 6608 iwl4965_connection_init_rx_config(priv);
b481de9c
ZY		 6609 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
6610 }
6611
9fbab516 6612 /* Configure Bluetooth device coexistence support */
bb8c093b 6613 iwl4965_send_bt_config(priv);
b481de9c
ZY		 6614
6615 /* Configure the adapter for unassociated operation */
bb8c093b 6616 iwl4965_commit_rxon(priv);
b481de9c
ZY		 6617
6618 /* At this point, the NIC is initialized and operational */
6619 priv->notif_missed_beacons = 0;
6620 set_bit(STATUS_READY, &priv->status);
6621
6622 iwl4965_rf_kill_ct_config(priv);
5a66926a 6623
b481de9c 6624 IWL_DEBUG_INFO("ALIVE processing complete.\n");
5a66926a 6625 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY		 6626
6627 if (priv->error_recovering)
bb8c093b 6628 iwl4965_error_recovery(priv);
b481de9c
ZY		 6629
6630 return;
6631
6632 restart:
6633 queue_work(priv->workqueue, &priv->restart);
6634}
6635
bb8c093b 6636static void iwl4965_cancel_deferred_work(struct iwl4965_priv *priv);
b481de9c 6637
bb8c093b 6638static void __iwl4965_down(struct iwl4965_priv *priv)
b481de9c
ZY		 6639{
6640 unsigned long flags;
6641 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
6642 struct ieee80211_conf *conf = NULL;
6643
6644 IWL_DEBUG_INFO(DRV_NAME " is going down\n");
6645
6646 conf = ieee80211_get_hw_conf(priv->hw);
6647
6648 if (!exit_pending)
6649 set_bit(STATUS_EXIT_PENDING, &priv->status);
6650
bb8c093b 6651 iwl4965_clear_stations_table(priv);
b481de9c
ZY		 6652
6653 /* Unblock any waiting calls */
6654 wake_up_interruptible_all(&priv->wait_command_queue);
6655
b481de9c
ZY		 6656 /* Wipe out the EXIT_PENDING status bit if we are not actually
6657 * exiting the module */
6658 if (!exit_pending)
6659 clear_bit(STATUS_EXIT_PENDING, &priv->status);
6660
6661 /* stop and reset the on-board processor */
bb8c093b 6662 iwl4965_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY		 6663
6664 /* tell the device to stop sending interrupts */
bb8c093b 6665 iwl4965_disable_interrupts(priv);
b481de9c
ZY		 6666
6667 if (priv->mac80211_registered)
6668 ieee80211_stop_queues(priv->hw);
6669
bb8c093b 6670 /* If we have not previously called iwl4965_init() then
b481de9c 6671 * clear all bits but the RF Kill and SUSPEND bits and return */
bb8c093b 6672 if (!iwl4965_is_init(priv)) {
b481de9c
ZY		 6673 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
6674 STATUS_RF_KILL_HW |
6675 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
6676 STATUS_RF_KILL_SW |
6677 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
6678 STATUS_IN_SUSPEND;
6679 goto exit;
6680 }
6681
6682 /* ...otherwise clear out all the status bits but the RF Kill and
6683 * SUSPEND bits and continue taking the NIC down. */
6684 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
6685 STATUS_RF_KILL_HW |
6686 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
6687 STATUS_RF_KILL_SW |
6688 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
6689 STATUS_IN_SUSPEND |
6690 test_bit(STATUS_FW_ERROR, &priv->status) <<
6691 STATUS_FW_ERROR;
6692
6693 spin_lock_irqsave(&priv->lock, flags);
9fbab516
BC		 6694 iwl4965_clear_bit(priv, CSR_GP_CNTRL,
6695 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY		 6696 spin_unlock_irqrestore(&priv->lock, flags);
6697
bb8c093b
CH		 6698 iwl4965_hw_txq_ctx_stop(priv);
6699 iwl4965_hw_rxq_stop(priv);
b481de9c
ZY		 6700
6701 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH		 6702 if (!iwl4965_grab_nic_access(priv)) {
6703 iwl4965_write_prph(priv, APMG_CLK_DIS_REG,
b481de9c 6704 APMG_CLK_VAL_DMA_CLK_RQT);
bb8c093b 6705 iwl4965_release_nic_access(priv);
b481de9c
ZY		 6706 }
6707 spin_unlock_irqrestore(&priv->lock, flags);
6708
6709 udelay(5);
6710
bb8c093b
CH		 6711 iwl4965_hw_nic_stop_master(priv);
6712 iwl4965_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
6713 iwl4965_hw_nic_reset(priv);
b481de9c
ZY		 6714
6715 exit:
bb8c093b 6716 memset(&priv->card_alive, 0, sizeof(struct iwl4965_alive_resp));
b481de9c
ZY		 6717
6718 if (priv->ibss_beacon)
6719 dev_kfree_skb(priv->ibss_beacon);
6720 priv->ibss_beacon = NULL;
6721
6722 /* clear out any free frames */
bb8c093b 6723 iwl4965_clear_free_frames(priv);
b481de9c
ZY		 6724}
6725
bb8c093b 6726static void iwl4965_down(struct iwl4965_priv *priv)
b481de9c
ZY		 6727{
6728 mutex_lock(&priv->mutex);
bb8c093b 6729 __iwl4965_down(priv);
b481de9c 6730 mutex_unlock(&priv->mutex);
b24d22b1 6731
bb8c093b 6732 iwl4965_cancel_deferred_work(priv);
b481de9c
ZY		 6733}
6734
6735#define MAX_HW_RESTARTS 5
6736
bb8c093b 6737static int __iwl4965_up(struct iwl4965_priv *priv)
b481de9c
ZY		 6738{
6739 int rc, i;
b481de9c
ZY		 6740
6741 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
6742 IWL_WARNING("Exit pending; will not bring the NIC up\n");
6743 return -EIO;
6744 }
6745
6746 if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
6747 IWL_WARNING("Radio disabled by SW RF kill (module "
6748 "parameter)\n");
e655b9f0
ZY		 6749 return -ENODEV;
6750 }
6751
6752 /* If platform's RF_KILL switch is NOT set to KILL */
6753 if (iwl4965_read32(priv, CSR_GP_CNTRL) &
6754 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
6755 clear_bit(STATUS_RF_KILL_HW, &priv->status);
6756 else {
6757 set_bit(STATUS_RF_KILL_HW, &priv->status);
6758 if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
6759 IWL_WARNING("Radio disabled by HW RF Kill switch\n");
6760 return -ENODEV;
6761 }
b481de9c
ZY		 6762 }
6763
a781cf94
RC		 6764 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
6765 IWL_ERROR("ucode not available for device bringup\n");
6766 return -EIO;
6767 }
6768
bb8c093b 6769 iwl4965_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 6770
bb8c093b 6771 rc = iwl4965_hw_nic_init(priv);
b481de9c
ZY		 6772 if (rc) {
6773 IWL_ERROR("Unable to int nic\n");
6774 return rc;
6775 }
6776
6777 /* make sure rfkill handshake bits are cleared */
bb8c093b
CH		 6778 iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
6779 iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 6780 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
6781
6782 /* clear (again), then enable host interrupts */
bb8c093b
CH		 6783 iwl4965_write32(priv, CSR_INT, 0xFFFFFFFF);
6784 iwl4965_enable_interrupts(priv);
b481de9c
ZY		 6785
6786 /* really make sure rfkill handshake bits are cleared */
bb8c093b
CH		 6787 iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
6788 iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 6789
6790 /* Copy original ucode data image from disk into backup cache.
6791 * This will be used to initialize the on-board processor's
6792 * data SRAM for a clean start when the runtime program first loads. */
6793 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 6794 priv->ucode_data.len);
b481de9c 6795
e655b9f0
ZY		 6796 /* We return success when we resume from suspend and rf_kill is on. */
6797 if (test_bit(STATUS_RF_KILL_HW, &priv->status))
b481de9c 6798 return 0;
b481de9c
ZY		 6799
6800 for (i = 0; i < MAX_HW_RESTARTS; i++) {
6801
bb8c093b 6802 iwl4965_clear_stations_table(priv);
b481de9c
ZY		 6803
6804 /* load bootstrap state machine,
6805 * load bootstrap program into processor's memory,
6806 * prepare to load the "initialize" uCode */
bb8c093b 6807 rc = iwl4965_load_bsm(priv);
b481de9c
ZY		 6808
6809 if (rc) {
6810 IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
6811 continue;
6812 }
6813
6814 /* start card; "initialize" will load runtime ucode */
bb8c093b 6815 iwl4965_nic_start(priv);
b481de9c 6816
b481de9c
ZY		 6817 IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
6818
6819 return 0;
6820 }
6821
6822 set_bit(STATUS_EXIT_PENDING, &priv->status);
bb8c093b 6823 __iwl4965_down(priv);
b481de9c
ZY		 6824
6825 /* tried to restart and config the device for as long as our
6826 * patience could withstand */
6827 IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
6828 return -EIO;
6829}
6830
6831
6832/*****************************************************************************
6833 *
6834 * Workqueue callbacks
6835 *
6836 *****************************************************************************/
6837
bb8c093b 6838static void iwl4965_bg_init_alive_start(struct work_struct *data)
b481de9c 6839{
bb8c093b
CH		 6840 struct iwl4965_priv *priv =
6841 container_of(data, struct iwl4965_priv, init_alive_start.work);
b481de9c
ZY		 6842
6843 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6844 return;
6845
6846 mutex_lock(&priv->mutex);
bb8c093b 6847 iwl4965_init_alive_start(priv);
b481de9c
ZY		 6848 mutex_unlock(&priv->mutex);
6849}
6850
bb8c093b 6851static void iwl4965_bg_alive_start(struct work_struct *data)
b481de9c 6852{
bb8c093b
CH		 6853 struct iwl4965_priv *priv =
6854 container_of(data, struct iwl4965_priv, alive_start.work);
b481de9c
ZY		 6855
6856 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6857 return;
6858
6859 mutex_lock(&priv->mutex);
bb8c093b 6860 iwl4965_alive_start(priv);
b481de9c
ZY		 6861 mutex_unlock(&priv->mutex);
6862}
6863
bb8c093b 6864static void iwl4965_bg_rf_kill(struct work_struct *work)
b481de9c 6865{
bb8c093b 6866 struct iwl4965_priv *priv = container_of(work, struct iwl4965_priv, rf_kill);
b481de9c
ZY		 6867
6868 wake_up_interruptible(&priv->wait_command_queue);
6869
6870 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6871 return;
6872
6873 mutex_lock(&priv->mutex);
6874
bb8c093b 6875 if (!iwl4965_is_rfkill(priv)) {
b481de9c
ZY		 6876 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
6877 "HW and/or SW RF Kill no longer active, restarting "
6878 "device\n");
6879 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
6880 queue_work(priv->workqueue, &priv->restart);
6881 } else {
6882
6883 if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
6884 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
6885 "disabled by SW switch\n");
6886 else
6887 IWL_WARNING("Radio Frequency Kill Switch is On:\n"
6888 "Kill switch must be turned off for "
6889 "wireless networking to work.\n");
6890 }
6891 mutex_unlock(&priv->mutex);
6892}
6893
6894#define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
6895
bb8c093b 6896static void iwl4965_bg_scan_check(struct work_struct *data)
b481de9c 6897{
bb8c093b
CH		 6898 struct iwl4965_priv *priv =
6899 container_of(data, struct iwl4965_priv, scan_check.work);
b481de9c
ZY		 6900
6901 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6902 return;
6903
6904 mutex_lock(&priv->mutex);
6905 if (test_bit(STATUS_SCANNING, &priv->status) ||
6906 test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6907 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
6908 "Scan completion watchdog resetting adapter (%dms)\n",
6909 jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
052c4b9f 6910
b481de9c 6911 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
bb8c093b 6912 iwl4965_send_scan_abort(priv);
b481de9c
ZY		 6913 }
6914 mutex_unlock(&priv->mutex);
6915}
6916
bb8c093b 6917static void iwl4965_bg_request_scan(struct work_struct *data)
b481de9c 6918{
bb8c093b
CH		 6919 struct iwl4965_priv *priv =
6920 container_of(data, struct iwl4965_priv, request_scan);
6921 struct iwl4965_host_cmd cmd = {
b481de9c 6922 .id = REPLY_SCAN_CMD,
bb8c093b 6923 .len = sizeof(struct iwl4965_scan_cmd),
b481de9c
ZY		 6924 .meta.flags = CMD_SIZE_HUGE,
6925 };
6926 int rc = 0;
bb8c093b 6927 struct iwl4965_scan_cmd *scan;
b481de9c
ZY		 6928 struct ieee80211_conf *conf = NULL;
6929 u8 direct_mask;
6930 int phymode;
6931
6932 conf = ieee80211_get_hw_conf(priv->hw);
6933
6934 mutex_lock(&priv->mutex);
6935
bb8c093b 6936 if (!iwl4965_is_ready(priv)) {
b481de9c
ZY		 6937 IWL_WARNING("request scan called when driver not ready.\n");
6938 goto done;
6939 }
6940
6941 /* Make sure the scan wasn't cancelled before this queued work
6942 * was given the chance to run... */
6943 if (!test_bit(STATUS_SCANNING, &priv->status))
6944 goto done;
6945
6946 /* This should never be called or scheduled if there is currently
6947 * a scan active in the hardware. */
6948 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
6949 IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
6950 "Ignoring second request.\n");
6951 rc = -EIO;
6952 goto done;
6953 }
6954
6955 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
6956 IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
6957 goto done;
6958 }
6959
6960 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6961 IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
6962 goto done;
6963 }
6964
bb8c093b 6965 if (iwl4965_is_rfkill(priv)) {
b481de9c
ZY		 6966 IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
6967 goto done;
6968 }
6969
6970 if (!test_bit(STATUS_READY, &priv->status)) {
6971 IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
6972 goto done;
6973 }
6974
6975 if (!priv->scan_bands) {
6976 IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
6977 goto done;
6978 }
6979
6980 if (!priv->scan) {
bb8c093b 6981 priv->scan = kmalloc(sizeof(struct iwl4965_scan_cmd) +
b481de9c
ZY		 6982 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
6983 if (!priv->scan) {
6984 rc = -ENOMEM;
6985 goto done;
6986 }
6987 }
6988 scan = priv->scan;
bb8c093b 6989 memset(scan, 0, sizeof(struct iwl4965_scan_cmd) + IWL_MAX_SCAN_SIZE);
b481de9c
ZY		 6990
6991 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
6992 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
6993
bb8c093b 6994 if (iwl4965_is_associated(priv)) {
b481de9c
ZY		 6995 u16 interval = 0;
6996 u32 extra;
6997 u32 suspend_time = 100;
6998 u32 scan_suspend_time = 100;
6999 unsigned long flags;
7000
7001 IWL_DEBUG_INFO("Scanning while associated...\n");
7002
7003 spin_lock_irqsave(&priv->lock, flags);
7004 interval = priv->beacon_int;
7005 spin_unlock_irqrestore(&priv->lock, flags);
7006
7007 scan->suspend_time = 0;
052c4b9f 7008 scan->max_out_time = cpu_to_le32(200 * 1024);
b481de9c
ZY		 7009 if (!interval)
7010 interval = suspend_time;
7011
7012 extra = (suspend_time / interval) << 22;
7013 scan_suspend_time = (extra |
7014 ((suspend_time % interval) * 1024));
7015 scan->suspend_time = cpu_to_le32(scan_suspend_time);
7016 IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
7017 scan_suspend_time, interval);
7018 }
7019
7020 /* We should add the ability for user to lock to PASSIVE ONLY */
7021 if (priv->one_direct_scan) {
7022 IWL_DEBUG_SCAN
7023 ("Kicking off one direct scan for '%s'\n",
bb8c093b 7024 iwl4965_escape_essid(priv->direct_ssid,
b481de9c
ZY		 7025 priv->direct_ssid_len));
7026 scan->direct_scan[0].id = WLAN_EID_SSID;
7027 scan->direct_scan[0].len = priv->direct_ssid_len;
7028 memcpy(scan->direct_scan[0].ssid,
7029 priv->direct_ssid, priv->direct_ssid_len);
7030 direct_mask = 1;
bb8c093b 7031 } else if (!iwl4965_is_associated(priv) && priv->essid_len) {
b481de9c
ZY		 7032 scan->direct_scan[0].id = WLAN_EID_SSID;
7033 scan->direct_scan[0].len = priv->essid_len;
7034 memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len);
7035 direct_mask = 1;
7036 } else
7037 direct_mask = 0;
7038
7039 /* We don't build a direct scan probe request; the uCode will do
7040 * that based on the direct_mask added to each channel entry */
7041 scan->tx_cmd.len = cpu_to_le16(
bb8c093b 7042 iwl4965_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
b481de9c
ZY		 7043 IWL_MAX_SCAN_SIZE - sizeof(scan), 0));
7044 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
7045 scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
7046 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
7047
7048 /* flags + rate selection */
7049
7050 scan->tx_cmd.tx_flags |= cpu_to_le32(0x200);
7051
7052 switch (priv->scan_bands) {
7053 case 2:
7054 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
7055 scan->tx_cmd.rate_n_flags =
bb8c093b 7056 iwl4965_hw_set_rate_n_flags(IWL_RATE_1M_PLCP,
b481de9c
ZY		 7057 RATE_MCS_ANT_B_MSK|RATE_MCS_CCK_MSK);
7058
7059 scan->good_CRC_th = 0;
7060 phymode = MODE_IEEE80211G;
7061 break;
7062
7063 case 1:
7064 scan->tx_cmd.rate_n_flags =
bb8c093b 7065 iwl4965_hw_set_rate_n_flags(IWL_RATE_6M_PLCP,
b481de9c
ZY		 7066 RATE_MCS_ANT_B_MSK);
7067 scan->good_CRC_th = IWL_GOOD_CRC_TH;
7068 phymode = MODE_IEEE80211A;
7069 break;
7070
7071 default:
7072 IWL_WARNING("Invalid scan band count\n");
7073 goto done;
7074 }
7075
7076 /* select Rx chains */
7077
7078 /* Force use of chains B and C (0x6) for scan Rx.
7079 * Avoid A (0x1) because of its off-channel reception on A-band.
7080 * MIMO is not used here, but value is required to make uCode happy. */
7081 scan->rx_chain = RXON_RX_CHAIN_DRIVER_FORCE_MSK |
7082 cpu_to_le16((0x7 << RXON_RX_CHAIN_VALID_POS) |
7083 (0x6 << RXON_RX_CHAIN_FORCE_SEL_POS) |
7084 (0x7 << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS));
7085
7086 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR)
7087 scan->filter_flags = RXON_FILTER_PROMISC_MSK;
7088
7089 if (direct_mask)
7090 IWL_DEBUG_SCAN
7091 ("Initiating direct scan for %s.\n",
bb8c093b 7092 iwl4965_escape_essid(priv->essid, priv->essid_len));
b481de9c
ZY		 7093 else
7094 IWL_DEBUG_SCAN("Initiating indirect scan.\n");
7095
7096 scan->channel_count =
bb8c093b 7097 iwl4965_get_channels_for_scan(
b481de9c
ZY		 7098 priv, phymode, 1, /* active */
7099 direct_mask,
7100 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
7101
7102 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
bb8c093b 7103 scan->channel_count * sizeof(struct iwl4965_scan_channel);
b481de9c
ZY		 7104 cmd.data = scan;
7105 scan->len = cpu_to_le16(cmd.len);
7106
7107 set_bit(STATUS_SCAN_HW, &priv->status);
bb8c093b 7108 rc = iwl4965_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 7109 if (rc)
7110 goto done;
7111
7112 queue_delayed_work(priv->workqueue, &priv->scan_check,
7113 IWL_SCAN_CHECK_WATCHDOG);
7114
7115 mutex_unlock(&priv->mutex);
7116 return;
7117
7118 done:
01ebd063 7119 /* inform mac80211 scan aborted */
b481de9c
ZY		 7120 queue_work(priv->workqueue, &priv->scan_completed);
7121 mutex_unlock(&priv->mutex);
7122}
7123
bb8c093b 7124static void iwl4965_bg_up(struct work_struct *data)
b481de9c 7125{
bb8c093b 7126 struct iwl4965_priv *priv = container_of(data, struct iwl4965_priv, up);
b481de9c
ZY		 7127
7128 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
7129 return;
7130
7131 mutex_lock(&priv->mutex);
bb8c093b 7132 __iwl4965_up(priv);
b481de9c
ZY		 7133 mutex_unlock(&priv->mutex);
7134}
7135
bb8c093b 7136static void iwl4965_bg_restart(struct work_struct *data)
b481de9c 7137{
bb8c093b 7138 struct iwl4965_priv *priv = container_of(data, struct iwl4965_priv, restart);
b481de9c
ZY		 7139
7140 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
7141 return;
7142
bb8c093b 7143 iwl4965_down(priv);
b481de9c
ZY		 7144 queue_work(priv->workqueue, &priv->up);
7145}
7146
bb8c093b 7147static void iwl4965_bg_rx_replenish(struct work_struct *data)
b481de9c 7148{
bb8c093b
CH		 7149 struct iwl4965_priv *priv =
7150 container_of(data, struct iwl4965_priv, rx_replenish);
b481de9c
ZY		 7151
7152 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
7153 return;
7154
7155 mutex_lock(&priv->mutex);
bb8c093b 7156 iwl4965_rx_replenish(priv);
b481de9c
ZY		 7157 mutex_unlock(&priv->mutex);
7158}
7159
7878a5a4
MA		 7160#define IWL_DELAY_NEXT_SCAN (HZ*2)
7161
bb8c093b 7162static void iwl4965_bg_post_associate(struct work_struct *data)
b481de9c 7163{
bb8c093b 7164 struct iwl4965_priv *priv = container_of(data, struct iwl4965_priv,
b481de9c
ZY		 7165 post_associate.work);
7166
7167 int rc = 0;
7168 struct ieee80211_conf *conf = NULL;
0795af57 7169 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 7170
7171 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
7172 IWL_ERROR("%s Should not be called in AP mode\n", __FUNCTION__);
7173 return;
7174 }
7175
0795af57
JP		 7176 IWL_DEBUG_ASSOC("Associated as %d to: %s\n",
7177 priv->assoc_id,
7178 print_mac(mac, priv->active_rxon.bssid_addr));
b481de9c
ZY		 7179
7180
7181 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
7182 return;
7183
7184 mutex_lock(&priv->mutex);
7185
32bfd35d 7186 if (!priv->vif || !priv->is_open) {
948c171c
MA		 7187 mutex_unlock(&priv->mutex);
7188 return;
7189 }
bb8c093b 7190 iwl4965_scan_cancel_timeout(priv, 200);
052c4b9f 7191
b481de9c
ZY		 7192 conf = ieee80211_get_hw_conf(priv->hw);
7193
7194 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 7195 iwl4965_commit_rxon(priv);
b481de9c 7196
bb8c093b
CH		 7197 memset(&priv->rxon_timing, 0, sizeof(struct iwl4965_rxon_time_cmd));
7198 iwl4965_setup_rxon_timing(priv);
7199 rc = iwl4965_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY		 7200 sizeof(priv->rxon_timing), &priv->rxon_timing);
7201 if (rc)
7202 IWL_WARNING("REPLY_RXON_TIMING failed - "
7203 "Attempting to continue.\n");
7204
7205 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
7206
c8b0e6e1 7207#ifdef CONFIG_IWL4965_HT
fd105e79
RR		 7208 if (priv->current_ht_config.is_ht)
7209 iwl4965_set_rxon_ht(priv, &priv->current_ht_config);
c8b0e6e1 7210#endif /* CONFIG_IWL4965_HT*/
b481de9c
ZY		 7211 iwl4965_set_rxon_chain(priv);
7212 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
7213
7214 IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
7215 priv->assoc_id, priv->beacon_int);
7216
7217 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
7218 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
7219 else
7220 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
7221
7222 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
7223 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
7224 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
7225 else
7226 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
7227
7228 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
7229 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
7230
7231 }
7232
bb8c093b 7233 iwl4965_commit_rxon(priv);
b481de9c
ZY		 7234
7235 switch (priv->iw_mode) {
7236 case IEEE80211_IF_TYPE_STA:
bb8c093b 7237 iwl4965_rate_scale_init(priv->hw, IWL_AP_ID);
b481de9c
ZY		 7238 break;
7239
7240 case IEEE80211_IF_TYPE_IBSS:
7241
7242 /* clear out the station table */
bb8c093b 7243 iwl4965_clear_stations_table(priv);
b481de9c 7244
bb8c093b
CH		 7245 iwl4965_rxon_add_station(priv, iwl4965_broadcast_addr, 0);
7246 iwl4965_rxon_add_station(priv, priv->bssid, 0);
7247 iwl4965_rate_scale_init(priv->hw, IWL_STA_ID);
7248 iwl4965_send_beacon_cmd(priv);
b481de9c
ZY		 7249
7250 break;
7251
7252 default:
7253 IWL_ERROR("%s Should not be called in %d mode\n",
7254 __FUNCTION__, priv->iw_mode);
7255 break;
7256 }
7257
bb8c093b 7258 iwl4965_sequence_reset(priv);
b481de9c 7259
c8b0e6e1 7260#ifdef CONFIG_IWL4965_SENSITIVITY
b481de9c
ZY		 7261 /* Enable Rx differential gain and sensitivity calibrations */
7262 iwl4965_chain_noise_reset(priv);
7263 priv->start_calib = 1;
c8b0e6e1 7264#endif /* CONFIG_IWL4965_SENSITIVITY */
b481de9c
ZY		 7265
7266 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
7267 priv->assoc_station_added = 1;
7268
c8b0e6e1 7269#ifdef CONFIG_IWL4965_QOS
bb8c093b 7270 iwl4965_activate_qos(priv, 0);
c8b0e6e1 7271#endif /* CONFIG_IWL4965_QOS */
7878a5a4
MA		 7272 /* we have just associated, don't start scan too early */
7273 priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
b481de9c
ZY		 7274 mutex_unlock(&priv->mutex);
7275}
7276
bb8c093b 7277static void iwl4965_bg_abort_scan(struct work_struct *work)
b481de9c 7278{
bb8c093b 7279 struct iwl4965_priv *priv = container_of(work, struct iwl4965_priv, abort_scan);
b481de9c 7280
bb8c093b 7281 if (!iwl4965_is_ready(priv))
b481de9c
ZY		 7282 return;
7283
7284 mutex_lock(&priv->mutex);
7285
7286 set_bit(STATUS_SCAN_ABORTING, &priv->status);
bb8c093b 7287 iwl4965_send_scan_abort(priv);
b481de9c
ZY		 7288
7289 mutex_unlock(&priv->mutex);
7290}
7291
76bb77e0
ZY		 7292static int iwl4965_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf);
7293
bb8c093b 7294static void iwl4965_bg_scan_completed(struct work_struct *work)
b481de9c 7295{
bb8c093b
CH		 7296 struct iwl4965_priv *priv =
7297 container_of(work, struct iwl4965_priv, scan_completed);
b481de9c
ZY		 7298
7299 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
7300
7301 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
7302 return;
7303
a0646470
ZY		 7304 if (test_bit(STATUS_CONF_PENDING, &priv->status))
7305 iwl4965_mac_config(priv->hw, ieee80211_get_hw_conf(priv->hw));
76bb77e0 7306
b481de9c
ZY		 7307 ieee80211_scan_completed(priv->hw);
7308
7309 /* Since setting the TXPOWER may have been deferred while
7310 * performing the scan, fire one off */
7311 mutex_lock(&priv->mutex);
bb8c093b 7312 iwl4965_hw_reg_send_txpower(priv);
b481de9c
ZY		 7313 mutex_unlock(&priv->mutex);
7314}
7315
7316/*****************************************************************************
7317 *
7318 * mac80211 entry point functions
7319 *
7320 *****************************************************************************/
7321
5a66926a
ZY		 7322#define UCODE_READY_TIMEOUT (2 * HZ)
7323
bb8c093b 7324static int iwl4965_mac_start(struct ieee80211_hw *hw)
b481de9c 7325{
bb8c093b 7326 struct iwl4965_priv *priv = hw->priv;
5a66926a 7327 int ret;
b481de9c
ZY		 7328
7329 IWL_DEBUG_MAC80211("enter\n");
7330
5a66926a
ZY		 7331 if (pci_enable_device(priv->pci_dev)) {
7332 IWL_ERROR("Fail to pci_enable_device\n");
7333 return -ENODEV;
7334 }
7335 pci_restore_state(priv->pci_dev);
7336 pci_enable_msi(priv->pci_dev);
7337
7338 ret = request_irq(priv->pci_dev->irq, iwl4965_isr, IRQF_SHARED,
7339 DRV_NAME, priv);
7340 if (ret) {
7341 IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq);
7342 goto out_disable_msi;
7343 }
7344
b481de9c
ZY		 7345 /* we should be verifying the device is ready to be opened */
7346 mutex_lock(&priv->mutex);
7347
5a66926a
ZY		 7348 memset(&priv->staging_rxon, 0, sizeof(struct iwl4965_rxon_cmd));
7349 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
7350 * ucode filename and max sizes are card-specific. */
b481de9c 7351
5a66926a
ZY		 7352 if (!priv->ucode_code.len) {
7353 ret = iwl4965_read_ucode(priv);
7354 if (ret) {
7355 IWL_ERROR("Could not read microcode: %d\n", ret);
7356 mutex_unlock(&priv->mutex);
7357 goto out_release_irq;
7358 }
7359 }
b481de9c 7360
e655b9f0 7361 ret = __iwl4965_up(priv);
5a66926a 7362
b481de9c 7363 mutex_unlock(&priv->mutex);
5a66926a 7364
e655b9f0
ZY		 7365 if (ret)
7366 goto out_release_irq;
7367
7368 IWL_DEBUG_INFO("Start UP work done.\n");
7369
7370 if (test_bit(STATUS_IN_SUSPEND, &priv->status))
7371 return 0;
7372
5a66926a
ZY		 7373 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
7374 * mac80211 will not be run successfully. */
7375 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
7376 test_bit(STATUS_READY, &priv->status),
7377 UCODE_READY_TIMEOUT);
7378 if (!ret) {
7379 if (!test_bit(STATUS_READY, &priv->status)) {
7380 IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n",
7381 jiffies_to_msecs(UCODE_READY_TIMEOUT));
7382 ret = -ETIMEDOUT;
7383 goto out_release_irq;
7384 }
7385 }
7386
e655b9f0 7387 priv->is_open = 1;
b481de9c
ZY		 7388 IWL_DEBUG_MAC80211("leave\n");
7389 return 0;
5a66926a
ZY		 7390
7391out_release_irq:
7392 free_irq(priv->pci_dev->irq, priv);
7393out_disable_msi:
7394 pci_disable_msi(priv->pci_dev);
e655b9f0
ZY		 7395 pci_disable_device(priv->pci_dev);
7396 priv->is_open = 0;
7397 IWL_DEBUG_MAC80211("leave - failed\n");
5a66926a 7398 return ret;
b481de9c
ZY		 7399}
7400
bb8c093b 7401static void iwl4965_mac_stop(struct ieee80211_hw *hw)
b481de9c 7402{
bb8c093b 7403 struct iwl4965_priv *priv = hw->priv;
b481de9c
ZY		 7404
7405 IWL_DEBUG_MAC80211("enter\n");
948c171c 7406
e655b9f0
ZY		 7407 if (!priv->is_open) {
7408 IWL_DEBUG_MAC80211("leave - skip\n");
7409 return;
7410 }
7411
b481de9c 7412 priv->is_open = 0;
5a66926a
ZY		 7413
7414 if (iwl4965_is_ready_rf(priv)) {
e655b9f0
ZY		 7415 /* stop mac, cancel any scan request and clear
7416 * RXON_FILTER_ASSOC_MSK BIT
7417 */
5a66926a
ZY		 7418 mutex_lock(&priv->mutex);
7419 iwl4965_scan_cancel_timeout(priv, 100);
7420 cancel_delayed_work(&priv->post_associate);
fde3571f 7421 mutex_unlock(&priv->mutex);
fde3571f
MA		 7422 }
7423
5a66926a
ZY		 7424 iwl4965_down(priv);
7425
7426 flush_workqueue(priv->workqueue);
7427 free_irq(priv->pci_dev->irq, priv);
7428 pci_disable_msi(priv->pci_dev);
7429 pci_save_state(priv->pci_dev);
7430 pci_disable_device(priv->pci_dev);
948c171c 7431
b481de9c 7432 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 7433}
7434
bb8c093b 7435static int iwl4965_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
b481de9c
ZY		 7436 struct ieee80211_tx_control *ctl)
7437{
bb8c093b 7438 struct iwl4965_priv *priv = hw->priv;
b481de9c
ZY		 7439
7440 IWL_DEBUG_MAC80211("enter\n");
7441
7442 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
7443 IWL_DEBUG_MAC80211("leave - monitor\n");
7444 return -1;
7445 }
7446
7447 IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
7448 ctl->tx_rate);
7449
bb8c093b 7450 if (iwl4965_tx_skb(priv, skb, ctl))
b481de9c
ZY		 7451 dev_kfree_skb_any(skb);
7452
7453 IWL_DEBUG_MAC80211("leave\n");
7454 return 0;
7455}
7456
bb8c093b 7457static int iwl4965_mac_add_interface(struct ieee80211_hw *hw,
b481de9c
ZY		 7458 struct ieee80211_if_init_conf *conf)
7459{
bb8c093b 7460 struct iwl4965_priv *priv = hw->priv;
b481de9c 7461 unsigned long flags;
0795af57 7462 DECLARE_MAC_BUF(mac);
b481de9c 7463
32bfd35d 7464 IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
b481de9c 7465
32bfd35d
JB		 7466 if (priv->vif) {
7467 IWL_DEBUG_MAC80211("leave - vif != NULL\n");
75849d28 7468 return -EOPNOTSUPP;
b481de9c
ZY		 7469 }
7470
7471 spin_lock_irqsave(&priv->lock, flags);
32bfd35d 7472 priv->vif = conf->vif;
b481de9c
ZY		 7473
7474 spin_unlock_irqrestore(&priv->lock, flags);
7475
7476 mutex_lock(&priv->mutex);
864792e3
TW		 7477
7478 if (conf->mac_addr) {
7479 IWL_DEBUG_MAC80211("Set %s\n", print_mac(mac, conf->mac_addr));
7480 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
7481 }
b481de9c 7482
5a66926a
ZY		 7483 if (iwl4965_is_ready(priv))
7484 iwl4965_set_mode(priv, conf->type);
7485
b481de9c
ZY		 7486 mutex_unlock(&priv->mutex);
7487
5a66926a 7488 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 7489 return 0;
7490}
7491
7492/**
bb8c093b 7493 * iwl4965_mac_config - mac80211 config callback
b481de9c
ZY		 7494 *
7495 * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
7496 * be set inappropriately and the driver currently sets the hardware up to
7497 * use it whenever needed.
7498 */
bb8c093b 7499static int iwl4965_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
b481de9c 7500{
bb8c093b
CH		 7501 struct iwl4965_priv *priv = hw->priv;
7502 const struct iwl4965_channel_info *ch_info;
b481de9c 7503 unsigned long flags;
76bb77e0 7504 int ret = 0;
b481de9c
ZY		 7505
7506 mutex_lock(&priv->mutex);
7507 IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel);
7508
12342c47
ZY		 7509 priv->add_radiotap = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
7510
bb8c093b 7511 if (!iwl4965_is_ready(priv)) {
b481de9c 7512 IWL_DEBUG_MAC80211("leave - not ready\n");
76bb77e0
ZY		 7513 ret = -EIO;
7514 goto out;
b481de9c
ZY		 7515 }
7516
bb8c093b 7517 if (unlikely(!iwl4965_param_disable_hw_scan &&
b481de9c 7518 test_bit(STATUS_SCANNING, &priv->status))) {
a0646470
ZY		 7519 IWL_DEBUG_MAC80211("leave - scanning\n");
7520 set_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 7521 mutex_unlock(&priv->mutex);
a0646470 7522 return 0;
b481de9c
ZY		 7523 }
7524
7525 spin_lock_irqsave(&priv->lock, flags);
7526
bb8c093b 7527 ch_info = iwl4965_get_channel_info(priv, conf->phymode, conf->channel);
b481de9c
ZY		 7528 if (!is_channel_valid(ch_info)) {
7529 IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this SKU.\n",
7530 conf->channel, conf->phymode);
7531 IWL_DEBUG_MAC80211("leave - invalid channel\n");
7532 spin_unlock_irqrestore(&priv->lock, flags);
76bb77e0
ZY		 7533 ret = -EINVAL;
7534 goto out;
b481de9c
ZY		 7535 }
7536
c8b0e6e1 7537#ifdef CONFIG_IWL4965_HT
b481de9c
ZY		 7538 /* if we are switching fron ht to 2.4 clear flags
7539 * from any ht related info since 2.4 does not
7540 * support ht */
7541 if ((le16_to_cpu(priv->staging_rxon.channel) != conf->channel)
7542#ifdef IEEE80211_CONF_CHANNEL_SWITCH
7543 && !(conf->flags & IEEE80211_CONF_CHANNEL_SWITCH)
7544#endif
7545 )
7546 priv->staging_rxon.flags = 0;
c8b0e6e1 7547#endif /* CONFIG_IWL4965_HT */
b481de9c 7548
bb8c093b 7549 iwl4965_set_rxon_channel(priv, conf->phymode, conf->channel);
b481de9c 7550
bb8c093b 7551 iwl4965_set_flags_for_phymode(priv, conf->phymode);
b481de9c
ZY		 7552
7553 /* The list of supported rates and rate mask can be different
7554 * for each phymode; since the phymode may have changed, reset
7555 * the rate mask to what mac80211 lists */
bb8c093b 7556 iwl4965_set_rate(priv);
b481de9c
ZY		 7557
7558 spin_unlock_irqrestore(&priv->lock, flags);
7559
7560#ifdef IEEE80211_CONF_CHANNEL_SWITCH
7561 if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
bb8c093b 7562 iwl4965_hw_channel_switch(priv, conf->channel);
76bb77e0 7563 goto out;
b481de9c
ZY		 7564 }
7565#endif
7566
bb8c093b 7567 iwl4965_radio_kill_sw(priv, !conf->radio_enabled);
b481de9c
ZY		 7568
7569 if (!conf->radio_enabled) {
7570 IWL_DEBUG_MAC80211("leave - radio disabled\n");
76bb77e0 7571 goto out;
b481de9c
ZY		 7572 }
7573
bb8c093b 7574 if (iwl4965_is_rfkill(priv)) {
b481de9c 7575 IWL_DEBUG_MAC80211("leave - RF kill\n");
76bb77e0
ZY		 7576 ret = -EIO;
7577 goto out;
b481de9c
ZY		 7578 }
7579
bb8c093b 7580 iwl4965_set_rate(priv);
b481de9c
ZY		 7581
7582 if (memcmp(&priv->active_rxon,
7583 &priv->staging_rxon, sizeof(priv->staging_rxon)))
bb8c093b 7584 iwl4965_commit_rxon(priv);
b481de9c
ZY		 7585 else
7586 IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
7587
7588 IWL_DEBUG_MAC80211("leave\n");
7589
a0646470
ZY		 7590out:
7591 clear_bit(STATUS_CONF_PENDING, &priv->status);
5a66926a 7592 mutex_unlock(&priv->mutex);
76bb77e0 7593 return ret;
b481de9c
ZY		 7594}
7595
bb8c093b 7596static void iwl4965_config_ap(struct iwl4965_priv *priv)
b481de9c
ZY		 7597{
7598 int rc = 0;
7599
d986bcd1 7600 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY		 7601 return;
7602
7603 /* The following should be done only at AP bring up */
7604 if ((priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) == 0) {
7605
7606 /* RXON - unassoc (to set timing command) */
7607 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 7608 iwl4965_commit_rxon(priv);
b481de9c
ZY		 7609
7610 /* RXON Timing */
bb8c093b
CH		 7611 memset(&priv->rxon_timing, 0, sizeof(struct iwl4965_rxon_time_cmd));
7612 iwl4965_setup_rxon_timing(priv);
7613 rc = iwl4965_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY		 7614 sizeof(priv->rxon_timing), &priv->rxon_timing);
7615 if (rc)
7616 IWL_WARNING("REPLY_RXON_TIMING failed - "
7617 "Attempting to continue.\n");
7618
7619 iwl4965_set_rxon_chain(priv);
7620
7621 /* FIXME: what should be the assoc_id for AP? */
7622 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
7623 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
7624 priv->staging_rxon.flags |=
7625 RXON_FLG_SHORT_PREAMBLE_MSK;
7626 else
7627 priv->staging_rxon.flags &=
7628 ~RXON_FLG_SHORT_PREAMBLE_MSK;
7629
7630 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
7631 if (priv->assoc_capability &
7632 WLAN_CAPABILITY_SHORT_SLOT_TIME)
7633 priv->staging_rxon.flags |=
7634 RXON_FLG_SHORT_SLOT_MSK;
7635 else
7636 priv->staging_rxon.flags &=
7637 ~RXON_FLG_SHORT_SLOT_MSK;
7638
7639 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
7640 priv->staging_rxon.flags &=
7641 ~RXON_FLG_SHORT_SLOT_MSK;
7642 }
7643 /* restore RXON assoc */
7644 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
bb8c093b 7645 iwl4965_commit_rxon(priv);
c8b0e6e1 7646#ifdef CONFIG_IWL4965_QOS
bb8c093b 7647 iwl4965_activate_qos(priv, 1);
b481de9c 7648#endif
bb8c093b 7649 iwl4965_rxon_add_station(priv, iwl4965_broadcast_addr, 0);
e1493deb 7650 }
bb8c093b 7651 iwl4965_send_beacon_cmd(priv);
b481de9c
ZY		 7652
7653 /* FIXME - we need to add code here to detect a totally new
7654 * configuration, reset the AP, unassoc, rxon timing, assoc,
7655 * clear sta table, add BCAST sta... */
7656}
7657
32bfd35d
JB		 7658static int iwl4965_mac_config_interface(struct ieee80211_hw *hw,
7659 struct ieee80211_vif *vif,
b481de9c
ZY		 7660 struct ieee80211_if_conf *conf)
7661{
bb8c093b 7662 struct iwl4965_priv *priv = hw->priv;
0795af57 7663 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 7664 unsigned long flags;
7665 int rc;
7666
7667 if (conf == NULL)
7668 return -EIO;
7669
7670 if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
7671 (!conf->beacon || !conf->ssid_len)) {
7672 IWL_DEBUG_MAC80211
7673 ("Leaving in AP mode because HostAPD is not ready.\n");
7674 return 0;
7675 }
7676
5a66926a
ZY		 7677 if (!iwl4965_is_alive(priv))
7678 return -EAGAIN;
7679
b481de9c
ZY		 7680 mutex_lock(&priv->mutex);
7681
b481de9c 7682 if (conf->bssid)
0795af57
JP		 7683 IWL_DEBUG_MAC80211("bssid: %s\n",
7684 print_mac(mac, conf->bssid));
b481de9c 7685
4150c572
JB		 7686/*
7687 * very dubious code was here; the probe filtering flag is never set:
7688 *
b481de9c
ZY		 7689 if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
7690 !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
4150c572
JB		 7691 */
7692 if (unlikely(test_bit(STATUS_SCANNING, &priv->status))) {
b481de9c
ZY		 7693 IWL_DEBUG_MAC80211("leave - scanning\n");
7694 mutex_unlock(&priv->mutex);
7695 return 0;
7696 }
7697
32bfd35d
JB		 7698 if (priv->vif != vif) {
7699 IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
b481de9c
ZY		 7700 mutex_unlock(&priv->mutex);
7701 return 0;
7702 }
7703
7704 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
7705 if (!conf->bssid) {
7706 conf->bssid = priv->mac_addr;
7707 memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
0795af57
JP		 7708 IWL_DEBUG_MAC80211("bssid was set to: %s\n",
7709 print_mac(mac, conf->bssid));
b481de9c
ZY		 7710 }
7711 if (priv->ibss_beacon)
7712 dev_kfree_skb(priv->ibss_beacon);
7713
7714 priv->ibss_beacon = conf->beacon;
7715 }
7716
fde3571f
MA		 7717 if (iwl4965_is_rfkill(priv))
7718 goto done;
7719
b481de9c
ZY		 7720 if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
7721 !is_multicast_ether_addr(conf->bssid)) {
7722 /* If there is currently a HW scan going on in the background
7723 * then we need to cancel it else the RXON below will fail. */
bb8c093b 7724 if (iwl4965_scan_cancel_timeout(priv, 100)) {
b481de9c
ZY		 7725 IWL_WARNING("Aborted scan still in progress "
7726 "after 100ms\n");
7727 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
7728 mutex_unlock(&priv->mutex);
7729 return -EAGAIN;
7730 }
7731 memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
7732
7733 /* TODO: Audit driver for usage of these members and see
7734 * if mac80211 deprecates them (priv->bssid looks like it
7735 * shouldn't be there, but I haven't scanned the IBSS code
7736 * to verify) - jpk */
7737 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
7738
7739 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
bb8c093b 7740 iwl4965_config_ap(priv);
b481de9c 7741 else {
bb8c093b 7742 rc = iwl4965_commit_rxon(priv);
b481de9c 7743 if ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && rc)
bb8c093b 7744 iwl4965_rxon_add_station(
b481de9c
ZY		 7745 priv, priv->active_rxon.bssid_addr, 1);
7746 }
7747
7748 } else {
bb8c093b 7749 iwl4965_scan_cancel_timeout(priv, 100);
b481de9c 7750 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 7751 iwl4965_commit_rxon(priv);
b481de9c
ZY		 7752 }
7753
fde3571f 7754 done:
b481de9c
ZY		 7755 spin_lock_irqsave(&priv->lock, flags);
7756 if (!conf->ssid_len)
7757 memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
7758 else
7759 memcpy(priv->essid, conf->ssid, conf->ssid_len);
7760
7761 priv->essid_len = conf->ssid_len;
7762 spin_unlock_irqrestore(&priv->lock, flags);
7763
7764 IWL_DEBUG_MAC80211("leave\n");
7765 mutex_unlock(&priv->mutex);
7766
7767 return 0;
7768}
7769
bb8c093b 7770static void iwl4965_configure_filter(struct ieee80211_hw *hw,
4150c572
JB		 7771 unsigned int changed_flags,
7772 unsigned int *total_flags,
7773 int mc_count, struct dev_addr_list *mc_list)
7774{
7775 /*
7776 * XXX: dummy
bb8c093b 7777 * see also iwl4965_connection_init_rx_config
4150c572
JB		 7778 */
7779 *total_flags = 0;
7780}
7781
bb8c093b 7782static void iwl4965_mac_remove_interface(struct ieee80211_hw *hw,
b481de9c
ZY		 7783 struct ieee80211_if_init_conf *conf)
7784{
bb8c093b 7785 struct iwl4965_priv *priv = hw->priv;
b481de9c
ZY		 7786
7787 IWL_DEBUG_MAC80211("enter\n");
7788
7789 mutex_lock(&priv->mutex);
948c171c 7790
fde3571f
MA		 7791 if (iwl4965_is_ready_rf(priv)) {
7792 iwl4965_scan_cancel_timeout(priv, 100);
7793 cancel_delayed_work(&priv->post_associate);
7794 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
7795 iwl4965_commit_rxon(priv);
7796 }
32bfd35d
JB		 7797 if (priv->vif == conf->vif) {
7798 priv->vif = NULL;
b481de9c
ZY		 7799 memset(priv->bssid, 0, ETH_ALEN);
7800 memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
7801 priv->essid_len = 0;
7802 }
7803 mutex_unlock(&priv->mutex);
7804
7805 IWL_DEBUG_MAC80211("leave\n");
7806
7807}
471b3efd
JB		 7808
7809static void iwl4965_bss_info_changed(struct ieee80211_hw *hw,
7810 struct ieee80211_vif *vif,
7811 struct ieee80211_bss_conf *bss_conf,
7812 u32 changes)
220173b0 7813{
bb8c093b 7814 struct iwl4965_priv *priv = hw->priv;
220173b0 7815
471b3efd
JB		 7816 if (changes & BSS_CHANGED_ERP_PREAMBLE) {
7817 if (bss_conf->use_short_preamble)
220173b0
TW		 7818 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
7819 else
7820 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
7821 }
7822
471b3efd
JB		 7823 if (changes & BSS_CHANGED_ERP_CTS_PROT) {
7824 if (bss_conf->use_cts_prot && (priv->phymode != MODE_IEEE80211A))
220173b0
TW		 7825 priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
7826 else
7827 priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
7828 }
7829
471b3efd
JB		 7830 if (changes & BSS_CHANGED_ASSOC) {
7831 /*
7832 * TODO:
7833 * do stuff instead of sniffing assoc resp
7834 */
7835 }
7836
bb8c093b
CH		 7837 if (iwl4965_is_associated(priv))
7838 iwl4965_send_rxon_assoc(priv);
220173b0 7839}
b481de9c 7840
bb8c093b 7841static int iwl4965_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
b481de9c
ZY		 7842{
7843 int rc = 0;
7844 unsigned long flags;
bb8c093b 7845 struct iwl4965_priv *priv = hw->priv;
b481de9c
ZY		 7846
7847 IWL_DEBUG_MAC80211("enter\n");
7848
052c4b9f 7849 mutex_lock(&priv->mutex);
b481de9c
ZY		 7850 spin_lock_irqsave(&priv->lock, flags);
7851
bb8c093b 7852 if (!iwl4965_is_ready_rf(priv)) {
b481de9c
ZY		 7853 rc = -EIO;
7854 IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
7855 goto out_unlock;
7856 }
7857
7858 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { /* APs don't scan */
7859 rc = -EIO;
7860 IWL_ERROR("ERROR: APs don't scan\n");
7861 goto out_unlock;
7862 }
7863
7878a5a4
MA		 7864 /* we don't schedule scan within next_scan_jiffies period */
7865 if (priv->next_scan_jiffies &&
7866 time_after(priv->next_scan_jiffies, jiffies)) {
7867 rc = -EAGAIN;
7868 goto out_unlock;
7869 }
b481de9c 7870 /* if we just finished scan ask for delay */
7878a5a4
MA		 7871 if (priv->last_scan_jiffies && time_after(priv->last_scan_jiffies +
7872 IWL_DELAY_NEXT_SCAN, jiffies)) {
b481de9c
ZY		 7873 rc = -EAGAIN;
7874 goto out_unlock;
7875 }
7876 if (len) {
7878a5a4 7877 IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
bb8c093b 7878 iwl4965_escape_essid(ssid, len), (int)len);
b481de9c
ZY		 7879
7880 priv->one_direct_scan = 1;
7881 priv->direct_ssid_len = (u8)
7882 min((u8) len, (u8) IW_ESSID_MAX_SIZE);
7883 memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
948c171c
MA		 7884 } else
7885 priv->one_direct_scan = 0;
b481de9c 7886
bb8c093b 7887 rc = iwl4965_scan_initiate(priv);
b481de9c
ZY		 7888
7889 IWL_DEBUG_MAC80211("leave\n");
7890
7891out_unlock:
7892 spin_unlock_irqrestore(&priv->lock, flags);
052c4b9f 7893 mutex_unlock(&priv->mutex);
b481de9c
ZY		 7894
7895 return rc;
7896}
7897
bb8c093b 7898static int iwl4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
b481de9c
ZY		 7899 const u8 *local_addr, const u8 *addr,
7900 struct ieee80211_key_conf *key)
7901{
bb8c093b 7902 struct iwl4965_priv *priv = hw->priv;
0795af57 7903 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 7904 int rc = 0;
7905 u8 sta_id;
7906
7907 IWL_DEBUG_MAC80211("enter\n");
7908
bb8c093b 7909 if (!iwl4965_param_hwcrypto) {
b481de9c
ZY		 7910 IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
7911 return -EOPNOTSUPP;
7912 }
7913
7914 if (is_zero_ether_addr(addr))
7915 /* only support pairwise keys */
7916 return -EOPNOTSUPP;
7917
bb8c093b 7918 sta_id = iwl4965_hw_find_station(priv, addr);
b481de9c 7919 if (sta_id == IWL_INVALID_STATION) {
0795af57
JP		 7920 IWL_DEBUG_MAC80211("leave - %s not in station map.\n",
7921 print_mac(mac, addr));
b481de9c
ZY		 7922 return -EINVAL;
7923 }
7924
7925 mutex_lock(&priv->mutex);
7926
bb8c093b 7927 iwl4965_scan_cancel_timeout(priv, 100);
052c4b9f 7928
b481de9c
ZY		 7929 switch (cmd) {
7930 case SET_KEY:
bb8c093b 7931 rc = iwl4965_update_sta_key_info(priv, key, sta_id);
b481de9c 7932 if (!rc) {
bb8c093b
CH		 7933 iwl4965_set_rxon_hwcrypto(priv, 1);
7934 iwl4965_commit_rxon(priv);
b481de9c
ZY		 7935 key->hw_key_idx = sta_id;
7936 IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
7937 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
7938 }
7939 break;
7940 case DISABLE_KEY:
bb8c093b 7941 rc = iwl4965_clear_sta_key_info(priv, sta_id);
b481de9c 7942 if (!rc) {
bb8c093b
CH		 7943 iwl4965_set_rxon_hwcrypto(priv, 0);
7944 iwl4965_commit_rxon(priv);
b481de9c
ZY		 7945 IWL_DEBUG_MAC80211("disable hwcrypto key\n");
7946 }
7947 break;
7948 default:
7949 rc = -EINVAL;
7950 }
7951
7952 IWL_DEBUG_MAC80211("leave\n");
7953 mutex_unlock(&priv->mutex);
7954
7955 return rc;
7956}
7957
bb8c093b 7958static int iwl4965_mac_conf_tx(struct ieee80211_hw *hw, int queue,
b481de9c
ZY		 7959 const struct ieee80211_tx_queue_params *params)
7960{
bb8c093b 7961 struct iwl4965_priv *priv = hw->priv;
c8b0e6e1 7962#ifdef CONFIG_IWL4965_QOS
b481de9c
ZY		 7963 unsigned long flags;
7964 int q;
0054b34d 7965#endif /* CONFIG_IWL4965_QOS */
b481de9c
ZY		 7966
7967 IWL_DEBUG_MAC80211("enter\n");
7968
bb8c093b 7969 if (!iwl4965_is_ready_rf(priv)) {
b481de9c
ZY		 7970 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7971 return -EIO;
7972 }
7973
7974 if (queue >= AC_NUM) {
7975 IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
7976 return 0;
7977 }
7978
c8b0e6e1 7979#ifdef CONFIG_IWL4965_QOS
b481de9c
ZY		 7980 if (!priv->qos_data.qos_enable) {
7981 priv->qos_data.qos_active = 0;
7982 IWL_DEBUG_MAC80211("leave - qos not enabled\n");
7983 return 0;
7984 }
7985 q = AC_NUM - 1 - queue;
7986
7987 spin_lock_irqsave(&priv->lock, flags);
7988
7989 priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
7990 priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
7991 priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
7992 priv->qos_data.def_qos_parm.ac[q].edca_txop =
7993 cpu_to_le16((params->burst_time * 100));
7994
7995 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
7996 priv->qos_data.qos_active = 1;
7997
7998 spin_unlock_irqrestore(&priv->lock, flags);
7999
8000 mutex_lock(&priv->mutex);
8001 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
bb8c093b
CH		 8002 iwl4965_activate_qos(priv, 1);
8003 else if (priv->assoc_id && iwl4965_is_associated(priv))
8004 iwl4965_activate_qos(priv, 0);
b481de9c
ZY		 8005
8006 mutex_unlock(&priv->mutex);
8007
c8b0e6e1 8008#endif /*CONFIG_IWL4965_QOS */
b481de9c
ZY		 8009
8010 IWL_DEBUG_MAC80211("leave\n");
8011 return 0;
8012}
8013
bb8c093b 8014static int iwl4965_mac_get_tx_stats(struct ieee80211_hw *hw,
b481de9c
ZY		 8015 struct ieee80211_tx_queue_stats *stats)
8016{
bb8c093b 8017 struct iwl4965_priv *priv = hw->priv;
b481de9c 8018 int i, avail;
bb8c093b
CH		 8019 struct iwl4965_tx_queue *txq;
8020 struct iwl4965_queue *q;
b481de9c
ZY		 8021 unsigned long flags;
8022
8023 IWL_DEBUG_MAC80211("enter\n");
8024
bb8c093b 8025 if (!iwl4965_is_ready_rf(priv)) {
b481de9c
ZY		 8026 IWL_DEBUG_MAC80211("leave - RF not ready\n");
8027 return -EIO;
8028 }
8029
8030 spin_lock_irqsave(&priv->lock, flags);
8031
8032 for (i = 0; i < AC_NUM; i++) {
8033 txq = &priv->txq[i];
8034 q = &txq->q;
bb8c093b 8035 avail = iwl4965_queue_space(q);
b481de9c
ZY		 8036
8037 stats->data[i].len = q->n_window - avail;
8038 stats->data[i].limit = q->n_window - q->high_mark;
8039 stats->data[i].count = q->n_window;
8040
8041 }
8042 spin_unlock_irqrestore(&priv->lock, flags);
8043
8044 IWL_DEBUG_MAC80211("leave\n");
8045
8046 return 0;
8047}
8048
bb8c093b 8049static int iwl4965_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY		 8050 struct ieee80211_low_level_stats *stats)
8051{
8052 IWL_DEBUG_MAC80211("enter\n");
8053 IWL_DEBUG_MAC80211("leave\n");
8054
8055 return 0;
8056}
8057
bb8c093b 8058static u64 iwl4965_mac_get_tsf(struct ieee80211_hw *hw)
b481de9c
ZY		 8059{
8060 IWL_DEBUG_MAC80211("enter\n");
8061 IWL_DEBUG_MAC80211("leave\n");
8062
8063 return 0;
8064}
8065
bb8c093b 8066static void iwl4965_mac_reset_tsf(struct ieee80211_hw *hw)
b481de9c 8067{
bb8c093b 8068 struct iwl4965_priv *priv = hw->priv;
b481de9c
ZY		 8069 unsigned long flags;
8070
8071 mutex_lock(&priv->mutex);
8072 IWL_DEBUG_MAC80211("enter\n");
8073
8074 priv->lq_mngr.lq_ready = 0;
c8b0e6e1 8075#ifdef CONFIG_IWL4965_HT
b481de9c 8076 spin_lock_irqsave(&priv->lock, flags);
fd105e79 8077 memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_info));
b481de9c 8078 spin_unlock_irqrestore(&priv->lock, flags);
c8b0e6e1 8079#ifdef CONFIG_IWL4965_HT_AGG
b481de9c
ZY		 8080/* if (priv->lq_mngr.agg_ctrl.granted_ba)
8081 iwl4965_turn_off_agg(priv, TID_ALL_SPECIFIED);*/
8082
bb8c093b 8083 memset(&(priv->lq_mngr.agg_ctrl), 0, sizeof(struct iwl4965_agg_control));
b481de9c
ZY		 8084 priv->lq_mngr.agg_ctrl.tid_traffic_load_threshold = 10;
8085 priv->lq_mngr.agg_ctrl.ba_timeout = 5000;
8086 priv->lq_mngr.agg_ctrl.auto_agg = 1;
8087
8088 if (priv->lq_mngr.agg_ctrl.auto_agg)
8089 priv->lq_mngr.agg_ctrl.requested_ba = TID_ALL_ENABLED;
c8b0e6e1
CH		 8090#endif /*CONFIG_IWL4965_HT_AGG */
8091#endif /* CONFIG_IWL4965_HT */
b481de9c 8092
c8b0e6e1 8093#ifdef CONFIG_IWL4965_QOS
bb8c093b 8094 iwl4965_reset_qos(priv);
b481de9c
ZY		 8095#endif
8096
8097 cancel_delayed_work(&priv->post_associate);
8098
8099 spin_lock_irqsave(&priv->lock, flags);
8100 priv->assoc_id = 0;
8101 priv->assoc_capability = 0;
8102 priv->call_post_assoc_from_beacon = 0;
8103 priv->assoc_station_added = 0;
8104
8105 /* new association get rid of ibss beacon skb */
8106 if (priv->ibss_beacon)
8107 dev_kfree_skb(priv->ibss_beacon);
8108
8109 priv->ibss_beacon = NULL;
8110
8111 priv->beacon_int = priv->hw->conf.beacon_int;
8112 priv->timestamp1 = 0;
8113 priv->timestamp0 = 0;
8114 if ((priv->iw_mode == IEEE80211_IF_TYPE_STA))
8115 priv->beacon_int = 0;
8116
8117 spin_unlock_irqrestore(&priv->lock, flags);
8118
fde3571f
MA		 8119 if (!iwl4965_is_ready_rf(priv)) {
8120 IWL_DEBUG_MAC80211("leave - not ready\n");
8121 mutex_unlock(&priv->mutex);
8122 return;
8123 }
8124
052c4b9f 8125 /* we are restarting association process
8126 * clear RXON_FILTER_ASSOC_MSK bit
8127 */
8128 if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
bb8c093b 8129 iwl4965_scan_cancel_timeout(priv, 100);
052c4b9f 8130 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 8131 iwl4965_commit_rxon(priv);
052c4b9f 8132 }
8133
b481de9c
ZY		 8134 /* Per mac80211.h: This is only used in IBSS mode... */
8135 if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
052c4b9f 8136
b481de9c
ZY		 8137 IWL_DEBUG_MAC80211("leave - not in IBSS\n");
8138 mutex_unlock(&priv->mutex);
8139 return;
8140 }
8141
b481de9c
ZY		 8142 priv->only_active_channel = 0;
8143
bb8c093b 8144 iwl4965_set_rate(priv);
b481de9c
ZY		 8145
8146 mutex_unlock(&priv->mutex);
8147
8148 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 8149}
8150
bb8c093b 8151static int iwl4965_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
b481de9c
ZY		 8152 struct ieee80211_tx_control *control)
8153{
bb8c093b 8154 struct iwl4965_priv *priv = hw->priv;
b481de9c
ZY		 8155 unsigned long flags;
8156
8157 mutex_lock(&priv->mutex);
8158 IWL_DEBUG_MAC80211("enter\n");
8159
bb8c093b 8160 if (!iwl4965_is_ready_rf(priv)) {
b481de9c
ZY		 8161 IWL_DEBUG_MAC80211("leave - RF not ready\n");
8162 mutex_unlock(&priv->mutex);
8163 return -EIO;
8164 }
8165
8166 if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
8167 IWL_DEBUG_MAC80211("leave - not IBSS\n");
8168 mutex_unlock(&priv->mutex);
8169 return -EIO;
8170 }
8171
8172 spin_lock_irqsave(&priv->lock, flags);
8173
8174 if (priv->ibss_beacon)
8175 dev_kfree_skb(priv->ibss_beacon);
8176
8177 priv->ibss_beacon = skb;
8178
8179 priv->assoc_id = 0;
8180
8181 IWL_DEBUG_MAC80211("leave\n");
8182 spin_unlock_irqrestore(&priv->lock, flags);
8183
c8b0e6e1 8184#ifdef CONFIG_IWL4965_QOS
bb8c093b 8185 iwl4965_reset_qos(priv);
b481de9c
ZY		 8186#endif
8187
8188 queue_work(priv->workqueue, &priv->post_associate.work);
8189
8190 mutex_unlock(&priv->mutex);
8191
8192 return 0;
8193}
8194
c8b0e6e1 8195#ifdef CONFIG_IWL4965_HT
b481de9c 8196
fd105e79
RR		 8197static void iwl4965_ht_info_fill(struct ieee80211_conf *conf,
8198 struct iwl4965_priv *priv)
b481de9c 8199{
fd105e79
RR		 8200 struct iwl_ht_info *iwl_conf = &priv->current_ht_config;
8201 struct ieee80211_ht_info *ht_conf = &conf->ht_conf;
8202 struct ieee80211_ht_bss_info *ht_bss_conf = &conf->ht_bss_conf;
b481de9c
ZY		 8203
8204 IWL_DEBUG_MAC80211("enter: \n");
8205
fd105e79
RR		 8206 if (!(conf->flags & IEEE80211_CONF_SUPPORT_HT_MODE)) {
8207 iwl_conf->is_ht = 0;
8208 return;
b481de9c
ZY		 8209 }
8210
fd105e79
RR		 8211 iwl_conf->is_ht = 1;
8212 priv->ps_mode = (u8)((ht_conf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2);
8213
8214 if (ht_conf->cap & IEEE80211_HT_CAP_SGI_20)
8215 iwl_conf->sgf |= 0x1;
8216 if (ht_conf->cap & IEEE80211_HT_CAP_SGI_40)
8217 iwl_conf->sgf |= 0x2;
8218
8219 iwl_conf->is_green_field = !!(ht_conf->cap & IEEE80211_HT_CAP_GRN_FLD);
8220 iwl_conf->max_amsdu_size =
8221 !!(ht_conf->cap & IEEE80211_HT_CAP_MAX_AMSDU);
8222 iwl_conf->supported_chan_width =
8223 !!(ht_conf->cap & IEEE80211_HT_CAP_SUP_WIDTH);
8224 iwl_conf->tx_mimo_ps_mode =
8225 (u8)((ht_conf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2);
8226 memcpy(iwl_conf->supp_mcs_set, ht_conf->supp_mcs_set, 16);
8227
8228 iwl_conf->control_channel = ht_bss_conf->primary_channel;
8229 iwl_conf->extension_chan_offset =
8230 ht_bss_conf->bss_cap & IEEE80211_HT_IE_CHA_SEC_OFFSET;
8231 iwl_conf->tx_chan_width =
8232 !!(ht_bss_conf->bss_cap & IEEE80211_HT_IE_CHA_WIDTH);
8233 iwl_conf->ht_protection =
8234 ht_bss_conf->bss_op_mode & IEEE80211_HT_IE_HT_PROTECTION;
8235 iwl_conf->non_GF_STA_present =
8236 !!(ht_bss_conf->bss_op_mode & IEEE80211_HT_IE_NON_GF_STA_PRSNT);
8237
8238 IWL_DEBUG_MAC80211("control channel %d\n",
8239 iwl_conf->control_channel);
b481de9c 8240 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 8241}
8242
bb8c093b 8243static int iwl4965_mac_conf_ht(struct ieee80211_hw *hw,
fd105e79 8244 struct ieee80211_conf *conf)
b481de9c 8245{
bb8c093b 8246 struct iwl4965_priv *priv = hw->priv;
b481de9c
ZY		 8247
8248 IWL_DEBUG_MAC80211("enter: \n");
8249
fd105e79 8250 iwl4965_ht_info_fill(conf, priv);
b481de9c
ZY		 8251 iwl4965_set_rxon_chain(priv);
8252
8253 if (priv && priv->assoc_id &&
8254 (priv->iw_mode == IEEE80211_IF_TYPE_STA)) {
8255 unsigned long flags;
8256
8257 spin_lock_irqsave(&priv->lock, flags);
8258 if (priv->beacon_int)
8259 queue_work(priv->workqueue, &priv->post_associate.work);
8260 else
8261 priv->call_post_assoc_from_beacon = 1;
8262 spin_unlock_irqrestore(&priv->lock, flags);
8263 }
8264
fd105e79
RR		 8265 IWL_DEBUG_MAC80211("leave:\n");
8266 return 0;
b481de9c
ZY		 8267}
8268
bb8c093b 8269static void iwl4965_set_ht_capab(struct ieee80211_hw *hw,
8fb88032
RR		 8270 struct ieee80211_ht_cap *ht_cap,
8271 u8 use_current_config)
b481de9c 8272{
8fb88032
RR		 8273 struct ieee80211_conf *conf = &hw->conf;
8274 struct ieee80211_hw_mode *mode = conf->mode;
b481de9c 8275
8fb88032
RR		 8276 if (use_current_config) {
8277 ht_cap->cap_info = cpu_to_le16(conf->ht_conf.cap);
8278 memcpy(ht_cap->supp_mcs_set,
8279 conf->ht_conf.supp_mcs_set, 16);
8280 } else {
8281 ht_cap->cap_info = cpu_to_le16(mode->ht_info.cap);
8282 memcpy(ht_cap->supp_mcs_set,
8283 mode->ht_info.supp_mcs_set, 16);
8284 }
8285 ht_cap->ampdu_params_info =
8286 (mode->ht_info.ampdu_factor & IEEE80211_HT_CAP_AMPDU_FACTOR) |
8287 ((mode->ht_info.ampdu_density << 2) &
8288 IEEE80211_HT_CAP_AMPDU_DENSITY);
b481de9c
ZY		 8289}
8290
c8b0e6e1 8291#endif /*CONFIG_IWL4965_HT*/
b481de9c
ZY		 8292
8293/*****************************************************************************
8294 *
8295 * sysfs attributes
8296 *
8297 *****************************************************************************/
8298
c8b0e6e1 8299#ifdef CONFIG_IWL4965_DEBUG
b481de9c
ZY		 8300
8301/*
8302 * The following adds a new attribute to the sysfs representation
8303 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
8304 * used for controlling the debug level.
8305 *
8306 * See the level definitions in iwl for details.
8307 */
8308
8309static ssize_t show_debug_level(struct device_driver *d, char *buf)
8310{
bb8c093b 8311 return sprintf(buf, "0x%08X\n", iwl4965_debug_level);
b481de9c
ZY		 8312}
8313static ssize_t store_debug_level(struct device_driver *d,
8314 const char *buf, size_t count)
8315{
8316 char *p = (char *)buf;
8317 u32 val;
8318
8319 val = simple_strtoul(p, &p, 0);
8320 if (p == buf)
8321 printk(KERN_INFO DRV_NAME
8322 ": %s is not in hex or decimal form.\n", buf);
8323 else
bb8c093b 8324 iwl4965_debug_level = val;
b481de9c
ZY		 8325
8326 return strnlen(buf, count);
8327}
8328
8329static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
8330 show_debug_level, store_debug_level);
8331
c8b0e6e1 8332#endif /* CONFIG_IWL4965_DEBUG */
b481de9c
ZY		 8333
8334static ssize_t show_rf_kill(struct device *d,
8335 struct device_attribute *attr, char *buf)
8336{
8337 /*
8338 * 0 - RF kill not enabled
8339 * 1 - SW based RF kill active (sysfs)
8340 * 2 - HW based RF kill active
8341 * 3 - Both HW and SW based RF kill active
8342 */
bb8c093b 8343 struct iwl4965_priv *priv = (struct iwl4965_priv *)d->driver_data;
b481de9c
ZY		 8344 int val = (test_bit(STATUS_RF_KILL_SW, &priv->status) ? 0x1 : 0x0) |
8345 (test_bit(STATUS_RF_KILL_HW, &priv->status) ? 0x2 : 0x0);
8346
8347 return sprintf(buf, "%i\n", val);
8348}
8349
8350static ssize_t store_rf_kill(struct device *d,
8351 struct device_attribute *attr,
8352 const char *buf, size_t count)
8353{
bb8c093b 8354 struct iwl4965_priv *priv = (struct iwl4965_priv *)d->driver_data;
b481de9c
ZY		 8355
8356 mutex_lock(&priv->mutex);
bb8c093b 8357 iwl4965_radio_kill_sw(priv, buf[0] == '1');
b481de9c
ZY		 8358 mutex_unlock(&priv->mutex);
8359
8360 return count;
8361}
8362
8363static DEVICE_ATTR(rf_kill, S_IWUSR | S_IRUGO, show_rf_kill, store_rf_kill);
8364
8365static ssize_t show_temperature(struct device *d,
8366 struct device_attribute *attr, char *buf)
8367{
bb8c093b 8368 struct iwl4965_priv *priv = (struct iwl4965_priv *)d->driver_data;
b481de9c 8369
bb8c093b 8370 if (!iwl4965_is_alive(priv))
b481de9c
ZY		 8371 return -EAGAIN;
8372
bb8c093b 8373 return sprintf(buf, "%d\n", iwl4965_hw_get_temperature(priv));
b481de9c
ZY		 8374}
8375
8376static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
8377
8378static ssize_t show_rs_window(struct device *d,
8379 struct device_attribute *attr,
8380 char *buf)
8381{
bb8c093b
CH		 8382 struct iwl4965_priv *priv = d->driver_data;
8383 return iwl4965_fill_rs_info(priv->hw, buf, IWL_AP_ID);
b481de9c
ZY		 8384}
8385static DEVICE_ATTR(rs_window, S_IRUGO, show_rs_window, NULL);
8386
8387static ssize_t show_tx_power(struct device *d,
8388 struct device_attribute *attr, char *buf)
8389{
bb8c093b 8390 struct iwl4965_priv *priv = (struct iwl4965_priv *)d->driver_data;
b481de9c
ZY		 8391 return sprintf(buf, "%d\n", priv->user_txpower_limit);
8392}
8393
8394static ssize_t store_tx_power(struct device *d,
8395 struct device_attribute *attr,
8396 const char *buf, size_t count)
8397{
bb8c093b 8398 struct iwl4965_priv *priv = (struct iwl4965_priv *)d->driver_data;
b481de9c
ZY		 8399 char *p = (char *)buf;
8400 u32 val;
8401
8402 val = simple_strtoul(p, &p, 10);
8403 if (p == buf)
8404 printk(KERN_INFO DRV_NAME
8405 ": %s is not in decimal form.\n", buf);
8406 else
bb8c093b 8407 iwl4965_hw_reg_set_txpower(priv, val);
b481de9c
ZY		 8408
8409 return count;
8410}
8411
8412static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
8413
8414static ssize_t show_flags(struct device *d,
8415 struct device_attribute *attr, char *buf)
8416{
bb8c093b 8417 struct iwl4965_priv *priv = (struct iwl4965_priv *)d->driver_data;
b481de9c
ZY		 8418
8419 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
8420}
8421
8422static ssize_t store_flags(struct device *d,
8423 struct device_attribute *attr,
8424 const char *buf, size_t count)
8425{
bb8c093b 8426 struct iwl4965_priv *priv = (struct iwl4965_priv *)d->driver_data;
b481de9c
ZY		 8427 u32 flags = simple_strtoul(buf, NULL, 0);
8428
8429 mutex_lock(&priv->mutex);
8430 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
8431 /* Cancel any currently running scans... */
bb8c093b 8432 if (iwl4965_scan_cancel_timeout(priv, 100))
b481de9c
ZY		 8433 IWL_WARNING("Could not cancel scan.\n");
8434 else {
8435 IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
8436 flags);
8437 priv->staging_rxon.flags = cpu_to_le32(flags);
bb8c093b 8438 iwl4965_commit_rxon(priv);
b481de9c
ZY		 8439 }
8440 }
8441 mutex_unlock(&priv->mutex);
8442
8443 return count;
8444}
8445
8446static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
8447
8448static ssize_t show_filter_flags(struct device *d,
8449 struct device_attribute *attr, char *buf)
8450{
bb8c093b 8451 struct iwl4965_priv *priv = (struct iwl4965_priv *)d->driver_data;
b481de9c
ZY		 8452
8453 return sprintf(buf, "0x%04X\n",
8454 le32_to_cpu(priv->active_rxon.filter_flags));
8455}
8456
8457static ssize_t store_filter_flags(struct device *d,
8458 struct device_attribute *attr,
8459 const char *buf, size_t count)
8460{
bb8c093b 8461 struct iwl4965_priv *priv = (struct iwl4965_priv *)d->driver_data;
b481de9c
ZY		 8462 u32 filter_flags = simple_strtoul(buf, NULL, 0);
8463
8464 mutex_lock(&priv->mutex);
8465 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
8466 /* Cancel any currently running scans... */
bb8c093b 8467 if (iwl4965_scan_cancel_timeout(priv, 100))
b481de9c
ZY		 8468 IWL_WARNING("Could not cancel scan.\n");
8469 else {
8470 IWL_DEBUG_INFO("Committing rxon.filter_flags = "
8471 "0x%04X\n", filter_flags);
8472 priv->staging_rxon.filter_flags =
8473 cpu_to_le32(filter_flags);
bb8c093b 8474 iwl4965_commit_rxon(priv);
b481de9c
ZY		 8475 }
8476 }
8477 mutex_unlock(&priv->mutex);
8478
8479 return count;
8480}
8481
8482static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
8483 store_filter_flags);
8484
8485static ssize_t show_tune(struct device *d,
8486 struct device_attribute *attr, char *buf)
8487{
bb8c093b 8488 struct iwl4965_priv *priv = (struct iwl4965_priv *)d->driver_data;
b481de9c
ZY		 8489
8490 return sprintf(buf, "0x%04X\n",
8491 (priv->phymode << 8) |
8492 le16_to_cpu(priv->active_rxon.channel));
8493}
8494
bb8c093b 8495static void iwl4965_set_flags_for_phymode(struct iwl4965_priv *priv, u8 phymode);
b481de9c
ZY		 8496
8497static ssize_t store_tune(struct device *d,
8498 struct device_attribute *attr,
8499 const char *buf, size_t count)
8500{
bb8c093b 8501 struct iwl4965_priv *priv = (struct iwl4965_priv *)d->driver_data;
b481de9c
ZY		 8502 char *p = (char *)buf;
8503 u16 tune = simple_strtoul(p, &p, 0);
8504 u8 phymode = (tune >> 8) & 0xff;
8505 u16 channel = tune & 0xff;
8506
8507 IWL_DEBUG_INFO("Tune request to:%d channel:%d\n", phymode, channel);
8508
8509 mutex_lock(&priv->mutex);
8510 if ((le16_to_cpu(priv->staging_rxon.channel) != channel) ||
8511 (priv->phymode != phymode)) {
bb8c093b 8512 const struct iwl4965_channel_info *ch_info;
b481de9c 8513
bb8c093b 8514 ch_info = iwl4965_get_channel_info(priv, phymode, channel);
b481de9c
ZY		 8515 if (!ch_info) {
8516 IWL_WARNING("Requested invalid phymode/channel "
8517 "combination: %d %d\n", phymode, channel);
8518 mutex_unlock(&priv->mutex);
8519 return -EINVAL;
8520 }
8521
8522 /* Cancel any currently running scans... */
bb8c093b 8523 if (iwl4965_scan_cancel_timeout(priv, 100))
b481de9c
ZY		 8524 IWL_WARNING("Could not cancel scan.\n");
8525 else {
8526 IWL_DEBUG_INFO("Committing phymode and "
8527 "rxon.channel = %d %d\n",
8528 phymode, channel);
8529
bb8c093b
CH		 8530 iwl4965_set_rxon_channel(priv, phymode, channel);
8531 iwl4965_set_flags_for_phymode(priv, phymode);
b481de9c 8532
bb8c093b
CH		 8533 iwl4965_set_rate(priv);
8534 iwl4965_commit_rxon(priv);
b481de9c
ZY		 8535 }
8536 }
8537 mutex_unlock(&priv->mutex);
8538
8539 return count;
8540}
8541
8542static DEVICE_ATTR(tune, S_IWUSR | S_IRUGO, show_tune, store_tune);
8543
c8b0e6e1 8544#ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT
b481de9c
ZY		 8545
8546static ssize_t show_measurement(struct device *d,
8547 struct device_attribute *attr, char *buf)
8548{
bb8c093b
CH		 8549 struct iwl4965_priv *priv = dev_get_drvdata(d);
8550 struct iwl4965_spectrum_notification measure_report;
b481de9c
ZY		 8551 u32 size = sizeof(measure_report), len = 0, ofs = 0;
8552 u8 *data = (u8 *) & measure_report;
8553 unsigned long flags;
8554
8555 spin_lock_irqsave(&priv->lock, flags);
8556 if (!(priv->measurement_status & MEASUREMENT_READY)) {
8557 spin_unlock_irqrestore(&priv->lock, flags);
8558 return 0;
8559 }
8560 memcpy(&measure_report, &priv->measure_report, size);
8561 priv->measurement_status = 0;
8562 spin_unlock_irqrestore(&priv->lock, flags);
8563
8564 while (size && (PAGE_SIZE - len)) {
8565 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
8566 PAGE_SIZE - len, 1);
8567 len = strlen(buf);
8568 if (PAGE_SIZE - len)
8569 buf[len++] = '\n';
8570
8571 ofs += 16;
8572 size -= min(size, 16U);
8573 }
8574
8575 return len;
8576}
8577
8578static ssize_t store_measurement(struct device *d,
8579 struct device_attribute *attr,
8580 const char *buf, size_t count)
8581{
bb8c093b 8582 struct iwl4965_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 8583 struct ieee80211_measurement_params params = {
8584 .channel = le16_to_cpu(priv->active_rxon.channel),
8585 .start_time = cpu_to_le64(priv->last_tsf),
8586 .duration = cpu_to_le16(1),
8587 };
8588 u8 type = IWL_MEASURE_BASIC;
8589 u8 buffer[32];
8590 u8 channel;
8591
8592 if (count) {
8593 char *p = buffer;
8594 strncpy(buffer, buf, min(sizeof(buffer), count));
8595 channel = simple_strtoul(p, NULL, 0);
8596 if (channel)
8597 params.channel = channel;
8598
8599 p = buffer;
8600 while (*p && *p != ' ')
8601 p++;
8602 if (*p)
8603 type = simple_strtoul(p + 1, NULL, 0);
8604 }
8605
8606 IWL_DEBUG_INFO("Invoking measurement of type %d on "
8607 "channel %d (for '%s')\n", type, params.channel, buf);
bb8c093b 8608 iwl4965_get_measurement(priv, &params, type);
b481de9c
ZY		 8609
8610 return count;
8611}
8612
8613static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
8614 show_measurement, store_measurement);
c8b0e6e1 8615#endif /* CONFIG_IWL4965_SPECTRUM_MEASUREMENT */
b481de9c
ZY		 8616
8617static ssize_t store_retry_rate(struct device *d,
8618 struct device_attribute *attr,
8619 const char *buf, size_t count)
8620{
bb8c093b 8621 struct iwl4965_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 8622
8623 priv->retry_rate = simple_strtoul(buf, NULL, 0);
8624 if (priv->retry_rate <= 0)
8625 priv->retry_rate = 1;
8626
8627 return count;
8628}
8629
8630static ssize_t show_retry_rate(struct device *d,
8631 struct device_attribute *attr, char *buf)
8632{
bb8c093b 8633 struct iwl4965_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 8634 return sprintf(buf, "%d", priv->retry_rate);
8635}
8636
8637static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
8638 store_retry_rate);
8639
8640static ssize_t store_power_level(struct device *d,
8641 struct device_attribute *attr,
8642 const char *buf, size_t count)
8643{
bb8c093b 8644 struct iwl4965_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 8645 int rc;
8646 int mode;
8647
8648 mode = simple_strtoul(buf, NULL, 0);
8649 mutex_lock(&priv->mutex);
8650
bb8c093b 8651 if (!iwl4965_is_ready(priv)) {
b481de9c
ZY		 8652 rc = -EAGAIN;
8653 goto out;
8654 }
8655
8656 if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
8657 mode = IWL_POWER_AC;
8658 else
8659 mode |= IWL_POWER_ENABLED;
8660
8661 if (mode != priv->power_mode) {
bb8c093b 8662 rc = iwl4965_send_power_mode(priv, IWL_POWER_LEVEL(mode));
b481de9c
ZY		 8663 if (rc) {
8664 IWL_DEBUG_MAC80211("failed setting power mode.\n");
8665 goto out;
8666 }
8667 priv->power_mode = mode;
8668 }
8669
8670 rc = count;
8671
8672 out:
8673 mutex_unlock(&priv->mutex);
8674 return rc;
8675}
8676
8677#define MAX_WX_STRING 80
8678
8679/* Values are in microsecond */
8680static const s32 timeout_duration[] = {
8681 350000,
8682 250000,
8683 75000,
8684 37000,
8685 25000,
8686};
8687static const s32 period_duration[] = {
8688 400000,
8689 700000,
8690 1000000,
8691 1000000,
8692 1000000
8693};
8694
8695static ssize_t show_power_level(struct device *d,
8696 struct device_attribute *attr, char *buf)
8697{
bb8c093b 8698 struct iwl4965_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 8699 int level = IWL_POWER_LEVEL(priv->power_mode);
8700 char *p = buf;
8701
8702 p += sprintf(p, "%d ", level);
8703 switch (level) {
8704 case IWL_POWER_MODE_CAM:
8705 case IWL_POWER_AC:
8706 p += sprintf(p, "(AC)");
8707 break;
8708 case IWL_POWER_BATTERY:
8709 p += sprintf(p, "(BATTERY)");
8710 break;
8711 default:
8712 p += sprintf(p,
8713 "(Timeout %dms, Period %dms)",
8714 timeout_duration[level - 1] / 1000,
8715 period_duration[level - 1] / 1000);
8716 }
8717
8718 if (!(priv->power_mode & IWL_POWER_ENABLED))
8719 p += sprintf(p, " OFF\n");
8720 else
8721 p += sprintf(p, " \n");
8722
8723 return (p - buf + 1);
8724
8725}
8726
8727static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
8728 store_power_level);
8729
8730static ssize_t show_channels(struct device *d,
8731 struct device_attribute *attr, char *buf)
8732{
bb8c093b 8733 struct iwl4965_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 8734 int len = 0, i;
8735 struct ieee80211_channel *channels = NULL;
8736 const struct ieee80211_hw_mode *hw_mode = NULL;
8737 int count = 0;
8738
bb8c093b 8739 if (!iwl4965_is_ready(priv))
b481de9c
ZY		 8740 return -EAGAIN;
8741
bb8c093b 8742 hw_mode = iwl4965_get_hw_mode(priv, MODE_IEEE80211G);
b481de9c 8743 if (!hw_mode)
bb8c093b 8744 hw_mode = iwl4965_get_hw_mode(priv, MODE_IEEE80211B);
b481de9c
ZY		 8745 if (hw_mode) {
8746 channels = hw_mode->channels;
8747 count = hw_mode->num_channels;
8748 }
8749
8750 len +=
8751 sprintf(&buf[len],
8752 "Displaying %d channels in 2.4GHz band "
8753 "(802.11bg):\n", count);
8754
8755 for (i = 0; i < count; i++)
8756 len += sprintf(&buf[len], "%d: %ddBm: BSS%s%s, %s.\n",
8757 channels[i].chan,
8758 channels[i].power_level,
8759 channels[i].
8760 flag & IEEE80211_CHAN_W_RADAR_DETECT ?
8761 " (IEEE 802.11h required)" : "",
8762 (!(channels[i].flag & IEEE80211_CHAN_W_IBSS)
8763 || (channels[i].
8764 flag &
8765 IEEE80211_CHAN_W_RADAR_DETECT)) ? "" :
8766 ", IBSS",
8767 channels[i].
8768 flag & IEEE80211_CHAN_W_ACTIVE_SCAN ?
8769 "active/passive" : "passive only");
8770
bb8c093b 8771 hw_mode = iwl4965_get_hw_mode(priv, MODE_IEEE80211A);
b481de9c
ZY		 8772 if (hw_mode) {
8773 channels = hw_mode->channels;
8774 count = hw_mode->num_channels;
8775 } else {
8776 channels = NULL;
8777 count = 0;
8778 }
8779
8780 len += sprintf(&buf[len], "Displaying %d channels in 5.2GHz band "
8781 "(802.11a):\n", count);
8782
8783 for (i = 0; i < count; i++)
8784 len += sprintf(&buf[len], "%d: %ddBm: BSS%s%s, %s.\n",
8785 channels[i].chan,
8786 channels[i].power_level,
8787 channels[i].
8788 flag & IEEE80211_CHAN_W_RADAR_DETECT ?
8789 " (IEEE 802.11h required)" : "",
8790 (!(channels[i].flag & IEEE80211_CHAN_W_IBSS)
8791 || (channels[i].
8792 flag &
8793 IEEE80211_CHAN_W_RADAR_DETECT)) ? "" :
8794 ", IBSS",
8795 channels[i].
8796 flag & IEEE80211_CHAN_W_ACTIVE_SCAN ?
8797 "active/passive" : "passive only");
8798
8799 return len;
8800}
8801
8802static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
8803
8804static ssize_t show_statistics(struct device *d,
8805 struct device_attribute *attr, char *buf)
8806{
bb8c093b
CH		 8807 struct iwl4965_priv *priv = dev_get_drvdata(d);
8808 u32 size = sizeof(struct iwl4965_notif_statistics);
b481de9c
ZY		 8809 u32 len = 0, ofs = 0;
8810 u8 *data = (u8 *) & priv->statistics;
8811 int rc = 0;
8812
bb8c093b 8813 if (!iwl4965_is_alive(priv))
b481de9c
ZY		 8814 return -EAGAIN;
8815
8816 mutex_lock(&priv->mutex);
bb8c093b 8817 rc = iwl4965_send_statistics_request(priv);
b481de9c
ZY		 8818 mutex_unlock(&priv->mutex);
8819
8820 if (rc) {
8821 len = sprintf(buf,
8822 "Error sending statistics request: 0x%08X\n", rc);
8823 return len;
8824 }
8825
8826 while (size && (PAGE_SIZE - len)) {
8827 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
8828 PAGE_SIZE - len, 1);
8829 len = strlen(buf);
8830 if (PAGE_SIZE - len)
8831 buf[len++] = '\n';
8832
8833 ofs += 16;
8834 size -= min(size, 16U);
8835 }
8836
8837 return len;
8838}
8839
8840static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
8841
8842static ssize_t show_antenna(struct device *d,
8843 struct device_attribute *attr, char *buf)
8844{
bb8c093b 8845 struct iwl4965_priv *priv = dev_get_drvdata(d);
b481de9c 8846
bb8c093b 8847 if (!iwl4965_is_alive(priv))
b481de9c
ZY		 8848 return -EAGAIN;
8849
8850 return sprintf(buf, "%d\n", priv->antenna);
8851}
8852
8853static ssize_t store_antenna(struct device *d,
8854 struct device_attribute *attr,
8855 const char *buf, size_t count)
8856{
8857 int ant;
bb8c093b 8858 struct iwl4965_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 8859
8860 if (count == 0)
8861 return 0;
8862
8863 if (sscanf(buf, "%1i", &ant) != 1) {
8864 IWL_DEBUG_INFO("not in hex or decimal form.\n");
8865 return count;
8866 }
8867
8868 if ((ant >= 0) && (ant <= 2)) {
8869 IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
bb8c093b 8870 priv->antenna = (enum iwl4965_antenna)ant;
b481de9c
ZY		 8871 } else
8872 IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
8873
8874
8875 return count;
8876}
8877
8878static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
8879
8880static ssize_t show_status(struct device *d,
8881 struct device_attribute *attr, char *buf)
8882{
bb8c093b
CH		 8883 struct iwl4965_priv *priv = (struct iwl4965_priv *)d->driver_data;
8884 if (!iwl4965_is_alive(priv))
b481de9c
ZY		 8885 return -EAGAIN;
8886 return sprintf(buf, "0x%08x\n", (int)priv->status);
8887}
8888
8889static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
8890
8891static ssize_t dump_error_log(struct device *d,
8892 struct device_attribute *attr,
8893 const char *buf, size_t count)
8894{
8895 char *p = (char *)buf;
8896
8897 if (p[0] == '1')
bb8c093b 8898 iwl4965_dump_nic_error_log((struct iwl4965_priv *)d->driver_data);
b481de9c
ZY		 8899
8900 return strnlen(buf, count);
8901}
8902
8903static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
8904
8905static ssize_t dump_event_log(struct device *d,
8906 struct device_attribute *attr,
8907 const char *buf, size_t count)
8908{
8909 char *p = (char *)buf;
8910
8911 if (p[0] == '1')
bb8c093b 8912 iwl4965_dump_nic_event_log((struct iwl4965_priv *)d->driver_data);
b481de9c
ZY		 8913
8914 return strnlen(buf, count);
8915}
8916
8917static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
8918
8919/*****************************************************************************
8920 *
8921 * driver setup and teardown
8922 *
8923 *****************************************************************************/
8924
bb8c093b 8925static void iwl4965_setup_deferred_work(struct iwl4965_priv *priv)
b481de9c
ZY		 8926{
8927 priv->workqueue = create_workqueue(DRV_NAME);
8928
8929 init_waitqueue_head(&priv->wait_command_queue);
8930
bb8c093b
CH		 8931 INIT_WORK(&priv->up, iwl4965_bg_up);
8932 INIT_WORK(&priv->restart, iwl4965_bg_restart);
8933 INIT_WORK(&priv->rx_replenish, iwl4965_bg_rx_replenish);
8934 INIT_WORK(&priv->scan_completed, iwl4965_bg_scan_completed);
8935 INIT_WORK(&priv->request_scan, iwl4965_bg_request_scan);
8936 INIT_WORK(&priv->abort_scan, iwl4965_bg_abort_scan);
8937 INIT_WORK(&priv->rf_kill, iwl4965_bg_rf_kill);
8938 INIT_WORK(&priv->beacon_update, iwl4965_bg_beacon_update);
8939 INIT_DELAYED_WORK(&priv->post_associate, iwl4965_bg_post_associate);
8940 INIT_DELAYED_WORK(&priv->init_alive_start, iwl4965_bg_init_alive_start);
8941 INIT_DELAYED_WORK(&priv->alive_start, iwl4965_bg_alive_start);
8942 INIT_DELAYED_WORK(&priv->scan_check, iwl4965_bg_scan_check);
8943
8944 iwl4965_hw_setup_deferred_work(priv);
b481de9c
ZY		 8945
8946 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
bb8c093b 8947 iwl4965_irq_tasklet, (unsigned long)priv);
b481de9c
ZY		 8948}
8949
bb8c093b 8950static void iwl4965_cancel_deferred_work(struct iwl4965_priv *priv)
b481de9c 8951{
bb8c093b 8952 iwl4965_hw_cancel_deferred_work(priv);
b481de9c 8953
3ae6a054 8954 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY		 8955 cancel_delayed_work(&priv->scan_check);
8956 cancel_delayed_work(&priv->alive_start);
8957 cancel_delayed_work(&priv->post_associate);
8958 cancel_work_sync(&priv->beacon_update);
8959}
8960
bb8c093b 8961static struct attribute *iwl4965_sysfs_entries[] = {
b481de9c
ZY		 8962 &dev_attr_antenna.attr,
8963 &dev_attr_channels.attr,
8964 &dev_attr_dump_errors.attr,
8965 &dev_attr_dump_events.attr,
8966 &dev_attr_flags.attr,
8967 &dev_attr_filter_flags.attr,
c8b0e6e1 8968#ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT
b481de9c
ZY		 8969 &dev_attr_measurement.attr,
8970#endif
8971 &dev_attr_power_level.attr,
8972 &dev_attr_retry_rate.attr,
8973 &dev_attr_rf_kill.attr,
8974 &dev_attr_rs_window.attr,
8975 &dev_attr_statistics.attr,
8976 &dev_attr_status.attr,
8977 &dev_attr_temperature.attr,
8978 &dev_attr_tune.attr,
8979 &dev_attr_tx_power.attr,
8980
8981 NULL
8982};
8983
bb8c093b 8984static struct attribute_group iwl4965_attribute_group = {
b481de9c 8985 .name = NULL, /* put in device directory */
bb8c093b 8986 .attrs = iwl4965_sysfs_entries,
b481de9c
ZY		 8987};
8988
bb8c093b
CH		 8989static struct ieee80211_ops iwl4965_hw_ops = {
8990 .tx = iwl4965_mac_tx,
8991 .start = iwl4965_mac_start,
8992 .stop = iwl4965_mac_stop,
8993 .add_interface = iwl4965_mac_add_interface,
8994 .remove_interface = iwl4965_mac_remove_interface,
8995 .config = iwl4965_mac_config,
8996 .config_interface = iwl4965_mac_config_interface,
8997 .configure_filter = iwl4965_configure_filter,
8998 .set_key = iwl4965_mac_set_key,
8999 .get_stats = iwl4965_mac_get_stats,
9000 .get_tx_stats = iwl4965_mac_get_tx_stats,
9001 .conf_tx = iwl4965_mac_conf_tx,
9002 .get_tsf = iwl4965_mac_get_tsf,
9003 .reset_tsf = iwl4965_mac_reset_tsf,
9004 .beacon_update = iwl4965_mac_beacon_update,
471b3efd 9005 .bss_info_changed = iwl4965_bss_info_changed,
c8b0e6e1 9006#ifdef CONFIG_IWL4965_HT
bb8c093b 9007 .conf_ht = iwl4965_mac_conf_ht,
9ab46173 9008 .ampdu_action = iwl4965_mac_ampdu_action,
c8b0e6e1 9009#ifdef CONFIG_IWL4965_HT_AGG
bb8c093b
CH		 9010 .ht_tx_agg_start = iwl4965_mac_ht_tx_agg_start,
9011 .ht_tx_agg_stop = iwl4965_mac_ht_tx_agg_stop,
c8b0e6e1
CH		 9012#endif /* CONFIG_IWL4965_HT_AGG */
9013#endif /* CONFIG_IWL4965_HT */
bb8c093b 9014 .hw_scan = iwl4965_mac_hw_scan
b481de9c
ZY		 9015};
9016
bb8c093b 9017static int iwl4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY		 9018{
9019 int err = 0;
bb8c093b 9020 struct iwl4965_priv *priv;
b481de9c
ZY		 9021 struct ieee80211_hw *hw;
9022 int i;
5a66926a 9023 DECLARE_MAC_BUF(mac);
b481de9c 9024
6440adb5
CB		 9025 /* Disabling hardware scan means that mac80211 will perform scans
9026 * "the hard way", rather than using device's scan. */
bb8c093b 9027 if (iwl4965_param_disable_hw_scan) {
b481de9c 9028 IWL_DEBUG_INFO("Disabling hw_scan\n");
bb8c093b 9029 iwl4965_hw_ops.hw_scan = NULL;
b481de9c
ZY		 9030 }
9031
bb8c093b
CH		 9032 if ((iwl4965_param_queues_num > IWL_MAX_NUM_QUEUES) ||
9033 (iwl4965_param_queues_num < IWL_MIN_NUM_QUEUES)) {
b481de9c
ZY		 9034 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
9035 IWL_MIN_NUM_QUEUES, IWL_MAX_NUM_QUEUES);
9036 err = -EINVAL;
9037 goto out;
9038 }
9039
9040 /* mac80211 allocates memory for this device instance, including
9041 * space for this driver's private structure */
bb8c093b 9042 hw = ieee80211_alloc_hw(sizeof(struct iwl4965_priv), &iwl4965_hw_ops);
b481de9c
ZY		 9043 if (hw == NULL) {
9044 IWL_ERROR("Can not allocate network device\n");
9045 err = -ENOMEM;
9046 goto out;
9047 }
9048 SET_IEEE80211_DEV(hw, &pdev->dev);
9049
f51359a8
JB		 9050 hw->rate_control_algorithm = "iwl-4965-rs";
9051
b481de9c
ZY		 9052 IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
9053 priv = hw->priv;
9054 priv->hw = hw;
9055
9056 priv->pci_dev = pdev;
bb8c093b 9057 priv->antenna = (enum iwl4965_antenna)iwl4965_param_antenna;
c8b0e6e1 9058#ifdef CONFIG_IWL4965_DEBUG
bb8c093b 9059 iwl4965_debug_level = iwl4965_param_debug;
b481de9c
ZY		 9060 atomic_set(&priv->restrict_refcnt, 0);
9061#endif
9062 priv->retry_rate = 1;
9063
9064 priv->ibss_beacon = NULL;
9065
9066 /* Tell mac80211 and its clients (e.g. Wireless Extensions)
9067 * the range of signal quality values that we'll provide.
9068 * Negative values for level/noise indicate that we'll provide dBm.
9069 * For WE, at least, non-0 values here *enable* display of values
9070 * in app (iwconfig). */
9071 hw->max_rssi = -20; /* signal level, negative indicates dBm */
9072 hw->max_noise = -20; /* noise level, negative indicates dBm */
9073 hw->max_signal = 100; /* link quality indication (%) */
9074
9075 /* Tell mac80211 our Tx characteristics */
9076 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE;
9077
6440adb5 9078 /* Default value; 4 EDCA QOS priorities */
b481de9c 9079 hw->queues = 4;
c8b0e6e1
CH		 9080#ifdef CONFIG_IWL4965_HT
9081#ifdef CONFIG_IWL4965_HT_AGG
6440adb5 9082 /* Enhanced value; more queues, to support 11n aggregation */
b481de9c 9083 hw->queues = 16;
c8b0e6e1
CH		 9084#endif /* CONFIG_IWL4965_HT_AGG */
9085#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY		 9086
9087 spin_lock_init(&priv->lock);
9088 spin_lock_init(&priv->power_data.lock);
9089 spin_lock_init(&priv->sta_lock);
9090 spin_lock_init(&priv->hcmd_lock);
9091 spin_lock_init(&priv->lq_mngr.lock);
9092
9093 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
9094 INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
9095
9096 INIT_LIST_HEAD(&priv->free_frames);
9097
9098 mutex_init(&priv->mutex);
9099 if (pci_enable_device(pdev)) {
9100 err = -ENODEV;
9101 goto out_ieee80211_free_hw;
9102 }
9103
9104 pci_set_master(pdev);
9105
6440adb5 9106 /* Clear the driver's (not device's) station table */
bb8c093b 9107 iwl4965_clear_stations_table(priv);
b481de9c
ZY		 9108
9109 priv->data_retry_limit = -1;
9110 priv->ieee_channels = NULL;
9111 priv->ieee_rates = NULL;
9112 priv->phymode = -1;
9113
9114 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
9115 if (!err)
9116 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
9117 if (err) {
9118 printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
9119 goto out_pci_disable_device;
9120 }
9121
9122 pci_set_drvdata(pdev, priv);
9123 err = pci_request_regions(pdev, DRV_NAME);
9124 if (err)
9125 goto out_pci_disable_device;
6440adb5 9126
b481de9c
ZY		 9127 /* We disable the RETRY_TIMEOUT register (0x41) to keep
9128 * PCI Tx retries from interfering with C3 CPU state */
9129 pci_write_config_byte(pdev, 0x41, 0x00);
6440adb5 9130
b481de9c
ZY		 9131 priv->hw_base = pci_iomap(pdev, 0, 0);
9132 if (!priv->hw_base) {
9133 err = -ENODEV;
9134 goto out_pci_release_regions;
9135 }
9136
9137 IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
9138 (unsigned long long) pci_resource_len(pdev, 0));
9139 IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
9140
9141 /* Initialize module parameter values here */
9142
6440adb5 9143 /* Disable radio (SW RF KILL) via parameter when loading driver */
bb8c093b 9144 if (iwl4965_param_disable) {
b481de9c
ZY		 9145 set_bit(STATUS_RF_KILL_SW, &priv->status);
9146 IWL_DEBUG_INFO("Radio disabled.\n");
9147 }
9148
9149 priv->iw_mode = IEEE80211_IF_TYPE_STA;
9150
9151 priv->ps_mode = 0;
9152 priv->use_ant_b_for_management_frame = 1; /* start with ant B */
b481de9c
ZY		 9153 priv->valid_antenna = 0x7; /* assume all 3 connected */
9154 priv->ps_mode = IWL_MIMO_PS_NONE;
b481de9c 9155
6440adb5 9156 /* Choose which receivers/antennas to use */
b481de9c
ZY		 9157 iwl4965_set_rxon_chain(priv);
9158
9159 printk(KERN_INFO DRV_NAME
9160 ": Detected Intel Wireless WiFi Link 4965AGN\n");
9161
9162 /* Device-specific setup */
bb8c093b 9163 if (iwl4965_hw_set_hw_setting(priv)) {
b481de9c 9164 IWL_ERROR("failed to set hw settings\n");
b481de9c
ZY		 9165 goto out_iounmap;
9166 }
9167
c8b0e6e1 9168#ifdef CONFIG_IWL4965_QOS
bb8c093b 9169 if (iwl4965_param_qos_enable)
b481de9c
ZY		 9170 priv->qos_data.qos_enable = 1;
9171
bb8c093b 9172 iwl4965_reset_qos(priv);
b481de9c
ZY		 9173
9174 priv->qos_data.qos_active = 0;
9175 priv->qos_data.qos_cap.val = 0;
c8b0e6e1 9176#endif /* CONFIG_IWL4965_QOS */
b481de9c 9177
bb8c093b
CH		 9178 iwl4965_set_rxon_channel(priv, MODE_IEEE80211G, 6);
9179 iwl4965_setup_deferred_work(priv);
9180 iwl4965_setup_rx_handlers(priv);
b481de9c
ZY		 9181
9182 priv->rates_mask = IWL_RATES_MASK;
9183 /* If power management is turned on, default to AC mode */
9184 priv->power_mode = IWL_POWER_AC;
9185 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
9186
bb8c093b 9187 iwl4965_disable_interrupts(priv);
49df2b33 9188
bb8c093b 9189 err = sysfs_create_group(&pdev->dev.kobj, &iwl4965_attribute_group);
b481de9c
ZY		 9190 if (err) {
9191 IWL_ERROR("failed to create sysfs device attributes\n");
b481de9c
ZY		 9192 goto out_release_irq;
9193 }
9194
5a66926a
ZY		 9195 /* nic init */
9196 iwl4965_set_bit(priv, CSR_GIO_CHICKEN_BITS,
9197 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
9198
9199 iwl4965_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
9200 err = iwl4965_poll_bit(priv, CSR_GP_CNTRL,
9201 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
9202 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
9203 if (err < 0) {
9204 IWL_DEBUG_INFO("Failed to init the card\n");
9205 goto out_remove_sysfs;
9206 }
9207 /* Read the EEPROM */
9208 err = iwl4965_eeprom_init(priv);
b481de9c 9209 if (err) {
5a66926a
ZY		 9210 IWL_ERROR("Unable to init EEPROM\n");
9211 goto out_remove_sysfs;
b481de9c 9212 }
5a66926a
ZY		 9213 /* MAC Address location in EEPROM same for 3945/4965 */
9214 get_eeprom_mac(priv, priv->mac_addr);
9215 IWL_DEBUG_INFO("MAC address: %s\n", print_mac(mac, priv->mac_addr));
9216 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
b481de9c 9217
849e0dce
RC		 9218 err = iwl4965_init_channel_map(priv);
9219 if (err) {
9220 IWL_ERROR("initializing regulatory failed: %d\n", err);
9221 goto out_remove_sysfs;
9222 }
9223
9224 err = iwl4965_init_geos(priv);
9225 if (err) {
9226 IWL_ERROR("initializing geos failed: %d\n", err);
9227 goto out_free_channel_map;
9228 }
9229 iwl4965_reset_channel_flag(priv);
9230
5a66926a
ZY		 9231 iwl4965_rate_control_register(priv->hw);
9232 err = ieee80211_register_hw(priv->hw);
9233 if (err) {
9234 IWL_ERROR("Failed to register network device (error %d)\n", err);
849e0dce 9235 goto out_free_geos;
5a66926a 9236 }
b481de9c 9237
5a66926a
ZY		 9238 priv->hw->conf.beacon_int = 100;
9239 priv->mac80211_registered = 1;
9240 pci_save_state(pdev);
9241 pci_disable_device(pdev);
b481de9c
ZY		 9242
9243 return 0;
9244
849e0dce
RC		 9245 out_free_geos:
9246 iwl4965_free_geos(priv);
9247 out_free_channel_map:
9248 iwl4965_free_channel_map(priv);
5a66926a 9249 out_remove_sysfs:
bb8c093b 9250 sysfs_remove_group(&pdev->dev.kobj, &iwl4965_attribute_group);
b481de9c
ZY		 9251
9252 out_release_irq:
b481de9c
ZY		 9253 destroy_workqueue(priv->workqueue);
9254 priv->workqueue = NULL;
bb8c093b 9255 iwl4965_unset_hw_setting(priv);
b481de9c
ZY		 9256
9257 out_iounmap:
9258 pci_iounmap(pdev, priv->hw_base);
9259 out_pci_release_regions:
9260 pci_release_regions(pdev);
9261 out_pci_disable_device:
9262 pci_disable_device(pdev);
9263 pci_set_drvdata(pdev, NULL);
9264 out_ieee80211_free_hw:
9265 ieee80211_free_hw(priv->hw);
9266 out:
9267 return err;
9268}
9269
bb8c093b 9270static void iwl4965_pci_remove(struct pci_dev *pdev)
b481de9c 9271{
bb8c093b 9272 struct iwl4965_priv *priv = pci_get_drvdata(pdev);
b481de9c
ZY		 9273 struct list_head *p, *q;
9274 int i;
9275
9276 if (!priv)
9277 return;
9278
9279 IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
9280
b481de9c 9281 set_bit(STATUS_EXIT_PENDING, &priv->status);
b24d22b1 9282
bb8c093b 9283 iwl4965_down(priv);
b481de9c
ZY		 9284
9285 /* Free MAC hash list for ADHOC */
9286 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) {
9287 list_for_each_safe(p, q, &priv->ibss_mac_hash[i]) {
9288 list_del(p);
bb8c093b 9289 kfree(list_entry(p, struct iwl4965_ibss_seq, list));
b481de9c
ZY		 9290 }
9291 }
9292
bb8c093b 9293 sysfs_remove_group(&pdev->dev.kobj, &iwl4965_attribute_group);
b481de9c 9294
bb8c093b 9295 iwl4965_dealloc_ucode_pci(priv);
b481de9c
ZY		 9296
9297 if (priv->rxq.bd)
bb8c093b
CH		 9298 iwl4965_rx_queue_free(priv, &priv->rxq);
9299 iwl4965_hw_txq_ctx_free(priv);
b481de9c 9300
bb8c093b
CH		 9301 iwl4965_unset_hw_setting(priv);
9302 iwl4965_clear_stations_table(priv);
b481de9c
ZY		 9303
9304 if (priv->mac80211_registered) {
9305 ieee80211_unregister_hw(priv->hw);
bb8c093b 9306 iwl4965_rate_control_unregister(priv->hw);
b481de9c
ZY		 9307 }
9308
948c171c
MA		 9309 /*netif_stop_queue(dev); */
9310 flush_workqueue(priv->workqueue);
9311
bb8c093b 9312 /* ieee80211_unregister_hw calls iwl4965_mac_stop, which flushes
b481de9c
ZY		 9313 * priv->workqueue... so we can't take down the workqueue
9314 * until now... */
9315 destroy_workqueue(priv->workqueue);
9316 priv->workqueue = NULL;
9317
b481de9c
ZY		 9318 pci_iounmap(pdev, priv->hw_base);
9319 pci_release_regions(pdev);
9320 pci_disable_device(pdev);
9321 pci_set_drvdata(pdev, NULL);
9322
849e0dce
RC		 9323 iwl4965_free_channel_map(priv);
9324 iwl4965_free_geos(priv);
b481de9c
ZY		 9325
9326 if (priv->ibss_beacon)
9327 dev_kfree_skb(priv->ibss_beacon);
9328
9329 ieee80211_free_hw(priv->hw);
9330}
9331
9332#ifdef CONFIG_PM
9333
bb8c093b 9334static int iwl4965_pci_suspend(struct pci_dev *pdev, pm_message_t state)
b481de9c 9335{
bb8c093b 9336 struct iwl4965_priv *priv = pci_get_drvdata(pdev);
b481de9c 9337
e655b9f0
ZY		 9338 if (priv->is_open) {
9339 set_bit(STATUS_IN_SUSPEND, &priv->status);
9340 iwl4965_mac_stop(priv->hw);
9341 priv->is_open = 1;
9342 }
b481de9c 9343
b481de9c
ZY		 9344 pci_set_power_state(pdev, PCI_D3hot);
9345
b481de9c
ZY		 9346 return 0;
9347}
9348
bb8c093b 9349static int iwl4965_pci_resume(struct pci_dev *pdev)
b481de9c 9350{
bb8c093b 9351 struct iwl4965_priv *priv = pci_get_drvdata(pdev);
b481de9c 9352
b481de9c 9353 pci_set_power_state(pdev, PCI_D0);
b481de9c 9354
e655b9f0
ZY		 9355 if (priv->is_open)
9356 iwl4965_mac_start(priv->hw);
b481de9c 9357
e655b9f0 9358 clear_bit(STATUS_IN_SUSPEND, &priv->status);
b481de9c
ZY		 9359 return 0;
9360}
9361
9362#endif /* CONFIG_PM */
9363
9364/*****************************************************************************
9365 *
9366 * driver and module entry point
9367 *
9368 *****************************************************************************/
9369
bb8c093b 9370static struct pci_driver iwl4965_driver = {
b481de9c 9371 .name = DRV_NAME,
bb8c093b
CH		 9372 .id_table = iwl4965_hw_card_ids,
9373 .probe = iwl4965_pci_probe,
9374 .remove = __devexit_p(iwl4965_pci_remove),
b481de9c 9375#ifdef CONFIG_PM
bb8c093b
CH		 9376 .suspend = iwl4965_pci_suspend,
9377 .resume = iwl4965_pci_resume,
b481de9c
ZY		 9378#endif
9379};
9380
bb8c093b 9381static int __init iwl4965_init(void)
b481de9c
ZY		 9382{
9383
9384 int ret;
9385 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
9386 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
bb8c093b 9387 ret = pci_register_driver(&iwl4965_driver);
b481de9c
ZY		 9388 if (ret) {
9389 IWL_ERROR("Unable to initialize PCI module\n");
9390 return ret;
9391 }
c8b0e6e1 9392#ifdef CONFIG_IWL4965_DEBUG
bb8c093b 9393 ret = driver_create_file(&iwl4965_driver.driver, &driver_attr_debug_level);
b481de9c
ZY		 9394 if (ret) {
9395 IWL_ERROR("Unable to create driver sysfs file\n");
bb8c093b 9396 pci_unregister_driver(&iwl4965_driver);
b481de9c
ZY		 9397 return ret;
9398 }
9399#endif
9400
9401 return ret;
9402}
9403
bb8c093b 9404static void __exit iwl4965_exit(void)
b481de9c 9405{
c8b0e6e1 9406#ifdef CONFIG_IWL4965_DEBUG
bb8c093b 9407 driver_remove_file(&iwl4965_driver.driver, &driver_attr_debug_level);
b481de9c 9408#endif
bb8c093b 9409 pci_unregister_driver(&iwl4965_driver);
b481de9c
ZY		 9410}
9411
bb8c093b 9412module_param_named(antenna, iwl4965_param_antenna, int, 0444);
b481de9c 9413MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
bb8c093b 9414module_param_named(disable, iwl4965_param_disable, int, 0444);
b481de9c 9415MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
bb8c093b 9416module_param_named(hwcrypto, iwl4965_param_hwcrypto, int, 0444);
b481de9c
ZY		 9417MODULE_PARM_DESC(hwcrypto,
9418 "using hardware crypto engine (default 0 [software])\n");
bb8c093b 9419module_param_named(debug, iwl4965_param_debug, int, 0444);
b481de9c 9420MODULE_PARM_DESC(debug, "debug output mask");
bb8c093b 9421module_param_named(disable_hw_scan, iwl4965_param_disable_hw_scan, int, 0444);
b481de9c
ZY		 9422MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
9423
bb8c093b 9424module_param_named(queues_num, iwl4965_param_queues_num, int, 0444);
b481de9c
ZY		 9425MODULE_PARM_DESC(queues_num, "number of hw queues.");
9426
9427/* QoS */
bb8c093b 9428module_param_named(qos_enable, iwl4965_param_qos_enable, int, 0444);
b481de9c 9429MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
9ee1ba47
RR		 9430module_param_named(amsdu_size_8K, iwl4965_param_amsdu_size_8K, int, 0444);
9431MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
b481de9c 9432
bb8c093b
CH		 9433module_exit(iwl4965_exit);
9434module_init(iwl4965_init);
Linux kernel - Deliverables
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