iwlwifi: Move HBUS address to iwl-csr.h
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl4965-base.c
CommitLineData
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1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2007 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
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30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/version.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/dma-mapping.h>
36#include <linux/delay.h>
37#include <linux/skbuff.h>
38#include <linux/netdevice.h>
39#include <linux/wireless.h>
40#include <linux/firmware.h>
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41#include <linux/etherdevice.h>
42#include <linux/if_arp.h>
43
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44#include <net/mac80211.h>
45
46#include <asm/div64.h>
47
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48#include "iwl-4965.h"
49#include "iwl-helpers.h"
50
c8b0e6e1 51#ifdef CONFIG_IWL4965_DEBUG
bb8c093b 52u32 iwl4965_debug_level;
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53#endif
54
bb8c093b
CH
55static int iwl4965_tx_queue_update_write_ptr(struct iwl4965_priv *priv,
56 struct iwl4965_tx_queue *txq);
416e1438 57
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58/******************************************************************************
59 *
60 * module boiler plate
61 *
62 ******************************************************************************/
63
64/* module parameters */
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65static int iwl4965_param_disable_hw_scan; /* def: 0 = use 4965's h/w scan */
66static int iwl4965_param_debug; /* def: 0 = minimal debug log messages */
9fbab516
BC
67static int iwl4965_param_disable; /* def: enable radio */
68static int iwl4965_param_antenna; /* def: 0 = both antennas (use diversity) */
69int iwl4965_param_hwcrypto; /* def: using software encryption */
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70static int iwl4965_param_qos_enable = 1; /* def: 1 = use quality of service */
71int iwl4965_param_queues_num = IWL_MAX_NUM_QUEUES; /* def: 16 Tx queues */
9ee1ba47 72int iwl4965_param_amsdu_size_8K; /* def: enable 8K amsdu size */
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73
74/*
75 * module name, copyright, version, etc.
76 * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
77 */
78
79#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link 4965AGN driver for Linux"
80
c8b0e6e1 81#ifdef CONFIG_IWL4965_DEBUG
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82#define VD "d"
83#else
84#define VD
85#endif
86
c8b0e6e1 87#ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT
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88#define VS "s"
89#else
90#define VS
91#endif
92
b9e0b449 93#define IWLWIFI_VERSION "1.2.26k" VD VS
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94#define DRV_COPYRIGHT "Copyright(c) 2003-2007 Intel Corporation"
95#define DRV_VERSION IWLWIFI_VERSION
96
97/* Change firmware file name, using "-" and incrementing number,
98 * *only* when uCode interface or architecture changes so that it
99 * is not compatible with earlier drivers.
100 * This number will also appear in << 8 position of 1st dword of uCode file */
101#define IWL4965_UCODE_API "-1"
102
103MODULE_DESCRIPTION(DRV_DESCRIPTION);
104MODULE_VERSION(DRV_VERSION);
105MODULE_AUTHOR(DRV_COPYRIGHT);
106MODULE_LICENSE("GPL");
107
108__le16 *ieee80211_get_qos_ctrl(struct ieee80211_hdr *hdr)
109{
110 u16 fc = le16_to_cpu(hdr->frame_control);
111 int hdr_len = ieee80211_get_hdrlen(fc);
112
113 if ((fc & 0x00cc) == (IEEE80211_STYPE_QOS_DATA | IEEE80211_FTYPE_DATA))
114 return (__le16 *) ((u8 *) hdr + hdr_len - QOS_CONTROL_LEN);
115 return NULL;
116}
117
8318d78a
JB
118static const struct ieee80211_supported_band *iwl4965_get_hw_mode(
119 struct iwl4965_priv *priv, enum ieee80211_band band)
b481de9c 120{
8318d78a 121 return priv->hw->wiphy->bands[band];
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122}
123
bb8c093b 124static int iwl4965_is_empty_essid(const char *essid, int essid_len)
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125{
126 /* Single white space is for Linksys APs */
127 if (essid_len == 1 && essid[0] == ' ')
128 return 1;
129
130 /* Otherwise, if the entire essid is 0, we assume it is hidden */
131 while (essid_len) {
132 essid_len--;
133 if (essid[essid_len] != '\0')
134 return 0;
135 }
136
137 return 1;
138}
139
bb8c093b 140static const char *iwl4965_escape_essid(const char *essid, u8 essid_len)
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141{
142 static char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
143 const char *s = essid;
144 char *d = escaped;
145
bb8c093b 146 if (iwl4965_is_empty_essid(essid, essid_len)) {
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147 memcpy(escaped, "<hidden>", sizeof("<hidden>"));
148 return escaped;
149 }
150
151 essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE);
152 while (essid_len--) {
153 if (*s == '\0') {
154 *d++ = '\\';
155 *d++ = '0';
156 s++;
157 } else
158 *d++ = *s++;
159 }
160 *d = '\0';
161 return escaped;
162}
163
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164/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
165 * DMA services
166 *
167 * Theory of operation
168 *
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169 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
170 * of buffer descriptors, each of which points to one or more data buffers for
171 * the device to read from or fill. Driver and device exchange status of each
172 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
173 * entries in each circular buffer, to protect against confusing empty and full
174 * queue states.
175 *
176 * The device reads or writes the data in the queues via the device's several
177 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
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178 *
179 * For Tx queue, there are low mark and high mark limits. If, after queuing
180 * the packet for Tx, free space become < low mark, Tx queue stopped. When
181 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
182 * Tx queue resumed.
183 *
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184 * The 4965 operates with up to 17 queues: One receive queue, one transmit
185 * queue (#4) for sending commands to the device firmware, and 15 other
186 * Tx queues that may be mapped to prioritized Tx DMA/FIFO channels.
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BC
187 *
188 * See more detailed info in iwl-4965-hw.h.
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189 ***************************************************/
190
fe01b477 191int iwl4965_queue_space(const struct iwl4965_queue *q)
b481de9c 192{
fc4b6853 193 int s = q->read_ptr - q->write_ptr;
b481de9c 194
fc4b6853 195 if (q->read_ptr > q->write_ptr)
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196 s -= q->n_bd;
197
198 if (s <= 0)
199 s += q->n_window;
200 /* keep some reserve to not confuse empty and full situations */
201 s -= 2;
202 if (s < 0)
203 s = 0;
204 return s;
205}
206
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207/**
208 * iwl4965_queue_inc_wrap - increment queue index, wrap back to beginning
209 * @index -- current index
210 * @n_bd -- total number of entries in queue (must be power of 2)
211 */
bb8c093b 212static inline int iwl4965_queue_inc_wrap(int index, int n_bd)
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213{
214 return ++index & (n_bd - 1);
215}
216
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217/**
218 * iwl4965_queue_dec_wrap - decrement queue index, wrap back to end
219 * @index -- current index
220 * @n_bd -- total number of entries in queue (must be power of 2)
221 */
bb8c093b 222static inline int iwl4965_queue_dec_wrap(int index, int n_bd)
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223{
224 return --index & (n_bd - 1);
225}
226
bb8c093b 227static inline int x2_queue_used(const struct iwl4965_queue *q, int i)
b481de9c 228{
fc4b6853
TW
229 return q->write_ptr > q->read_ptr ?
230 (i >= q->read_ptr && i < q->write_ptr) :
231 !(i < q->read_ptr && i >= q->write_ptr);
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232}
233
bb8c093b 234static inline u8 get_cmd_index(struct iwl4965_queue *q, u32 index, int is_huge)
b481de9c 235{
6440adb5 236 /* This is for scan command, the big buffer at end of command array */
b481de9c 237 if (is_huge)
6440adb5 238 return q->n_window; /* must be power of 2 */
b481de9c 239
6440adb5 240 /* Otherwise, use normal size buffers */
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241 return index & (q->n_window - 1);
242}
243
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244/**
245 * iwl4965_queue_init - Initialize queue's high/low-water and read/write indexes
246 */
bb8c093b 247static int iwl4965_queue_init(struct iwl4965_priv *priv, struct iwl4965_queue *q,
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248 int count, int slots_num, u32 id)
249{
250 q->n_bd = count;
251 q->n_window = slots_num;
252 q->id = id;
253
bb8c093b
CH
254 /* count must be power-of-two size, otherwise iwl4965_queue_inc_wrap
255 * and iwl4965_queue_dec_wrap are broken. */
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256 BUG_ON(!is_power_of_2(count));
257
258 /* slots_num must be power-of-two size, otherwise
259 * get_cmd_index is broken. */
260 BUG_ON(!is_power_of_2(slots_num));
261
262 q->low_mark = q->n_window / 4;
263 if (q->low_mark < 4)
264 q->low_mark = 4;
265
266 q->high_mark = q->n_window / 8;
267 if (q->high_mark < 2)
268 q->high_mark = 2;
269
fc4b6853 270 q->write_ptr = q->read_ptr = 0;
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271
272 return 0;
273}
274
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275/**
276 * iwl4965_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
277 */
bb8c093b
CH
278static int iwl4965_tx_queue_alloc(struct iwl4965_priv *priv,
279 struct iwl4965_tx_queue *txq, u32 id)
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280{
281 struct pci_dev *dev = priv->pci_dev;
282
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283 /* Driver private data, only for Tx (not command) queues,
284 * not shared with device. */
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285 if (id != IWL_CMD_QUEUE_NUM) {
286 txq->txb = kmalloc(sizeof(txq->txb[0]) *
287 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
288 if (!txq->txb) {
01ebd063 289 IWL_ERROR("kmalloc for auxiliary BD "
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290 "structures failed\n");
291 goto error;
292 }
293 } else
294 txq->txb = NULL;
295
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296 /* Circular buffer of transmit frame descriptors (TFDs),
297 * shared with device */
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298 txq->bd = pci_alloc_consistent(dev,
299 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
300 &txq->q.dma_addr);
301
302 if (!txq->bd) {
303 IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
304 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
305 goto error;
306 }
307 txq->q.id = id;
308
309 return 0;
310
311 error:
312 if (txq->txb) {
313 kfree(txq->txb);
314 txq->txb = NULL;
315 }
316
317 return -ENOMEM;
318}
319
8b6eaea8
CB
320/**
321 * iwl4965_tx_queue_init - Allocate and initialize one tx/cmd queue
322 */
bb8c093b
CH
323int iwl4965_tx_queue_init(struct iwl4965_priv *priv,
324 struct iwl4965_tx_queue *txq, int slots_num, u32 txq_id)
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325{
326 struct pci_dev *dev = priv->pci_dev;
327 int len;
328 int rc = 0;
329
8b6eaea8
CB
330 /*
331 * Alloc buffer array for commands (Tx or other types of commands).
332 * For the command queue (#4), allocate command space + one big
333 * command for scan, since scan command is very huge; the system will
334 * not have two scans at the same time, so only one is needed.
bb54244b 335 * For normal Tx queues (all other queues), no super-size command
8b6eaea8
CB
336 * space is needed.
337 */
bb8c093b 338 len = sizeof(struct iwl4965_cmd) * slots_num;
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339 if (txq_id == IWL_CMD_QUEUE_NUM)
340 len += IWL_MAX_SCAN_SIZE;
341 txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
342 if (!txq->cmd)
343 return -ENOMEM;
344
8b6eaea8 345 /* Alloc driver data array and TFD circular buffer */
bb8c093b 346 rc = iwl4965_tx_queue_alloc(priv, txq, txq_id);
b481de9c
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347 if (rc) {
348 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
349
350 return -ENOMEM;
351 }
352 txq->need_update = 0;
353
354 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
bb8c093b 355 * iwl4965_queue_inc_wrap and iwl4965_queue_dec_wrap are broken. */
b481de9c 356 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
8b6eaea8
CB
357
358 /* Initialize queue's high/low-water marks, and head/tail indexes */
bb8c093b 359 iwl4965_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
b481de9c 360
8b6eaea8 361 /* Tell device where to find queue */
bb8c093b 362 iwl4965_hw_tx_queue_init(priv, txq);
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363
364 return 0;
365}
366
367/**
bb8c093b 368 * iwl4965_tx_queue_free - Deallocate DMA queue.
b481de9c
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369 * @txq: Transmit queue to deallocate.
370 *
371 * Empty queue by removing and destroying all BD's.
6440adb5
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372 * Free all buffers.
373 * 0-fill, but do not free "txq" descriptor structure.
b481de9c 374 */
bb8c093b 375void iwl4965_tx_queue_free(struct iwl4965_priv *priv, struct iwl4965_tx_queue *txq)
b481de9c 376{
bb8c093b 377 struct iwl4965_queue *q = &txq->q;
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378 struct pci_dev *dev = priv->pci_dev;
379 int len;
380
381 if (q->n_bd == 0)
382 return;
383
384 /* first, empty all BD's */
fc4b6853 385 for (; q->write_ptr != q->read_ptr;
bb8c093b
CH
386 q->read_ptr = iwl4965_queue_inc_wrap(q->read_ptr, q->n_bd))
387 iwl4965_hw_txq_free_tfd(priv, txq);
b481de9c 388
bb8c093b 389 len = sizeof(struct iwl4965_cmd) * q->n_window;
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390 if (q->id == IWL_CMD_QUEUE_NUM)
391 len += IWL_MAX_SCAN_SIZE;
392
6440adb5 393 /* De-alloc array of command/tx buffers */
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394 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
395
6440adb5 396 /* De-alloc circular buffer of TFDs */
b481de9c 397 if (txq->q.n_bd)
bb8c093b 398 pci_free_consistent(dev, sizeof(struct iwl4965_tfd_frame) *
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399 txq->q.n_bd, txq->bd, txq->q.dma_addr);
400
6440adb5 401 /* De-alloc array of per-TFD driver data */
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402 if (txq->txb) {
403 kfree(txq->txb);
404 txq->txb = NULL;
405 }
406
6440adb5 407 /* 0-fill queue descriptor structure */
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408 memset(txq, 0, sizeof(*txq));
409}
410
bb8c093b 411const u8 iwl4965_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
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412
413/*************** STATION TABLE MANAGEMENT ****
9fbab516 414 * mac80211 should be examined to determine if sta_info is duplicating
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415 * the functionality provided here
416 */
417
418/**************************************************************/
419
01ebd063 420#if 0 /* temporary disable till we add real remove station */
6440adb5
CB
421/**
422 * iwl4965_remove_station - Remove driver's knowledge of station.
423 *
424 * NOTE: This does not remove station from device's station table.
425 */
bb8c093b 426static u8 iwl4965_remove_station(struct iwl4965_priv *priv, const u8 *addr, int is_ap)
b481de9c
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427{
428 int index = IWL_INVALID_STATION;
429 int i;
430 unsigned long flags;
431
432 spin_lock_irqsave(&priv->sta_lock, flags);
433
434 if (is_ap)
435 index = IWL_AP_ID;
436 else if (is_broadcast_ether_addr(addr))
437 index = priv->hw_setting.bcast_sta_id;
438 else
439 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
440 if (priv->stations[i].used &&
441 !compare_ether_addr(priv->stations[i].sta.sta.addr,
442 addr)) {
443 index = i;
444 break;
445 }
446
447 if (unlikely(index == IWL_INVALID_STATION))
448 goto out;
449
450 if (priv->stations[index].used) {
451 priv->stations[index].used = 0;
452 priv->num_stations--;
453 }
454
455 BUG_ON(priv->num_stations < 0);
456
457out:
458 spin_unlock_irqrestore(&priv->sta_lock, flags);
459 return 0;
460}
556f8db7 461#endif
b481de9c 462
6440adb5
CB
463/**
464 * iwl4965_clear_stations_table - Clear the driver's station table
465 *
466 * NOTE: This does not clear or otherwise alter the device's station table.
467 */
bb8c093b 468static void iwl4965_clear_stations_table(struct iwl4965_priv *priv)
b481de9c
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469{
470 unsigned long flags;
471
472 spin_lock_irqsave(&priv->sta_lock, flags);
473
474 priv->num_stations = 0;
475 memset(priv->stations, 0, sizeof(priv->stations));
476
477 spin_unlock_irqrestore(&priv->sta_lock, flags);
478}
479
6440adb5
CB
480/**
481 * iwl4965_add_station_flags - Add station to tables in driver and device
482 */
67d62035
RR
483u8 iwl4965_add_station_flags(struct iwl4965_priv *priv, const u8 *addr,
484 int is_ap, u8 flags, void *ht_data)
b481de9c
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485{
486 int i;
487 int index = IWL_INVALID_STATION;
bb8c093b 488 struct iwl4965_station_entry *station;
b481de9c 489 unsigned long flags_spin;
0795af57 490 DECLARE_MAC_BUF(mac);
b481de9c
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491
492 spin_lock_irqsave(&priv->sta_lock, flags_spin);
493 if (is_ap)
494 index = IWL_AP_ID;
495 else if (is_broadcast_ether_addr(addr))
496 index = priv->hw_setting.bcast_sta_id;
497 else
498 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
499 if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
500 addr)) {
501 index = i;
502 break;
503 }
504
505 if (!priv->stations[i].used &&
506 index == IWL_INVALID_STATION)
507 index = i;
508 }
509
510
9fbab516
BC
511 /* These two conditions have the same outcome, but keep them separate
512 since they have different meanings */
b481de9c
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513 if (unlikely(index == IWL_INVALID_STATION)) {
514 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
515 return index;
516 }
517
518 if (priv->stations[index].used &&
519 !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
520 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
521 return index;
522 }
523
524
0795af57 525 IWL_DEBUG_ASSOC("Add STA ID %d: %s\n", index, print_mac(mac, addr));
b481de9c
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526 station = &priv->stations[index];
527 station->used = 1;
528 priv->num_stations++;
529
6440adb5 530 /* Set up the REPLY_ADD_STA command to send to device */
bb8c093b 531 memset(&station->sta, 0, sizeof(struct iwl4965_addsta_cmd));
b481de9c
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532 memcpy(station->sta.sta.addr, addr, ETH_ALEN);
533 station->sta.mode = 0;
534 station->sta.sta.sta_id = index;
535 station->sta.station_flags = 0;
536
c8b0e6e1 537#ifdef CONFIG_IWL4965_HT
b481de9c
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538 /* BCAST station and IBSS stations do not work in HT mode */
539 if (index != priv->hw_setting.bcast_sta_id &&
540 priv->iw_mode != IEEE80211_IF_TYPE_IBSS)
67d62035
RR
541 iwl4965_set_ht_add_station(priv, index,
542 (struct ieee80211_ht_info *) ht_data);
c8b0e6e1 543#endif /*CONFIG_IWL4965_HT*/
b481de9c
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544
545 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
6440adb5
CB
546
547 /* Add station to device's station table */
bb8c093b 548 iwl4965_send_add_station(priv, &station->sta, flags);
b481de9c
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549 return index;
550
551}
552
553/*************** DRIVER STATUS FUNCTIONS *****/
554
bb8c093b 555static inline int iwl4965_is_ready(struct iwl4965_priv *priv)
b481de9c
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556{
557 /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
558 * set but EXIT_PENDING is not */
559 return test_bit(STATUS_READY, &priv->status) &&
560 test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
561 !test_bit(STATUS_EXIT_PENDING, &priv->status);
562}
563
bb8c093b 564static inline int iwl4965_is_alive(struct iwl4965_priv *priv)
b481de9c
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565{
566 return test_bit(STATUS_ALIVE, &priv->status);
567}
568
bb8c093b 569static inline int iwl4965_is_init(struct iwl4965_priv *priv)
b481de9c
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570{
571 return test_bit(STATUS_INIT, &priv->status);
572}
573
bb8c093b 574static inline int iwl4965_is_rfkill(struct iwl4965_priv *priv)
b481de9c
ZY
575{
576 return test_bit(STATUS_RF_KILL_HW, &priv->status) ||
577 test_bit(STATUS_RF_KILL_SW, &priv->status);
578}
579
bb8c093b 580static inline int iwl4965_is_ready_rf(struct iwl4965_priv *priv)
b481de9c
ZY
581{
582
bb8c093b 583 if (iwl4965_is_rfkill(priv))
b481de9c
ZY
584 return 0;
585
bb8c093b 586 return iwl4965_is_ready(priv);
b481de9c
ZY
587}
588
589/*************** HOST COMMAND QUEUE FUNCTIONS *****/
590
591#define IWL_CMD(x) case x : return #x
592
593static const char *get_cmd_string(u8 cmd)
594{
595 switch (cmd) {
596 IWL_CMD(REPLY_ALIVE);
597 IWL_CMD(REPLY_ERROR);
598 IWL_CMD(REPLY_RXON);
599 IWL_CMD(REPLY_RXON_ASSOC);
600 IWL_CMD(REPLY_QOS_PARAM);
601 IWL_CMD(REPLY_RXON_TIMING);
602 IWL_CMD(REPLY_ADD_STA);
603 IWL_CMD(REPLY_REMOVE_STA);
604 IWL_CMD(REPLY_REMOVE_ALL_STA);
605 IWL_CMD(REPLY_TX);
606 IWL_CMD(REPLY_RATE_SCALE);
607 IWL_CMD(REPLY_LEDS_CMD);
608 IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
609 IWL_CMD(RADAR_NOTIFICATION);
610 IWL_CMD(REPLY_QUIET_CMD);
611 IWL_CMD(REPLY_CHANNEL_SWITCH);
612 IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
613 IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
614 IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
615 IWL_CMD(POWER_TABLE_CMD);
616 IWL_CMD(PM_SLEEP_NOTIFICATION);
617 IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
618 IWL_CMD(REPLY_SCAN_CMD);
619 IWL_CMD(REPLY_SCAN_ABORT_CMD);
620 IWL_CMD(SCAN_START_NOTIFICATION);
621 IWL_CMD(SCAN_RESULTS_NOTIFICATION);
622 IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
623 IWL_CMD(BEACON_NOTIFICATION);
624 IWL_CMD(REPLY_TX_BEACON);
625 IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
626 IWL_CMD(QUIET_NOTIFICATION);
627 IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
628 IWL_CMD(MEASURE_ABORT_NOTIFICATION);
629 IWL_CMD(REPLY_BT_CONFIG);
630 IWL_CMD(REPLY_STATISTICS_CMD);
631 IWL_CMD(STATISTICS_NOTIFICATION);
632 IWL_CMD(REPLY_CARD_STATE_CMD);
633 IWL_CMD(CARD_STATE_NOTIFICATION);
634 IWL_CMD(MISSED_BEACONS_NOTIFICATION);
635 IWL_CMD(REPLY_CT_KILL_CONFIG_CMD);
636 IWL_CMD(SENSITIVITY_CMD);
637 IWL_CMD(REPLY_PHY_CALIBRATION_CMD);
638 IWL_CMD(REPLY_RX_PHY_CMD);
639 IWL_CMD(REPLY_RX_MPDU_CMD);
640 IWL_CMD(REPLY_4965_RX);
641 IWL_CMD(REPLY_COMPRESSED_BA);
642 default:
643 return "UNKNOWN";
644
645 }
646}
647
648#define HOST_COMPLETE_TIMEOUT (HZ / 2)
649
650/**
bb8c093b 651 * iwl4965_enqueue_hcmd - enqueue a uCode command
b481de9c
ZY
652 * @priv: device private data point
653 * @cmd: a point to the ucode command structure
654 *
655 * The function returns < 0 values to indicate the operation is
656 * failed. On success, it turns the index (> 0) of command in the
657 * command queue.
658 */
bb8c093b 659static int iwl4965_enqueue_hcmd(struct iwl4965_priv *priv, struct iwl4965_host_cmd *cmd)
b481de9c 660{
bb8c093b
CH
661 struct iwl4965_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
662 struct iwl4965_queue *q = &txq->q;
663 struct iwl4965_tfd_frame *tfd;
b481de9c 664 u32 *control_flags;
bb8c093b 665 struct iwl4965_cmd *out_cmd;
b481de9c
ZY
666 u32 idx;
667 u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
668 dma_addr_t phys_addr;
669 int ret;
670 unsigned long flags;
671
672 /* If any of the command structures end up being larger than
673 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
674 * we will need to increase the size of the TFD entries */
675 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
676 !(cmd->meta.flags & CMD_SIZE_HUGE));
677
c342a1b9
GG
678 if (iwl4965_is_rfkill(priv)) {
679 IWL_DEBUG_INFO("Not sending command - RF KILL");
680 return -EIO;
681 }
682
bb8c093b 683 if (iwl4965_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
b481de9c
ZY
684 IWL_ERROR("No space for Tx\n");
685 return -ENOSPC;
686 }
687
688 spin_lock_irqsave(&priv->hcmd_lock, flags);
689
fc4b6853 690 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY
691 memset(tfd, 0, sizeof(*tfd));
692
693 control_flags = (u32 *) tfd;
694
fc4b6853 695 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
b481de9c
ZY
696 out_cmd = &txq->cmd[idx];
697
698 out_cmd->hdr.cmd = cmd->id;
699 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
700 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
701
702 /* At this point, the out_cmd now has all of the incoming cmd
703 * information */
704
705 out_cmd->hdr.flags = 0;
706 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
fc4b6853 707 INDEX_TO_SEQ(q->write_ptr));
b481de9c
ZY
708 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
709 out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
710
711 phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
bb8c093b
CH
712 offsetof(struct iwl4965_cmd, hdr);
713 iwl4965_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
b481de9c
ZY
714
715 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
716 "%d bytes at %d[%d]:%d\n",
717 get_cmd_string(out_cmd->hdr.cmd),
718 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
fc4b6853 719 fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
b481de9c
ZY
720
721 txq->need_update = 1;
6440adb5
CB
722
723 /* Set up entry in queue's byte count circular buffer */
b481de9c 724 ret = iwl4965_tx_queue_update_wr_ptr(priv, txq, 0);
6440adb5
CB
725
726 /* Increment and update queue's write index */
bb8c093b
CH
727 q->write_ptr = iwl4965_queue_inc_wrap(q->write_ptr, q->n_bd);
728 iwl4965_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY
729
730 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
731 return ret ? ret : idx;
732}
733
bb8c093b 734static int iwl4965_send_cmd_async(struct iwl4965_priv *priv, struct iwl4965_host_cmd *cmd)
b481de9c
ZY
735{
736 int ret;
737
738 BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
739
740 /* An asynchronous command can not expect an SKB to be set. */
741 BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
742
743 /* An asynchronous command MUST have a callback. */
744 BUG_ON(!cmd->meta.u.callback);
745
746 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
747 return -EBUSY;
748
bb8c093b 749 ret = iwl4965_enqueue_hcmd(priv, cmd);
b481de9c 750 if (ret < 0) {
bb8c093b 751 IWL_ERROR("Error sending %s: iwl4965_enqueue_hcmd failed: %d\n",
b481de9c
ZY
752 get_cmd_string(cmd->id), ret);
753 return ret;
754 }
755 return 0;
756}
757
bb8c093b 758static int iwl4965_send_cmd_sync(struct iwl4965_priv *priv, struct iwl4965_host_cmd *cmd)
b481de9c
ZY
759{
760 int cmd_idx;
761 int ret;
762 static atomic_t entry = ATOMIC_INIT(0); /* reentrance protection */
763
764 BUG_ON(cmd->meta.flags & CMD_ASYNC);
765
766 /* A synchronous command can not have a callback set. */
767 BUG_ON(cmd->meta.u.callback != NULL);
768
769 if (atomic_xchg(&entry, 1)) {
770 IWL_ERROR("Error sending %s: Already sending a host command\n",
771 get_cmd_string(cmd->id));
772 return -EBUSY;
773 }
774
775 set_bit(STATUS_HCMD_ACTIVE, &priv->status);
776
777 if (cmd->meta.flags & CMD_WANT_SKB)
778 cmd->meta.source = &cmd->meta;
779
bb8c093b 780 cmd_idx = iwl4965_enqueue_hcmd(priv, cmd);
b481de9c
ZY
781 if (cmd_idx < 0) {
782 ret = cmd_idx;
bb8c093b 783 IWL_ERROR("Error sending %s: iwl4965_enqueue_hcmd failed: %d\n",
b481de9c
ZY
784 get_cmd_string(cmd->id), ret);
785 goto out;
786 }
787
788 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
789 !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
790 HOST_COMPLETE_TIMEOUT);
791 if (!ret) {
792 if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
793 IWL_ERROR("Error sending %s: time out after %dms.\n",
794 get_cmd_string(cmd->id),
795 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
796
797 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
798 ret = -ETIMEDOUT;
799 goto cancel;
800 }
801 }
802
803 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
804 IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
805 get_cmd_string(cmd->id));
806 ret = -ECANCELED;
807 goto fail;
808 }
809 if (test_bit(STATUS_FW_ERROR, &priv->status)) {
810 IWL_DEBUG_INFO("Command %s failed: FW Error\n",
811 get_cmd_string(cmd->id));
812 ret = -EIO;
813 goto fail;
814 }
815 if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
816 IWL_ERROR("Error: Response NULL in '%s'\n",
817 get_cmd_string(cmd->id));
818 ret = -EIO;
819 goto out;
820 }
821
822 ret = 0;
823 goto out;
824
825cancel:
826 if (cmd->meta.flags & CMD_WANT_SKB) {
bb8c093b 827 struct iwl4965_cmd *qcmd;
b481de9c
ZY
828
829 /* Cancel the CMD_WANT_SKB flag for the cmd in the
830 * TX cmd queue. Otherwise in case the cmd comes
831 * in later, it will possibly set an invalid
832 * address (cmd->meta.source). */
833 qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
834 qcmd->meta.flags &= ~CMD_WANT_SKB;
835 }
836fail:
837 if (cmd->meta.u.skb) {
838 dev_kfree_skb_any(cmd->meta.u.skb);
839 cmd->meta.u.skb = NULL;
840 }
841out:
842 atomic_set(&entry, 0);
843 return ret;
844}
845
bb8c093b 846int iwl4965_send_cmd(struct iwl4965_priv *priv, struct iwl4965_host_cmd *cmd)
b481de9c 847{
b481de9c 848 if (cmd->meta.flags & CMD_ASYNC)
bb8c093b 849 return iwl4965_send_cmd_async(priv, cmd);
b481de9c 850
bb8c093b 851 return iwl4965_send_cmd_sync(priv, cmd);
b481de9c
ZY
852}
853
bb8c093b 854int iwl4965_send_cmd_pdu(struct iwl4965_priv *priv, u8 id, u16 len, const void *data)
b481de9c 855{
bb8c093b 856 struct iwl4965_host_cmd cmd = {
b481de9c
ZY
857 .id = id,
858 .len = len,
859 .data = data,
860 };
861
bb8c093b 862 return iwl4965_send_cmd_sync(priv, &cmd);
b481de9c
ZY
863}
864
bb8c093b 865static int __must_check iwl4965_send_cmd_u32(struct iwl4965_priv *priv, u8 id, u32 val)
b481de9c 866{
bb8c093b 867 struct iwl4965_host_cmd cmd = {
b481de9c
ZY
868 .id = id,
869 .len = sizeof(val),
870 .data = &val,
871 };
872
bb8c093b 873 return iwl4965_send_cmd_sync(priv, &cmd);
b481de9c
ZY
874}
875
bb8c093b 876int iwl4965_send_statistics_request(struct iwl4965_priv *priv)
b481de9c 877{
bb8c093b 878 return iwl4965_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
b481de9c
ZY
879}
880
881/**
bb8c093b 882 * iwl4965_rxon_add_station - add station into station table.
b481de9c
ZY
883 *
884 * there is only one AP station with id= IWL_AP_ID
9fbab516
BC
885 * NOTE: mutex must be held before calling this fnction
886 */
bb8c093b 887static int iwl4965_rxon_add_station(struct iwl4965_priv *priv,
b481de9c
ZY
888 const u8 *addr, int is_ap)
889{
556f8db7 890 u8 sta_id;
b481de9c 891
6440adb5 892 /* Add station to device's station table */
67d62035
RR
893#ifdef CONFIG_IWL4965_HT
894 struct ieee80211_conf *conf = &priv->hw->conf;
895 struct ieee80211_ht_info *cur_ht_config = &conf->ht_conf;
896
897 if ((is_ap) &&
898 (conf->flags & IEEE80211_CONF_SUPPORT_HT_MODE) &&
899 (priv->iw_mode == IEEE80211_IF_TYPE_STA))
900 sta_id = iwl4965_add_station_flags(priv, addr, is_ap,
901 0, cur_ht_config);
902 else
903#endif /* CONFIG_IWL4965_HT */
904 sta_id = iwl4965_add_station_flags(priv, addr, is_ap,
905 0, NULL);
6440adb5
CB
906
907 /* Set up default rate scaling table in device's station table */
b481de9c
ZY
908 iwl4965_add_station(priv, addr, is_ap);
909
556f8db7 910 return sta_id;
b481de9c
ZY
911}
912
913/**
bb8c093b 914 * iwl4965_set_rxon_channel - Set the phymode and channel values in staging RXON
b481de9c
ZY
915 * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
916 * @channel: Any channel valid for the requested phymode
917
918 * In addition to setting the staging RXON, priv->phymode is also set.
919 *
920 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
921 * in the staging RXON flag structure based on the phymode
922 */
8318d78a
JB
923static int iwl4965_set_rxon_channel(struct iwl4965_priv *priv,
924 enum ieee80211_band band,
9fbab516 925 u16 channel)
b481de9c 926{
8318d78a 927 if (!iwl4965_get_channel_info(priv, band, channel)) {
b481de9c 928 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
8318d78a 929 channel, band);
b481de9c
ZY
930 return -EINVAL;
931 }
932
933 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
8318d78a 934 (priv->band == band))
b481de9c
ZY
935 return 0;
936
937 priv->staging_rxon.channel = cpu_to_le16(channel);
8318d78a 938 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY
939 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
940 else
941 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
942
8318d78a 943 priv->band = band;
b481de9c 944
8318d78a 945 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
b481de9c
ZY
946
947 return 0;
948}
949
950/**
bb8c093b 951 * iwl4965_check_rxon_cmd - validate RXON structure is valid
b481de9c
ZY
952 *
953 * NOTE: This is really only useful during development and can eventually
954 * be #ifdef'd out once the driver is stable and folks aren't actively
955 * making changes
956 */
bb8c093b 957static int iwl4965_check_rxon_cmd(struct iwl4965_rxon_cmd *rxon)
b481de9c
ZY
958{
959 int error = 0;
960 int counter = 1;
961
962 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
963 error |= le32_to_cpu(rxon->flags &
964 (RXON_FLG_TGJ_NARROW_BAND_MSK |
965 RXON_FLG_RADAR_DETECT_MSK));
966 if (error)
967 IWL_WARNING("check 24G fields %d | %d\n",
968 counter++, error);
969 } else {
970 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
971 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
972 if (error)
973 IWL_WARNING("check 52 fields %d | %d\n",
974 counter++, error);
975 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
976 if (error)
977 IWL_WARNING("check 52 CCK %d | %d\n",
978 counter++, error);
979 }
980 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
981 if (error)
982 IWL_WARNING("check mac addr %d | %d\n", counter++, error);
983
984 /* make sure basic rates 6Mbps and 1Mbps are supported */
985 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
986 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
987 if (error)
988 IWL_WARNING("check basic rate %d | %d\n", counter++, error);
989
990 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
991 if (error)
992 IWL_WARNING("check assoc id %d | %d\n", counter++, error);
993
994 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
995 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
996 if (error)
997 IWL_WARNING("check CCK and short slot %d | %d\n",
998 counter++, error);
999
1000 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
1001 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
1002 if (error)
1003 IWL_WARNING("check CCK & auto detect %d | %d\n",
1004 counter++, error);
1005
1006 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
1007 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
1008 if (error)
1009 IWL_WARNING("check TGG and auto detect %d | %d\n",
1010 counter++, error);
1011
1012 if (error)
1013 IWL_WARNING("Tuning to channel %d\n",
1014 le16_to_cpu(rxon->channel));
1015
1016 if (error) {
bb8c093b 1017 IWL_ERROR("Not a valid iwl4965_rxon_assoc_cmd field values\n");
b481de9c
ZY
1018 return -1;
1019 }
1020 return 0;
1021}
1022
1023/**
9fbab516 1024 * iwl4965_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
01ebd063 1025 * @priv: staging_rxon is compared to active_rxon
b481de9c 1026 *
9fbab516
BC
1027 * If the RXON structure is changing enough to require a new tune,
1028 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
1029 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
b481de9c 1030 */
bb8c093b 1031static int iwl4965_full_rxon_required(struct iwl4965_priv *priv)
b481de9c
ZY
1032{
1033
1034 /* These items are only settable from the full RXON command */
1035 if (!(priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ||
1036 compare_ether_addr(priv->staging_rxon.bssid_addr,
1037 priv->active_rxon.bssid_addr) ||
1038 compare_ether_addr(priv->staging_rxon.node_addr,
1039 priv->active_rxon.node_addr) ||
1040 compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
1041 priv->active_rxon.wlap_bssid_addr) ||
1042 (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
1043 (priv->staging_rxon.channel != priv->active_rxon.channel) ||
1044 (priv->staging_rxon.air_propagation !=
1045 priv->active_rxon.air_propagation) ||
1046 (priv->staging_rxon.ofdm_ht_single_stream_basic_rates !=
1047 priv->active_rxon.ofdm_ht_single_stream_basic_rates) ||
1048 (priv->staging_rxon.ofdm_ht_dual_stream_basic_rates !=
1049 priv->active_rxon.ofdm_ht_dual_stream_basic_rates) ||
1050 (priv->staging_rxon.rx_chain != priv->active_rxon.rx_chain) ||
1051 (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
1052 return 1;
1053
1054 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
1055 * be updated with the RXON_ASSOC command -- however only some
1056 * flag transitions are allowed using RXON_ASSOC */
1057
1058 /* Check if we are not switching bands */
1059 if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
1060 (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
1061 return 1;
1062
1063 /* Check if we are switching association toggle */
1064 if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
1065 (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
1066 return 1;
1067
1068 return 0;
1069}
1070
bb8c093b 1071static int iwl4965_send_rxon_assoc(struct iwl4965_priv *priv)
b481de9c
ZY
1072{
1073 int rc = 0;
bb8c093b
CH
1074 struct iwl4965_rx_packet *res = NULL;
1075 struct iwl4965_rxon_assoc_cmd rxon_assoc;
1076 struct iwl4965_host_cmd cmd = {
b481de9c
ZY
1077 .id = REPLY_RXON_ASSOC,
1078 .len = sizeof(rxon_assoc),
1079 .meta.flags = CMD_WANT_SKB,
1080 .data = &rxon_assoc,
1081 };
bb8c093b
CH
1082 const struct iwl4965_rxon_cmd *rxon1 = &priv->staging_rxon;
1083 const struct iwl4965_rxon_cmd *rxon2 = &priv->active_rxon;
b481de9c
ZY
1084
1085 if ((rxon1->flags == rxon2->flags) &&
1086 (rxon1->filter_flags == rxon2->filter_flags) &&
1087 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1088 (rxon1->ofdm_ht_single_stream_basic_rates ==
1089 rxon2->ofdm_ht_single_stream_basic_rates) &&
1090 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1091 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1092 (rxon1->rx_chain == rxon2->rx_chain) &&
1093 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1094 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
1095 return 0;
1096 }
1097
1098 rxon_assoc.flags = priv->staging_rxon.flags;
1099 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1100 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1101 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1102 rxon_assoc.reserved = 0;
1103 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1104 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1105 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1106 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1107 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1108
bb8c093b 1109 rc = iwl4965_send_cmd_sync(priv, &cmd);
b481de9c
ZY
1110 if (rc)
1111 return rc;
1112
bb8c093b 1113 res = (struct iwl4965_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY
1114 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1115 IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
1116 rc = -EIO;
1117 }
1118
1119 priv->alloc_rxb_skb--;
1120 dev_kfree_skb_any(cmd.meta.u.skb);
1121
1122 return rc;
1123}
1124
1125/**
bb8c093b 1126 * iwl4965_commit_rxon - commit staging_rxon to hardware
b481de9c 1127 *
01ebd063 1128 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
ZY
1129 * the active_rxon structure is updated with the new data. This
1130 * function correctly transitions out of the RXON_ASSOC_MSK state if
1131 * a HW tune is required based on the RXON structure changes.
1132 */
bb8c093b 1133static int iwl4965_commit_rxon(struct iwl4965_priv *priv)
b481de9c
ZY
1134{
1135 /* cast away the const for active_rxon in this function */
bb8c093b 1136 struct iwl4965_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
0795af57 1137 DECLARE_MAC_BUF(mac);
b481de9c
ZY
1138 int rc = 0;
1139
bb8c093b 1140 if (!iwl4965_is_alive(priv))
b481de9c
ZY
1141 return -1;
1142
1143 /* always get timestamp with Rx frame */
1144 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
1145
bb8c093b 1146 rc = iwl4965_check_rxon_cmd(&priv->staging_rxon);
b481de9c
ZY
1147 if (rc) {
1148 IWL_ERROR("Invalid RXON configuration. Not committing.\n");
1149 return -EINVAL;
1150 }
1151
1152 /* If we don't need to send a full RXON, we can use
bb8c093b 1153 * iwl4965_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 1154 * and other flags for the current radio configuration. */
bb8c093b
CH
1155 if (!iwl4965_full_rxon_required(priv)) {
1156 rc = iwl4965_send_rxon_assoc(priv);
b481de9c
ZY
1157 if (rc) {
1158 IWL_ERROR("Error setting RXON_ASSOC "
1159 "configuration (%d).\n", rc);
1160 return rc;
1161 }
1162
1163 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1164
1165 return 0;
1166 }
1167
1168 /* station table will be cleared */
1169 priv->assoc_station_added = 0;
1170
c8b0e6e1 1171#ifdef CONFIG_IWL4965_SENSITIVITY
b481de9c
ZY
1172 priv->sensitivity_data.state = IWL_SENS_CALIB_NEED_REINIT;
1173 if (!priv->error_recovering)
1174 priv->start_calib = 0;
1175
1176 iwl4965_init_sensitivity(priv, CMD_ASYNC, 1);
c8b0e6e1 1177#endif /* CONFIG_IWL4965_SENSITIVITY */
b481de9c
ZY
1178
1179 /* If we are currently associated and the new config requires
1180 * an RXON_ASSOC and the new config wants the associated mask enabled,
1181 * we must clear the associated from the active configuration
1182 * before we apply the new config */
bb8c093b 1183 if (iwl4965_is_associated(priv) &&
b481de9c
ZY
1184 (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
1185 IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
1186 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1187
bb8c093b
CH
1188 rc = iwl4965_send_cmd_pdu(priv, REPLY_RXON,
1189 sizeof(struct iwl4965_rxon_cmd),
b481de9c
ZY
1190 &priv->active_rxon);
1191
1192 /* If the mask clearing failed then we set
1193 * active_rxon back to what it was previously */
1194 if (rc) {
1195 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1196 IWL_ERROR("Error clearing ASSOC_MSK on current "
1197 "configuration (%d).\n", rc);
1198 return rc;
1199 }
b481de9c
ZY
1200 }
1201
1202 IWL_DEBUG_INFO("Sending RXON\n"
1203 "* with%s RXON_FILTER_ASSOC_MSK\n"
1204 "* channel = %d\n"
0795af57 1205 "* bssid = %s\n",
b481de9c
ZY
1206 ((priv->staging_rxon.filter_flags &
1207 RXON_FILTER_ASSOC_MSK) ? "" : "out"),
1208 le16_to_cpu(priv->staging_rxon.channel),
0795af57 1209 print_mac(mac, priv->staging_rxon.bssid_addr));
b481de9c
ZY
1210
1211 /* Apply the new configuration */
bb8c093b
CH
1212 rc = iwl4965_send_cmd_pdu(priv, REPLY_RXON,
1213 sizeof(struct iwl4965_rxon_cmd), &priv->staging_rxon);
b481de9c
ZY
1214 if (rc) {
1215 IWL_ERROR("Error setting new configuration (%d).\n", rc);
1216 return rc;
1217 }
1218
bb8c093b 1219 iwl4965_clear_stations_table(priv);
556f8db7 1220
c8b0e6e1 1221#ifdef CONFIG_IWL4965_SENSITIVITY
b481de9c
ZY
1222 if (!priv->error_recovering)
1223 priv->start_calib = 0;
1224
1225 priv->sensitivity_data.state = IWL_SENS_CALIB_NEED_REINIT;
1226 iwl4965_init_sensitivity(priv, CMD_ASYNC, 1);
c8b0e6e1 1227#endif /* CONFIG_IWL4965_SENSITIVITY */
b481de9c
ZY
1228
1229 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1230
1231 /* If we issue a new RXON command which required a tune then we must
1232 * send a new TXPOWER command or we won't be able to Tx any frames */
bb8c093b 1233 rc = iwl4965_hw_reg_send_txpower(priv);
b481de9c
ZY
1234 if (rc) {
1235 IWL_ERROR("Error setting Tx power (%d).\n", rc);
1236 return rc;
1237 }
1238
1239 /* Add the broadcast address so we can send broadcast frames */
bb8c093b 1240 if (iwl4965_rxon_add_station(priv, iwl4965_broadcast_addr, 0) ==
b481de9c
ZY
1241 IWL_INVALID_STATION) {
1242 IWL_ERROR("Error adding BROADCAST address for transmit.\n");
1243 return -EIO;
1244 }
1245
1246 /* If we have set the ASSOC_MSK and we are in BSS mode then
1247 * add the IWL_AP_ID to the station rate table */
bb8c093b 1248 if (iwl4965_is_associated(priv) &&
b481de9c 1249 (priv->iw_mode == IEEE80211_IF_TYPE_STA)) {
bb8c093b 1250 if (iwl4965_rxon_add_station(priv, priv->active_rxon.bssid_addr, 1)
b481de9c
ZY
1251 == IWL_INVALID_STATION) {
1252 IWL_ERROR("Error adding AP address for transmit.\n");
1253 return -EIO;
1254 }
1255 priv->assoc_station_added = 1;
1256 }
1257
1258 return 0;
1259}
1260
bb8c093b 1261static int iwl4965_send_bt_config(struct iwl4965_priv *priv)
b481de9c 1262{
bb8c093b 1263 struct iwl4965_bt_cmd bt_cmd = {
b481de9c
ZY
1264 .flags = 3,
1265 .lead_time = 0xAA,
1266 .max_kill = 1,
1267 .kill_ack_mask = 0,
1268 .kill_cts_mask = 0,
1269 };
1270
bb8c093b
CH
1271 return iwl4965_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1272 sizeof(struct iwl4965_bt_cmd), &bt_cmd);
b481de9c
ZY
1273}
1274
bb8c093b 1275static int iwl4965_send_scan_abort(struct iwl4965_priv *priv)
b481de9c
ZY
1276{
1277 int rc = 0;
bb8c093b
CH
1278 struct iwl4965_rx_packet *res;
1279 struct iwl4965_host_cmd cmd = {
b481de9c
ZY
1280 .id = REPLY_SCAN_ABORT_CMD,
1281 .meta.flags = CMD_WANT_SKB,
1282 };
1283
1284 /* If there isn't a scan actively going on in the hardware
1285 * then we are in between scan bands and not actually
1286 * actively scanning, so don't send the abort command */
1287 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
1288 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1289 return 0;
1290 }
1291
bb8c093b 1292 rc = iwl4965_send_cmd_sync(priv, &cmd);
b481de9c
ZY
1293 if (rc) {
1294 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1295 return rc;
1296 }
1297
bb8c093b 1298 res = (struct iwl4965_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY
1299 if (res->u.status != CAN_ABORT_STATUS) {
1300 /* The scan abort will return 1 for success or
1301 * 2 for "failure". A failure condition can be
1302 * due to simply not being in an active scan which
1303 * can occur if we send the scan abort before we
1304 * the microcode has notified us that a scan is
1305 * completed. */
1306 IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
1307 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1308 clear_bit(STATUS_SCAN_HW, &priv->status);
1309 }
1310
1311 dev_kfree_skb_any(cmd.meta.u.skb);
1312
1313 return rc;
1314}
1315
bb8c093b
CH
1316static int iwl4965_card_state_sync_callback(struct iwl4965_priv *priv,
1317 struct iwl4965_cmd *cmd,
b481de9c
ZY
1318 struct sk_buff *skb)
1319{
1320 return 1;
1321}
1322
1323/*
1324 * CARD_STATE_CMD
1325 *
9fbab516 1326 * Use: Sets the device's internal card state to enable, disable, or halt
b481de9c
ZY
1327 *
1328 * When in the 'enable' state the card operates as normal.
1329 * When in the 'disable' state, the card enters into a low power mode.
1330 * When in the 'halt' state, the card is shut down and must be fully
1331 * restarted to come back on.
1332 */
bb8c093b 1333static int iwl4965_send_card_state(struct iwl4965_priv *priv, u32 flags, u8 meta_flag)
b481de9c 1334{
bb8c093b 1335 struct iwl4965_host_cmd cmd = {
b481de9c
ZY
1336 .id = REPLY_CARD_STATE_CMD,
1337 .len = sizeof(u32),
1338 .data = &flags,
1339 .meta.flags = meta_flag,
1340 };
1341
1342 if (meta_flag & CMD_ASYNC)
bb8c093b 1343 cmd.meta.u.callback = iwl4965_card_state_sync_callback;
b481de9c 1344
bb8c093b 1345 return iwl4965_send_cmd(priv, &cmd);
b481de9c
ZY
1346}
1347
bb8c093b
CH
1348static int iwl4965_add_sta_sync_callback(struct iwl4965_priv *priv,
1349 struct iwl4965_cmd *cmd, struct sk_buff *skb)
b481de9c 1350{
bb8c093b 1351 struct iwl4965_rx_packet *res = NULL;
b481de9c
ZY
1352
1353 if (!skb) {
1354 IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
1355 return 1;
1356 }
1357
bb8c093b 1358 res = (struct iwl4965_rx_packet *)skb->data;
b481de9c
ZY
1359 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1360 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1361 res->hdr.flags);
1362 return 1;
1363 }
1364
1365 switch (res->u.add_sta.status) {
1366 case ADD_STA_SUCCESS_MSK:
1367 break;
1368 default:
1369 break;
1370 }
1371
1372 /* We didn't cache the SKB; let the caller free it */
1373 return 1;
1374}
1375
bb8c093b
CH
1376int iwl4965_send_add_station(struct iwl4965_priv *priv,
1377 struct iwl4965_addsta_cmd *sta, u8 flags)
b481de9c 1378{
bb8c093b 1379 struct iwl4965_rx_packet *res = NULL;
b481de9c 1380 int rc = 0;
bb8c093b 1381 struct iwl4965_host_cmd cmd = {
b481de9c 1382 .id = REPLY_ADD_STA,
bb8c093b 1383 .len = sizeof(struct iwl4965_addsta_cmd),
b481de9c
ZY
1384 .meta.flags = flags,
1385 .data = sta,
1386 };
1387
1388 if (flags & CMD_ASYNC)
bb8c093b 1389 cmd.meta.u.callback = iwl4965_add_sta_sync_callback;
b481de9c
ZY
1390 else
1391 cmd.meta.flags |= CMD_WANT_SKB;
1392
bb8c093b 1393 rc = iwl4965_send_cmd(priv, &cmd);
b481de9c
ZY
1394
1395 if (rc || (flags & CMD_ASYNC))
1396 return rc;
1397
bb8c093b 1398 res = (struct iwl4965_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY
1399 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1400 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1401 res->hdr.flags);
1402 rc = -EIO;
1403 }
1404
1405 if (rc == 0) {
1406 switch (res->u.add_sta.status) {
1407 case ADD_STA_SUCCESS_MSK:
1408 IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
1409 break;
1410 default:
1411 rc = -EIO;
1412 IWL_WARNING("REPLY_ADD_STA failed\n");
1413 break;
1414 }
1415 }
1416
1417 priv->alloc_rxb_skb--;
1418 dev_kfree_skb_any(cmd.meta.u.skb);
1419
1420 return rc;
1421}
1422
bb8c093b 1423static int iwl4965_update_sta_key_info(struct iwl4965_priv *priv,
b481de9c
ZY
1424 struct ieee80211_key_conf *keyconf,
1425 u8 sta_id)
1426{
1427 unsigned long flags;
1428 __le16 key_flags = 0;
1429
1430 switch (keyconf->alg) {
1431 case ALG_CCMP:
1432 key_flags |= STA_KEY_FLG_CCMP;
1433 key_flags |= cpu_to_le16(
1434 keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
1435 key_flags &= ~STA_KEY_FLG_INVALID;
1436 break;
1437 case ALG_TKIP:
1438 case ALG_WEP:
b481de9c
ZY
1439 default:
1440 return -EINVAL;
1441 }
1442 spin_lock_irqsave(&priv->sta_lock, flags);
1443 priv->stations[sta_id].keyinfo.alg = keyconf->alg;
1444 priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
1445 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
1446 keyconf->keylen);
1447
1448 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
1449 keyconf->keylen);
1450 priv->stations[sta_id].sta.key.key_flags = key_flags;
1451 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1452 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1453
1454 spin_unlock_irqrestore(&priv->sta_lock, flags);
1455
1456 IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
bb8c093b 1457 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY
1458 return 0;
1459}
1460
bb8c093b 1461static int iwl4965_clear_sta_key_info(struct iwl4965_priv *priv, u8 sta_id)
b481de9c
ZY
1462{
1463 unsigned long flags;
1464
1465 spin_lock_irqsave(&priv->sta_lock, flags);
bb8c093b
CH
1466 memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl4965_hw_key));
1467 memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl4965_keyinfo));
b481de9c
ZY
1468 priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
1469 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1470 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1471 spin_unlock_irqrestore(&priv->sta_lock, flags);
1472
1473 IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
bb8c093b 1474 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY
1475 return 0;
1476}
1477
bb8c093b 1478static void iwl4965_clear_free_frames(struct iwl4965_priv *priv)
b481de9c
ZY
1479{
1480 struct list_head *element;
1481
1482 IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
1483 priv->frames_count);
1484
1485 while (!list_empty(&priv->free_frames)) {
1486 element = priv->free_frames.next;
1487 list_del(element);
bb8c093b 1488 kfree(list_entry(element, struct iwl4965_frame, list));
b481de9c
ZY
1489 priv->frames_count--;
1490 }
1491
1492 if (priv->frames_count) {
1493 IWL_WARNING("%d frames still in use. Did we lose one?\n",
1494 priv->frames_count);
1495 priv->frames_count = 0;
1496 }
1497}
1498
bb8c093b 1499static struct iwl4965_frame *iwl4965_get_free_frame(struct iwl4965_priv *priv)
b481de9c 1500{
bb8c093b 1501 struct iwl4965_frame *frame;
b481de9c
ZY
1502 struct list_head *element;
1503 if (list_empty(&priv->free_frames)) {
1504 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
1505 if (!frame) {
1506 IWL_ERROR("Could not allocate frame!\n");
1507 return NULL;
1508 }
1509
1510 priv->frames_count++;
1511 return frame;
1512 }
1513
1514 element = priv->free_frames.next;
1515 list_del(element);
bb8c093b 1516 return list_entry(element, struct iwl4965_frame, list);
b481de9c
ZY
1517}
1518
bb8c093b 1519static void iwl4965_free_frame(struct iwl4965_priv *priv, struct iwl4965_frame *frame)
b481de9c
ZY
1520{
1521 memset(frame, 0, sizeof(*frame));
1522 list_add(&frame->list, &priv->free_frames);
1523}
1524
bb8c093b 1525unsigned int iwl4965_fill_beacon_frame(struct iwl4965_priv *priv,
b481de9c
ZY
1526 struct ieee80211_hdr *hdr,
1527 const u8 *dest, int left)
1528{
1529
bb8c093b 1530 if (!iwl4965_is_associated(priv) || !priv->ibss_beacon ||
b481de9c
ZY
1531 ((priv->iw_mode != IEEE80211_IF_TYPE_IBSS) &&
1532 (priv->iw_mode != IEEE80211_IF_TYPE_AP)))
1533 return 0;
1534
1535 if (priv->ibss_beacon->len > left)
1536 return 0;
1537
1538 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
1539
1540 return priv->ibss_beacon->len;
1541}
1542
bb8c093b 1543static u8 iwl4965_rate_get_lowest_plcp(int rate_mask)
b481de9c
ZY
1544{
1545 u8 i;
1546
1547 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
bb8c093b 1548 i = iwl4965_rates[i].next_ieee) {
b481de9c 1549 if (rate_mask & (1 << i))
bb8c093b 1550 return iwl4965_rates[i].plcp;
b481de9c
ZY
1551 }
1552
1553 return IWL_RATE_INVALID;
1554}
1555
bb8c093b 1556static int iwl4965_send_beacon_cmd(struct iwl4965_priv *priv)
b481de9c 1557{
bb8c093b 1558 struct iwl4965_frame *frame;
b481de9c
ZY
1559 unsigned int frame_size;
1560 int rc;
1561 u8 rate;
1562
bb8c093b 1563 frame = iwl4965_get_free_frame(priv);
b481de9c
ZY
1564
1565 if (!frame) {
1566 IWL_ERROR("Could not obtain free frame buffer for beacon "
1567 "command.\n");
1568 return -ENOMEM;
1569 }
1570
1571 if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) {
bb8c093b 1572 rate = iwl4965_rate_get_lowest_plcp(priv->active_rate_basic &
b481de9c
ZY
1573 0xFF0);
1574 if (rate == IWL_INVALID_RATE)
1575 rate = IWL_RATE_6M_PLCP;
1576 } else {
bb8c093b 1577 rate = iwl4965_rate_get_lowest_plcp(priv->active_rate_basic & 0xF);
b481de9c
ZY
1578 if (rate == IWL_INVALID_RATE)
1579 rate = IWL_RATE_1M_PLCP;
1580 }
1581
bb8c093b 1582 frame_size = iwl4965_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 1583
bb8c093b 1584 rc = iwl4965_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY
1585 &frame->u.cmd[0]);
1586
bb8c093b 1587 iwl4965_free_frame(priv, frame);
b481de9c
ZY
1588
1589 return rc;
1590}
1591
1592/******************************************************************************
1593 *
1594 * EEPROM related functions
1595 *
1596 ******************************************************************************/
1597
bb8c093b 1598static void get_eeprom_mac(struct iwl4965_priv *priv, u8 *mac)
b481de9c
ZY
1599{
1600 memcpy(mac, priv->eeprom.mac_address, 6);
1601}
1602
74a3a250
RC
1603static inline void iwl4965_eeprom_release_semaphore(struct iwl4965_priv *priv)
1604{
1605 iwl4965_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1606 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
1607}
1608
b481de9c 1609/**
bb8c093b 1610 * iwl4965_eeprom_init - read EEPROM contents
b481de9c 1611 *
6440adb5 1612 * Load the EEPROM contents from adapter into priv->eeprom
b481de9c
ZY
1613 *
1614 * NOTE: This routine uses the non-debug IO access functions.
1615 */
bb8c093b 1616int iwl4965_eeprom_init(struct iwl4965_priv *priv)
b481de9c 1617{
58ff6d4d 1618 u16 *e = (u16 *)&priv->eeprom;
bb8c093b 1619 u32 gp = iwl4965_read32(priv, CSR_EEPROM_GP);
b481de9c
ZY
1620 u32 r;
1621 int sz = sizeof(priv->eeprom);
1622 int rc;
1623 int i;
1624 u16 addr;
1625
1626 /* The EEPROM structure has several padding buffers within it
1627 * and when adding new EEPROM maps is subject to programmer errors
1628 * which may be very difficult to identify without explicitly
1629 * checking the resulting size of the eeprom map. */
1630 BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
1631
1632 if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
1633 IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp);
1634 return -ENOENT;
1635 }
1636
6440adb5 1637 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
bb8c093b 1638 rc = iwl4965_eeprom_acquire_semaphore(priv);
b481de9c 1639 if (rc < 0) {
91e17473 1640 IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
b481de9c
ZY
1641 return -ENOENT;
1642 }
1643
1644 /* eeprom is an array of 16bit values */
1645 for (addr = 0; addr < sz; addr += sizeof(u16)) {
bb8c093b
CH
1646 _iwl4965_write32(priv, CSR_EEPROM_REG, addr << 1);
1647 _iwl4965_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
b481de9c
ZY
1648
1649 for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
1650 i += IWL_EEPROM_ACCESS_DELAY) {
bb8c093b 1651 r = _iwl4965_read_direct32(priv, CSR_EEPROM_REG);
b481de9c
ZY
1652 if (r & CSR_EEPROM_REG_READ_VALID_MSK)
1653 break;
1654 udelay(IWL_EEPROM_ACCESS_DELAY);
1655 }
1656
1657 if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) {
1658 IWL_ERROR("Time out reading EEPROM[%d]", addr);
1659 rc = -ETIMEDOUT;
1660 goto done;
1661 }
58ff6d4d 1662 e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
b481de9c
ZY
1663 }
1664 rc = 0;
1665
1666done:
bb8c093b 1667 iwl4965_eeprom_release_semaphore(priv);
b481de9c
ZY
1668 return rc;
1669}
1670
1671/******************************************************************************
1672 *
1673 * Misc. internal state and helper functions
1674 *
1675 ******************************************************************************/
b481de9c 1676
bb8c093b 1677static void iwl4965_unset_hw_setting(struct iwl4965_priv *priv)
b481de9c
ZY
1678{
1679 if (priv->hw_setting.shared_virt)
1680 pci_free_consistent(priv->pci_dev,
bb8c093b 1681 sizeof(struct iwl4965_shared),
b481de9c
ZY
1682 priv->hw_setting.shared_virt,
1683 priv->hw_setting.shared_phys);
1684}
1685
1686/**
bb8c093b 1687 * iwl4965_supported_rate_to_ie - fill in the supported rate in IE field
b481de9c
ZY
1688 *
1689 * return : set the bit for each supported rate insert in ie
1690 */
bb8c093b 1691static u16 iwl4965_supported_rate_to_ie(u8 *ie, u16 supported_rate,
c7c46676 1692 u16 basic_rate, int *left)
b481de9c
ZY
1693{
1694 u16 ret_rates = 0, bit;
1695 int i;
c7c46676
TW
1696 u8 *cnt = ie;
1697 u8 *rates = ie + 1;
b481de9c
ZY
1698
1699 for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
1700 if (bit & supported_rate) {
1701 ret_rates |= bit;
bb8c093b 1702 rates[*cnt] = iwl4965_rates[i].ieee |
c7c46676
TW
1703 ((bit & basic_rate) ? 0x80 : 0x00);
1704 (*cnt)++;
1705 (*left)--;
1706 if ((*left <= 0) ||
1707 (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
b481de9c
ZY
1708 break;
1709 }
1710 }
1711
1712 return ret_rates;
1713}
1714
b481de9c 1715/**
bb8c093b 1716 * iwl4965_fill_probe_req - fill in all required fields and IE for probe request
b481de9c 1717 */
bb8c093b 1718static u16 iwl4965_fill_probe_req(struct iwl4965_priv *priv,
78330fdd
TW
1719 enum ieee80211_band band,
1720 struct ieee80211_mgmt *frame,
1721 int left, int is_direct)
b481de9c
ZY
1722{
1723 int len = 0;
1724 u8 *pos = NULL;
bee488db 1725 u16 active_rates, ret_rates, cck_rates, active_rate_basic;
8fb88032 1726#ifdef CONFIG_IWL4965_HT
78330fdd
TW
1727 const struct ieee80211_supported_band *sband =
1728 iwl4965_get_hw_mode(priv, band);
8fb88032 1729#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY
1730
1731 /* Make sure there is enough space for the probe request,
1732 * two mandatory IEs and the data */
1733 left -= 24;
1734 if (left < 0)
1735 return 0;
1736 len += 24;
1737
1738 frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
bb8c093b 1739 memcpy(frame->da, iwl4965_broadcast_addr, ETH_ALEN);
b481de9c 1740 memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
bb8c093b 1741 memcpy(frame->bssid, iwl4965_broadcast_addr, ETH_ALEN);
b481de9c
ZY
1742 frame->seq_ctrl = 0;
1743
1744 /* fill in our indirect SSID IE */
1745 /* ...next IE... */
1746
1747 left -= 2;
1748 if (left < 0)
1749 return 0;
1750 len += 2;
1751 pos = &(frame->u.probe_req.variable[0]);
1752 *pos++ = WLAN_EID_SSID;
1753 *pos++ = 0;
1754
1755 /* fill in our direct SSID IE... */
1756 if (is_direct) {
1757 /* ...next IE... */
1758 left -= 2 + priv->essid_len;
1759 if (left < 0)
1760 return 0;
1761 /* ... fill it in... */
1762 *pos++ = WLAN_EID_SSID;
1763 *pos++ = priv->essid_len;
1764 memcpy(pos, priv->essid, priv->essid_len);
1765 pos += priv->essid_len;
1766 len += 2 + priv->essid_len;
1767 }
1768
1769 /* fill in supported rate */
1770 /* ...next IE... */
1771 left -= 2;
1772 if (left < 0)
1773 return 0;
c7c46676 1774
b481de9c
ZY
1775 /* ... fill it in... */
1776 *pos++ = WLAN_EID_SUPP_RATES;
1777 *pos = 0;
c7c46676 1778
bee488db 1779 /* exclude 60M rate */
1780 active_rates = priv->rates_mask;
1781 active_rates &= ~IWL_RATE_60M_MASK;
1782
1783 active_rate_basic = active_rates & IWL_BASIC_RATES_MASK;
b481de9c 1784
c7c46676 1785 cck_rates = IWL_CCK_RATES_MASK & active_rates;
bb8c093b 1786 ret_rates = iwl4965_supported_rate_to_ie(pos, cck_rates,
bee488db 1787 active_rate_basic, &left);
c7c46676
TW
1788 active_rates &= ~ret_rates;
1789
bb8c093b 1790 ret_rates = iwl4965_supported_rate_to_ie(pos, active_rates,
bee488db 1791 active_rate_basic, &left);
c7c46676
TW
1792 active_rates &= ~ret_rates;
1793
b481de9c
ZY
1794 len += 2 + *pos;
1795 pos += (*pos) + 1;
c7c46676 1796 if (active_rates == 0)
b481de9c
ZY
1797 goto fill_end;
1798
1799 /* fill in supported extended rate */
1800 /* ...next IE... */
1801 left -= 2;
1802 if (left < 0)
1803 return 0;
1804 /* ... fill it in... */
1805 *pos++ = WLAN_EID_EXT_SUPP_RATES;
1806 *pos = 0;
bb8c093b 1807 iwl4965_supported_rate_to_ie(pos, active_rates,
bee488db 1808 active_rate_basic, &left);
b481de9c
ZY
1809 if (*pos > 0)
1810 len += 2 + *pos;
1811
c8b0e6e1 1812#ifdef CONFIG_IWL4965_HT
78330fdd
TW
1813 if (sband && sband->ht_info.ht_supported) {
1814 struct ieee80211_ht_cap *ht_cap;
b481de9c
ZY
1815 pos += (*pos) + 1;
1816 *pos++ = WLAN_EID_HT_CAPABILITY;
8fb88032 1817 *pos++ = sizeof(struct ieee80211_ht_cap);
78330fdd
TW
1818 ht_cap = (struct ieee80211_ht_cap *)pos;
1819 ht_cap->cap_info = cpu_to_le16(sband->ht_info.cap);
1820 memcpy(ht_cap->supp_mcs_set, sband->ht_info.supp_mcs_set, 16);
1821 ht_cap->ampdu_params_info =(sband->ht_info.ampdu_factor &
1822 IEEE80211_HT_CAP_AMPDU_FACTOR) |
1823 ((sband->ht_info.ampdu_density << 2) &
1824 IEEE80211_HT_CAP_AMPDU_DENSITY);
8fb88032 1825 len += 2 + sizeof(struct ieee80211_ht_cap);
b481de9c 1826 }
c8b0e6e1 1827#endif /*CONFIG_IWL4965_HT */
b481de9c
ZY
1828
1829 fill_end:
1830 return (u16)len;
1831}
1832
1833/*
1834 * QoS support
1835*/
bb8c093b
CH
1836static int iwl4965_send_qos_params_command(struct iwl4965_priv *priv,
1837 struct iwl4965_qosparam_cmd *qos)
b481de9c
ZY
1838{
1839
bb8c093b
CH
1840 return iwl4965_send_cmd_pdu(priv, REPLY_QOS_PARAM,
1841 sizeof(struct iwl4965_qosparam_cmd), qos);
b481de9c
ZY
1842}
1843
bb8c093b 1844static void iwl4965_reset_qos(struct iwl4965_priv *priv)
b481de9c
ZY
1845{
1846 u16 cw_min = 15;
1847 u16 cw_max = 1023;
1848 u8 aifs = 2;
1849 u8 is_legacy = 0;
1850 unsigned long flags;
1851 int i;
1852
1853 spin_lock_irqsave(&priv->lock, flags);
1854 priv->qos_data.qos_active = 0;
1855
1856 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
1857 if (priv->qos_data.qos_enable)
1858 priv->qos_data.qos_active = 1;
1859 if (!(priv->active_rate & 0xfff0)) {
1860 cw_min = 31;
1861 is_legacy = 1;
1862 }
1863 } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
1864 if (priv->qos_data.qos_enable)
1865 priv->qos_data.qos_active = 1;
1866 } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
1867 cw_min = 31;
1868 is_legacy = 1;
1869 }
1870
1871 if (priv->qos_data.qos_active)
1872 aifs = 3;
1873
1874 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
1875 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
1876 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
1877 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
1878 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
1879
1880 if (priv->qos_data.qos_active) {
1881 i = 1;
1882 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
1883 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
1884 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
1885 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
1886 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1887
1888 i = 2;
1889 priv->qos_data.def_qos_parm.ac[i].cw_min =
1890 cpu_to_le16((cw_min + 1) / 2 - 1);
1891 priv->qos_data.def_qos_parm.ac[i].cw_max =
1892 cpu_to_le16(cw_max);
1893 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1894 if (is_legacy)
1895 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1896 cpu_to_le16(6016);
1897 else
1898 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1899 cpu_to_le16(3008);
1900 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1901
1902 i = 3;
1903 priv->qos_data.def_qos_parm.ac[i].cw_min =
1904 cpu_to_le16((cw_min + 1) / 4 - 1);
1905 priv->qos_data.def_qos_parm.ac[i].cw_max =
1906 cpu_to_le16((cw_max + 1) / 2 - 1);
1907 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1908 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1909 if (is_legacy)
1910 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1911 cpu_to_le16(3264);
1912 else
1913 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1914 cpu_to_le16(1504);
1915 } else {
1916 for (i = 1; i < 4; i++) {
1917 priv->qos_data.def_qos_parm.ac[i].cw_min =
1918 cpu_to_le16(cw_min);
1919 priv->qos_data.def_qos_parm.ac[i].cw_max =
1920 cpu_to_le16(cw_max);
1921 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
1922 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
1923 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1924 }
1925 }
1926 IWL_DEBUG_QOS("set QoS to default \n");
1927
1928 spin_unlock_irqrestore(&priv->lock, flags);
1929}
1930
bb8c093b 1931static void iwl4965_activate_qos(struct iwl4965_priv *priv, u8 force)
b481de9c
ZY
1932{
1933 unsigned long flags;
1934
b481de9c
ZY
1935 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1936 return;
1937
1938 if (!priv->qos_data.qos_enable)
1939 return;
1940
1941 spin_lock_irqsave(&priv->lock, flags);
1942 priv->qos_data.def_qos_parm.qos_flags = 0;
1943
1944 if (priv->qos_data.qos_cap.q_AP.queue_request &&
1945 !priv->qos_data.qos_cap.q_AP.txop_request)
1946 priv->qos_data.def_qos_parm.qos_flags |=
1947 QOS_PARAM_FLG_TXOP_TYPE_MSK;
b481de9c
ZY
1948 if (priv->qos_data.qos_active)
1949 priv->qos_data.def_qos_parm.qos_flags |=
1950 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
1951
c8b0e6e1 1952#ifdef CONFIG_IWL4965_HT
fd105e79 1953 if (priv->current_ht_config.is_ht)
f1f1f5c7 1954 priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
c8b0e6e1 1955#endif /* CONFIG_IWL4965_HT */
f1f1f5c7 1956
b481de9c
ZY
1957 spin_unlock_irqrestore(&priv->lock, flags);
1958
bb8c093b 1959 if (force || iwl4965_is_associated(priv)) {
f1f1f5c7
TW
1960 IWL_DEBUG_QOS("send QoS cmd with Qos active=%d FLAGS=0x%X\n",
1961 priv->qos_data.qos_active,
1962 priv->qos_data.def_qos_parm.qos_flags);
b481de9c 1963
bb8c093b 1964 iwl4965_send_qos_params_command(priv,
b481de9c
ZY
1965 &(priv->qos_data.def_qos_parm));
1966 }
1967}
1968
b481de9c
ZY
1969/*
1970 * Power management (not Tx power!) functions
1971 */
1972#define MSEC_TO_USEC 1024
1973
1974#define NOSLP __constant_cpu_to_le16(0), 0, 0
1975#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
1976#define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
1977#define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
1978 __constant_cpu_to_le32(X1), \
1979 __constant_cpu_to_le32(X2), \
1980 __constant_cpu_to_le32(X3), \
1981 __constant_cpu_to_le32(X4)}
1982
1983
1984/* default power management (not Tx power) table values */
1985/* for tim 0-10 */
bb8c093b 1986static struct iwl4965_power_vec_entry range_0[IWL_POWER_AC] = {
b481de9c
ZY
1987 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1988 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
1989 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
1990 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
1991 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
1992 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
1993};
1994
1995/* for tim > 10 */
bb8c093b 1996static struct iwl4965_power_vec_entry range_1[IWL_POWER_AC] = {
b481de9c
ZY
1997 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1998 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
1999 SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
2000 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
2001 SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
2002 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
2003 SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
2004 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
2005 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
2006 SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
2007};
2008
bb8c093b 2009int iwl4965_power_init_handle(struct iwl4965_priv *priv)
b481de9c
ZY
2010{
2011 int rc = 0, i;
bb8c093b
CH
2012 struct iwl4965_power_mgr *pow_data;
2013 int size = sizeof(struct iwl4965_power_vec_entry) * IWL_POWER_AC;
b481de9c
ZY
2014 u16 pci_pm;
2015
2016 IWL_DEBUG_POWER("Initialize power \n");
2017
2018 pow_data = &(priv->power_data);
2019
2020 memset(pow_data, 0, sizeof(*pow_data));
2021
2022 pow_data->active_index = IWL_POWER_RANGE_0;
2023 pow_data->dtim_val = 0xffff;
2024
2025 memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
2026 memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
2027
2028 rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
2029 if (rc != 0)
2030 return 0;
2031 else {
bb8c093b 2032 struct iwl4965_powertable_cmd *cmd;
b481de9c
ZY
2033
2034 IWL_DEBUG_POWER("adjust power command flags\n");
2035
2036 for (i = 0; i < IWL_POWER_AC; i++) {
2037 cmd = &pow_data->pwr_range_0[i].cmd;
2038
2039 if (pci_pm & 0x1)
2040 cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
2041 else
2042 cmd->flags |= IWL_POWER_PCI_PM_MSK;
2043 }
2044 }
2045 return rc;
2046}
2047
bb8c093b
CH
2048static int iwl4965_update_power_cmd(struct iwl4965_priv *priv,
2049 struct iwl4965_powertable_cmd *cmd, u32 mode)
b481de9c
ZY
2050{
2051 int rc = 0, i;
2052 u8 skip;
2053 u32 max_sleep = 0;
bb8c093b 2054 struct iwl4965_power_vec_entry *range;
b481de9c 2055 u8 period = 0;
bb8c093b 2056 struct iwl4965_power_mgr *pow_data;
b481de9c
ZY
2057
2058 if (mode > IWL_POWER_INDEX_5) {
2059 IWL_DEBUG_POWER("Error invalid power mode \n");
2060 return -1;
2061 }
2062 pow_data = &(priv->power_data);
2063
2064 if (pow_data->active_index == IWL_POWER_RANGE_0)
2065 range = &pow_data->pwr_range_0[0];
2066 else
2067 range = &pow_data->pwr_range_1[1];
2068
bb8c093b 2069 memcpy(cmd, &range[mode].cmd, sizeof(struct iwl4965_powertable_cmd));
b481de9c
ZY
2070
2071#ifdef IWL_MAC80211_DISABLE
2072 if (priv->assoc_network != NULL) {
2073 unsigned long flags;
2074
2075 period = priv->assoc_network->tim.tim_period;
2076 }
2077#endif /*IWL_MAC80211_DISABLE */
2078 skip = range[mode].no_dtim;
2079
2080 if (period == 0) {
2081 period = 1;
2082 skip = 0;
2083 }
2084
2085 if (skip == 0) {
2086 max_sleep = period;
2087 cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
2088 } else {
2089 __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
2090 max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
2091 cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
2092 }
2093
2094 for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
2095 if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
2096 cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
2097 }
2098
2099 IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
2100 IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
2101 IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
2102 IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
2103 le32_to_cpu(cmd->sleep_interval[0]),
2104 le32_to_cpu(cmd->sleep_interval[1]),
2105 le32_to_cpu(cmd->sleep_interval[2]),
2106 le32_to_cpu(cmd->sleep_interval[3]),
2107 le32_to_cpu(cmd->sleep_interval[4]));
2108
2109 return rc;
2110}
2111
bb8c093b 2112static int iwl4965_send_power_mode(struct iwl4965_priv *priv, u32 mode)
b481de9c 2113{
9a62f73b 2114 u32 uninitialized_var(final_mode);
b481de9c 2115 int rc;
bb8c093b 2116 struct iwl4965_powertable_cmd cmd;
b481de9c
ZY
2117
2118 /* If on battery, set to 3,
01ebd063 2119 * if plugged into AC power, set to CAM ("continuously aware mode"),
b481de9c
ZY
2120 * else user level */
2121 switch (mode) {
2122 case IWL_POWER_BATTERY:
2123 final_mode = IWL_POWER_INDEX_3;
2124 break;
2125 case IWL_POWER_AC:
2126 final_mode = IWL_POWER_MODE_CAM;
2127 break;
2128 default:
2129 final_mode = mode;
2130 break;
2131 }
2132
2133 cmd.keep_alive_beacons = 0;
2134
bb8c093b 2135 iwl4965_update_power_cmd(priv, &cmd, final_mode);
b481de9c 2136
bb8c093b 2137 rc = iwl4965_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
b481de9c
ZY
2138
2139 if (final_mode == IWL_POWER_MODE_CAM)
2140 clear_bit(STATUS_POWER_PMI, &priv->status);
2141 else
2142 set_bit(STATUS_POWER_PMI, &priv->status);
2143
2144 return rc;
2145}
2146
bb8c093b 2147int iwl4965_is_network_packet(struct iwl4965_priv *priv, struct ieee80211_hdr *header)
b481de9c
ZY
2148{
2149 /* Filter incoming packets to determine if they are targeted toward
2150 * this network, discarding packets coming from ourselves */
2151 switch (priv->iw_mode) {
2152 case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */
2153 /* packets from our adapter are dropped (echo) */
2154 if (!compare_ether_addr(header->addr2, priv->mac_addr))
2155 return 0;
2156 /* {broad,multi}cast packets to our IBSS go through */
2157 if (is_multicast_ether_addr(header->addr1))
2158 return !compare_ether_addr(header->addr3, priv->bssid);
2159 /* packets to our adapter go through */
2160 return !compare_ether_addr(header->addr1, priv->mac_addr);
2161 case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */
2162 /* packets from our adapter are dropped (echo) */
2163 if (!compare_ether_addr(header->addr3, priv->mac_addr))
2164 return 0;
2165 /* {broad,multi}cast packets to our BSS go through */
2166 if (is_multicast_ether_addr(header->addr1))
2167 return !compare_ether_addr(header->addr2, priv->bssid);
2168 /* packets to our adapter go through */
2169 return !compare_ether_addr(header->addr1, priv->mac_addr);
2170 }
2171
2172 return 1;
2173}
2174
2175#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
2176
bb8c093b 2177static const char *iwl4965_get_tx_fail_reason(u32 status)
b481de9c
ZY
2178{
2179 switch (status & TX_STATUS_MSK) {
2180 case TX_STATUS_SUCCESS:
2181 return "SUCCESS";
2182 TX_STATUS_ENTRY(SHORT_LIMIT);
2183 TX_STATUS_ENTRY(LONG_LIMIT);
2184 TX_STATUS_ENTRY(FIFO_UNDERRUN);
2185 TX_STATUS_ENTRY(MGMNT_ABORT);
2186 TX_STATUS_ENTRY(NEXT_FRAG);
2187 TX_STATUS_ENTRY(LIFE_EXPIRE);
2188 TX_STATUS_ENTRY(DEST_PS);
2189 TX_STATUS_ENTRY(ABORTED);
2190 TX_STATUS_ENTRY(BT_RETRY);
2191 TX_STATUS_ENTRY(STA_INVALID);
2192 TX_STATUS_ENTRY(FRAG_DROPPED);
2193 TX_STATUS_ENTRY(TID_DISABLE);
2194 TX_STATUS_ENTRY(FRAME_FLUSHED);
2195 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
2196 TX_STATUS_ENTRY(TX_LOCKED);
2197 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
2198 }
2199
2200 return "UNKNOWN";
2201}
2202
2203/**
bb8c093b 2204 * iwl4965_scan_cancel - Cancel any currently executing HW scan
b481de9c
ZY
2205 *
2206 * NOTE: priv->mutex is not required before calling this function
2207 */
bb8c093b 2208static int iwl4965_scan_cancel(struct iwl4965_priv *priv)
b481de9c
ZY
2209{
2210 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
2211 clear_bit(STATUS_SCANNING, &priv->status);
2212 return 0;
2213 }
2214
2215 if (test_bit(STATUS_SCANNING, &priv->status)) {
2216 if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2217 IWL_DEBUG_SCAN("Queuing scan abort.\n");
2218 set_bit(STATUS_SCAN_ABORTING, &priv->status);
2219 queue_work(priv->workqueue, &priv->abort_scan);
2220
2221 } else
2222 IWL_DEBUG_SCAN("Scan abort already in progress.\n");
2223
2224 return test_bit(STATUS_SCANNING, &priv->status);
2225 }
2226
2227 return 0;
2228}
2229
2230/**
bb8c093b 2231 * iwl4965_scan_cancel_timeout - Cancel any currently executing HW scan
b481de9c
ZY
2232 * @ms: amount of time to wait (in milliseconds) for scan to abort
2233 *
2234 * NOTE: priv->mutex must be held before calling this function
2235 */
bb8c093b 2236static int iwl4965_scan_cancel_timeout(struct iwl4965_priv *priv, unsigned long ms)
b481de9c
ZY
2237{
2238 unsigned long now = jiffies;
2239 int ret;
2240
bb8c093b 2241 ret = iwl4965_scan_cancel(priv);
b481de9c
ZY
2242 if (ret && ms) {
2243 mutex_unlock(&priv->mutex);
2244 while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
2245 test_bit(STATUS_SCANNING, &priv->status))
2246 msleep(1);
2247 mutex_lock(&priv->mutex);
2248
2249 return test_bit(STATUS_SCANNING, &priv->status);
2250 }
2251
2252 return ret;
2253}
2254
bb8c093b 2255static void iwl4965_sequence_reset(struct iwl4965_priv *priv)
b481de9c
ZY
2256{
2257 /* Reset ieee stats */
2258
2259 /* We don't reset the net_device_stats (ieee->stats) on
2260 * re-association */
2261
2262 priv->last_seq_num = -1;
2263 priv->last_frag_num = -1;
2264 priv->last_packet_time = 0;
2265
bb8c093b 2266 iwl4965_scan_cancel(priv);
b481de9c
ZY
2267}
2268
2269#define MAX_UCODE_BEACON_INTERVAL 4096
2270#define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
2271
bb8c093b 2272static __le16 iwl4965_adjust_beacon_interval(u16 beacon_val)
b481de9c
ZY
2273{
2274 u16 new_val = 0;
2275 u16 beacon_factor = 0;
2276
2277 beacon_factor =
2278 (beacon_val + MAX_UCODE_BEACON_INTERVAL)
2279 / MAX_UCODE_BEACON_INTERVAL;
2280 new_val = beacon_val / beacon_factor;
2281
2282 return cpu_to_le16(new_val);
2283}
2284
bb8c093b 2285static void iwl4965_setup_rxon_timing(struct iwl4965_priv *priv)
b481de9c
ZY
2286{
2287 u64 interval_tm_unit;
2288 u64 tsf, result;
2289 unsigned long flags;
2290 struct ieee80211_conf *conf = NULL;
2291 u16 beacon_int = 0;
2292
2293 conf = ieee80211_get_hw_conf(priv->hw);
2294
2295 spin_lock_irqsave(&priv->lock, flags);
2296 priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
2297 priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
2298
2299 priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
2300
2301 tsf = priv->timestamp1;
2302 tsf = ((tsf << 32) | priv->timestamp0);
2303
2304 beacon_int = priv->beacon_int;
2305 spin_unlock_irqrestore(&priv->lock, flags);
2306
2307 if (priv->iw_mode == IEEE80211_IF_TYPE_STA) {
2308 if (beacon_int == 0) {
2309 priv->rxon_timing.beacon_interval = cpu_to_le16(100);
2310 priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
2311 } else {
2312 priv->rxon_timing.beacon_interval =
2313 cpu_to_le16(beacon_int);
2314 priv->rxon_timing.beacon_interval =
bb8c093b 2315 iwl4965_adjust_beacon_interval(
b481de9c
ZY
2316 le16_to_cpu(priv->rxon_timing.beacon_interval));
2317 }
2318
2319 priv->rxon_timing.atim_window = 0;
2320 } else {
2321 priv->rxon_timing.beacon_interval =
bb8c093b 2322 iwl4965_adjust_beacon_interval(conf->beacon_int);
b481de9c
ZY
2323 /* TODO: we need to get atim_window from upper stack
2324 * for now we set to 0 */
2325 priv->rxon_timing.atim_window = 0;
2326 }
2327
2328 interval_tm_unit =
2329 (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
2330 result = do_div(tsf, interval_tm_unit);
2331 priv->rxon_timing.beacon_init_val =
2332 cpu_to_le32((u32) ((u64) interval_tm_unit - result));
2333
2334 IWL_DEBUG_ASSOC
2335 ("beacon interval %d beacon timer %d beacon tim %d\n",
2336 le16_to_cpu(priv->rxon_timing.beacon_interval),
2337 le32_to_cpu(priv->rxon_timing.beacon_init_val),
2338 le16_to_cpu(priv->rxon_timing.atim_window));
2339}
2340
bb8c093b 2341static int iwl4965_scan_initiate(struct iwl4965_priv *priv)
b481de9c
ZY
2342{
2343 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
2344 IWL_ERROR("APs don't scan.\n");
2345 return 0;
2346 }
2347
bb8c093b 2348 if (!iwl4965_is_ready_rf(priv)) {
b481de9c
ZY
2349 IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
2350 return -EIO;
2351 }
2352
2353 if (test_bit(STATUS_SCANNING, &priv->status)) {
2354 IWL_DEBUG_SCAN("Scan already in progress.\n");
2355 return -EAGAIN;
2356 }
2357
2358 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2359 IWL_DEBUG_SCAN("Scan request while abort pending. "
2360 "Queuing.\n");
2361 return -EAGAIN;
2362 }
2363
2364 IWL_DEBUG_INFO("Starting scan...\n");
2365 priv->scan_bands = 2;
2366 set_bit(STATUS_SCANNING, &priv->status);
2367 priv->scan_start = jiffies;
2368 priv->scan_pass_start = priv->scan_start;
2369
2370 queue_work(priv->workqueue, &priv->request_scan);
2371
2372 return 0;
2373}
2374
bb8c093b 2375static int iwl4965_set_rxon_hwcrypto(struct iwl4965_priv *priv, int hw_decrypt)
b481de9c 2376{
bb8c093b 2377 struct iwl4965_rxon_cmd *rxon = &priv->staging_rxon;
b481de9c
ZY
2378
2379 if (hw_decrypt)
2380 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
2381 else
2382 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
2383
2384 return 0;
2385}
2386
8318d78a
JB
2387static void iwl4965_set_flags_for_phymode(struct iwl4965_priv *priv,
2388 enum ieee80211_band band)
b481de9c 2389{
8318d78a 2390 if (band == IEEE80211_BAND_5GHZ) {
b481de9c
ZY
2391 priv->staging_rxon.flags &=
2392 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
2393 | RXON_FLG_CCK_MSK);
2394 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2395 } else {
bb8c093b 2396 /* Copied from iwl4965_bg_post_associate() */
b481de9c
ZY
2397 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2398 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2399 else
2400 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2401
2402 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
2403 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2404
2405 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
2406 priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
2407 priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
2408 }
2409}
2410
2411/*
01ebd063 2412 * initialize rxon structure with default values from eeprom
b481de9c 2413 */
bb8c093b 2414static void iwl4965_connection_init_rx_config(struct iwl4965_priv *priv)
b481de9c 2415{
bb8c093b 2416 const struct iwl4965_channel_info *ch_info;
b481de9c
ZY
2417
2418 memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
2419
2420 switch (priv->iw_mode) {
2421 case IEEE80211_IF_TYPE_AP:
2422 priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
2423 break;
2424
2425 case IEEE80211_IF_TYPE_STA:
2426 priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
2427 priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
2428 break;
2429
2430 case IEEE80211_IF_TYPE_IBSS:
2431 priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
2432 priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
2433 priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
2434 RXON_FILTER_ACCEPT_GRP_MSK;
2435 break;
2436
2437 case IEEE80211_IF_TYPE_MNTR:
2438 priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
2439 priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
2440 RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
2441 break;
2442 }
2443
2444#if 0
2445 /* TODO: Figure out when short_preamble would be set and cache from
2446 * that */
2447 if (!hw_to_local(priv->hw)->short_preamble)
2448 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2449 else
2450 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2451#endif
2452
8318d78a 2453 ch_info = iwl4965_get_channel_info(priv, priv->band,
b481de9c
ZY
2454 le16_to_cpu(priv->staging_rxon.channel));
2455
2456 if (!ch_info)
2457 ch_info = &priv->channel_info[0];
2458
2459 /*
2460 * in some case A channels are all non IBSS
2461 * in this case force B/G channel
2462 */
2463 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
2464 !(is_channel_ibss(ch_info)))
2465 ch_info = &priv->channel_info[0];
2466
2467 priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
8318d78a 2468 priv->band = ch_info->band;
b481de9c 2469
8318d78a 2470 iwl4965_set_flags_for_phymode(priv, priv->band);
b481de9c
ZY
2471
2472 priv->staging_rxon.ofdm_basic_rates =
2473 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2474 priv->staging_rxon.cck_basic_rates =
2475 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2476
2477 priv->staging_rxon.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
2478 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
2479 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2480 memcpy(priv->staging_rxon.wlap_bssid_addr, priv->mac_addr, ETH_ALEN);
2481 priv->staging_rxon.ofdm_ht_single_stream_basic_rates = 0xff;
2482 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates = 0xff;
2483 iwl4965_set_rxon_chain(priv);
2484}
2485
bb8c093b 2486static int iwl4965_set_mode(struct iwl4965_priv *priv, int mode)
b481de9c 2487{
b481de9c 2488 if (mode == IEEE80211_IF_TYPE_IBSS) {
bb8c093b 2489 const struct iwl4965_channel_info *ch_info;
b481de9c 2490
bb8c093b 2491 ch_info = iwl4965_get_channel_info(priv,
8318d78a 2492 priv->band,
b481de9c
ZY
2493 le16_to_cpu(priv->staging_rxon.channel));
2494
2495 if (!ch_info || !is_channel_ibss(ch_info)) {
2496 IWL_ERROR("channel %d not IBSS channel\n",
2497 le16_to_cpu(priv->staging_rxon.channel));
2498 return -EINVAL;
2499 }
2500 }
2501
b481de9c
ZY
2502 priv->iw_mode = mode;
2503
bb8c093b 2504 iwl4965_connection_init_rx_config(priv);
b481de9c
ZY
2505 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2506
bb8c093b 2507 iwl4965_clear_stations_table(priv);
b481de9c 2508
fde3571f
MA
2509 /* dont commit rxon if rf-kill is on*/
2510 if (!iwl4965_is_ready_rf(priv))
2511 return -EAGAIN;
2512
2513 cancel_delayed_work(&priv->scan_check);
2514 if (iwl4965_scan_cancel_timeout(priv, 100)) {
2515 IWL_WARNING("Aborted scan still in progress after 100ms\n");
2516 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
2517 return -EAGAIN;
2518 }
2519
bb8c093b 2520 iwl4965_commit_rxon(priv);
b481de9c
ZY
2521
2522 return 0;
2523}
2524
bb8c093b 2525static void iwl4965_build_tx_cmd_hwcrypto(struct iwl4965_priv *priv,
b481de9c 2526 struct ieee80211_tx_control *ctl,
bb8c093b 2527 struct iwl4965_cmd *cmd,
b481de9c
ZY
2528 struct sk_buff *skb_frag,
2529 int last_frag)
2530{
bb8c093b 2531 struct iwl4965_hw_key *keyinfo = &priv->stations[ctl->key_idx].keyinfo;
b481de9c
ZY
2532
2533 switch (keyinfo->alg) {
2534 case ALG_CCMP:
2535 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
2536 memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
2537 IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
2538 break;
2539
2540 case ALG_TKIP:
2541#if 0
2542 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
2543
2544 if (last_frag)
2545 memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
2546 8);
2547 else
2548 memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
2549#endif
2550 break;
2551
2552 case ALG_WEP:
2553 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
2554 (ctl->key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
2555
2556 if (keyinfo->keylen == 13)
2557 cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
2558
2559 memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
2560
2561 IWL_DEBUG_TX("Configuring packet for WEP encryption "
2562 "with key %d\n", ctl->key_idx);
2563 break;
2564
b481de9c
ZY
2565 default:
2566 printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
2567 break;
2568 }
2569}
2570
2571/*
2572 * handle build REPLY_TX command notification.
2573 */
bb8c093b
CH
2574static void iwl4965_build_tx_cmd_basic(struct iwl4965_priv *priv,
2575 struct iwl4965_cmd *cmd,
b481de9c
ZY
2576 struct ieee80211_tx_control *ctrl,
2577 struct ieee80211_hdr *hdr,
2578 int is_unicast, u8 std_id)
2579{
2580 __le16 *qc;
2581 u16 fc = le16_to_cpu(hdr->frame_control);
2582 __le32 tx_flags = cmd->cmd.tx.tx_flags;
2583
2584 cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2585 if (!(ctrl->flags & IEEE80211_TXCTL_NO_ACK)) {
2586 tx_flags |= TX_CMD_FLG_ACK_MSK;
2587 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
2588 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2589 if (ieee80211_is_probe_response(fc) &&
2590 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
2591 tx_flags |= TX_CMD_FLG_TSF_MSK;
2592 } else {
2593 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
2594 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2595 }
2596
87e4f7df
TW
2597 if (ieee80211_is_back_request(fc))
2598 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
2599
2600
b481de9c
ZY
2601 cmd->cmd.tx.sta_id = std_id;
2602 if (ieee80211_get_morefrag(hdr))
2603 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
2604
2605 qc = ieee80211_get_qos_ctrl(hdr);
2606 if (qc) {
2607 cmd->cmd.tx.tid_tspec = (u8) (le16_to_cpu(*qc) & 0xf);
2608 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
2609 } else
2610 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2611
2612 if (ctrl->flags & IEEE80211_TXCTL_USE_RTS_CTS) {
2613 tx_flags |= TX_CMD_FLG_RTS_MSK;
2614 tx_flags &= ~TX_CMD_FLG_CTS_MSK;
2615 } else if (ctrl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) {
2616 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2617 tx_flags |= TX_CMD_FLG_CTS_MSK;
2618 }
2619
2620 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
2621 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
2622
2623 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
2624 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) {
2625 if ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_REQ ||
2626 (fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_REASSOC_REQ)
bc434dd2 2627 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
b481de9c 2628 else
bc434dd2 2629 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
b481de9c
ZY
2630 } else
2631 cmd->cmd.tx.timeout.pm_frame_timeout = 0;
2632
2633 cmd->cmd.tx.driver_txop = 0;
2634 cmd->cmd.tx.tx_flags = tx_flags;
2635 cmd->cmd.tx.next_frame_len = 0;
2636}
2637
6440adb5
CB
2638/**
2639 * iwl4965_get_sta_id - Find station's index within station table
2640 *
2641 * If new IBSS station, create new entry in station table
2642 */
9fbab516
BC
2643static int iwl4965_get_sta_id(struct iwl4965_priv *priv,
2644 struct ieee80211_hdr *hdr)
b481de9c
ZY
2645{
2646 int sta_id;
2647 u16 fc = le16_to_cpu(hdr->frame_control);
0795af57 2648 DECLARE_MAC_BUF(mac);
b481de9c 2649
6440adb5 2650 /* If this frame is broadcast or management, use broadcast station id */
b481de9c
ZY
2651 if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
2652 is_multicast_ether_addr(hdr->addr1))
2653 return priv->hw_setting.bcast_sta_id;
2654
2655 switch (priv->iw_mode) {
2656
6440adb5
CB
2657 /* If we are a client station in a BSS network, use the special
2658 * AP station entry (that's the only station we communicate with) */
b481de9c
ZY
2659 case IEEE80211_IF_TYPE_STA:
2660 return IWL_AP_ID;
2661
2662 /* If we are an AP, then find the station, or use BCAST */
2663 case IEEE80211_IF_TYPE_AP:
bb8c093b 2664 sta_id = iwl4965_hw_find_station(priv, hdr->addr1);
b481de9c
ZY
2665 if (sta_id != IWL_INVALID_STATION)
2666 return sta_id;
2667 return priv->hw_setting.bcast_sta_id;
2668
6440adb5
CB
2669 /* If this frame is going out to an IBSS network, find the station,
2670 * or create a new station table entry */
b481de9c 2671 case IEEE80211_IF_TYPE_IBSS:
bb8c093b 2672 sta_id = iwl4965_hw_find_station(priv, hdr->addr1);
b481de9c
ZY
2673 if (sta_id != IWL_INVALID_STATION)
2674 return sta_id;
2675
6440adb5 2676 /* Create new station table entry */
67d62035
RR
2677 sta_id = iwl4965_add_station_flags(priv, hdr->addr1,
2678 0, CMD_ASYNC, NULL);
b481de9c
ZY
2679
2680 if (sta_id != IWL_INVALID_STATION)
2681 return sta_id;
2682
0795af57 2683 IWL_DEBUG_DROP("Station %s not in station map. "
b481de9c 2684 "Defaulting to broadcast...\n",
0795af57 2685 print_mac(mac, hdr->addr1));
bb8c093b 2686 iwl4965_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
b481de9c
ZY
2687 return priv->hw_setting.bcast_sta_id;
2688
2689 default:
01ebd063 2690 IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode);
b481de9c
ZY
2691 return priv->hw_setting.bcast_sta_id;
2692 }
2693}
2694
2695/*
2696 * start REPLY_TX command process
2697 */
bb8c093b 2698static int iwl4965_tx_skb(struct iwl4965_priv *priv,
b481de9c
ZY
2699 struct sk_buff *skb, struct ieee80211_tx_control *ctl)
2700{
2701 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
bb8c093b 2702 struct iwl4965_tfd_frame *tfd;
b481de9c
ZY
2703 u32 *control_flags;
2704 int txq_id = ctl->queue;
bb8c093b
CH
2705 struct iwl4965_tx_queue *txq = NULL;
2706 struct iwl4965_queue *q = NULL;
b481de9c
ZY
2707 dma_addr_t phys_addr;
2708 dma_addr_t txcmd_phys;
87e4f7df 2709 dma_addr_t scratch_phys;
bb8c093b 2710 struct iwl4965_cmd *out_cmd = NULL;
b481de9c
ZY
2711 u16 len, idx, len_org;
2712 u8 id, hdr_len, unicast;
2713 u8 sta_id;
2714 u16 seq_number = 0;
2715 u16 fc;
2716 __le16 *qc;
2717 u8 wait_write_ptr = 0;
2718 unsigned long flags;
2719 int rc;
2720
2721 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2722 if (iwl4965_is_rfkill(priv)) {
b481de9c
ZY
2723 IWL_DEBUG_DROP("Dropping - RF KILL\n");
2724 goto drop_unlock;
2725 }
2726
32bfd35d
JB
2727 if (!priv->vif) {
2728 IWL_DEBUG_DROP("Dropping - !priv->vif\n");
b481de9c
ZY
2729 goto drop_unlock;
2730 }
2731
8318d78a 2732 if ((ctl->tx_rate->hw_value & 0xFF) == IWL_INVALID_RATE) {
b481de9c
ZY
2733 IWL_ERROR("ERROR: No TX rate available.\n");
2734 goto drop_unlock;
2735 }
2736
2737 unicast = !is_multicast_ether_addr(hdr->addr1);
2738 id = 0;
2739
2740 fc = le16_to_cpu(hdr->frame_control);
2741
c8b0e6e1 2742#ifdef CONFIG_IWL4965_DEBUG
b481de9c
ZY
2743 if (ieee80211_is_auth(fc))
2744 IWL_DEBUG_TX("Sending AUTH frame\n");
2745 else if (ieee80211_is_assoc_request(fc))
2746 IWL_DEBUG_TX("Sending ASSOC frame\n");
2747 else if (ieee80211_is_reassoc_request(fc))
2748 IWL_DEBUG_TX("Sending REASSOC frame\n");
2749#endif
2750
7878a5a4 2751 /* drop all data frame if we are not associated */
76f3915b
GG
2752 if (((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA) &&
2753 (!iwl4965_is_associated(priv) ||
a6477249 2754 ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && !priv->assoc_id) ||
76f3915b 2755 !priv->assoc_station_added)) {
bb8c093b 2756 IWL_DEBUG_DROP("Dropping - !iwl4965_is_associated\n");
b481de9c
ZY
2757 goto drop_unlock;
2758 }
2759
2760 spin_unlock_irqrestore(&priv->lock, flags);
2761
2762 hdr_len = ieee80211_get_hdrlen(fc);
6440adb5
CB
2763
2764 /* Find (or create) index into station table for destination station */
bb8c093b 2765 sta_id = iwl4965_get_sta_id(priv, hdr);
b481de9c 2766 if (sta_id == IWL_INVALID_STATION) {
0795af57
JP
2767 DECLARE_MAC_BUF(mac);
2768
2769 IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
2770 print_mac(mac, hdr->addr1));
b481de9c
ZY
2771 goto drop;
2772 }
2773
2774 IWL_DEBUG_RATE("station Id %d\n", sta_id);
2775
2776 qc = ieee80211_get_qos_ctrl(hdr);
2777 if (qc) {
2778 u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
2779 seq_number = priv->stations[sta_id].tid[tid].seq_number &
2780 IEEE80211_SCTL_SEQ;
2781 hdr->seq_ctrl = cpu_to_le16(seq_number) |
2782 (hdr->seq_ctrl &
2783 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
2784 seq_number += 0x10;
c8b0e6e1 2785#ifdef CONFIG_IWL4965_HT
b481de9c 2786 /* aggregation is on for this <sta,tid> */
fe01b477 2787 if (ctl->flags & IEEE80211_TXCTL_AMPDU)
b481de9c 2788 txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
fe01b477 2789 priv->stations[sta_id].tid[tid].tfds_in_queue++;
c8b0e6e1 2790#endif /* CONFIG_IWL4965_HT */
b481de9c 2791 }
6440adb5
CB
2792
2793 /* Descriptor for chosen Tx queue */
b481de9c
ZY
2794 txq = &priv->txq[txq_id];
2795 q = &txq->q;
2796
2797 spin_lock_irqsave(&priv->lock, flags);
2798
6440adb5 2799 /* Set up first empty TFD within this queue's circular TFD buffer */
fc4b6853 2800 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY
2801 memset(tfd, 0, sizeof(*tfd));
2802 control_flags = (u32 *) tfd;
fc4b6853 2803 idx = get_cmd_index(q, q->write_ptr, 0);
b481de9c 2804
6440adb5 2805 /* Set up driver data for this TFD */
bb8c093b 2806 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl4965_tx_info));
fc4b6853
TW
2807 txq->txb[q->write_ptr].skb[0] = skb;
2808 memcpy(&(txq->txb[q->write_ptr].status.control),
b481de9c 2809 ctl, sizeof(struct ieee80211_tx_control));
6440adb5
CB
2810
2811 /* Set up first empty entry in queue's array of Tx/cmd buffers */
b481de9c
ZY
2812 out_cmd = &txq->cmd[idx];
2813 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
2814 memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
6440adb5
CB
2815
2816 /*
2817 * Set up the Tx-command (not MAC!) header.
2818 * Store the chosen Tx queue and TFD index within the sequence field;
2819 * after Tx, uCode's Tx response will return this value so driver can
2820 * locate the frame within the tx queue and do post-tx processing.
2821 */
b481de9c
ZY
2822 out_cmd->hdr.cmd = REPLY_TX;
2823 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
fc4b6853 2824 INDEX_TO_SEQ(q->write_ptr)));
6440adb5
CB
2825
2826 /* Copy MAC header from skb into command buffer */
b481de9c
ZY
2827 memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
2828
6440adb5
CB
2829 /*
2830 * Use the first empty entry in this queue's command buffer array
2831 * to contain the Tx command and MAC header concatenated together
2832 * (payload data will be in another buffer).
2833 * Size of this varies, due to varying MAC header length.
2834 * If end is not dword aligned, we'll have 2 extra bytes at the end
2835 * of the MAC header (device reads on dword boundaries).
2836 * We'll tell device about this padding later.
2837 */
b481de9c 2838 len = priv->hw_setting.tx_cmd_len +
bb8c093b 2839 sizeof(struct iwl4965_cmd_header) + hdr_len;
b481de9c
ZY
2840
2841 len_org = len;
2842 len = (len + 3) & ~3;
2843
2844 if (len_org != len)
2845 len_org = 1;
2846 else
2847 len_org = 0;
2848
6440adb5
CB
2849 /* Physical address of this Tx command's header (not MAC header!),
2850 * within command buffer array. */
bb8c093b
CH
2851 txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl4965_cmd) * idx +
2852 offsetof(struct iwl4965_cmd, hdr);
b481de9c 2853
6440adb5
CB
2854 /* Add buffer containing Tx command and MAC(!) header to TFD's
2855 * first entry */
bb8c093b 2856 iwl4965_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
b481de9c
ZY
2857
2858 if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT))
bb8c093b 2859 iwl4965_build_tx_cmd_hwcrypto(priv, ctl, out_cmd, skb, 0);
b481de9c 2860
6440adb5
CB
2861 /* Set up TFD's 2nd entry to point directly to remainder of skb,
2862 * if any (802.11 null frames have no payload). */
b481de9c
ZY
2863 len = skb->len - hdr_len;
2864 if (len) {
2865 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
2866 len, PCI_DMA_TODEVICE);
bb8c093b 2867 iwl4965_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
b481de9c
ZY
2868 }
2869
6440adb5 2870 /* Tell 4965 about any 2-byte padding after MAC header */
b481de9c
ZY
2871 if (len_org)
2872 out_cmd->cmd.tx.tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
2873
6440adb5 2874 /* Total # bytes to be transmitted */
b481de9c
ZY
2875 len = (u16)skb->len;
2876 out_cmd->cmd.tx.len = cpu_to_le16(len);
2877
2878 /* TODO need this for burst mode later on */
bb8c093b 2879 iwl4965_build_tx_cmd_basic(priv, out_cmd, ctl, hdr, unicast, sta_id);
b481de9c
ZY
2880
2881 /* set is_hcca to 0; it probably will never be implemented */
bb8c093b 2882 iwl4965_hw_build_tx_cmd_rate(priv, out_cmd, ctl, hdr, sta_id, 0);
b481de9c 2883
87e4f7df
TW
2884 scratch_phys = txcmd_phys + sizeof(struct iwl4965_cmd_header) +
2885 offsetof(struct iwl4965_tx_cmd, scratch);
2886 out_cmd->cmd.tx.dram_lsb_ptr = cpu_to_le32(scratch_phys);
2887 out_cmd->cmd.tx.dram_msb_ptr = iwl_get_dma_hi_address(scratch_phys);
2888
b481de9c
ZY
2889 if (!ieee80211_get_morefrag(hdr)) {
2890 txq->need_update = 1;
2891 if (qc) {
2892 u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
2893 priv->stations[sta_id].tid[tid].seq_number = seq_number;
2894 }
2895 } else {
2896 wait_write_ptr = 1;
2897 txq->need_update = 0;
2898 }
2899
bb8c093b 2900 iwl4965_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
b481de9c
ZY
2901 sizeof(out_cmd->cmd.tx));
2902
bb8c093b 2903 iwl4965_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
b481de9c
ZY
2904 ieee80211_get_hdrlen(fc));
2905
6440adb5 2906 /* Set up entry for this TFD in Tx byte-count array */
b481de9c
ZY
2907 iwl4965_tx_queue_update_wr_ptr(priv, txq, len);
2908
6440adb5 2909 /* Tell device the write index *just past* this latest filled TFD */
bb8c093b
CH
2910 q->write_ptr = iwl4965_queue_inc_wrap(q->write_ptr, q->n_bd);
2911 rc = iwl4965_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY
2912 spin_unlock_irqrestore(&priv->lock, flags);
2913
2914 if (rc)
2915 return rc;
2916
bb8c093b 2917 if ((iwl4965_queue_space(q) < q->high_mark)
b481de9c
ZY
2918 && priv->mac80211_registered) {
2919 if (wait_write_ptr) {
2920 spin_lock_irqsave(&priv->lock, flags);
2921 txq->need_update = 1;
bb8c093b 2922 iwl4965_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY
2923 spin_unlock_irqrestore(&priv->lock, flags);
2924 }
2925
2926 ieee80211_stop_queue(priv->hw, ctl->queue);
2927 }
2928
2929 return 0;
2930
2931drop_unlock:
2932 spin_unlock_irqrestore(&priv->lock, flags);
2933drop:
2934 return -1;
2935}
2936
bb8c093b 2937static void iwl4965_set_rate(struct iwl4965_priv *priv)
b481de9c 2938{
8318d78a 2939 const struct ieee80211_supported_band *hw = NULL;
b481de9c
ZY
2940 struct ieee80211_rate *rate;
2941 int i;
2942
8318d78a 2943 hw = iwl4965_get_hw_mode(priv, priv->band);
c4ba9621
SA
2944 if (!hw) {
2945 IWL_ERROR("Failed to set rate: unable to get hw mode\n");
2946 return;
2947 }
b481de9c
ZY
2948
2949 priv->active_rate = 0;
2950 priv->active_rate_basic = 0;
2951
8318d78a
JB
2952 for (i = 0; i < hw->n_bitrates; i++) {
2953 rate = &(hw->bitrates[i]);
2954 if (rate->hw_value < IWL_RATE_COUNT)
2955 priv->active_rate |= (1 << rate->hw_value);
b481de9c
ZY
2956 }
2957
2958 IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
2959 priv->active_rate, priv->active_rate_basic);
2960
2961 /*
2962 * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
2963 * otherwise set it to the default of all CCK rates and 6, 12, 24 for
2964 * OFDM
2965 */
2966 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
2967 priv->staging_rxon.cck_basic_rates =
2968 ((priv->active_rate_basic &
2969 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
2970 else
2971 priv->staging_rxon.cck_basic_rates =
2972 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2973
2974 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
2975 priv->staging_rxon.ofdm_basic_rates =
2976 ((priv->active_rate_basic &
2977 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
2978 IWL_FIRST_OFDM_RATE) & 0xFF;
2979 else
2980 priv->staging_rxon.ofdm_basic_rates =
2981 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2982}
2983
bb8c093b 2984static void iwl4965_radio_kill_sw(struct iwl4965_priv *priv, int disable_radio)
b481de9c
ZY
2985{
2986 unsigned long flags;
2987
2988 if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
2989 return;
2990
2991 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
2992 disable_radio ? "OFF" : "ON");
2993
2994 if (disable_radio) {
bb8c093b 2995 iwl4965_scan_cancel(priv);
b481de9c
ZY
2996 /* FIXME: This is a workaround for AP */
2997 if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
2998 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2999 iwl4965_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
3000 CSR_UCODE_SW_BIT_RFKILL);
3001 spin_unlock_irqrestore(&priv->lock, flags);
bb8c093b 3002 iwl4965_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
b481de9c
ZY
3003 set_bit(STATUS_RF_KILL_SW, &priv->status);
3004 }
3005 return;
3006 }
3007
3008 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 3009 iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
3010
3011 clear_bit(STATUS_RF_KILL_SW, &priv->status);
3012 spin_unlock_irqrestore(&priv->lock, flags);
3013
3014 /* wake up ucode */
3015 msleep(10);
3016
3017 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH
3018 iwl4965_read32(priv, CSR_UCODE_DRV_GP1);
3019 if (!iwl4965_grab_nic_access(priv))
3020 iwl4965_release_nic_access(priv);
b481de9c
ZY
3021 spin_unlock_irqrestore(&priv->lock, flags);
3022
3023 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
3024 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
3025 "disabled by HW switch\n");
3026 return;
3027 }
3028
3029 queue_work(priv->workqueue, &priv->restart);
3030 return;
3031}
3032
bb8c093b 3033void iwl4965_set_decrypted_flag(struct iwl4965_priv *priv, struct sk_buff *skb,
b481de9c
ZY
3034 u32 decrypt_res, struct ieee80211_rx_status *stats)
3035{
3036 u16 fc =
3037 le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
3038
3039 if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
3040 return;
3041
3042 if (!(fc & IEEE80211_FCTL_PROTECTED))
3043 return;
3044
3045 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
3046 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
3047 case RX_RES_STATUS_SEC_TYPE_TKIP:
3048 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
3049 RX_RES_STATUS_BAD_ICV_MIC)
3050 stats->flag |= RX_FLAG_MMIC_ERROR;
3051 case RX_RES_STATUS_SEC_TYPE_WEP:
3052 case RX_RES_STATUS_SEC_TYPE_CCMP:
3053 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
3054 RX_RES_STATUS_DECRYPT_OK) {
3055 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
3056 stats->flag |= RX_FLAG_DECRYPTED;
3057 }
3058 break;
3059
3060 default:
3061 break;
3062 }
3063}
3064
b481de9c
ZY
3065
3066#define IWL_PACKET_RETRY_TIME HZ
3067
bb8c093b 3068int iwl4965_is_duplicate_packet(struct iwl4965_priv *priv, struct ieee80211_hdr *header)
b481de9c
ZY
3069{
3070 u16 sc = le16_to_cpu(header->seq_ctrl);
3071 u16 seq = (sc & IEEE80211_SCTL_SEQ) >> 4;
3072 u16 frag = sc & IEEE80211_SCTL_FRAG;
3073 u16 *last_seq, *last_frag;
3074 unsigned long *last_time;
3075
3076 switch (priv->iw_mode) {
3077 case IEEE80211_IF_TYPE_IBSS:{
3078 struct list_head *p;
bb8c093b 3079 struct iwl4965_ibss_seq *entry = NULL;
b481de9c
ZY
3080 u8 *mac = header->addr2;
3081 int index = mac[5] & (IWL_IBSS_MAC_HASH_SIZE - 1);
3082
3083 __list_for_each(p, &priv->ibss_mac_hash[index]) {
bb8c093b 3084 entry = list_entry(p, struct iwl4965_ibss_seq, list);
b481de9c
ZY
3085 if (!compare_ether_addr(entry->mac, mac))
3086 break;
3087 }
3088 if (p == &priv->ibss_mac_hash[index]) {
3089 entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
3090 if (!entry) {
bc434dd2 3091 IWL_ERROR("Cannot malloc new mac entry\n");
b481de9c
ZY
3092 return 0;
3093 }
3094 memcpy(entry->mac, mac, ETH_ALEN);
3095 entry->seq_num = seq;
3096 entry->frag_num = frag;
3097 entry->packet_time = jiffies;
bc434dd2 3098 list_add(&entry->list, &priv->ibss_mac_hash[index]);
b481de9c
ZY
3099 return 0;
3100 }
3101 last_seq = &entry->seq_num;
3102 last_frag = &entry->frag_num;
3103 last_time = &entry->packet_time;
3104 break;
3105 }
3106 case IEEE80211_IF_TYPE_STA:
3107 last_seq = &priv->last_seq_num;
3108 last_frag = &priv->last_frag_num;
3109 last_time = &priv->last_packet_time;
3110 break;
3111 default:
3112 return 0;
3113 }
3114 if ((*last_seq == seq) &&
3115 time_after(*last_time + IWL_PACKET_RETRY_TIME, jiffies)) {
3116 if (*last_frag == frag)
3117 goto drop;
3118 if (*last_frag + 1 != frag)
3119 /* out-of-order fragment */
3120 goto drop;
3121 } else
3122 *last_seq = seq;
3123
3124 *last_frag = frag;
3125 *last_time = jiffies;
3126 return 0;
3127
3128 drop:
3129 return 1;
3130}
3131
c8b0e6e1 3132#ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT
b481de9c
ZY
3133
3134#include "iwl-spectrum.h"
3135
3136#define BEACON_TIME_MASK_LOW 0x00FFFFFF
3137#define BEACON_TIME_MASK_HIGH 0xFF000000
3138#define TIME_UNIT 1024
3139
3140/*
3141 * extended beacon time format
3142 * time in usec will be changed into a 32-bit value in 8:24 format
3143 * the high 1 byte is the beacon counts
3144 * the lower 3 bytes is the time in usec within one beacon interval
3145 */
3146
bb8c093b 3147static u32 iwl4965_usecs_to_beacons(u32 usec, u32 beacon_interval)
b481de9c
ZY
3148{
3149 u32 quot;
3150 u32 rem;
3151 u32 interval = beacon_interval * 1024;
3152
3153 if (!interval || !usec)
3154 return 0;
3155
3156 quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
3157 rem = (usec % interval) & BEACON_TIME_MASK_LOW;
3158
3159 return (quot << 24) + rem;
3160}
3161
3162/* base is usually what we get from ucode with each received frame,
3163 * the same as HW timer counter counting down
3164 */
3165
bb8c093b 3166static __le32 iwl4965_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
b481de9c
ZY
3167{
3168 u32 base_low = base & BEACON_TIME_MASK_LOW;
3169 u32 addon_low = addon & BEACON_TIME_MASK_LOW;
3170 u32 interval = beacon_interval * TIME_UNIT;
3171 u32 res = (base & BEACON_TIME_MASK_HIGH) +
3172 (addon & BEACON_TIME_MASK_HIGH);
3173
3174 if (base_low > addon_low)
3175 res += base_low - addon_low;
3176 else if (base_low < addon_low) {
3177 res += interval + base_low - addon_low;
3178 res += (1 << 24);
3179 } else
3180 res += (1 << 24);
3181
3182 return cpu_to_le32(res);
3183}
3184
bb8c093b 3185static int iwl4965_get_measurement(struct iwl4965_priv *priv,
b481de9c
ZY
3186 struct ieee80211_measurement_params *params,
3187 u8 type)
3188{
bb8c093b
CH
3189 struct iwl4965_spectrum_cmd spectrum;
3190 struct iwl4965_rx_packet *res;
3191 struct iwl4965_host_cmd cmd = {
b481de9c
ZY
3192 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
3193 .data = (void *)&spectrum,
3194 .meta.flags = CMD_WANT_SKB,
3195 };
3196 u32 add_time = le64_to_cpu(params->start_time);
3197 int rc;
3198 int spectrum_resp_status;
3199 int duration = le16_to_cpu(params->duration);
3200
bb8c093b 3201 if (iwl4965_is_associated(priv))
b481de9c 3202 add_time =
bb8c093b 3203 iwl4965_usecs_to_beacons(
b481de9c
ZY
3204 le64_to_cpu(params->start_time) - priv->last_tsf,
3205 le16_to_cpu(priv->rxon_timing.beacon_interval));
3206
3207 memset(&spectrum, 0, sizeof(spectrum));
3208
3209 spectrum.channel_count = cpu_to_le16(1);
3210 spectrum.flags =
3211 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
3212 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
3213 cmd.len = sizeof(spectrum);
3214 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
3215
bb8c093b 3216 if (iwl4965_is_associated(priv))
b481de9c 3217 spectrum.start_time =
bb8c093b 3218 iwl4965_add_beacon_time(priv->last_beacon_time,
b481de9c
ZY
3219 add_time,
3220 le16_to_cpu(priv->rxon_timing.beacon_interval));
3221 else
3222 spectrum.start_time = 0;
3223
3224 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
3225 spectrum.channels[0].channel = params->channel;
3226 spectrum.channels[0].type = type;
3227 if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
3228 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
3229 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
3230
bb8c093b 3231 rc = iwl4965_send_cmd_sync(priv, &cmd);
b481de9c
ZY
3232 if (rc)
3233 return rc;
3234
bb8c093b 3235 res = (struct iwl4965_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY
3236 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
3237 IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
3238 rc = -EIO;
3239 }
3240
3241 spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
3242 switch (spectrum_resp_status) {
3243 case 0: /* Command will be handled */
3244 if (res->u.spectrum.id != 0xff) {
3245 IWL_DEBUG_INFO
3246 ("Replaced existing measurement: %d\n",
3247 res->u.spectrum.id);
3248 priv->measurement_status &= ~MEASUREMENT_READY;
3249 }
3250 priv->measurement_status |= MEASUREMENT_ACTIVE;
3251 rc = 0;
3252 break;
3253
3254 case 1: /* Command will not be handled */
3255 rc = -EAGAIN;
3256 break;
3257 }
3258
3259 dev_kfree_skb_any(cmd.meta.u.skb);
3260
3261 return rc;
3262}
3263#endif
3264
bb8c093b
CH
3265static void iwl4965_txstatus_to_ieee(struct iwl4965_priv *priv,
3266 struct iwl4965_tx_info *tx_sta)
b481de9c
ZY
3267{
3268
3269 tx_sta->status.ack_signal = 0;
3270 tx_sta->status.excessive_retries = 0;
3271 tx_sta->status.queue_length = 0;
3272 tx_sta->status.queue_number = 0;
3273
3274 if (in_interrupt())
3275 ieee80211_tx_status_irqsafe(priv->hw,
3276 tx_sta->skb[0], &(tx_sta->status));
3277 else
3278 ieee80211_tx_status(priv->hw,
3279 tx_sta->skb[0], &(tx_sta->status));
3280
3281 tx_sta->skb[0] = NULL;
3282}
3283
3284/**
6440adb5 3285 * iwl4965_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
b481de9c 3286 *
6440adb5
CB
3287 * When FW advances 'R' index, all entries between old and new 'R' index
3288 * need to be reclaimed. As result, some free space forms. If there is
3289 * enough free space (> low mark), wake the stack that feeds us.
b481de9c 3290 */
bb8c093b 3291int iwl4965_tx_queue_reclaim(struct iwl4965_priv *priv, int txq_id, int index)
b481de9c 3292{
bb8c093b
CH
3293 struct iwl4965_tx_queue *txq = &priv->txq[txq_id];
3294 struct iwl4965_queue *q = &txq->q;
b481de9c
ZY
3295 int nfreed = 0;
3296
3297 if ((index >= q->n_bd) || (x2_queue_used(q, index) == 0)) {
3298 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
3299 "is out of range [0-%d] %d %d.\n", txq_id,
fc4b6853 3300 index, q->n_bd, q->write_ptr, q->read_ptr);
b481de9c
ZY
3301 return 0;
3302 }
3303
bb8c093b 3304 for (index = iwl4965_queue_inc_wrap(index, q->n_bd);
fc4b6853 3305 q->read_ptr != index;
bb8c093b 3306 q->read_ptr = iwl4965_queue_inc_wrap(q->read_ptr, q->n_bd)) {
b481de9c 3307 if (txq_id != IWL_CMD_QUEUE_NUM) {
bb8c093b 3308 iwl4965_txstatus_to_ieee(priv,
fc4b6853 3309 &(txq->txb[txq->q.read_ptr]));
bb8c093b 3310 iwl4965_hw_txq_free_tfd(priv, txq);
b481de9c
ZY
3311 } else if (nfreed > 1) {
3312 IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
fc4b6853 3313 q->write_ptr, q->read_ptr);
b481de9c
ZY
3314 queue_work(priv->workqueue, &priv->restart);
3315 }
3316 nfreed++;
3317 }
3318
fe01b477 3319/* if (iwl4965_queue_space(q) > q->low_mark && (txq_id >= 0) &&
b481de9c
ZY
3320 (txq_id != IWL_CMD_QUEUE_NUM) &&
3321 priv->mac80211_registered)
fe01b477 3322 ieee80211_wake_queue(priv->hw, txq_id); */
b481de9c
ZY
3323
3324
3325 return nfreed;
3326}
3327
bb8c093b 3328static int iwl4965_is_tx_success(u32 status)
b481de9c
ZY
3329{
3330 status &= TX_STATUS_MSK;
3331 return (status == TX_STATUS_SUCCESS)
3332 || (status == TX_STATUS_DIRECT_DONE);
3333}
3334
3335/******************************************************************************
3336 *
3337 * Generic RX handler implementations
3338 *
3339 ******************************************************************************/
c8b0e6e1 3340#ifdef CONFIG_IWL4965_HT
b481de9c 3341
bb8c093b 3342static inline int iwl4965_get_ra_sta_id(struct iwl4965_priv *priv,
b481de9c
ZY
3343 struct ieee80211_hdr *hdr)
3344{
3345 if (priv->iw_mode == IEEE80211_IF_TYPE_STA)
3346 return IWL_AP_ID;
3347 else {
3348 u8 *da = ieee80211_get_DA(hdr);
bb8c093b 3349 return iwl4965_hw_find_station(priv, da);
b481de9c
ZY
3350 }
3351}
3352
bb8c093b
CH
3353static struct ieee80211_hdr *iwl4965_tx_queue_get_hdr(
3354 struct iwl4965_priv *priv, int txq_id, int idx)
b481de9c
ZY
3355{
3356 if (priv->txq[txq_id].txb[idx].skb[0])
3357 return (struct ieee80211_hdr *)priv->txq[txq_id].
3358 txb[idx].skb[0]->data;
3359 return NULL;
3360}
3361
bb8c093b 3362static inline u32 iwl4965_get_scd_ssn(struct iwl4965_tx_resp *tx_resp)
b481de9c
ZY
3363{
3364 __le32 *scd_ssn = (__le32 *)((u32 *)&tx_resp->status +
3365 tx_resp->frame_count);
3366 return le32_to_cpu(*scd_ssn) & MAX_SN;
3367
3368}
6440adb5
CB
3369
3370/**
3371 * iwl4965_tx_status_reply_tx - Handle Tx rspnse for frames in aggregation queue
3372 */
bb8c093b
CH
3373static int iwl4965_tx_status_reply_tx(struct iwl4965_priv *priv,
3374 struct iwl4965_ht_agg *agg,
fe01b477 3375 struct iwl4965_tx_resp_agg *tx_resp,
b481de9c
ZY
3376 u16 start_idx)
3377{
fe01b477
RR
3378 u16 status;
3379 struct agg_tx_status *frame_status = &tx_resp->status;
b481de9c
ZY
3380 struct ieee80211_tx_status *tx_status = NULL;
3381 struct ieee80211_hdr *hdr = NULL;
3382 int i, sh;
3383 int txq_id, idx;
3384 u16 seq;
3385
3386 if (agg->wait_for_ba)
6440adb5 3387 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
b481de9c
ZY
3388
3389 agg->frame_count = tx_resp->frame_count;
3390 agg->start_idx = start_idx;
3391 agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
fe01b477 3392 agg->bitmap = 0;
b481de9c 3393
6440adb5 3394 /* # frames attempted by Tx command */
b481de9c 3395 if (agg->frame_count == 1) {
6440adb5 3396 /* Only one frame was attempted; no block-ack will arrive */
fe01b477
RR
3397 status = le16_to_cpu(frame_status[0].status);
3398 seq = le16_to_cpu(frame_status[0].sequence);
3399 idx = SEQ_TO_INDEX(seq);
3400 txq_id = SEQ_TO_QUEUE(seq);
b481de9c 3401
b481de9c 3402 /* FIXME: code repetition */
fe01b477
RR
3403 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
3404 agg->frame_count, agg->start_idx, idx);
b481de9c 3405
fe01b477 3406 tx_status = &(priv->txq[txq_id].txb[idx].status);
b481de9c
ZY
3407 tx_status->retry_count = tx_resp->failure_frame;
3408 tx_status->queue_number = status & 0xff;
fe01b477
RR
3409 tx_status->queue_length = tx_resp->failure_rts;
3410 tx_status->control.flags &= ~IEEE80211_TXCTL_AMPDU;
bb8c093b 3411 tx_status->flags = iwl4965_is_tx_success(status)?
b481de9c 3412 IEEE80211_TX_STATUS_ACK : 0;
4c424e4c
RR
3413 iwl4965_hwrate_to_tx_control(priv,
3414 le32_to_cpu(tx_resp->rate_n_flags),
3415 &tx_status->control);
b481de9c
ZY
3416 /* FIXME: code repetition end */
3417
3418 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
3419 status & 0xff, tx_resp->failure_frame);
3420 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n",
bb8c093b 3421 iwl4965_hw_get_rate_n_flags(tx_resp->rate_n_flags));
b481de9c
ZY
3422
3423 agg->wait_for_ba = 0;
3424 } else {
6440adb5 3425 /* Two or more frames were attempted; expect block-ack */
b481de9c
ZY
3426 u64 bitmap = 0;
3427 int start = agg->start_idx;
3428
6440adb5 3429 /* Construct bit-map of pending frames within Tx window */
b481de9c
ZY
3430 for (i = 0; i < agg->frame_count; i++) {
3431 u16 sc;
fe01b477
RR
3432 status = le16_to_cpu(frame_status[i].status);
3433 seq = le16_to_cpu(frame_status[i].sequence);
b481de9c
ZY
3434 idx = SEQ_TO_INDEX(seq);
3435 txq_id = SEQ_TO_QUEUE(seq);
3436
3437 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
3438 AGG_TX_STATE_ABORT_MSK))
3439 continue;
3440
3441 IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
3442 agg->frame_count, txq_id, idx);
3443
bb8c093b 3444 hdr = iwl4965_tx_queue_get_hdr(priv, txq_id, idx);
b481de9c
ZY
3445
3446 sc = le16_to_cpu(hdr->seq_ctrl);
3447 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
3448 IWL_ERROR("BUG_ON idx doesn't match seq control"
3449 " idx=%d, seq_idx=%d, seq=%d\n",
3450 idx, SEQ_TO_SN(sc),
3451 hdr->seq_ctrl);
3452 return -1;
3453 }
3454
3455 IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
3456 i, idx, SEQ_TO_SN(sc));
3457
3458 sh = idx - start;
3459 if (sh > 64) {
3460 sh = (start - idx) + 0xff;
3461 bitmap = bitmap << sh;
3462 sh = 0;
3463 start = idx;
3464 } else if (sh < -64)
3465 sh = 0xff - (start - idx);
3466 else if (sh < 0) {
3467 sh = start - idx;
3468 start = idx;
3469 bitmap = bitmap << sh;
3470 sh = 0;
3471 }
3472 bitmap |= (1 << sh);
3473 IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%x\n",
3474 start, (u32)(bitmap & 0xFFFFFFFF));
3475 }
3476
fe01b477 3477 agg->bitmap = bitmap;
b481de9c
ZY
3478 agg->start_idx = start;
3479 agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
fe01b477 3480 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
b481de9c 3481 agg->frame_count, agg->start_idx,
fe01b477 3482 agg->bitmap);
b481de9c
ZY
3483
3484 if (bitmap)
3485 agg->wait_for_ba = 1;
3486 }
3487 return 0;
3488}
3489#endif
b481de9c 3490
6440adb5
CB
3491/**
3492 * iwl4965_rx_reply_tx - Handle standard (non-aggregation) Tx response
3493 */
bb8c093b
CH
3494static void iwl4965_rx_reply_tx(struct iwl4965_priv *priv,
3495 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3496{
bb8c093b 3497 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY
3498 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3499 int txq_id = SEQ_TO_QUEUE(sequence);
3500 int index = SEQ_TO_INDEX(sequence);
bb8c093b 3501 struct iwl4965_tx_queue *txq = &priv->txq[txq_id];
b481de9c 3502 struct ieee80211_tx_status *tx_status;
bb8c093b 3503 struct iwl4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
b481de9c 3504 u32 status = le32_to_cpu(tx_resp->status);
c8b0e6e1 3505#ifdef CONFIG_IWL4965_HT
fe01b477
RR
3506 int tid = MAX_TID_COUNT, sta_id = IWL_INVALID_STATION;
3507 struct ieee80211_hdr *hdr;
3508 __le16 *qc;
b481de9c
ZY
3509#endif
3510
3511 if ((index >= txq->q.n_bd) || (x2_queue_used(&txq->q, index) == 0)) {
3512 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
3513 "is out of range [0-%d] %d %d\n", txq_id,
fc4b6853
TW
3514 index, txq->q.n_bd, txq->q.write_ptr,
3515 txq->q.read_ptr);
b481de9c
ZY
3516 return;
3517 }
3518
c8b0e6e1 3519#ifdef CONFIG_IWL4965_HT
fe01b477
RR
3520 hdr = iwl4965_tx_queue_get_hdr(priv, txq_id, index);
3521 qc = ieee80211_get_qos_ctrl(hdr);
3522
3523 if (qc)
3524 tid = le16_to_cpu(*qc) & 0xf;
3525
3526 sta_id = iwl4965_get_ra_sta_id(priv, hdr);
3527 if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) {
3528 IWL_ERROR("Station not known\n");
3529 return;
3530 }
3531
b481de9c 3532 if (txq->sched_retry) {
bb8c093b 3533 const u32 scd_ssn = iwl4965_get_scd_ssn(tx_resp);
bb8c093b 3534 struct iwl4965_ht_agg *agg = NULL;
b481de9c 3535
fe01b477 3536 if (!qc)
b481de9c 3537 return;
b481de9c
ZY
3538
3539 agg = &priv->stations[sta_id].tid[tid].agg;
3540
fe01b477
RR
3541 iwl4965_tx_status_reply_tx(priv, agg,
3542 (struct iwl4965_tx_resp_agg *)tx_resp, index);
b481de9c
ZY
3543
3544 if ((tx_resp->frame_count == 1) &&
bb8c093b 3545 !iwl4965_is_tx_success(status)) {
b481de9c
ZY
3546 /* TODO: send BAR */
3547 }
3548
fe01b477
RR
3549 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
3550 int freed;
bb8c093b 3551 index = iwl4965_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
b481de9c
ZY
3552 IWL_DEBUG_TX_REPLY("Retry scheduler reclaim scd_ssn "
3553 "%d index %d\n", scd_ssn , index);
fe01b477
RR
3554 freed = iwl4965_tx_queue_reclaim(priv, txq_id, index);
3555 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
3556
3557 if (iwl4965_queue_space(&txq->q) > txq->q.low_mark &&
3558 txq_id >= 0 && priv->mac80211_registered &&
3559 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
3560 ieee80211_wake_queue(priv->hw, txq_id);
3561
3562 iwl4965_check_empty_hw_queue(priv, sta_id, tid, txq_id);
b481de9c
ZY
3563 }
3564 } else {
c8b0e6e1 3565#endif /* CONFIG_IWL4965_HT */
fc4b6853 3566 tx_status = &(txq->txb[txq->q.read_ptr].status);
b481de9c
ZY
3567
3568 tx_status->retry_count = tx_resp->failure_frame;
3569 tx_status->queue_number = status;
3570 tx_status->queue_length = tx_resp->bt_kill_count;
3571 tx_status->queue_length |= tx_resp->failure_rts;
b481de9c 3572 tx_status->flags =
bb8c093b 3573 iwl4965_is_tx_success(status) ? IEEE80211_TX_STATUS_ACK : 0;
4c424e4c
RR
3574 iwl4965_hwrate_to_tx_control(priv, le32_to_cpu(tx_resp->rate_n_flags),
3575 &tx_status->control);
b481de9c 3576
b481de9c 3577 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) rate_n_flags 0x%x "
bb8c093b 3578 "retries %d\n", txq_id, iwl4965_get_tx_fail_reason(status),
b481de9c
ZY
3579 status, le32_to_cpu(tx_resp->rate_n_flags),
3580 tx_resp->failure_frame);
3581
3582 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
fe01b477
RR
3583 if (index != -1) {
3584 int freed = iwl4965_tx_queue_reclaim(priv, txq_id, index);
3585#ifdef CONFIG_IWL4965_HT
3586 if (tid != MAX_TID_COUNT)
3587 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
3588 if (iwl4965_queue_space(&txq->q) > txq->q.low_mark &&
3589 (txq_id >= 0) &&
3590 priv->mac80211_registered)
3591 ieee80211_wake_queue(priv->hw, txq_id);
3592 if (tid != MAX_TID_COUNT)
3593 iwl4965_check_empty_hw_queue(priv, sta_id, tid, txq_id);
3594#endif
3595 }
c8b0e6e1 3596#ifdef CONFIG_IWL4965_HT
b481de9c 3597 }
c8b0e6e1 3598#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY
3599
3600 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
3601 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
3602}
3603
3604
bb8c093b
CH
3605static void iwl4965_rx_reply_alive(struct iwl4965_priv *priv,
3606 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3607{
bb8c093b
CH
3608 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3609 struct iwl4965_alive_resp *palive;
b481de9c
ZY
3610 struct delayed_work *pwork;
3611
3612 palive = &pkt->u.alive_frame;
3613
3614 IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
3615 "0x%01X 0x%01X\n",
3616 palive->is_valid, palive->ver_type,
3617 palive->ver_subtype);
3618
3619 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
3620 IWL_DEBUG_INFO("Initialization Alive received.\n");
3621 memcpy(&priv->card_alive_init,
3622 &pkt->u.alive_frame,
bb8c093b 3623 sizeof(struct iwl4965_init_alive_resp));
b481de9c
ZY
3624 pwork = &priv->init_alive_start;
3625 } else {
3626 IWL_DEBUG_INFO("Runtime Alive received.\n");
3627 memcpy(&priv->card_alive, &pkt->u.alive_frame,
bb8c093b 3628 sizeof(struct iwl4965_alive_resp));
b481de9c
ZY
3629 pwork = &priv->alive_start;
3630 }
3631
3632 /* We delay the ALIVE response by 5ms to
3633 * give the HW RF Kill time to activate... */
3634 if (palive->is_valid == UCODE_VALID_OK)
3635 queue_delayed_work(priv->workqueue, pwork,
3636 msecs_to_jiffies(5));
3637 else
3638 IWL_WARNING("uCode did not respond OK.\n");
3639}
3640
bb8c093b
CH
3641static void iwl4965_rx_reply_add_sta(struct iwl4965_priv *priv,
3642 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3643{
bb8c093b 3644 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY
3645
3646 IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
3647 return;
3648}
3649
bb8c093b
CH
3650static void iwl4965_rx_reply_error(struct iwl4965_priv *priv,
3651 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3652{
bb8c093b 3653 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY
3654
3655 IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
3656 "seq 0x%04X ser 0x%08X\n",
3657 le32_to_cpu(pkt->u.err_resp.error_type),
3658 get_cmd_string(pkt->u.err_resp.cmd_id),
3659 pkt->u.err_resp.cmd_id,
3660 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
3661 le32_to_cpu(pkt->u.err_resp.error_info));
3662}
3663
3664#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
3665
bb8c093b 3666static void iwl4965_rx_csa(struct iwl4965_priv *priv, struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3667{
bb8c093b
CH
3668 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3669 struct iwl4965_rxon_cmd *rxon = (void *)&priv->active_rxon;
3670 struct iwl4965_csa_notification *csa = &(pkt->u.csa_notif);
b481de9c
ZY
3671 IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
3672 le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
3673 rxon->channel = csa->channel;
3674 priv->staging_rxon.channel = csa->channel;
3675}
3676
bb8c093b
CH
3677static void iwl4965_rx_spectrum_measure_notif(struct iwl4965_priv *priv,
3678 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3679{
c8b0e6e1 3680#ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT
bb8c093b
CH
3681 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3682 struct iwl4965_spectrum_notification *report = &(pkt->u.spectrum_notif);
b481de9c
ZY
3683
3684 if (!report->state) {
3685 IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
3686 "Spectrum Measure Notification: Start\n");
3687 return;
3688 }
3689
3690 memcpy(&priv->measure_report, report, sizeof(*report));
3691 priv->measurement_status |= MEASUREMENT_READY;
3692#endif
3693}
3694
bb8c093b
CH
3695static void iwl4965_rx_pm_sleep_notif(struct iwl4965_priv *priv,
3696 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3697{
c8b0e6e1 3698#ifdef CONFIG_IWL4965_DEBUG
bb8c093b
CH
3699 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3700 struct iwl4965_sleep_notification *sleep = &(pkt->u.sleep_notif);
b481de9c
ZY
3701 IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
3702 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
3703#endif
3704}
3705
bb8c093b
CH
3706static void iwl4965_rx_pm_debug_statistics_notif(struct iwl4965_priv *priv,
3707 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3708{
bb8c093b 3709 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY
3710 IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
3711 "notification for %s:\n",
3712 le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
bb8c093b 3713 iwl4965_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
b481de9c
ZY
3714}
3715
bb8c093b 3716static void iwl4965_bg_beacon_update(struct work_struct *work)
b481de9c 3717{
bb8c093b
CH
3718 struct iwl4965_priv *priv =
3719 container_of(work, struct iwl4965_priv, beacon_update);
b481de9c
ZY
3720 struct sk_buff *beacon;
3721
3722 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
32bfd35d 3723 beacon = ieee80211_beacon_get(priv->hw, priv->vif, NULL);
b481de9c
ZY
3724
3725 if (!beacon) {
3726 IWL_ERROR("update beacon failed\n");
3727 return;
3728 }
3729
3730 mutex_lock(&priv->mutex);
3731 /* new beacon skb is allocated every time; dispose previous.*/
3732 if (priv->ibss_beacon)
3733 dev_kfree_skb(priv->ibss_beacon);
3734
3735 priv->ibss_beacon = beacon;
3736 mutex_unlock(&priv->mutex);
3737
bb8c093b 3738 iwl4965_send_beacon_cmd(priv);
b481de9c
ZY
3739}
3740
bb8c093b
CH
3741static void iwl4965_rx_beacon_notif(struct iwl4965_priv *priv,
3742 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3743{
c8b0e6e1 3744#ifdef CONFIG_IWL4965_DEBUG
bb8c093b
CH
3745 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3746 struct iwl4965_beacon_notif *beacon = &(pkt->u.beacon_status);
3747 u8 rate = iwl4965_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
b481de9c
ZY
3748
3749 IWL_DEBUG_RX("beacon status %x retries %d iss %d "
3750 "tsf %d %d rate %d\n",
3751 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
3752 beacon->beacon_notify_hdr.failure_frame,
3753 le32_to_cpu(beacon->ibss_mgr_status),
3754 le32_to_cpu(beacon->high_tsf),
3755 le32_to_cpu(beacon->low_tsf), rate);
3756#endif
3757
3758 if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
3759 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
3760 queue_work(priv->workqueue, &priv->beacon_update);
3761}
3762
3763/* Service response to REPLY_SCAN_CMD (0x80) */
bb8c093b
CH
3764static void iwl4965_rx_reply_scan(struct iwl4965_priv *priv,
3765 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3766{
c8b0e6e1 3767#ifdef CONFIG_IWL4965_DEBUG
bb8c093b
CH
3768 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3769 struct iwl4965_scanreq_notification *notif =
3770 (struct iwl4965_scanreq_notification *)pkt->u.raw;
b481de9c
ZY
3771
3772 IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
3773#endif
3774}
3775
3776/* Service SCAN_START_NOTIFICATION (0x82) */
bb8c093b
CH
3777static void iwl4965_rx_scan_start_notif(struct iwl4965_priv *priv,
3778 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3779{
bb8c093b
CH
3780 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3781 struct iwl4965_scanstart_notification *notif =
3782 (struct iwl4965_scanstart_notification *)pkt->u.raw;
b481de9c
ZY
3783 priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
3784 IWL_DEBUG_SCAN("Scan start: "
3785 "%d [802.11%s] "
3786 "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
3787 notif->channel,
3788 notif->band ? "bg" : "a",
3789 notif->tsf_high,
3790 notif->tsf_low, notif->status, notif->beacon_timer);
3791}
3792
3793/* Service SCAN_RESULTS_NOTIFICATION (0x83) */
bb8c093b
CH
3794static void iwl4965_rx_scan_results_notif(struct iwl4965_priv *priv,
3795 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3796{
bb8c093b
CH
3797 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3798 struct iwl4965_scanresults_notification *notif =
3799 (struct iwl4965_scanresults_notification *)pkt->u.raw;
b481de9c
ZY
3800
3801 IWL_DEBUG_SCAN("Scan ch.res: "
3802 "%d [802.11%s] "
3803 "(TSF: 0x%08X:%08X) - %d "
3804 "elapsed=%lu usec (%dms since last)\n",
3805 notif->channel,
3806 notif->band ? "bg" : "a",
3807 le32_to_cpu(notif->tsf_high),
3808 le32_to_cpu(notif->tsf_low),
3809 le32_to_cpu(notif->statistics[0]),
3810 le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
3811 jiffies_to_msecs(elapsed_jiffies
3812 (priv->last_scan_jiffies, jiffies)));
3813
3814 priv->last_scan_jiffies = jiffies;
7878a5a4 3815 priv->next_scan_jiffies = 0;
b481de9c
ZY
3816}
3817
3818/* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
bb8c093b
CH
3819static void iwl4965_rx_scan_complete_notif(struct iwl4965_priv *priv,
3820 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3821{
bb8c093b
CH
3822 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3823 struct iwl4965_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
b481de9c
ZY
3824
3825 IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
3826 scan_notif->scanned_channels,
3827 scan_notif->tsf_low,
3828 scan_notif->tsf_high, scan_notif->status);
3829
3830 /* The HW is no longer scanning */
3831 clear_bit(STATUS_SCAN_HW, &priv->status);
3832
3833 /* The scan completion notification came in, so kill that timer... */
3834 cancel_delayed_work(&priv->scan_check);
3835
3836 IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
3837 (priv->scan_bands == 2) ? "2.4" : "5.2",
3838 jiffies_to_msecs(elapsed_jiffies
3839 (priv->scan_pass_start, jiffies)));
3840
3841 /* Remove this scanned band from the list
3842 * of pending bands to scan */
3843 priv->scan_bands--;
3844
3845 /* If a request to abort was given, or the scan did not succeed
3846 * then we reset the scan state machine and terminate,
3847 * re-queuing another scan if one has been requested */
3848 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
3849 IWL_DEBUG_INFO("Aborted scan completed.\n");
3850 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
3851 } else {
3852 /* If there are more bands on this scan pass reschedule */
3853 if (priv->scan_bands > 0)
3854 goto reschedule;
3855 }
3856
3857 priv->last_scan_jiffies = jiffies;
7878a5a4 3858 priv->next_scan_jiffies = 0;
b481de9c
ZY
3859 IWL_DEBUG_INFO("Setting scan to off\n");
3860
3861 clear_bit(STATUS_SCANNING, &priv->status);
3862
3863 IWL_DEBUG_INFO("Scan took %dms\n",
3864 jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
3865
3866 queue_work(priv->workqueue, &priv->scan_completed);
3867
3868 return;
3869
3870reschedule:
3871 priv->scan_pass_start = jiffies;
3872 queue_work(priv->workqueue, &priv->request_scan);
3873}
3874
3875/* Handle notification from uCode that card's power state is changing
3876 * due to software, hardware, or critical temperature RFKILL */
bb8c093b
CH
3877static void iwl4965_rx_card_state_notif(struct iwl4965_priv *priv,
3878 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3879{
bb8c093b 3880 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY
3881 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
3882 unsigned long status = priv->status;
3883
3884 IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
3885 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3886 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
3887
3888 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
3889 RF_CARD_DISABLED)) {
3890
bb8c093b 3891 iwl4965_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
3892 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3893
bb8c093b
CH
3894 if (!iwl4965_grab_nic_access(priv)) {
3895 iwl4965_write_direct32(
b481de9c
ZY
3896 priv, HBUS_TARG_MBX_C,
3897 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
3898
bb8c093b 3899 iwl4965_release_nic_access(priv);
b481de9c
ZY
3900 }
3901
3902 if (!(flags & RXON_CARD_DISABLED)) {
bb8c093b 3903 iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c 3904 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
bb8c093b
CH
3905 if (!iwl4965_grab_nic_access(priv)) {
3906 iwl4965_write_direct32(
b481de9c
ZY
3907 priv, HBUS_TARG_MBX_C,
3908 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
3909
bb8c093b 3910 iwl4965_release_nic_access(priv);
b481de9c
ZY
3911 }
3912 }
3913
3914 if (flags & RF_CARD_DISABLED) {
bb8c093b 3915 iwl4965_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c 3916 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
bb8c093b
CH
3917 iwl4965_read32(priv, CSR_UCODE_DRV_GP1);
3918 if (!iwl4965_grab_nic_access(priv))
3919 iwl4965_release_nic_access(priv);
b481de9c
ZY
3920 }
3921 }
3922
3923 if (flags & HW_CARD_DISABLED)
3924 set_bit(STATUS_RF_KILL_HW, &priv->status);
3925 else
3926 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3927
3928
3929 if (flags & SW_CARD_DISABLED)
3930 set_bit(STATUS_RF_KILL_SW, &priv->status);
3931 else
3932 clear_bit(STATUS_RF_KILL_SW, &priv->status);
3933
3934 if (!(flags & RXON_CARD_DISABLED))
bb8c093b 3935 iwl4965_scan_cancel(priv);
b481de9c
ZY
3936
3937 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
3938 test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
3939 (test_bit(STATUS_RF_KILL_SW, &status) !=
3940 test_bit(STATUS_RF_KILL_SW, &priv->status)))
3941 queue_work(priv->workqueue, &priv->rf_kill);
3942 else
3943 wake_up_interruptible(&priv->wait_command_queue);
3944}
3945
3946/**
bb8c093b 3947 * iwl4965_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY
3948 *
3949 * Setup the RX handlers for each of the reply types sent from the uCode
3950 * to the host.
3951 *
3952 * This function chains into the hardware specific files for them to setup
3953 * any hardware specific handlers as well.
3954 */
bb8c093b 3955static void iwl4965_setup_rx_handlers(struct iwl4965_priv *priv)
b481de9c 3956{
bb8c093b
CH
3957 priv->rx_handlers[REPLY_ALIVE] = iwl4965_rx_reply_alive;
3958 priv->rx_handlers[REPLY_ADD_STA] = iwl4965_rx_reply_add_sta;
3959 priv->rx_handlers[REPLY_ERROR] = iwl4965_rx_reply_error;
3960 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl4965_rx_csa;
b481de9c 3961 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
bb8c093b
CH
3962 iwl4965_rx_spectrum_measure_notif;
3963 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl4965_rx_pm_sleep_notif;
b481de9c 3964 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
bb8c093b
CH
3965 iwl4965_rx_pm_debug_statistics_notif;
3966 priv->rx_handlers[BEACON_NOTIFICATION] = iwl4965_rx_beacon_notif;
b481de9c 3967
9fbab516
BC
3968 /*
3969 * The same handler is used for both the REPLY to a discrete
3970 * statistics request from the host as well as for the periodic
3971 * statistics notifications (after received beacons) from the uCode.
b481de9c 3972 */
bb8c093b
CH
3973 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl4965_hw_rx_statistics;
3974 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl4965_hw_rx_statistics;
b481de9c 3975
bb8c093b
CH
3976 priv->rx_handlers[REPLY_SCAN_CMD] = iwl4965_rx_reply_scan;
3977 priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl4965_rx_scan_start_notif;
b481de9c 3978 priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
bb8c093b 3979 iwl4965_rx_scan_results_notif;
b481de9c 3980 priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
bb8c093b
CH
3981 iwl4965_rx_scan_complete_notif;
3982 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl4965_rx_card_state_notif;
3983 priv->rx_handlers[REPLY_TX] = iwl4965_rx_reply_tx;
b481de9c 3984
9fbab516 3985 /* Set up hardware specific Rx handlers */
bb8c093b 3986 iwl4965_hw_rx_handler_setup(priv);
b481de9c
ZY
3987}
3988
3989/**
bb8c093b 3990 * iwl4965_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
b481de9c
ZY
3991 * @rxb: Rx buffer to reclaim
3992 *
3993 * If an Rx buffer has an async callback associated with it the callback
3994 * will be executed. The attached skb (if present) will only be freed
3995 * if the callback returns 1
3996 */
bb8c093b
CH
3997static void iwl4965_tx_cmd_complete(struct iwl4965_priv *priv,
3998 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3999{
bb8c093b 4000 struct iwl4965_rx_packet *pkt = (struct iwl4965_rx_packet *)rxb->skb->data;
b481de9c
ZY
4001 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
4002 int txq_id = SEQ_TO_QUEUE(sequence);
4003 int index = SEQ_TO_INDEX(sequence);
4004 int huge = sequence & SEQ_HUGE_FRAME;
4005 int cmd_index;
bb8c093b 4006 struct iwl4965_cmd *cmd;
b481de9c
ZY
4007
4008 /* If a Tx command is being handled and it isn't in the actual
4009 * command queue then there a command routing bug has been introduced
4010 * in the queue management code. */
4011 if (txq_id != IWL_CMD_QUEUE_NUM)
4012 IWL_ERROR("Error wrong command queue %d command id 0x%X\n",
4013 txq_id, pkt->hdr.cmd);
4014 BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
4015
4016 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
4017 cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
4018
4019 /* Input error checking is done when commands are added to queue. */
4020 if (cmd->meta.flags & CMD_WANT_SKB) {
4021 cmd->meta.source->u.skb = rxb->skb;
4022 rxb->skb = NULL;
4023 } else if (cmd->meta.u.callback &&
4024 !cmd->meta.u.callback(priv, cmd, rxb->skb))
4025 rxb->skb = NULL;
4026
bb8c093b 4027 iwl4965_tx_queue_reclaim(priv, txq_id, index);
b481de9c
ZY
4028
4029 if (!(cmd->meta.flags & CMD_ASYNC)) {
4030 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
4031 wake_up_interruptible(&priv->wait_command_queue);
4032 }
4033}
4034
4035/************************** RX-FUNCTIONS ****************************/
4036/*
4037 * Rx theory of operation
4038 *
9fbab516
BC
4039 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
4040 * each of which point to Receive Buffers to be filled by 4965. These get
4041 * used not only for Rx frames, but for any command response or notification
4042 * from the 4965. The driver and 4965 manage the Rx buffers by means
4043 * of indexes into the circular buffer.
b481de9c
ZY
4044 *
4045 * Rx Queue Indexes
4046 * The host/firmware share two index registers for managing the Rx buffers.
4047 *
4048 * The READ index maps to the first position that the firmware may be writing
4049 * to -- the driver can read up to (but not including) this position and get
4050 * good data.
4051 * The READ index is managed by the firmware once the card is enabled.
4052 *
4053 * The WRITE index maps to the last position the driver has read from -- the
4054 * position preceding WRITE is the last slot the firmware can place a packet.
4055 *
4056 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
4057 * WRITE = READ.
4058 *
9fbab516 4059 * During initialization, the host sets up the READ queue position to the first
b481de9c
ZY
4060 * INDEX position, and WRITE to the last (READ - 1 wrapped)
4061 *
9fbab516 4062 * When the firmware places a packet in a buffer, it will advance the READ index
b481de9c
ZY
4063 * and fire the RX interrupt. The driver can then query the READ index and
4064 * process as many packets as possible, moving the WRITE index forward as it
4065 * resets the Rx queue buffers with new memory.
4066 *
4067 * The management in the driver is as follows:
4068 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
4069 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
01ebd063 4070 * to replenish the iwl->rxq->rx_free.
bb8c093b 4071 * + In iwl4965_rx_replenish (scheduled) if 'processed' != 'read' then the
b481de9c
ZY
4072 * iwl->rxq is replenished and the READ INDEX is updated (updating the
4073 * 'processed' and 'read' driver indexes as well)
4074 * + A received packet is processed and handed to the kernel network stack,
4075 * detached from the iwl->rxq. The driver 'processed' index is updated.
4076 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
4077 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
4078 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
4079 * were enough free buffers and RX_STALLED is set it is cleared.
4080 *
4081 *
4082 * Driver sequence:
4083 *
9fbab516
BC
4084 * iwl4965_rx_queue_alloc() Allocates rx_free
4085 * iwl4965_rx_replenish() Replenishes rx_free list from rx_used, and calls
bb8c093b 4086 * iwl4965_rx_queue_restock
9fbab516 4087 * iwl4965_rx_queue_restock() Moves available buffers from rx_free into Rx
b481de9c
ZY
4088 * queue, updates firmware pointers, and updates
4089 * the WRITE index. If insufficient rx_free buffers
bb8c093b 4090 * are available, schedules iwl4965_rx_replenish
b481de9c
ZY
4091 *
4092 * -- enable interrupts --
9fbab516 4093 * ISR - iwl4965_rx() Detach iwl4965_rx_mem_buffers from pool up to the
b481de9c
ZY
4094 * READ INDEX, detaching the SKB from the pool.
4095 * Moves the packet buffer from queue to rx_used.
bb8c093b 4096 * Calls iwl4965_rx_queue_restock to refill any empty
b481de9c
ZY
4097 * slots.
4098 * ...
4099 *
4100 */
4101
4102/**
bb8c093b 4103 * iwl4965_rx_queue_space - Return number of free slots available in queue.
b481de9c 4104 */
bb8c093b 4105static int iwl4965_rx_queue_space(const struct iwl4965_rx_queue *q)
b481de9c
ZY
4106{
4107 int s = q->read - q->write;
4108 if (s <= 0)
4109 s += RX_QUEUE_SIZE;
4110 /* keep some buffer to not confuse full and empty queue */
4111 s -= 2;
4112 if (s < 0)
4113 s = 0;
4114 return s;
4115}
4116
4117/**
bb8c093b 4118 * iwl4965_rx_queue_update_write_ptr - Update the write pointer for the RX queue
b481de9c 4119 */
bb8c093b 4120int iwl4965_rx_queue_update_write_ptr(struct iwl4965_priv *priv, struct iwl4965_rx_queue *q)
b481de9c
ZY
4121{
4122 u32 reg = 0;
4123 int rc = 0;
4124 unsigned long flags;
4125
4126 spin_lock_irqsave(&q->lock, flags);
4127
4128 if (q->need_update == 0)
4129 goto exit_unlock;
4130
6440adb5 4131 /* If power-saving is in use, make sure device is awake */
b481de9c 4132 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
bb8c093b 4133 reg = iwl4965_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY
4134
4135 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
bb8c093b 4136 iwl4965_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY
4137 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
4138 goto exit_unlock;
4139 }
4140
bb8c093b 4141 rc = iwl4965_grab_nic_access(priv);
b481de9c
ZY
4142 if (rc)
4143 goto exit_unlock;
4144
6440adb5 4145 /* Device expects a multiple of 8 */
bb8c093b 4146 iwl4965_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
b481de9c 4147 q->write & ~0x7);
bb8c093b 4148 iwl4965_release_nic_access(priv);
6440adb5
CB
4149
4150 /* Else device is assumed to be awake */
b481de9c 4151 } else
6440adb5 4152 /* Device expects a multiple of 8 */
bb8c093b 4153 iwl4965_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
b481de9c
ZY
4154
4155
4156 q->need_update = 0;
4157
4158 exit_unlock:
4159 spin_unlock_irqrestore(&q->lock, flags);
4160 return rc;
4161}
4162
4163/**
9fbab516 4164 * iwl4965_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
b481de9c 4165 */
bb8c093b 4166static inline __le32 iwl4965_dma_addr2rbd_ptr(struct iwl4965_priv *priv,
b481de9c
ZY
4167 dma_addr_t dma_addr)
4168{
4169 return cpu_to_le32((u32)(dma_addr >> 8));
4170}
4171
4172
4173/**
bb8c093b 4174 * iwl4965_rx_queue_restock - refill RX queue from pre-allocated pool
b481de9c 4175 *
9fbab516 4176 * If there are slots in the RX queue that need to be restocked,
b481de9c 4177 * and we have free pre-allocated buffers, fill the ranks as much
9fbab516 4178 * as we can, pulling from rx_free.
b481de9c
ZY
4179 *
4180 * This moves the 'write' index forward to catch up with 'processed', and
4181 * also updates the memory address in the firmware to reference the new
4182 * target buffer.
4183 */
bb8c093b 4184static int iwl4965_rx_queue_restock(struct iwl4965_priv *priv)
b481de9c 4185{
bb8c093b 4186 struct iwl4965_rx_queue *rxq = &priv->rxq;
b481de9c 4187 struct list_head *element;
bb8c093b 4188 struct iwl4965_rx_mem_buffer *rxb;
b481de9c
ZY
4189 unsigned long flags;
4190 int write, rc;
4191
4192 spin_lock_irqsave(&rxq->lock, flags);
4193 write = rxq->write & ~0x7;
bb8c093b 4194 while ((iwl4965_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
6440adb5 4195 /* Get next free Rx buffer, remove from free list */
b481de9c 4196 element = rxq->rx_free.next;
bb8c093b 4197 rxb = list_entry(element, struct iwl4965_rx_mem_buffer, list);
b481de9c 4198 list_del(element);
6440adb5
CB
4199
4200 /* Point to Rx buffer via next RBD in circular buffer */
bb8c093b 4201 rxq->bd[rxq->write] = iwl4965_dma_addr2rbd_ptr(priv, rxb->dma_addr);
b481de9c
ZY
4202 rxq->queue[rxq->write] = rxb;
4203 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
4204 rxq->free_count--;
4205 }
4206 spin_unlock_irqrestore(&rxq->lock, flags);
4207 /* If the pre-allocated buffer pool is dropping low, schedule to
4208 * refill it */
4209 if (rxq->free_count <= RX_LOW_WATERMARK)
4210 queue_work(priv->workqueue, &priv->rx_replenish);
4211
4212
6440adb5
CB
4213 /* If we've added more space for the firmware to place data, tell it.
4214 * Increment device's write pointer in multiples of 8. */
b481de9c
ZY
4215 if ((write != (rxq->write & ~0x7))
4216 || (abs(rxq->write - rxq->read) > 7)) {
4217 spin_lock_irqsave(&rxq->lock, flags);
4218 rxq->need_update = 1;
4219 spin_unlock_irqrestore(&rxq->lock, flags);
bb8c093b 4220 rc = iwl4965_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY
4221 if (rc)
4222 return rc;
4223 }
4224
4225 return 0;
4226}
4227
4228/**
bb8c093b 4229 * iwl4965_rx_replenish - Move all used packet from rx_used to rx_free
b481de9c
ZY
4230 *
4231 * When moving to rx_free an SKB is allocated for the slot.
4232 *
bb8c093b 4233 * Also restock the Rx queue via iwl4965_rx_queue_restock.
01ebd063 4234 * This is called as a scheduled work item (except for during initialization)
b481de9c 4235 */
5c0eef96 4236static void iwl4965_rx_allocate(struct iwl4965_priv *priv)
b481de9c 4237{
bb8c093b 4238 struct iwl4965_rx_queue *rxq = &priv->rxq;
b481de9c 4239 struct list_head *element;
bb8c093b 4240 struct iwl4965_rx_mem_buffer *rxb;
b481de9c
ZY
4241 unsigned long flags;
4242 spin_lock_irqsave(&rxq->lock, flags);
4243 while (!list_empty(&rxq->rx_used)) {
4244 element = rxq->rx_used.next;
bb8c093b 4245 rxb = list_entry(element, struct iwl4965_rx_mem_buffer, list);
6440adb5
CB
4246
4247 /* Alloc a new receive buffer */
b481de9c 4248 rxb->skb =
9ee1ba47
RR
4249 alloc_skb(priv->hw_setting.rx_buf_size,
4250 __GFP_NOWARN | GFP_ATOMIC);
b481de9c
ZY
4251 if (!rxb->skb) {
4252 if (net_ratelimit())
4253 printk(KERN_CRIT DRV_NAME
4254 ": Can not allocate SKB buffers\n");
4255 /* We don't reschedule replenish work here -- we will
4256 * call the restock method and if it still needs
4257 * more buffers it will schedule replenish */
4258 break;
4259 }
4260 priv->alloc_rxb_skb++;
4261 list_del(element);
6440adb5
CB
4262
4263 /* Get physical address of RB/SKB */
b481de9c
ZY
4264 rxb->dma_addr =
4265 pci_map_single(priv->pci_dev, rxb->skb->data,
9ee1ba47 4266 priv->hw_setting.rx_buf_size, PCI_DMA_FROMDEVICE);
b481de9c
ZY
4267 list_add_tail(&rxb->list, &rxq->rx_free);
4268 rxq->free_count++;
4269 }
4270 spin_unlock_irqrestore(&rxq->lock, flags);
5c0eef96
MA
4271}
4272
4273/*
4274 * this should be called while priv->lock is locked
4275*/
4fd1f841 4276static void __iwl4965_rx_replenish(void *data)
5c0eef96
MA
4277{
4278 struct iwl4965_priv *priv = data;
4279
4280 iwl4965_rx_allocate(priv);
4281 iwl4965_rx_queue_restock(priv);
4282}
4283
4284
4285void iwl4965_rx_replenish(void *data)
4286{
4287 struct iwl4965_priv *priv = data;
4288 unsigned long flags;
4289
4290 iwl4965_rx_allocate(priv);
b481de9c
ZY
4291
4292 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 4293 iwl4965_rx_queue_restock(priv);
b481de9c
ZY
4294 spin_unlock_irqrestore(&priv->lock, flags);
4295}
4296
4297/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
9fbab516 4298 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
b481de9c
ZY
4299 * This free routine walks the list of POOL entries and if SKB is set to
4300 * non NULL it is unmapped and freed
4301 */
bb8c093b 4302static void iwl4965_rx_queue_free(struct iwl4965_priv *priv, struct iwl4965_rx_queue *rxq)
b481de9c
ZY
4303{
4304 int i;
4305 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
4306 if (rxq->pool[i].skb != NULL) {
4307 pci_unmap_single(priv->pci_dev,
4308 rxq->pool[i].dma_addr,
9ee1ba47
RR
4309 priv->hw_setting.rx_buf_size,
4310 PCI_DMA_FROMDEVICE);
b481de9c
ZY
4311 dev_kfree_skb(rxq->pool[i].skb);
4312 }
4313 }
4314
4315 pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
4316 rxq->dma_addr);
4317 rxq->bd = NULL;
4318}
4319
bb8c093b 4320int iwl4965_rx_queue_alloc(struct iwl4965_priv *priv)
b481de9c 4321{
bb8c093b 4322 struct iwl4965_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
4323 struct pci_dev *dev = priv->pci_dev;
4324 int i;
4325
4326 spin_lock_init(&rxq->lock);
4327 INIT_LIST_HEAD(&rxq->rx_free);
4328 INIT_LIST_HEAD(&rxq->rx_used);
6440adb5
CB
4329
4330 /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
b481de9c
ZY
4331 rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
4332 if (!rxq->bd)
4333 return -ENOMEM;
6440adb5 4334
b481de9c
ZY
4335 /* Fill the rx_used queue with _all_ of the Rx buffers */
4336 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
4337 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
6440adb5 4338
b481de9c
ZY
4339 /* Set us so that we have processed and used all buffers, but have
4340 * not restocked the Rx queue with fresh buffers */
4341 rxq->read = rxq->write = 0;
4342 rxq->free_count = 0;
4343 rxq->need_update = 0;
4344 return 0;
4345}
4346
bb8c093b 4347void iwl4965_rx_queue_reset(struct iwl4965_priv *priv, struct iwl4965_rx_queue *rxq)
b481de9c
ZY
4348{
4349 unsigned long flags;
4350 int i;
4351 spin_lock_irqsave(&rxq->lock, flags);
4352 INIT_LIST_HEAD(&rxq->rx_free);
4353 INIT_LIST_HEAD(&rxq->rx_used);
4354 /* Fill the rx_used queue with _all_ of the Rx buffers */
4355 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
4356 /* In the reset function, these buffers may have been allocated
4357 * to an SKB, so we need to unmap and free potential storage */
4358 if (rxq->pool[i].skb != NULL) {
4359 pci_unmap_single(priv->pci_dev,
4360 rxq->pool[i].dma_addr,
9ee1ba47
RR
4361 priv->hw_setting.rx_buf_size,
4362 PCI_DMA_FROMDEVICE);
b481de9c
ZY
4363 priv->alloc_rxb_skb--;
4364 dev_kfree_skb(rxq->pool[i].skb);
4365 rxq->pool[i].skb = NULL;
4366 }
4367 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
4368 }
4369
4370 /* Set us so that we have processed and used all buffers, but have
4371 * not restocked the Rx queue with fresh buffers */
4372 rxq->read = rxq->write = 0;
4373 rxq->free_count = 0;
4374 spin_unlock_irqrestore(&rxq->lock, flags);
4375}
4376
4377/* Convert linear signal-to-noise ratio into dB */
4378static u8 ratio2dB[100] = {
4379/* 0 1 2 3 4 5 6 7 8 9 */
4380 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
4381 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
4382 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
4383 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
4384 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
4385 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
4386 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
4387 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
4388 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
4389 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
4390};
4391
4392/* Calculates a relative dB value from a ratio of linear
4393 * (i.e. not dB) signal levels.
4394 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
bb8c093b 4395int iwl4965_calc_db_from_ratio(int sig_ratio)
b481de9c 4396{
c899a575
AB
4397 /* 1000:1 or higher just report as 60 dB */
4398 if (sig_ratio >= 1000)
b481de9c
ZY
4399 return 60;
4400
c899a575 4401 /* 100:1 or higher, divide by 10 and use table,
b481de9c 4402 * add 20 dB to make up for divide by 10 */
c899a575 4403 if (sig_ratio >= 100)
b481de9c
ZY
4404 return (20 + (int)ratio2dB[sig_ratio/10]);
4405
4406 /* We shouldn't see this */
4407 if (sig_ratio < 1)
4408 return 0;
4409
4410 /* Use table for ratios 1:1 - 99:1 */
4411 return (int)ratio2dB[sig_ratio];
4412}
4413
4414#define PERFECT_RSSI (-20) /* dBm */
4415#define WORST_RSSI (-95) /* dBm */
4416#define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
4417
4418/* Calculate an indication of rx signal quality (a percentage, not dBm!).
4419 * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
4420 * about formulas used below. */
bb8c093b 4421int iwl4965_calc_sig_qual(int rssi_dbm, int noise_dbm)
b481de9c
ZY
4422{
4423 int sig_qual;
4424 int degradation = PERFECT_RSSI - rssi_dbm;
4425
4426 /* If we get a noise measurement, use signal-to-noise ratio (SNR)
4427 * as indicator; formula is (signal dbm - noise dbm).
4428 * SNR at or above 40 is a great signal (100%).
4429 * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
4430 * Weakest usable signal is usually 10 - 15 dB SNR. */
4431 if (noise_dbm) {
4432 if (rssi_dbm - noise_dbm >= 40)
4433 return 100;
4434 else if (rssi_dbm < noise_dbm)
4435 return 0;
4436 sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
4437
4438 /* Else use just the signal level.
4439 * This formula is a least squares fit of data points collected and
4440 * compared with a reference system that had a percentage (%) display
4441 * for signal quality. */
4442 } else
4443 sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
4444 (15 * RSSI_RANGE + 62 * degradation)) /
4445 (RSSI_RANGE * RSSI_RANGE);
4446
4447 if (sig_qual > 100)
4448 sig_qual = 100;
4449 else if (sig_qual < 1)
4450 sig_qual = 0;
4451
4452 return sig_qual;
4453}
4454
4455/**
9fbab516 4456 * iwl4965_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
4457 *
4458 * Uses the priv->rx_handlers callback function array to invoke
4459 * the appropriate handlers, including command responses,
4460 * frame-received notifications, and other notifications.
4461 */
bb8c093b 4462static void iwl4965_rx_handle(struct iwl4965_priv *priv)
b481de9c 4463{
bb8c093b
CH
4464 struct iwl4965_rx_mem_buffer *rxb;
4465 struct iwl4965_rx_packet *pkt;
4466 struct iwl4965_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
4467 u32 r, i;
4468 int reclaim;
4469 unsigned long flags;
5c0eef96 4470 u8 fill_rx = 0;
d68ab680 4471 u32 count = 8;
b481de9c 4472
6440adb5
CB
4473 /* uCode's read index (stored in shared DRAM) indicates the last Rx
4474 * buffer that the driver may process (last buffer filled by ucode). */
bb8c093b 4475 r = iwl4965_hw_get_rx_read(priv);
b481de9c
ZY
4476 i = rxq->read;
4477
4478 /* Rx interrupt, but nothing sent from uCode */
4479 if (i == r)
4480 IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
4481
5c0eef96
MA
4482 if (iwl4965_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
4483 fill_rx = 1;
4484
b481de9c
ZY
4485 while (i != r) {
4486 rxb = rxq->queue[i];
4487
9fbab516 4488 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
4489 * then a bug has been introduced in the queue refilling
4490 * routines -- catch it here */
4491 BUG_ON(rxb == NULL);
4492
4493 rxq->queue[i] = NULL;
4494
4495 pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
9ee1ba47 4496 priv->hw_setting.rx_buf_size,
b481de9c 4497 PCI_DMA_FROMDEVICE);
bb8c093b 4498 pkt = (struct iwl4965_rx_packet *)rxb->skb->data;
b481de9c
ZY
4499
4500 /* Reclaim a command buffer only if this packet is a response
4501 * to a (driver-originated) command.
4502 * If the packet (e.g. Rx frame) originated from uCode,
4503 * there is no command buffer to reclaim.
4504 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
4505 * but apparently a few don't get set; catch them here. */
4506 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
4507 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
4508 (pkt->hdr.cmd != REPLY_4965_RX) &&
cfe01709 4509 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY
4510 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
4511 (pkt->hdr.cmd != REPLY_TX);
4512
4513 /* Based on type of command response or notification,
4514 * handle those that need handling via function in
bb8c093b 4515 * rx_handlers table. See iwl4965_setup_rx_handlers() */
b481de9c
ZY
4516 if (priv->rx_handlers[pkt->hdr.cmd]) {
4517 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
4518 "r = %d, i = %d, %s, 0x%02x\n", r, i,
4519 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
4520 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
4521 } else {
4522 /* No handling needed */
4523 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
4524 "r %d i %d No handler needed for %s, 0x%02x\n",
4525 r, i, get_cmd_string(pkt->hdr.cmd),
4526 pkt->hdr.cmd);
4527 }
4528
4529 if (reclaim) {
9fbab516
BC
4530 /* Invoke any callbacks, transfer the skb to caller, and
4531 * fire off the (possibly) blocking iwl4965_send_cmd()
b481de9c
ZY
4532 * as we reclaim the driver command queue */
4533 if (rxb && rxb->skb)
bb8c093b 4534 iwl4965_tx_cmd_complete(priv, rxb);
b481de9c
ZY
4535 else
4536 IWL_WARNING("Claim null rxb?\n");
4537 }
4538
4539 /* For now we just don't re-use anything. We can tweak this
4540 * later to try and re-use notification packets and SKBs that
4541 * fail to Rx correctly */
4542 if (rxb->skb != NULL) {
4543 priv->alloc_rxb_skb--;
4544 dev_kfree_skb_any(rxb->skb);
4545 rxb->skb = NULL;
4546 }
4547
4548 pci_unmap_single(priv->pci_dev, rxb->dma_addr,
9ee1ba47
RR
4549 priv->hw_setting.rx_buf_size,
4550 PCI_DMA_FROMDEVICE);
b481de9c
ZY
4551 spin_lock_irqsave(&rxq->lock, flags);
4552 list_add_tail(&rxb->list, &priv->rxq.rx_used);
4553 spin_unlock_irqrestore(&rxq->lock, flags);
4554 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
4555 /* If there are a lot of unused frames,
4556 * restock the Rx queue so ucode wont assert. */
4557 if (fill_rx) {
4558 count++;
4559 if (count >= 8) {
4560 priv->rxq.read = i;
4561 __iwl4965_rx_replenish(priv);
4562 count = 0;
4563 }
4564 }
b481de9c
ZY
4565 }
4566
4567 /* Backtrack one entry */
4568 priv->rxq.read = i;
bb8c093b 4569 iwl4965_rx_queue_restock(priv);
b481de9c
ZY
4570}
4571
6440adb5
CB
4572/**
4573 * iwl4965_tx_queue_update_write_ptr - Send new write index to hardware
4574 */
bb8c093b
CH
4575static int iwl4965_tx_queue_update_write_ptr(struct iwl4965_priv *priv,
4576 struct iwl4965_tx_queue *txq)
b481de9c
ZY
4577{
4578 u32 reg = 0;
4579 int rc = 0;
4580 int txq_id = txq->q.id;
4581
4582 if (txq->need_update == 0)
4583 return rc;
4584
4585 /* if we're trying to save power */
4586 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
4587 /* wake up nic if it's powered down ...
4588 * uCode will wake up, and interrupt us again, so next
4589 * time we'll skip this part. */
bb8c093b 4590 reg = iwl4965_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY
4591
4592 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
4593 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
bb8c093b 4594 iwl4965_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY
4595 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
4596 return rc;
4597 }
4598
4599 /* restore this queue's parameters in nic hardware. */
bb8c093b 4600 rc = iwl4965_grab_nic_access(priv);
b481de9c
ZY
4601 if (rc)
4602 return rc;
bb8c093b 4603 iwl4965_write_direct32(priv, HBUS_TARG_WRPTR,
fc4b6853 4604 txq->q.write_ptr | (txq_id << 8));
bb8c093b 4605 iwl4965_release_nic_access(priv);
b481de9c
ZY
4606
4607 /* else not in power-save mode, uCode will never sleep when we're
4608 * trying to tx (during RFKILL, we're not trying to tx). */
4609 } else
bb8c093b 4610 iwl4965_write32(priv, HBUS_TARG_WRPTR,
fc4b6853 4611 txq->q.write_ptr | (txq_id << 8));
b481de9c
ZY
4612
4613 txq->need_update = 0;
4614
4615 return rc;
4616}
4617
c8b0e6e1 4618#ifdef CONFIG_IWL4965_DEBUG
bb8c093b 4619static void iwl4965_print_rx_config_cmd(struct iwl4965_rxon_cmd *rxon)
b481de9c 4620{
0795af57
JP
4621 DECLARE_MAC_BUF(mac);
4622
b481de9c 4623 IWL_DEBUG_RADIO("RX CONFIG:\n");
bb8c093b 4624 iwl4965_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
b481de9c
ZY
4625 IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
4626 IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
4627 IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
4628 le32_to_cpu(rxon->filter_flags));
4629 IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
4630 IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
4631 rxon->ofdm_basic_rates);
4632 IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
0795af57
JP
4633 IWL_DEBUG_RADIO("u8[6] node_addr: %s\n",
4634 print_mac(mac, rxon->node_addr));
4635 IWL_DEBUG_RADIO("u8[6] bssid_addr: %s\n",
4636 print_mac(mac, rxon->bssid_addr));
b481de9c
ZY
4637 IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
4638}
4639#endif
4640
bb8c093b 4641static void iwl4965_enable_interrupts(struct iwl4965_priv *priv)
b481de9c
ZY
4642{
4643 IWL_DEBUG_ISR("Enabling interrupts\n");
4644 set_bit(STATUS_INT_ENABLED, &priv->status);
bb8c093b 4645 iwl4965_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
b481de9c
ZY
4646}
4647
bb8c093b 4648static inline void iwl4965_disable_interrupts(struct iwl4965_priv *priv)
b481de9c
ZY
4649{
4650 clear_bit(STATUS_INT_ENABLED, &priv->status);
4651
4652 /* disable interrupts from uCode/NIC to host */
bb8c093b 4653 iwl4965_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY
4654
4655 /* acknowledge/clear/reset any interrupts still pending
4656 * from uCode or flow handler (Rx/Tx DMA) */
bb8c093b
CH
4657 iwl4965_write32(priv, CSR_INT, 0xffffffff);
4658 iwl4965_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
b481de9c
ZY
4659 IWL_DEBUG_ISR("Disabled interrupts\n");
4660}
4661
4662static const char *desc_lookup(int i)
4663{
4664 switch (i) {
4665 case 1:
4666 return "FAIL";
4667 case 2:
4668 return "BAD_PARAM";
4669 case 3:
4670 return "BAD_CHECKSUM";
4671 case 4:
4672 return "NMI_INTERRUPT";
4673 case 5:
4674 return "SYSASSERT";
4675 case 6:
4676 return "FATAL_ERROR";
4677 }
4678
4679 return "UNKNOWN";
4680}
4681
4682#define ERROR_START_OFFSET (1 * sizeof(u32))
4683#define ERROR_ELEM_SIZE (7 * sizeof(u32))
4684
bb8c093b 4685static void iwl4965_dump_nic_error_log(struct iwl4965_priv *priv)
b481de9c
ZY
4686{
4687 u32 data2, line;
4688 u32 desc, time, count, base, data1;
4689 u32 blink1, blink2, ilink1, ilink2;
4690 int rc;
4691
4692 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
4693
bb8c093b 4694 if (!iwl4965_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY
4695 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
4696 return;
4697 }
4698
bb8c093b 4699 rc = iwl4965_grab_nic_access(priv);
b481de9c
ZY
4700 if (rc) {
4701 IWL_WARNING("Can not read from adapter at this time.\n");
4702 return;
4703 }
4704
bb8c093b 4705 count = iwl4965_read_targ_mem(priv, base);
b481de9c
ZY
4706
4707 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
4708 IWL_ERROR("Start IWL Error Log Dump:\n");
2acae16e 4709 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
b481de9c
ZY
4710 }
4711
bb8c093b
CH
4712 desc = iwl4965_read_targ_mem(priv, base + 1 * sizeof(u32));
4713 blink1 = iwl4965_read_targ_mem(priv, base + 3 * sizeof(u32));
4714 blink2 = iwl4965_read_targ_mem(priv, base + 4 * sizeof(u32));
4715 ilink1 = iwl4965_read_targ_mem(priv, base + 5 * sizeof(u32));
4716 ilink2 = iwl4965_read_targ_mem(priv, base + 6 * sizeof(u32));
4717 data1 = iwl4965_read_targ_mem(priv, base + 7 * sizeof(u32));
4718 data2 = iwl4965_read_targ_mem(priv, base + 8 * sizeof(u32));
4719 line = iwl4965_read_targ_mem(priv, base + 9 * sizeof(u32));
4720 time = iwl4965_read_targ_mem(priv, base + 11 * sizeof(u32));
b481de9c
ZY
4721
4722 IWL_ERROR("Desc Time "
4723 "data1 data2 line\n");
4724 IWL_ERROR("%-13s (#%d) %010u 0x%08X 0x%08X %u\n",
4725 desc_lookup(desc), desc, time, data1, data2, line);
4726 IWL_ERROR("blink1 blink2 ilink1 ilink2\n");
4727 IWL_ERROR("0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
4728 ilink1, ilink2);
4729
bb8c093b 4730 iwl4965_release_nic_access(priv);
b481de9c
ZY
4731}
4732
4733#define EVENT_START_OFFSET (4 * sizeof(u32))
4734
4735/**
bb8c093b 4736 * iwl4965_print_event_log - Dump error event log to syslog
b481de9c 4737 *
bb8c093b 4738 * NOTE: Must be called with iwl4965_grab_nic_access() already obtained!
b481de9c 4739 */
bb8c093b 4740static void iwl4965_print_event_log(struct iwl4965_priv *priv, u32 start_idx,
b481de9c
ZY
4741 u32 num_events, u32 mode)
4742{
4743 u32 i;
4744 u32 base; /* SRAM byte address of event log header */
4745 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
4746 u32 ptr; /* SRAM byte address of log data */
4747 u32 ev, time, data; /* event log data */
4748
4749 if (num_events == 0)
4750 return;
4751
4752 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
4753
4754 if (mode == 0)
4755 event_size = 2 * sizeof(u32);
4756 else
4757 event_size = 3 * sizeof(u32);
4758
4759 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
4760
4761 /* "time" is actually "data" for mode 0 (no timestamp).
4762 * place event id # at far right for easier visual parsing. */
4763 for (i = 0; i < num_events; i++) {
bb8c093b 4764 ev = iwl4965_read_targ_mem(priv, ptr);
b481de9c 4765 ptr += sizeof(u32);
bb8c093b 4766 time = iwl4965_read_targ_mem(priv, ptr);
b481de9c
ZY
4767 ptr += sizeof(u32);
4768 if (mode == 0)
4769 IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
4770 else {
bb8c093b 4771 data = iwl4965_read_targ_mem(priv, ptr);
b481de9c
ZY
4772 ptr += sizeof(u32);
4773 IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
4774 }
4775 }
4776}
4777
bb8c093b 4778static void iwl4965_dump_nic_event_log(struct iwl4965_priv *priv)
b481de9c
ZY
4779{
4780 int rc;
4781 u32 base; /* SRAM byte address of event log header */
4782 u32 capacity; /* event log capacity in # entries */
4783 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
4784 u32 num_wraps; /* # times uCode wrapped to top of log */
4785 u32 next_entry; /* index of next entry to be written by uCode */
4786 u32 size; /* # entries that we'll print */
4787
4788 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 4789 if (!iwl4965_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY
4790 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
4791 return;
4792 }
4793
bb8c093b 4794 rc = iwl4965_grab_nic_access(priv);
b481de9c
ZY
4795 if (rc) {
4796 IWL_WARNING("Can not read from adapter at this time.\n");
4797 return;
4798 }
4799
4800 /* event log header */
bb8c093b
CH
4801 capacity = iwl4965_read_targ_mem(priv, base);
4802 mode = iwl4965_read_targ_mem(priv, base + (1 * sizeof(u32)));
4803 num_wraps = iwl4965_read_targ_mem(priv, base + (2 * sizeof(u32)));
4804 next_entry = iwl4965_read_targ_mem(priv, base + (3 * sizeof(u32)));
b481de9c
ZY
4805
4806 size = num_wraps ? capacity : next_entry;
4807
4808 /* bail out if nothing in log */
4809 if (size == 0) {
583fab37 4810 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
bb8c093b 4811 iwl4965_release_nic_access(priv);
b481de9c
ZY
4812 return;
4813 }
4814
583fab37 4815 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
b481de9c
ZY
4816 size, num_wraps);
4817
4818 /* if uCode has wrapped back to top of log, start at the oldest entry,
4819 * i.e the next one that uCode would fill. */
4820 if (num_wraps)
bb8c093b 4821 iwl4965_print_event_log(priv, next_entry,
b481de9c
ZY
4822 capacity - next_entry, mode);
4823
4824 /* (then/else) start at top of log */
bb8c093b 4825 iwl4965_print_event_log(priv, 0, next_entry, mode);
b481de9c 4826
bb8c093b 4827 iwl4965_release_nic_access(priv);
b481de9c
ZY
4828}
4829
4830/**
bb8c093b 4831 * iwl4965_irq_handle_error - called for HW or SW error interrupt from card
b481de9c 4832 */
bb8c093b 4833static void iwl4965_irq_handle_error(struct iwl4965_priv *priv)
b481de9c 4834{
bb8c093b 4835 /* Set the FW error flag -- cleared on iwl4965_down */
b481de9c
ZY
4836 set_bit(STATUS_FW_ERROR, &priv->status);
4837
4838 /* Cancel currently queued command. */
4839 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
4840
c8b0e6e1 4841#ifdef CONFIG_IWL4965_DEBUG
bb8c093b
CH
4842 if (iwl4965_debug_level & IWL_DL_FW_ERRORS) {
4843 iwl4965_dump_nic_error_log(priv);
4844 iwl4965_dump_nic_event_log(priv);
4845 iwl4965_print_rx_config_cmd(&priv->staging_rxon);
b481de9c
ZY
4846 }
4847#endif
4848
4849 wake_up_interruptible(&priv->wait_command_queue);
4850
4851 /* Keep the restart process from trying to send host
4852 * commands by clearing the INIT status bit */
4853 clear_bit(STATUS_READY, &priv->status);
4854
4855 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
4856 IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
4857 "Restarting adapter due to uCode error.\n");
4858
bb8c093b 4859 if (iwl4965_is_associated(priv)) {
b481de9c
ZY
4860 memcpy(&priv->recovery_rxon, &priv->active_rxon,
4861 sizeof(priv->recovery_rxon));
4862 priv->error_recovering = 1;
4863 }
4864 queue_work(priv->workqueue, &priv->restart);
4865 }
4866}
4867
bb8c093b 4868static void iwl4965_error_recovery(struct iwl4965_priv *priv)
b481de9c
ZY
4869{
4870 unsigned long flags;
4871
4872 memcpy(&priv->staging_rxon, &priv->recovery_rxon,
4873 sizeof(priv->staging_rxon));
4874 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 4875 iwl4965_commit_rxon(priv);
b481de9c 4876
bb8c093b 4877 iwl4965_rxon_add_station(priv, priv->bssid, 1);
b481de9c
ZY
4878
4879 spin_lock_irqsave(&priv->lock, flags);
4880 priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
4881 priv->error_recovering = 0;
4882 spin_unlock_irqrestore(&priv->lock, flags);
4883}
4884
bb8c093b 4885static void iwl4965_irq_tasklet(struct iwl4965_priv *priv)
b481de9c
ZY
4886{
4887 u32 inta, handled = 0;
4888 u32 inta_fh;
4889 unsigned long flags;
c8b0e6e1 4890#ifdef CONFIG_IWL4965_DEBUG
b481de9c
ZY
4891 u32 inta_mask;
4892#endif
4893
4894 spin_lock_irqsave(&priv->lock, flags);
4895
4896 /* Ack/clear/reset pending uCode interrupts.
4897 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
4898 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
bb8c093b
CH
4899 inta = iwl4965_read32(priv, CSR_INT);
4900 iwl4965_write32(priv, CSR_INT, inta);
b481de9c
ZY
4901
4902 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
4903 * Any new interrupts that happen after this, either while we're
4904 * in this tasklet, or later, will show up in next ISR/tasklet. */
bb8c093b
CH
4905 inta_fh = iwl4965_read32(priv, CSR_FH_INT_STATUS);
4906 iwl4965_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 4907
c8b0e6e1 4908#ifdef CONFIG_IWL4965_DEBUG
bb8c093b 4909 if (iwl4965_debug_level & IWL_DL_ISR) {
9fbab516
BC
4910 /* just for debug */
4911 inta_mask = iwl4965_read32(priv, CSR_INT_MASK);
b481de9c
ZY
4912 IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4913 inta, inta_mask, inta_fh);
4914 }
4915#endif
4916
4917 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
4918 * atomic, make sure that inta covers all the interrupts that
4919 * we've discovered, even if FH interrupt came in just after
4920 * reading CSR_INT. */
6f83eaa1 4921 if (inta_fh & CSR49_FH_INT_RX_MASK)
b481de9c 4922 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 4923 if (inta_fh & CSR49_FH_INT_TX_MASK)
b481de9c
ZY
4924 inta |= CSR_INT_BIT_FH_TX;
4925
4926 /* Now service all interrupt bits discovered above. */
4927 if (inta & CSR_INT_BIT_HW_ERR) {
4928 IWL_ERROR("Microcode HW error detected. Restarting.\n");
4929
4930 /* Tell the device to stop sending interrupts */
bb8c093b 4931 iwl4965_disable_interrupts(priv);
b481de9c 4932
bb8c093b 4933 iwl4965_irq_handle_error(priv);
b481de9c
ZY
4934
4935 handled |= CSR_INT_BIT_HW_ERR;
4936
4937 spin_unlock_irqrestore(&priv->lock, flags);
4938
4939 return;
4940 }
4941
c8b0e6e1 4942#ifdef CONFIG_IWL4965_DEBUG
bb8c093b 4943 if (iwl4965_debug_level & (IWL_DL_ISR)) {
b481de9c 4944 /* NIC fires this, but we don't use it, redundant with WAKEUP */
25c03d8e
JP
4945 if (inta & CSR_INT_BIT_SCD)
4946 IWL_DEBUG_ISR("Scheduler finished to transmit "
4947 "the frame/frames.\n");
b481de9c
ZY
4948
4949 /* Alive notification via Rx interrupt will do the real work */
4950 if (inta & CSR_INT_BIT_ALIVE)
4951 IWL_DEBUG_ISR("Alive interrupt\n");
4952 }
4953#endif
4954 /* Safely ignore these bits for debug checks below */
25c03d8e 4955 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 4956
9fbab516 4957 /* HW RF KILL switch toggled */
b481de9c
ZY
4958 if (inta & CSR_INT_BIT_RF_KILL) {
4959 int hw_rf_kill = 0;
bb8c093b 4960 if (!(iwl4965_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY
4961 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
4962 hw_rf_kill = 1;
4963
4964 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR,
4965 "RF_KILL bit toggled to %s.\n",
4966 hw_rf_kill ? "disable radio":"enable radio");
4967
4968 /* Queue restart only if RF_KILL switch was set to "kill"
4969 * when we loaded driver, and is now set to "enable".
4970 * After we're Alive, RF_KILL gets handled by
3230455d 4971 * iwl4965_rx_card_state_notif() */
53e49093
ZY
4972 if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) {
4973 clear_bit(STATUS_RF_KILL_HW, &priv->status);
b481de9c 4974 queue_work(priv->workqueue, &priv->restart);
53e49093 4975 }
b481de9c
ZY
4976
4977 handled |= CSR_INT_BIT_RF_KILL;
4978 }
4979
9fbab516 4980 /* Chip got too hot and stopped itself */
b481de9c
ZY
4981 if (inta & CSR_INT_BIT_CT_KILL) {
4982 IWL_ERROR("Microcode CT kill error detected.\n");
4983 handled |= CSR_INT_BIT_CT_KILL;
4984 }
4985
4986 /* Error detected by uCode */
4987 if (inta & CSR_INT_BIT_SW_ERR) {
4988 IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
4989 inta);
bb8c093b 4990 iwl4965_irq_handle_error(priv);
b481de9c
ZY
4991 handled |= CSR_INT_BIT_SW_ERR;
4992 }
4993
4994 /* uCode wakes up after power-down sleep */
4995 if (inta & CSR_INT_BIT_WAKEUP) {
4996 IWL_DEBUG_ISR("Wakeup interrupt\n");
bb8c093b
CH
4997 iwl4965_rx_queue_update_write_ptr(priv, &priv->rxq);
4998 iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[0]);
4999 iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[1]);
5000 iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[2]);
5001 iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[3]);
5002 iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[4]);
5003 iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[5]);
b481de9c
ZY
5004
5005 handled |= CSR_INT_BIT_WAKEUP;
5006 }
5007
5008 /* All uCode command responses, including Tx command responses,
5009 * Rx "responses" (frame-received notification), and other
5010 * notifications from uCode come through here*/
5011 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
bb8c093b 5012 iwl4965_rx_handle(priv);
b481de9c
ZY
5013 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
5014 }
5015
5016 if (inta & CSR_INT_BIT_FH_TX) {
5017 IWL_DEBUG_ISR("Tx interrupt\n");
5018 handled |= CSR_INT_BIT_FH_TX;
5019 }
5020
5021 if (inta & ~handled)
5022 IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
5023
5024 if (inta & ~CSR_INI_SET_MASK) {
5025 IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
5026 inta & ~CSR_INI_SET_MASK);
5027 IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
5028 }
5029
5030 /* Re-enable all interrupts */
bb8c093b 5031 iwl4965_enable_interrupts(priv);
b481de9c 5032
c8b0e6e1 5033#ifdef CONFIG_IWL4965_DEBUG
bb8c093b
CH
5034 if (iwl4965_debug_level & (IWL_DL_ISR)) {
5035 inta = iwl4965_read32(priv, CSR_INT);
5036 inta_mask = iwl4965_read32(priv, CSR_INT_MASK);
5037 inta_fh = iwl4965_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY
5038 IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
5039 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
5040 }
5041#endif
5042 spin_unlock_irqrestore(&priv->lock, flags);
5043}
5044
bb8c093b 5045static irqreturn_t iwl4965_isr(int irq, void *data)
b481de9c 5046{
bb8c093b 5047 struct iwl4965_priv *priv = data;
b481de9c
ZY
5048 u32 inta, inta_mask;
5049 u32 inta_fh;
5050 if (!priv)
5051 return IRQ_NONE;
5052
5053 spin_lock(&priv->lock);
5054
5055 /* Disable (but don't clear!) interrupts here to avoid
5056 * back-to-back ISRs and sporadic interrupts from our NIC.
5057 * If we have something to service, the tasklet will re-enable ints.
5058 * If we *don't* have something, we'll re-enable before leaving here. */
bb8c093b
CH
5059 inta_mask = iwl4965_read32(priv, CSR_INT_MASK); /* just for debug */
5060 iwl4965_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY
5061
5062 /* Discover which interrupts are active/pending */
bb8c093b
CH
5063 inta = iwl4965_read32(priv, CSR_INT);
5064 inta_fh = iwl4965_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY
5065
5066 /* Ignore interrupt if there's nothing in NIC to service.
5067 * This may be due to IRQ shared with another device,
5068 * or due to sporadic interrupts thrown from our NIC. */
5069 if (!inta && !inta_fh) {
5070 IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
5071 goto none;
5072 }
5073
5074 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
66fbb541
ON
5075 /* Hardware disappeared. It might have already raised
5076 * an interrupt */
b481de9c 5077 IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta);
66fbb541 5078 goto unplugged;
b481de9c
ZY
5079 }
5080
5081 IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
5082 inta, inta_mask, inta_fh);
5083
25c03d8e
JP
5084 inta &= ~CSR_INT_BIT_SCD;
5085
bb8c093b 5086 /* iwl4965_irq_tasklet() will service interrupts and re-enable them */
25c03d8e
JP
5087 if (likely(inta || inta_fh))
5088 tasklet_schedule(&priv->irq_tasklet);
b481de9c 5089
66fbb541
ON
5090 unplugged:
5091 spin_unlock(&priv->lock);
b481de9c
ZY
5092 return IRQ_HANDLED;
5093
5094 none:
5095 /* re-enable interrupts here since we don't have anything to service. */
bb8c093b 5096 iwl4965_enable_interrupts(priv);
b481de9c
ZY
5097 spin_unlock(&priv->lock);
5098 return IRQ_NONE;
5099}
5100
5101/************************** EEPROM BANDS ****************************
5102 *
bb8c093b 5103 * The iwl4965_eeprom_band definitions below provide the mapping from the
b481de9c
ZY
5104 * EEPROM contents to the specific channel number supported for each
5105 * band.
5106 *
bb8c093b 5107 * For example, iwl4965_priv->eeprom.band_3_channels[4] from the band_3
b481de9c
ZY
5108 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
5109 * The specific geography and calibration information for that channel
5110 * is contained in the eeprom map itself.
5111 *
5112 * During init, we copy the eeprom information and channel map
5113 * information into priv->channel_info_24/52 and priv->channel_map_24/52
5114 *
5115 * channel_map_24/52 provides the index in the channel_info array for a
5116 * given channel. We have to have two separate maps as there is channel
5117 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
5118 * band_2
5119 *
5120 * A value of 0xff stored in the channel_map indicates that the channel
5121 * is not supported by the hardware at all.
5122 *
5123 * A value of 0xfe in the channel_map indicates that the channel is not
5124 * valid for Tx with the current hardware. This means that
5125 * while the system can tune and receive on a given channel, it may not
5126 * be able to associate or transmit any frames on that
5127 * channel. There is no corresponding channel information for that
5128 * entry.
5129 *
5130 *********************************************************************/
5131
5132/* 2.4 GHz */
bb8c093b 5133static const u8 iwl4965_eeprom_band_1[14] = {
b481de9c
ZY
5134 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
5135};
5136
5137/* 5.2 GHz bands */
9fbab516 5138static const u8 iwl4965_eeprom_band_2[] = { /* 4915-5080MHz */
b481de9c
ZY
5139 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
5140};
5141
9fbab516 5142static const u8 iwl4965_eeprom_band_3[] = { /* 5170-5320MHz */
b481de9c
ZY
5143 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
5144};
5145
bb8c093b 5146static const u8 iwl4965_eeprom_band_4[] = { /* 5500-5700MHz */
b481de9c
ZY
5147 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
5148};
5149
bb8c093b 5150static const u8 iwl4965_eeprom_band_5[] = { /* 5725-5825MHz */
b481de9c
ZY
5151 145, 149, 153, 157, 161, 165
5152};
5153
bb8c093b 5154static u8 iwl4965_eeprom_band_6[] = { /* 2.4 FAT channel */
b481de9c
ZY
5155 1, 2, 3, 4, 5, 6, 7
5156};
5157
bb8c093b 5158static u8 iwl4965_eeprom_band_7[] = { /* 5.2 FAT channel */
b481de9c
ZY
5159 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157
5160};
5161
9fbab516
BC
5162static void iwl4965_init_band_reference(const struct iwl4965_priv *priv,
5163 int band,
b481de9c 5164 int *eeprom_ch_count,
bb8c093b 5165 const struct iwl4965_eeprom_channel
b481de9c
ZY
5166 **eeprom_ch_info,
5167 const u8 **eeprom_ch_index)
5168{
5169 switch (band) {
5170 case 1: /* 2.4GHz band */
bb8c093b 5171 *eeprom_ch_count = ARRAY_SIZE(iwl4965_eeprom_band_1);
b481de9c 5172 *eeprom_ch_info = priv->eeprom.band_1_channels;
bb8c093b 5173 *eeprom_ch_index = iwl4965_eeprom_band_1;
b481de9c 5174 break;
9fbab516 5175 case 2: /* 4.9GHz band */
bb8c093b 5176 *eeprom_ch_count = ARRAY_SIZE(iwl4965_eeprom_band_2);
b481de9c 5177 *eeprom_ch_info = priv->eeprom.band_2_channels;
bb8c093b 5178 *eeprom_ch_index = iwl4965_eeprom_band_2;
b481de9c
ZY
5179 break;
5180 case 3: /* 5.2GHz band */
bb8c093b 5181 *eeprom_ch_count = ARRAY_SIZE(iwl4965_eeprom_band_3);
b481de9c 5182 *eeprom_ch_info = priv->eeprom.band_3_channels;
bb8c093b 5183 *eeprom_ch_index = iwl4965_eeprom_band_3;
b481de9c 5184 break;
9fbab516 5185 case 4: /* 5.5GHz band */
bb8c093b 5186 *eeprom_ch_count = ARRAY_SIZE(iwl4965_eeprom_band_4);
b481de9c 5187 *eeprom_ch_info = priv->eeprom.band_4_channels;
bb8c093b 5188 *eeprom_ch_index = iwl4965_eeprom_band_4;
b481de9c 5189 break;
9fbab516 5190 case 5: /* 5.7GHz band */
bb8c093b 5191 *eeprom_ch_count = ARRAY_SIZE(iwl4965_eeprom_band_5);
b481de9c 5192 *eeprom_ch_info = priv->eeprom.band_5_channels;
bb8c093b 5193 *eeprom_ch_index = iwl4965_eeprom_band_5;
b481de9c 5194 break;
9fbab516 5195 case 6: /* 2.4GHz FAT channels */
bb8c093b 5196 *eeprom_ch_count = ARRAY_SIZE(iwl4965_eeprom_band_6);
b481de9c 5197 *eeprom_ch_info = priv->eeprom.band_24_channels;
bb8c093b 5198 *eeprom_ch_index = iwl4965_eeprom_band_6;
b481de9c 5199 break;
9fbab516 5200 case 7: /* 5 GHz FAT channels */
bb8c093b 5201 *eeprom_ch_count = ARRAY_SIZE(iwl4965_eeprom_band_7);
b481de9c 5202 *eeprom_ch_info = priv->eeprom.band_52_channels;
bb8c093b 5203 *eeprom_ch_index = iwl4965_eeprom_band_7;
b481de9c
ZY
5204 break;
5205 default:
5206 BUG();
5207 return;
5208 }
5209}
5210
6440adb5
CB
5211/**
5212 * iwl4965_get_channel_info - Find driver's private channel info
5213 *
5214 * Based on band and channel number.
5215 */
bb8c093b 5216const struct iwl4965_channel_info *iwl4965_get_channel_info(const struct iwl4965_priv *priv,
8318d78a 5217 enum ieee80211_band band, u16 channel)
b481de9c
ZY
5218{
5219 int i;
5220
8318d78a
JB
5221 switch (band) {
5222 case IEEE80211_BAND_5GHZ:
b481de9c
ZY
5223 for (i = 14; i < priv->channel_count; i++) {
5224 if (priv->channel_info[i].channel == channel)
5225 return &priv->channel_info[i];
5226 }
5227 break;
8318d78a 5228 case IEEE80211_BAND_2GHZ:
b481de9c
ZY
5229 if (channel >= 1 && channel <= 14)
5230 return &priv->channel_info[channel - 1];
5231 break;
8318d78a
JB
5232 default:
5233 BUG();
b481de9c
ZY
5234 }
5235
5236 return NULL;
5237}
5238
5239#define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
5240 ? # x " " : "")
5241
6440adb5
CB
5242/**
5243 * iwl4965_init_channel_map - Set up driver's info for all possible channels
5244 */
bb8c093b 5245static int iwl4965_init_channel_map(struct iwl4965_priv *priv)
b481de9c
ZY
5246{
5247 int eeprom_ch_count = 0;
5248 const u8 *eeprom_ch_index = NULL;
bb8c093b 5249 const struct iwl4965_eeprom_channel *eeprom_ch_info = NULL;
b481de9c 5250 int band, ch;
bb8c093b 5251 struct iwl4965_channel_info *ch_info;
b481de9c
ZY
5252
5253 if (priv->channel_count) {
5254 IWL_DEBUG_INFO("Channel map already initialized.\n");
5255 return 0;
5256 }
5257
5258 if (priv->eeprom.version < 0x2f) {
5259 IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
5260 priv->eeprom.version);
5261 return -EINVAL;
5262 }
5263
5264 IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
5265
5266 priv->channel_count =
bb8c093b
CH
5267 ARRAY_SIZE(iwl4965_eeprom_band_1) +
5268 ARRAY_SIZE(iwl4965_eeprom_band_2) +
5269 ARRAY_SIZE(iwl4965_eeprom_band_3) +
5270 ARRAY_SIZE(iwl4965_eeprom_band_4) +
5271 ARRAY_SIZE(iwl4965_eeprom_band_5);
b481de9c
ZY
5272
5273 IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
5274
bb8c093b 5275 priv->channel_info = kzalloc(sizeof(struct iwl4965_channel_info) *
b481de9c
ZY
5276 priv->channel_count, GFP_KERNEL);
5277 if (!priv->channel_info) {
5278 IWL_ERROR("Could not allocate channel_info\n");
5279 priv->channel_count = 0;
5280 return -ENOMEM;
5281 }
5282
5283 ch_info = priv->channel_info;
5284
5285 /* Loop through the 5 EEPROM bands adding them in order to the
5286 * channel map we maintain (that contains additional information than
5287 * what just in the EEPROM) */
5288 for (band = 1; band <= 5; band++) {
5289
bb8c093b 5290 iwl4965_init_band_reference(priv, band, &eeprom_ch_count,
b481de9c
ZY
5291 &eeprom_ch_info, &eeprom_ch_index);
5292
5293 /* Loop through each band adding each of the channels */
5294 for (ch = 0; ch < eeprom_ch_count; ch++) {
5295 ch_info->channel = eeprom_ch_index[ch];
8318d78a
JB
5296 ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
5297 IEEE80211_BAND_5GHZ;
b481de9c
ZY
5298
5299 /* permanently store EEPROM's channel regulatory flags
5300 * and max power in channel info database. */
5301 ch_info->eeprom = eeprom_ch_info[ch];
5302
5303 /* Copy the run-time flags so they are there even on
5304 * invalid channels */
5305 ch_info->flags = eeprom_ch_info[ch].flags;
5306
5307 if (!(is_channel_valid(ch_info))) {
5308 IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
5309 "No traffic\n",
5310 ch_info->channel,
5311 ch_info->flags,
5312 is_channel_a_band(ch_info) ?
5313 "5.2" : "2.4");
5314 ch_info++;
5315 continue;
5316 }
5317
5318 /* Initialize regulatory-based run-time data */
5319 ch_info->max_power_avg = ch_info->curr_txpow =
5320 eeprom_ch_info[ch].max_power_avg;
5321 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
5322 ch_info->min_power = 0;
5323
8211ef78 5324 IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s%s(0x%02x"
b481de9c
ZY
5325 " %ddBm): Ad-Hoc %ssupported\n",
5326 ch_info->channel,
5327 is_channel_a_band(ch_info) ?
5328 "5.2" : "2.4",
8211ef78 5329 CHECK_AND_PRINT(VALID),
b481de9c
ZY
5330 CHECK_AND_PRINT(IBSS),
5331 CHECK_AND_PRINT(ACTIVE),
5332 CHECK_AND_PRINT(RADAR),
5333 CHECK_AND_PRINT(WIDE),
5334 CHECK_AND_PRINT(NARROW),
5335 CHECK_AND_PRINT(DFS),
5336 eeprom_ch_info[ch].flags,
5337 eeprom_ch_info[ch].max_power_avg,
5338 ((eeprom_ch_info[ch].
5339 flags & EEPROM_CHANNEL_IBSS)
5340 && !(eeprom_ch_info[ch].
5341 flags & EEPROM_CHANNEL_RADAR))
5342 ? "" : "not ");
5343
5344 /* Set the user_txpower_limit to the highest power
5345 * supported by any channel */
5346 if (eeprom_ch_info[ch].max_power_avg >
5347 priv->user_txpower_limit)
5348 priv->user_txpower_limit =
5349 eeprom_ch_info[ch].max_power_avg;
5350
5351 ch_info++;
5352 }
5353 }
5354
6440adb5 5355 /* Two additional EEPROM bands for 2.4 and 5 GHz FAT channels */
b481de9c 5356 for (band = 6; band <= 7; band++) {
8318d78a 5357 enum ieee80211_band ieeeband;
b481de9c
ZY
5358 u8 fat_extension_chan;
5359
bb8c093b 5360 iwl4965_init_band_reference(priv, band, &eeprom_ch_count,
b481de9c
ZY
5361 &eeprom_ch_info, &eeprom_ch_index);
5362
6440adb5 5363 /* EEPROM band 6 is 2.4, band 7 is 5 GHz */
8318d78a 5364 ieeeband = (band == 6) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
6440adb5 5365
b481de9c
ZY
5366 /* Loop through each band adding each of the channels */
5367 for (ch = 0; ch < eeprom_ch_count; ch++) {
5368
5369 if ((band == 6) &&
5370 ((eeprom_ch_index[ch] == 5) ||
5371 (eeprom_ch_index[ch] == 6) ||
5372 (eeprom_ch_index[ch] == 7)))
5373 fat_extension_chan = HT_IE_EXT_CHANNEL_MAX;
5374 else
5375 fat_extension_chan = HT_IE_EXT_CHANNEL_ABOVE;
5376
6440adb5 5377 /* Set up driver's info for lower half */
8318d78a 5378 iwl4965_set_fat_chan_info(priv, ieeeband,
b481de9c
ZY
5379 eeprom_ch_index[ch],
5380 &(eeprom_ch_info[ch]),
5381 fat_extension_chan);
5382
6440adb5 5383 /* Set up driver's info for upper half */
8318d78a 5384 iwl4965_set_fat_chan_info(priv, ieeeband,
b481de9c
ZY
5385 (eeprom_ch_index[ch] + 4),
5386 &(eeprom_ch_info[ch]),
5387 HT_IE_EXT_CHANNEL_BELOW);
5388 }
5389 }
5390
5391 return 0;
5392}
5393
849e0dce
RC
5394/*
5395 * iwl4965_free_channel_map - undo allocations in iwl4965_init_channel_map
5396 */
5397static void iwl4965_free_channel_map(struct iwl4965_priv *priv)
5398{
5399 kfree(priv->channel_info);
5400 priv->channel_count = 0;
5401}
5402
b481de9c
ZY
5403/* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
5404 * sending probe req. This should be set long enough to hear probe responses
5405 * from more than one AP. */
5406#define IWL_ACTIVE_DWELL_TIME_24 (20) /* all times in msec */
5407#define IWL_ACTIVE_DWELL_TIME_52 (10)
5408
5409/* For faster active scanning, scan will move to the next channel if fewer than
5410 * PLCP_QUIET_THRESH packets are heard on this channel within
5411 * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
5412 * time if it's a quiet channel (nothing responded to our probe, and there's
5413 * no other traffic).
5414 * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
5415#define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
5416#define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(5) /* msec */
5417
5418/* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
5419 * Must be set longer than active dwell time.
5420 * For the most reliable scan, set > AP beacon interval (typically 100msec). */
5421#define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
5422#define IWL_PASSIVE_DWELL_TIME_52 (10)
5423#define IWL_PASSIVE_DWELL_BASE (100)
5424#define IWL_CHANNEL_TUNE_TIME 5
5425
8318d78a
JB
5426static inline u16 iwl4965_get_active_dwell_time(struct iwl4965_priv *priv,
5427 enum ieee80211_band band)
b481de9c 5428{
8318d78a 5429 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY
5430 return IWL_ACTIVE_DWELL_TIME_52;
5431 else
5432 return IWL_ACTIVE_DWELL_TIME_24;
5433}
5434
8318d78a
JB
5435static u16 iwl4965_get_passive_dwell_time(struct iwl4965_priv *priv,
5436 enum ieee80211_band band)
b481de9c 5437{
8318d78a
JB
5438 u16 active = iwl4965_get_active_dwell_time(priv, band);
5439 u16 passive = (band != IEEE80211_BAND_5GHZ) ?
b481de9c
ZY
5440 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
5441 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
5442
bb8c093b 5443 if (iwl4965_is_associated(priv)) {
b481de9c
ZY
5444 /* If we're associated, we clamp the maximum passive
5445 * dwell time to be 98% of the beacon interval (minus
5446 * 2 * channel tune time) */
5447 passive = priv->beacon_int;
5448 if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
5449 passive = IWL_PASSIVE_DWELL_BASE;
5450 passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
5451 }
5452
5453 if (passive <= active)
5454 passive = active + 1;
5455
5456 return passive;
5457}
5458
8318d78a
JB
5459static int iwl4965_get_channels_for_scan(struct iwl4965_priv *priv,
5460 enum ieee80211_band band,
b481de9c 5461 u8 is_active, u8 direct_mask,
bb8c093b 5462 struct iwl4965_scan_channel *scan_ch)
b481de9c
ZY
5463{
5464 const struct ieee80211_channel *channels = NULL;
8318d78a 5465 const struct ieee80211_supported_band *sband;
bb8c093b 5466 const struct iwl4965_channel_info *ch_info;
b481de9c
ZY
5467 u16 passive_dwell = 0;
5468 u16 active_dwell = 0;
5469 int added, i;
5470
8318d78a
JB
5471 sband = iwl4965_get_hw_mode(priv, band);
5472 if (!sband)
b481de9c
ZY
5473 return 0;
5474
8318d78a 5475 channels = sband->channels;
b481de9c 5476
8318d78a
JB
5477 active_dwell = iwl4965_get_active_dwell_time(priv, band);
5478 passive_dwell = iwl4965_get_passive_dwell_time(priv, band);
b481de9c 5479
8318d78a
JB
5480 for (i = 0, added = 0; i < sband->n_channels; i++) {
5481 if (ieee80211_frequency_to_channel(channels[i].center_freq) ==
b481de9c 5482 le16_to_cpu(priv->active_rxon.channel)) {
bb8c093b 5483 if (iwl4965_is_associated(priv)) {
b481de9c
ZY
5484 IWL_DEBUG_SCAN
5485 ("Skipping current channel %d\n",
5486 le16_to_cpu(priv->active_rxon.channel));
5487 continue;
5488 }
5489 } else if (priv->only_active_channel)
5490 continue;
5491
8318d78a 5492 scan_ch->channel = ieee80211_frequency_to_channel(channels[i].center_freq);
b481de9c 5493
8318d78a 5494 ch_info = iwl4965_get_channel_info(priv, band,
9fbab516 5495 scan_ch->channel);
b481de9c
ZY
5496 if (!is_channel_valid(ch_info)) {
5497 IWL_DEBUG_SCAN("Channel %d is INVALID for this SKU.\n",
5498 scan_ch->channel);
5499 continue;
5500 }
5501
5502 if (!is_active || is_channel_passive(ch_info) ||
8318d78a 5503 (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN))
b481de9c
ZY
5504 scan_ch->type = 0; /* passive */
5505 else
5506 scan_ch->type = 1; /* active */
5507
5508 if (scan_ch->type & 1)
5509 scan_ch->type |= (direct_mask << 1);
5510
5511 if (is_channel_narrow(ch_info))
5512 scan_ch->type |= (1 << 7);
5513
5514 scan_ch->active_dwell = cpu_to_le16(active_dwell);
5515 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
5516
9fbab516 5517 /* Set txpower levels to defaults */
b481de9c
ZY
5518 scan_ch->tpc.dsp_atten = 110;
5519 /* scan_pwr_info->tpc.dsp_atten; */
5520
5521 /*scan_pwr_info->tpc.tx_gain; */
8318d78a 5522 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY
5523 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
5524 else {
5525 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
5526 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
9fbab516 5527 * power level:
8a1b0245 5528 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
b481de9c
ZY
5529 */
5530 }
5531
5532 IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
5533 scan_ch->channel,
5534 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
5535 (scan_ch->type & 1) ?
5536 active_dwell : passive_dwell);
5537
5538 scan_ch++;
5539 added++;
5540 }
5541
5542 IWL_DEBUG_SCAN("total channels to scan %d \n", added);
5543 return added;
5544}
5545
bb8c093b 5546static void iwl4965_init_hw_rates(struct iwl4965_priv *priv,
b481de9c
ZY
5547 struct ieee80211_rate *rates)
5548{
5549 int i;
5550
5551 for (i = 0; i < IWL_RATE_COUNT; i++) {
8318d78a
JB
5552 rates[i].bitrate = iwl4965_rates[i].ieee * 5;
5553 rates[i].hw_value = i; /* Rate scaling will work on indexes */
5554 rates[i].hw_value_short = i;
5555 rates[i].flags = 0;
5556 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
b481de9c 5557 /*
8318d78a 5558 * If CCK != 1M then set short preamble rate flag.
b481de9c 5559 */
bb8c093b 5560 rates[i].flags |= (iwl4965_rates[i].plcp == 10) ?
8318d78a 5561 0 : IEEE80211_RATE_SHORT_PREAMBLE;
b481de9c 5562 }
b481de9c 5563 }
b481de9c
ZY
5564}
5565
5566/**
bb8c093b 5567 * iwl4965_init_geos - Initialize mac80211's geo/channel info based from eeprom
b481de9c 5568 */
bb8c093b 5569static int iwl4965_init_geos(struct iwl4965_priv *priv)
b481de9c 5570{
bb8c093b 5571 struct iwl4965_channel_info *ch;
8211ef78 5572 struct ieee80211_supported_band *sband;
b481de9c
ZY
5573 struct ieee80211_channel *channels;
5574 struct ieee80211_channel *geo_ch;
5575 struct ieee80211_rate *rates;
5576 int i = 0;
b481de9c 5577
8318d78a
JB
5578 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
5579 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
b481de9c
ZY
5580 IWL_DEBUG_INFO("Geography modes already initialized.\n");
5581 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
5582 return 0;
5583 }
5584
b481de9c
ZY
5585 channels = kzalloc(sizeof(struct ieee80211_channel) *
5586 priv->channel_count, GFP_KERNEL);
8318d78a 5587 if (!channels)
b481de9c 5588 return -ENOMEM;
b481de9c 5589
8211ef78 5590 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
b481de9c
ZY
5591 GFP_KERNEL);
5592 if (!rates) {
b481de9c
ZY
5593 kfree(channels);
5594 return -ENOMEM;
5595 }
5596
b481de9c 5597 /* 5.2GHz channels start after the 2.4GHz channels */
8211ef78
TW
5598 sband = &priv->bands[IEEE80211_BAND_5GHZ];
5599 sband->channels = &channels[ARRAY_SIZE(iwl4965_eeprom_band_1)];
5600 /* just OFDM */
5601 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
5602 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
8318d78a 5603
8211ef78 5604 iwl4965_init_ht_hw_capab(&sband->ht_info, IEEE80211_BAND_5GHZ);
78330fdd 5605
8211ef78
TW
5606 sband = &priv->bands[IEEE80211_BAND_2GHZ];
5607 sband->channels = channels;
5608 /* OFDM & CCK */
5609 sband->bitrates = rates;
5610 sband->n_bitrates = IWL_RATE_COUNT;
b481de9c 5611
8211ef78 5612 iwl4965_init_ht_hw_capab(&sband->ht_info, IEEE80211_BAND_2GHZ);
78330fdd 5613
b481de9c
ZY
5614 priv->ieee_channels = channels;
5615 priv->ieee_rates = rates;
5616
bb8c093b 5617 iwl4965_init_hw_rates(priv, rates);
b481de9c 5618
8211ef78 5619 for (i = 0; i < priv->channel_count; i++) {
b481de9c
ZY
5620 ch = &priv->channel_info[i];
5621
8211ef78
TW
5622 /* FIXME: might be removed if scan is OK */
5623 if (!is_channel_valid(ch))
b481de9c 5624 continue;
b481de9c 5625
8211ef78
TW
5626 if (is_channel_a_band(ch))
5627 sband = &priv->bands[IEEE80211_BAND_5GHZ];
5628 else
5629 sband = &priv->bands[IEEE80211_BAND_2GHZ];
b481de9c 5630
8211ef78
TW
5631 geo_ch = &sband->channels[sband->n_channels++];
5632
5633 geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
8318d78a
JB
5634 geo_ch->max_power = ch->max_power_avg;
5635 geo_ch->max_antenna_gain = 0xff;
7b72304d 5636 geo_ch->hw_value = ch->channel;
b481de9c
ZY
5637
5638 if (is_channel_valid(ch)) {
8318d78a
JB
5639 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
5640 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
b481de9c 5641
8318d78a
JB
5642 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
5643 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
b481de9c
ZY
5644
5645 if (ch->flags & EEPROM_CHANNEL_RADAR)
8318d78a 5646 geo_ch->flags |= IEEE80211_CHAN_RADAR;
b481de9c
ZY
5647
5648 if (ch->max_power_avg > priv->max_channel_txpower_limit)
5649 priv->max_channel_txpower_limit =
5650 ch->max_power_avg;
8211ef78 5651 } else {
8318d78a 5652 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
8211ef78
TW
5653 }
5654
5655 /* Save flags for reg domain usage */
5656 geo_ch->orig_flags = geo_ch->flags;
5657
5658 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
5659 ch->channel, geo_ch->center_freq,
5660 is_channel_a_band(ch) ? "5.2" : "2.4",
5661 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
5662 "restricted" : "valid",
5663 geo_ch->flags);
b481de9c
ZY
5664 }
5665
8318d78a 5666 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) && priv->is_abg) {
b481de9c
ZY
5667 printk(KERN_INFO DRV_NAME
5668 ": Incorrectly detected BG card as ABG. Please send "
5669 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
5670 priv->pci_dev->device, priv->pci_dev->subsystem_device);
5671 priv->is_abg = 0;
5672 }
5673
5674 printk(KERN_INFO DRV_NAME
5675 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
8318d78a
JB
5676 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
5677 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
b481de9c 5678
8318d78a
JB
5679 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->bands[IEEE80211_BAND_2GHZ];
5680 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &priv->bands[IEEE80211_BAND_5GHZ];
b481de9c 5681
b481de9c
ZY
5682 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
5683
5684 return 0;
5685}
5686
849e0dce
RC
5687/*
5688 * iwl4965_free_geos - undo allocations in iwl4965_init_geos
5689 */
5690static void iwl4965_free_geos(struct iwl4965_priv *priv)
5691{
849e0dce
RC
5692 kfree(priv->ieee_channels);
5693 kfree(priv->ieee_rates);
5694 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
5695}
5696
b481de9c
ZY
5697/******************************************************************************
5698 *
5699 * uCode download functions
5700 *
5701 ******************************************************************************/
5702
bb8c093b 5703static void iwl4965_dealloc_ucode_pci(struct iwl4965_priv *priv)
b481de9c 5704{
98c92211
TW
5705 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
5706 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
5707 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
5708 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
5709 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
5710 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY
5711}
5712
5713/**
bb8c093b 5714 * iwl4965_verify_inst_full - verify runtime uCode image in card vs. host,
b481de9c
ZY
5715 * looking at all data.
5716 */
4fd1f841 5717static int iwl4965_verify_inst_full(struct iwl4965_priv *priv, __le32 *image,
9fbab516 5718 u32 len)
b481de9c
ZY
5719{
5720 u32 val;
5721 u32 save_len = len;
5722 int rc = 0;
5723 u32 errcnt;
5724
5725 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5726
bb8c093b 5727 rc = iwl4965_grab_nic_access(priv);
b481de9c
ZY
5728 if (rc)
5729 return rc;
5730
bb8c093b 5731 iwl4965_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
b481de9c
ZY
5732
5733 errcnt = 0;
5734 for (; len > 0; len -= sizeof(u32), image++) {
5735 /* read data comes through single port, auto-incr addr */
5736 /* NOTE: Use the debugless read so we don't flood kernel log
5737 * if IWL_DL_IO is set */
bb8c093b 5738 val = _iwl4965_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY
5739 if (val != le32_to_cpu(*image)) {
5740 IWL_ERROR("uCode INST section is invalid at "
5741 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5742 save_len - len, val, le32_to_cpu(*image));
5743 rc = -EIO;
5744 errcnt++;
5745 if (errcnt >= 20)
5746 break;
5747 }
5748 }
5749
bb8c093b 5750 iwl4965_release_nic_access(priv);
b481de9c
ZY
5751
5752 if (!errcnt)
5753 IWL_DEBUG_INFO
5754 ("ucode image in INSTRUCTION memory is good\n");
5755
5756 return rc;
5757}
5758
5759
5760/**
bb8c093b 5761 * iwl4965_verify_inst_sparse - verify runtime uCode image in card vs. host,
b481de9c
ZY
5762 * using sample data 100 bytes apart. If these sample points are good,
5763 * it's a pretty good bet that everything between them is good, too.
5764 */
bb8c093b 5765static int iwl4965_verify_inst_sparse(struct iwl4965_priv *priv, __le32 *image, u32 len)
b481de9c
ZY
5766{
5767 u32 val;
5768 int rc = 0;
5769 u32 errcnt = 0;
5770 u32 i;
5771
5772 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5773
bb8c093b 5774 rc = iwl4965_grab_nic_access(priv);
b481de9c
ZY
5775 if (rc)
5776 return rc;
5777
5778 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
5779 /* read data comes through single port, auto-incr addr */
5780 /* NOTE: Use the debugless read so we don't flood kernel log
5781 * if IWL_DL_IO is set */
bb8c093b 5782 iwl4965_write_direct32(priv, HBUS_TARG_MEM_RADDR,
b481de9c 5783 i + RTC_INST_LOWER_BOUND);
bb8c093b 5784 val = _iwl4965_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY
5785 if (val != le32_to_cpu(*image)) {
5786#if 0 /* Enable this if you want to see details */
5787 IWL_ERROR("uCode INST section is invalid at "
5788 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5789 i, val, *image);
5790#endif
5791 rc = -EIO;
5792 errcnt++;
5793 if (errcnt >= 3)
5794 break;
5795 }
5796 }
5797
bb8c093b 5798 iwl4965_release_nic_access(priv);
b481de9c
ZY
5799
5800 return rc;
5801}
5802
5803
5804/**
bb8c093b 5805 * iwl4965_verify_ucode - determine which instruction image is in SRAM,
b481de9c
ZY
5806 * and verify its contents
5807 */
bb8c093b 5808static int iwl4965_verify_ucode(struct iwl4965_priv *priv)
b481de9c
ZY
5809{
5810 __le32 *image;
5811 u32 len;
5812 int rc = 0;
5813
5814 /* Try bootstrap */
5815 image = (__le32 *)priv->ucode_boot.v_addr;
5816 len = priv->ucode_boot.len;
bb8c093b 5817 rc = iwl4965_verify_inst_sparse(priv, image, len);
b481de9c
ZY
5818 if (rc == 0) {
5819 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
5820 return 0;
5821 }
5822
5823 /* Try initialize */
5824 image = (__le32 *)priv->ucode_init.v_addr;
5825 len = priv->ucode_init.len;
bb8c093b 5826 rc = iwl4965_verify_inst_sparse(priv, image, len);
b481de9c
ZY
5827 if (rc == 0) {
5828 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
5829 return 0;
5830 }
5831
5832 /* Try runtime/protocol */
5833 image = (__le32 *)priv->ucode_code.v_addr;
5834 len = priv->ucode_code.len;
bb8c093b 5835 rc = iwl4965_verify_inst_sparse(priv, image, len);
b481de9c
ZY
5836 if (rc == 0) {
5837 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
5838 return 0;
5839 }
5840
5841 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
5842
9fbab516
BC
5843 /* Since nothing seems to match, show first several data entries in
5844 * instruction SRAM, so maybe visual inspection will give a clue.
5845 * Selection of bootstrap image (vs. other images) is arbitrary. */
b481de9c
ZY
5846 image = (__le32 *)priv->ucode_boot.v_addr;
5847 len = priv->ucode_boot.len;
bb8c093b 5848 rc = iwl4965_verify_inst_full(priv, image, len);
b481de9c
ZY
5849
5850 return rc;
5851}
5852
5853
5854/* check contents of special bootstrap uCode SRAM */
bb8c093b 5855static int iwl4965_verify_bsm(struct iwl4965_priv *priv)
b481de9c
ZY
5856{
5857 __le32 *image = priv->ucode_boot.v_addr;
5858 u32 len = priv->ucode_boot.len;
5859 u32 reg;
5860 u32 val;
5861
5862 IWL_DEBUG_INFO("Begin verify bsm\n");
5863
5864 /* verify BSM SRAM contents */
bb8c093b 5865 val = iwl4965_read_prph(priv, BSM_WR_DWCOUNT_REG);
b481de9c
ZY
5866 for (reg = BSM_SRAM_LOWER_BOUND;
5867 reg < BSM_SRAM_LOWER_BOUND + len;
5868 reg += sizeof(u32), image ++) {
bb8c093b 5869 val = iwl4965_read_prph(priv, reg);
b481de9c
ZY
5870 if (val != le32_to_cpu(*image)) {
5871 IWL_ERROR("BSM uCode verification failed at "
5872 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
5873 BSM_SRAM_LOWER_BOUND,
5874 reg - BSM_SRAM_LOWER_BOUND, len,
5875 val, le32_to_cpu(*image));
5876 return -EIO;
5877 }
5878 }
5879
5880 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
5881
5882 return 0;
5883}
5884
5885/**
bb8c093b 5886 * iwl4965_load_bsm - Load bootstrap instructions
b481de9c
ZY
5887 *
5888 * BSM operation:
5889 *
5890 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
5891 * in special SRAM that does not power down during RFKILL. When powering back
5892 * up after power-saving sleeps (or during initial uCode load), the BSM loads
5893 * the bootstrap program into the on-board processor, and starts it.
5894 *
5895 * The bootstrap program loads (via DMA) instructions and data for a new
5896 * program from host DRAM locations indicated by the host driver in the
5897 * BSM_DRAM_* registers. Once the new program is loaded, it starts
5898 * automatically.
5899 *
5900 * When initializing the NIC, the host driver points the BSM to the
5901 * "initialize" uCode image. This uCode sets up some internal data, then
5902 * notifies host via "initialize alive" that it is complete.
5903 *
5904 * The host then replaces the BSM_DRAM_* pointer values to point to the
5905 * normal runtime uCode instructions and a backup uCode data cache buffer
5906 * (filled initially with starting data values for the on-board processor),
5907 * then triggers the "initialize" uCode to load and launch the runtime uCode,
5908 * which begins normal operation.
5909 *
5910 * When doing a power-save shutdown, runtime uCode saves data SRAM into
5911 * the backup data cache in DRAM before SRAM is powered down.
5912 *
5913 * When powering back up, the BSM loads the bootstrap program. This reloads
5914 * the runtime uCode instructions and the backup data cache into SRAM,
5915 * and re-launches the runtime uCode from where it left off.
5916 */
bb8c093b 5917static int iwl4965_load_bsm(struct iwl4965_priv *priv)
b481de9c
ZY
5918{
5919 __le32 *image = priv->ucode_boot.v_addr;
5920 u32 len = priv->ucode_boot.len;
5921 dma_addr_t pinst;
5922 dma_addr_t pdata;
5923 u32 inst_len;
5924 u32 data_len;
5925 int rc;
5926 int i;
5927 u32 done;
5928 u32 reg_offset;
5929
5930 IWL_DEBUG_INFO("Begin load bsm\n");
5931
5932 /* make sure bootstrap program is no larger than BSM's SRAM size */
5933 if (len > IWL_MAX_BSM_SIZE)
5934 return -EINVAL;
5935
5936 /* Tell bootstrap uCode where to find the "Initialize" uCode
9fbab516 5937 * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
bb8c093b 5938 * NOTE: iwl4965_initialize_alive_start() will replace these values,
b481de9c
ZY
5939 * after the "initialize" uCode has run, to point to
5940 * runtime/protocol instructions and backup data cache. */
5941 pinst = priv->ucode_init.p_addr >> 4;
5942 pdata = priv->ucode_init_data.p_addr >> 4;
5943 inst_len = priv->ucode_init.len;
5944 data_len = priv->ucode_init_data.len;
5945
bb8c093b 5946 rc = iwl4965_grab_nic_access(priv);
b481de9c
ZY
5947 if (rc)
5948 return rc;
5949
bb8c093b
CH
5950 iwl4965_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5951 iwl4965_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5952 iwl4965_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
5953 iwl4965_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
b481de9c
ZY
5954
5955 /* Fill BSM memory with bootstrap instructions */
5956 for (reg_offset = BSM_SRAM_LOWER_BOUND;
5957 reg_offset < BSM_SRAM_LOWER_BOUND + len;
5958 reg_offset += sizeof(u32), image++)
bb8c093b 5959 _iwl4965_write_prph(priv, reg_offset,
b481de9c
ZY
5960 le32_to_cpu(*image));
5961
bb8c093b 5962 rc = iwl4965_verify_bsm(priv);
b481de9c 5963 if (rc) {
bb8c093b 5964 iwl4965_release_nic_access(priv);
b481de9c
ZY
5965 return rc;
5966 }
5967
5968 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
bb8c093b
CH
5969 iwl4965_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
5970 iwl4965_write_prph(priv, BSM_WR_MEM_DST_REG,
b481de9c 5971 RTC_INST_LOWER_BOUND);
bb8c093b 5972 iwl4965_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
b481de9c
ZY
5973
5974 /* Load bootstrap code into instruction SRAM now,
5975 * to prepare to load "initialize" uCode */
bb8c093b 5976 iwl4965_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY
5977 BSM_WR_CTRL_REG_BIT_START);
5978
5979 /* Wait for load of bootstrap uCode to finish */
5980 for (i = 0; i < 100; i++) {
bb8c093b 5981 done = iwl4965_read_prph(priv, BSM_WR_CTRL_REG);
b481de9c
ZY
5982 if (!(done & BSM_WR_CTRL_REG_BIT_START))
5983 break;
5984 udelay(10);
5985 }
5986 if (i < 100)
5987 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
5988 else {
5989 IWL_ERROR("BSM write did not complete!\n");
5990 return -EIO;
5991 }
5992
5993 /* Enable future boot loads whenever power management unit triggers it
5994 * (e.g. when powering back up after power-save shutdown) */
bb8c093b 5995 iwl4965_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY
5996 BSM_WR_CTRL_REG_BIT_START_EN);
5997
bb8c093b 5998 iwl4965_release_nic_access(priv);
b481de9c
ZY
5999
6000 return 0;
6001}
6002
bb8c093b 6003static void iwl4965_nic_start(struct iwl4965_priv *priv)
b481de9c
ZY
6004{
6005 /* Remove all resets to allow NIC to operate */
bb8c093b 6006 iwl4965_write32(priv, CSR_RESET, 0);
b481de9c
ZY
6007}
6008
90e759d1 6009
b481de9c 6010/**
bb8c093b 6011 * iwl4965_read_ucode - Read uCode images from disk file.
b481de9c
ZY
6012 *
6013 * Copy into buffers for card to fetch via bus-mastering
6014 */
bb8c093b 6015static int iwl4965_read_ucode(struct iwl4965_priv *priv)
b481de9c 6016{
bb8c093b 6017 struct iwl4965_ucode *ucode;
90e759d1 6018 int ret;
b481de9c
ZY
6019 const struct firmware *ucode_raw;
6020 const char *name = "iwlwifi-4965" IWL4965_UCODE_API ".ucode";
6021 u8 *src;
6022 size_t len;
6023 u32 ver, inst_size, data_size, init_size, init_data_size, boot_size;
6024
6025 /* Ask kernel firmware_class module to get the boot firmware off disk.
6026 * request_firmware() is synchronous, file is in memory on return. */
90e759d1
TW
6027 ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev);
6028 if (ret < 0) {
6029 IWL_ERROR("%s firmware file req failed: Reason %d\n",
6030 name, ret);
b481de9c
ZY
6031 goto error;
6032 }
6033
6034 IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
6035 name, ucode_raw->size);
6036
6037 /* Make sure that we got at least our header! */
6038 if (ucode_raw->size < sizeof(*ucode)) {
6039 IWL_ERROR("File size way too small!\n");
90e759d1 6040 ret = -EINVAL;
b481de9c
ZY
6041 goto err_release;
6042 }
6043
6044 /* Data from ucode file: header followed by uCode images */
6045 ucode = (void *)ucode_raw->data;
6046
6047 ver = le32_to_cpu(ucode->ver);
6048 inst_size = le32_to_cpu(ucode->inst_size);
6049 data_size = le32_to_cpu(ucode->data_size);
6050 init_size = le32_to_cpu(ucode->init_size);
6051 init_data_size = le32_to_cpu(ucode->init_data_size);
6052 boot_size = le32_to_cpu(ucode->boot_size);
6053
6054 IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver);
6055 IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n",
6056 inst_size);
6057 IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n",
6058 data_size);
6059 IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n",
6060 init_size);
6061 IWL_DEBUG_INFO("f/w package hdr init data size = %u\n",
6062 init_data_size);
6063 IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n",
6064 boot_size);
6065
6066 /* Verify size of file vs. image size info in file's header */
6067 if (ucode_raw->size < sizeof(*ucode) +
6068 inst_size + data_size + init_size +
6069 init_data_size + boot_size) {
6070
6071 IWL_DEBUG_INFO("uCode file size %d too small\n",
6072 (int)ucode_raw->size);
90e759d1 6073 ret = -EINVAL;
b481de9c
ZY
6074 goto err_release;
6075 }
6076
6077 /* Verify that uCode images will fit in card's SRAM */
6078 if (inst_size > IWL_MAX_INST_SIZE) {
90e759d1
TW
6079 IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
6080 inst_size);
6081 ret = -EINVAL;
b481de9c
ZY
6082 goto err_release;
6083 }
6084
6085 if (data_size > IWL_MAX_DATA_SIZE) {
90e759d1
TW
6086 IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
6087 data_size);
6088 ret = -EINVAL;
b481de9c
ZY
6089 goto err_release;
6090 }
6091 if (init_size > IWL_MAX_INST_SIZE) {
6092 IWL_DEBUG_INFO
90e759d1
TW
6093 ("uCode init instr len %d too large to fit in\n",
6094 init_size);
6095 ret = -EINVAL;
b481de9c
ZY
6096 goto err_release;
6097 }
6098 if (init_data_size > IWL_MAX_DATA_SIZE) {
6099 IWL_DEBUG_INFO
90e759d1
TW
6100 ("uCode init data len %d too large to fit in\n",
6101 init_data_size);
6102 ret = -EINVAL;
b481de9c
ZY
6103 goto err_release;
6104 }
6105 if (boot_size > IWL_MAX_BSM_SIZE) {
6106 IWL_DEBUG_INFO
90e759d1
TW
6107 ("uCode boot instr len %d too large to fit in\n",
6108 boot_size);
6109 ret = -EINVAL;
b481de9c
ZY
6110 goto err_release;
6111 }
6112
6113 /* Allocate ucode buffers for card's bus-master loading ... */
6114
6115 /* Runtime instructions and 2 copies of data:
6116 * 1) unmodified from disk
6117 * 2) backup cache for save/restore during power-downs */
6118 priv->ucode_code.len = inst_size;
98c92211 6119 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY
6120
6121 priv->ucode_data.len = data_size;
98c92211 6122 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY
6123
6124 priv->ucode_data_backup.len = data_size;
98c92211 6125 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c
ZY
6126
6127 /* Initialization instructions and data */
90e759d1
TW
6128 if (init_size && init_data_size) {
6129 priv->ucode_init.len = init_size;
98c92211 6130 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW
6131
6132 priv->ucode_init_data.len = init_data_size;
98c92211 6133 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW
6134
6135 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
6136 goto err_pci_alloc;
6137 }
b481de9c
ZY
6138
6139 /* Bootstrap (instructions only, no data) */
90e759d1
TW
6140 if (boot_size) {
6141 priv->ucode_boot.len = boot_size;
98c92211 6142 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 6143
90e759d1
TW
6144 if (!priv->ucode_boot.v_addr)
6145 goto err_pci_alloc;
6146 }
b481de9c
ZY
6147
6148 /* Copy images into buffers for card's bus-master reads ... */
6149
6150 /* Runtime instructions (first block of data in file) */
6151 src = &ucode->data[0];
6152 len = priv->ucode_code.len;
90e759d1 6153 IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c
ZY
6154 memcpy(priv->ucode_code.v_addr, src, len);
6155 IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
6156 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
6157
6158 /* Runtime data (2nd block)
bb8c093b 6159 * NOTE: Copy into backup buffer will be done in iwl4965_up() */
b481de9c
ZY
6160 src = &ucode->data[inst_size];
6161 len = priv->ucode_data.len;
90e759d1 6162 IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY
6163 memcpy(priv->ucode_data.v_addr, src, len);
6164 memcpy(priv->ucode_data_backup.v_addr, src, len);
6165
6166 /* Initialization instructions (3rd block) */
6167 if (init_size) {
6168 src = &ucode->data[inst_size + data_size];
6169 len = priv->ucode_init.len;
90e759d1
TW
6170 IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
6171 len);
b481de9c
ZY
6172 memcpy(priv->ucode_init.v_addr, src, len);
6173 }
6174
6175 /* Initialization data (4th block) */
6176 if (init_data_size) {
6177 src = &ucode->data[inst_size + data_size + init_size];
6178 len = priv->ucode_init_data.len;
90e759d1
TW
6179 IWL_DEBUG_INFO("Copying (but not loading) init data len %Zd\n",
6180 len);
b481de9c
ZY
6181 memcpy(priv->ucode_init_data.v_addr, src, len);
6182 }
6183
6184 /* Bootstrap instructions (5th block) */
6185 src = &ucode->data[inst_size + data_size + init_size + init_data_size];
6186 len = priv->ucode_boot.len;
90e759d1 6187 IWL_DEBUG_INFO("Copying (but not loading) boot instr len %Zd\n", len);
b481de9c
ZY
6188 memcpy(priv->ucode_boot.v_addr, src, len);
6189
6190 /* We have our copies now, allow OS release its copies */
6191 release_firmware(ucode_raw);
6192 return 0;
6193
6194 err_pci_alloc:
6195 IWL_ERROR("failed to allocate pci memory\n");
90e759d1 6196 ret = -ENOMEM;
bb8c093b 6197 iwl4965_dealloc_ucode_pci(priv);
b481de9c
ZY
6198
6199 err_release:
6200 release_firmware(ucode_raw);
6201
6202 error:
90e759d1 6203 return ret;
b481de9c
ZY
6204}
6205
6206
6207/**
bb8c093b 6208 * iwl4965_set_ucode_ptrs - Set uCode address location
b481de9c
ZY
6209 *
6210 * Tell initialization uCode where to find runtime uCode.
6211 *
6212 * BSM registers initially contain pointers to initialization uCode.
6213 * We need to replace them to load runtime uCode inst and data,
6214 * and to save runtime data when powering down.
6215 */
bb8c093b 6216static int iwl4965_set_ucode_ptrs(struct iwl4965_priv *priv)
b481de9c
ZY
6217{
6218 dma_addr_t pinst;
6219 dma_addr_t pdata;
6220 int rc = 0;
6221 unsigned long flags;
6222
6223 /* bits 35:4 for 4965 */
6224 pinst = priv->ucode_code.p_addr >> 4;
6225 pdata = priv->ucode_data_backup.p_addr >> 4;
6226
6227 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 6228 rc = iwl4965_grab_nic_access(priv);
b481de9c
ZY
6229 if (rc) {
6230 spin_unlock_irqrestore(&priv->lock, flags);
6231 return rc;
6232 }
6233
6234 /* Tell bootstrap uCode where to find image to load */
bb8c093b
CH
6235 iwl4965_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
6236 iwl4965_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
6237 iwl4965_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
b481de9c
ZY
6238 priv->ucode_data.len);
6239
6240 /* Inst bytecount must be last to set up, bit 31 signals uCode
6241 * that all new ptr/size info is in place */
bb8c093b 6242 iwl4965_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
b481de9c
ZY
6243 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
6244
bb8c093b 6245 iwl4965_release_nic_access(priv);
b481de9c
ZY
6246
6247 spin_unlock_irqrestore(&priv->lock, flags);
6248
6249 IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
6250
6251 return rc;
6252}
6253
6254/**
bb8c093b 6255 * iwl4965_init_alive_start - Called after REPLY_ALIVE notification received
b481de9c
ZY
6256 *
6257 * Called after REPLY_ALIVE notification received from "initialize" uCode.
6258 *
6259 * The 4965 "initialize" ALIVE reply contains calibration data for:
6260 * Voltage, temperature, and MIMO tx gain correction, now stored in priv
6261 * (3945 does not contain this data).
6262 *
6263 * Tell "initialize" uCode to go ahead and load the runtime uCode.
6264*/
bb8c093b 6265static void iwl4965_init_alive_start(struct iwl4965_priv *priv)
b481de9c
ZY
6266{
6267 /* Check alive response for "valid" sign from uCode */
6268 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
6269 /* We had an error bringing up the hardware, so take it
6270 * all the way back down so we can try again */
6271 IWL_DEBUG_INFO("Initialize Alive failed.\n");
6272 goto restart;
6273 }
6274
6275 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
6276 * This is a paranoid check, because we would not have gotten the
6277 * "initialize" alive if code weren't properly loaded. */
bb8c093b 6278 if (iwl4965_verify_ucode(priv)) {
b481de9c
ZY
6279 /* Runtime instruction load was bad;
6280 * take it all the way back down so we can try again */
6281 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
6282 goto restart;
6283 }
6284
6285 /* Calculate temperature */
6286 priv->temperature = iwl4965_get_temperature(priv);
6287
6288 /* Send pointers to protocol/runtime uCode image ... init code will
6289 * load and launch runtime uCode, which will send us another "Alive"
6290 * notification. */
6291 IWL_DEBUG_INFO("Initialization Alive received.\n");
bb8c093b 6292 if (iwl4965_set_ucode_ptrs(priv)) {
b481de9c
ZY
6293 /* Runtime instruction load won't happen;
6294 * take it all the way back down so we can try again */
6295 IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
6296 goto restart;
6297 }
6298 return;
6299
6300 restart:
6301 queue_work(priv->workqueue, &priv->restart);
6302}
6303
6304
6305/**
bb8c093b 6306 * iwl4965_alive_start - called after REPLY_ALIVE notification received
b481de9c 6307 * from protocol/runtime uCode (initialization uCode's
bb8c093b 6308 * Alive gets handled by iwl4965_init_alive_start()).
b481de9c 6309 */
bb8c093b 6310static void iwl4965_alive_start(struct iwl4965_priv *priv)
b481de9c
ZY
6311{
6312 int rc = 0;
6313
6314 IWL_DEBUG_INFO("Runtime Alive received.\n");
6315
6316 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
6317 /* We had an error bringing up the hardware, so take it
6318 * all the way back down so we can try again */
6319 IWL_DEBUG_INFO("Alive failed.\n");
6320 goto restart;
6321 }
6322
6323 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
6324 * This is a paranoid check, because we would not have gotten the
6325 * "runtime" alive if code weren't properly loaded. */
bb8c093b 6326 if (iwl4965_verify_ucode(priv)) {
b481de9c
ZY
6327 /* Runtime instruction load was bad;
6328 * take it all the way back down so we can try again */
6329 IWL_DEBUG_INFO("Bad runtime uCode load.\n");
6330 goto restart;
6331 }
6332
bb8c093b 6333 iwl4965_clear_stations_table(priv);
b481de9c
ZY
6334
6335 rc = iwl4965_alive_notify(priv);
6336 if (rc) {
6337 IWL_WARNING("Could not complete ALIVE transition [ntf]: %d\n",
6338 rc);
6339 goto restart;
6340 }
6341
9fbab516 6342 /* After the ALIVE response, we can send host commands to 4965 uCode */
b481de9c
ZY
6343 set_bit(STATUS_ALIVE, &priv->status);
6344
6345 /* Clear out the uCode error bit if it is set */
6346 clear_bit(STATUS_FW_ERROR, &priv->status);
6347
bb8c093b 6348 if (iwl4965_is_rfkill(priv))
b481de9c
ZY
6349 return;
6350
5a66926a 6351 ieee80211_start_queues(priv->hw);
b481de9c
ZY
6352
6353 priv->active_rate = priv->rates_mask;
6354 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
6355
bb8c093b 6356 iwl4965_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
b481de9c 6357
bb8c093b
CH
6358 if (iwl4965_is_associated(priv)) {
6359 struct iwl4965_rxon_cmd *active_rxon =
6360 (struct iwl4965_rxon_cmd *)(&priv->active_rxon);
b481de9c
ZY
6361
6362 memcpy(&priv->staging_rxon, &priv->active_rxon,
6363 sizeof(priv->staging_rxon));
6364 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
6365 } else {
6366 /* Initialize our rx_config data */
bb8c093b 6367 iwl4965_connection_init_rx_config(priv);
b481de9c
ZY
6368 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
6369 }
6370
9fbab516 6371 /* Configure Bluetooth device coexistence support */
bb8c093b 6372 iwl4965_send_bt_config(priv);
b481de9c
ZY
6373
6374 /* Configure the adapter for unassociated operation */
bb8c093b 6375 iwl4965_commit_rxon(priv);
b481de9c
ZY
6376
6377 /* At this point, the NIC is initialized and operational */
6378 priv->notif_missed_beacons = 0;
6379 set_bit(STATUS_READY, &priv->status);
6380
6381 iwl4965_rf_kill_ct_config(priv);
5a66926a 6382
b481de9c 6383 IWL_DEBUG_INFO("ALIVE processing complete.\n");
5a66926a 6384 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY
6385
6386 if (priv->error_recovering)
bb8c093b 6387 iwl4965_error_recovery(priv);
b481de9c
ZY
6388
6389 return;
6390
6391 restart:
6392 queue_work(priv->workqueue, &priv->restart);
6393}
6394
bb8c093b 6395static void iwl4965_cancel_deferred_work(struct iwl4965_priv *priv);
b481de9c 6396
bb8c093b 6397static void __iwl4965_down(struct iwl4965_priv *priv)
b481de9c
ZY
6398{
6399 unsigned long flags;
6400 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
6401 struct ieee80211_conf *conf = NULL;
6402
6403 IWL_DEBUG_INFO(DRV_NAME " is going down\n");
6404
6405 conf = ieee80211_get_hw_conf(priv->hw);
6406
6407 if (!exit_pending)
6408 set_bit(STATUS_EXIT_PENDING, &priv->status);
6409
bb8c093b 6410 iwl4965_clear_stations_table(priv);
b481de9c
ZY
6411
6412 /* Unblock any waiting calls */
6413 wake_up_interruptible_all(&priv->wait_command_queue);
6414
b481de9c
ZY
6415 /* Wipe out the EXIT_PENDING status bit if we are not actually
6416 * exiting the module */
6417 if (!exit_pending)
6418 clear_bit(STATUS_EXIT_PENDING, &priv->status);
6419
6420 /* stop and reset the on-board processor */
bb8c093b 6421 iwl4965_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY
6422
6423 /* tell the device to stop sending interrupts */
bb8c093b 6424 iwl4965_disable_interrupts(priv);
b481de9c
ZY
6425
6426 if (priv->mac80211_registered)
6427 ieee80211_stop_queues(priv->hw);
6428
bb8c093b 6429 /* If we have not previously called iwl4965_init() then
b481de9c 6430 * clear all bits but the RF Kill and SUSPEND bits and return */
bb8c093b 6431 if (!iwl4965_is_init(priv)) {
b481de9c
ZY
6432 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
6433 STATUS_RF_KILL_HW |
6434 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
6435 STATUS_RF_KILL_SW |
9788864e
RC
6436 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
6437 STATUS_GEO_CONFIGURED |
b481de9c
ZY
6438 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
6439 STATUS_IN_SUSPEND;
6440 goto exit;
6441 }
6442
6443 /* ...otherwise clear out all the status bits but the RF Kill and
6444 * SUSPEND bits and continue taking the NIC down. */
6445 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
6446 STATUS_RF_KILL_HW |
6447 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
6448 STATUS_RF_KILL_SW |
9788864e
RC
6449 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
6450 STATUS_GEO_CONFIGURED |
b481de9c
ZY
6451 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
6452 STATUS_IN_SUSPEND |
6453 test_bit(STATUS_FW_ERROR, &priv->status) <<
6454 STATUS_FW_ERROR;
6455
6456 spin_lock_irqsave(&priv->lock, flags);
9fbab516
BC
6457 iwl4965_clear_bit(priv, CSR_GP_CNTRL,
6458 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY
6459 spin_unlock_irqrestore(&priv->lock, flags);
6460
bb8c093b
CH
6461 iwl4965_hw_txq_ctx_stop(priv);
6462 iwl4965_hw_rxq_stop(priv);
b481de9c
ZY
6463
6464 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH
6465 if (!iwl4965_grab_nic_access(priv)) {
6466 iwl4965_write_prph(priv, APMG_CLK_DIS_REG,
b481de9c 6467 APMG_CLK_VAL_DMA_CLK_RQT);
bb8c093b 6468 iwl4965_release_nic_access(priv);
b481de9c
ZY
6469 }
6470 spin_unlock_irqrestore(&priv->lock, flags);
6471
6472 udelay(5);
6473
bb8c093b
CH
6474 iwl4965_hw_nic_stop_master(priv);
6475 iwl4965_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
6476 iwl4965_hw_nic_reset(priv);
b481de9c
ZY
6477
6478 exit:
bb8c093b 6479 memset(&priv->card_alive, 0, sizeof(struct iwl4965_alive_resp));
b481de9c
ZY
6480
6481 if (priv->ibss_beacon)
6482 dev_kfree_skb(priv->ibss_beacon);
6483 priv->ibss_beacon = NULL;
6484
6485 /* clear out any free frames */
bb8c093b 6486 iwl4965_clear_free_frames(priv);
b481de9c
ZY
6487}
6488
bb8c093b 6489static void iwl4965_down(struct iwl4965_priv *priv)
b481de9c
ZY
6490{
6491 mutex_lock(&priv->mutex);
bb8c093b 6492 __iwl4965_down(priv);
b481de9c 6493 mutex_unlock(&priv->mutex);
b24d22b1 6494
bb8c093b 6495 iwl4965_cancel_deferred_work(priv);
b481de9c
ZY
6496}
6497
6498#define MAX_HW_RESTARTS 5
6499
bb8c093b 6500static int __iwl4965_up(struct iwl4965_priv *priv)
b481de9c
ZY
6501{
6502 int rc, i;
b481de9c
ZY
6503
6504 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
6505 IWL_WARNING("Exit pending; will not bring the NIC up\n");
6506 return -EIO;
6507 }
6508
6509 if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
6510 IWL_WARNING("Radio disabled by SW RF kill (module "
6511 "parameter)\n");
e655b9f0
ZY
6512 return -ENODEV;
6513 }
6514
e903fbd4
RC
6515 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
6516 IWL_ERROR("ucode not available for device bringup\n");
6517 return -EIO;
6518 }
6519
e655b9f0
ZY
6520 /* If platform's RF_KILL switch is NOT set to KILL */
6521 if (iwl4965_read32(priv, CSR_GP_CNTRL) &
6522 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
6523 clear_bit(STATUS_RF_KILL_HW, &priv->status);
6524 else {
6525 set_bit(STATUS_RF_KILL_HW, &priv->status);
6526 if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
6527 IWL_WARNING("Radio disabled by HW RF Kill switch\n");
6528 return -ENODEV;
6529 }
b481de9c
ZY
6530 }
6531
bb8c093b 6532 iwl4965_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 6533
bb8c093b 6534 rc = iwl4965_hw_nic_init(priv);
b481de9c
ZY
6535 if (rc) {
6536 IWL_ERROR("Unable to int nic\n");
6537 return rc;
6538 }
6539
6540 /* make sure rfkill handshake bits are cleared */
bb8c093b
CH
6541 iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
6542 iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY
6543 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
6544
6545 /* clear (again), then enable host interrupts */
bb8c093b
CH
6546 iwl4965_write32(priv, CSR_INT, 0xFFFFFFFF);
6547 iwl4965_enable_interrupts(priv);
b481de9c
ZY
6548
6549 /* really make sure rfkill handshake bits are cleared */
bb8c093b
CH
6550 iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
6551 iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
6552
6553 /* Copy original ucode data image from disk into backup cache.
6554 * This will be used to initialize the on-board processor's
6555 * data SRAM for a clean start when the runtime program first loads. */
6556 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 6557 priv->ucode_data.len);
b481de9c 6558
e655b9f0
ZY
6559 /* We return success when we resume from suspend and rf_kill is on. */
6560 if (test_bit(STATUS_RF_KILL_HW, &priv->status))
b481de9c 6561 return 0;
b481de9c
ZY
6562
6563 for (i = 0; i < MAX_HW_RESTARTS; i++) {
6564
bb8c093b 6565 iwl4965_clear_stations_table(priv);
b481de9c
ZY
6566
6567 /* load bootstrap state machine,
6568 * load bootstrap program into processor's memory,
6569 * prepare to load the "initialize" uCode */
bb8c093b 6570 rc = iwl4965_load_bsm(priv);
b481de9c
ZY
6571
6572 if (rc) {
6573 IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
6574 continue;
6575 }
6576
6577 /* start card; "initialize" will load runtime ucode */
bb8c093b 6578 iwl4965_nic_start(priv);
b481de9c 6579
b481de9c
ZY
6580 IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
6581
6582 return 0;
6583 }
6584
6585 set_bit(STATUS_EXIT_PENDING, &priv->status);
bb8c093b 6586 __iwl4965_down(priv);
b481de9c
ZY
6587
6588 /* tried to restart and config the device for as long as our
6589 * patience could withstand */
6590 IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
6591 return -EIO;
6592}
6593
6594
6595/*****************************************************************************
6596 *
6597 * Workqueue callbacks
6598 *
6599 *****************************************************************************/
6600
bb8c093b 6601static void iwl4965_bg_init_alive_start(struct work_struct *data)
b481de9c 6602{
bb8c093b
CH
6603 struct iwl4965_priv *priv =
6604 container_of(data, struct iwl4965_priv, init_alive_start.work);
b481de9c
ZY
6605
6606 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6607 return;
6608
6609 mutex_lock(&priv->mutex);
bb8c093b 6610 iwl4965_init_alive_start(priv);
b481de9c
ZY
6611 mutex_unlock(&priv->mutex);
6612}
6613
bb8c093b 6614static void iwl4965_bg_alive_start(struct work_struct *data)
b481de9c 6615{
bb8c093b
CH
6616 struct iwl4965_priv *priv =
6617 container_of(data, struct iwl4965_priv, alive_start.work);
b481de9c
ZY
6618
6619 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6620 return;
6621
6622 mutex_lock(&priv->mutex);
bb8c093b 6623 iwl4965_alive_start(priv);
b481de9c
ZY
6624 mutex_unlock(&priv->mutex);
6625}
6626
bb8c093b 6627static void iwl4965_bg_rf_kill(struct work_struct *work)
b481de9c 6628{
bb8c093b 6629 struct iwl4965_priv *priv = container_of(work, struct iwl4965_priv, rf_kill);
b481de9c
ZY
6630
6631 wake_up_interruptible(&priv->wait_command_queue);
6632
6633 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6634 return;
6635
6636 mutex_lock(&priv->mutex);
6637
bb8c093b 6638 if (!iwl4965_is_rfkill(priv)) {
b481de9c
ZY
6639 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
6640 "HW and/or SW RF Kill no longer active, restarting "
6641 "device\n");
6642 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
6643 queue_work(priv->workqueue, &priv->restart);
6644 } else {
6645
6646 if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
6647 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
6648 "disabled by SW switch\n");
6649 else
6650 IWL_WARNING("Radio Frequency Kill Switch is On:\n"
6651 "Kill switch must be turned off for "
6652 "wireless networking to work.\n");
6653 }
6654 mutex_unlock(&priv->mutex);
6655}
6656
6657#define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
6658
bb8c093b 6659static void iwl4965_bg_scan_check(struct work_struct *data)
b481de9c 6660{
bb8c093b
CH
6661 struct iwl4965_priv *priv =
6662 container_of(data, struct iwl4965_priv, scan_check.work);
b481de9c
ZY
6663
6664 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6665 return;
6666
6667 mutex_lock(&priv->mutex);
6668 if (test_bit(STATUS_SCANNING, &priv->status) ||
6669 test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6670 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
6671 "Scan completion watchdog resetting adapter (%dms)\n",
6672 jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
052c4b9f 6673
b481de9c 6674 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
bb8c093b 6675 iwl4965_send_scan_abort(priv);
b481de9c
ZY
6676 }
6677 mutex_unlock(&priv->mutex);
6678}
6679
bb8c093b 6680static void iwl4965_bg_request_scan(struct work_struct *data)
b481de9c 6681{
bb8c093b
CH
6682 struct iwl4965_priv *priv =
6683 container_of(data, struct iwl4965_priv, request_scan);
6684 struct iwl4965_host_cmd cmd = {
b481de9c 6685 .id = REPLY_SCAN_CMD,
bb8c093b 6686 .len = sizeof(struct iwl4965_scan_cmd),
b481de9c
ZY
6687 .meta.flags = CMD_SIZE_HUGE,
6688 };
6689 int rc = 0;
bb8c093b 6690 struct iwl4965_scan_cmd *scan;
b481de9c 6691 struct ieee80211_conf *conf = NULL;
78330fdd 6692 u16 cmd_len;
8318d78a 6693 enum ieee80211_band band;
78330fdd 6694 u8 direct_mask;
b481de9c
ZY
6695
6696 conf = ieee80211_get_hw_conf(priv->hw);
6697
6698 mutex_lock(&priv->mutex);
6699
bb8c093b 6700 if (!iwl4965_is_ready(priv)) {
b481de9c
ZY
6701 IWL_WARNING("request scan called when driver not ready.\n");
6702 goto done;
6703 }
6704
6705 /* Make sure the scan wasn't cancelled before this queued work
6706 * was given the chance to run... */
6707 if (!test_bit(STATUS_SCANNING, &priv->status))
6708 goto done;
6709
6710 /* This should never be called or scheduled if there is currently
6711 * a scan active in the hardware. */
6712 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
6713 IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
6714 "Ignoring second request.\n");
6715 rc = -EIO;
6716 goto done;
6717 }
6718
6719 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
6720 IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
6721 goto done;
6722 }
6723
6724 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6725 IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
6726 goto done;
6727 }
6728
bb8c093b 6729 if (iwl4965_is_rfkill(priv)) {
b481de9c
ZY
6730 IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
6731 goto done;
6732 }
6733
6734 if (!test_bit(STATUS_READY, &priv->status)) {
6735 IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
6736 goto done;
6737 }
6738
6739 if (!priv->scan_bands) {
6740 IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
6741 goto done;
6742 }
6743
6744 if (!priv->scan) {
bb8c093b 6745 priv->scan = kmalloc(sizeof(struct iwl4965_scan_cmd) +
b481de9c
ZY
6746 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
6747 if (!priv->scan) {
6748 rc = -ENOMEM;
6749 goto done;
6750 }
6751 }
6752 scan = priv->scan;
bb8c093b 6753 memset(scan, 0, sizeof(struct iwl4965_scan_cmd) + IWL_MAX_SCAN_SIZE);
b481de9c
ZY
6754
6755 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
6756 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
6757
bb8c093b 6758 if (iwl4965_is_associated(priv)) {
b481de9c
ZY
6759 u16 interval = 0;
6760 u32 extra;
6761 u32 suspend_time = 100;
6762 u32 scan_suspend_time = 100;
6763 unsigned long flags;
6764
6765 IWL_DEBUG_INFO("Scanning while associated...\n");
6766
6767 spin_lock_irqsave(&priv->lock, flags);
6768 interval = priv->beacon_int;
6769 spin_unlock_irqrestore(&priv->lock, flags);
6770
6771 scan->suspend_time = 0;
052c4b9f 6772 scan->max_out_time = cpu_to_le32(200 * 1024);
b481de9c
ZY
6773 if (!interval)
6774 interval = suspend_time;
6775
6776 extra = (suspend_time / interval) << 22;
6777 scan_suspend_time = (extra |
6778 ((suspend_time % interval) * 1024));
6779 scan->suspend_time = cpu_to_le32(scan_suspend_time);
6780 IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
6781 scan_suspend_time, interval);
6782 }
6783
6784 /* We should add the ability for user to lock to PASSIVE ONLY */
6785 if (priv->one_direct_scan) {
6786 IWL_DEBUG_SCAN
6787 ("Kicking off one direct scan for '%s'\n",
bb8c093b 6788 iwl4965_escape_essid(priv->direct_ssid,
b481de9c
ZY
6789 priv->direct_ssid_len));
6790 scan->direct_scan[0].id = WLAN_EID_SSID;
6791 scan->direct_scan[0].len = priv->direct_ssid_len;
6792 memcpy(scan->direct_scan[0].ssid,
6793 priv->direct_ssid, priv->direct_ssid_len);
6794 direct_mask = 1;
bb8c093b 6795 } else if (!iwl4965_is_associated(priv) && priv->essid_len) {
b481de9c
ZY
6796 scan->direct_scan[0].id = WLAN_EID_SSID;
6797 scan->direct_scan[0].len = priv->essid_len;
6798 memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len);
6799 direct_mask = 1;
6800 } else
6801 direct_mask = 0;
6802
b481de9c
ZY
6803 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
6804 scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
6805 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
6806
b481de9c
ZY
6807
6808 switch (priv->scan_bands) {
6809 case 2:
6810 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
6811 scan->tx_cmd.rate_n_flags =
bb8c093b 6812 iwl4965_hw_set_rate_n_flags(IWL_RATE_1M_PLCP,
b481de9c
ZY
6813 RATE_MCS_ANT_B_MSK|RATE_MCS_CCK_MSK);
6814
6815 scan->good_CRC_th = 0;
8318d78a 6816 band = IEEE80211_BAND_2GHZ;
b481de9c
ZY
6817 break;
6818
6819 case 1:
6820 scan->tx_cmd.rate_n_flags =
bb8c093b 6821 iwl4965_hw_set_rate_n_flags(IWL_RATE_6M_PLCP,
b481de9c
ZY
6822 RATE_MCS_ANT_B_MSK);
6823 scan->good_CRC_th = IWL_GOOD_CRC_TH;
8318d78a 6824 band = IEEE80211_BAND_5GHZ;
b481de9c
ZY
6825 break;
6826
6827 default:
6828 IWL_WARNING("Invalid scan band count\n");
6829 goto done;
6830 }
6831
78330fdd
TW
6832 /* We don't build a direct scan probe request; the uCode will do
6833 * that based on the direct_mask added to each channel entry */
6834 cmd_len = iwl4965_fill_probe_req(priv, band,
6835 (struct ieee80211_mgmt *)scan->data,
6836 IWL_MAX_SCAN_SIZE - sizeof(*scan), 0);
6837
6838 scan->tx_cmd.len = cpu_to_le16(cmd_len);
b481de9c
ZY
6839 /* select Rx chains */
6840
6841 /* Force use of chains B and C (0x6) for scan Rx.
6842 * Avoid A (0x1) because of its off-channel reception on A-band.
6843 * MIMO is not used here, but value is required to make uCode happy. */
6844 scan->rx_chain = RXON_RX_CHAIN_DRIVER_FORCE_MSK |
6845 cpu_to_le16((0x7 << RXON_RX_CHAIN_VALID_POS) |
6846 (0x6 << RXON_RX_CHAIN_FORCE_SEL_POS) |
6847 (0x7 << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS));
6848
6849 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR)
6850 scan->filter_flags = RXON_FILTER_PROMISC_MSK;
6851
6852 if (direct_mask)
6853 IWL_DEBUG_SCAN
6854 ("Initiating direct scan for %s.\n",
bb8c093b 6855 iwl4965_escape_essid(priv->essid, priv->essid_len));
b481de9c
ZY
6856 else
6857 IWL_DEBUG_SCAN("Initiating indirect scan.\n");
6858
6859 scan->channel_count =
bb8c093b 6860 iwl4965_get_channels_for_scan(
8318d78a 6861 priv, band, 1, /* active */
b481de9c
ZY
6862 direct_mask,
6863 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
6864
6865 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
bb8c093b 6866 scan->channel_count * sizeof(struct iwl4965_scan_channel);
b481de9c
ZY
6867 cmd.data = scan;
6868 scan->len = cpu_to_le16(cmd.len);
6869
6870 set_bit(STATUS_SCAN_HW, &priv->status);
bb8c093b 6871 rc = iwl4965_send_cmd_sync(priv, &cmd);
b481de9c
ZY
6872 if (rc)
6873 goto done;
6874
6875 queue_delayed_work(priv->workqueue, &priv->scan_check,
6876 IWL_SCAN_CHECK_WATCHDOG);
6877
6878 mutex_unlock(&priv->mutex);
6879 return;
6880
6881 done:
01ebd063 6882 /* inform mac80211 scan aborted */
b481de9c
ZY
6883 queue_work(priv->workqueue, &priv->scan_completed);
6884 mutex_unlock(&priv->mutex);
6885}
6886
bb8c093b 6887static void iwl4965_bg_up(struct work_struct *data)
b481de9c 6888{
bb8c093b 6889 struct iwl4965_priv *priv = container_of(data, struct iwl4965_priv, up);
b481de9c
ZY
6890
6891 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6892 return;
6893
6894 mutex_lock(&priv->mutex);
bb8c093b 6895 __iwl4965_up(priv);
b481de9c
ZY
6896 mutex_unlock(&priv->mutex);
6897}
6898
bb8c093b 6899static void iwl4965_bg_restart(struct work_struct *data)
b481de9c 6900{
bb8c093b 6901 struct iwl4965_priv *priv = container_of(data, struct iwl4965_priv, restart);
b481de9c
ZY
6902
6903 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6904 return;
6905
bb8c093b 6906 iwl4965_down(priv);
b481de9c
ZY
6907 queue_work(priv->workqueue, &priv->up);
6908}
6909
bb8c093b 6910static void iwl4965_bg_rx_replenish(struct work_struct *data)
b481de9c 6911{
bb8c093b
CH
6912 struct iwl4965_priv *priv =
6913 container_of(data, struct iwl4965_priv, rx_replenish);
b481de9c
ZY
6914
6915 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6916 return;
6917
6918 mutex_lock(&priv->mutex);
bb8c093b 6919 iwl4965_rx_replenish(priv);
b481de9c
ZY
6920 mutex_unlock(&priv->mutex);
6921}
6922
7878a5a4
MA
6923#define IWL_DELAY_NEXT_SCAN (HZ*2)
6924
bb8c093b 6925static void iwl4965_bg_post_associate(struct work_struct *data)
b481de9c 6926{
bb8c093b 6927 struct iwl4965_priv *priv = container_of(data, struct iwl4965_priv,
b481de9c
ZY
6928 post_associate.work);
6929
6930 int rc = 0;
6931 struct ieee80211_conf *conf = NULL;
0795af57 6932 DECLARE_MAC_BUF(mac);
b481de9c
ZY
6933
6934 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
6935 IWL_ERROR("%s Should not be called in AP mode\n", __FUNCTION__);
6936 return;
6937 }
6938
0795af57
JP
6939 IWL_DEBUG_ASSOC("Associated as %d to: %s\n",
6940 priv->assoc_id,
6941 print_mac(mac, priv->active_rxon.bssid_addr));
b481de9c
ZY
6942
6943
6944 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6945 return;
6946
6947 mutex_lock(&priv->mutex);
6948
32bfd35d 6949 if (!priv->vif || !priv->is_open) {
948c171c
MA
6950 mutex_unlock(&priv->mutex);
6951 return;
6952 }
bb8c093b 6953 iwl4965_scan_cancel_timeout(priv, 200);
052c4b9f 6954
b481de9c
ZY
6955 conf = ieee80211_get_hw_conf(priv->hw);
6956
6957 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6958 iwl4965_commit_rxon(priv);
b481de9c 6959
bb8c093b
CH
6960 memset(&priv->rxon_timing, 0, sizeof(struct iwl4965_rxon_time_cmd));
6961 iwl4965_setup_rxon_timing(priv);
6962 rc = iwl4965_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY
6963 sizeof(priv->rxon_timing), &priv->rxon_timing);
6964 if (rc)
6965 IWL_WARNING("REPLY_RXON_TIMING failed - "
6966 "Attempting to continue.\n");
6967
6968 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
6969
c8b0e6e1 6970#ifdef CONFIG_IWL4965_HT
fd105e79
RR
6971 if (priv->current_ht_config.is_ht)
6972 iwl4965_set_rxon_ht(priv, &priv->current_ht_config);
c8b0e6e1 6973#endif /* CONFIG_IWL4965_HT*/
b481de9c
ZY
6974 iwl4965_set_rxon_chain(priv);
6975 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
6976
6977 IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
6978 priv->assoc_id, priv->beacon_int);
6979
6980 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
6981 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
6982 else
6983 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
6984
6985 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
6986 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
6987 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
6988 else
6989 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
6990
6991 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
6992 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
6993
6994 }
6995
bb8c093b 6996 iwl4965_commit_rxon(priv);
b481de9c
ZY
6997
6998 switch (priv->iw_mode) {
6999 case IEEE80211_IF_TYPE_STA:
bb8c093b 7000 iwl4965_rate_scale_init(priv->hw, IWL_AP_ID);
b481de9c
ZY
7001 break;
7002
7003 case IEEE80211_IF_TYPE_IBSS:
7004
7005 /* clear out the station table */
bb8c093b 7006 iwl4965_clear_stations_table(priv);
b481de9c 7007
bb8c093b
CH
7008 iwl4965_rxon_add_station(priv, iwl4965_broadcast_addr, 0);
7009 iwl4965_rxon_add_station(priv, priv->bssid, 0);
7010 iwl4965_rate_scale_init(priv->hw, IWL_STA_ID);
7011 iwl4965_send_beacon_cmd(priv);
b481de9c
ZY
7012
7013 break;
7014
7015 default:
7016 IWL_ERROR("%s Should not be called in %d mode\n",
7017 __FUNCTION__, priv->iw_mode);
7018 break;
7019 }
7020
bb8c093b 7021 iwl4965_sequence_reset(priv);
b481de9c 7022
c8b0e6e1 7023#ifdef CONFIG_IWL4965_SENSITIVITY
b481de9c
ZY
7024 /* Enable Rx differential gain and sensitivity calibrations */
7025 iwl4965_chain_noise_reset(priv);
7026 priv->start_calib = 1;
c8b0e6e1 7027#endif /* CONFIG_IWL4965_SENSITIVITY */
b481de9c
ZY
7028
7029 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
7030 priv->assoc_station_added = 1;
7031
bb8c093b 7032 iwl4965_activate_qos(priv, 0);
292ae174 7033
7878a5a4
MA
7034 /* we have just associated, don't start scan too early */
7035 priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
b481de9c
ZY
7036 mutex_unlock(&priv->mutex);
7037}
7038
bb8c093b 7039static void iwl4965_bg_abort_scan(struct work_struct *work)
b481de9c 7040{
bb8c093b 7041 struct iwl4965_priv *priv = container_of(work, struct iwl4965_priv, abort_scan);
b481de9c 7042
bb8c093b 7043 if (!iwl4965_is_ready(priv))
b481de9c
ZY
7044 return;
7045
7046 mutex_lock(&priv->mutex);
7047
7048 set_bit(STATUS_SCAN_ABORTING, &priv->status);
bb8c093b 7049 iwl4965_send_scan_abort(priv);
b481de9c
ZY
7050
7051 mutex_unlock(&priv->mutex);
7052}
7053
76bb77e0
ZY
7054static int iwl4965_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf);
7055
bb8c093b 7056static void iwl4965_bg_scan_completed(struct work_struct *work)
b481de9c 7057{
bb8c093b
CH
7058 struct iwl4965_priv *priv =
7059 container_of(work, struct iwl4965_priv, scan_completed);
b481de9c
ZY
7060
7061 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
7062
7063 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
7064 return;
7065
a0646470
ZY
7066 if (test_bit(STATUS_CONF_PENDING, &priv->status))
7067 iwl4965_mac_config(priv->hw, ieee80211_get_hw_conf(priv->hw));
76bb77e0 7068
b481de9c
ZY
7069 ieee80211_scan_completed(priv->hw);
7070
7071 /* Since setting the TXPOWER may have been deferred while
7072 * performing the scan, fire one off */
7073 mutex_lock(&priv->mutex);
bb8c093b 7074 iwl4965_hw_reg_send_txpower(priv);
b481de9c
ZY
7075 mutex_unlock(&priv->mutex);
7076}
7077
7078/*****************************************************************************
7079 *
7080 * mac80211 entry point functions
7081 *
7082 *****************************************************************************/
7083
5a66926a
ZY
7084#define UCODE_READY_TIMEOUT (2 * HZ)
7085
bb8c093b 7086static int iwl4965_mac_start(struct ieee80211_hw *hw)
b481de9c 7087{
bb8c093b 7088 struct iwl4965_priv *priv = hw->priv;
5a66926a 7089 int ret;
b481de9c
ZY
7090
7091 IWL_DEBUG_MAC80211("enter\n");
7092
5a66926a
ZY
7093 if (pci_enable_device(priv->pci_dev)) {
7094 IWL_ERROR("Fail to pci_enable_device\n");
7095 return -ENODEV;
7096 }
7097 pci_restore_state(priv->pci_dev);
7098 pci_enable_msi(priv->pci_dev);
7099
7100 ret = request_irq(priv->pci_dev->irq, iwl4965_isr, IRQF_SHARED,
7101 DRV_NAME, priv);
7102 if (ret) {
7103 IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq);
7104 goto out_disable_msi;
7105 }
7106
b481de9c
ZY
7107 /* we should be verifying the device is ready to be opened */
7108 mutex_lock(&priv->mutex);
7109
5a66926a
ZY
7110 memset(&priv->staging_rxon, 0, sizeof(struct iwl4965_rxon_cmd));
7111 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
7112 * ucode filename and max sizes are card-specific. */
b481de9c 7113
5a66926a
ZY
7114 if (!priv->ucode_code.len) {
7115 ret = iwl4965_read_ucode(priv);
7116 if (ret) {
7117 IWL_ERROR("Could not read microcode: %d\n", ret);
7118 mutex_unlock(&priv->mutex);
7119 goto out_release_irq;
7120 }
7121 }
b481de9c 7122
e655b9f0 7123 ret = __iwl4965_up(priv);
5a66926a 7124
b481de9c 7125 mutex_unlock(&priv->mutex);
5a66926a 7126
e655b9f0
ZY
7127 if (ret)
7128 goto out_release_irq;
7129
7130 IWL_DEBUG_INFO("Start UP work done.\n");
7131
7132 if (test_bit(STATUS_IN_SUSPEND, &priv->status))
7133 return 0;
7134
5a66926a
ZY
7135 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
7136 * mac80211 will not be run successfully. */
7137 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
7138 test_bit(STATUS_READY, &priv->status),
7139 UCODE_READY_TIMEOUT);
7140 if (!ret) {
7141 if (!test_bit(STATUS_READY, &priv->status)) {
7142 IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n",
7143 jiffies_to_msecs(UCODE_READY_TIMEOUT));
7144 ret = -ETIMEDOUT;
7145 goto out_release_irq;
7146 }
7147 }
7148
e655b9f0 7149 priv->is_open = 1;
b481de9c
ZY
7150 IWL_DEBUG_MAC80211("leave\n");
7151 return 0;
5a66926a
ZY
7152
7153out_release_irq:
7154 free_irq(priv->pci_dev->irq, priv);
7155out_disable_msi:
7156 pci_disable_msi(priv->pci_dev);
e655b9f0
ZY
7157 pci_disable_device(priv->pci_dev);
7158 priv->is_open = 0;
7159 IWL_DEBUG_MAC80211("leave - failed\n");
5a66926a 7160 return ret;
b481de9c
ZY
7161}
7162
bb8c093b 7163static void iwl4965_mac_stop(struct ieee80211_hw *hw)
b481de9c 7164{
bb8c093b 7165 struct iwl4965_priv *priv = hw->priv;
b481de9c
ZY
7166
7167 IWL_DEBUG_MAC80211("enter\n");
948c171c 7168
e655b9f0
ZY
7169 if (!priv->is_open) {
7170 IWL_DEBUG_MAC80211("leave - skip\n");
7171 return;
7172 }
7173
b481de9c 7174 priv->is_open = 0;
5a66926a
ZY
7175
7176 if (iwl4965_is_ready_rf(priv)) {
e655b9f0
ZY
7177 /* stop mac, cancel any scan request and clear
7178 * RXON_FILTER_ASSOC_MSK BIT
7179 */
5a66926a
ZY
7180 mutex_lock(&priv->mutex);
7181 iwl4965_scan_cancel_timeout(priv, 100);
7182 cancel_delayed_work(&priv->post_associate);
fde3571f 7183 mutex_unlock(&priv->mutex);
fde3571f
MA
7184 }
7185
5a66926a
ZY
7186 iwl4965_down(priv);
7187
7188 flush_workqueue(priv->workqueue);
7189 free_irq(priv->pci_dev->irq, priv);
7190 pci_disable_msi(priv->pci_dev);
7191 pci_save_state(priv->pci_dev);
7192 pci_disable_device(priv->pci_dev);
948c171c 7193
b481de9c 7194 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY
7195}
7196
bb8c093b 7197static int iwl4965_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
b481de9c
ZY
7198 struct ieee80211_tx_control *ctl)
7199{
bb8c093b 7200 struct iwl4965_priv *priv = hw->priv;
b481de9c
ZY
7201
7202 IWL_DEBUG_MAC80211("enter\n");
7203
7204 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
7205 IWL_DEBUG_MAC80211("leave - monitor\n");
7206 return -1;
7207 }
7208
7209 IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
8318d78a 7210 ctl->tx_rate->bitrate);
b481de9c 7211
bb8c093b 7212 if (iwl4965_tx_skb(priv, skb, ctl))
b481de9c
ZY
7213 dev_kfree_skb_any(skb);
7214
7215 IWL_DEBUG_MAC80211("leave\n");
7216 return 0;
7217}
7218
bb8c093b 7219static int iwl4965_mac_add_interface(struct ieee80211_hw *hw,
b481de9c
ZY
7220 struct ieee80211_if_init_conf *conf)
7221{
bb8c093b 7222 struct iwl4965_priv *priv = hw->priv;
b481de9c 7223 unsigned long flags;
0795af57 7224 DECLARE_MAC_BUF(mac);
b481de9c 7225
32bfd35d 7226 IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
b481de9c 7227
32bfd35d
JB
7228 if (priv->vif) {
7229 IWL_DEBUG_MAC80211("leave - vif != NULL\n");
75849d28 7230 return -EOPNOTSUPP;
b481de9c
ZY
7231 }
7232
7233 spin_lock_irqsave(&priv->lock, flags);
32bfd35d 7234 priv->vif = conf->vif;
b481de9c
ZY
7235
7236 spin_unlock_irqrestore(&priv->lock, flags);
7237
7238 mutex_lock(&priv->mutex);
864792e3
TW
7239
7240 if (conf->mac_addr) {
7241 IWL_DEBUG_MAC80211("Set %s\n", print_mac(mac, conf->mac_addr));
7242 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
7243 }
b481de9c 7244
5a66926a
ZY
7245 if (iwl4965_is_ready(priv))
7246 iwl4965_set_mode(priv, conf->type);
7247
b481de9c
ZY
7248 mutex_unlock(&priv->mutex);
7249
5a66926a 7250 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY
7251 return 0;
7252}
7253
7254/**
bb8c093b 7255 * iwl4965_mac_config - mac80211 config callback
b481de9c
ZY
7256 *
7257 * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
7258 * be set inappropriately and the driver currently sets the hardware up to
7259 * use it whenever needed.
7260 */
bb8c093b 7261static int iwl4965_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
b481de9c 7262{
bb8c093b
CH
7263 struct iwl4965_priv *priv = hw->priv;
7264 const struct iwl4965_channel_info *ch_info;
b481de9c 7265 unsigned long flags;
76bb77e0 7266 int ret = 0;
b481de9c
ZY
7267
7268 mutex_lock(&priv->mutex);
8318d78a 7269 IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
b481de9c 7270
12342c47
ZY
7271 priv->add_radiotap = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
7272
bb8c093b 7273 if (!iwl4965_is_ready(priv)) {
b481de9c 7274 IWL_DEBUG_MAC80211("leave - not ready\n");
76bb77e0
ZY
7275 ret = -EIO;
7276 goto out;
b481de9c
ZY
7277 }
7278
bb8c093b 7279 if (unlikely(!iwl4965_param_disable_hw_scan &&
b481de9c 7280 test_bit(STATUS_SCANNING, &priv->status))) {
a0646470
ZY
7281 IWL_DEBUG_MAC80211("leave - scanning\n");
7282 set_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 7283 mutex_unlock(&priv->mutex);
a0646470 7284 return 0;
b481de9c
ZY
7285 }
7286
7287 spin_lock_irqsave(&priv->lock, flags);
7288
8318d78a
JB
7289 ch_info = iwl4965_get_channel_info(priv, conf->channel->band,
7290 ieee80211_frequency_to_channel(conf->channel->center_freq));
b481de9c 7291 if (!is_channel_valid(ch_info)) {
b481de9c
ZY
7292 IWL_DEBUG_MAC80211("leave - invalid channel\n");
7293 spin_unlock_irqrestore(&priv->lock, flags);
76bb77e0
ZY
7294 ret = -EINVAL;
7295 goto out;
b481de9c
ZY
7296 }
7297
c8b0e6e1 7298#ifdef CONFIG_IWL4965_HT
78330fdd 7299 /* if we are switching from ht to 2.4 clear flags
b481de9c
ZY
7300 * from any ht related info since 2.4 does not
7301 * support ht */
78330fdd 7302 if ((le16_to_cpu(priv->staging_rxon.channel) != conf->channel->hw_value)
b481de9c
ZY
7303#ifdef IEEE80211_CONF_CHANNEL_SWITCH
7304 && !(conf->flags & IEEE80211_CONF_CHANNEL_SWITCH)
7305#endif
7306 )
7307 priv->staging_rxon.flags = 0;
c8b0e6e1 7308#endif /* CONFIG_IWL4965_HT */
b481de9c 7309
8318d78a
JB
7310 iwl4965_set_rxon_channel(priv, conf->channel->band,
7311 ieee80211_frequency_to_channel(conf->channel->center_freq));
b481de9c 7312
8318d78a 7313 iwl4965_set_flags_for_phymode(priv, conf->channel->band);
b481de9c
ZY
7314
7315 /* The list of supported rates and rate mask can be different
8318d78a 7316 * for each band; since the band may have changed, reset
b481de9c 7317 * the rate mask to what mac80211 lists */
bb8c093b 7318 iwl4965_set_rate(priv);
b481de9c
ZY
7319
7320 spin_unlock_irqrestore(&priv->lock, flags);
7321
7322#ifdef IEEE80211_CONF_CHANNEL_SWITCH
7323 if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
bb8c093b 7324 iwl4965_hw_channel_switch(priv, conf->channel);
76bb77e0 7325 goto out;
b481de9c
ZY
7326 }
7327#endif
7328
bb8c093b 7329 iwl4965_radio_kill_sw(priv, !conf->radio_enabled);
b481de9c
ZY
7330
7331 if (!conf->radio_enabled) {
7332 IWL_DEBUG_MAC80211("leave - radio disabled\n");
76bb77e0 7333 goto out;
b481de9c
ZY
7334 }
7335
bb8c093b 7336 if (iwl4965_is_rfkill(priv)) {
b481de9c 7337 IWL_DEBUG_MAC80211("leave - RF kill\n");
76bb77e0
ZY
7338 ret = -EIO;
7339 goto out;
b481de9c
ZY
7340 }
7341
bb8c093b 7342 iwl4965_set_rate(priv);
b481de9c
ZY
7343
7344 if (memcmp(&priv->active_rxon,
7345 &priv->staging_rxon, sizeof(priv->staging_rxon)))
bb8c093b 7346 iwl4965_commit_rxon(priv);
b481de9c
ZY
7347 else
7348 IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
7349
7350 IWL_DEBUG_MAC80211("leave\n");
7351
a0646470
ZY
7352out:
7353 clear_bit(STATUS_CONF_PENDING, &priv->status);
5a66926a 7354 mutex_unlock(&priv->mutex);
76bb77e0 7355 return ret;
b481de9c
ZY
7356}
7357
bb8c093b 7358static void iwl4965_config_ap(struct iwl4965_priv *priv)
b481de9c
ZY
7359{
7360 int rc = 0;
7361
d986bcd1 7362 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY
7363 return;
7364
7365 /* The following should be done only at AP bring up */
7366 if ((priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) == 0) {
7367
7368 /* RXON - unassoc (to set timing command) */
7369 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 7370 iwl4965_commit_rxon(priv);
b481de9c
ZY
7371
7372 /* RXON Timing */
bb8c093b
CH
7373 memset(&priv->rxon_timing, 0, sizeof(struct iwl4965_rxon_time_cmd));
7374 iwl4965_setup_rxon_timing(priv);
7375 rc = iwl4965_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY
7376 sizeof(priv->rxon_timing), &priv->rxon_timing);
7377 if (rc)
7378 IWL_WARNING("REPLY_RXON_TIMING failed - "
7379 "Attempting to continue.\n");
7380
7381 iwl4965_set_rxon_chain(priv);
7382
7383 /* FIXME: what should be the assoc_id for AP? */
7384 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
7385 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
7386 priv->staging_rxon.flags |=
7387 RXON_FLG_SHORT_PREAMBLE_MSK;
7388 else
7389 priv->staging_rxon.flags &=
7390 ~RXON_FLG_SHORT_PREAMBLE_MSK;
7391
7392 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
7393 if (priv->assoc_capability &
7394 WLAN_CAPABILITY_SHORT_SLOT_TIME)
7395 priv->staging_rxon.flags |=
7396 RXON_FLG_SHORT_SLOT_MSK;
7397 else
7398 priv->staging_rxon.flags &=
7399 ~RXON_FLG_SHORT_SLOT_MSK;
7400
7401 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
7402 priv->staging_rxon.flags &=
7403 ~RXON_FLG_SHORT_SLOT_MSK;
7404 }
7405 /* restore RXON assoc */
7406 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
bb8c093b 7407 iwl4965_commit_rxon(priv);
bb8c093b 7408 iwl4965_activate_qos(priv, 1);
bb8c093b 7409 iwl4965_rxon_add_station(priv, iwl4965_broadcast_addr, 0);
e1493deb 7410 }
bb8c093b 7411 iwl4965_send_beacon_cmd(priv);
b481de9c
ZY
7412
7413 /* FIXME - we need to add code here to detect a totally new
7414 * configuration, reset the AP, unassoc, rxon timing, assoc,
7415 * clear sta table, add BCAST sta... */
7416}
7417
32bfd35d
JB
7418static int iwl4965_mac_config_interface(struct ieee80211_hw *hw,
7419 struct ieee80211_vif *vif,
b481de9c
ZY
7420 struct ieee80211_if_conf *conf)
7421{
bb8c093b 7422 struct iwl4965_priv *priv = hw->priv;
0795af57 7423 DECLARE_MAC_BUF(mac);
b481de9c
ZY
7424 unsigned long flags;
7425 int rc;
7426
7427 if (conf == NULL)
7428 return -EIO;
7429
7430 if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
7431 (!conf->beacon || !conf->ssid_len)) {
7432 IWL_DEBUG_MAC80211
7433 ("Leaving in AP mode because HostAPD is not ready.\n");
7434 return 0;
7435 }
7436
5a66926a
ZY
7437 if (!iwl4965_is_alive(priv))
7438 return -EAGAIN;
7439
b481de9c
ZY
7440 mutex_lock(&priv->mutex);
7441
b481de9c 7442 if (conf->bssid)
0795af57
JP
7443 IWL_DEBUG_MAC80211("bssid: %s\n",
7444 print_mac(mac, conf->bssid));
b481de9c 7445
4150c572
JB
7446/*
7447 * very dubious code was here; the probe filtering flag is never set:
7448 *
b481de9c
ZY
7449 if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
7450 !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
4150c572
JB
7451 */
7452 if (unlikely(test_bit(STATUS_SCANNING, &priv->status))) {
b481de9c
ZY
7453 IWL_DEBUG_MAC80211("leave - scanning\n");
7454 mutex_unlock(&priv->mutex);
7455 return 0;
7456 }
7457
32bfd35d
JB
7458 if (priv->vif != vif) {
7459 IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
b481de9c
ZY
7460 mutex_unlock(&priv->mutex);
7461 return 0;
7462 }
7463
7464 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
7465 if (!conf->bssid) {
7466 conf->bssid = priv->mac_addr;
7467 memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
0795af57
JP
7468 IWL_DEBUG_MAC80211("bssid was set to: %s\n",
7469 print_mac(mac, conf->bssid));
b481de9c
ZY
7470 }
7471 if (priv->ibss_beacon)
7472 dev_kfree_skb(priv->ibss_beacon);
7473
7474 priv->ibss_beacon = conf->beacon;
7475 }
7476
fde3571f
MA
7477 if (iwl4965_is_rfkill(priv))
7478 goto done;
7479
b481de9c
ZY
7480 if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
7481 !is_multicast_ether_addr(conf->bssid)) {
7482 /* If there is currently a HW scan going on in the background
7483 * then we need to cancel it else the RXON below will fail. */
bb8c093b 7484 if (iwl4965_scan_cancel_timeout(priv, 100)) {
b481de9c
ZY
7485 IWL_WARNING("Aborted scan still in progress "
7486 "after 100ms\n");
7487 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
7488 mutex_unlock(&priv->mutex);
7489 return -EAGAIN;
7490 }
7491 memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
7492
7493 /* TODO: Audit driver for usage of these members and see
7494 * if mac80211 deprecates them (priv->bssid looks like it
7495 * shouldn't be there, but I haven't scanned the IBSS code
7496 * to verify) - jpk */
7497 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
7498
7499 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
bb8c093b 7500 iwl4965_config_ap(priv);
b481de9c 7501 else {
bb8c093b 7502 rc = iwl4965_commit_rxon(priv);
b481de9c 7503 if ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && rc)
bb8c093b 7504 iwl4965_rxon_add_station(
b481de9c
ZY
7505 priv, priv->active_rxon.bssid_addr, 1);
7506 }
7507
7508 } else {
bb8c093b 7509 iwl4965_scan_cancel_timeout(priv, 100);
b481de9c 7510 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 7511 iwl4965_commit_rxon(priv);
b481de9c
ZY
7512 }
7513
fde3571f 7514 done:
b481de9c
ZY
7515 spin_lock_irqsave(&priv->lock, flags);
7516 if (!conf->ssid_len)
7517 memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
7518 else
7519 memcpy(priv->essid, conf->ssid, conf->ssid_len);
7520
7521 priv->essid_len = conf->ssid_len;
7522 spin_unlock_irqrestore(&priv->lock, flags);
7523
7524 IWL_DEBUG_MAC80211("leave\n");
7525 mutex_unlock(&priv->mutex);
7526
7527 return 0;
7528}
7529
bb8c093b 7530static void iwl4965_configure_filter(struct ieee80211_hw *hw,
4150c572
JB
7531 unsigned int changed_flags,
7532 unsigned int *total_flags,
7533 int mc_count, struct dev_addr_list *mc_list)
7534{
7535 /*
7536 * XXX: dummy
bb8c093b 7537 * see also iwl4965_connection_init_rx_config
4150c572
JB
7538 */
7539 *total_flags = 0;
7540}
7541
bb8c093b 7542static void iwl4965_mac_remove_interface(struct ieee80211_hw *hw,
b481de9c
ZY
7543 struct ieee80211_if_init_conf *conf)
7544{
bb8c093b 7545 struct iwl4965_priv *priv = hw->priv;
b481de9c
ZY
7546
7547 IWL_DEBUG_MAC80211("enter\n");
7548
7549 mutex_lock(&priv->mutex);
948c171c 7550
fde3571f
MA
7551 if (iwl4965_is_ready_rf(priv)) {
7552 iwl4965_scan_cancel_timeout(priv, 100);
7553 cancel_delayed_work(&priv->post_associate);
7554 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
7555 iwl4965_commit_rxon(priv);
7556 }
32bfd35d
JB
7557 if (priv->vif == conf->vif) {
7558 priv->vif = NULL;
b481de9c
ZY
7559 memset(priv->bssid, 0, ETH_ALEN);
7560 memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
7561 priv->essid_len = 0;
7562 }
7563 mutex_unlock(&priv->mutex);
7564
7565 IWL_DEBUG_MAC80211("leave\n");
7566
7567}
471b3efd
JB
7568
7569static void iwl4965_bss_info_changed(struct ieee80211_hw *hw,
7570 struct ieee80211_vif *vif,
7571 struct ieee80211_bss_conf *bss_conf,
7572 u32 changes)
220173b0 7573{
bb8c093b 7574 struct iwl4965_priv *priv = hw->priv;
220173b0 7575
471b3efd
JB
7576 if (changes & BSS_CHANGED_ERP_PREAMBLE) {
7577 if (bss_conf->use_short_preamble)
220173b0
TW
7578 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
7579 else
7580 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
7581 }
7582
471b3efd 7583 if (changes & BSS_CHANGED_ERP_CTS_PROT) {
8318d78a 7584 if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
220173b0
TW
7585 priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
7586 else
7587 priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
7588 }
7589
471b3efd
JB
7590 if (changes & BSS_CHANGED_ASSOC) {
7591 /*
7592 * TODO:
7593 * do stuff instead of sniffing assoc resp
7594 */
7595 }
7596
bb8c093b
CH
7597 if (iwl4965_is_associated(priv))
7598 iwl4965_send_rxon_assoc(priv);
220173b0 7599}
b481de9c 7600
bb8c093b 7601static int iwl4965_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
b481de9c
ZY
7602{
7603 int rc = 0;
7604 unsigned long flags;
bb8c093b 7605 struct iwl4965_priv *priv = hw->priv;
b481de9c
ZY
7606
7607 IWL_DEBUG_MAC80211("enter\n");
7608
052c4b9f 7609 mutex_lock(&priv->mutex);
b481de9c
ZY
7610 spin_lock_irqsave(&priv->lock, flags);
7611
bb8c093b 7612 if (!iwl4965_is_ready_rf(priv)) {
b481de9c
ZY
7613 rc = -EIO;
7614 IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
7615 goto out_unlock;
7616 }
7617
7618 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { /* APs don't scan */
7619 rc = -EIO;
7620 IWL_ERROR("ERROR: APs don't scan\n");
7621 goto out_unlock;
7622 }
7623
7878a5a4
MA
7624 /* we don't schedule scan within next_scan_jiffies period */
7625 if (priv->next_scan_jiffies &&
7626 time_after(priv->next_scan_jiffies, jiffies)) {
7627 rc = -EAGAIN;
7628 goto out_unlock;
7629 }
b481de9c 7630 /* if we just finished scan ask for delay */
7878a5a4
MA
7631 if (priv->last_scan_jiffies && time_after(priv->last_scan_jiffies +
7632 IWL_DELAY_NEXT_SCAN, jiffies)) {
b481de9c
ZY
7633 rc = -EAGAIN;
7634 goto out_unlock;
7635 }
7636 if (len) {
7878a5a4 7637 IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
bb8c093b 7638 iwl4965_escape_essid(ssid, len), (int)len);
b481de9c
ZY
7639
7640 priv->one_direct_scan = 1;
7641 priv->direct_ssid_len = (u8)
7642 min((u8) len, (u8) IW_ESSID_MAX_SIZE);
7643 memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
948c171c
MA
7644 } else
7645 priv->one_direct_scan = 0;
b481de9c 7646
bb8c093b 7647 rc = iwl4965_scan_initiate(priv);
b481de9c
ZY
7648
7649 IWL_DEBUG_MAC80211("leave\n");
7650
7651out_unlock:
7652 spin_unlock_irqrestore(&priv->lock, flags);
052c4b9f 7653 mutex_unlock(&priv->mutex);
b481de9c
ZY
7654
7655 return rc;
7656}
7657
bb8c093b 7658static int iwl4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
b481de9c
ZY
7659 const u8 *local_addr, const u8 *addr,
7660 struct ieee80211_key_conf *key)
7661{
bb8c093b 7662 struct iwl4965_priv *priv = hw->priv;
0795af57 7663 DECLARE_MAC_BUF(mac);
b481de9c
ZY
7664 int rc = 0;
7665 u8 sta_id;
7666
7667 IWL_DEBUG_MAC80211("enter\n");
7668
bb8c093b 7669 if (!iwl4965_param_hwcrypto) {
b481de9c
ZY
7670 IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
7671 return -EOPNOTSUPP;
7672 }
7673
7674 if (is_zero_ether_addr(addr))
7675 /* only support pairwise keys */
7676 return -EOPNOTSUPP;
7677
bb8c093b 7678 sta_id = iwl4965_hw_find_station(priv, addr);
b481de9c 7679 if (sta_id == IWL_INVALID_STATION) {
0795af57
JP
7680 IWL_DEBUG_MAC80211("leave - %s not in station map.\n",
7681 print_mac(mac, addr));
b481de9c
ZY
7682 return -EINVAL;
7683 }
7684
7685 mutex_lock(&priv->mutex);
7686
bb8c093b 7687 iwl4965_scan_cancel_timeout(priv, 100);
052c4b9f 7688
b481de9c
ZY
7689 switch (cmd) {
7690 case SET_KEY:
bb8c093b 7691 rc = iwl4965_update_sta_key_info(priv, key, sta_id);
b481de9c 7692 if (!rc) {
bb8c093b
CH
7693 iwl4965_set_rxon_hwcrypto(priv, 1);
7694 iwl4965_commit_rxon(priv);
b481de9c
ZY
7695 key->hw_key_idx = sta_id;
7696 IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
7697 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
7698 }
7699 break;
7700 case DISABLE_KEY:
bb8c093b 7701 rc = iwl4965_clear_sta_key_info(priv, sta_id);
b481de9c 7702 if (!rc) {
bb8c093b
CH
7703 iwl4965_set_rxon_hwcrypto(priv, 0);
7704 iwl4965_commit_rxon(priv);
b481de9c
ZY
7705 IWL_DEBUG_MAC80211("disable hwcrypto key\n");
7706 }
7707 break;
7708 default:
7709 rc = -EINVAL;
7710 }
7711
7712 IWL_DEBUG_MAC80211("leave\n");
7713 mutex_unlock(&priv->mutex);
7714
7715 return rc;
7716}
7717
bb8c093b 7718static int iwl4965_mac_conf_tx(struct ieee80211_hw *hw, int queue,
b481de9c
ZY
7719 const struct ieee80211_tx_queue_params *params)
7720{
bb8c093b 7721 struct iwl4965_priv *priv = hw->priv;
b481de9c
ZY
7722 unsigned long flags;
7723 int q;
b481de9c
ZY
7724
7725 IWL_DEBUG_MAC80211("enter\n");
7726
bb8c093b 7727 if (!iwl4965_is_ready_rf(priv)) {
b481de9c
ZY
7728 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7729 return -EIO;
7730 }
7731
7732 if (queue >= AC_NUM) {
7733 IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
7734 return 0;
7735 }
7736
b481de9c
ZY
7737 if (!priv->qos_data.qos_enable) {
7738 priv->qos_data.qos_active = 0;
7739 IWL_DEBUG_MAC80211("leave - qos not enabled\n");
7740 return 0;
7741 }
7742 q = AC_NUM - 1 - queue;
7743
7744 spin_lock_irqsave(&priv->lock, flags);
7745
7746 priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
7747 priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
7748 priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
7749 priv->qos_data.def_qos_parm.ac[q].edca_txop =
3330d7be 7750 cpu_to_le16((params->txop * 32));
b481de9c
ZY
7751
7752 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
7753 priv->qos_data.qos_active = 1;
7754
7755 spin_unlock_irqrestore(&priv->lock, flags);
7756
7757 mutex_lock(&priv->mutex);
7758 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
bb8c093b
CH
7759 iwl4965_activate_qos(priv, 1);
7760 else if (priv->assoc_id && iwl4965_is_associated(priv))
7761 iwl4965_activate_qos(priv, 0);
b481de9c
ZY
7762
7763 mutex_unlock(&priv->mutex);
7764
b481de9c
ZY
7765 IWL_DEBUG_MAC80211("leave\n");
7766 return 0;
7767}
7768
bb8c093b 7769static int iwl4965_mac_get_tx_stats(struct ieee80211_hw *hw,
b481de9c
ZY
7770 struct ieee80211_tx_queue_stats *stats)
7771{
bb8c093b 7772 struct iwl4965_priv *priv = hw->priv;
b481de9c 7773 int i, avail;
bb8c093b
CH
7774 struct iwl4965_tx_queue *txq;
7775 struct iwl4965_queue *q;
b481de9c
ZY
7776 unsigned long flags;
7777
7778 IWL_DEBUG_MAC80211("enter\n");
7779
bb8c093b 7780 if (!iwl4965_is_ready_rf(priv)) {
b481de9c
ZY
7781 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7782 return -EIO;
7783 }
7784
7785 spin_lock_irqsave(&priv->lock, flags);
7786
7787 for (i = 0; i < AC_NUM; i++) {
7788 txq = &priv->txq[i];
7789 q = &txq->q;
bb8c093b 7790 avail = iwl4965_queue_space(q);
b481de9c
ZY
7791
7792 stats->data[i].len = q->n_window - avail;
7793 stats->data[i].limit = q->n_window - q->high_mark;
7794 stats->data[i].count = q->n_window;
7795
7796 }
7797 spin_unlock_irqrestore(&priv->lock, flags);
7798
7799 IWL_DEBUG_MAC80211("leave\n");
7800
7801 return 0;
7802}
7803
bb8c093b 7804static int iwl4965_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY
7805 struct ieee80211_low_level_stats *stats)
7806{
7807 IWL_DEBUG_MAC80211("enter\n");
7808 IWL_DEBUG_MAC80211("leave\n");
7809
7810 return 0;
7811}
7812
bb8c093b 7813static u64 iwl4965_mac_get_tsf(struct ieee80211_hw *hw)
b481de9c
ZY
7814{
7815 IWL_DEBUG_MAC80211("enter\n");
7816 IWL_DEBUG_MAC80211("leave\n");
7817
7818 return 0;
7819}
7820
bb8c093b 7821static void iwl4965_mac_reset_tsf(struct ieee80211_hw *hw)
b481de9c 7822{
bb8c093b 7823 struct iwl4965_priv *priv = hw->priv;
b481de9c
ZY
7824 unsigned long flags;
7825
7826 mutex_lock(&priv->mutex);
7827 IWL_DEBUG_MAC80211("enter\n");
7828
7829 priv->lq_mngr.lq_ready = 0;
c8b0e6e1 7830#ifdef CONFIG_IWL4965_HT
b481de9c 7831 spin_lock_irqsave(&priv->lock, flags);
fd105e79 7832 memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_info));
b481de9c 7833 spin_unlock_irqrestore(&priv->lock, flags);
c8b0e6e1 7834#endif /* CONFIG_IWL4965_HT */
b481de9c 7835
bb8c093b 7836 iwl4965_reset_qos(priv);
b481de9c
ZY
7837
7838 cancel_delayed_work(&priv->post_associate);
7839
7840 spin_lock_irqsave(&priv->lock, flags);
7841 priv->assoc_id = 0;
7842 priv->assoc_capability = 0;
7843 priv->call_post_assoc_from_beacon = 0;
7844 priv->assoc_station_added = 0;
7845
7846 /* new association get rid of ibss beacon skb */
7847 if (priv->ibss_beacon)
7848 dev_kfree_skb(priv->ibss_beacon);
7849
7850 priv->ibss_beacon = NULL;
7851
7852 priv->beacon_int = priv->hw->conf.beacon_int;
7853 priv->timestamp1 = 0;
7854 priv->timestamp0 = 0;
7855 if ((priv->iw_mode == IEEE80211_IF_TYPE_STA))
7856 priv->beacon_int = 0;
7857
7858 spin_unlock_irqrestore(&priv->lock, flags);
7859
fde3571f
MA
7860 if (!iwl4965_is_ready_rf(priv)) {
7861 IWL_DEBUG_MAC80211("leave - not ready\n");
7862 mutex_unlock(&priv->mutex);
7863 return;
7864 }
7865
052c4b9f 7866 /* we are restarting association process
7867 * clear RXON_FILTER_ASSOC_MSK bit
7868 */
7869 if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
bb8c093b 7870 iwl4965_scan_cancel_timeout(priv, 100);
052c4b9f 7871 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 7872 iwl4965_commit_rxon(priv);
052c4b9f 7873 }
7874
b481de9c
ZY
7875 /* Per mac80211.h: This is only used in IBSS mode... */
7876 if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
052c4b9f 7877
b481de9c
ZY
7878 IWL_DEBUG_MAC80211("leave - not in IBSS\n");
7879 mutex_unlock(&priv->mutex);
7880 return;
7881 }
7882
b481de9c
ZY
7883 priv->only_active_channel = 0;
7884
bb8c093b 7885 iwl4965_set_rate(priv);
b481de9c
ZY
7886
7887 mutex_unlock(&priv->mutex);
7888
7889 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY
7890}
7891
bb8c093b 7892static int iwl4965_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
b481de9c
ZY
7893 struct ieee80211_tx_control *control)
7894{
bb8c093b 7895 struct iwl4965_priv *priv = hw->priv;
b481de9c
ZY
7896 unsigned long flags;
7897
7898 mutex_lock(&priv->mutex);
7899 IWL_DEBUG_MAC80211("enter\n");
7900
bb8c093b 7901 if (!iwl4965_is_ready_rf(priv)) {
b481de9c
ZY
7902 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7903 mutex_unlock(&priv->mutex);
7904 return -EIO;
7905 }
7906
7907 if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
7908 IWL_DEBUG_MAC80211("leave - not IBSS\n");
7909 mutex_unlock(&priv->mutex);
7910 return -EIO;
7911 }
7912
7913 spin_lock_irqsave(&priv->lock, flags);
7914
7915 if (priv->ibss_beacon)
7916 dev_kfree_skb(priv->ibss_beacon);
7917
7918 priv->ibss_beacon = skb;
7919
7920 priv->assoc_id = 0;
7921
7922 IWL_DEBUG_MAC80211("leave\n");
7923 spin_unlock_irqrestore(&priv->lock, flags);
7924
bb8c093b 7925 iwl4965_reset_qos(priv);
b481de9c
ZY
7926
7927 queue_work(priv->workqueue, &priv->post_associate.work);
7928
7929 mutex_unlock(&priv->mutex);
7930
7931 return 0;
7932}
7933
c8b0e6e1 7934#ifdef CONFIG_IWL4965_HT
b481de9c 7935
fd105e79
RR
7936static void iwl4965_ht_info_fill(struct ieee80211_conf *conf,
7937 struct iwl4965_priv *priv)
b481de9c 7938{
fd105e79
RR
7939 struct iwl_ht_info *iwl_conf = &priv->current_ht_config;
7940 struct ieee80211_ht_info *ht_conf = &conf->ht_conf;
7941 struct ieee80211_ht_bss_info *ht_bss_conf = &conf->ht_bss_conf;
b481de9c
ZY
7942
7943 IWL_DEBUG_MAC80211("enter: \n");
7944
fd105e79
RR
7945 if (!(conf->flags & IEEE80211_CONF_SUPPORT_HT_MODE)) {
7946 iwl_conf->is_ht = 0;
7947 return;
b481de9c
ZY
7948 }
7949
fd105e79
RR
7950 iwl_conf->is_ht = 1;
7951 priv->ps_mode = (u8)((ht_conf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2);
7952
7953 if (ht_conf->cap & IEEE80211_HT_CAP_SGI_20)
7954 iwl_conf->sgf |= 0x1;
7955 if (ht_conf->cap & IEEE80211_HT_CAP_SGI_40)
7956 iwl_conf->sgf |= 0x2;
7957
7958 iwl_conf->is_green_field = !!(ht_conf->cap & IEEE80211_HT_CAP_GRN_FLD);
7959 iwl_conf->max_amsdu_size =
7960 !!(ht_conf->cap & IEEE80211_HT_CAP_MAX_AMSDU);
134eb5d3 7961
fd105e79
RR
7962 iwl_conf->supported_chan_width =
7963 !!(ht_conf->cap & IEEE80211_HT_CAP_SUP_WIDTH);
134eb5d3
GC
7964 iwl_conf->extension_chan_offset =
7965 ht_bss_conf->bss_cap & IEEE80211_HT_IE_CHA_SEC_OFFSET;
7966 /* If no above or below channel supplied disable FAT channel */
7967 if (iwl_conf->extension_chan_offset != IWL_EXT_CHANNEL_OFFSET_ABOVE &&
7968 iwl_conf->extension_chan_offset != IWL_EXT_CHANNEL_OFFSET_BELOW)
7969 iwl_conf->supported_chan_width = 0;
7970
fd105e79
RR
7971 iwl_conf->tx_mimo_ps_mode =
7972 (u8)((ht_conf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2);
7973 memcpy(iwl_conf->supp_mcs_set, ht_conf->supp_mcs_set, 16);
7974
7975 iwl_conf->control_channel = ht_bss_conf->primary_channel;
fd105e79
RR
7976 iwl_conf->tx_chan_width =
7977 !!(ht_bss_conf->bss_cap & IEEE80211_HT_IE_CHA_WIDTH);
7978 iwl_conf->ht_protection =
7979 ht_bss_conf->bss_op_mode & IEEE80211_HT_IE_HT_PROTECTION;
7980 iwl_conf->non_GF_STA_present =
7981 !!(ht_bss_conf->bss_op_mode & IEEE80211_HT_IE_NON_GF_STA_PRSNT);
7982
7983 IWL_DEBUG_MAC80211("control channel %d\n",
7984 iwl_conf->control_channel);
b481de9c 7985 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY
7986}
7987
bb8c093b 7988static int iwl4965_mac_conf_ht(struct ieee80211_hw *hw,
fd105e79 7989 struct ieee80211_conf *conf)
b481de9c 7990{
bb8c093b 7991 struct iwl4965_priv *priv = hw->priv;
b481de9c
ZY
7992
7993 IWL_DEBUG_MAC80211("enter: \n");
7994
fd105e79 7995 iwl4965_ht_info_fill(conf, priv);
b481de9c
ZY
7996 iwl4965_set_rxon_chain(priv);
7997
7998 if (priv && priv->assoc_id &&
7999 (priv->iw_mode == IEEE80211_IF_TYPE_STA)) {
8000 unsigned long flags;
8001
8002 spin_lock_irqsave(&priv->lock, flags);
8003 if (priv->beacon_int)
8004 queue_work(priv->workqueue, &priv->post_associate.work);
8005 else
8006 priv->call_post_assoc_from_beacon = 1;
8007 spin_unlock_irqrestore(&priv->lock, flags);
8008 }
8009
fd105e79
RR
8010 IWL_DEBUG_MAC80211("leave:\n");
8011 return 0;
b481de9c
ZY
8012}
8013
c8b0e6e1 8014#endif /*CONFIG_IWL4965_HT*/
b481de9c
ZY
8015
8016/*****************************************************************************
8017 *
8018 * sysfs attributes
8019 *
8020 *****************************************************************************/
8021
c8b0e6e1 8022#ifdef CONFIG_IWL4965_DEBUG
b481de9c
ZY
8023
8024/*
8025 * The following adds a new attribute to the sysfs representation
8026 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
8027 * used for controlling the debug level.
8028 *
8029 * See the level definitions in iwl for details.
8030 */
8031
8032static ssize_t show_debug_level(struct device_driver *d, char *buf)
8033{
bb8c093b 8034 return sprintf(buf, "0x%08X\n", iwl4965_debug_level);
b481de9c
ZY
8035}
8036static ssize_t store_debug_level(struct device_driver *d,
8037 const char *buf, size_t count)
8038{
8039 char *p = (char *)buf;
8040 u32 val;
8041
8042 val = simple_strtoul(p, &p, 0);
8043 if (p == buf)
8044 printk(KERN_INFO DRV_NAME
8045 ": %s is not in hex or decimal form.\n", buf);
8046 else
bb8c093b 8047 iwl4965_debug_level = val;
b481de9c
ZY
8048
8049 return strnlen(buf, count);
8050}
8051
8052static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
8053 show_debug_level, store_debug_level);
8054
c8b0e6e1 8055#endif /* CONFIG_IWL4965_DEBUG */
b481de9c
ZY
8056
8057static ssize_t show_rf_kill(struct device *d,
8058 struct device_attribute *attr, char *buf)
8059{
8060 /*
8061 * 0 - RF kill not enabled
8062 * 1 - SW based RF kill active (sysfs)
8063 * 2 - HW based RF kill active
8064 * 3 - Both HW and SW based RF kill active
8065 */
bb8c093b 8066 struct iwl4965_priv *priv = (struct iwl4965_priv *)d->driver_data;
b481de9c
ZY
8067 int val = (test_bit(STATUS_RF_KILL_SW, &priv->status) ? 0x1 : 0x0) |
8068 (test_bit(STATUS_RF_KILL_HW, &priv->status) ? 0x2 : 0x0);
8069
8070 return sprintf(buf, "%i\n", val);
8071}
8072
8073static ssize_t store_rf_kill(struct device *d,
8074 struct device_attribute *attr,
8075 const char *buf, size_t count)
8076{
bb8c093b 8077 struct iwl4965_priv *priv = (struct iwl4965_priv *)d->driver_data;
b481de9c
ZY
8078
8079 mutex_lock(&priv->mutex);
bb8c093b 8080 iwl4965_radio_kill_sw(priv, buf[0] == '1');
b481de9c
ZY
8081 mutex_unlock(&priv->mutex);
8082
8083 return count;
8084}
8085
8086static DEVICE_ATTR(rf_kill, S_IWUSR | S_IRUGO, show_rf_kill, store_rf_kill);
8087
8088static ssize_t show_temperature(struct device *d,
8089 struct device_attribute *attr, char *buf)
8090{
bb8c093b 8091 struct iwl4965_priv *priv = (struct iwl4965_priv *)d->driver_data;
b481de9c 8092
bb8c093b 8093 if (!iwl4965_is_alive(priv))
b481de9c
ZY
8094 return -EAGAIN;
8095
bb8c093b 8096 return sprintf(buf, "%d\n", iwl4965_hw_get_temperature(priv));
b481de9c
ZY
8097}
8098
8099static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
8100
8101static ssize_t show_rs_window(struct device *d,
8102 struct device_attribute *attr,
8103 char *buf)
8104{
bb8c093b
CH
8105 struct iwl4965_priv *priv = d->driver_data;
8106 return iwl4965_fill_rs_info(priv->hw, buf, IWL_AP_ID);
b481de9c
ZY
8107}
8108static DEVICE_ATTR(rs_window, S_IRUGO, show_rs_window, NULL);
8109
8110static ssize_t show_tx_power(struct device *d,
8111 struct device_attribute *attr, char *buf)
8112{
bb8c093b 8113 struct iwl4965_priv *priv = (struct iwl4965_priv *)d->driver_data;
b481de9c
ZY
8114 return sprintf(buf, "%d\n", priv->user_txpower_limit);
8115}
8116
8117static ssize_t store_tx_power(struct device *d,
8118 struct device_attribute *attr,
8119 const char *buf, size_t count)
8120{
bb8c093b 8121 struct iwl4965_priv *priv = (struct iwl4965_priv *)d->driver_data;
b481de9c
ZY
8122 char *p = (char *)buf;
8123 u32 val;
8124
8125 val = simple_strtoul(p, &p, 10);
8126 if (p == buf)
8127 printk(KERN_INFO DRV_NAME
8128 ": %s is not in decimal form.\n", buf);
8129 else
bb8c093b 8130 iwl4965_hw_reg_set_txpower(priv, val);
b481de9c
ZY
8131
8132 return count;
8133}
8134
8135static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
8136
8137static ssize_t show_flags(struct device *d,
8138 struct device_attribute *attr, char *buf)
8139{
bb8c093b 8140 struct iwl4965_priv *priv = (struct iwl4965_priv *)d->driver_data;
b481de9c
ZY
8141
8142 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
8143}
8144
8145static ssize_t store_flags(struct device *d,
8146 struct device_attribute *attr,
8147 const char *buf, size_t count)
8148{
bb8c093b 8149 struct iwl4965_priv *priv = (struct iwl4965_priv *)d->driver_data;
b481de9c
ZY
8150 u32 flags = simple_strtoul(buf, NULL, 0);
8151
8152 mutex_lock(&priv->mutex);
8153 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
8154 /* Cancel any currently running scans... */
bb8c093b 8155 if (iwl4965_scan_cancel_timeout(priv, 100))
b481de9c
ZY
8156 IWL_WARNING("Could not cancel scan.\n");
8157 else {
8158 IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
8159 flags);
8160 priv->staging_rxon.flags = cpu_to_le32(flags);
bb8c093b 8161 iwl4965_commit_rxon(priv);
b481de9c
ZY
8162 }
8163 }
8164 mutex_unlock(&priv->mutex);
8165
8166 return count;
8167}
8168
8169static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
8170
8171static ssize_t show_filter_flags(struct device *d,
8172 struct device_attribute *attr, char *buf)
8173{
bb8c093b 8174 struct iwl4965_priv *priv = (struct iwl4965_priv *)d->driver_data;
b481de9c
ZY
8175
8176 return sprintf(buf, "0x%04X\n",
8177 le32_to_cpu(priv->active_rxon.filter_flags));
8178}
8179
8180static ssize_t store_filter_flags(struct device *d,
8181 struct device_attribute *attr,
8182 const char *buf, size_t count)
8183{
bb8c093b 8184 struct iwl4965_priv *priv = (struct iwl4965_priv *)d->driver_data;
b481de9c
ZY
8185 u32 filter_flags = simple_strtoul(buf, NULL, 0);
8186
8187 mutex_lock(&priv->mutex);
8188 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
8189 /* Cancel any currently running scans... */
bb8c093b 8190 if (iwl4965_scan_cancel_timeout(priv, 100))
b481de9c
ZY
8191 IWL_WARNING("Could not cancel scan.\n");
8192 else {
8193 IWL_DEBUG_INFO("Committing rxon.filter_flags = "
8194 "0x%04X\n", filter_flags);
8195 priv->staging_rxon.filter_flags =
8196 cpu_to_le32(filter_flags);
bb8c093b 8197 iwl4965_commit_rxon(priv);
b481de9c
ZY
8198 }
8199 }
8200 mutex_unlock(&priv->mutex);
8201
8202 return count;
8203}
8204
8205static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
8206 store_filter_flags);
8207
c8b0e6e1 8208#ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT
b481de9c
ZY
8209
8210static ssize_t show_measurement(struct device *d,
8211 struct device_attribute *attr, char *buf)
8212{
bb8c093b
CH
8213 struct iwl4965_priv *priv = dev_get_drvdata(d);
8214 struct iwl4965_spectrum_notification measure_report;
b481de9c
ZY
8215 u32 size = sizeof(measure_report), len = 0, ofs = 0;
8216 u8 *data = (u8 *) & measure_report;
8217 unsigned long flags;
8218
8219 spin_lock_irqsave(&priv->lock, flags);
8220 if (!(priv->measurement_status & MEASUREMENT_READY)) {
8221 spin_unlock_irqrestore(&priv->lock, flags);
8222 return 0;
8223 }
8224 memcpy(&measure_report, &priv->measure_report, size);
8225 priv->measurement_status = 0;
8226 spin_unlock_irqrestore(&priv->lock, flags);
8227
8228 while (size && (PAGE_SIZE - len)) {
8229 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
8230 PAGE_SIZE - len, 1);
8231 len = strlen(buf);
8232 if (PAGE_SIZE - len)
8233 buf[len++] = '\n';
8234
8235 ofs += 16;
8236 size -= min(size, 16U);
8237 }
8238
8239 return len;
8240}
8241
8242static ssize_t store_measurement(struct device *d,
8243 struct device_attribute *attr,
8244 const char *buf, size_t count)
8245{
bb8c093b 8246 struct iwl4965_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
8247 struct ieee80211_measurement_params params = {
8248 .channel = le16_to_cpu(priv->active_rxon.channel),
8249 .start_time = cpu_to_le64(priv->last_tsf),
8250 .duration = cpu_to_le16(1),
8251 };
8252 u8 type = IWL_MEASURE_BASIC;
8253 u8 buffer[32];
8254 u8 channel;
8255
8256 if (count) {
8257 char *p = buffer;
8258 strncpy(buffer, buf, min(sizeof(buffer), count));
8259 channel = simple_strtoul(p, NULL, 0);
8260 if (channel)
8261 params.channel = channel;
8262
8263 p = buffer;
8264 while (*p && *p != ' ')
8265 p++;
8266 if (*p)
8267 type = simple_strtoul(p + 1, NULL, 0);
8268 }
8269
8270 IWL_DEBUG_INFO("Invoking measurement of type %d on "
8271 "channel %d (for '%s')\n", type, params.channel, buf);
bb8c093b 8272 iwl4965_get_measurement(priv, &params, type);
b481de9c
ZY
8273
8274 return count;
8275}
8276
8277static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
8278 show_measurement, store_measurement);
c8b0e6e1 8279#endif /* CONFIG_IWL4965_SPECTRUM_MEASUREMENT */
b481de9c
ZY
8280
8281static ssize_t store_retry_rate(struct device *d,
8282 struct device_attribute *attr,
8283 const char *buf, size_t count)
8284{
bb8c093b 8285 struct iwl4965_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
8286
8287 priv->retry_rate = simple_strtoul(buf, NULL, 0);
8288 if (priv->retry_rate <= 0)
8289 priv->retry_rate = 1;
8290
8291 return count;
8292}
8293
8294static ssize_t show_retry_rate(struct device *d,
8295 struct device_attribute *attr, char *buf)
8296{
bb8c093b 8297 struct iwl4965_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
8298 return sprintf(buf, "%d", priv->retry_rate);
8299}
8300
8301static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
8302 store_retry_rate);
8303
8304static ssize_t store_power_level(struct device *d,
8305 struct device_attribute *attr,
8306 const char *buf, size_t count)
8307{
bb8c093b 8308 struct iwl4965_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
8309 int rc;
8310 int mode;
8311
8312 mode = simple_strtoul(buf, NULL, 0);
8313 mutex_lock(&priv->mutex);
8314
bb8c093b 8315 if (!iwl4965_is_ready(priv)) {
b481de9c
ZY
8316 rc = -EAGAIN;
8317 goto out;
8318 }
8319
8320 if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
8321 mode = IWL_POWER_AC;
8322 else
8323 mode |= IWL_POWER_ENABLED;
8324
8325 if (mode != priv->power_mode) {
bb8c093b 8326 rc = iwl4965_send_power_mode(priv, IWL_POWER_LEVEL(mode));
b481de9c
ZY
8327 if (rc) {
8328 IWL_DEBUG_MAC80211("failed setting power mode.\n");
8329 goto out;
8330 }
8331 priv->power_mode = mode;
8332 }
8333
8334 rc = count;
8335
8336 out:
8337 mutex_unlock(&priv->mutex);
8338 return rc;
8339}
8340
8341#define MAX_WX_STRING 80
8342
8343/* Values are in microsecond */
8344static const s32 timeout_duration[] = {
8345 350000,
8346 250000,
8347 75000,
8348 37000,
8349 25000,
8350};
8351static const s32 period_duration[] = {
8352 400000,
8353 700000,
8354 1000000,
8355 1000000,
8356 1000000
8357};
8358
8359static ssize_t show_power_level(struct device *d,
8360 struct device_attribute *attr, char *buf)
8361{
bb8c093b 8362 struct iwl4965_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
8363 int level = IWL_POWER_LEVEL(priv->power_mode);
8364 char *p = buf;
8365
8366 p += sprintf(p, "%d ", level);
8367 switch (level) {
8368 case IWL_POWER_MODE_CAM:
8369 case IWL_POWER_AC:
8370 p += sprintf(p, "(AC)");
8371 break;
8372 case IWL_POWER_BATTERY:
8373 p += sprintf(p, "(BATTERY)");
8374 break;
8375 default:
8376 p += sprintf(p,
8377 "(Timeout %dms, Period %dms)",
8378 timeout_duration[level - 1] / 1000,
8379 period_duration[level - 1] / 1000);
8380 }
8381
8382 if (!(priv->power_mode & IWL_POWER_ENABLED))
8383 p += sprintf(p, " OFF\n");
8384 else
8385 p += sprintf(p, " \n");
8386
8387 return (p - buf + 1);
8388
8389}
8390
8391static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
8392 store_power_level);
8393
8394static ssize_t show_channels(struct device *d,
8395 struct device_attribute *attr, char *buf)
8396{
8318d78a
JB
8397 /* all this shit doesn't belong into sysfs anyway */
8398 return 0;
b481de9c
ZY
8399}
8400
8401static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
8402
8403static ssize_t show_statistics(struct device *d,
8404 struct device_attribute *attr, char *buf)
8405{
bb8c093b
CH
8406 struct iwl4965_priv *priv = dev_get_drvdata(d);
8407 u32 size = sizeof(struct iwl4965_notif_statistics);
b481de9c
ZY
8408 u32 len = 0, ofs = 0;
8409 u8 *data = (u8 *) & priv->statistics;
8410 int rc = 0;
8411
bb8c093b 8412 if (!iwl4965_is_alive(priv))
b481de9c
ZY
8413 return -EAGAIN;
8414
8415 mutex_lock(&priv->mutex);
bb8c093b 8416 rc = iwl4965_send_statistics_request(priv);
b481de9c
ZY
8417 mutex_unlock(&priv->mutex);
8418
8419 if (rc) {
8420 len = sprintf(buf,
8421 "Error sending statistics request: 0x%08X\n", rc);
8422 return len;
8423 }
8424
8425 while (size && (PAGE_SIZE - len)) {
8426 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
8427 PAGE_SIZE - len, 1);
8428 len = strlen(buf);
8429 if (PAGE_SIZE - len)
8430 buf[len++] = '\n';
8431
8432 ofs += 16;
8433 size -= min(size, 16U);
8434 }
8435
8436 return len;
8437}
8438
8439static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
8440
8441static ssize_t show_antenna(struct device *d,
8442 struct device_attribute *attr, char *buf)
8443{
bb8c093b 8444 struct iwl4965_priv *priv = dev_get_drvdata(d);
b481de9c 8445
bb8c093b 8446 if (!iwl4965_is_alive(priv))
b481de9c
ZY
8447 return -EAGAIN;
8448
8449 return sprintf(buf, "%d\n", priv->antenna);
8450}
8451
8452static ssize_t store_antenna(struct device *d,
8453 struct device_attribute *attr,
8454 const char *buf, size_t count)
8455{
8456 int ant;
bb8c093b 8457 struct iwl4965_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
8458
8459 if (count == 0)
8460 return 0;
8461
8462 if (sscanf(buf, "%1i", &ant) != 1) {
8463 IWL_DEBUG_INFO("not in hex or decimal form.\n");
8464 return count;
8465 }
8466
8467 if ((ant >= 0) && (ant <= 2)) {
8468 IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
bb8c093b 8469 priv->antenna = (enum iwl4965_antenna)ant;
b481de9c
ZY
8470 } else
8471 IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
8472
8473
8474 return count;
8475}
8476
8477static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
8478
8479static ssize_t show_status(struct device *d,
8480 struct device_attribute *attr, char *buf)
8481{
bb8c093b
CH
8482 struct iwl4965_priv *priv = (struct iwl4965_priv *)d->driver_data;
8483 if (!iwl4965_is_alive(priv))
b481de9c
ZY
8484 return -EAGAIN;
8485 return sprintf(buf, "0x%08x\n", (int)priv->status);
8486}
8487
8488static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
8489
8490static ssize_t dump_error_log(struct device *d,
8491 struct device_attribute *attr,
8492 const char *buf, size_t count)
8493{
8494 char *p = (char *)buf;
8495
8496 if (p[0] == '1')
bb8c093b 8497 iwl4965_dump_nic_error_log((struct iwl4965_priv *)d->driver_data);
b481de9c
ZY
8498
8499 return strnlen(buf, count);
8500}
8501
8502static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
8503
8504static ssize_t dump_event_log(struct device *d,
8505 struct device_attribute *attr,
8506 const char *buf, size_t count)
8507{
8508 char *p = (char *)buf;
8509
8510 if (p[0] == '1')
bb8c093b 8511 iwl4965_dump_nic_event_log((struct iwl4965_priv *)d->driver_data);
b481de9c
ZY
8512
8513 return strnlen(buf, count);
8514}
8515
8516static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
8517
8518/*****************************************************************************
8519 *
8520 * driver setup and teardown
8521 *
8522 *****************************************************************************/
8523
bb8c093b 8524static void iwl4965_setup_deferred_work(struct iwl4965_priv *priv)
b481de9c
ZY
8525{
8526 priv->workqueue = create_workqueue(DRV_NAME);
8527
8528 init_waitqueue_head(&priv->wait_command_queue);
8529
bb8c093b
CH
8530 INIT_WORK(&priv->up, iwl4965_bg_up);
8531 INIT_WORK(&priv->restart, iwl4965_bg_restart);
8532 INIT_WORK(&priv->rx_replenish, iwl4965_bg_rx_replenish);
8533 INIT_WORK(&priv->scan_completed, iwl4965_bg_scan_completed);
8534 INIT_WORK(&priv->request_scan, iwl4965_bg_request_scan);
8535 INIT_WORK(&priv->abort_scan, iwl4965_bg_abort_scan);
8536 INIT_WORK(&priv->rf_kill, iwl4965_bg_rf_kill);
8537 INIT_WORK(&priv->beacon_update, iwl4965_bg_beacon_update);
8538 INIT_DELAYED_WORK(&priv->post_associate, iwl4965_bg_post_associate);
8539 INIT_DELAYED_WORK(&priv->init_alive_start, iwl4965_bg_init_alive_start);
8540 INIT_DELAYED_WORK(&priv->alive_start, iwl4965_bg_alive_start);
8541 INIT_DELAYED_WORK(&priv->scan_check, iwl4965_bg_scan_check);
8542
8543 iwl4965_hw_setup_deferred_work(priv);
b481de9c
ZY
8544
8545 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
bb8c093b 8546 iwl4965_irq_tasklet, (unsigned long)priv);
b481de9c
ZY
8547}
8548
bb8c093b 8549static void iwl4965_cancel_deferred_work(struct iwl4965_priv *priv)
b481de9c 8550{
bb8c093b 8551 iwl4965_hw_cancel_deferred_work(priv);
b481de9c 8552
3ae6a054 8553 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY
8554 cancel_delayed_work(&priv->scan_check);
8555 cancel_delayed_work(&priv->alive_start);
8556 cancel_delayed_work(&priv->post_associate);
8557 cancel_work_sync(&priv->beacon_update);
8558}
8559
bb8c093b 8560static struct attribute *iwl4965_sysfs_entries[] = {
b481de9c
ZY
8561 &dev_attr_antenna.attr,
8562 &dev_attr_channels.attr,
8563 &dev_attr_dump_errors.attr,
8564 &dev_attr_dump_events.attr,
8565 &dev_attr_flags.attr,
8566 &dev_attr_filter_flags.attr,
c8b0e6e1 8567#ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT
b481de9c
ZY
8568 &dev_attr_measurement.attr,
8569#endif
8570 &dev_attr_power_level.attr,
8571 &dev_attr_retry_rate.attr,
8572 &dev_attr_rf_kill.attr,
8573 &dev_attr_rs_window.attr,
8574 &dev_attr_statistics.attr,
8575 &dev_attr_status.attr,
8576 &dev_attr_temperature.attr,
b481de9c
ZY
8577 &dev_attr_tx_power.attr,
8578
8579 NULL
8580};
8581
bb8c093b 8582static struct attribute_group iwl4965_attribute_group = {
b481de9c 8583 .name = NULL, /* put in device directory */
bb8c093b 8584 .attrs = iwl4965_sysfs_entries,
b481de9c
ZY
8585};
8586
bb8c093b
CH
8587static struct ieee80211_ops iwl4965_hw_ops = {
8588 .tx = iwl4965_mac_tx,
8589 .start = iwl4965_mac_start,
8590 .stop = iwl4965_mac_stop,
8591 .add_interface = iwl4965_mac_add_interface,
8592 .remove_interface = iwl4965_mac_remove_interface,
8593 .config = iwl4965_mac_config,
8594 .config_interface = iwl4965_mac_config_interface,
8595 .configure_filter = iwl4965_configure_filter,
8596 .set_key = iwl4965_mac_set_key,
8597 .get_stats = iwl4965_mac_get_stats,
8598 .get_tx_stats = iwl4965_mac_get_tx_stats,
8599 .conf_tx = iwl4965_mac_conf_tx,
8600 .get_tsf = iwl4965_mac_get_tsf,
8601 .reset_tsf = iwl4965_mac_reset_tsf,
8602 .beacon_update = iwl4965_mac_beacon_update,
471b3efd 8603 .bss_info_changed = iwl4965_bss_info_changed,
c8b0e6e1 8604#ifdef CONFIG_IWL4965_HT
bb8c093b 8605 .conf_ht = iwl4965_mac_conf_ht,
9ab46173 8606 .ampdu_action = iwl4965_mac_ampdu_action,
c8b0e6e1 8607#endif /* CONFIG_IWL4965_HT */
bb8c093b 8608 .hw_scan = iwl4965_mac_hw_scan
b481de9c
ZY
8609};
8610
bb8c093b 8611static int iwl4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY
8612{
8613 int err = 0;
bb8c093b 8614 struct iwl4965_priv *priv;
b481de9c
ZY
8615 struct ieee80211_hw *hw;
8616 int i;
5a66926a 8617 DECLARE_MAC_BUF(mac);
b481de9c 8618
6440adb5
CB
8619 /* Disabling hardware scan means that mac80211 will perform scans
8620 * "the hard way", rather than using device's scan. */
bb8c093b 8621 if (iwl4965_param_disable_hw_scan) {
b481de9c 8622 IWL_DEBUG_INFO("Disabling hw_scan\n");
bb8c093b 8623 iwl4965_hw_ops.hw_scan = NULL;
b481de9c
ZY
8624 }
8625
bb8c093b
CH
8626 if ((iwl4965_param_queues_num > IWL_MAX_NUM_QUEUES) ||
8627 (iwl4965_param_queues_num < IWL_MIN_NUM_QUEUES)) {
b481de9c
ZY
8628 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
8629 IWL_MIN_NUM_QUEUES, IWL_MAX_NUM_QUEUES);
8630 err = -EINVAL;
8631 goto out;
8632 }
8633
8634 /* mac80211 allocates memory for this device instance, including
8635 * space for this driver's private structure */
bb8c093b 8636 hw = ieee80211_alloc_hw(sizeof(struct iwl4965_priv), &iwl4965_hw_ops);
b481de9c
ZY
8637 if (hw == NULL) {
8638 IWL_ERROR("Can not allocate network device\n");
8639 err = -ENOMEM;
8640 goto out;
8641 }
8642 SET_IEEE80211_DEV(hw, &pdev->dev);
8643
f51359a8
JB
8644 hw->rate_control_algorithm = "iwl-4965-rs";
8645
b481de9c
ZY
8646 IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
8647 priv = hw->priv;
8648 priv->hw = hw;
8649
8650 priv->pci_dev = pdev;
bb8c093b 8651 priv->antenna = (enum iwl4965_antenna)iwl4965_param_antenna;
c8b0e6e1 8652#ifdef CONFIG_IWL4965_DEBUG
bb8c093b 8653 iwl4965_debug_level = iwl4965_param_debug;
b481de9c
ZY
8654 atomic_set(&priv->restrict_refcnt, 0);
8655#endif
8656 priv->retry_rate = 1;
8657
8658 priv->ibss_beacon = NULL;
8659
8660 /* Tell mac80211 and its clients (e.g. Wireless Extensions)
8661 * the range of signal quality values that we'll provide.
8662 * Negative values for level/noise indicate that we'll provide dBm.
8663 * For WE, at least, non-0 values here *enable* display of values
8664 * in app (iwconfig). */
8665 hw->max_rssi = -20; /* signal level, negative indicates dBm */
8666 hw->max_noise = -20; /* noise level, negative indicates dBm */
8667 hw->max_signal = 100; /* link quality indication (%) */
8668
8669 /* Tell mac80211 our Tx characteristics */
8670 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE;
8671
6440adb5 8672 /* Default value; 4 EDCA QOS priorities */
b481de9c 8673 hw->queues = 4;
c8b0e6e1 8674#ifdef CONFIG_IWL4965_HT
6440adb5 8675 /* Enhanced value; more queues, to support 11n aggregation */
b481de9c 8676 hw->queues = 16;
c8b0e6e1 8677#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY
8678
8679 spin_lock_init(&priv->lock);
8680 spin_lock_init(&priv->power_data.lock);
8681 spin_lock_init(&priv->sta_lock);
8682 spin_lock_init(&priv->hcmd_lock);
8683 spin_lock_init(&priv->lq_mngr.lock);
8684
8685 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
8686 INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
8687
8688 INIT_LIST_HEAD(&priv->free_frames);
8689
8690 mutex_init(&priv->mutex);
8691 if (pci_enable_device(pdev)) {
8692 err = -ENODEV;
8693 goto out_ieee80211_free_hw;
8694 }
8695
8696 pci_set_master(pdev);
8697
6440adb5 8698 /* Clear the driver's (not device's) station table */
bb8c093b 8699 iwl4965_clear_stations_table(priv);
b481de9c
ZY
8700
8701 priv->data_retry_limit = -1;
8702 priv->ieee_channels = NULL;
8703 priv->ieee_rates = NULL;
8318d78a 8704 priv->band = IEEE80211_BAND_2GHZ;
b481de9c
ZY
8705
8706 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
8707 if (!err)
8708 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
8709 if (err) {
8710 printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
8711 goto out_pci_disable_device;
8712 }
8713
8714 pci_set_drvdata(pdev, priv);
8715 err = pci_request_regions(pdev, DRV_NAME);
8716 if (err)
8717 goto out_pci_disable_device;
6440adb5 8718
b481de9c
ZY
8719 /* We disable the RETRY_TIMEOUT register (0x41) to keep
8720 * PCI Tx retries from interfering with C3 CPU state */
8721 pci_write_config_byte(pdev, 0x41, 0x00);
6440adb5 8722
b481de9c
ZY
8723 priv->hw_base = pci_iomap(pdev, 0, 0);
8724 if (!priv->hw_base) {
8725 err = -ENODEV;
8726 goto out_pci_release_regions;
8727 }
8728
8729 IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
8730 (unsigned long long) pci_resource_len(pdev, 0));
8731 IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
8732
8733 /* Initialize module parameter values here */
8734
6440adb5 8735 /* Disable radio (SW RF KILL) via parameter when loading driver */
bb8c093b 8736 if (iwl4965_param_disable) {
b481de9c
ZY
8737 set_bit(STATUS_RF_KILL_SW, &priv->status);
8738 IWL_DEBUG_INFO("Radio disabled.\n");
8739 }
8740
8741 priv->iw_mode = IEEE80211_IF_TYPE_STA;
8742
8743 priv->ps_mode = 0;
8744 priv->use_ant_b_for_management_frame = 1; /* start with ant B */
b481de9c
ZY
8745 priv->valid_antenna = 0x7; /* assume all 3 connected */
8746 priv->ps_mode = IWL_MIMO_PS_NONE;
b481de9c 8747
6440adb5 8748 /* Choose which receivers/antennas to use */
b481de9c
ZY
8749 iwl4965_set_rxon_chain(priv);
8750
8751 printk(KERN_INFO DRV_NAME
8752 ": Detected Intel Wireless WiFi Link 4965AGN\n");
8753
8754 /* Device-specific setup */
bb8c093b 8755 if (iwl4965_hw_set_hw_setting(priv)) {
b481de9c 8756 IWL_ERROR("failed to set hw settings\n");
b481de9c
ZY
8757 goto out_iounmap;
8758 }
8759
bb8c093b 8760 if (iwl4965_param_qos_enable)
b481de9c
ZY
8761 priv->qos_data.qos_enable = 1;
8762
bb8c093b 8763 iwl4965_reset_qos(priv);
b481de9c
ZY
8764
8765 priv->qos_data.qos_active = 0;
8766 priv->qos_data.qos_cap.val = 0;
b481de9c 8767
8318d78a 8768 iwl4965_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
bb8c093b
CH
8769 iwl4965_setup_deferred_work(priv);
8770 iwl4965_setup_rx_handlers(priv);
b481de9c
ZY
8771
8772 priv->rates_mask = IWL_RATES_MASK;
8773 /* If power management is turned on, default to AC mode */
8774 priv->power_mode = IWL_POWER_AC;
8775 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
8776
bb8c093b 8777 iwl4965_disable_interrupts(priv);
49df2b33 8778
bb8c093b 8779 err = sysfs_create_group(&pdev->dev.kobj, &iwl4965_attribute_group);
b481de9c
ZY
8780 if (err) {
8781 IWL_ERROR("failed to create sysfs device attributes\n");
b481de9c
ZY
8782 goto out_release_irq;
8783 }
8784
5a66926a
ZY
8785 /* nic init */
8786 iwl4965_set_bit(priv, CSR_GIO_CHICKEN_BITS,
8787 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
8788
8789 iwl4965_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
8790 err = iwl4965_poll_bit(priv, CSR_GP_CNTRL,
8791 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
8792 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
8793 if (err < 0) {
8794 IWL_DEBUG_INFO("Failed to init the card\n");
8795 goto out_remove_sysfs;
8796 }
8797 /* Read the EEPROM */
8798 err = iwl4965_eeprom_init(priv);
b481de9c 8799 if (err) {
5a66926a
ZY
8800 IWL_ERROR("Unable to init EEPROM\n");
8801 goto out_remove_sysfs;
b481de9c 8802 }
5a66926a
ZY
8803 /* MAC Address location in EEPROM same for 3945/4965 */
8804 get_eeprom_mac(priv, priv->mac_addr);
8805 IWL_DEBUG_INFO("MAC address: %s\n", print_mac(mac, priv->mac_addr));
8806 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
b481de9c 8807
849e0dce
RC
8808 err = iwl4965_init_channel_map(priv);
8809 if (err) {
8810 IWL_ERROR("initializing regulatory failed: %d\n", err);
8811 goto out_remove_sysfs;
8812 }
8813
8814 err = iwl4965_init_geos(priv);
8815 if (err) {
8816 IWL_ERROR("initializing geos failed: %d\n", err);
8817 goto out_free_channel_map;
8818 }
849e0dce 8819
5a66926a
ZY
8820 iwl4965_rate_control_register(priv->hw);
8821 err = ieee80211_register_hw(priv->hw);
8822 if (err) {
8823 IWL_ERROR("Failed to register network device (error %d)\n", err);
849e0dce 8824 goto out_free_geos;
5a66926a 8825 }
b481de9c 8826
5a66926a
ZY
8827 priv->hw->conf.beacon_int = 100;
8828 priv->mac80211_registered = 1;
8829 pci_save_state(pdev);
8830 pci_disable_device(pdev);
b481de9c
ZY
8831
8832 return 0;
8833
849e0dce
RC
8834 out_free_geos:
8835 iwl4965_free_geos(priv);
8836 out_free_channel_map:
8837 iwl4965_free_channel_map(priv);
5a66926a 8838 out_remove_sysfs:
bb8c093b 8839 sysfs_remove_group(&pdev->dev.kobj, &iwl4965_attribute_group);
b481de9c
ZY
8840
8841 out_release_irq:
b481de9c
ZY
8842 destroy_workqueue(priv->workqueue);
8843 priv->workqueue = NULL;
bb8c093b 8844 iwl4965_unset_hw_setting(priv);
b481de9c
ZY
8845
8846 out_iounmap:
8847 pci_iounmap(pdev, priv->hw_base);
8848 out_pci_release_regions:
8849 pci_release_regions(pdev);
8850 out_pci_disable_device:
8851 pci_disable_device(pdev);
8852 pci_set_drvdata(pdev, NULL);
8853 out_ieee80211_free_hw:
8854 ieee80211_free_hw(priv->hw);
8855 out:
8856 return err;
8857}
8858
bb8c093b 8859static void iwl4965_pci_remove(struct pci_dev *pdev)
b481de9c 8860{
bb8c093b 8861 struct iwl4965_priv *priv = pci_get_drvdata(pdev);
b481de9c
ZY
8862 struct list_head *p, *q;
8863 int i;
8864
8865 if (!priv)
8866 return;
8867
8868 IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
8869
b481de9c 8870 set_bit(STATUS_EXIT_PENDING, &priv->status);
b24d22b1 8871
bb8c093b 8872 iwl4965_down(priv);
b481de9c
ZY
8873
8874 /* Free MAC hash list for ADHOC */
8875 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) {
8876 list_for_each_safe(p, q, &priv->ibss_mac_hash[i]) {
8877 list_del(p);
bb8c093b 8878 kfree(list_entry(p, struct iwl4965_ibss_seq, list));
b481de9c
ZY
8879 }
8880 }
8881
bb8c093b 8882 sysfs_remove_group(&pdev->dev.kobj, &iwl4965_attribute_group);
b481de9c 8883
bb8c093b 8884 iwl4965_dealloc_ucode_pci(priv);
b481de9c
ZY
8885
8886 if (priv->rxq.bd)
bb8c093b
CH
8887 iwl4965_rx_queue_free(priv, &priv->rxq);
8888 iwl4965_hw_txq_ctx_free(priv);
b481de9c 8889
bb8c093b
CH
8890 iwl4965_unset_hw_setting(priv);
8891 iwl4965_clear_stations_table(priv);
b481de9c
ZY
8892
8893 if (priv->mac80211_registered) {
8894 ieee80211_unregister_hw(priv->hw);
bb8c093b 8895 iwl4965_rate_control_unregister(priv->hw);
b481de9c
ZY
8896 }
8897
948c171c
MA
8898 /*netif_stop_queue(dev); */
8899 flush_workqueue(priv->workqueue);
8900
bb8c093b 8901 /* ieee80211_unregister_hw calls iwl4965_mac_stop, which flushes
b481de9c
ZY
8902 * priv->workqueue... so we can't take down the workqueue
8903 * until now... */
8904 destroy_workqueue(priv->workqueue);
8905 priv->workqueue = NULL;
8906
b481de9c
ZY
8907 pci_iounmap(pdev, priv->hw_base);
8908 pci_release_regions(pdev);
8909 pci_disable_device(pdev);
8910 pci_set_drvdata(pdev, NULL);
8911
849e0dce
RC
8912 iwl4965_free_channel_map(priv);
8913 iwl4965_free_geos(priv);
b481de9c
ZY
8914
8915 if (priv->ibss_beacon)
8916 dev_kfree_skb(priv->ibss_beacon);
8917
8918 ieee80211_free_hw(priv->hw);
8919}
8920
8921#ifdef CONFIG_PM
8922
bb8c093b 8923static int iwl4965_pci_suspend(struct pci_dev *pdev, pm_message_t state)
b481de9c 8924{
bb8c093b 8925 struct iwl4965_priv *priv = pci_get_drvdata(pdev);
b481de9c 8926
e655b9f0
ZY
8927 if (priv->is_open) {
8928 set_bit(STATUS_IN_SUSPEND, &priv->status);
8929 iwl4965_mac_stop(priv->hw);
8930 priv->is_open = 1;
8931 }
b481de9c 8932
b481de9c
ZY
8933 pci_set_power_state(pdev, PCI_D3hot);
8934
b481de9c
ZY
8935 return 0;
8936}
8937
bb8c093b 8938static int iwl4965_pci_resume(struct pci_dev *pdev)
b481de9c 8939{
bb8c093b 8940 struct iwl4965_priv *priv = pci_get_drvdata(pdev);
b481de9c 8941
b481de9c 8942 pci_set_power_state(pdev, PCI_D0);
b481de9c 8943
e655b9f0
ZY
8944 if (priv->is_open)
8945 iwl4965_mac_start(priv->hw);
b481de9c 8946
e655b9f0 8947 clear_bit(STATUS_IN_SUSPEND, &priv->status);
b481de9c
ZY
8948 return 0;
8949}
8950
8951#endif /* CONFIG_PM */
8952
8953/*****************************************************************************
8954 *
8955 * driver and module entry point
8956 *
8957 *****************************************************************************/
8958
bb8c093b 8959static struct pci_driver iwl4965_driver = {
b481de9c 8960 .name = DRV_NAME,
bb8c093b
CH
8961 .id_table = iwl4965_hw_card_ids,
8962 .probe = iwl4965_pci_probe,
8963 .remove = __devexit_p(iwl4965_pci_remove),
b481de9c 8964#ifdef CONFIG_PM
bb8c093b
CH
8965 .suspend = iwl4965_pci_suspend,
8966 .resume = iwl4965_pci_resume,
b481de9c
ZY
8967#endif
8968};
8969
bb8c093b 8970static int __init iwl4965_init(void)
b481de9c
ZY
8971{
8972
8973 int ret;
8974 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
8975 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
bb8c093b 8976 ret = pci_register_driver(&iwl4965_driver);
b481de9c
ZY
8977 if (ret) {
8978 IWL_ERROR("Unable to initialize PCI module\n");
8979 return ret;
8980 }
c8b0e6e1 8981#ifdef CONFIG_IWL4965_DEBUG
bb8c093b 8982 ret = driver_create_file(&iwl4965_driver.driver, &driver_attr_debug_level);
b481de9c
ZY
8983 if (ret) {
8984 IWL_ERROR("Unable to create driver sysfs file\n");
bb8c093b 8985 pci_unregister_driver(&iwl4965_driver);
b481de9c
ZY
8986 return ret;
8987 }
8988#endif
8989
8990 return ret;
8991}
8992
bb8c093b 8993static void __exit iwl4965_exit(void)
b481de9c 8994{
c8b0e6e1 8995#ifdef CONFIG_IWL4965_DEBUG
bb8c093b 8996 driver_remove_file(&iwl4965_driver.driver, &driver_attr_debug_level);
b481de9c 8997#endif
bb8c093b 8998 pci_unregister_driver(&iwl4965_driver);
b481de9c
ZY
8999}
9000
bb8c093b 9001module_param_named(antenna, iwl4965_param_antenna, int, 0444);
b481de9c 9002MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
bb8c093b 9003module_param_named(disable, iwl4965_param_disable, int, 0444);
b481de9c 9004MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
bb8c093b 9005module_param_named(hwcrypto, iwl4965_param_hwcrypto, int, 0444);
b481de9c
ZY
9006MODULE_PARM_DESC(hwcrypto,
9007 "using hardware crypto engine (default 0 [software])\n");
bb8c093b 9008module_param_named(debug, iwl4965_param_debug, int, 0444);
b481de9c 9009MODULE_PARM_DESC(debug, "debug output mask");
bb8c093b 9010module_param_named(disable_hw_scan, iwl4965_param_disable_hw_scan, int, 0444);
b481de9c
ZY
9011MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
9012
bb8c093b 9013module_param_named(queues_num, iwl4965_param_queues_num, int, 0444);
b481de9c
ZY
9014MODULE_PARM_DESC(queues_num, "number of hw queues.");
9015
9016/* QoS */
bb8c093b 9017module_param_named(qos_enable, iwl4965_param_qos_enable, int, 0444);
b481de9c 9018MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
9ee1ba47
RR
9019module_param_named(amsdu_size_8K, iwl4965_param_amsdu_size_8K, int, 0444);
9020MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
b481de9c 9021
bb8c093b
CH
9022module_exit(iwl4965_exit);
9023module_init(iwl4965_init);
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