iwlwifi: pcie: provide a way to stop configuration if it is forbidden
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / mvm / fw-api.h
CommitLineData
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1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
51368bf7 8 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
ee9219b2 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
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10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
23 * USA
24 *
25 * The full GNU General Public License is included in this distribution
410dc5aa 26 * in the file called COPYING.
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27 *
28 * Contact Information:
29 * Intel Linux Wireless <ilw@linux.intel.com>
30 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 *
32 * BSD LICENSE
33 *
51368bf7 34 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
ee9219b2 35 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
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36 * All rights reserved.
37 *
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
40 * are met:
41 *
42 * * Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * * Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in
46 * the documentation and/or other materials provided with the
47 * distribution.
48 * * Neither the name Intel Corporation nor the names of its
49 * contributors may be used to endorse or promote products derived
50 * from this software without specific prior written permission.
51 *
52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *
64 *****************************************************************************/
65
66#ifndef __fw_api_h__
67#define __fw_api_h__
68
69#include "fw-api-rs.h"
70#include "fw-api-tx.h"
71#include "fw-api-sta.h"
72#include "fw-api-mac.h"
73#include "fw-api-power.h"
74#include "fw-api-d3.h"
5b7ff615 75#include "fw-api-coex.h"
e820c2da 76#include "fw-api-scan.h"
d19ac589 77#include "fw-api-stats.h"
ce792918 78#include "fw-api-tof.h"
8ca151b5 79
19e737c9 80/* Tx queue numbers */
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81enum {
82 IWL_MVM_OFFCHANNEL_QUEUE = 8,
83 IWL_MVM_CMD_QUEUE = 9,
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84};
85
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86enum iwl_mvm_tx_fifo {
87 IWL_MVM_TX_FIFO_BK = 0,
88 IWL_MVM_TX_FIFO_BE,
89 IWL_MVM_TX_FIFO_VI,
90 IWL_MVM_TX_FIFO_VO,
91 IWL_MVM_TX_FIFO_MCAST = 5,
92 IWL_MVM_TX_FIFO_CMD = 7,
93};
19e737c9 94
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95#define IWL_MVM_STATION_COUNT 16
96
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97#define IWL_MVM_TDLS_STA_COUNT 4
98
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99/* commands */
100enum {
101 MVM_ALIVE = 0x1,
102 REPLY_ERROR = 0x2,
103
104 INIT_COMPLETE_NOTIF = 0x4,
105
106 /* PHY context commands */
107 PHY_CONTEXT_CMD = 0x8,
108 DBG_CFG = 0x9,
b9fae2d5 109 ANTENNA_COUPLING_NOTIFICATION = 0xa,
8ca151b5 110
d2496221 111 /* UMAC scan commands */
ee9219b2 112 SCAN_ITERATION_COMPLETE_UMAC = 0xb5,
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113 SCAN_CFG_CMD = 0xc,
114 SCAN_REQ_UMAC = 0xd,
115 SCAN_ABORT_UMAC = 0xe,
116 SCAN_COMPLETE_UMAC = 0xf,
117
8ca151b5 118 /* station table */
5a258aae 119 ADD_STA_KEY = 0x17,
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120 ADD_STA = 0x18,
121 REMOVE_STA = 0x19,
122
123 /* TX */
124 TX_CMD = 0x1c,
125 TXPATH_FLUSH = 0x1e,
126 MGMT_MCAST_KEY = 0x1f,
127
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128 /* scheduler config */
129 SCD_QUEUE_CFG = 0x1d,
130
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131 /* global key */
132 WEP_KEY = 0x20,
133
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134 /* Memory */
135 SHARED_MEM_CFG = 0x25,
136
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137 /* TDLS */
138 TDLS_CHANNEL_SWITCH_CMD = 0x27,
139 TDLS_CHANNEL_SWITCH_NOTIFICATION = 0xaa,
307e4723 140 TDLS_CONFIG_CMD = 0xa7,
77c5d7ef 141
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142 /* MAC and Binding commands */
143 MAC_CONTEXT_CMD = 0x28,
144 TIME_EVENT_CMD = 0x29, /* both CMD and response */
145 TIME_EVENT_NOTIFICATION = 0x2a,
146 BINDING_CONTEXT_CMD = 0x2b,
147 TIME_QUOTA_CMD = 0x2c,
4ac6cb59 148 NON_QOS_TX_COUNTER_CMD = 0x2d,
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149
150 LQ_CMD = 0x4e,
151
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152 /* Scan offload */
153 SCAN_OFFLOAD_REQUEST_CMD = 0x51,
154 SCAN_OFFLOAD_ABORT_CMD = 0x52,
720befbf 155 HOT_SPOT_CMD = 0x53,
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156 SCAN_OFFLOAD_COMPLETE = 0x6D,
157 SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6E,
158 SCAN_OFFLOAD_CONFIG_CMD = 0x6f,
35a000b7 159 MATCH_FOUND_NOTIFICATION = 0xd9,
fb98be5e 160 SCAN_ITERATION_COMPLETE = 0xe7,
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161
162 /* Phy */
163 PHY_CONFIGURATION_CMD = 0x6a,
164 CALIB_RES_NOTIF_PHY_DB = 0x6b,
165 /* PHY_DB_CMD = 0x6c, */
166
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167 /* ToF - 802.11mc FTM */
168 TOF_CMD = 0x10,
169 TOF_NOTIFICATION = 0x11,
170
e811ada7 171 /* Power - legacy power table command */
8ca151b5 172 POWER_TABLE_CMD = 0x77,
175a70b7 173 PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78,
9180ac50 174 LTR_CONFIG = 0xee,
8ca151b5 175
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176 /* Thermal Throttling*/
177 REPLY_THERMAL_MNG_BACKOFF = 0x7e,
178
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179 /* Set/Get DC2DC frequency tune */
180 DC2DC_CONFIG_CMD = 0x83,
181
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182 /* NVM */
183 NVM_ACCESS_CMD = 0x88,
184
185 SET_CALIB_DEFAULT_CMD = 0x8e,
186
571765c8 187 BEACON_NOTIFICATION = 0x90,
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188 BEACON_TEMPLATE_CMD = 0x91,
189 TX_ANT_CONFIGURATION_CMD = 0x98,
91a8bcde 190 STATISTICS_CMD = 0x9c,
8ca151b5 191 STATISTICS_NOTIFICATION = 0x9d,
3e56eadf 192 EOSP_NOTIFICATION = 0x9e,
88f2fd73 193 REDUCE_TX_POWER_CMD = 0x9f,
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194
195 /* RF-KILL commands and notifications */
196 CARD_STATE_CMD = 0xa0,
197 CARD_STATE_NOTIFICATION = 0xa1,
198
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199 MISSED_BEACONS_NOTIFICATION = 0xa2,
200
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201 /* Power - new power table command */
202 MAC_PM_POWER_TABLE = 0xa9,
203
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204 MFUART_LOAD_NOTIFICATION = 0xb1,
205
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206 REPLY_RX_PHY_CMD = 0xc0,
207 REPLY_RX_MPDU_CMD = 0xc1,
208 BA_NOTIF = 0xc5,
209
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210 /* Location Aware Regulatory */
211 MCC_UPDATE_CMD = 0xc8,
88931cc9 212 MCC_CHUB_UPDATE_CMD = 0xc9,
dcaf9f5e 213
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214 MARKER_CMD = 0xcb,
215
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216 /* BT Coex */
217 BT_COEX_PRIO_TABLE = 0xcc,
218 BT_COEX_PROT_ENV = 0xcd,
219 BT_PROFILE_NOTIFICATION = 0xce,
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220 BT_CONFIG = 0x9b,
221 BT_COEX_UPDATE_SW_BOOST = 0x5a,
222 BT_COEX_UPDATE_CORUN_LUT = 0x5b,
223 BT_COEX_UPDATE_REDUCED_TXP = 0x5c,
dac94da8 224 BT_COEX_CI = 0x5d,
fb3ceb81 225
1f3b0ff8 226 REPLY_SF_CFG_CMD = 0xd1,
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227 REPLY_BEACON_FILTERING_CMD = 0xd2,
228
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229 /* DTS measurements */
230 CMD_DTS_MEASUREMENT_TRIGGER = 0xdc,
231 DTS_MEASUREMENT_NOTIFICATION = 0xdd,
232
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233 REPLY_DEBUG_CMD = 0xf0,
234 DEBUG_LOG_MSG = 0xf7,
235
c87163b9 236 BCAST_FILTER_CMD = 0xcf,
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237 MCAST_FILTER_CMD = 0xd0,
238
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239 /* D3 commands/notifications */
240 D3_CONFIG_CMD = 0xd3,
241 PROT_OFFLOAD_CONFIG_CMD = 0xd4,
242 OFFLOADS_QUERY_CMD = 0xd5,
243 REMOTE_WAKE_CONFIG_CMD = 0xd6,
98ee7783 244 D0I3_END_CMD = 0xed,
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245
246 /* for WoWLAN in particular */
247 WOWLAN_PATTERNS = 0xe0,
248 WOWLAN_CONFIGURATION = 0xe1,
249 WOWLAN_TSC_RSC_PARAM = 0xe2,
250 WOWLAN_TKIP_PARAM = 0xe3,
251 WOWLAN_KEK_KCK_MATERIAL = 0xe4,
252 WOWLAN_GET_STATUSES = 0xe5,
253 WOWLAN_TX_POWER_PER_DB = 0xe6,
254
255 /* and for NetDetect */
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LC
256 SCAN_OFFLOAD_PROFILES_QUERY_CMD = 0x56,
257 SCAN_OFFLOAD_HOTSPOTS_CONFIG_CMD = 0x58,
258 SCAN_OFFLOAD_HOTSPOTS_QUERY_CMD = 0x59,
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259
260 REPLY_MAX = 0xff,
261};
262
263/**
264 * struct iwl_cmd_response - generic response struct for most commands
265 * @status: status of the command asked, changes for each one
266 */
267struct iwl_cmd_response {
268 __le32 status;
269};
270
271/*
272 * struct iwl_tx_ant_cfg_cmd
273 * @valid: valid antenna configuration
274 */
275struct iwl_tx_ant_cfg_cmd {
276 __le32 valid;
277} __packed;
278
279/*
280 * Calibration control struct.
281 * Sent as part of the phy configuration command.
282 * @flow_trigger: bitmap for which calibrations to perform according to
283 * flow triggers.
284 * @event_trigger: bitmap for which calibrations to perform according to
285 * event triggers.
286 */
287struct iwl_calib_ctrl {
288 __le32 flow_trigger;
289 __le32 event_trigger;
290} __packed;
291
292/* This enum defines the bitmap of various calibrations to enable in both
293 * init ucode and runtime ucode through CALIBRATION_CFG_CMD.
294 */
295enum iwl_calib_cfg {
296 IWL_CALIB_CFG_XTAL_IDX = BIT(0),
297 IWL_CALIB_CFG_TEMPERATURE_IDX = BIT(1),
298 IWL_CALIB_CFG_VOLTAGE_READ_IDX = BIT(2),
299 IWL_CALIB_CFG_PAPD_IDX = BIT(3),
300 IWL_CALIB_CFG_TX_PWR_IDX = BIT(4),
301 IWL_CALIB_CFG_DC_IDX = BIT(5),
302 IWL_CALIB_CFG_BB_FILTER_IDX = BIT(6),
303 IWL_CALIB_CFG_LO_LEAKAGE_IDX = BIT(7),
304 IWL_CALIB_CFG_TX_IQ_IDX = BIT(8),
305 IWL_CALIB_CFG_TX_IQ_SKEW_IDX = BIT(9),
306 IWL_CALIB_CFG_RX_IQ_IDX = BIT(10),
307 IWL_CALIB_CFG_RX_IQ_SKEW_IDX = BIT(11),
308 IWL_CALIB_CFG_SENSITIVITY_IDX = BIT(12),
309 IWL_CALIB_CFG_CHAIN_NOISE_IDX = BIT(13),
310 IWL_CALIB_CFG_DISCONNECTED_ANT_IDX = BIT(14),
311 IWL_CALIB_CFG_ANT_COUPLING_IDX = BIT(15),
312 IWL_CALIB_CFG_DAC_IDX = BIT(16),
313 IWL_CALIB_CFG_ABS_IDX = BIT(17),
314 IWL_CALIB_CFG_AGC_IDX = BIT(18),
315};
316
317/*
318 * Phy configuration command.
319 */
320struct iwl_phy_cfg_cmd {
321 __le32 phy_cfg;
322 struct iwl_calib_ctrl calib_control;
323} __packed;
324
325#define PHY_CFG_RADIO_TYPE (BIT(0) | BIT(1))
326#define PHY_CFG_RADIO_STEP (BIT(2) | BIT(3))
327#define PHY_CFG_RADIO_DASH (BIT(4) | BIT(5))
328#define PHY_CFG_PRODUCT_NUMBER (BIT(6) | BIT(7))
329#define PHY_CFG_TX_CHAIN_A BIT(8)
330#define PHY_CFG_TX_CHAIN_B BIT(9)
331#define PHY_CFG_TX_CHAIN_C BIT(10)
332#define PHY_CFG_RX_CHAIN_A BIT(12)
333#define PHY_CFG_RX_CHAIN_B BIT(13)
334#define PHY_CFG_RX_CHAIN_C BIT(14)
335
336
337/* Target of the NVM_ACCESS_CMD */
338enum {
339 NVM_ACCESS_TARGET_CACHE = 0,
340 NVM_ACCESS_TARGET_OTP = 1,
341 NVM_ACCESS_TARGET_EEPROM = 2,
342};
343
b9545b48 344/* Section types for NVM_ACCESS_CMD */
8ca151b5 345enum {
ae2b21b0 346 NVM_SECTION_TYPE_SW = 1,
77db0a3c 347 NVM_SECTION_TYPE_REGULATORY = 3,
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348 NVM_SECTION_TYPE_CALIBRATION = 4,
349 NVM_SECTION_TYPE_PRODUCTION = 5,
77db0a3c 350 NVM_SECTION_TYPE_MAC_OVERRIDE = 11,
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351 NVM_SECTION_TYPE_PHY_SKU = 12,
352 NVM_MAX_NUM_SECTIONS = 13,
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353};
354
355/**
356 * struct iwl_nvm_access_cmd_ver2 - Request the device to send an NVM section
357 * @op_code: 0 - read, 1 - write
358 * @target: NVM_ACCESS_TARGET_*
359 * @type: NVM_SECTION_TYPE_*
360 * @offset: offset in bytes into the section
361 * @length: in bytes, to read/write
362 * @data: if write operation, the data to write. On read its empty
363 */
b9545b48 364struct iwl_nvm_access_cmd {
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365 u8 op_code;
366 u8 target;
367 __le16 type;
368 __le16 offset;
369 __le16 length;
370 u8 data[];
371} __packed; /* NVM_ACCESS_CMD_API_S_VER_2 */
372
373/**
374 * struct iwl_nvm_access_resp_ver2 - response to NVM_ACCESS_CMD
375 * @offset: offset in bytes into the section
376 * @length: in bytes, either how much was written or read
377 * @type: NVM_SECTION_TYPE_*
378 * @status: 0 for success, fail otherwise
379 * @data: if read operation, the data returned. Empty on write.
380 */
b9545b48 381struct iwl_nvm_access_resp {
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382 __le16 offset;
383 __le16 length;
384 __le16 type;
385 __le16 status;
386 u8 data[];
387} __packed; /* NVM_ACCESS_CMD_RESP_API_S_VER_2 */
388
389/* MVM_ALIVE 0x1 */
390
391/* alive response is_valid values */
392#define ALIVE_RESP_UCODE_OK BIT(0)
393#define ALIVE_RESP_RFKILL BIT(1)
394
395/* alive response ver_type values */
396enum {
397 FW_TYPE_HW = 0,
398 FW_TYPE_PROT = 1,
399 FW_TYPE_AP = 2,
400 FW_TYPE_WOWLAN = 3,
401 FW_TYPE_TIMING = 4,
402 FW_TYPE_WIPAN = 5
403};
404
405/* alive response ver_subtype values */
406enum {
407 FW_SUBTYPE_FULL_FEATURE = 0,
408 FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */
409 FW_SUBTYPE_REDUCED = 2,
410 FW_SUBTYPE_ALIVE_ONLY = 3,
411 FW_SUBTYPE_WOWLAN = 4,
412 FW_SUBTYPE_AP_SUBTYPE = 5,
413 FW_SUBTYPE_WIPAN = 6,
414 FW_SUBTYPE_INITIALIZE = 9
415};
416
417#define IWL_ALIVE_STATUS_ERR 0xDEAD
418#define IWL_ALIVE_STATUS_OK 0xCAFE
419
420#define IWL_ALIVE_FLG_RFKILL BIT(0)
421
7e1223b5 422struct mvm_alive_resp_ver1 {
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423 __le16 status;
424 __le16 flags;
425 u8 ucode_minor;
426 u8 ucode_major;
427 __le16 id;
428 u8 api_minor;
429 u8 api_major;
430 u8 ver_subtype;
431 u8 ver_type;
432 u8 mac;
433 u8 opt;
434 __le16 reserved2;
435 __le32 timestamp;
436 __le32 error_event_table_ptr; /* SRAM address for error log */
437 __le32 log_event_table_ptr; /* SRAM address for event log */
438 __le32 cpu_register_ptr;
439 __le32 dbgm_config_ptr;
440 __le32 alive_counter_ptr;
441 __le32 scd_base_ptr; /* SRAM address for SCD */
442} __packed; /* ALIVE_RES_API_S_VER_1 */
443
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EH
444struct mvm_alive_resp_ver2 {
445 __le16 status;
446 __le16 flags;
447 u8 ucode_minor;
448 u8 ucode_major;
449 __le16 id;
450 u8 api_minor;
451 u8 api_major;
452 u8 ver_subtype;
453 u8 ver_type;
454 u8 mac;
455 u8 opt;
456 __le16 reserved2;
457 __le32 timestamp;
458 __le32 error_event_table_ptr; /* SRAM address for error log */
459 __le32 log_event_table_ptr; /* SRAM address for LMAC event log */
460 __le32 cpu_register_ptr;
461 __le32 dbgm_config_ptr;
462 __le32 alive_counter_ptr;
463 __le32 scd_base_ptr; /* SRAM address for SCD */
464 __le32 st_fwrd_addr; /* pointer to Store and forward */
465 __le32 st_fwrd_size;
466 u8 umac_minor; /* UMAC version: minor */
467 u8 umac_major; /* UMAC version: major */
468 __le16 umac_id; /* UMAC version: id */
469 __le32 error_info_addr; /* SRAM address for UMAC error log */
470 __le32 dbg_print_buff_addr;
471} __packed; /* ALIVE_RES_API_S_VER_2 */
472
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EG
473struct mvm_alive_resp {
474 __le16 status;
475 __le16 flags;
476 __le32 ucode_minor;
477 __le32 ucode_major;
478 u8 ver_subtype;
479 u8 ver_type;
480 u8 mac;
481 u8 opt;
482 __le32 timestamp;
483 __le32 error_event_table_ptr; /* SRAM address for error log */
484 __le32 log_event_table_ptr; /* SRAM address for LMAC event log */
485 __le32 cpu_register_ptr;
486 __le32 dbgm_config_ptr;
487 __le32 alive_counter_ptr;
488 __le32 scd_base_ptr; /* SRAM address for SCD */
489 __le32 st_fwrd_addr; /* pointer to Store and forward */
490 __le32 st_fwrd_size;
491 __le32 umac_minor; /* UMAC version: minor */
492 __le32 umac_major; /* UMAC version: major */
493 __le32 error_info_addr; /* SRAM address for UMAC error log */
494 __le32 dbg_print_buff_addr;
495} __packed; /* ALIVE_RES_API_S_VER_3 */
496
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497/* Error response/notification */
498enum {
499 FW_ERR_UNKNOWN_CMD = 0x0,
500 FW_ERR_INVALID_CMD_PARAM = 0x1,
501 FW_ERR_SERVICE = 0x2,
502 FW_ERR_ARC_MEMORY = 0x3,
503 FW_ERR_ARC_CODE = 0x4,
504 FW_ERR_WATCH_DOG = 0x5,
505 FW_ERR_WEP_GRP_KEY_INDX = 0x10,
506 FW_ERR_WEP_KEY_SIZE = 0x11,
507 FW_ERR_OBSOLETE_FUNC = 0x12,
508 FW_ERR_UNEXPECTED = 0xFE,
509 FW_ERR_FATAL = 0xFF
510};
511
512/**
513 * struct iwl_error_resp - FW error indication
514 * ( REPLY_ERROR = 0x2 )
515 * @error_type: one of FW_ERR_*
516 * @cmd_id: the command ID for which the error occured
517 * @bad_cmd_seq_num: sequence number of the erroneous command
518 * @error_service: which service created the error, applicable only if
519 * error_type = 2, otherwise 0
520 * @timestamp: TSF in usecs.
521 */
522struct iwl_error_resp {
523 __le32 error_type;
524 u8 cmd_id;
525 u8 reserved1;
526 __le16 bad_cmd_seq_num;
527 __le32 error_service;
528 __le64 timestamp;
529} __packed;
530
531
532/* Common PHY, MAC and Bindings definitions */
533
534#define MAX_MACS_IN_BINDING (3)
535#define MAX_BINDINGS (4)
536#define AUX_BINDING_INDEX (3)
537#define MAX_PHYS (4)
538
539/* Used to extract ID and color from the context dword */
540#define FW_CTXT_ID_POS (0)
541#define FW_CTXT_ID_MSK (0xff << FW_CTXT_ID_POS)
542#define FW_CTXT_COLOR_POS (8)
543#define FW_CTXT_COLOR_MSK (0xff << FW_CTXT_COLOR_POS)
544#define FW_CTXT_INVALID (0xffffffff)
545
546#define FW_CMD_ID_AND_COLOR(_id, _color) ((_id << FW_CTXT_ID_POS) |\
547 (_color << FW_CTXT_COLOR_POS))
548
549/* Possible actions on PHYs, MACs and Bindings */
550enum {
551 FW_CTXT_ACTION_STUB = 0,
552 FW_CTXT_ACTION_ADD,
553 FW_CTXT_ACTION_MODIFY,
554 FW_CTXT_ACTION_REMOVE,
555 FW_CTXT_ACTION_NUM
556}; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */
557
558/* Time Events */
559
560/* Time Event types, according to MAC type */
561enum iwl_time_event_type {
562 /* BSS Station Events */
563 TE_BSS_STA_AGGRESSIVE_ASSOC,
564 TE_BSS_STA_ASSOC,
565 TE_BSS_EAP_DHCP_PROT,
566 TE_BSS_QUIET_PERIOD,
567
568 /* P2P Device Events */
569 TE_P2P_DEVICE_DISCOVERABLE,
570 TE_P2P_DEVICE_LISTEN,
571 TE_P2P_DEVICE_ACTION_SCAN,
572 TE_P2P_DEVICE_FULL_SCAN,
573
574 /* P2P Client Events */
575 TE_P2P_CLIENT_AGGRESSIVE_ASSOC,
576 TE_P2P_CLIENT_ASSOC,
577 TE_P2P_CLIENT_QUIET_PERIOD,
578
579 /* P2P GO Events */
580 TE_P2P_GO_ASSOC_PROT,
581 TE_P2P_GO_REPETITIVE_NOA,
582 TE_P2P_GO_CT_WINDOW,
583
584 /* WiDi Sync Events */
585 TE_WIDI_TX_SYNC,
586
7f0a7c67 587 /* Channel Switch NoA */
f991e17b 588 TE_CHANNEL_SWITCH_PERIOD,
7f0a7c67 589
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590 TE_MAX
591}; /* MAC_EVENT_TYPE_API_E_VER_1 */
592
f8f03c3e
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593
594
595/* Time event - defines for command API v1 */
596
597/*
598 * @TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed.
599 * @TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only
600 * the first fragment is scheduled.
601 * @TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only
602 * the first 2 fragments are scheduled.
603 * @TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
604 * number of fragments are valid.
605 *
606 * Other than the constant defined above, specifying a fragmentation value 'x'
607 * means that the event can be fragmented but only the first 'x' will be
608 * scheduled.
609 */
610enum {
611 TE_V1_FRAG_NONE = 0,
612 TE_V1_FRAG_SINGLE = 1,
613 TE_V1_FRAG_DUAL = 2,
614 TE_V1_FRAG_ENDLESS = 0xffffffff
615};
616
617/* If a Time Event can be fragmented, this is the max number of fragments */
618#define TE_V1_FRAG_MAX_MSK 0x0fffffff
619/* Repeat the time event endlessly (until removed) */
620#define TE_V1_REPEAT_ENDLESS 0xffffffff
621/* If a Time Event has bounded repetitions, this is the maximal value */
622#define TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff
623
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624/* Time Event dependencies: none, on another TE, or in a specific time */
625enum {
f8f03c3e
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626 TE_V1_INDEPENDENT = 0,
627 TE_V1_DEP_OTHER = BIT(0),
628 TE_V1_DEP_TSF = BIT(1),
629 TE_V1_EVENT_SOCIOPATHIC = BIT(2),
8ca151b5 630}; /* MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */
f8f03c3e 631
1da80e80 632/*
f8f03c3e
EL
633 * @TE_V1_NOTIF_NONE: no notifications
634 * @TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start
635 * @TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end
636 * @TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use
637 * @TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use.
638 * @TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start
639 * @TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end
640 * @TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use.
641 * @TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use.
642 *
1da80e80
IP
643 * Supported Time event notifications configuration.
644 * A notification (both event and fragment) includes a status indicating weather
645 * the FW was able to schedule the event or not. For fragment start/end
646 * notification the status is always success. There is no start/end fragment
647 * notification for monolithic events.
1da80e80 648 */
8ca151b5 649enum {
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650 TE_V1_NOTIF_NONE = 0,
651 TE_V1_NOTIF_HOST_EVENT_START = BIT(0),
652 TE_V1_NOTIF_HOST_EVENT_END = BIT(1),
653 TE_V1_NOTIF_INTERNAL_EVENT_START = BIT(2),
654 TE_V1_NOTIF_INTERNAL_EVENT_END = BIT(3),
655 TE_V1_NOTIF_HOST_FRAG_START = BIT(4),
656 TE_V1_NOTIF_HOST_FRAG_END = BIT(5),
657 TE_V1_NOTIF_INTERNAL_FRAG_START = BIT(6),
658 TE_V1_NOTIF_INTERNAL_FRAG_END = BIT(7),
1da80e80 659}; /* MAC_EVENT_ACTION_API_E_VER_2 */
8ca151b5 660
a373f67c 661/* Time event - defines for command API */
f8f03c3e 662
8ca151b5 663/*
f8f03c3e
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664 * @TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed.
665 * @TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only
8ca151b5 666 * the first fragment is scheduled.
f8f03c3e 667 * @TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only
8ca151b5 668 * the first 2 fragments are scheduled.
f8f03c3e
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669 * @TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
670 * number of fragments are valid.
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671 *
672 * Other than the constant defined above, specifying a fragmentation value 'x'
673 * means that the event can be fragmented but only the first 'x' will be
674 * scheduled.
675 */
676enum {
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677 TE_V2_FRAG_NONE = 0,
678 TE_V2_FRAG_SINGLE = 1,
679 TE_V2_FRAG_DUAL = 2,
680 TE_V2_FRAG_MAX = 0xfe,
681 TE_V2_FRAG_ENDLESS = 0xff
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682};
683
684/* Repeat the time event endlessly (until removed) */
f8f03c3e 685#define TE_V2_REPEAT_ENDLESS 0xff
8ca151b5 686/* If a Time Event has bounded repetitions, this is the maximal value */
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EL
687#define TE_V2_REPEAT_MAX 0xfe
688
689#define TE_V2_PLACEMENT_POS 12
690#define TE_V2_ABSENCE_POS 15
691
a373f67c 692/* Time event policy values
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693 * A notification (both event and fragment) includes a status indicating weather
694 * the FW was able to schedule the event or not. For fragment start/end
695 * notification the status is always success. There is no start/end fragment
696 * notification for monolithic events.
697 *
698 * @TE_V2_DEFAULT_POLICY: independent, social, present, unoticable
699 * @TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start
700 * @TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end
701 * @TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use
702 * @TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use.
703 * @TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start
704 * @TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end
705 * @TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use.
706 * @TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use.
707 * @TE_V2_DEP_OTHER: depends on another time event
708 * @TE_V2_DEP_TSF: depends on a specific time
709 * @TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC
710 * @TE_V2_ABSENCE: are we present or absent during the Time Event.
711 */
712enum {
713 TE_V2_DEFAULT_POLICY = 0x0,
714
715 /* notifications (event start/stop, fragment start/stop) */
716 TE_V2_NOTIF_HOST_EVENT_START = BIT(0),
717 TE_V2_NOTIF_HOST_EVENT_END = BIT(1),
718 TE_V2_NOTIF_INTERNAL_EVENT_START = BIT(2),
719 TE_V2_NOTIF_INTERNAL_EVENT_END = BIT(3),
720
721 TE_V2_NOTIF_HOST_FRAG_START = BIT(4),
722 TE_V2_NOTIF_HOST_FRAG_END = BIT(5),
723 TE_V2_NOTIF_INTERNAL_FRAG_START = BIT(6),
724 TE_V2_NOTIF_INTERNAL_FRAG_END = BIT(7),
1f6bf078 725 T2_V2_START_IMMEDIATELY = BIT(11),
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726
727 TE_V2_NOTIF_MSK = 0xff,
728
729 /* placement characteristics */
730 TE_V2_DEP_OTHER = BIT(TE_V2_PLACEMENT_POS),
731 TE_V2_DEP_TSF = BIT(TE_V2_PLACEMENT_POS + 1),
732 TE_V2_EVENT_SOCIOPATHIC = BIT(TE_V2_PLACEMENT_POS + 2),
733
734 /* are we present or absent during the Time Event. */
735 TE_V2_ABSENCE = BIT(TE_V2_ABSENCE_POS),
736};
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737
738/**
a373f67c 739 * struct iwl_time_event_cmd_api - configuring Time Events
f8f03c3e
EL
740 * with struct MAC_TIME_EVENT_DATA_API_S_VER_2 (see also
741 * with version 1. determined by IWL_UCODE_TLV_FLAGS)
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742 * ( TIME_EVENT_CMD = 0x29 )
743 * @id_and_color: ID and color of the relevant MAC
744 * @action: action to perform, one of FW_CTXT_ACTION_*
745 * @id: this field has two meanings, depending on the action:
746 * If the action is ADD, then it means the type of event to add.
747 * For all other actions it is the unique event ID assigned when the
748 * event was added by the FW.
749 * @apply_time: When to start the Time Event (in GP2)
750 * @max_delay: maximum delay to event's start (apply time), in TU
751 * @depends_on: the unique ID of the event we depend on (if any)
752 * @interval: interval between repetitions, in TU
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753 * @duration: duration of event in TU
754 * @repeat: how many repetitions to do, can be TE_REPEAT_ENDLESS
8ca151b5 755 * @max_frags: maximal number of fragments the Time Event can be divided to
f8f03c3e
EL
756 * @policy: defines whether uCode shall notify the host or other uCode modules
757 * on event and/or fragment start and/or end
758 * using one of TE_INDEPENDENT, TE_DEP_OTHER, TE_DEP_TSF
759 * TE_EVENT_SOCIOPATHIC
760 * using TE_ABSENCE and using TE_NOTIF_*
8ca151b5 761 */
a373f67c 762struct iwl_time_event_cmd {
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763 /* COMMON_INDEX_HDR_API_S_VER_1 */
764 __le32 id_and_color;
765 __le32 action;
766 __le32 id;
f8f03c3e 767 /* MAC_TIME_EVENT_DATA_API_S_VER_2 */
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768 __le32 apply_time;
769 __le32 max_delay;
8ca151b5 770 __le32 depends_on;
8ca151b5 771 __le32 interval;
8ca151b5 772 __le32 duration;
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773 u8 repeat;
774 u8 max_frags;
775 __le16 policy;
776} __packed; /* MAC_TIME_EVENT_CMD_API_S_VER_2 */
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777
778/**
779 * struct iwl_time_event_resp - response structure to iwl_time_event_cmd
780 * @status: bit 0 indicates success, all others specify errors
781 * @id: the Time Event type
782 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE
783 * @id_and_color: ID and color of the relevant MAC
784 */
785struct iwl_time_event_resp {
786 __le32 status;
787 __le32 id;
788 __le32 unique_id;
789 __le32 id_and_color;
790} __packed; /* MAC_TIME_EVENT_RSP_API_S_VER_1 */
791
792/**
793 * struct iwl_time_event_notif - notifications of time event start/stop
794 * ( TIME_EVENT_NOTIFICATION = 0x2a )
795 * @timestamp: action timestamp in GP2
796 * @session_id: session's unique id
797 * @unique_id: unique id of the Time Event itself
798 * @id_and_color: ID and color of the relevant MAC
799 * @action: one of TE_NOTIF_START or TE_NOTIF_END
800 * @status: true if scheduled, false otherwise (not executed)
801 */
802struct iwl_time_event_notif {
803 __le32 timestamp;
804 __le32 session_id;
805 __le32 unique_id;
806 __le32 id_and_color;
807 __le32 action;
808 __le32 status;
809} __packed; /* MAC_TIME_EVENT_NTFY_API_S_VER_1 */
810
811
812/* Bindings and Time Quota */
813
814/**
815 * struct iwl_binding_cmd - configuring bindings
816 * ( BINDING_CONTEXT_CMD = 0x2b )
817 * @id_and_color: ID and color of the relevant Binding
818 * @action: action to perform, one of FW_CTXT_ACTION_*
819 * @macs: array of MAC id and colors which belong to the binding
820 * @phy: PHY id and color which belongs to the binding
821 */
822struct iwl_binding_cmd {
823 /* COMMON_INDEX_HDR_API_S_VER_1 */
824 __le32 id_and_color;
825 __le32 action;
826 /* BINDING_DATA_API_S_VER_1 */
827 __le32 macs[MAX_MACS_IN_BINDING];
828 __le32 phy;
829} __packed; /* BINDING_CMD_API_S_VER_1 */
830
35adfd6e
IP
831/* The maximal number of fragments in the FW's schedule session */
832#define IWL_MVM_MAX_QUOTA 128
833
8ca151b5
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834/**
835 * struct iwl_time_quota_data - configuration of time quota per binding
836 * @id_and_color: ID and color of the relevant Binding
837 * @quota: absolute time quota in TU. The scheduler will try to divide the
838 * remainig quota (after Time Events) according to this quota.
839 * @max_duration: max uninterrupted context duration in TU
840 */
841struct iwl_time_quota_data {
842 __le32 id_and_color;
843 __le32 quota;
844 __le32 max_duration;
845} __packed; /* TIME_QUOTA_DATA_API_S_VER_1 */
846
847/**
848 * struct iwl_time_quota_cmd - configuration of time quota between bindings
849 * ( TIME_QUOTA_CMD = 0x2c )
850 * @quotas: allocations per binding
851 */
852struct iwl_time_quota_cmd {
853 struct iwl_time_quota_data quotas[MAX_BINDINGS];
854} __packed; /* TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */
855
856
857/* PHY context */
858
859/* Supported bands */
860#define PHY_BAND_5 (0)
861#define PHY_BAND_24 (1)
862
863/* Supported channel width, vary if there is VHT support */
864#define PHY_VHT_CHANNEL_MODE20 (0x0)
865#define PHY_VHT_CHANNEL_MODE40 (0x1)
866#define PHY_VHT_CHANNEL_MODE80 (0x2)
867#define PHY_VHT_CHANNEL_MODE160 (0x3)
868
869/*
870 * Control channel position:
871 * For legacy set bit means upper channel, otherwise lower.
872 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq
873 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0.
874 * center_freq
875 * |
876 * 40Mhz |_______|_______|
877 * 80Mhz |_______|_______|_______|_______|
878 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______|
879 * code 011 010 001 000 | 100 101 110 111
880 */
881#define PHY_VHT_CTRL_POS_1_BELOW (0x0)
882#define PHY_VHT_CTRL_POS_2_BELOW (0x1)
883#define PHY_VHT_CTRL_POS_3_BELOW (0x2)
884#define PHY_VHT_CTRL_POS_4_BELOW (0x3)
885#define PHY_VHT_CTRL_POS_1_ABOVE (0x4)
886#define PHY_VHT_CTRL_POS_2_ABOVE (0x5)
887#define PHY_VHT_CTRL_POS_3_ABOVE (0x6)
888#define PHY_VHT_CTRL_POS_4_ABOVE (0x7)
889
890/*
891 * @band: PHY_BAND_*
892 * @channel: channel number
893 * @width: PHY_[VHT|LEGACY]_CHANNEL_*
894 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_*
895 */
896struct iwl_fw_channel_info {
897 u8 band;
898 u8 channel;
899 u8 width;
900 u8 ctrl_pos;
901} __packed;
902
903#define PHY_RX_CHAIN_DRIVER_FORCE_POS (0)
904#define PHY_RX_CHAIN_DRIVER_FORCE_MSK \
905 (0x1 << PHY_RX_CHAIN_DRIVER_FORCE_POS)
906#define PHY_RX_CHAIN_VALID_POS (1)
907#define PHY_RX_CHAIN_VALID_MSK \
908 (0x7 << PHY_RX_CHAIN_VALID_POS)
909#define PHY_RX_CHAIN_FORCE_SEL_POS (4)
910#define PHY_RX_CHAIN_FORCE_SEL_MSK \
911 (0x7 << PHY_RX_CHAIN_FORCE_SEL_POS)
912#define PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
913#define PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \
914 (0x7 << PHY_RX_CHAIN_FORCE_MIMO_SEL_POS)
915#define PHY_RX_CHAIN_CNT_POS (10)
916#define PHY_RX_CHAIN_CNT_MSK \
917 (0x3 << PHY_RX_CHAIN_CNT_POS)
918#define PHY_RX_CHAIN_MIMO_CNT_POS (12)
919#define PHY_RX_CHAIN_MIMO_CNT_MSK \
920 (0x3 << PHY_RX_CHAIN_MIMO_CNT_POS)
921#define PHY_RX_CHAIN_MIMO_FORCE_POS (14)
922#define PHY_RX_CHAIN_MIMO_FORCE_MSK \
923 (0x1 << PHY_RX_CHAIN_MIMO_FORCE_POS)
924
925/* TODO: fix the value, make it depend on firmware at runtime? */
926#define NUM_PHY_CTX 3
927
928/* TODO: complete missing documentation */
929/**
930 * struct iwl_phy_context_cmd - config of the PHY context
931 * ( PHY_CONTEXT_CMD = 0x8 )
932 * @id_and_color: ID and color of the relevant Binding
933 * @action: action to perform, one of FW_CTXT_ACTION_*
934 * @apply_time: 0 means immediate apply and context switch.
935 * other value means apply new params after X usecs
936 * @tx_param_color: ???
937 * @channel_info:
938 * @txchain_info: ???
939 * @rxchain_info: ???
940 * @acquisition_data: ???
941 * @dsp_cfg_flags: set to 0
942 */
943struct iwl_phy_context_cmd {
944 /* COMMON_INDEX_HDR_API_S_VER_1 */
945 __le32 id_and_color;
946 __le32 action;
947 /* PHY_CONTEXT_DATA_API_S_VER_1 */
948 __le32 apply_time;
949 __le32 tx_param_color;
950 struct iwl_fw_channel_info ci;
951 __le32 txchain_info;
952 __le32 rxchain_info;
953 __le32 acquisition_data;
954 __le32 dsp_cfg_flags;
955} __packed; /* PHY_CONTEXT_CMD_API_VER_1 */
956
720befbf
AM
957/*
958 * Aux ROC command
959 *
960 * Command requests the firmware to create a time event for a certain duration
961 * and remain on the given channel. This is done by using the Aux framework in
962 * the FW.
963 * The command was first used for Hot Spot issues - but can be used regardless
964 * to Hot Spot.
965 *
966 * ( HOT_SPOT_CMD 0x53 )
967 *
968 * @id_and_color: ID and color of the MAC
969 * @action: action to perform, one of FW_CTXT_ACTION_*
970 * @event_unique_id: If the action FW_CTXT_ACTION_REMOVE then the
971 * event_unique_id should be the id of the time event assigned by ucode.
972 * Otherwise ignore the event_unique_id.
973 * @sta_id_and_color: station id and color, resumed during "Remain On Channel"
974 * activity.
975 * @channel_info: channel info
976 * @node_addr: Our MAC Address
977 * @reserved: reserved for alignment
978 * @apply_time: GP2 value to start (should always be the current GP2 value)
979 * @apply_time_max_delay: Maximum apply time delay value in TU. Defines max
980 * time by which start of the event is allowed to be postponed.
981 * @duration: event duration in TU To calculate event duration:
982 * timeEventDuration = min(duration, remainingQuota)
983 */
984struct iwl_hs20_roc_req {
985 /* COMMON_INDEX_HDR_API_S_VER_1 hdr */
986 __le32 id_and_color;
987 __le32 action;
988 __le32 event_unique_id;
989 __le32 sta_id_and_color;
990 struct iwl_fw_channel_info channel_info;
991 u8 node_addr[ETH_ALEN];
992 __le16 reserved;
993 __le32 apply_time;
994 __le32 apply_time_max_delay;
995 __le32 duration;
996} __packed; /* HOT_SPOT_CMD_API_S_VER_1 */
997
998/*
999 * values for AUX ROC result values
1000 */
1001enum iwl_mvm_hot_spot {
1002 HOT_SPOT_RSP_STATUS_OK,
1003 HOT_SPOT_RSP_STATUS_TOO_MANY_EVENTS,
1004 HOT_SPOT_MAX_NUM_OF_SESSIONS,
1005};
1006
1007/*
1008 * Aux ROC command response
1009 *
1010 * In response to iwl_hs20_roc_req the FW sends this command to notify the
1011 * driver the uid of the timevent.
1012 *
1013 * ( HOT_SPOT_CMD 0x53 )
1014 *
1015 * @event_unique_id: Unique ID of time event assigned by ucode
1016 * @status: Return status 0 is success, all the rest used for specific errors
1017 */
1018struct iwl_hs20_roc_res {
1019 __le32 event_unique_id;
1020 __le32 status;
1021} __packed; /* HOT_SPOT_RSP_API_S_VER_1 */
1022
8ca151b5 1023#define IWL_RX_INFO_PHY_CNT 8
a2d7b870
AA
1024#define IWL_RX_INFO_ENERGY_ANT_ABC_IDX 1
1025#define IWL_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
1026#define IWL_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
1027#define IWL_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000
1028#define IWL_RX_INFO_ENERGY_ANT_A_POS 0
1029#define IWL_RX_INFO_ENERGY_ANT_B_POS 8
1030#define IWL_RX_INFO_ENERGY_ANT_C_POS 16
1031
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JB
1032#define IWL_RX_INFO_AGC_IDX 1
1033#define IWL_RX_INFO_RSSI_AB_IDX 2
8101a7f0
EG
1034#define IWL_OFDM_AGC_A_MSK 0x0000007f
1035#define IWL_OFDM_AGC_A_POS 0
1036#define IWL_OFDM_AGC_B_MSK 0x00003f80
1037#define IWL_OFDM_AGC_B_POS 7
1038#define IWL_OFDM_AGC_CODE_MSK 0x3fe00000
1039#define IWL_OFDM_AGC_CODE_POS 20
8ca151b5 1040#define IWL_OFDM_RSSI_INBAND_A_MSK 0x00ff
8ca151b5 1041#define IWL_OFDM_RSSI_A_POS 0
8101a7f0
EG
1042#define IWL_OFDM_RSSI_ALLBAND_A_MSK 0xff00
1043#define IWL_OFDM_RSSI_ALLBAND_A_POS 8
8ca151b5 1044#define IWL_OFDM_RSSI_INBAND_B_MSK 0xff0000
8ca151b5 1045#define IWL_OFDM_RSSI_B_POS 16
8101a7f0
EG
1046#define IWL_OFDM_RSSI_ALLBAND_B_MSK 0xff000000
1047#define IWL_OFDM_RSSI_ALLBAND_B_POS 24
8ca151b5
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1048
1049/**
1050 * struct iwl_rx_phy_info - phy info
1051 * (REPLY_RX_PHY_CMD = 0xc0)
1052 * @non_cfg_phy_cnt: non configurable DSP phy data byte count
1053 * @cfg_phy_cnt: configurable DSP phy data byte count
1054 * @stat_id: configurable DSP phy data set ID
1055 * @reserved1:
1056 * @system_timestamp: GP2 at on air rise
1057 * @timestamp: TSF at on air rise
1058 * @beacon_time_stamp: beacon at on-air rise
1059 * @phy_flags: general phy flags: band, modulation, ...
1060 * @channel: channel number
1061 * @non_cfg_phy_buf: for various implementations of non_cfg_phy
1062 * @rate_n_flags: RATE_MCS_*
1063 * @byte_count: frame's byte-count
1064 * @frame_time: frame's time on the air, based on byte count and frame rate
1065 * calculation
6bfcb7e8 1066 * @mac_active_msk: what MACs were active when the frame was received
8ca151b5
JB
1067 *
1068 * Before each Rx, the device sends this data. It contains PHY information
1069 * about the reception of the packet.
1070 */
1071struct iwl_rx_phy_info {
1072 u8 non_cfg_phy_cnt;
1073 u8 cfg_phy_cnt;
1074 u8 stat_id;
1075 u8 reserved1;
1076 __le32 system_timestamp;
1077 __le64 timestamp;
1078 __le32 beacon_time_stamp;
1079 __le16 phy_flags;
1080 __le16 channel;
1081 __le32 non_cfg_phy[IWL_RX_INFO_PHY_CNT];
1082 __le32 rate_n_flags;
1083 __le32 byte_count;
6bfcb7e8 1084 __le16 mac_active_msk;
8ca151b5
JB
1085 __le16 frame_time;
1086} __packed;
1087
1088struct iwl_rx_mpdu_res_start {
1089 __le16 byte_count;
1090 __le16 reserved;
1091} __packed;
1092
1093/**
1094 * enum iwl_rx_phy_flags - to parse %iwl_rx_phy_info phy_flags
1095 * @RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band
1096 * @RX_RES_PHY_FLAGS_MOD_CCK:
1097 * @RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short
1098 * @RX_RES_PHY_FLAGS_NARROW_BAND:
1099 * @RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received
1100 * @RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU
1101 * @RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame
1102 * @RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble
1103 * @RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame
1104 */
1105enum iwl_rx_phy_flags {
1106 RX_RES_PHY_FLAGS_BAND_24 = BIT(0),
1107 RX_RES_PHY_FLAGS_MOD_CCK = BIT(1),
1108 RX_RES_PHY_FLAGS_SHORT_PREAMBLE = BIT(2),
1109 RX_RES_PHY_FLAGS_NARROW_BAND = BIT(3),
1110 RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4),
1111 RX_RES_PHY_FLAGS_ANTENNA_POS = 4,
1112 RX_RES_PHY_FLAGS_AGG = BIT(7),
1113 RX_RES_PHY_FLAGS_OFDM_HT = BIT(8),
1114 RX_RES_PHY_FLAGS_OFDM_GF = BIT(9),
1115 RX_RES_PHY_FLAGS_OFDM_VHT = BIT(10),
1116};
1117
1118/**
1119 * enum iwl_mvm_rx_status - written by fw for each Rx packet
1120 * @RX_MPDU_RES_STATUS_CRC_OK: CRC is fine
1121 * @RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow
1122 * @RX_MPDU_RES_STATUS_SRC_STA_FOUND:
1123 * @RX_MPDU_RES_STATUS_KEY_VALID:
1124 * @RX_MPDU_RES_STATUS_KEY_PARAM_OK:
1125 * @RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed
1126 * @RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked
1127 * in the driver.
1128 * @RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine
1129 * @RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or
1130 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if
1131 * %RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set.
1132 * @RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted
1133 * @RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP
1134 * @RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM
1135 * @RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP
1136 * @RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC
1137 * @RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted
1138 * @RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm
1139 * @RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted
1140 * @RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP:
1141 * @RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP:
1142 * @RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT:
1143 * @RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame
1144 * @RX_MPDU_RES_STATUS_HASH_INDEX_MSK:
1145 * @RX_MPDU_RES_STATUS_STA_ID_MSK:
1146 * @RX_MPDU_RES_STATUS_RRF_KILL:
1147 * @RX_MPDU_RES_STATUS_FILTERING_MSK:
1148 * @RX_MPDU_RES_STATUS2_FILTERING_MSK:
1149 */
1150enum iwl_mvm_rx_status {
1151 RX_MPDU_RES_STATUS_CRC_OK = BIT(0),
1152 RX_MPDU_RES_STATUS_OVERRUN_OK = BIT(1),
1153 RX_MPDU_RES_STATUS_SRC_STA_FOUND = BIT(2),
1154 RX_MPDU_RES_STATUS_KEY_VALID = BIT(3),
1155 RX_MPDU_RES_STATUS_KEY_PARAM_OK = BIT(4),
1156 RX_MPDU_RES_STATUS_ICV_OK = BIT(5),
1157 RX_MPDU_RES_STATUS_MIC_OK = BIT(6),
1158 RX_MPDU_RES_STATUS_TTAK_OK = BIT(7),
1159 RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = BIT(7),
1160 RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8),
1161 RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8),
1162 RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8),
1163 RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8),
e36e5433 1164 RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8),
8ca151b5
JB
1165 RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8),
1166 RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8),
1167 RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8),
1168 RX_MPDU_RES_STATUS_DEC_DONE = BIT(11),
1169 RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = BIT(12),
1170 RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = BIT(13),
1171 RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = BIT(14),
1172 RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = BIT(15),
1173 RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000),
1174 RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000),
1175 RX_MPDU_RES_STATUS_RRF_KILL = BIT(29),
1176 RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000),
1177 RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000),
1178};
1179
1180/**
1181 * struct iwl_radio_version_notif - information on the radio version
1182 * ( RADIO_VERSION_NOTIFICATION = 0x68 )
1183 * @radio_flavor:
1184 * @radio_step:
1185 * @radio_dash:
1186 */
1187struct iwl_radio_version_notif {
1188 __le32 radio_flavor;
1189 __le32 radio_step;
1190 __le32 radio_dash;
1191} __packed; /* RADIO_VERSION_NOTOFICATION_S_VER_1 */
1192
1193enum iwl_card_state_flags {
1194 CARD_ENABLED = 0x00,
1195 HW_CARD_DISABLED = 0x01,
1196 SW_CARD_DISABLED = 0x02,
1197 CT_KILL_CARD_DISABLED = 0x04,
1198 HALT_CARD_DISABLED = 0x08,
1199 CARD_DISABLED_MSK = 0x0f,
1200 CARD_IS_RX_ON = 0x10,
1201};
1202
1203/**
1204 * struct iwl_radio_version_notif - information on the radio version
1205 * ( CARD_STATE_NOTIFICATION = 0xa1 )
1206 * @flags: %iwl_card_state_flags
1207 */
1208struct iwl_card_state_notif {
1209 __le32 flags;
1210} __packed; /* CARD_STATE_NTFY_API_S_VER_1 */
1211
d64048ed
HG
1212/**
1213 * struct iwl_missed_beacons_notif - information on missed beacons
1214 * ( MISSED_BEACONS_NOTIFICATION = 0xa2 )
1215 * @mac_id: interface ID
1216 * @consec_missed_beacons_since_last_rx: number of consecutive missed
1217 * beacons since last RX.
1218 * @consec_missed_beacons: number of consecutive missed beacons
1219 * @num_expected_beacons:
1220 * @num_recvd_beacons:
1221 */
1222struct iwl_missed_beacons_notif {
1223 __le32 mac_id;
1224 __le32 consec_missed_beacons_since_last_rx;
1225 __le32 consec_missed_beacons;
1226 __le32 num_expected_beacons;
1227 __le32 num_recvd_beacons;
1228} __packed; /* MISSED_BEACON_NTFY_API_S_VER_3 */
1229
30269c12
CRI
1230/**
1231 * struct iwl_mfuart_load_notif - mfuart image version & status
1232 * ( MFUART_LOAD_NOTIFICATION = 0xb1 )
1233 * @installed_ver: installed image version
1234 * @external_ver: external image version
1235 * @status: MFUART loading status
1236 * @duration: MFUART loading time
1237*/
1238struct iwl_mfuart_load_notif {
1239 __le32 installed_ver;
1240 __le32 external_ver;
1241 __le32 status;
1242 __le32 duration;
1243} __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/
1244
8ca151b5
JB
1245/**
1246 * struct iwl_set_calib_default_cmd - set default value for calibration.
1247 * ( SET_CALIB_DEFAULT_CMD = 0x8e )
1248 * @calib_index: the calibration to set value for
1249 * @length: of data
1250 * @data: the value to set for the calibration result
1251 */
1252struct iwl_set_calib_default_cmd {
1253 __le16 calib_index;
1254 __le16 length;
1255 u8 data[0];
1256} __packed; /* PHY_CALIB_OVERRIDE_VALUES_S */
1257
51b6b9e0 1258#define MAX_PORT_ID_NUM 2
e59647ea 1259#define MAX_MCAST_FILTERING_ADDRESSES 256
51b6b9e0
EG
1260
1261/**
1262 * struct iwl_mcast_filter_cmd - configure multicast filter.
1263 * @filter_own: Set 1 to filter out multicast packets sent by station itself
1264 * @port_id: Multicast MAC addresses array specifier. This is a strange way
1265 * to identify network interface adopted in host-device IF.
1266 * It is used by FW as index in array of addresses. This array has
1267 * MAX_PORT_ID_NUM members.
1268 * @count: Number of MAC addresses in the array
1269 * @pass_all: Set 1 to pass all multicast packets.
1270 * @bssid: current association BSSID.
1271 * @addr_list: Place holder for array of MAC addresses.
1272 * IMPORTANT: add padding if necessary to ensure DWORD alignment.
1273 */
1274struct iwl_mcast_filter_cmd {
1275 u8 filter_own;
1276 u8 port_id;
1277 u8 count;
1278 u8 pass_all;
1279 u8 bssid[6];
1280 u8 reserved[2];
1281 u8 addr_list[0];
1282} __packed; /* MCAST_FILTERING_CMD_API_S_VER_1 */
1283
c87163b9
EP
1284#define MAX_BCAST_FILTERS 8
1285#define MAX_BCAST_FILTER_ATTRS 2
1286
1287/**
1288 * enum iwl_mvm_bcast_filter_attr_offset - written by fw for each Rx packet
1289 * @BCAST_FILTER_OFFSET_PAYLOAD_START: offset is from payload start.
1290 * @BCAST_FILTER_OFFSET_IP_END: offset is from ip header end (i.e.
1291 * start of ip payload).
1292 */
1293enum iwl_mvm_bcast_filter_attr_offset {
1294 BCAST_FILTER_OFFSET_PAYLOAD_START = 0,
1295 BCAST_FILTER_OFFSET_IP_END = 1,
1296};
1297
1298/**
1299 * struct iwl_fw_bcast_filter_attr - broadcast filter attribute
1300 * @offset_type: &enum iwl_mvm_bcast_filter_attr_offset.
1301 * @offset: starting offset of this pattern.
1302 * @val: value to match - big endian (MSB is the first
1303 * byte to match from offset pos).
1304 * @mask: mask to match (big endian).
1305 */
1306struct iwl_fw_bcast_filter_attr {
1307 u8 offset_type;
1308 u8 offset;
1309 __le16 reserved1;
1310 __be32 val;
1311 __be32 mask;
1312} __packed; /* BCAST_FILTER_ATT_S_VER_1 */
1313
1314/**
1315 * enum iwl_mvm_bcast_filter_frame_type - filter frame type
1316 * @BCAST_FILTER_FRAME_TYPE_ALL: consider all frames.
1317 * @BCAST_FILTER_FRAME_TYPE_IPV4: consider only ipv4 frames
1318 */
1319enum iwl_mvm_bcast_filter_frame_type {
1320 BCAST_FILTER_FRAME_TYPE_ALL = 0,
1321 BCAST_FILTER_FRAME_TYPE_IPV4 = 1,
1322};
1323
1324/**
1325 * struct iwl_fw_bcast_filter - broadcast filter
1326 * @discard: discard frame (1) or let it pass (0).
1327 * @frame_type: &enum iwl_mvm_bcast_filter_frame_type.
1328 * @num_attrs: number of valid attributes in this filter.
1329 * @attrs: attributes of this filter. a filter is considered matched
1330 * only when all its attributes are matched (i.e. AND relationship)
1331 */
1332struct iwl_fw_bcast_filter {
1333 u8 discard;
1334 u8 frame_type;
1335 u8 num_attrs;
1336 u8 reserved1;
1337 struct iwl_fw_bcast_filter_attr attrs[MAX_BCAST_FILTER_ATTRS];
1338} __packed; /* BCAST_FILTER_S_VER_1 */
1339
1340/**
1341 * struct iwl_fw_bcast_mac - per-mac broadcast filtering configuration.
1342 * @default_discard: default action for this mac (discard (1) / pass (0)).
1343 * @attached_filters: bitmap of relevant filters for this mac.
1344 */
1345struct iwl_fw_bcast_mac {
1346 u8 default_discard;
1347 u8 reserved1;
1348 __le16 attached_filters;
1349} __packed; /* BCAST_MAC_CONTEXT_S_VER_1 */
1350
1351/**
1352 * struct iwl_bcast_filter_cmd - broadcast filtering configuration
1353 * @disable: enable (0) / disable (1)
1354 * @max_bcast_filters: max number of filters (MAX_BCAST_FILTERS)
1355 * @max_macs: max number of macs (NUM_MAC_INDEX_DRIVER)
1356 * @filters: broadcast filters
1357 * @macs: broadcast filtering configuration per-mac
1358 */
1359struct iwl_bcast_filter_cmd {
1360 u8 disable;
1361 u8 max_bcast_filters;
1362 u8 max_macs;
1363 u8 reserved1;
1364 struct iwl_fw_bcast_filter filters[MAX_BCAST_FILTERS];
1365 struct iwl_fw_bcast_mac macs[NUM_MAC_INDEX_DRIVER];
1366} __packed; /* BCAST_FILTERING_HCMD_API_S_VER_1 */
1367
a2d79c57
MG
1368/*
1369 * enum iwl_mvm_marker_id - maker ids
1370 *
1371 * The ids for different type of markers to insert into the usniffer logs
1372 */
1373enum iwl_mvm_marker_id {
1374 MARKER_ID_TX_FRAME_LATENCY = 1,
1375}; /* MARKER_ID_API_E_VER_1 */
1376
1377/**
1378 * struct iwl_mvm_marker - mark info into the usniffer logs
1379 *
1380 * (MARKER_CMD = 0xcb)
1381 *
1382 * Mark the UTC time stamp into the usniffer logs together with additional
1383 * metadata, so the usniffer output can be parsed.
1384 * In the command response the ucode will return the GP2 time.
1385 *
1386 * @dw_len: The amount of dwords following this byte including this byte.
1387 * @marker_id: A unique marker id (iwl_mvm_marker_id).
1388 * @reserved: reserved.
1389 * @timestamp: in milliseconds since 1970-01-01 00:00:00 UTC
1390 * @metadata: additional meta data that will be written to the unsiffer log
1391 */
1392struct iwl_mvm_marker {
1393 u8 dwLen;
1394 u8 markerId;
1395 __le16 reserved;
1396 __le64 timestamp;
1397 __le32 metadata[0];
1398} __packed; /* MARKER_API_S_VER_1 */
1399
0becb377
MG
1400/*
1401 * enum iwl_dc2dc_config_id - flag ids
1402 *
1403 * Ids of dc2dc configuration flags
1404 */
1405enum iwl_dc2dc_config_id {
1406 DCDC_LOW_POWER_MODE_MSK_SET = 0x1, /* not used */
1407 DCDC_FREQ_TUNE_SET = 0x2,
1408}; /* MARKER_ID_API_E_VER_1 */
1409
1410/**
1411 * struct iwl_dc2dc_config_cmd - configure dc2dc values
1412 *
1413 * (DC2DC_CONFIG_CMD = 0x83)
1414 *
1415 * Set/Get & configure dc2dc values.
1416 * The command always returns the current dc2dc values.
1417 *
1418 * @flags: set/get dc2dc
1419 * @enable_low_power_mode: not used.
1420 * @dc2dc_freq_tune0: frequency divider - digital domain
1421 * @dc2dc_freq_tune1: frequency divider - analog domain
1422 */
1423struct iwl_dc2dc_config_cmd {
1424 __le32 flags;
1425 __le32 enable_low_power_mode; /* not used */
1426 __le32 dc2dc_freq_tune0;
1427 __le32 dc2dc_freq_tune1;
1428} __packed; /* DC2DC_CONFIG_CMD_API_S_VER_1 */
1429
1430/**
1431 * struct iwl_dc2dc_config_resp - response for iwl_dc2dc_config_cmd
1432 *
1433 * Current dc2dc values returned by the FW.
1434 *
1435 * @dc2dc_freq_tune0: frequency divider - digital domain
1436 * @dc2dc_freq_tune1: frequency divider - analog domain
1437 */
1438struct iwl_dc2dc_config_resp {
1439 __le32 dc2dc_freq_tune0;
1440 __le32 dc2dc_freq_tune1;
1441} __packed; /* DC2DC_CONFIG_RESP_API_S_VER_1 */
1442
1f3b0ff8
LE
1443/***********************************
1444 * Smart Fifo API
1445 ***********************************/
1446/* Smart Fifo state */
1447enum iwl_sf_state {
1448 SF_LONG_DELAY_ON = 0, /* should never be called by driver */
1449 SF_FULL_ON,
1450 SF_UNINIT,
1451 SF_INIT_OFF,
1452 SF_HW_NUM_STATES
1453};
1454
1455/* Smart Fifo possible scenario */
1456enum iwl_sf_scenario {
1457 SF_SCENARIO_SINGLE_UNICAST,
1458 SF_SCENARIO_AGG_UNICAST,
1459 SF_SCENARIO_MULTICAST,
1460 SF_SCENARIO_BA_RESP,
1461 SF_SCENARIO_TX_RESP,
1462 SF_NUM_SCENARIO
1463};
1464
1465#define SF_TRANSIENT_STATES_NUMBER 2 /* SF_LONG_DELAY_ON and SF_FULL_ON */
1466#define SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */
1467
1468/* smart FIFO default values */
b4c82adc 1469#define SF_W_MARK_SISO 6144
1f3b0ff8
LE
1470#define SF_W_MARK_MIMO2 8192
1471#define SF_W_MARK_MIMO3 6144
1472#define SF_W_MARK_LEGACY 4096
1473#define SF_W_MARK_SCAN 4096
1474
f4a3ee49
EH
1475/* SF Scenarios timers for default configuration (aligned to 32 uSec) */
1476#define SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */
1477#define SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
1478#define SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */
1479#define SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
1480#define SF_MCAST_IDLE_TIMER_DEF 160 /* 150 mSec */
1481#define SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
1482#define SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */
1483#define SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */
1484#define SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */
1485#define SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */
1486
1487/* SF Scenarios timers for BSS MAC configuration (aligned to 32 uSec) */
1f3b0ff8
LE
1488#define SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */
1489#define SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */
1490#define SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */
1491#define SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */
1492#define SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */
1493#define SF_MCAST_AGING_TIMER 10016 /* 10 mSec */
1494#define SF_BA_IDLE_TIMER 320 /* 300 uSec */
1495#define SF_BA_AGING_TIMER 2016 /* 2 mSec */
1496#define SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */
1497#define SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */
1498
1499#define SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */
1500
161bdb77
EH
1501#define SF_CFG_DUMMY_NOTIF_OFF BIT(16)
1502
1f3b0ff8
LE
1503/**
1504 * Smart Fifo configuration command.
86974bff 1505 * @state: smart fifo state, types listed in enum %iwl_sf_sate.
1f3b0ff8
LE
1506 * @watermark: Minimum allowed availabe free space in RXF for transient state.
1507 * @long_delay_timeouts: aging and idle timer values for each scenario
1508 * in long delay state.
1509 * @full_on_timeouts: timer values for each scenario in full on state.
1510 */
1511struct iwl_sf_cfg_cmd {
86974bff 1512 __le32 state;
1f3b0ff8
LE
1513 __le32 watermark[SF_TRANSIENT_STATES_NUMBER];
1514 __le32 long_delay_timeouts[SF_NUM_SCENARIO][SF_NUM_TIMEOUT_TYPES];
1515 __le32 full_on_timeouts[SF_NUM_SCENARIO][SF_NUM_TIMEOUT_TYPES];
1516} __packed; /* SF_CFG_API_S_VER_2 */
1517
8ba2d7a1
EH
1518/***********************************
1519 * Location Aware Regulatory (LAR) API - MCC updates
1520 ***********************************/
1521
1522/**
1523 * struct iwl_mcc_update_cmd - Request the device to update geographic
1524 * regulatory profile according to the given MCC (Mobile Country Code).
1525 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain.
1526 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the
1527 * MCC in the cmd response will be the relevant MCC in the NVM.
1528 * @mcc: given mobile country code
1529 * @source_id: the source from where we got the MCC, see iwl_mcc_source
1530 * @reserved: reserved for alignment
1531 */
1532struct iwl_mcc_update_cmd {
1533 __le16 mcc;
1534 u8 source_id;
1535 u8 reserved;
1536} __packed; /* LAR_UPDATE_MCC_CMD_API_S */
1537
1538/**
1539 * iwl_mcc_update_resp - response to MCC_UPDATE_CMD.
1540 * Contains the new channel control profile map, if changed, and the new MCC
1541 * (mobile country code).
1542 * The new MCC may be different than what was requested in MCC_UPDATE_CMD.
47c8b154 1543 * @status: see &enum iwl_mcc_update_status
8ba2d7a1
EH
1544 * @mcc: the new applied MCC
1545 * @cap: capabilities for all channels which matches the MCC
1546 * @source_id: the MCC source, see iwl_mcc_source
1547 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51
1548 * channels, depending on platform)
1549 * @channels: channel control data map, DWORD for each channel. Only the first
1550 * 16bits are used.
1551 */
1552struct iwl_mcc_update_resp {
1553 __le32 status;
1554 __le16 mcc;
1555 u8 cap;
1556 u8 source_id;
1557 __le32 n_channels;
1558 __le32 channels[0];
1559} __packed; /* LAR_UPDATE_MCC_CMD_RESP_S */
1560
1561/**
1562 * struct iwl_mcc_chub_notif - chub notifies of mcc change
1563 * (MCC_CHUB_UPDATE_CMD = 0xc9)
1564 * The Chub (Communication Hub, CommsHUB) is a HW component that connects to
1565 * the cellular and connectivity cores that gets updates of the mcc, and
1566 * notifies the ucode directly of any mcc change.
1567 * The ucode requests the driver to request the device to update geographic
1568 * regulatory profile according to the given MCC (Mobile Country Code).
1569 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain.
1570 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the
1571 * MCC in the cmd response will be the relevant MCC in the NVM.
1572 * @mcc: given mobile country code
1573 * @source_id: identity of the change originator, see iwl_mcc_source
1574 * @reserved1: reserved for alignment
1575 */
1576struct iwl_mcc_chub_notif {
1577 u16 mcc;
1578 u8 source_id;
1579 u8 reserved1;
1580} __packed; /* LAR_MCC_NOTIFY_S */
1581
1582enum iwl_mcc_update_status {
1583 MCC_RESP_NEW_CHAN_PROFILE,
1584 MCC_RESP_SAME_CHAN_PROFILE,
1585 MCC_RESP_INVALID,
1586 MCC_RESP_NVM_DISABLED,
1587 MCC_RESP_ILLEGAL,
1588 MCC_RESP_LOW_PRIORITY,
1589};
1590
1591enum iwl_mcc_source {
1592 MCC_SOURCE_OLD_FW = 0,
1593 MCC_SOURCE_ME = 1,
1594 MCC_SOURCE_BIOS = 2,
1595 MCC_SOURCE_3G_LTE_HOST = 3,
1596 MCC_SOURCE_3G_LTE_DEVICE = 4,
1597 MCC_SOURCE_WIFI = 5,
1598 MCC_SOURCE_RESERVED = 6,
1599 MCC_SOURCE_DEFAULT = 7,
1600 MCC_SOURCE_UNINITIALIZED = 8,
1601 MCC_SOURCE_GET_CURRENT = 0x10
1602};
1603
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LC
1604/* DTS measurements */
1605
1606enum iwl_dts_measurement_flags {
1607 DTS_TRIGGER_CMD_FLAGS_TEMP = BIT(0),
1608 DTS_TRIGGER_CMD_FLAGS_VOLT = BIT(1),
1609};
1610
1611/**
1612 * iwl_dts_measurement_cmd - request DTS temperature and/or voltage measurements
1613 *
1614 * @flags: indicates which measurements we want as specified in &enum
1615 * iwl_dts_measurement_flags
1616 */
1617struct iwl_dts_measurement_cmd {
1618 __le32 flags;
1619} __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_CMD_S */
1620
1621/**
1622 * iwl_dts_measurement_notif - notification received with the measurements
1623 *
1624 * @temp: the measured temperature
1625 * @voltage: the measured voltage
1626 */
1627struct iwl_dts_measurement_notif {
1628 __le32 temp;
1629 __le32 voltage;
1630} __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S */
1631
77c5d7ef
AN
1632/***********************************
1633 * TDLS API
1634 ***********************************/
1635
1636/* Type of TDLS request */
1637enum iwl_tdls_channel_switch_type {
1638 TDLS_SEND_CHAN_SW_REQ = 0,
1639 TDLS_SEND_CHAN_SW_RESP_AND_MOVE_CH,
1640 TDLS_MOVE_CH,
1641}; /* TDLS_STA_CHANNEL_SWITCH_CMD_TYPE_API_E_VER_1 */
1642
1643/**
1644 * Switch timing sub-element in a TDLS channel-switch command
1645 * @frame_timestamp: GP2 timestamp of channel-switch request/response packet
1646 * received from peer
1647 * @max_offchan_duration: What amount of microseconds out of a DTIM is given
1648 * to the TDLS off-channel communication. For instance if the DTIM is
1649 * 200TU and the TDLS peer is to be given 25% of the time, the value
1650 * given will be 50TU, or 50 * 1024 if translated into microseconds.
1651 * @switch_time: switch time the peer sent in its channel switch timing IE
1652 * @switch_timout: switch timeout the peer sent in its channel switch timing IE
1653 */
1654struct iwl_tdls_channel_switch_timing {
1655 __le32 frame_timestamp; /* GP2 time of peer packet Rx */
1656 __le32 max_offchan_duration; /* given in micro-seconds */
1657 __le32 switch_time; /* given in micro-seconds */
1658 __le32 switch_timeout; /* given in micro-seconds */
1659} __packed; /* TDLS_STA_CHANNEL_SWITCH_TIMING_DATA_API_S_VER_1 */
1660
1661#define IWL_TDLS_CH_SW_FRAME_MAX_SIZE 200
1662
1663/**
1664 * TDLS channel switch frame template
1665 *
1666 * A template representing a TDLS channel-switch request or response frame
1667 *
1668 * @switch_time_offset: offset to the channel switch timing IE in the template
1669 * @tx_cmd: Tx parameters for the frame
1670 * @data: frame data
1671 */
1672struct iwl_tdls_channel_switch_frame {
1673 __le32 switch_time_offset;
1674 struct iwl_tx_cmd tx_cmd;
1675 u8 data[IWL_TDLS_CH_SW_FRAME_MAX_SIZE];
1676} __packed; /* TDLS_STA_CHANNEL_SWITCH_FRAME_API_S_VER_1 */
1677
1678/**
1679 * TDLS channel switch command
1680 *
1681 * The command is sent to initiate a channel switch and also in response to
1682 * incoming TDLS channel-switch request/response packets from remote peers.
1683 *
1684 * @switch_type: see &enum iwl_tdls_channel_switch_type
1685 * @peer_sta_id: station id of TDLS peer
1686 * @ci: channel we switch to
1687 * @timing: timing related data for command
1688 * @frame: channel-switch request/response template, depending to switch_type
1689 */
1690struct iwl_tdls_channel_switch_cmd {
1691 u8 switch_type;
1692 __le32 peer_sta_id;
1693 struct iwl_fw_channel_info ci;
1694 struct iwl_tdls_channel_switch_timing timing;
1695 struct iwl_tdls_channel_switch_frame frame;
1696} __packed; /* TDLS_STA_CHANNEL_SWITCH_CMD_API_S_VER_1 */
1697
1698/**
1699 * TDLS channel switch start notification
1700 *
1701 * @status: non-zero on success
1702 * @offchannel_duration: duration given in microseconds
1703 * @sta_id: peer currently performing the channel-switch with
1704 */
1705struct iwl_tdls_channel_switch_notif {
1706 __le32 status;
1707 __le32 offchannel_duration;
1708 __le32 sta_id;
1709} __packed; /* TDLS_STA_CHANNEL_SWITCH_NTFY_API_S_VER_1 */
1710
307e4723
AN
1711/**
1712 * TDLS station info
1713 *
1714 * @sta_id: station id of the TDLS peer
1715 * @tx_to_peer_tid: TID reserved vs. the peer for FW based Tx
1716 * @tx_to_peer_ssn: initial SSN the FW should use for Tx on its TID vs the peer
1717 * @is_initiator: 1 if the peer is the TDLS link initiator, 0 otherwise
1718 */
1719struct iwl_tdls_sta_info {
1720 u8 sta_id;
1721 u8 tx_to_peer_tid;
1722 __le16 tx_to_peer_ssn;
1723 __le32 is_initiator;
1724} __packed; /* TDLS_STA_INFO_VER_1 */
1725
1726/**
1727 * TDLS basic config command
1728 *
1729 * @id_and_color: MAC id and color being configured
1730 * @tdls_peer_count: amount of currently connected TDLS peers
1731 * @tx_to_ap_tid: TID reverved vs. the AP for FW based Tx
1732 * @tx_to_ap_ssn: initial SSN the FW should use for Tx on its TID vs. the AP
1733 * @sta_info: per-station info. Only the first tdls_peer_count entries are set
1734 * @pti_req_data_offset: offset of network-level data for the PTI template
1735 * @pti_req_tx_cmd: Tx parameters for PTI request template
1736 * @pti_req_template: PTI request template data
1737 */
1738struct iwl_tdls_config_cmd {
1739 __le32 id_and_color; /* mac id and color */
1740 u8 tdls_peer_count;
1741 u8 tx_to_ap_tid;
1742 __le16 tx_to_ap_ssn;
1743 struct iwl_tdls_sta_info sta_info[IWL_MVM_TDLS_STA_COUNT];
1744
1745 __le32 pti_req_data_offset;
1746 struct iwl_tx_cmd pti_req_tx_cmd;
1747 u8 pti_req_template[0];
1748} __packed; /* TDLS_CONFIG_CMD_API_S_VER_1 */
1749
1750/**
1751 * TDLS per-station config information from FW
1752 *
1753 * @sta_id: station id of the TDLS peer
1754 * @tx_to_peer_last_seq: last sequence number used by FW during FW-based Tx to
1755 * the peer
1756 */
1757struct iwl_tdls_config_sta_info_res {
1758 __le16 sta_id;
1759 __le16 tx_to_peer_last_seq;
1760} __packed; /* TDLS_STA_INFO_RSP_VER_1 */
1761
1762/**
1763 * TDLS config information from FW
1764 *
1765 * @tx_to_ap_last_seq: last sequence number used by FW during FW-based Tx to AP
1766 * @sta_info: per-station TDLS config information
1767 */
1768struct iwl_tdls_config_res {
1769 __le32 tx_to_ap_last_seq;
1770 struct iwl_tdls_config_sta_info_res sta_info[IWL_MVM_TDLS_STA_COUNT];
1771} __packed; /* TDLS_CONFIG_RSP_API_S_VER_1 */
1772
04fd2c28
LK
1773#define TX_FIFO_MAX_NUM 8
1774#define RX_FIFO_MAX_NUM 2
1775
1776/**
1777 * Shared memory configuration information from the FW
1778 *
1779 * @shared_mem_addr: shared memory addr (pre 8000 HW set to 0x0 as MARBH is not
1780 * accessible)
1781 * @shared_mem_size: shared memory size
1782 * @sample_buff_addr: internal sample (mon/adc) buff addr (pre 8000 HW set to
1783 * 0x0 as accessible only via DBGM RDAT)
1784 * @sample_buff_size: internal sample buff size
1785 * @txfifo_addr: start addr of TXF0 (excluding the context table 0.5KB), (pre
1786 * 8000 HW set to 0x0 as not accessible)
1787 * @txfifo_size: size of TXF0 ... TXF7
1788 * @rxfifo_size: RXF1, RXF2 sizes. If there is no RXF2, it'll have a value of 0
1789 * @page_buff_addr: used by UMAC and performance debug (page miss analysis),
1790 * when paging is not supported this should be 0
1791 * @page_buff_size: size of %page_buff_addr
1792 */
1793struct iwl_shared_mem_cfg {
1794 __le32 shared_mem_addr;
1795 __le32 shared_mem_size;
1796 __le32 sample_buff_addr;
1797 __le32 sample_buff_size;
1798 __le32 txfifo_addr;
1799 __le32 txfifo_size[TX_FIFO_MAX_NUM];
1800 __le32 rxfifo_size[RX_FIFO_MAX_NUM];
1801 __le32 page_buff_addr;
1802 __le32 page_buff_size;
1803} __packed; /* SHARED_MEM_ALLOC_API_S_VER_1 */
1804
8ca151b5 1805#endif /* __fw_api_h__ */
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