projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
iwlwifi: mvm: rs: don't save debugfs files
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / mvm / fw-api.h
CommitLineData
8ca151b5
JB		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
51368bf7 8 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
8ca151b5
JB		 9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
410dc5aa 25 * in the file called COPYING.
8ca151b5
JB		 26 *
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
51368bf7 33 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
8ca151b5
JB		 34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
63
64#ifndef __fw_api_h__
65#define __fw_api_h__
66
67#include "fw-api-rs.h"
68#include "fw-api-tx.h"
69#include "fw-api-sta.h"
70#include "fw-api-mac.h"
71#include "fw-api-power.h"
72#include "fw-api-d3.h"
5b7ff615 73#include "fw-api-coex.h"
e820c2da 74#include "fw-api-scan.h"
8ca151b5 75
19e737c9
EL		 76/* maximal number of Tx queues in any platform */
77#define IWL_MVM_MAX_QUEUES 20
78
79/* Tx queue numbers */
8ca151b5
JB		 80enum {
81 IWL_MVM_OFFCHANNEL_QUEUE = 8,
82 IWL_MVM_CMD_QUEUE = 9,
8ca151b5
JB		 83};
84
19e737c9
EL		 85#define IWL_MVM_CMD_FIFO 7
86
8ca151b5
JB		 87#define IWL_MVM_STATION_COUNT 16
88
89/* commands */
90enum {
91 MVM_ALIVE = 0x1,
92 REPLY_ERROR = 0x2,
93
94 INIT_COMPLETE_NOTIF = 0x4,
95
96 /* PHY context commands */
97 PHY_CONTEXT_CMD = 0x8,
98 DBG_CFG = 0x9,
b9fae2d5 99 ANTENNA_COUPLING_NOTIFICATION = 0xa,
8ca151b5
JB		 100
101 /* station table */
5a258aae 102 ADD_STA_KEY = 0x17,
8ca151b5
JB		 103 ADD_STA = 0x18,
104 REMOVE_STA = 0x19,
105
106 /* TX */
107 TX_CMD = 0x1c,
108 TXPATH_FLUSH = 0x1e,
109 MGMT_MCAST_KEY = 0x1f,
110
111 /* global key */
112 WEP_KEY = 0x20,
113
114 /* MAC and Binding commands */
115 MAC_CONTEXT_CMD = 0x28,
116 TIME_EVENT_CMD = 0x29, /* both CMD and response */
117 TIME_EVENT_NOTIFICATION = 0x2a,
118 BINDING_CONTEXT_CMD = 0x2b,
119 TIME_QUOTA_CMD = 0x2c,
4ac6cb59 120 NON_QOS_TX_COUNTER_CMD = 0x2d,
8ca151b5
JB		 121
122 LQ_CMD = 0x4e,
123
124 /* Calibration */
125 TEMPERATURE_NOTIFICATION = 0x62,
126 CALIBRATION_CFG_CMD = 0x65,
127 CALIBRATION_RES_NOTIFICATION = 0x66,
128 CALIBRATION_COMPLETE_NOTIFICATION = 0x67,
129 RADIO_VERSION_NOTIFICATION = 0x68,
130
131 /* Scan offload */
132 SCAN_OFFLOAD_REQUEST_CMD = 0x51,
133 SCAN_OFFLOAD_ABORT_CMD = 0x52,
134 SCAN_OFFLOAD_COMPLETE = 0x6D,
135 SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6E,
136 SCAN_OFFLOAD_CONFIG_CMD = 0x6f,
35a000b7 137 MATCH_FOUND_NOTIFICATION = 0xd9,
8ca151b5
JB		 138
139 /* Phy */
140 PHY_CONFIGURATION_CMD = 0x6a,
141 CALIB_RES_NOTIF_PHY_DB = 0x6b,
142 /* PHY_DB_CMD = 0x6c, */
143
e811ada7 144 /* Power - legacy power table command */
8ca151b5 145 POWER_TABLE_CMD = 0x77,
175a70b7 146 PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78,
8ca151b5 147
9ee718aa
EL		 148 /* Thermal Throttling*/
149 REPLY_THERMAL_MNG_BACKOFF = 0x7e,
150
8ca151b5
JB		 151 /* Scanning */
152 SCAN_REQUEST_CMD = 0x80,
153 SCAN_ABORT_CMD = 0x81,
154 SCAN_START_NOTIFICATION = 0x82,
155 SCAN_RESULTS_NOTIFICATION = 0x83,
156 SCAN_COMPLETE_NOTIFICATION = 0x84,
157
158 /* NVM */
159 NVM_ACCESS_CMD = 0x88,
160
161 SET_CALIB_DEFAULT_CMD = 0x8e,
162
571765c8 163 BEACON_NOTIFICATION = 0x90,
8ca151b5
JB		 164 BEACON_TEMPLATE_CMD = 0x91,
165 TX_ANT_CONFIGURATION_CMD = 0x98,
166 STATISTICS_NOTIFICATION = 0x9d,
3e56eadf 167 EOSP_NOTIFICATION = 0x9e,
88f2fd73 168 REDUCE_TX_POWER_CMD = 0x9f,
8ca151b5
JB		 169
170 /* RF-KILL commands and notifications */
171 CARD_STATE_CMD = 0xa0,
172 CARD_STATE_NOTIFICATION = 0xa1,
173
d64048ed
HG		 174 MISSED_BEACONS_NOTIFICATION = 0xa2,
175
e811ada7
AB		 176 /* Power - new power table command */
177 MAC_PM_POWER_TABLE = 0xa9,
178
8ca151b5
JB		 179 REPLY_RX_PHY_CMD = 0xc0,
180 REPLY_RX_MPDU_CMD = 0xc1,
181 BA_NOTIF = 0xc5,
182
fb3ceb81
EG		 183 /* BT Coex */
184 BT_COEX_PRIO_TABLE = 0xcc,
185 BT_COEX_PROT_ENV = 0xcd,
186 BT_PROFILE_NOTIFICATION = 0xce,
430a3bba
EG		 187 BT_CONFIG = 0x9b,
188 BT_COEX_UPDATE_SW_BOOST = 0x5a,
189 BT_COEX_UPDATE_CORUN_LUT = 0x5b,
190 BT_COEX_UPDATE_REDUCED_TXP = 0x5c,
dac94da8 191 BT_COEX_CI = 0x5d,
fb3ceb81 192
1f3b0ff8 193 REPLY_SF_CFG_CMD = 0xd1,
7df15b1e
HG		 194 REPLY_BEACON_FILTERING_CMD = 0xd2,
195
8ca151b5
JB		 196 REPLY_DEBUG_CMD = 0xf0,
197 DEBUG_LOG_MSG = 0xf7,
198
c87163b9 199 BCAST_FILTER_CMD = 0xcf,
51b6b9e0
EG		 200 MCAST_FILTER_CMD = 0xd0,
201
8ca151b5
JB		 202 /* D3 commands/notifications */
203 D3_CONFIG_CMD = 0xd3,
204 PROT_OFFLOAD_CONFIG_CMD = 0xd4,
205 OFFLOADS_QUERY_CMD = 0xd5,
206 REMOTE_WAKE_CONFIG_CMD = 0xd6,
98ee7783 207 D0I3_END_CMD = 0xed,
8ca151b5
JB		 208
209 /* for WoWLAN in particular */
210 WOWLAN_PATTERNS = 0xe0,
211 WOWLAN_CONFIGURATION = 0xe1,
212 WOWLAN_TSC_RSC_PARAM = 0xe2,
213 WOWLAN_TKIP_PARAM = 0xe3,
214 WOWLAN_KEK_KCK_MATERIAL = 0xe4,
215 WOWLAN_GET_STATUSES = 0xe5,
216 WOWLAN_TX_POWER_PER_DB = 0xe6,
217
218 /* and for NetDetect */
219 NET_DETECT_CONFIG_CMD = 0x54,
220 NET_DETECT_PROFILES_QUERY_CMD = 0x56,
221 NET_DETECT_PROFILES_CMD = 0x57,
222 NET_DETECT_HOTSPOTS_CMD = 0x58,
223 NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59,
224
225 REPLY_MAX = 0xff,
226};
227
228/**
229 * struct iwl_cmd_response - generic response struct for most commands
230 * @status: status of the command asked, changes for each one
231 */
232struct iwl_cmd_response {
233 __le32 status;
234};
235
236/*
237 * struct iwl_tx_ant_cfg_cmd
238 * @valid: valid antenna configuration
239 */
240struct iwl_tx_ant_cfg_cmd {
241 __le32 valid;
242} __packed;
243
88f2fd73
MG		 244/**
245 * struct iwl_reduce_tx_power_cmd - TX power reduction command
246 * REDUCE_TX_POWER_CMD = 0x9f
247 * @flags: (reserved for future implementation)
248 * @mac_context_id: id of the mac ctx for which we are reducing TX power.
249 * @pwr_restriction: TX power restriction in dBms.
250 */
251struct iwl_reduce_tx_power_cmd {
252 u8 flags;
253 u8 mac_context_id;
254 __le16 pwr_restriction;
255} __packed; /* TX_REDUCED_POWER_API_S_VER_1 */
256
8ca151b5
JB		 257/*
258 * Calibration control struct.
259 * Sent as part of the phy configuration command.
260 * @flow_trigger: bitmap for which calibrations to perform according to
261 * flow triggers.
262 * @event_trigger: bitmap for which calibrations to perform according to
263 * event triggers.
264 */
265struct iwl_calib_ctrl {
266 __le32 flow_trigger;
267 __le32 event_trigger;
268} __packed;
269
270/* This enum defines the bitmap of various calibrations to enable in both
271 * init ucode and runtime ucode through CALIBRATION_CFG_CMD.
272 */
273enum iwl_calib_cfg {
274 IWL_CALIB_CFG_XTAL_IDX = BIT(0),
275 IWL_CALIB_CFG_TEMPERATURE_IDX = BIT(1),
276 IWL_CALIB_CFG_VOLTAGE_READ_IDX = BIT(2),
277 IWL_CALIB_CFG_PAPD_IDX = BIT(3),
278 IWL_CALIB_CFG_TX_PWR_IDX = BIT(4),
279 IWL_CALIB_CFG_DC_IDX = BIT(5),
280 IWL_CALIB_CFG_BB_FILTER_IDX = BIT(6),
281 IWL_CALIB_CFG_LO_LEAKAGE_IDX = BIT(7),
282 IWL_CALIB_CFG_TX_IQ_IDX = BIT(8),
283 IWL_CALIB_CFG_TX_IQ_SKEW_IDX = BIT(9),
284 IWL_CALIB_CFG_RX_IQ_IDX = BIT(10),
285 IWL_CALIB_CFG_RX_IQ_SKEW_IDX = BIT(11),
286 IWL_CALIB_CFG_SENSITIVITY_IDX = BIT(12),
287 IWL_CALIB_CFG_CHAIN_NOISE_IDX = BIT(13),
288 IWL_CALIB_CFG_DISCONNECTED_ANT_IDX = BIT(14),
289 IWL_CALIB_CFG_ANT_COUPLING_IDX = BIT(15),
290 IWL_CALIB_CFG_DAC_IDX = BIT(16),
291 IWL_CALIB_CFG_ABS_IDX = BIT(17),
292 IWL_CALIB_CFG_AGC_IDX = BIT(18),
293};
294
295/*
296 * Phy configuration command.
297 */
298struct iwl_phy_cfg_cmd {
299 __le32 phy_cfg;
300 struct iwl_calib_ctrl calib_control;
301} __packed;
302
303#define PHY_CFG_RADIO_TYPE (BIT(0) | BIT(1))
304#define PHY_CFG_RADIO_STEP (BIT(2) | BIT(3))
305#define PHY_CFG_RADIO_DASH (BIT(4) | BIT(5))
306#define PHY_CFG_PRODUCT_NUMBER (BIT(6) | BIT(7))
307#define PHY_CFG_TX_CHAIN_A BIT(8)
308#define PHY_CFG_TX_CHAIN_B BIT(9)
309#define PHY_CFG_TX_CHAIN_C BIT(10)
310#define PHY_CFG_RX_CHAIN_A BIT(12)
311#define PHY_CFG_RX_CHAIN_B BIT(13)
312#define PHY_CFG_RX_CHAIN_C BIT(14)
313
314
315/* Target of the NVM_ACCESS_CMD */
316enum {
317 NVM_ACCESS_TARGET_CACHE = 0,
318 NVM_ACCESS_TARGET_OTP = 1,
319 NVM_ACCESS_TARGET_EEPROM = 2,
320};
321
b9545b48 322/* Section types for NVM_ACCESS_CMD */
8ca151b5 323enum {
ae2b21b0 324 NVM_SECTION_TYPE_SW = 1,
77db0a3c 325 NVM_SECTION_TYPE_REGULATORY = 3,
ae2b21b0
EH		 326 NVM_SECTION_TYPE_CALIBRATION = 4,
327 NVM_SECTION_TYPE_PRODUCTION = 5,
77db0a3c
EH		 328 NVM_SECTION_TYPE_MAC_OVERRIDE = 11,
329 NVM_MAX_NUM_SECTIONS = 12,
8ca151b5
JB		 330};
331
332/**
333 * struct iwl_nvm_access_cmd_ver2 - Request the device to send an NVM section
334 * @op_code: 0 - read, 1 - write
335 * @target: NVM_ACCESS_TARGET_*
336 * @type: NVM_SECTION_TYPE_*
337 * @offset: offset in bytes into the section
338 * @length: in bytes, to read/write
339 * @data: if write operation, the data to write. On read its empty
340 */
b9545b48 341struct iwl_nvm_access_cmd {
8ca151b5
JB		 342 u8 op_code;
343 u8 target;
344 __le16 type;
345 __le16 offset;
346 __le16 length;
347 u8 data[];
348} __packed; /* NVM_ACCESS_CMD_API_S_VER_2 */
349
350/**
351 * struct iwl_nvm_access_resp_ver2 - response to NVM_ACCESS_CMD
352 * @offset: offset in bytes into the section
353 * @length: in bytes, either how much was written or read
354 * @type: NVM_SECTION_TYPE_*
355 * @status: 0 for success, fail otherwise
356 * @data: if read operation, the data returned. Empty on write.
357 */
b9545b48 358struct iwl_nvm_access_resp {
8ca151b5
JB		 359 __le16 offset;
360 __le16 length;
361 __le16 type;
362 __le16 status;
363 u8 data[];
364} __packed; /* NVM_ACCESS_CMD_RESP_API_S_VER_2 */
365
366/* MVM_ALIVE 0x1 */
367
368/* alive response is_valid values */
369#define ALIVE_RESP_UCODE_OK BIT(0)
370#define ALIVE_RESP_RFKILL BIT(1)
371
372/* alive response ver_type values */
373enum {
374 FW_TYPE_HW = 0,
375 FW_TYPE_PROT = 1,
376 FW_TYPE_AP = 2,
377 FW_TYPE_WOWLAN = 3,
378 FW_TYPE_TIMING = 4,
379 FW_TYPE_WIPAN = 5
380};
381
382/* alive response ver_subtype values */
383enum {
384 FW_SUBTYPE_FULL_FEATURE = 0,
385 FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */
386 FW_SUBTYPE_REDUCED = 2,
387 FW_SUBTYPE_ALIVE_ONLY = 3,
388 FW_SUBTYPE_WOWLAN = 4,
389 FW_SUBTYPE_AP_SUBTYPE = 5,
390 FW_SUBTYPE_WIPAN = 6,
391 FW_SUBTYPE_INITIALIZE = 9
392};
393
394#define IWL_ALIVE_STATUS_ERR 0xDEAD
395#define IWL_ALIVE_STATUS_OK 0xCAFE
396
397#define IWL_ALIVE_FLG_RFKILL BIT(0)
398
399struct mvm_alive_resp {
400 __le16 status;
401 __le16 flags;
402 u8 ucode_minor;
403 u8 ucode_major;
404 __le16 id;
405 u8 api_minor;
406 u8 api_major;
407 u8 ver_subtype;
408 u8 ver_type;
409 u8 mac;
410 u8 opt;
411 __le16 reserved2;
412 __le32 timestamp;
413 __le32 error_event_table_ptr; /* SRAM address for error log */
414 __le32 log_event_table_ptr; /* SRAM address for event log */
415 __le32 cpu_register_ptr;
416 __le32 dbgm_config_ptr;
417 __le32 alive_counter_ptr;
418 __le32 scd_base_ptr; /* SRAM address for SCD */
419} __packed; /* ALIVE_RES_API_S_VER_1 */
420
01a9ca51
EH		 421struct mvm_alive_resp_ver2 {
422 __le16 status;
423 __le16 flags;
424 u8 ucode_minor;
425 u8 ucode_major;
426 __le16 id;
427 u8 api_minor;
428 u8 api_major;
429 u8 ver_subtype;
430 u8 ver_type;
431 u8 mac;
432 u8 opt;
433 __le16 reserved2;
434 __le32 timestamp;
435 __le32 error_event_table_ptr; /* SRAM address for error log */
436 __le32 log_event_table_ptr; /* SRAM address for LMAC event log */
437 __le32 cpu_register_ptr;
438 __le32 dbgm_config_ptr;
439 __le32 alive_counter_ptr;
440 __le32 scd_base_ptr; /* SRAM address for SCD */
441 __le32 st_fwrd_addr; /* pointer to Store and forward */
442 __le32 st_fwrd_size;
443 u8 umac_minor; /* UMAC version: minor */
444 u8 umac_major; /* UMAC version: major */
445 __le16 umac_id; /* UMAC version: id */
446 __le32 error_info_addr; /* SRAM address for UMAC error log */
447 __le32 dbg_print_buff_addr;
448} __packed; /* ALIVE_RES_API_S_VER_2 */
449
8ca151b5
JB		 450/* Error response/notification */
451enum {
452 FW_ERR_UNKNOWN_CMD = 0x0,
453 FW_ERR_INVALID_CMD_PARAM = 0x1,
454 FW_ERR_SERVICE = 0x2,
455 FW_ERR_ARC_MEMORY = 0x3,
456 FW_ERR_ARC_CODE = 0x4,
457 FW_ERR_WATCH_DOG = 0x5,
458 FW_ERR_WEP_GRP_KEY_INDX = 0x10,
459 FW_ERR_WEP_KEY_SIZE = 0x11,
460 FW_ERR_OBSOLETE_FUNC = 0x12,
461 FW_ERR_UNEXPECTED = 0xFE,
462 FW_ERR_FATAL = 0xFF
463};
464
465/**
466 * struct iwl_error_resp - FW error indication
467 * ( REPLY_ERROR = 0x2 )
468 * @error_type: one of FW_ERR_*
469 * @cmd_id: the command ID for which the error occured
470 * @bad_cmd_seq_num: sequence number of the erroneous command
471 * @error_service: which service created the error, applicable only if
472 * error_type = 2, otherwise 0
473 * @timestamp: TSF in usecs.
474 */
475struct iwl_error_resp {
476 __le32 error_type;
477 u8 cmd_id;
478 u8 reserved1;
479 __le16 bad_cmd_seq_num;
480 __le32 error_service;
481 __le64 timestamp;
482} __packed;
483
484
485/* Common PHY, MAC and Bindings definitions */
486
487#define MAX_MACS_IN_BINDING (3)
488#define MAX_BINDINGS (4)
489#define AUX_BINDING_INDEX (3)
490#define MAX_PHYS (4)
491
492/* Used to extract ID and color from the context dword */
493#define FW_CTXT_ID_POS (0)
494#define FW_CTXT_ID_MSK (0xff << FW_CTXT_ID_POS)
495#define FW_CTXT_COLOR_POS (8)
496#define FW_CTXT_COLOR_MSK (0xff << FW_CTXT_COLOR_POS)
497#define FW_CTXT_INVALID (0xffffffff)
498
499#define FW_CMD_ID_AND_COLOR(_id, _color) ((_id << FW_CTXT_ID_POS) |\
500 (_color << FW_CTXT_COLOR_POS))
501
502/* Possible actions on PHYs, MACs and Bindings */
503enum {
504 FW_CTXT_ACTION_STUB = 0,
505 FW_CTXT_ACTION_ADD,
506 FW_CTXT_ACTION_MODIFY,
507 FW_CTXT_ACTION_REMOVE,
508 FW_CTXT_ACTION_NUM
509}; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */
510
511/* Time Events */
512
513/* Time Event types, according to MAC type */
514enum iwl_time_event_type {
515 /* BSS Station Events */
516 TE_BSS_STA_AGGRESSIVE_ASSOC,
517 TE_BSS_STA_ASSOC,
518 TE_BSS_EAP_DHCP_PROT,
519 TE_BSS_QUIET_PERIOD,
520
521 /* P2P Device Events */
522 TE_P2P_DEVICE_DISCOVERABLE,
523 TE_P2P_DEVICE_LISTEN,
524 TE_P2P_DEVICE_ACTION_SCAN,
525 TE_P2P_DEVICE_FULL_SCAN,
526
527 /* P2P Client Events */
528 TE_P2P_CLIENT_AGGRESSIVE_ASSOC,
529 TE_P2P_CLIENT_ASSOC,
530 TE_P2P_CLIENT_QUIET_PERIOD,
531
532 /* P2P GO Events */
533 TE_P2P_GO_ASSOC_PROT,
534 TE_P2P_GO_REPETITIVE_NOA,
535 TE_P2P_GO_CT_WINDOW,
536
537 /* WiDi Sync Events */
538 TE_WIDI_TX_SYNC,
539
540 TE_MAX
541}; /* MAC_EVENT_TYPE_API_E_VER_1 */
542
f8f03c3e
EL		 543
544
545/* Time event - defines for command API v1 */
546
547/*
548 * @TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed.
549 * @TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only
550 * the first fragment is scheduled.
551 * @TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only
552 * the first 2 fragments are scheduled.
553 * @TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
554 * number of fragments are valid.
555 *
556 * Other than the constant defined above, specifying a fragmentation value 'x'
557 * means that the event can be fragmented but only the first 'x' will be
558 * scheduled.
559 */
560enum {
561 TE_V1_FRAG_NONE = 0,
562 TE_V1_FRAG_SINGLE = 1,
563 TE_V1_FRAG_DUAL = 2,
564 TE_V1_FRAG_ENDLESS = 0xffffffff
565};
566
567/* If a Time Event can be fragmented, this is the max number of fragments */
568#define TE_V1_FRAG_MAX_MSK 0x0fffffff
569/* Repeat the time event endlessly (until removed) */
570#define TE_V1_REPEAT_ENDLESS 0xffffffff
571/* If a Time Event has bounded repetitions, this is the maximal value */
572#define TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff
573
8ca151b5
JB		 574/* Time Event dependencies: none, on another TE, or in a specific time */
575enum {
f8f03c3e
EL		 576 TE_V1_INDEPENDENT = 0,
577 TE_V1_DEP_OTHER = BIT(0),
578 TE_V1_DEP_TSF = BIT(1),
579 TE_V1_EVENT_SOCIOPATHIC = BIT(2),
8ca151b5 580}; /* MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */
f8f03c3e 581
1da80e80 582/*
f8f03c3e
EL		 583 * @TE_V1_NOTIF_NONE: no notifications
584 * @TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start
585 * @TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end
586 * @TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use
587 * @TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use.
588 * @TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start
589 * @TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end
590 * @TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use.
591 * @TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use.
592 *
1da80e80
IP		 593 * Supported Time event notifications configuration.
594 * A notification (both event and fragment) includes a status indicating weather
595 * the FW was able to schedule the event or not. For fragment start/end
596 * notification the status is always success. There is no start/end fragment
597 * notification for monolithic events.
1da80e80 598 */
8ca151b5 599enum {
f8f03c3e
EL		 600 TE_V1_NOTIF_NONE = 0,
601 TE_V1_NOTIF_HOST_EVENT_START = BIT(0),
602 TE_V1_NOTIF_HOST_EVENT_END = BIT(1),
603 TE_V1_NOTIF_INTERNAL_EVENT_START = BIT(2),
604 TE_V1_NOTIF_INTERNAL_EVENT_END = BIT(3),
605 TE_V1_NOTIF_HOST_FRAG_START = BIT(4),
606 TE_V1_NOTIF_HOST_FRAG_END = BIT(5),
607 TE_V1_NOTIF_INTERNAL_FRAG_START = BIT(6),
608 TE_V1_NOTIF_INTERNAL_FRAG_END = BIT(7),
1da80e80 609}; /* MAC_EVENT_ACTION_API_E_VER_2 */
8ca151b5 610
a373f67c 611/* Time event - defines for command API */
f8f03c3e 612
8ca151b5 613/*
f8f03c3e
EL		 614 * @TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed.
615 * @TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only
8ca151b5 616 * the first fragment is scheduled.
f8f03c3e 617 * @TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only
8ca151b5 618 * the first 2 fragments are scheduled.
f8f03c3e
EL		 619 * @TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
620 * number of fragments are valid.
8ca151b5
JB		 621 *
622 * Other than the constant defined above, specifying a fragmentation value 'x'
623 * means that the event can be fragmented but only the first 'x' will be
624 * scheduled.
625 */
626enum {
f8f03c3e
EL		 627 TE_V2_FRAG_NONE = 0,
628 TE_V2_FRAG_SINGLE = 1,
629 TE_V2_FRAG_DUAL = 2,
630 TE_V2_FRAG_MAX = 0xfe,
631 TE_V2_FRAG_ENDLESS = 0xff
8ca151b5
JB		 632};
633
634/* Repeat the time event endlessly (until removed) */
f8f03c3e 635#define TE_V2_REPEAT_ENDLESS 0xff
8ca151b5 636/* If a Time Event has bounded repetitions, this is the maximal value */
f8f03c3e
EL		 637#define TE_V2_REPEAT_MAX 0xfe
638
639#define TE_V2_PLACEMENT_POS 12
640#define TE_V2_ABSENCE_POS 15
641
a373f67c 642/* Time event policy values
f8f03c3e
EL		 643 * A notification (both event and fragment) includes a status indicating weather
644 * the FW was able to schedule the event or not. For fragment start/end
645 * notification the status is always success. There is no start/end fragment
646 * notification for monolithic events.
647 *
648 * @TE_V2_DEFAULT_POLICY: independent, social, present, unoticable
649 * @TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start
650 * @TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end
651 * @TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use
652 * @TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use.
653 * @TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start
654 * @TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end
655 * @TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use.
656 * @TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use.
657 * @TE_V2_DEP_OTHER: depends on another time event
658 * @TE_V2_DEP_TSF: depends on a specific time
659 * @TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC
660 * @TE_V2_ABSENCE: are we present or absent during the Time Event.
661 */
662enum {
663 TE_V2_DEFAULT_POLICY = 0x0,
664
665 /* notifications (event start/stop, fragment start/stop) */
666 TE_V2_NOTIF_HOST_EVENT_START = BIT(0),
667 TE_V2_NOTIF_HOST_EVENT_END = BIT(1),
668 TE_V2_NOTIF_INTERNAL_EVENT_START = BIT(2),
669 TE_V2_NOTIF_INTERNAL_EVENT_END = BIT(3),
670
671 TE_V2_NOTIF_HOST_FRAG_START = BIT(4),
672 TE_V2_NOTIF_HOST_FRAG_END = BIT(5),
673 TE_V2_NOTIF_INTERNAL_FRAG_START = BIT(6),
674 TE_V2_NOTIF_INTERNAL_FRAG_END = BIT(7),
1f6bf078 675 T2_V2_START_IMMEDIATELY = BIT(11),
f8f03c3e
EL		 676
677 TE_V2_NOTIF_MSK = 0xff,
678
679 /* placement characteristics */
680 TE_V2_DEP_OTHER = BIT(TE_V2_PLACEMENT_POS),
681 TE_V2_DEP_TSF = BIT(TE_V2_PLACEMENT_POS + 1),
682 TE_V2_EVENT_SOCIOPATHIC = BIT(TE_V2_PLACEMENT_POS + 2),
683
684 /* are we present or absent during the Time Event. */
685 TE_V2_ABSENCE = BIT(TE_V2_ABSENCE_POS),
686};
8ca151b5
JB		 687
688/**
a373f67c 689 * struct iwl_time_event_cmd_api - configuring Time Events
f8f03c3e
EL		 690 * with struct MAC_TIME_EVENT_DATA_API_S_VER_2 (see also
691 * with version 1. determined by IWL_UCODE_TLV_FLAGS)
8ca151b5
JB		 692 * ( TIME_EVENT_CMD = 0x29 )
693 * @id_and_color: ID and color of the relevant MAC
694 * @action: action to perform, one of FW_CTXT_ACTION_*
695 * @id: this field has two meanings, depending on the action:
696 * If the action is ADD, then it means the type of event to add.
697 * For all other actions it is the unique event ID assigned when the
698 * event was added by the FW.
699 * @apply_time: When to start the Time Event (in GP2)
700 * @max_delay: maximum delay to event's start (apply time), in TU
701 * @depends_on: the unique ID of the event we depend on (if any)
702 * @interval: interval between repetitions, in TU
8ca151b5
JB		 703 * @duration: duration of event in TU
704 * @repeat: how many repetitions to do, can be TE_REPEAT_ENDLESS
8ca151b5 705 * @max_frags: maximal number of fragments the Time Event can be divided to
f8f03c3e
EL		 706 * @policy: defines whether uCode shall notify the host or other uCode modules
707 * on event and/or fragment start and/or end
708 * using one of TE_INDEPENDENT, TE_DEP_OTHER, TE_DEP_TSF
709 * TE_EVENT_SOCIOPATHIC
710 * using TE_ABSENCE and using TE_NOTIF_*
8ca151b5 711 */
a373f67c 712struct iwl_time_event_cmd {
8ca151b5
JB		 713 /* COMMON_INDEX_HDR_API_S_VER_1 */
714 __le32 id_and_color;
715 __le32 action;
716 __le32 id;
f8f03c3e 717 /* MAC_TIME_EVENT_DATA_API_S_VER_2 */
8ca151b5
JB		 718 __le32 apply_time;
719 __le32 max_delay;
8ca151b5 720 __le32 depends_on;
8ca151b5 721 __le32 interval;
8ca151b5 722 __le32 duration;
f8f03c3e
EL		 723 u8 repeat;
724 u8 max_frags;
725 __le16 policy;
726} __packed; /* MAC_TIME_EVENT_CMD_API_S_VER_2 */
8ca151b5
JB		 727
728/**
729 * struct iwl_time_event_resp - response structure to iwl_time_event_cmd
730 * @status: bit 0 indicates success, all others specify errors
731 * @id: the Time Event type
732 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE
733 * @id_and_color: ID and color of the relevant MAC
734 */
735struct iwl_time_event_resp {
736 __le32 status;
737 __le32 id;
738 __le32 unique_id;
739 __le32 id_and_color;
740} __packed; /* MAC_TIME_EVENT_RSP_API_S_VER_1 */
741
742/**
743 * struct iwl_time_event_notif - notifications of time event start/stop
744 * ( TIME_EVENT_NOTIFICATION = 0x2a )
745 * @timestamp: action timestamp in GP2
746 * @session_id: session's unique id
747 * @unique_id: unique id of the Time Event itself
748 * @id_and_color: ID and color of the relevant MAC
749 * @action: one of TE_NOTIF_START or TE_NOTIF_END
750 * @status: true if scheduled, false otherwise (not executed)
751 */
752struct iwl_time_event_notif {
753 __le32 timestamp;
754 __le32 session_id;
755 __le32 unique_id;
756 __le32 id_and_color;
757 __le32 action;
758 __le32 status;
759} __packed; /* MAC_TIME_EVENT_NTFY_API_S_VER_1 */
760
761
762/* Bindings and Time Quota */
763
764/**
765 * struct iwl_binding_cmd - configuring bindings
766 * ( BINDING_CONTEXT_CMD = 0x2b )
767 * @id_and_color: ID and color of the relevant Binding
768 * @action: action to perform, one of FW_CTXT_ACTION_*
769 * @macs: array of MAC id and colors which belong to the binding
770 * @phy: PHY id and color which belongs to the binding
771 */
772struct iwl_binding_cmd {
773 /* COMMON_INDEX_HDR_API_S_VER_1 */
774 __le32 id_and_color;
775 __le32 action;
776 /* BINDING_DATA_API_S_VER_1 */
777 __le32 macs[MAX_MACS_IN_BINDING];
778 __le32 phy;
779} __packed; /* BINDING_CMD_API_S_VER_1 */
780
35adfd6e
IP		 781/* The maximal number of fragments in the FW's schedule session */
782#define IWL_MVM_MAX_QUOTA 128
783
8ca151b5
JB		 784/**
785 * struct iwl_time_quota_data - configuration of time quota per binding
786 * @id_and_color: ID and color of the relevant Binding
787 * @quota: absolute time quota in TU. The scheduler will try to divide the
788 * remainig quota (after Time Events) according to this quota.
789 * @max_duration: max uninterrupted context duration in TU
790 */
791struct iwl_time_quota_data {
792 __le32 id_and_color;
793 __le32 quota;
794 __le32 max_duration;
795} __packed; /* TIME_QUOTA_DATA_API_S_VER_1 */
796
797/**
798 * struct iwl_time_quota_cmd - configuration of time quota between bindings
799 * ( TIME_QUOTA_CMD = 0x2c )
800 * @quotas: allocations per binding
801 */
802struct iwl_time_quota_cmd {
803 struct iwl_time_quota_data quotas[MAX_BINDINGS];
804} __packed; /* TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */
805
806
807/* PHY context */
808
809/* Supported bands */
810#define PHY_BAND_5 (0)
811#define PHY_BAND_24 (1)
812
813/* Supported channel width, vary if there is VHT support */
814#define PHY_VHT_CHANNEL_MODE20 (0x0)
815#define PHY_VHT_CHANNEL_MODE40 (0x1)
816#define PHY_VHT_CHANNEL_MODE80 (0x2)
817#define PHY_VHT_CHANNEL_MODE160 (0x3)
818
819/*
820 * Control channel position:
821 * For legacy set bit means upper channel, otherwise lower.
822 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq
823 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0.
824 * center_freq
825 * |
826 * 40Mhz |_______|_______|
827 * 80Mhz |_______|_______|_______|_______|
828 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______|
829 * code 011 010 001 000 | 100 101 110 111
830 */
831#define PHY_VHT_CTRL_POS_1_BELOW (0x0)
832#define PHY_VHT_CTRL_POS_2_BELOW (0x1)
833#define PHY_VHT_CTRL_POS_3_BELOW (0x2)
834#define PHY_VHT_CTRL_POS_4_BELOW (0x3)
835#define PHY_VHT_CTRL_POS_1_ABOVE (0x4)
836#define PHY_VHT_CTRL_POS_2_ABOVE (0x5)
837#define PHY_VHT_CTRL_POS_3_ABOVE (0x6)
838#define PHY_VHT_CTRL_POS_4_ABOVE (0x7)
839
840/*
841 * @band: PHY_BAND_*
842 * @channel: channel number
843 * @width: PHY_[VHT|LEGACY]_CHANNEL_*
844 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_*
845 */
846struct iwl_fw_channel_info {
847 u8 band;
848 u8 channel;
849 u8 width;
850 u8 ctrl_pos;
851} __packed;
852
853#define PHY_RX_CHAIN_DRIVER_FORCE_POS (0)
854#define PHY_RX_CHAIN_DRIVER_FORCE_MSK \
855 (0x1 << PHY_RX_CHAIN_DRIVER_FORCE_POS)
856#define PHY_RX_CHAIN_VALID_POS (1)
857#define PHY_RX_CHAIN_VALID_MSK \
858 (0x7 << PHY_RX_CHAIN_VALID_POS)
859#define PHY_RX_CHAIN_FORCE_SEL_POS (4)
860#define PHY_RX_CHAIN_FORCE_SEL_MSK \
861 (0x7 << PHY_RX_CHAIN_FORCE_SEL_POS)
862#define PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
863#define PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \
864 (0x7 << PHY_RX_CHAIN_FORCE_MIMO_SEL_POS)
865#define PHY_RX_CHAIN_CNT_POS (10)
866#define PHY_RX_CHAIN_CNT_MSK \
867 (0x3 << PHY_RX_CHAIN_CNT_POS)
868#define PHY_RX_CHAIN_MIMO_CNT_POS (12)
869#define PHY_RX_CHAIN_MIMO_CNT_MSK \
870 (0x3 << PHY_RX_CHAIN_MIMO_CNT_POS)
871#define PHY_RX_CHAIN_MIMO_FORCE_POS (14)
872#define PHY_RX_CHAIN_MIMO_FORCE_MSK \
873 (0x1 << PHY_RX_CHAIN_MIMO_FORCE_POS)
874
875/* TODO: fix the value, make it depend on firmware at runtime? */
876#define NUM_PHY_CTX 3
877
878/* TODO: complete missing documentation */
879/**
880 * struct iwl_phy_context_cmd - config of the PHY context
881 * ( PHY_CONTEXT_CMD = 0x8 )
882 * @id_and_color: ID and color of the relevant Binding
883 * @action: action to perform, one of FW_CTXT_ACTION_*
884 * @apply_time: 0 means immediate apply and context switch.
885 * other value means apply new params after X usecs
886 * @tx_param_color: ???
887 * @channel_info:
888 * @txchain_info: ???
889 * @rxchain_info: ???
890 * @acquisition_data: ???
891 * @dsp_cfg_flags: set to 0
892 */
893struct iwl_phy_context_cmd {
894 /* COMMON_INDEX_HDR_API_S_VER_1 */
895 __le32 id_and_color;
896 __le32 action;
897 /* PHY_CONTEXT_DATA_API_S_VER_1 */
898 __le32 apply_time;
899 __le32 tx_param_color;
900 struct iwl_fw_channel_info ci;
901 __le32 txchain_info;
902 __le32 rxchain_info;
903 __le32 acquisition_data;
904 __le32 dsp_cfg_flags;
905} __packed; /* PHY_CONTEXT_CMD_API_VER_1 */
906
907#define IWL_RX_INFO_PHY_CNT 8
a2d7b870
AA		 908#define IWL_RX_INFO_ENERGY_ANT_ABC_IDX 1
909#define IWL_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
910#define IWL_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
911#define IWL_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000
912#define IWL_RX_INFO_ENERGY_ANT_A_POS 0
913#define IWL_RX_INFO_ENERGY_ANT_B_POS 8
914#define IWL_RX_INFO_ENERGY_ANT_C_POS 16
915
8ca151b5
JB		 916#define IWL_RX_INFO_AGC_IDX 1
917#define IWL_RX_INFO_RSSI_AB_IDX 2
8101a7f0
EG		 918#define IWL_OFDM_AGC_A_MSK 0x0000007f
919#define IWL_OFDM_AGC_A_POS 0
920#define IWL_OFDM_AGC_B_MSK 0x00003f80
921#define IWL_OFDM_AGC_B_POS 7
922#define IWL_OFDM_AGC_CODE_MSK 0x3fe00000
923#define IWL_OFDM_AGC_CODE_POS 20
8ca151b5 924#define IWL_OFDM_RSSI_INBAND_A_MSK 0x00ff
8ca151b5 925#define IWL_OFDM_RSSI_A_POS 0
8101a7f0
EG		 926#define IWL_OFDM_RSSI_ALLBAND_A_MSK 0xff00
927#define IWL_OFDM_RSSI_ALLBAND_A_POS 8
8ca151b5 928#define IWL_OFDM_RSSI_INBAND_B_MSK 0xff0000
8ca151b5 929#define IWL_OFDM_RSSI_B_POS 16
8101a7f0
EG		 930#define IWL_OFDM_RSSI_ALLBAND_B_MSK 0xff000000
931#define IWL_OFDM_RSSI_ALLBAND_B_POS 24
8ca151b5
JB		 932
933/**
934 * struct iwl_rx_phy_info - phy info
935 * (REPLY_RX_PHY_CMD = 0xc0)
936 * @non_cfg_phy_cnt: non configurable DSP phy data byte count
937 * @cfg_phy_cnt: configurable DSP phy data byte count
938 * @stat_id: configurable DSP phy data set ID
939 * @reserved1:
940 * @system_timestamp: GP2 at on air rise
941 * @timestamp: TSF at on air rise
942 * @beacon_time_stamp: beacon at on-air rise
943 * @phy_flags: general phy flags: band, modulation, ...
944 * @channel: channel number
945 * @non_cfg_phy_buf: for various implementations of non_cfg_phy
946 * @rate_n_flags: RATE_MCS_*
947 * @byte_count: frame's byte-count
948 * @frame_time: frame's time on the air, based on byte count and frame rate
949 * calculation
6bfcb7e8 950 * @mac_active_msk: what MACs were active when the frame was received
8ca151b5
JB		 951 *
952 * Before each Rx, the device sends this data. It contains PHY information
953 * about the reception of the packet.
954 */
955struct iwl_rx_phy_info {
956 u8 non_cfg_phy_cnt;
957 u8 cfg_phy_cnt;
958 u8 stat_id;
959 u8 reserved1;
960 __le32 system_timestamp;
961 __le64 timestamp;
962 __le32 beacon_time_stamp;
963 __le16 phy_flags;
964 __le16 channel;
965 __le32 non_cfg_phy[IWL_RX_INFO_PHY_CNT];
966 __le32 rate_n_flags;
967 __le32 byte_count;
6bfcb7e8 968 __le16 mac_active_msk;
8ca151b5
JB		 969 __le16 frame_time;
970} __packed;
971
972struct iwl_rx_mpdu_res_start {
973 __le16 byte_count;
974 __le16 reserved;
975} __packed;
976
977/**
978 * enum iwl_rx_phy_flags - to parse %iwl_rx_phy_info phy_flags
979 * @RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band
980 * @RX_RES_PHY_FLAGS_MOD_CCK:
981 * @RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short
982 * @RX_RES_PHY_FLAGS_NARROW_BAND:
983 * @RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received
984 * @RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU
985 * @RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame
986 * @RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble
987 * @RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame
988 */
989enum iwl_rx_phy_flags {
990 RX_RES_PHY_FLAGS_BAND_24 = BIT(0),
991 RX_RES_PHY_FLAGS_MOD_CCK = BIT(1),
992 RX_RES_PHY_FLAGS_SHORT_PREAMBLE = BIT(2),
993 RX_RES_PHY_FLAGS_NARROW_BAND = BIT(3),
994 RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4),
995 RX_RES_PHY_FLAGS_ANTENNA_POS = 4,
996 RX_RES_PHY_FLAGS_AGG = BIT(7),
997 RX_RES_PHY_FLAGS_OFDM_HT = BIT(8),
998 RX_RES_PHY_FLAGS_OFDM_GF = BIT(9),
999 RX_RES_PHY_FLAGS_OFDM_VHT = BIT(10),
1000};
1001
1002/**
1003 * enum iwl_mvm_rx_status - written by fw for each Rx packet
1004 * @RX_MPDU_RES_STATUS_CRC_OK: CRC is fine
1005 * @RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow
1006 * @RX_MPDU_RES_STATUS_SRC_STA_FOUND:
1007 * @RX_MPDU_RES_STATUS_KEY_VALID:
1008 * @RX_MPDU_RES_STATUS_KEY_PARAM_OK:
1009 * @RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed
1010 * @RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked
1011 * in the driver.
1012 * @RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine
1013 * @RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or
1014 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if
1015 * %RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set.
1016 * @RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted
1017 * @RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP
1018 * @RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM
1019 * @RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP
1020 * @RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC
1021 * @RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted
1022 * @RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm
1023 * @RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted
1024 * @RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP:
1025 * @RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP:
1026 * @RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT:
1027 * @RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame
1028 * @RX_MPDU_RES_STATUS_HASH_INDEX_MSK:
1029 * @RX_MPDU_RES_STATUS_STA_ID_MSK:
1030 * @RX_MPDU_RES_STATUS_RRF_KILL:
1031 * @RX_MPDU_RES_STATUS_FILTERING_MSK:
1032 * @RX_MPDU_RES_STATUS2_FILTERING_MSK:
1033 */
1034enum iwl_mvm_rx_status {
1035 RX_MPDU_RES_STATUS_CRC_OK = BIT(0),
1036 RX_MPDU_RES_STATUS_OVERRUN_OK = BIT(1),
1037 RX_MPDU_RES_STATUS_SRC_STA_FOUND = BIT(2),
1038 RX_MPDU_RES_STATUS_KEY_VALID = BIT(3),
1039 RX_MPDU_RES_STATUS_KEY_PARAM_OK = BIT(4),
1040 RX_MPDU_RES_STATUS_ICV_OK = BIT(5),
1041 RX_MPDU_RES_STATUS_MIC_OK = BIT(6),
1042 RX_MPDU_RES_STATUS_TTAK_OK = BIT(7),
1043 RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = BIT(7),
1044 RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8),
1045 RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8),
1046 RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8),
1047 RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8),
e36e5433 1048 RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8),
8ca151b5
JB		 1049 RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8),
1050 RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8),
1051 RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8),
1052 RX_MPDU_RES_STATUS_DEC_DONE = BIT(11),
1053 RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = BIT(12),
1054 RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = BIT(13),
1055 RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = BIT(14),
1056 RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = BIT(15),
1057 RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000),
1058 RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000),
1059 RX_MPDU_RES_STATUS_RRF_KILL = BIT(29),
1060 RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000),
1061 RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000),
1062};
1063
1064/**
1065 * struct iwl_radio_version_notif - information on the radio version
1066 * ( RADIO_VERSION_NOTIFICATION = 0x68 )
1067 * @radio_flavor:
1068 * @radio_step:
1069 * @radio_dash:
1070 */
1071struct iwl_radio_version_notif {
1072 __le32 radio_flavor;
1073 __le32 radio_step;
1074 __le32 radio_dash;
1075} __packed; /* RADIO_VERSION_NOTOFICATION_S_VER_1 */
1076
1077enum iwl_card_state_flags {
1078 CARD_ENABLED = 0x00,
1079 HW_CARD_DISABLED = 0x01,
1080 SW_CARD_DISABLED = 0x02,
1081 CT_KILL_CARD_DISABLED = 0x04,
1082 HALT_CARD_DISABLED = 0x08,
1083 CARD_DISABLED_MSK = 0x0f,
1084 CARD_IS_RX_ON = 0x10,
1085};
1086
1087/**
1088 * struct iwl_radio_version_notif - information on the radio version
1089 * ( CARD_STATE_NOTIFICATION = 0xa1 )
1090 * @flags: %iwl_card_state_flags
1091 */
1092struct iwl_card_state_notif {
1093 __le32 flags;
1094} __packed; /* CARD_STATE_NTFY_API_S_VER_1 */
1095
d64048ed
HG		 1096/**
1097 * struct iwl_missed_beacons_notif - information on missed beacons
1098 * ( MISSED_BEACONS_NOTIFICATION = 0xa2 )
1099 * @mac_id: interface ID
1100 * @consec_missed_beacons_since_last_rx: number of consecutive missed
1101 * beacons since last RX.
1102 * @consec_missed_beacons: number of consecutive missed beacons
1103 * @num_expected_beacons:
1104 * @num_recvd_beacons:
1105 */
1106struct iwl_missed_beacons_notif {
1107 __le32 mac_id;
1108 __le32 consec_missed_beacons_since_last_rx;
1109 __le32 consec_missed_beacons;
1110 __le32 num_expected_beacons;
1111 __le32 num_recvd_beacons;
1112} __packed; /* MISSED_BEACON_NTFY_API_S_VER_3 */
1113
8ca151b5
JB		 1114/**
1115 * struct iwl_set_calib_default_cmd - set default value for calibration.
1116 * ( SET_CALIB_DEFAULT_CMD = 0x8e )
1117 * @calib_index: the calibration to set value for
1118 * @length: of data
1119 * @data: the value to set for the calibration result
1120 */
1121struct iwl_set_calib_default_cmd {
1122 __le16 calib_index;
1123 __le16 length;
1124 u8 data[0];
1125} __packed; /* PHY_CALIB_OVERRIDE_VALUES_S */
1126
51b6b9e0 1127#define MAX_PORT_ID_NUM 2
e59647ea 1128#define MAX_MCAST_FILTERING_ADDRESSES 256
51b6b9e0
EG		 1129
1130/**
1131 * struct iwl_mcast_filter_cmd - configure multicast filter.
1132 * @filter_own: Set 1 to filter out multicast packets sent by station itself
1133 * @port_id: Multicast MAC addresses array specifier. This is a strange way
1134 * to identify network interface adopted in host-device IF.
1135 * It is used by FW as index in array of addresses. This array has
1136 * MAX_PORT_ID_NUM members.
1137 * @count: Number of MAC addresses in the array
1138 * @pass_all: Set 1 to pass all multicast packets.
1139 * @bssid: current association BSSID.
1140 * @addr_list: Place holder for array of MAC addresses.
1141 * IMPORTANT: add padding if necessary to ensure DWORD alignment.
1142 */
1143struct iwl_mcast_filter_cmd {
1144 u8 filter_own;
1145 u8 port_id;
1146 u8 count;
1147 u8 pass_all;
1148 u8 bssid[6];
1149 u8 reserved[2];
1150 u8 addr_list[0];
1151} __packed; /* MCAST_FILTERING_CMD_API_S_VER_1 */
1152
c87163b9
EP		 1153#define MAX_BCAST_FILTERS 8
1154#define MAX_BCAST_FILTER_ATTRS 2
1155
1156/**
1157 * enum iwl_mvm_bcast_filter_attr_offset - written by fw for each Rx packet
1158 * @BCAST_FILTER_OFFSET_PAYLOAD_START: offset is from payload start.
1159 * @BCAST_FILTER_OFFSET_IP_END: offset is from ip header end (i.e.
1160 * start of ip payload).
1161 */
1162enum iwl_mvm_bcast_filter_attr_offset {
1163 BCAST_FILTER_OFFSET_PAYLOAD_START = 0,
1164 BCAST_FILTER_OFFSET_IP_END = 1,
1165};
1166
1167/**
1168 * struct iwl_fw_bcast_filter_attr - broadcast filter attribute
1169 * @offset_type: &enum iwl_mvm_bcast_filter_attr_offset.
1170 * @offset: starting offset of this pattern.
1171 * @val: value to match - big endian (MSB is the first
1172 * byte to match from offset pos).
1173 * @mask: mask to match (big endian).
1174 */
1175struct iwl_fw_bcast_filter_attr {
1176 u8 offset_type;
1177 u8 offset;
1178 __le16 reserved1;
1179 __be32 val;
1180 __be32 mask;
1181} __packed; /* BCAST_FILTER_ATT_S_VER_1 */
1182
1183/**
1184 * enum iwl_mvm_bcast_filter_frame_type - filter frame type
1185 * @BCAST_FILTER_FRAME_TYPE_ALL: consider all frames.
1186 * @BCAST_FILTER_FRAME_TYPE_IPV4: consider only ipv4 frames
1187 */
1188enum iwl_mvm_bcast_filter_frame_type {
1189 BCAST_FILTER_FRAME_TYPE_ALL = 0,
1190 BCAST_FILTER_FRAME_TYPE_IPV4 = 1,
1191};
1192
1193/**
1194 * struct iwl_fw_bcast_filter - broadcast filter
1195 * @discard: discard frame (1) or let it pass (0).
1196 * @frame_type: &enum iwl_mvm_bcast_filter_frame_type.
1197 * @num_attrs: number of valid attributes in this filter.
1198 * @attrs: attributes of this filter. a filter is considered matched
1199 * only when all its attributes are matched (i.e. AND relationship)
1200 */
1201struct iwl_fw_bcast_filter {
1202 u8 discard;
1203 u8 frame_type;
1204 u8 num_attrs;
1205 u8 reserved1;
1206 struct iwl_fw_bcast_filter_attr attrs[MAX_BCAST_FILTER_ATTRS];
1207} __packed; /* BCAST_FILTER_S_VER_1 */
1208
1209/**
1210 * struct iwl_fw_bcast_mac - per-mac broadcast filtering configuration.
1211 * @default_discard: default action for this mac (discard (1) / pass (0)).
1212 * @attached_filters: bitmap of relevant filters for this mac.
1213 */
1214struct iwl_fw_bcast_mac {
1215 u8 default_discard;
1216 u8 reserved1;
1217 __le16 attached_filters;
1218} __packed; /* BCAST_MAC_CONTEXT_S_VER_1 */
1219
1220/**
1221 * struct iwl_bcast_filter_cmd - broadcast filtering configuration
1222 * @disable: enable (0) / disable (1)
1223 * @max_bcast_filters: max number of filters (MAX_BCAST_FILTERS)
1224 * @max_macs: max number of macs (NUM_MAC_INDEX_DRIVER)
1225 * @filters: broadcast filters
1226 * @macs: broadcast filtering configuration per-mac
1227 */
1228struct iwl_bcast_filter_cmd {
1229 u8 disable;
1230 u8 max_bcast_filters;
1231 u8 max_macs;
1232 u8 reserved1;
1233 struct iwl_fw_bcast_filter filters[MAX_BCAST_FILTERS];
1234 struct iwl_fw_bcast_mac macs[NUM_MAC_INDEX_DRIVER];
1235} __packed; /* BCAST_FILTERING_HCMD_API_S_VER_1 */
1236
9ee718aa
EL		 1237struct mvm_statistics_dbg {
1238 __le32 burst_check;
1239 __le32 burst_count;
1240 __le32 wait_for_silence_timeout_cnt;
1241 __le32 reserved[3];
1242} __packed; /* STATISTICS_DEBUG_API_S_VER_2 */
1243
1244struct mvm_statistics_div {
1245 __le32 tx_on_a;
1246 __le32 tx_on_b;
1247 __le32 exec_time;
1248 __le32 probe_time;
1249 __le32 rssi_ant;
1250 __le32 reserved2;
1251} __packed; /* STATISTICS_SLOW_DIV_API_S_VER_2 */
1252
1253struct mvm_statistics_general_common {
1254 __le32 temperature; /* radio temperature */
1255 __le32 temperature_m; /* radio voltage */
1256 struct mvm_statistics_dbg dbg;
1257 __le32 sleep_time;
1258 __le32 slots_out;
1259 __le32 slots_idle;
1260 __le32 ttl_timestamp;
1261 struct mvm_statistics_div div;
1262 __le32 rx_enable_counter;
1263 /*
1264 * num_of_sos_states:
1265 * count the number of times we have to re-tune
1266 * in order to get out of bad PHY status
1267 */
1268 __le32 num_of_sos_states;
1269} __packed; /* STATISTICS_GENERAL_API_S_VER_5 */
1270
1271struct mvm_statistics_rx_non_phy {
1272 __le32 bogus_cts; /* CTS received when not expecting CTS */
1273 __le32 bogus_ack; /* ACK received when not expecting ACK */
1274 __le32 non_bssid_frames; /* number of frames with BSSID that
1275 * doesn't belong to the STA BSSID */
1276 __le32 filtered_frames; /* count frames that were dumped in the
1277 * filtering process */
1278 __le32 non_channel_beacons; /* beacons with our bss id but not on
1279 * our serving channel */
1280 __le32 channel_beacons; /* beacons with our bss id and in our
1281 * serving channel */
1282 __le32 num_missed_bcon; /* number of missed beacons */
1283 __le32 adc_rx_saturation_time; /* count in 0.8us units the time the
1284 * ADC was in saturation */
1285 __le32 ina_detection_search_time;/* total time (in 0.8us) searched
1286 * for INA */
1287 __le32 beacon_silence_rssi_a; /* RSSI silence after beacon frame */
1288 __le32 beacon_silence_rssi_b; /* RSSI silence after beacon frame */
1289 __le32 beacon_silence_rssi_c; /* RSSI silence after beacon frame */
1290 __le32 interference_data_flag; /* flag for interference data
1291 * availability. 1 when data is
1292 * available. */
1293 __le32 channel_load; /* counts RX Enable time in uSec */
1294 __le32 dsp_false_alarms; /* DSP false alarm (both OFDM
1295 * and CCK) counter */
1296 __le32 beacon_rssi_a;
1297 __le32 beacon_rssi_b;
1298 __le32 beacon_rssi_c;
1299 __le32 beacon_energy_a;
1300 __le32 beacon_energy_b;
1301 __le32 beacon_energy_c;
1302 __le32 num_bt_kills;
1303 __le32 mac_id;
1304 __le32 directed_data_mpdu;
1305} __packed; /* STATISTICS_RX_NON_PHY_API_S_VER_3 */
1306
1307struct mvm_statistics_rx_phy {
1308 __le32 ina_cnt;
1309 __le32 fina_cnt;
1310 __le32 plcp_err;
1311 __le32 crc32_err;
1312 __le32 overrun_err;
1313 __le32 early_overrun_err;
1314 __le32 crc32_good;
1315 __le32 false_alarm_cnt;
1316 __le32 fina_sync_err_cnt;
1317 __le32 sfd_timeout;
1318 __le32 fina_timeout;
1319 __le32 unresponded_rts;
1320 __le32 rxe_frame_limit_overrun;
1321 __le32 sent_ack_cnt;
1322 __le32 sent_cts_cnt;
1323 __le32 sent_ba_rsp_cnt;
1324 __le32 dsp_self_kill;
1325 __le32 mh_format_err;
1326 __le32 re_acq_main_rssi_sum;
1327 __le32 reserved;
1328} __packed; /* STATISTICS_RX_PHY_API_S_VER_2 */
1329
1330struct mvm_statistics_rx_ht_phy {
1331 __le32 plcp_err;
1332 __le32 overrun_err;
1333 __le32 early_overrun_err;
1334 __le32 crc32_good;
1335 __le32 crc32_err;
1336 __le32 mh_format_err;
1337 __le32 agg_crc32_good;
1338 __le32 agg_mpdu_cnt;
1339 __le32 agg_cnt;
1340 __le32 unsupport_mcs;
1341} __packed; /* STATISTICS_HT_RX_PHY_API_S_VER_1 */
1342
1343#define MAX_CHAINS 3
1344
1345struct mvm_statistics_tx_non_phy_agg {
1346 __le32 ba_timeout;
1347 __le32 ba_reschedule_frames;
1348 __le32 scd_query_agg_frame_cnt;
1349 __le32 scd_query_no_agg;
1350 __le32 scd_query_agg;
1351 __le32 scd_query_mismatch;
1352 __le32 frame_not_ready;
1353 __le32 underrun;
1354 __le32 bt_prio_kill;
1355 __le32 rx_ba_rsp_cnt;
1356 __s8 txpower[MAX_CHAINS];
1357 __s8 reserved;
1358 __le32 reserved2;
1359} __packed; /* STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */
1360
1361struct mvm_statistics_tx_channel_width {
1362 __le32 ext_cca_narrow_ch20[1];
1363 __le32 ext_cca_narrow_ch40[2];
1364 __le32 ext_cca_narrow_ch80[3];
1365 __le32 ext_cca_narrow_ch160[4];
1366 __le32 last_tx_ch_width_indx;
1367 __le32 rx_detected_per_ch_width[4];
1368 __le32 success_per_ch_width[4];
1369 __le32 fail_per_ch_width[4];
1370}; /* STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */
1371
1372struct mvm_statistics_tx {
1373 __le32 preamble_cnt;
1374 __le32 rx_detected_cnt;
1375 __le32 bt_prio_defer_cnt;
1376 __le32 bt_prio_kill_cnt;
1377 __le32 few_bytes_cnt;
1378 __le32 cts_timeout;
1379 __le32 ack_timeout;
1380 __le32 expected_ack_cnt;
1381 __le32 actual_ack_cnt;
1382 __le32 dump_msdu_cnt;
1383 __le32 burst_abort_next_frame_mismatch_cnt;
1384 __le32 burst_abort_missing_next_frame_cnt;
1385 __le32 cts_timeout_collision;
1386 __le32 ack_or_ba_timeout_collision;
1387 struct mvm_statistics_tx_non_phy_agg agg;
1388 struct mvm_statistics_tx_channel_width channel_width;
1389} __packed; /* STATISTICS_TX_API_S_VER_4 */
1390
1391
1392struct mvm_statistics_bt_activity {
1393 __le32 hi_priority_tx_req_cnt;
1394 __le32 hi_priority_tx_denied_cnt;
1395 __le32 lo_priority_tx_req_cnt;
1396 __le32 lo_priority_tx_denied_cnt;
1397 __le32 hi_priority_rx_req_cnt;
1398 __le32 hi_priority_rx_denied_cnt;
1399 __le32 lo_priority_rx_req_cnt;
1400 __le32 lo_priority_rx_denied_cnt;
1401} __packed; /* STATISTICS_BT_ACTIVITY_API_S_VER_1 */
1402
1403struct mvm_statistics_general {
1404 struct mvm_statistics_general_common common;
1405 __le32 beacon_filtered;
1406 __le32 missed_beacons;
a20fd398 1407 __s8 beacon_filter_average_energy;
9ee718aa
EL		 1408 __s8 beacon_filter_reason;
1409 __s8 beacon_filter_current_energy;
1410 __s8 beacon_filter_reserved;
1411 __le32 beacon_filter_delta_time;
1412 struct mvm_statistics_bt_activity bt_activity;
1413} __packed; /* STATISTICS_GENERAL_API_S_VER_5 */
1414
1415struct mvm_statistics_rx {
1416 struct mvm_statistics_rx_phy ofdm;
1417 struct mvm_statistics_rx_phy cck;
1418 struct mvm_statistics_rx_non_phy general;
1419 struct mvm_statistics_rx_ht_phy ofdm_ht;
1420} __packed; /* STATISTICS_RX_API_S_VER_3 */
1421
1422/*
1423 * STATISTICS_NOTIFICATION = 0x9d (notification only, not a command)
1424 *
1425 * By default, uCode issues this notification after receiving a beacon
1426 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the
1427 * REPLY_STATISTICS_CMD 0x9c, above.
1428 *
1429 * Statistics counters continue to increment beacon after beacon, but are
1430 * cleared when changing channels or when driver issues REPLY_STATISTICS_CMD
1431 * 0x9c with CLEAR_STATS bit set (see above).
1432 *
1433 * uCode also issues this notification during scans. uCode clears statistics
1434 * appropriately so that each notification contains statistics for only the
1435 * one channel that has just been scanned.
1436 */
1437
1438struct iwl_notif_statistics { /* STATISTICS_NTFY_API_S_VER_8 */
1439 __le32 flag;
1440 struct mvm_statistics_rx rx;
1441 struct mvm_statistics_tx tx;
1442 struct mvm_statistics_general general;
1443} __packed;
1444
1f3b0ff8
LE		 1445/***********************************
1446 * Smart Fifo API
1447 ***********************************/
1448/* Smart Fifo state */
1449enum iwl_sf_state {
1450 SF_LONG_DELAY_ON = 0, /* should never be called by driver */
1451 SF_FULL_ON,
1452 SF_UNINIT,
1453 SF_INIT_OFF,
1454 SF_HW_NUM_STATES
1455};
1456
1457/* Smart Fifo possible scenario */
1458enum iwl_sf_scenario {
1459 SF_SCENARIO_SINGLE_UNICAST,
1460 SF_SCENARIO_AGG_UNICAST,
1461 SF_SCENARIO_MULTICAST,
1462 SF_SCENARIO_BA_RESP,
1463 SF_SCENARIO_TX_RESP,
1464 SF_NUM_SCENARIO
1465};
1466
1467#define SF_TRANSIENT_STATES_NUMBER 2 /* SF_LONG_DELAY_ON and SF_FULL_ON */
1468#define SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */
1469
1470/* smart FIFO default values */
1471#define SF_W_MARK_SISO 4096
1472#define SF_W_MARK_MIMO2 8192
1473#define SF_W_MARK_MIMO3 6144
1474#define SF_W_MARK_LEGACY 4096
1475#define SF_W_MARK_SCAN 4096
1476
1477/* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */
1478#define SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */
1479#define SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */
1480#define SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */
1481#define SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */
1482#define SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */
1483#define SF_MCAST_AGING_TIMER 10016 /* 10 mSec */
1484#define SF_BA_IDLE_TIMER 320 /* 300 uSec */
1485#define SF_BA_AGING_TIMER 2016 /* 2 mSec */
1486#define SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */
1487#define SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */
1488
1489#define SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */
1490
1491/**
1492 * Smart Fifo configuration command.
1493 * @state: smart fifo state, types listed in iwl_sf_sate.
1494 * @watermark: Minimum allowed availabe free space in RXF for transient state.
1495 * @long_delay_timeouts: aging and idle timer values for each scenario
1496 * in long delay state.
1497 * @full_on_timeouts: timer values for each scenario in full on state.
1498 */
1499struct iwl_sf_cfg_cmd {
1500 enum iwl_sf_state state;
1501 __le32 watermark[SF_TRANSIENT_STATES_NUMBER];
1502 __le32 long_delay_timeouts[SF_NUM_SCENARIO][SF_NUM_TIMEOUT_TYPES];
1503 __le32 full_on_timeouts[SF_NUM_SCENARIO][SF_NUM_TIMEOUT_TYPES];
1504} __packed; /* SF_CFG_API_S_VER_2 */
1505
8ca151b5 1506#endif /* __fw_api_h__ */
Linux kernel - Deliverables
This page took 0.166005 seconds and 5 git commands to generate.