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8ca151b5 JB |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
51368bf7 | 8 | * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. |
8d193ca2 | 9 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH |
8ca151b5 JB |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of version 2 of the GNU General Public License as | |
13 | * published by the Free Software Foundation. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but | |
16 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
23 | * USA | |
24 | * | |
25 | * The full GNU General Public License is included in this distribution | |
410dc5aa | 26 | * in the file called COPYING. |
8ca151b5 JB |
27 | * |
28 | * Contact Information: | |
29 | * Intel Linux Wireless <ilw@linux.intel.com> | |
30 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
31 | * | |
32 | * BSD LICENSE | |
33 | * | |
51368bf7 | 34 | * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. |
8d193ca2 | 35 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH |
8ca151b5 JB |
36 | * All rights reserved. |
37 | * | |
38 | * Redistribution and use in source and binary forms, with or without | |
39 | * modification, are permitted provided that the following conditions | |
40 | * are met: | |
41 | * | |
42 | * * Redistributions of source code must retain the above copyright | |
43 | * notice, this list of conditions and the following disclaimer. | |
44 | * * Redistributions in binary form must reproduce the above copyright | |
45 | * notice, this list of conditions and the following disclaimer in | |
46 | * the documentation and/or other materials provided with the | |
47 | * distribution. | |
48 | * * Neither the name Intel Corporation nor the names of its | |
49 | * contributors may be used to endorse or promote products derived | |
50 | * from this software without specific prior written permission. | |
51 | * | |
52 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
53 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
54 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
55 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
56 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
57 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
58 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
59 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
60 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
61 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
62 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
63 | * | |
64 | *****************************************************************************/ | |
65 | #include <net/mac80211.h> | |
66 | ||
67 | #include "iwl-trans.h" | |
68 | #include "iwl-op-mode.h" | |
69 | #include "iwl-fw.h" | |
70 | #include "iwl-debug.h" | |
71 | #include "iwl-csr.h" /* for iwl_mvm_rx_card_state_notif */ | |
72 | #include "iwl-io.h" /* for iwl_mvm_rx_card_state_notif */ | |
8c23f95c | 73 | #include "iwl-prph.h" |
8ca151b5 JB |
74 | #include "iwl-eeprom-parse.h" |
75 | ||
76 | #include "mvm.h" | |
77 | #include "iwl-phy-db.h" | |
78 | ||
79 | #define MVM_UCODE_ALIVE_TIMEOUT HZ | |
80 | #define MVM_UCODE_CALIB_TIMEOUT (2*HZ) | |
81 | ||
82 | #define UCODE_VALID_OK cpu_to_le32(0x1) | |
83 | ||
8ca151b5 JB |
84 | struct iwl_mvm_alive_data { |
85 | bool valid; | |
86 | u32 scd_base_addr; | |
87 | }; | |
88 | ||
89 | static inline const struct fw_img * | |
90 | iwl_get_ucode_image(struct iwl_mvm *mvm, enum iwl_ucode_type ucode_type) | |
91 | { | |
92 | if (ucode_type >= IWL_UCODE_TYPE_MAX) | |
93 | return NULL; | |
94 | ||
95 | return &mvm->fw->img[ucode_type]; | |
96 | } | |
97 | ||
98 | static int iwl_send_tx_ant_cfg(struct iwl_mvm *mvm, u8 valid_tx_ant) | |
99 | { | |
100 | struct iwl_tx_ant_cfg_cmd tx_ant_cmd = { | |
101 | .valid = cpu_to_le32(valid_tx_ant), | |
102 | }; | |
103 | ||
33223542 | 104 | IWL_DEBUG_FW(mvm, "select valid tx ant: %u\n", valid_tx_ant); |
a1022927 | 105 | return iwl_mvm_send_cmd_pdu(mvm, TX_ANT_CONFIGURATION_CMD, 0, |
8ca151b5 JB |
106 | sizeof(tx_ant_cmd), &tx_ant_cmd); |
107 | } | |
108 | ||
a6c4fb44 MG |
109 | static void iwl_free_fw_paging(struct iwl_mvm *mvm) |
110 | { | |
111 | int i; | |
112 | ||
113 | if (!mvm->fw_paging_db[0].fw_paging_block) | |
114 | return; | |
115 | ||
116 | for (i = 0; i < NUM_OF_FW_PAGING_BLOCKS; i++) { | |
117 | if (!mvm->fw_paging_db[i].fw_paging_block) { | |
118 | IWL_DEBUG_FW(mvm, | |
119 | "Paging: block %d already freed, continue to next page\n", | |
120 | i); | |
121 | ||
122 | continue; | |
123 | } | |
124 | ||
125 | __free_pages(mvm->fw_paging_db[i].fw_paging_block, | |
126 | get_order(mvm->fw_paging_db[i].fw_paging_size)); | |
127 | } | |
e1120187 | 128 | kfree(mvm->trans->paging_download_buf); |
a6c4fb44 MG |
129 | memset(mvm->fw_paging_db, 0, sizeof(mvm->fw_paging_db)); |
130 | } | |
131 | ||
132 | static int iwl_fill_paging_mem(struct iwl_mvm *mvm, const struct fw_img *image) | |
133 | { | |
134 | int sec_idx, idx; | |
135 | u32 offset = 0; | |
136 | ||
137 | /* | |
138 | * find where is the paging image start point: | |
139 | * if CPU2 exist and it's in paging format, then the image looks like: | |
140 | * CPU1 sections (2 or more) | |
141 | * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between CPU1 to CPU2 | |
142 | * CPU2 sections (not paged) | |
143 | * PAGING_SEPARATOR_SECTION delimiter - separate between CPU2 | |
144 | * non paged to CPU2 paging sec | |
145 | * CPU2 paging CSS | |
146 | * CPU2 paging image (including instruction and data) | |
147 | */ | |
148 | for (sec_idx = 0; sec_idx < IWL_UCODE_SECTION_MAX; sec_idx++) { | |
149 | if (image->sec[sec_idx].offset == PAGING_SEPARATOR_SECTION) { | |
150 | sec_idx++; | |
151 | break; | |
152 | } | |
153 | } | |
154 | ||
155 | if (sec_idx >= IWL_UCODE_SECTION_MAX) { | |
156 | IWL_ERR(mvm, "driver didn't find paging image\n"); | |
157 | iwl_free_fw_paging(mvm); | |
158 | return -EINVAL; | |
159 | } | |
160 | ||
161 | /* copy the CSS block to the dram */ | |
162 | IWL_DEBUG_FW(mvm, "Paging: load paging CSS to FW, sec = %d\n", | |
163 | sec_idx); | |
164 | ||
165 | memcpy(page_address(mvm->fw_paging_db[0].fw_paging_block), | |
166 | image->sec[sec_idx].data, | |
167 | mvm->fw_paging_db[0].fw_paging_size); | |
168 | ||
169 | IWL_DEBUG_FW(mvm, | |
170 | "Paging: copied %d CSS bytes to first block\n", | |
171 | mvm->fw_paging_db[0].fw_paging_size); | |
172 | ||
173 | sec_idx++; | |
174 | ||
175 | /* | |
176 | * copy the paging blocks to the dram | |
177 | * loop index start from 1 since that CSS block already copied to dram | |
178 | * and CSS index is 0. | |
179 | * loop stop at num_of_paging_blk since that last block is not full. | |
180 | */ | |
181 | for (idx = 1; idx < mvm->num_of_paging_blk; idx++) { | |
182 | memcpy(page_address(mvm->fw_paging_db[idx].fw_paging_block), | |
183 | image->sec[sec_idx].data + offset, | |
184 | mvm->fw_paging_db[idx].fw_paging_size); | |
185 | ||
186 | IWL_DEBUG_FW(mvm, | |
187 | "Paging: copied %d paging bytes to block %d\n", | |
188 | mvm->fw_paging_db[idx].fw_paging_size, | |
189 | idx); | |
190 | ||
191 | offset += mvm->fw_paging_db[idx].fw_paging_size; | |
192 | } | |
193 | ||
194 | /* copy the last paging block */ | |
195 | if (mvm->num_of_pages_in_last_blk > 0) { | |
196 | memcpy(page_address(mvm->fw_paging_db[idx].fw_paging_block), | |
197 | image->sec[sec_idx].data + offset, | |
198 | FW_PAGING_SIZE * mvm->num_of_pages_in_last_blk); | |
199 | ||
200 | IWL_DEBUG_FW(mvm, | |
201 | "Paging: copied %d pages in the last block %d\n", | |
202 | mvm->num_of_pages_in_last_blk, idx); | |
203 | } | |
204 | ||
205 | return 0; | |
206 | } | |
207 | ||
208 | static int iwl_alloc_fw_paging_mem(struct iwl_mvm *mvm, | |
209 | const struct fw_img *image) | |
210 | { | |
211 | struct page *block; | |
212 | dma_addr_t phys = 0; | |
213 | int blk_idx = 0; | |
214 | int order, num_of_pages; | |
215 | int dma_enabled; | |
216 | ||
217 | if (mvm->fw_paging_db[0].fw_paging_block) | |
218 | return 0; | |
219 | ||
220 | dma_enabled = is_device_dma_capable(mvm->trans->dev); | |
221 | ||
222 | /* ensure BLOCK_2_EXP_SIZE is power of 2 of PAGING_BLOCK_SIZE */ | |
223 | BUILD_BUG_ON(BIT(BLOCK_2_EXP_SIZE) != PAGING_BLOCK_SIZE); | |
224 | ||
225 | num_of_pages = image->paging_mem_size / FW_PAGING_SIZE; | |
226 | mvm->num_of_paging_blk = ((num_of_pages - 1) / | |
227 | NUM_OF_PAGE_PER_GROUP) + 1; | |
228 | ||
229 | mvm->num_of_pages_in_last_blk = | |
230 | num_of_pages - | |
231 | NUM_OF_PAGE_PER_GROUP * (mvm->num_of_paging_blk - 1); | |
232 | ||
233 | IWL_DEBUG_FW(mvm, | |
234 | "Paging: allocating mem for %d paging blocks, each block holds 8 pages, last block holds %d pages\n", | |
235 | mvm->num_of_paging_blk, | |
236 | mvm->num_of_pages_in_last_blk); | |
237 | ||
238 | /* allocate block of 4Kbytes for paging CSS */ | |
239 | order = get_order(FW_PAGING_SIZE); | |
240 | block = alloc_pages(GFP_KERNEL, order); | |
241 | if (!block) { | |
242 | /* free all the previous pages since we failed */ | |
243 | iwl_free_fw_paging(mvm); | |
244 | return -ENOMEM; | |
245 | } | |
246 | ||
247 | mvm->fw_paging_db[blk_idx].fw_paging_block = block; | |
248 | mvm->fw_paging_db[blk_idx].fw_paging_size = FW_PAGING_SIZE; | |
249 | ||
250 | if (dma_enabled) { | |
251 | phys = dma_map_page(mvm->trans->dev, block, 0, | |
252 | PAGE_SIZE << order, DMA_BIDIRECTIONAL); | |
253 | if (dma_mapping_error(mvm->trans->dev, phys)) { | |
254 | /* | |
255 | * free the previous pages and the current one since | |
256 | * we failed to map_page. | |
257 | */ | |
258 | iwl_free_fw_paging(mvm); | |
259 | return -ENOMEM; | |
260 | } | |
261 | mvm->fw_paging_db[blk_idx].fw_paging_phys = phys; | |
e1120187 MG |
262 | } else { |
263 | mvm->fw_paging_db[blk_idx].fw_paging_phys = PAGING_ADDR_SIG | | |
264 | blk_idx << BLOCK_2_EXP_SIZE; | |
a6c4fb44 MG |
265 | } |
266 | ||
267 | IWL_DEBUG_FW(mvm, | |
268 | "Paging: allocated 4K(CSS) bytes (order %d) for firmware paging.\n", | |
269 | order); | |
270 | ||
271 | /* | |
272 | * allocate blocks in dram. | |
273 | * since that CSS allocated in fw_paging_db[0] loop start from index 1 | |
274 | */ | |
275 | for (blk_idx = 1; blk_idx < mvm->num_of_paging_blk + 1; blk_idx++) { | |
276 | /* allocate block of PAGING_BLOCK_SIZE (32K) */ | |
277 | order = get_order(PAGING_BLOCK_SIZE); | |
278 | block = alloc_pages(GFP_KERNEL, order); | |
279 | if (!block) { | |
280 | /* free all the previous pages since we failed */ | |
281 | iwl_free_fw_paging(mvm); | |
282 | return -ENOMEM; | |
283 | } | |
284 | ||
285 | mvm->fw_paging_db[blk_idx].fw_paging_block = block; | |
286 | mvm->fw_paging_db[blk_idx].fw_paging_size = PAGING_BLOCK_SIZE; | |
287 | ||
288 | if (dma_enabled) { | |
289 | phys = dma_map_page(mvm->trans->dev, block, 0, | |
290 | PAGE_SIZE << order, | |
291 | DMA_BIDIRECTIONAL); | |
292 | if (dma_mapping_error(mvm->trans->dev, phys)) { | |
293 | /* | |
294 | * free the previous pages and the current one | |
295 | * since we failed to map_page. | |
296 | */ | |
297 | iwl_free_fw_paging(mvm); | |
298 | return -ENOMEM; | |
299 | } | |
300 | mvm->fw_paging_db[blk_idx].fw_paging_phys = phys; | |
e1120187 MG |
301 | } else { |
302 | mvm->fw_paging_db[blk_idx].fw_paging_phys = | |
303 | PAGING_ADDR_SIG | | |
304 | blk_idx << BLOCK_2_EXP_SIZE; | |
a6c4fb44 MG |
305 | } |
306 | ||
307 | IWL_DEBUG_FW(mvm, | |
308 | "Paging: allocated 32K bytes (order %d) for firmware paging.\n", | |
309 | order); | |
310 | } | |
311 | ||
312 | return 0; | |
313 | } | |
314 | ||
315 | static int iwl_save_fw_paging(struct iwl_mvm *mvm, | |
316 | const struct fw_img *fw) | |
317 | { | |
318 | int ret; | |
319 | ||
320 | ret = iwl_alloc_fw_paging_mem(mvm, fw); | |
321 | if (ret) | |
322 | return ret; | |
323 | ||
324 | return iwl_fill_paging_mem(mvm, fw); | |
325 | } | |
326 | ||
327 | /* send paging cmd to FW in case CPU2 has paging image */ | |
328 | static int iwl_send_paging_cmd(struct iwl_mvm *mvm, const struct fw_img *fw) | |
329 | { | |
330 | int blk_idx; | |
331 | __le32 dev_phy_addr; | |
332 | struct iwl_fw_paging_cmd fw_paging_cmd = { | |
333 | .flags = | |
334 | cpu_to_le32(PAGING_CMD_IS_SECURED | | |
335 | PAGING_CMD_IS_ENABLED | | |
336 | (mvm->num_of_pages_in_last_blk << | |
337 | PAGING_CMD_NUM_OF_PAGES_IN_LAST_GRP_POS)), | |
338 | .block_size = cpu_to_le32(BLOCK_2_EXP_SIZE), | |
339 | .block_num = cpu_to_le32(mvm->num_of_paging_blk), | |
340 | }; | |
341 | ||
342 | /* loop for for all paging blocks + CSS block */ | |
343 | for (blk_idx = 0; blk_idx < mvm->num_of_paging_blk + 1; blk_idx++) { | |
344 | dev_phy_addr = | |
345 | cpu_to_le32(mvm->fw_paging_db[blk_idx].fw_paging_phys >> | |
346 | PAGE_2_EXP_SIZE); | |
347 | fw_paging_cmd.device_phy_addr[blk_idx] = dev_phy_addr; | |
348 | } | |
349 | ||
350 | return iwl_mvm_send_cmd_pdu(mvm, iwl_cmd_id(FW_PAGING_BLOCK_CMD, | |
351 | IWL_ALWAYS_LONG_GROUP, 0), | |
352 | 0, sizeof(fw_paging_cmd), &fw_paging_cmd); | |
353 | } | |
354 | ||
e1120187 MG |
355 | /* |
356 | * Send paging item cmd to FW in case CPU2 has paging image | |
357 | */ | |
358 | static int iwl_trans_get_paging_item(struct iwl_mvm *mvm) | |
359 | { | |
360 | int ret; | |
361 | struct iwl_fw_get_item_cmd fw_get_item_cmd = { | |
362 | .item_id = cpu_to_le32(IWL_FW_ITEM_ID_PAGING), | |
363 | }; | |
364 | ||
365 | struct iwl_fw_get_item_resp *item_resp; | |
366 | struct iwl_host_cmd cmd = { | |
367 | .id = iwl_cmd_id(FW_GET_ITEM_CMD, IWL_ALWAYS_LONG_GROUP, 0), | |
368 | .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL, | |
369 | .data = { &fw_get_item_cmd, }, | |
370 | }; | |
371 | ||
372 | cmd.len[0] = sizeof(struct iwl_fw_get_item_cmd); | |
373 | ||
374 | ret = iwl_mvm_send_cmd(mvm, &cmd); | |
375 | if (ret) { | |
376 | IWL_ERR(mvm, | |
377 | "Paging: Failed to send FW_GET_ITEM_CMD cmd (err = %d)\n", | |
378 | ret); | |
379 | return ret; | |
380 | } | |
381 | ||
382 | item_resp = (void *)((struct iwl_rx_packet *)cmd.resp_pkt)->data; | |
383 | if (item_resp->item_id != cpu_to_le32(IWL_FW_ITEM_ID_PAGING)) { | |
384 | IWL_ERR(mvm, | |
385 | "Paging: got wrong item in FW_GET_ITEM_CMD resp (item_id = %u)\n", | |
386 | le32_to_cpu(item_resp->item_id)); | |
387 | ret = -EIO; | |
388 | goto exit; | |
389 | } | |
390 | ||
391 | mvm->trans->paging_download_buf = kzalloc(MAX_PAGING_IMAGE_SIZE, | |
392 | GFP_KERNEL); | |
393 | if (!mvm->trans->paging_download_buf) { | |
394 | ret = -ENOMEM; | |
395 | goto exit; | |
396 | } | |
397 | mvm->trans->paging_req_addr = le32_to_cpu(item_resp->item_val); | |
398 | mvm->trans->paging_db = mvm->fw_paging_db; | |
399 | IWL_DEBUG_FW(mvm, | |
400 | "Paging: got paging request address (paging_req_addr 0x%08x)\n", | |
401 | mvm->trans->paging_req_addr); | |
402 | ||
403 | exit: | |
404 | iwl_free_resp(&cmd); | |
405 | ||
406 | return ret; | |
407 | } | |
408 | ||
8ca151b5 JB |
409 | static bool iwl_alive_fn(struct iwl_notif_wait_data *notif_wait, |
410 | struct iwl_rx_packet *pkt, void *data) | |
411 | { | |
412 | struct iwl_mvm *mvm = | |
413 | container_of(notif_wait, struct iwl_mvm, notif_wait); | |
414 | struct iwl_mvm_alive_data *alive_data = data; | |
7e1223b5 | 415 | struct mvm_alive_resp_ver1 *palive1; |
01a9ca51 | 416 | struct mvm_alive_resp_ver2 *palive2; |
7e1223b5 | 417 | struct mvm_alive_resp *palive; |
01a9ca51 | 418 | |
7e1223b5 EG |
419 | if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive1)) { |
420 | palive1 = (void *)pkt->data; | |
01a9ca51 EH |
421 | |
422 | mvm->support_umac_log = false; | |
423 | mvm->error_event_table = | |
7e1223b5 EG |
424 | le32_to_cpu(palive1->error_event_table_ptr); |
425 | mvm->log_event_table = | |
426 | le32_to_cpu(palive1->log_event_table_ptr); | |
427 | alive_data->scd_base_addr = le32_to_cpu(palive1->scd_base_ptr); | |
01a9ca51 | 428 | |
7e1223b5 | 429 | alive_data->valid = le16_to_cpu(palive1->status) == |
01a9ca51 EH |
430 | IWL_ALIVE_STATUS_OK; |
431 | IWL_DEBUG_FW(mvm, | |
432 | "Alive VER1 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n", | |
7e1223b5 EG |
433 | le16_to_cpu(palive1->status), palive1->ver_type, |
434 | palive1->ver_subtype, palive1->flags); | |
435 | } else if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive2)) { | |
01a9ca51 EH |
436 | palive2 = (void *)pkt->data; |
437 | ||
01a9ca51 EH |
438 | mvm->error_event_table = |
439 | le32_to_cpu(palive2->error_event_table_ptr); | |
440 | mvm->log_event_table = | |
441 | le32_to_cpu(palive2->log_event_table_ptr); | |
442 | alive_data->scd_base_addr = le32_to_cpu(palive2->scd_base_ptr); | |
443 | mvm->umac_error_event_table = | |
444 | le32_to_cpu(palive2->error_info_addr); | |
91479b64 EH |
445 | mvm->sf_space.addr = le32_to_cpu(palive2->st_fwrd_addr); |
446 | mvm->sf_space.size = le32_to_cpu(palive2->st_fwrd_size); | |
01a9ca51 EH |
447 | |
448 | alive_data->valid = le16_to_cpu(palive2->status) == | |
449 | IWL_ALIVE_STATUS_OK; | |
ffa70264 EG |
450 | if (mvm->umac_error_event_table) |
451 | mvm->support_umac_log = true; | |
452 | ||
01a9ca51 EH |
453 | IWL_DEBUG_FW(mvm, |
454 | "Alive VER2 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n", | |
455 | le16_to_cpu(palive2->status), palive2->ver_type, | |
456 | palive2->ver_subtype, palive2->flags); | |
457 | ||
458 | IWL_DEBUG_FW(mvm, | |
459 | "UMAC version: Major - 0x%x, Minor - 0x%x\n", | |
460 | palive2->umac_major, palive2->umac_minor); | |
7e1223b5 EG |
461 | } else if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive)) { |
462 | palive = (void *)pkt->data; | |
463 | ||
464 | mvm->error_event_table = | |
465 | le32_to_cpu(palive->error_event_table_ptr); | |
466 | mvm->log_event_table = | |
467 | le32_to_cpu(palive->log_event_table_ptr); | |
468 | alive_data->scd_base_addr = le32_to_cpu(palive->scd_base_ptr); | |
469 | mvm->umac_error_event_table = | |
470 | le32_to_cpu(palive->error_info_addr); | |
471 | mvm->sf_space.addr = le32_to_cpu(palive->st_fwrd_addr); | |
472 | mvm->sf_space.size = le32_to_cpu(palive->st_fwrd_size); | |
473 | ||
474 | alive_data->valid = le16_to_cpu(palive->status) == | |
475 | IWL_ALIVE_STATUS_OK; | |
476 | if (mvm->umac_error_event_table) | |
477 | mvm->support_umac_log = true; | |
478 | ||
479 | IWL_DEBUG_FW(mvm, | |
480 | "Alive VER3 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n", | |
481 | le16_to_cpu(palive->status), palive->ver_type, | |
482 | palive->ver_subtype, palive->flags); | |
483 | ||
484 | IWL_DEBUG_FW(mvm, | |
485 | "UMAC version: Major - 0x%x, Minor - 0x%x\n", | |
486 | le32_to_cpu(palive->umac_major), | |
487 | le32_to_cpu(palive->umac_minor)); | |
01a9ca51 | 488 | } |
8ca151b5 JB |
489 | |
490 | return true; | |
491 | } | |
492 | ||
493 | static bool iwl_wait_phy_db_entry(struct iwl_notif_wait_data *notif_wait, | |
494 | struct iwl_rx_packet *pkt, void *data) | |
495 | { | |
496 | struct iwl_phy_db *phy_db = data; | |
497 | ||
498 | if (pkt->hdr.cmd != CALIB_RES_NOTIF_PHY_DB) { | |
499 | WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF); | |
500 | return true; | |
501 | } | |
502 | ||
503 | WARN_ON(iwl_phy_db_set_section(phy_db, pkt, GFP_ATOMIC)); | |
504 | ||
505 | return false; | |
506 | } | |
507 | ||
508 | static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm, | |
509 | enum iwl_ucode_type ucode_type) | |
510 | { | |
511 | struct iwl_notification_wait alive_wait; | |
512 | struct iwl_mvm_alive_data alive_data; | |
513 | const struct fw_img *fw; | |
514 | int ret, i; | |
515 | enum iwl_ucode_type old_type = mvm->cur_ucode; | |
6eb031d2 | 516 | static const u16 alive_cmd[] = { MVM_ALIVE }; |
91479b64 | 517 | struct iwl_sf_region st_fwrd_space; |
8ca151b5 | 518 | |
61df750c | 519 | if (ucode_type == IWL_UCODE_REGULAR && |
d2709ad7 | 520 | iwl_fw_dbg_conf_usniffer(mvm->fw, FW_DBG_START_FROM_ALIVE)) |
61df750c EH |
521 | fw = iwl_get_ucode_image(mvm, IWL_UCODE_REGULAR_USNIFFER); |
522 | else | |
523 | fw = iwl_get_ucode_image(mvm, ucode_type); | |
befe9b6f | 524 | if (WARN_ON(!fw)) |
8ca151b5 | 525 | return -EINVAL; |
befe9b6f JB |
526 | mvm->cur_ucode = ucode_type; |
527 | mvm->ucode_loaded = false; | |
8ca151b5 JB |
528 | |
529 | iwl_init_notification_wait(&mvm->notif_wait, &alive_wait, | |
530 | alive_cmd, ARRAY_SIZE(alive_cmd), | |
531 | iwl_alive_fn, &alive_data); | |
532 | ||
533 | ret = iwl_trans_start_fw(mvm->trans, fw, ucode_type == IWL_UCODE_INIT); | |
534 | if (ret) { | |
535 | mvm->cur_ucode = old_type; | |
536 | iwl_remove_notification(&mvm->notif_wait, &alive_wait); | |
537 | return ret; | |
538 | } | |
539 | ||
540 | /* | |
541 | * Some things may run in the background now, but we | |
542 | * just wait for the ALIVE notification here. | |
543 | */ | |
544 | ret = iwl_wait_notification(&mvm->notif_wait, &alive_wait, | |
545 | MVM_UCODE_ALIVE_TIMEOUT); | |
546 | if (ret) { | |
192de2b4 DS |
547 | if (mvm->trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) |
548 | IWL_ERR(mvm, | |
549 | "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n", | |
550 | iwl_read_prph(mvm->trans, SB_CPU_1_STATUS), | |
551 | iwl_read_prph(mvm->trans, SB_CPU_2_STATUS)); | |
8ca151b5 JB |
552 | mvm->cur_ucode = old_type; |
553 | return ret; | |
554 | } | |
555 | ||
556 | if (!alive_data.valid) { | |
557 | IWL_ERR(mvm, "Loaded ucode is not valid!\n"); | |
558 | mvm->cur_ucode = old_type; | |
559 | return -EIO; | |
560 | } | |
561 | ||
91479b64 EH |
562 | /* |
563 | * update the sdio allocation according to the pointer we get in the | |
564 | * alive notification. | |
565 | */ | |
566 | st_fwrd_space.addr = mvm->sf_space.addr; | |
567 | st_fwrd_space.size = mvm->sf_space.size; | |
568 | ret = iwl_trans_update_sf(mvm->trans, &st_fwrd_space); | |
82e8aea0 ES |
569 | if (ret) { |
570 | IWL_ERR(mvm, "Failed to update SF size. ret %d\n", ret); | |
571 | return ret; | |
572 | } | |
91479b64 | 573 | |
8ca151b5 JB |
574 | iwl_trans_fw_alive(mvm->trans, alive_data.scd_base_addr); |
575 | ||
a6c4fb44 MG |
576 | /* |
577 | * configure and operate fw paging mechanism. | |
578 | * driver configures the paging flow only once, CPU2 paging image | |
579 | * included in the IWL_UCODE_INIT image. | |
580 | */ | |
581 | if (fw->paging_mem_size) { | |
e1120187 MG |
582 | /* |
583 | * When dma is not enabled, the driver needs to copy / write | |
584 | * the downloaded / uploaded page to / from the smem. | |
585 | * This gets the location of the place were the pages are | |
586 | * stored. | |
587 | */ | |
588 | if (!is_device_dma_capable(mvm->trans->dev)) { | |
589 | ret = iwl_trans_get_paging_item(mvm); | |
590 | if (ret) { | |
591 | IWL_ERR(mvm, "failed to get FW paging item\n"); | |
592 | return ret; | |
593 | } | |
594 | } | |
595 | ||
a6c4fb44 MG |
596 | ret = iwl_save_fw_paging(mvm, fw); |
597 | if (ret) { | |
598 | IWL_ERR(mvm, "failed to save the FW paging image\n"); | |
599 | return ret; | |
600 | } | |
601 | ||
602 | ret = iwl_send_paging_cmd(mvm, fw); | |
603 | if (ret) { | |
604 | IWL_ERR(mvm, "failed to send the paging cmd\n"); | |
605 | iwl_free_fw_paging(mvm); | |
606 | return ret; | |
607 | } | |
608 | } | |
609 | ||
8ca151b5 JB |
610 | /* |
611 | * Note: all the queues are enabled as part of the interface | |
612 | * initialization, but in firmware restart scenarios they | |
613 | * could be stopped, so wake them up. In firmware restart, | |
614 | * mac80211 will have the queues stopped as well until the | |
615 | * reconfiguration completes. During normal startup, they | |
616 | * will be empty. | |
617 | */ | |
618 | ||
4ecafae9 LK |
619 | memset(&mvm->queue_info, 0, sizeof(mvm->queue_info)); |
620 | mvm->queue_info[IWL_MVM_CMD_QUEUE].hw_queue_refcount = 1; | |
8ca151b5 | 621 | |
df197c00 JB |
622 | for (i = 0; i < IEEE80211_MAX_QUEUES; i++) |
623 | atomic_set(&mvm->mac80211_queue_stop_count[i], 0); | |
8ca151b5 JB |
624 | |
625 | mvm->ucode_loaded = true; | |
626 | ||
627 | return 0; | |
628 | } | |
8ca151b5 JB |
629 | |
630 | static int iwl_send_phy_cfg_cmd(struct iwl_mvm *mvm) | |
631 | { | |
632 | struct iwl_phy_cfg_cmd phy_cfg_cmd; | |
633 | enum iwl_ucode_type ucode_type = mvm->cur_ucode; | |
634 | ||
635 | /* Set parameters */ | |
a0544272 | 636 | phy_cfg_cmd.phy_cfg = cpu_to_le32(iwl_mvm_get_phy_config(mvm)); |
8ca151b5 JB |
637 | phy_cfg_cmd.calib_control.event_trigger = |
638 | mvm->fw->default_calib[ucode_type].event_trigger; | |
639 | phy_cfg_cmd.calib_control.flow_trigger = | |
640 | mvm->fw->default_calib[ucode_type].flow_trigger; | |
641 | ||
642 | IWL_DEBUG_INFO(mvm, "Sending Phy CFG command: 0x%x\n", | |
643 | phy_cfg_cmd.phy_cfg); | |
644 | ||
a1022927 | 645 | return iwl_mvm_send_cmd_pdu(mvm, PHY_CONFIGURATION_CMD, 0, |
8ca151b5 JB |
646 | sizeof(phy_cfg_cmd), &phy_cfg_cmd); |
647 | } | |
648 | ||
8ca151b5 JB |
649 | int iwl_run_init_mvm_ucode(struct iwl_mvm *mvm, bool read_nvm) |
650 | { | |
651 | struct iwl_notification_wait calib_wait; | |
6eb031d2 | 652 | static const u16 init_complete[] = { |
8ca151b5 JB |
653 | INIT_COMPLETE_NOTIF, |
654 | CALIB_RES_NOTIF_PHY_DB | |
655 | }; | |
656 | int ret; | |
657 | ||
658 | lockdep_assert_held(&mvm->mutex); | |
659 | ||
8d193ca2 | 660 | if (WARN_ON_ONCE(mvm->calibrating)) |
8ca151b5 JB |
661 | return 0; |
662 | ||
663 | iwl_init_notification_wait(&mvm->notif_wait, | |
664 | &calib_wait, | |
665 | init_complete, | |
666 | ARRAY_SIZE(init_complete), | |
667 | iwl_wait_phy_db_entry, | |
668 | mvm->phy_db); | |
669 | ||
670 | /* Will also start the device */ | |
671 | ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_INIT); | |
672 | if (ret) { | |
673 | IWL_ERR(mvm, "Failed to start INIT ucode: %d\n", ret); | |
674 | goto error; | |
675 | } | |
676 | ||
ae397472 | 677 | ret = iwl_send_bt_init_conf(mvm); |
931d4160 EG |
678 | if (ret) |
679 | goto error; | |
680 | ||
81a67e32 | 681 | /* Read the NVM only at driver load time, no need to do this twice */ |
8ca151b5 JB |
682 | if (read_nvm) { |
683 | /* Read nvm */ | |
14b485f0 | 684 | ret = iwl_nvm_init(mvm, true); |
8ca151b5 JB |
685 | if (ret) { |
686 | IWL_ERR(mvm, "Failed to read NVM: %d\n", ret); | |
687 | goto error; | |
688 | } | |
689 | } | |
690 | ||
81a67e32 | 691 | /* In case we read the NVM from external file, load it to the NIC */ |
e02a9d60 | 692 | if (mvm->nvm_file_name) |
81a67e32 EL |
693 | iwl_mvm_load_nvm_to_nic(mvm); |
694 | ||
8ca151b5 JB |
695 | ret = iwl_nvm_check_version(mvm->nvm_data, mvm->trans); |
696 | WARN_ON(ret); | |
697 | ||
4f59334b EH |
698 | /* |
699 | * abort after reading the nvm in case RF Kill is on, we will complete | |
700 | * the init seq later when RF kill will switch to off | |
701 | */ | |
1a3fe0b2 | 702 | if (iwl_mvm_is_radio_hw_killed(mvm)) { |
4f59334b EH |
703 | IWL_DEBUG_RF_KILL(mvm, |
704 | "jump over all phy activities due to RF kill\n"); | |
705 | iwl_remove_notification(&mvm->notif_wait, &calib_wait); | |
a4082843 AN |
706 | ret = 1; |
707 | goto out; | |
4f59334b EH |
708 | } |
709 | ||
31b8b343 EG |
710 | mvm->calibrating = true; |
711 | ||
e07cbb53 | 712 | /* Send TX valid antennas before triggering calibrations */ |
a0544272 | 713 | ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); |
e07cbb53 DS |
714 | if (ret) |
715 | goto error; | |
716 | ||
8ca151b5 JB |
717 | /* |
718 | * Send phy configurations command to init uCode | |
719 | * to start the 16.0 uCode init image internal calibrations. | |
720 | */ | |
721 | ret = iwl_send_phy_cfg_cmd(mvm); | |
722 | if (ret) { | |
723 | IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n", | |
724 | ret); | |
725 | goto error; | |
726 | } | |
727 | ||
728 | /* | |
729 | * Some things may run in the background now, but we | |
730 | * just wait for the calibration complete notification. | |
731 | */ | |
732 | ret = iwl_wait_notification(&mvm->notif_wait, &calib_wait, | |
733 | MVM_UCODE_CALIB_TIMEOUT); | |
31b8b343 | 734 | |
1a3fe0b2 | 735 | if (ret && iwl_mvm_is_radio_hw_killed(mvm)) { |
31b8b343 EG |
736 | IWL_DEBUG_RF_KILL(mvm, "RFKILL while calibrating.\n"); |
737 | ret = 1; | |
738 | } | |
8ca151b5 JB |
739 | goto out; |
740 | ||
741 | error: | |
742 | iwl_remove_notification(&mvm->notif_wait, &calib_wait); | |
743 | out: | |
31b8b343 | 744 | mvm->calibrating = false; |
a4082843 | 745 | if (iwlmvm_mod_params.init_dbg && !mvm->nvm_data) { |
8ca151b5 JB |
746 | /* we want to debug INIT and we have no NVM - fake */ |
747 | mvm->nvm_data = kzalloc(sizeof(struct iwl_nvm_data) + | |
748 | sizeof(struct ieee80211_channel) + | |
749 | sizeof(struct ieee80211_rate), | |
750 | GFP_KERNEL); | |
751 | if (!mvm->nvm_data) | |
752 | return -ENOMEM; | |
8ca151b5 JB |
753 | mvm->nvm_data->bands[0].channels = mvm->nvm_data->channels; |
754 | mvm->nvm_data->bands[0].n_channels = 1; | |
755 | mvm->nvm_data->bands[0].n_bitrates = 1; | |
756 | mvm->nvm_data->bands[0].bitrates = | |
757 | (void *)mvm->nvm_data->channels + 1; | |
758 | mvm->nvm_data->bands[0].bitrates->hw_value = 10; | |
759 | } | |
760 | ||
761 | return ret; | |
762 | } | |
763 | ||
04fd2c28 LK |
764 | static void iwl_mvm_get_shared_mem_conf(struct iwl_mvm *mvm) |
765 | { | |
766 | struct iwl_host_cmd cmd = { | |
767 | .id = SHARED_MEM_CFG, | |
768 | .flags = CMD_WANT_SKB, | |
769 | .data = { NULL, }, | |
770 | .len = { 0, }, | |
771 | }; | |
772 | struct iwl_rx_packet *pkt; | |
773 | struct iwl_shared_mem_cfg *mem_cfg; | |
774 | u32 i; | |
775 | ||
776 | lockdep_assert_held(&mvm->mutex); | |
777 | ||
778 | if (WARN_ON(iwl_mvm_send_cmd(mvm, &cmd))) | |
779 | return; | |
780 | ||
781 | pkt = cmd.resp_pkt; | |
04fd2c28 LK |
782 | mem_cfg = (void *)pkt->data; |
783 | ||
784 | mvm->shared_mem_cfg.shared_mem_addr = | |
785 | le32_to_cpu(mem_cfg->shared_mem_addr); | |
786 | mvm->shared_mem_cfg.shared_mem_size = | |
787 | le32_to_cpu(mem_cfg->shared_mem_size); | |
788 | mvm->shared_mem_cfg.sample_buff_addr = | |
789 | le32_to_cpu(mem_cfg->sample_buff_addr); | |
790 | mvm->shared_mem_cfg.sample_buff_size = | |
791 | le32_to_cpu(mem_cfg->sample_buff_size); | |
792 | mvm->shared_mem_cfg.txfifo_addr = le32_to_cpu(mem_cfg->txfifo_addr); | |
793 | for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.txfifo_size); i++) | |
794 | mvm->shared_mem_cfg.txfifo_size[i] = | |
795 | le32_to_cpu(mem_cfg->txfifo_size[i]); | |
796 | for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.rxfifo_size); i++) | |
797 | mvm->shared_mem_cfg.rxfifo_size[i] = | |
798 | le32_to_cpu(mem_cfg->rxfifo_size[i]); | |
799 | mvm->shared_mem_cfg.page_buff_addr = | |
800 | le32_to_cpu(mem_cfg->page_buff_addr); | |
801 | mvm->shared_mem_cfg.page_buff_size = | |
802 | le32_to_cpu(mem_cfg->page_buff_size); | |
803 | IWL_DEBUG_INFO(mvm, "SHARED MEM CFG: got memory offsets/sizes\n"); | |
804 | ||
04fd2c28 LK |
805 | iwl_free_resp(&cmd); |
806 | } | |
807 | ||
b6eaa45a EG |
808 | int iwl_mvm_fw_dbg_collect_desc(struct iwl_mvm *mvm, |
809 | struct iwl_mvm_dump_desc *desc, | |
36fb9017 | 810 | struct iwl_fw_dbg_trigger_tlv *trigger) |
8c23f95c | 811 | { |
36fb9017 OG |
812 | unsigned int delay = 0; |
813 | ||
814 | if (trigger) | |
815 | delay = msecs_to_jiffies(le32_to_cpu(trigger->stop_delay)); | |
816 | ||
d2709ad7 EG |
817 | if (test_and_set_bit(IWL_MVM_STATUS_DUMPING_FW_LOG, &mvm->status)) |
818 | return -EBUSY; | |
819 | ||
b6eaa45a EG |
820 | if (WARN_ON(mvm->fw_dump_desc)) |
821 | iwl_mvm_free_fw_dump_desc(mvm); | |
822 | ||
823 | IWL_WARN(mvm, "Collecting data: trigger %d fired.\n", | |
824 | le32_to_cpu(desc->trig_desc.type)); | |
825 | ||
826 | mvm->fw_dump_desc = desc; | |
36fb9017 | 827 | mvm->fw_dump_trig = trigger; |
d2709ad7 | 828 | |
d2709ad7 EG |
829 | queue_delayed_work(system_wq, &mvm->fw_dump_wk, delay); |
830 | ||
831 | return 0; | |
832 | } | |
833 | ||
b6eaa45a | 834 | int iwl_mvm_fw_dbg_collect(struct iwl_mvm *mvm, enum iwl_fw_dbg_trigger trig, |
36fb9017 OG |
835 | const char *str, size_t len, |
836 | struct iwl_fw_dbg_trigger_tlv *trigger) | |
b6eaa45a EG |
837 | { |
838 | struct iwl_mvm_dump_desc *desc; | |
839 | ||
840 | desc = kzalloc(sizeof(*desc) + len, GFP_ATOMIC); | |
841 | if (!desc) | |
842 | return -ENOMEM; | |
843 | ||
844 | desc->len = len; | |
845 | desc->trig_desc.type = cpu_to_le32(trig); | |
846 | memcpy(desc->trig_desc.data, str, len); | |
847 | ||
36fb9017 | 848 | return iwl_mvm_fw_dbg_collect_desc(mvm, desc, trigger); |
b6eaa45a EG |
849 | } |
850 | ||
d2709ad7 | 851 | int iwl_mvm_fw_dbg_collect_trig(struct iwl_mvm *mvm, |
b6eaa45a | 852 | struct iwl_fw_dbg_trigger_tlv *trigger, |
5d4f929e | 853 | const char *fmt, ...) |
d2709ad7 | 854 | { |
d2709ad7 | 855 | u16 occurrences = le16_to_cpu(trigger->occurrences); |
5d4f929e JB |
856 | int ret, len = 0; |
857 | char buf[64]; | |
d2709ad7 EG |
858 | |
859 | if (!occurrences) | |
860 | return 0; | |
861 | ||
5d4f929e JB |
862 | if (fmt) { |
863 | va_list ap; | |
864 | ||
865 | buf[sizeof(buf) - 1] = '\0'; | |
866 | ||
867 | va_start(ap, fmt); | |
868 | vsnprintf(buf, sizeof(buf), fmt, ap); | |
869 | va_end(ap); | |
870 | ||
871 | /* check for truncation */ | |
872 | if (WARN_ON_ONCE(buf[sizeof(buf) - 1])) | |
873 | buf[sizeof(buf) - 1] = '\0'; | |
874 | ||
875 | len = strlen(buf) + 1; | |
876 | } | |
877 | ||
36fb9017 OG |
878 | ret = iwl_mvm_fw_dbg_collect(mvm, le32_to_cpu(trigger->id), buf, len, |
879 | trigger); | |
880 | ||
d2709ad7 EG |
881 | if (ret) |
882 | return ret; | |
883 | ||
884 | trigger->occurrences = cpu_to_le16(occurrences - 1); | |
885 | return 0; | |
8c23f95c EG |
886 | } |
887 | ||
945d4202 EG |
888 | static inline void iwl_mvm_restart_early_start(struct iwl_mvm *mvm) |
889 | { | |
890 | if (mvm->cfg->device_family == IWL_DEVICE_FAMILY_7000) | |
891 | iwl_clear_bits_prph(mvm->trans, MON_BUFF_SAMPLE_CTL, 0x100); | |
892 | else | |
893 | iwl_write_prph(mvm->trans, DBGC_IN_SAMPLE, 1); | |
894 | } | |
895 | ||
d2709ad7 | 896 | int iwl_mvm_start_fw_dbg_conf(struct iwl_mvm *mvm, u8 conf_id) |
6a951267 LK |
897 | { |
898 | u8 *ptr; | |
899 | int ret; | |
900 | int i; | |
901 | ||
902 | if (WARN_ONCE(conf_id >= ARRAY_SIZE(mvm->fw->dbg_conf_tlv), | |
903 | "Invalid configuration %d\n", conf_id)) | |
904 | return -EINVAL; | |
905 | ||
945d4202 EG |
906 | /* EARLY START - firmware's configuration is hard coded */ |
907 | if ((!mvm->fw->dbg_conf_tlv[conf_id] || | |
908 | !mvm->fw->dbg_conf_tlv[conf_id]->num_of_hcmds) && | |
909 | conf_id == FW_DBG_START_FROM_ALIVE) { | |
910 | iwl_mvm_restart_early_start(mvm); | |
911 | return 0; | |
912 | } | |
913 | ||
6a951267 LK |
914 | if (!mvm->fw->dbg_conf_tlv[conf_id]) |
915 | return -EINVAL; | |
916 | ||
917 | if (mvm->fw_dbg_conf != FW_DBG_INVALID) | |
918 | IWL_WARN(mvm, "FW already configured (%d) - re-configuring\n", | |
919 | mvm->fw_dbg_conf); | |
920 | ||
921 | /* Send all HCMDs for configuring the FW debug */ | |
922 | ptr = (void *)&mvm->fw->dbg_conf_tlv[conf_id]->hcmd; | |
923 | for (i = 0; i < mvm->fw->dbg_conf_tlv[conf_id]->num_of_hcmds; i++) { | |
924 | struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr; | |
925 | ||
926 | ret = iwl_mvm_send_cmd_pdu(mvm, cmd->id, 0, | |
927 | le16_to_cpu(cmd->len), cmd->data); | |
928 | if (ret) | |
929 | return ret; | |
930 | ||
931 | ptr += sizeof(*cmd); | |
932 | ptr += le16_to_cpu(cmd->len); | |
933 | } | |
934 | ||
935 | mvm->fw_dbg_conf = conf_id; | |
936 | return ret; | |
937 | } | |
938 | ||
84bfffa9 EG |
939 | static int iwl_mvm_config_ltr(struct iwl_mvm *mvm) |
940 | { | |
941 | struct iwl_ltr_config_cmd cmd = { | |
942 | .flags = cpu_to_le32(LTR_CFG_FLAG_FEATURE_ENABLE), | |
943 | }; | |
944 | ||
945 | if (!mvm->trans->ltr_enabled) | |
946 | return 0; | |
947 | ||
84bfffa9 EG |
948 | return iwl_mvm_send_cmd_pdu(mvm, LTR_CONFIG, 0, |
949 | sizeof(cmd), &cmd); | |
950 | } | |
951 | ||
8ca151b5 JB |
952 | int iwl_mvm_up(struct iwl_mvm *mvm) |
953 | { | |
954 | int ret, i; | |
53a9d61e IP |
955 | struct ieee80211_channel *chan; |
956 | struct cfg80211_chan_def chandef; | |
8ca151b5 JB |
957 | |
958 | lockdep_assert_held(&mvm->mutex); | |
959 | ||
960 | ret = iwl_trans_start_hw(mvm->trans); | |
961 | if (ret) | |
962 | return ret; | |
963 | ||
ff116373 EL |
964 | /* |
965 | * If we haven't completed the run of the init ucode during | |
966 | * module loading, load init ucode now | |
967 | * (for example, if we were in RFKILL) | |
968 | */ | |
8d193ca2 EH |
969 | ret = iwl_run_init_mvm_ucode(mvm, false); |
970 | if (ret && !iwlmvm_mod_params.init_dbg) { | |
971 | IWL_ERR(mvm, "Failed to run INIT ucode: %d\n", ret); | |
972 | /* this can't happen */ | |
973 | if (WARN_ON(ret > 0)) | |
974 | ret = -ERFKILL; | |
975 | goto error; | |
976 | } | |
977 | if (!iwlmvm_mod_params.init_dbg) { | |
978 | /* | |
979 | * Stop and start the transport without entering low power | |
980 | * mode. This will save the state of other components on the | |
981 | * device that are triggered by the INIT firwmare (MFUART). | |
982 | */ | |
983 | _iwl_trans_stop_device(mvm->trans, false); | |
d643c432 | 984 | ret = _iwl_trans_start_hw(mvm->trans, false); |
8d193ca2 | 985 | if (ret) |
d643c432 | 986 | goto error; |
8ca151b5 JB |
987 | } |
988 | ||
989 | if (iwlmvm_mod_params.init_dbg) | |
990 | return 0; | |
991 | ||
992 | ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR); | |
993 | if (ret) { | |
994 | IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret); | |
995 | goto error; | |
996 | } | |
997 | ||
6c7d32cf | 998 | iwl_mvm_get_shared_mem_conf(mvm); |
04fd2c28 | 999 | |
1f3b0ff8 LE |
1000 | ret = iwl_mvm_sf_update(mvm, NULL, false); |
1001 | if (ret) | |
1002 | IWL_ERR(mvm, "Failed to initialize Smart Fifo\n"); | |
1003 | ||
6a951267 | 1004 | mvm->fw_dbg_conf = FW_DBG_INVALID; |
945d4202 EG |
1005 | /* if we have a destination, assume EARLY START */ |
1006 | if (mvm->fw->dbg_dest_tlv) | |
1007 | mvm->fw_dbg_conf = FW_DBG_START_FROM_ALIVE; | |
d2709ad7 | 1008 | iwl_mvm_start_fw_dbg_conf(mvm, FW_DBG_START_FROM_ALIVE); |
6a951267 | 1009 | |
a0544272 | 1010 | ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); |
8ca151b5 JB |
1011 | if (ret) |
1012 | goto error; | |
1013 | ||
931d4160 EG |
1014 | ret = iwl_send_bt_init_conf(mvm); |
1015 | if (ret) | |
1016 | goto error; | |
1017 | ||
8ca151b5 JB |
1018 | /* Send phy db control command and then phy db calibration*/ |
1019 | ret = iwl_send_phy_db_data(mvm->phy_db); | |
1020 | if (ret) | |
1021 | goto error; | |
1022 | ||
1023 | ret = iwl_send_phy_cfg_cmd(mvm); | |
1024 | if (ret) | |
1025 | goto error; | |
1026 | ||
1027 | /* init the fw <-> mac80211 STA mapping */ | |
1028 | for (i = 0; i < IWL_MVM_STATION_COUNT; i++) | |
1029 | RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL); | |
1030 | ||
1d3c3f63 AN |
1031 | mvm->tdls_cs.peer.sta_id = IWL_MVM_STATION_COUNT; |
1032 | ||
b2b7875b JB |
1033 | /* reset quota debouncing buffer - 0xff will yield invalid data */ |
1034 | memset(&mvm->last_quota_cmd, 0xff, sizeof(mvm->last_quota_cmd)); | |
1035 | ||
8ca151b5 JB |
1036 | /* Add auxiliary station for scanning */ |
1037 | ret = iwl_mvm_add_aux_sta(mvm); | |
1038 | if (ret) | |
1039 | goto error; | |
1040 | ||
53a9d61e IP |
1041 | /* Add all the PHY contexts */ |
1042 | chan = &mvm->hw->wiphy->bands[IEEE80211_BAND_2GHZ]->channels[0]; | |
1043 | cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_NO_HT); | |
1044 | for (i = 0; i < NUM_PHY_CTX; i++) { | |
1045 | /* | |
1046 | * The channel used here isn't relevant as it's | |
1047 | * going to be overwritten in the other flows. | |
1048 | * For now use the first channel we have. | |
1049 | */ | |
1050 | ret = iwl_mvm_phy_ctxt_add(mvm, &mvm->phy_ctxts[i], | |
1051 | &chandef, 1, 1); | |
1052 | if (ret) | |
1053 | goto error; | |
1054 | } | |
8ca151b5 | 1055 | |
0c0e2c71 IY |
1056 | /* Initialize tx backoffs to the minimal possible */ |
1057 | iwl_mvm_tt_tx_backoff(mvm, 0); | |
1058 | ||
84bfffa9 | 1059 | WARN_ON(iwl_mvm_config_ltr(mvm)); |
9180ac50 | 1060 | |
c1cb92fc | 1061 | ret = iwl_mvm_power_update_device(mvm); |
64b928c4 AB |
1062 | if (ret) |
1063 | goto error; | |
1064 | ||
35af15d1 AN |
1065 | /* |
1066 | * RTNL is not taken during Ct-kill, but we don't need to scan/Tx | |
1067 | * anyway, so don't init MCC. | |
1068 | */ | |
1069 | if (!test_bit(IWL_MVM_STATUS_HW_CTKILL, &mvm->status)) { | |
1070 | ret = iwl_mvm_init_mcc(mvm); | |
1071 | if (ret) | |
1072 | goto error; | |
1073 | } | |
90d4f7db | 1074 | |
859d914c | 1075 | if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_UMAC_SCAN)) { |
d2496221 DS |
1076 | ret = iwl_mvm_config_scan(mvm); |
1077 | if (ret) | |
1078 | goto error; | |
1079 | } | |
1080 | ||
93190fb0 AA |
1081 | if (iwl_mvm_is_csum_supported(mvm) && |
1082 | mvm->cfg->features & NETIF_F_RXCSUM) | |
1083 | iwl_trans_write_prph(mvm->trans, RX_EN_CSUM, 0x3); | |
1084 | ||
7498cf4c EP |
1085 | /* allow FW/transport low power modes if not during restart */ |
1086 | if (!test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status)) | |
1087 | iwl_mvm_unref(mvm, IWL_MVM_REF_UCODE_DOWN); | |
1088 | ||
53a9d61e | 1089 | IWL_DEBUG_INFO(mvm, "RT uCode started.\n"); |
8ca151b5 JB |
1090 | return 0; |
1091 | error: | |
1092 | iwl_trans_stop_device(mvm->trans); | |
1093 | return ret; | |
1094 | } | |
1095 | ||
1096 | int iwl_mvm_load_d3_fw(struct iwl_mvm *mvm) | |
1097 | { | |
1098 | int ret, i; | |
1099 | ||
1100 | lockdep_assert_held(&mvm->mutex); | |
1101 | ||
1102 | ret = iwl_trans_start_hw(mvm->trans); | |
1103 | if (ret) | |
1104 | return ret; | |
1105 | ||
1106 | ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_WOWLAN); | |
1107 | if (ret) { | |
1108 | IWL_ERR(mvm, "Failed to start WoWLAN firmware: %d\n", ret); | |
1109 | goto error; | |
1110 | } | |
1111 | ||
a0544272 | 1112 | ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); |
8ca151b5 JB |
1113 | if (ret) |
1114 | goto error; | |
1115 | ||
1116 | /* Send phy db control command and then phy db calibration*/ | |
1117 | ret = iwl_send_phy_db_data(mvm->phy_db); | |
1118 | if (ret) | |
1119 | goto error; | |
1120 | ||
1121 | ret = iwl_send_phy_cfg_cmd(mvm); | |
1122 | if (ret) | |
1123 | goto error; | |
1124 | ||
1125 | /* init the fw <-> mac80211 STA mapping */ | |
1126 | for (i = 0; i < IWL_MVM_STATION_COUNT; i++) | |
1127 | RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL); | |
1128 | ||
1129 | /* Add auxiliary station for scanning */ | |
1130 | ret = iwl_mvm_add_aux_sta(mvm); | |
1131 | if (ret) | |
1132 | goto error; | |
1133 | ||
1134 | return 0; | |
1135 | error: | |
1136 | iwl_trans_stop_device(mvm->trans); | |
1137 | return ret; | |
1138 | } | |
1139 | ||
0416841d JB |
1140 | void iwl_mvm_rx_card_state_notif(struct iwl_mvm *mvm, |
1141 | struct iwl_rx_cmd_buffer *rxb) | |
8ca151b5 JB |
1142 | { |
1143 | struct iwl_rx_packet *pkt = rxb_addr(rxb); | |
1144 | struct iwl_card_state_notif *card_state_notif = (void *)pkt->data; | |
1145 | u32 flags = le32_to_cpu(card_state_notif->flags); | |
1146 | ||
1147 | IWL_DEBUG_RF_KILL(mvm, "Card state received: HW:%s SW:%s CT:%s\n", | |
1148 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", | |
1149 | (flags & SW_CARD_DISABLED) ? "Kill" : "On", | |
1150 | (flags & CT_KILL_CARD_DISABLED) ? | |
1151 | "Reached" : "Not reached"); | |
8ca151b5 JB |
1152 | } |
1153 | ||
0416841d JB |
1154 | void iwl_mvm_rx_mfuart_notif(struct iwl_mvm *mvm, |
1155 | struct iwl_rx_cmd_buffer *rxb) | |
30269c12 CRI |
1156 | { |
1157 | struct iwl_rx_packet *pkt = rxb_addr(rxb); | |
1158 | struct iwl_mfuart_load_notif *mfuart_notif = (void *)pkt->data; | |
1159 | ||
1160 | IWL_DEBUG_INFO(mvm, | |
1161 | "MFUART: installed ver: 0x%08x, external ver: 0x%08x, status: 0x%08x, duration: 0x%08x\n", | |
1162 | le32_to_cpu(mfuart_notif->installed_ver), | |
1163 | le32_to_cpu(mfuart_notif->external_ver), | |
1164 | le32_to_cpu(mfuart_notif->status), | |
1165 | le32_to_cpu(mfuart_notif->duration)); | |
30269c12 | 1166 | } |