[deliverable/linux.git] / drivers / net / wireless / iwlwifi / pcie / internal.h

/******************************************************************************
 *
 * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
 *
 * Portions of this file are derived from the ipw3945 project, as well
 * as portions of the ieee80211 subsystem header files.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
 *
 * The full GNU General Public License is included in this distribution in the
 * file called LICENSE.
 *
 * Contact Information:
 *  Intel Linux Wireless <ilw@linux.intel.com>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *
 *****************************************************************************/
#ifndef __iwl_trans_int_pcie_h__
#define __iwl_trans_int_pcie_h__

#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/skbuff.h>
#include <linux/wait.h>
#include <linux/pci.h>
#include <linux/timer.h>

#include "iwl-fh.h"
#include "iwl-csr.h"
#include "iwl-trans.h"
#include "iwl-debug.h"
#include "iwl-io.h"
#include "iwl-op-mode.h"

struct iwl_host_cmd;

/*This file includes the declaration that are internal to the
 * trans_pcie layer */

struct iwl_rx_mem_buffer {
	dma_addr_t page_dma;
	struct page *page;
	struct list_head list;
};

/**
 * struct isr_statistics - interrupt statistics
 *
 */
struct isr_statistics {
	u32 hw;
	u32 sw;
	u32 err_code;
	u32 sch;
	u32 alive;
	u32 rfkill;
	u32 ctkill;
	u32 wakeup;
	u32 rx;
	u32 tx;
	u32 unhandled;
};

/**
 * struct iwl_rx_queue - Rx queue
 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
 * @pool:
 * @queue:
 * @read: Shared index to newest available Rx buffer
 * @write: Shared index to oldest written Rx packet
 * @free_count: Number of pre-allocated buffers in rx_free
 * @write_actual:
 * @rx_free: list of free SKBs for use
 * @rx_used: List of Rx buffers with no SKB
 * @need_update: flag to indicate we need to update read/write index
 * @rb_stts: driver's pointer to receive buffer status
 * @rb_stts_dma: bus address of receive buffer status
 * @lock:
 *
 * NOTE:  rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
 */
struct iwl_rx_queue {
	__le32 *bd;
	dma_addr_t bd_dma;
	struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
	struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
	u32 read;
	u32 write;
	u32 free_count;
	u32 write_actual;
	struct list_head rx_free;
	struct list_head rx_used;
	int need_update;
	struct iwl_rb_status *rb_stts;
	dma_addr_t rb_stts_dma;
	spinlock_t lock;
};

struct iwl_dma_ptr {
	dma_addr_t dma;
	void *addr;
	size_t size;
};

/**
 * iwl_queue_inc_wrap - increment queue index, wrap back to beginning
 * @index -- current index
 * @n_bd -- total number of entries in queue (must be power of 2)
 */
static inline int iwl_queue_inc_wrap(int index, int n_bd)
{
	return ++index & (n_bd - 1);
}

/**
 * iwl_queue_dec_wrap - decrement queue index, wrap back to end
 * @index -- current index
 * @n_bd -- total number of entries in queue (must be power of 2)
 */
static inline int iwl_queue_dec_wrap(int index, int n_bd)
{
	return --index & (n_bd - 1);
}

struct iwl_cmd_meta {
	/* only for SYNC commands, iff the reply skb is wanted */
	struct iwl_host_cmd *source;

	DEFINE_DMA_UNMAP_ADDR(mapping);
	DEFINE_DMA_UNMAP_LEN(len);

	u32 flags;
};

/*
 * Generic queue structure
 *
 * Contains common data for Rx and Tx queues.
 *
 * Note the difference between n_bd and n_window: the hardware
 * always assumes 256 descriptors, so n_bd is always 256 (unless
 * there might be HW changes in the future). For the normal TX
 * queues, n_window, which is the size of the software queue data
 * is also 256; however, for the command queue, n_window is only
 * 32 since we don't need so many commands pending. Since the HW
 * still uses 256 BDs for DMA though, n_bd stays 256. As a result,
 * the software buffers (in the variables @meta, @txb in struct
 * iwl_tx_queue) only have 32 entries, while the HW buffers (@tfds
 * in the same struct) have 256.
 * This means that we end up with the following:
 *  HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 |
 *  SW entries:           | 0      | ... | 31          |
 * where N is a number between 0 and 7. This means that the SW
 * data is a window overlayed over the HW queue.
 */
struct iwl_queue {
	int n_bd;              /* number of BDs in this queue */
	int write_ptr;       /* 1-st empty entry (index) host_w*/
	int read_ptr;         /* last used entry (index) host_r*/
	/* use for monitoring and recovering the stuck queue */
	dma_addr_t dma_addr;   /* physical addr for BD's */
	int n_window;	       /* safe queue window */
	u32 id;
	int low_mark;	       /* low watermark, resume queue if free
				* space more than this */
	int high_mark;         /* high watermark, stop queue if free
				* space less than this */
};

#define TFD_TX_CMD_SLOTS 256
#define TFD_CMD_SLOTS 32

struct iwl_pcie_tx_queue_entry {
	struct iwl_device_cmd *cmd;
	struct iwl_device_cmd *copy_cmd;
	struct sk_buff *skb;
	struct iwl_cmd_meta meta;
};

/**
 * struct iwl_tx_queue - Tx Queue for DMA
 * @q: generic Rx/Tx queue descriptor
 * @tfds: transmit frame descriptors (DMA memory)
 * @entries: transmit entries (driver state)
 * @lock: queue lock
 * @stuck_timer: timer that fires if queue gets stuck
 * @trans_pcie: pointer back to transport (for timer)
 * @need_update: indicates need to update read/write index
 * @active: stores if queue is active
 *
 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
 * descriptors) and required locking structures.
 */
struct iwl_tx_queue {
	struct iwl_queue q;
	struct iwl_tfd *tfds;
	struct iwl_pcie_tx_queue_entry *entries;
	spinlock_t lock;
	struct timer_list stuck_timer;
	struct iwl_trans_pcie *trans_pcie;
	u8 need_update;
	u8 active;
};

/**
 * struct iwl_trans_pcie - PCIe transport specific data
 * @rxq: all the RX queue data
 * @rx_replenish: work that will be called when buffers need to be allocated
 * @drv - pointer to iwl_drv
 * @trans: pointer to the generic transport area
 * @irq - the irq number for the device
 * @irq_requested: true when the irq has been requested
 * @scd_base_addr: scheduler sram base address in SRAM
 * @scd_bc_tbls: pointer to the byte count table of the scheduler
 * @kw: keep warm address
 * @pci_dev: basic pci-network driver stuff
 * @hw_base: pci hardware address support
 * @ucode_write_complete: indicates that the ucode has been copied.
 * @ucode_write_waitq: wait queue for uCode load
 * @status - transport specific status flags
 * @cmd_queue - command queue number
 * @rx_buf_size_8k: 8 kB RX buffer size
 * @rx_page_order: page order for receive buffer size
 * @wd_timeout: queue watchdog timeout (jiffies)
 */
struct iwl_trans_pcie {
	struct iwl_rx_queue rxq;
	struct work_struct rx_replenish;
	struct iwl_trans *trans;
	struct iwl_drv *drv;

	/* INT ICT Table */
	__le32 *ict_tbl;
	dma_addr_t ict_tbl_dma;
	int ict_index;
	u32 inta;
	bool use_ict;
	bool irq_requested;
	struct tasklet_struct irq_tasklet;
	struct isr_statistics isr_stats;

	unsigned int irq;
	spinlock_t irq_lock;
	u32 inta_mask;
	u32 scd_base_addr;
	struct iwl_dma_ptr scd_bc_tbls;
	struct iwl_dma_ptr kw;

	struct iwl_tx_queue *txq;
	unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
	unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];

	/* PCI bus related data */
	struct pci_dev *pci_dev;
	void __iomem *hw_base;

	bool ucode_write_complete;
	wait_queue_head_t ucode_write_waitq;
	unsigned long status;
	u8 cmd_queue;
	u8 cmd_fifo;
	u8 n_no_reclaim_cmds;
	u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS];

	bool rx_buf_size_8k;
	u32 rx_page_order;

	const char **command_names;

	/* queue watchdog */
	unsigned long wd_timeout;
};

/*****************************************************
* DRIVER STATUS FUNCTIONS
******************************************************/
#define STATUS_HCMD_ACTIVE	0
#define STATUS_DEVICE_ENABLED	1
#define STATUS_TPOWER_PMI	2
#define STATUS_INT_ENABLED	3

#define IWL_TRANS_GET_PCIE_TRANS(_iwl_trans) \
	((struct iwl_trans_pcie *) ((_iwl_trans)->trans_specific))

static inline struct iwl_trans *
iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie)
{
	return container_of((void *)trans_pcie, struct iwl_trans,
			    trans_specific);
}

struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
				       const struct pci_device_id *ent,
				       const struct iwl_cfg *cfg);
void iwl_trans_pcie_free(struct iwl_trans *trans);

/*****************************************************
* RX
******************************************************/
void iwl_bg_rx_replenish(struct work_struct *data);
void iwl_irq_tasklet(struct iwl_trans *trans);
void iwl_rx_replenish(struct iwl_trans *trans);
void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
				   struct iwl_rx_queue *q);

/*****************************************************
* ICT
******************************************************/
void iwl_reset_ict(struct iwl_trans *trans);
void iwl_disable_ict(struct iwl_trans *trans);
int iwl_alloc_isr_ict(struct iwl_trans *trans);
void iwl_free_isr_ict(struct iwl_trans *trans);
irqreturn_t iwl_isr_ict(int irq, void *data);

/*****************************************************
* TX / HCMD
******************************************************/
void iwl_txq_update_write_ptr(struct iwl_trans *trans,
			      struct iwl_tx_queue *txq);
int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans,
				 struct iwl_tx_queue *txq,
				 dma_addr_t addr, u16 len, u8 reset);
int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id);
int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
void iwl_tx_cmd_complete(struct iwl_trans *trans,
			 struct iwl_rx_cmd_buffer *rxb, int handler_status);
void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
				       struct iwl_tx_queue *txq,
				       u16 byte_cnt);
void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, int fifo,
			       int sta_id, int tid, int frame_limit, u16 ssn);
void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue);
void iwl_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq,
		      enum dma_data_direction dma_dir);
int iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index,
			 struct sk_buff_head *skbs);
int iwl_queue_space(const struct iwl_queue *q);

/*****************************************************
* Error handling
******************************************************/
int iwl_dump_fh(struct iwl_trans *trans, char **buf);
void iwl_dump_csr(struct iwl_trans *trans);

/*****************************************************
* Helpers
******************************************************/
static inline void iwl_disable_interrupts(struct iwl_trans *trans)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);

	/* disable interrupts from uCode/NIC to host */
	iwl_write32(trans, CSR_INT_MASK, 0x00000000);

	/* acknowledge/clear/reset any interrupts still pending
	 * from uCode or flow handler (Rx/Tx DMA) */
	iwl_write32(trans, CSR_INT, 0xffffffff);
	iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff);
	IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
}

static inline void iwl_enable_interrupts(struct iwl_trans *trans)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

	IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
	set_bit(STATUS_INT_ENABLED, &trans_pcie->status);
	iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
}

static inline void iwl_enable_rfkill_int(struct iwl_trans *trans)
{
	IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
	iwl_write32(trans, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
}

static inline void iwl_wake_queue(struct iwl_trans *trans,
				  struct iwl_tx_queue *txq)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

	if (test_and_clear_bit(txq->q.id, trans_pcie->queue_stopped)) {
		IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->q.id);
		iwl_op_mode_queue_not_full(trans->op_mode, txq->q.id);
	}
}

static inline void iwl_stop_queue(struct iwl_trans *trans,
				  struct iwl_tx_queue *txq)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

	if (!test_and_set_bit(txq->q.id, trans_pcie->queue_stopped)) {
		iwl_op_mode_queue_full(trans->op_mode, txq->q.id);
		IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->q.id);
	} else
		IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n",
				    txq->q.id);
}

static inline int iwl_queue_used(const struct iwl_queue *q, int i)
{
	return q->write_ptr >= q->read_ptr ?
		(i >= q->read_ptr && i < q->write_ptr) :
		!(i < q->read_ptr && i >= q->write_ptr);
}

static inline u8 get_cmd_index(struct iwl_queue *q, u32 index)
{
	return index & (q->n_window - 1);
}

static inline const char *
trans_pcie_get_cmd_string(struct iwl_trans_pcie *trans_pcie, u8 cmd)
{
	if (!trans_pcie->command_names || !trans_pcie->command_names[cmd])
		return "UNKNOWN";
	return trans_pcie->command_names[cmd];
}

static inline bool iwl_is_rfkill_set(struct iwl_trans *trans)
{
	return !(iwl_read32(trans, CSR_GP_CNTRL) &
		CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
}

#endif /* __iwl_trans_int_pcie_h__ */
Commit	Line	Data
ab697a9f EG	1	/******************************************************************************
ab697a9f EG	2	*
4e318262	3	* Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
ab697a9f EG	4	*
	5	* Portions of this file are derived from the ipw3945 project, as well
	6	* as portions of the ieee80211 subsystem header files.
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of version 2 of the GNU General Public License as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	15	* more details.
	16	*
	17	* You should have received a copy of the GNU General Public License along with
	18	* this program; if not, write to the Free Software Foundation, Inc.,
	19	* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
	20	*
	21	* The full GNU General Public License is included in this distribution in the
	22	* file called LICENSE.
	23	*
	24	* Contact Information:
	25	* Intel Linux Wireless <ilw@linux.intel.com>
	26	* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	27	*
	28	*****************************************************************************/
	29	#ifndef __iwl_trans_int_pcie_h__
	30	#define __iwl_trans_int_pcie_h__
	31
a72b8b08 EG	32	#include <linux/spinlock.h>
	33	#include <linux/interrupt.h>
	34	#include <linux/skbuff.h>
13df1aab	35	#include <linux/wait.h>
522376d2	36	#include <linux/pci.h>
7c5ba4a8	37	#include <linux/timer.h>
a72b8b08	38
dda61a44	39	#include "iwl-fh.h"
a72b8b08	40	#include "iwl-csr.h"
a72b8b08 EG	41	#include "iwl-trans.h"
	42	#include "iwl-debug.h"
	43	#include "iwl-io.h"
02e38358	44	#include "iwl-op-mode.h"
a72b8b08	45
a72b8b08	46	struct iwl_host_cmd;
dda61a44	47
ab697a9f EG	48	/*This file includes the declaration that are internal to the
	49	* trans_pcie layer */
	50
48a2d66f JB	51	struct iwl_rx_mem_buffer {
	52	dma_addr_t page_dma;
	53	struct page *page;
	54	struct list_head list;
	55	};
	56
1f7b6172 EG	57	/**
	58	* struct isr_statistics - interrupt statistics
	59	*
	60	*/
	61	struct isr_statistics {
	62	u32 hw;
	63	u32 sw;
	64	u32 err_code;
	65	u32 sch;
	66	u32 alive;
	67	u32 rfkill;
	68	u32 ctkill;
	69	u32 wakeup;
	70	u32 rx;
	71	u32 tx;
	72	u32 unhandled;
	73	};
	74
5a878bf6 EG	75	/**
	76	* struct iwl_rx_queue - Rx queue
	77	* @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
	78	* @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
	79	* @pool:
	80	* @queue:
	81	* @read: Shared index to newest available Rx buffer
	82	* @write: Shared index to oldest written Rx packet
	83	* @free_count: Number of pre-allocated buffers in rx_free
	84	* @write_actual:
	85	* @rx_free: list of free SKBs for use
	86	* @rx_used: List of Rx buffers with no SKB
	87	* @need_update: flag to indicate we need to update read/write index
	88	* @rb_stts: driver's pointer to receive buffer status
	89	* @rb_stts_dma: bus address of receive buffer status
	90	* @lock:
	91	*
	92	* NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
	93	*/
	94	struct iwl_rx_queue {
	95	__le32 *bd;
	96	dma_addr_t bd_dma;
	97	struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
	98	struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
	99	u32 read;
	100	u32 write;
	101	u32 free_count;
	102	u32 write_actual;
	103	struct list_head rx_free;
	104	struct list_head rx_used;
	105	int need_update;
	106	struct iwl_rb_status *rb_stts;
	107	dma_addr_t rb_stts_dma;
	108	spinlock_t lock;
	109	};
	110
a72b8b08 EG	111	struct iwl_dma_ptr {
	112	dma_addr_t dma;
	113	void *addr;
	114	size_t size;
	115	};
	116
bffc66ce JB	117	/**
	118	* iwl_queue_inc_wrap - increment queue index, wrap back to beginning
	119	* @index -- current index
	120	* @n_bd -- total number of entries in queue (must be power of 2)
	121	*/
	122	static inline int iwl_queue_inc_wrap(int index, int n_bd)
	123	{
	124	return ++index & (n_bd - 1);
	125	}
	126
	127	/**
	128	* iwl_queue_dec_wrap - decrement queue index, wrap back to end
	129	* @index -- current index
	130	* @n_bd -- total number of entries in queue (must be power of 2)
	131	*/
	132	static inline int iwl_queue_dec_wrap(int index, int n_bd)
	133	{
	134	return --index & (n_bd - 1);
	135	}
	136
522376d2 EG	137	struct iwl_cmd_meta {
	138	/* only for SYNC commands, iff the reply skb is wanted */
	139	struct iwl_host_cmd *source;
522376d2	140
522376d2 EG	141	DEFINE_DMA_UNMAP_ADDR(mapping);
522376d2 EG	142	DEFINE_DMA_UNMAP_LEN(len);
c14c7372 JB	143
c14c7372 JB	144	u32 flags;
522376d2 EG	145	};
	146
	147	/*
	148	* Generic queue structure
	149	*
	150	* Contains common data for Rx and Tx queues.
	151	*
	152	* Note the difference between n_bd and n_window: the hardware
	153	* always assumes 256 descriptors, so n_bd is always 256 (unless
	154	* there might be HW changes in the future). For the normal TX
	155	* queues, n_window, which is the size of the software queue data
	156	* is also 256; however, for the command queue, n_window is only
	157	* 32 since we don't need so many commands pending. Since the HW
	158	* still uses 256 BDs for DMA though, n_bd stays 256. As a result,
	159	* the software buffers (in the variables @meta, @txb in struct
	160	* iwl_tx_queue) only have 32 entries, while the HW buffers (@tfds
	161	* in the same struct) have 256.
	162	* This means that we end up with the following:
	163	* HW entries: \| 0 \| ... \| N * 32 \| ... \| N * 32 + 31 \| ... \| 255 \|
	164	* SW entries: \| 0 \| ... \| 31 \|
	165	* where N is a number between 0 and 7. This means that the SW
	166	* data is a window overlayed over the HW queue.
	167	*/
	168	struct iwl_queue {
	169	int n_bd; /* number of BDs in this queue */
	170	int write_ptr; /* 1-st empty entry (index) host_w*/
	171	int read_ptr; /* last used entry (index) host_r*/
	172	/* use for monitoring and recovering the stuck queue */
	173	dma_addr_t dma_addr; /* physical addr for BD's */
	174	int n_window; /* safe queue window */
	175	u32 id;
	176	int low_mark; /* low watermark, resume queue if free
	177	* space more than this */
	178	int high_mark; /* high watermark, stop queue if free
	179	* space less than this */
	180	};
	181
bf8440e6 JB	182	#define TFD_TX_CMD_SLOTS 256
	183	#define TFD_CMD_SLOTS 32
	184
	185	struct iwl_pcie_tx_queue_entry {
	186	struct iwl_device_cmd *cmd;
96791422	187	struct iwl_device_cmd *copy_cmd;
bf8440e6 JB	188	struct sk_buff *skb;
	189	struct iwl_cmd_meta meta;
	190	};
	191
522376d2 EG	192	/**
	193	* struct iwl_tx_queue - Tx Queue for DMA
	194	* @q: generic Rx/Tx queue descriptor
bf8440e6 JB	195	* @tfds: transmit frame descriptors (DMA memory)
	196	* @entries: transmit entries (driver state)
	197	* @lock: queue lock
	198	* @stuck_timer: timer that fires if queue gets stuck
	199	* @trans_pcie: pointer back to transport (for timer)
522376d2	200	* @need_update: indicates need to update read/write index
bf8440e6	201	* @active: stores if queue is active
522376d2 EG	202	*
	203	* A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
	204	* descriptors) and required locking structures.
	205	*/
522376d2 EG	206	struct iwl_tx_queue {
	207	struct iwl_queue q;
	208	struct iwl_tfd *tfds;
bf8440e6	209	struct iwl_pcie_tx_queue_entry *entries;
015c15e1	210	spinlock_t lock;
7c5ba4a8 JB	211	struct timer_list stuck_timer;
7c5ba4a8 JB	212	struct iwl_trans_pcie *trans_pcie;
522376d2	213	u8 need_update;
522376d2	214	u8 active;
522376d2 EG	215	};
522376d2 EG	216
e6bb4c9c EG	217	/**
e6bb4c9c EG	218	* struct iwl_trans_pcie - PCIe transport specific data
5a878bf6 EG	219	* @rxq: all the RX queue data
5a878bf6 EG	220	* @rx_replenish: work that will be called when buffers need to be allocated
9130bab1	221	* @drv - pointer to iwl_drv
5a878bf6	222	* @trans: pointer to the generic transport area
75595536	223	* @irq - the irq number for the device
57a1dc89	224	* @irq_requested: true when the irq has been requested
105183b1 EG	225	* @scd_base_addr: scheduler sram base address in SRAM
105183b1 EG	226	* @scd_bc_tbls: pointer to the byte count table of the scheduler
9d6b2cb1	227	* @kw: keep warm address
a42a1844 EG	228	* @pci_dev: basic pci-network driver stuff
a42a1844 EG	229	* @hw_base: pci hardware address support
13df1aab JB	230	* @ucode_write_complete: indicates that the ucode has been copied.
13df1aab JB	231	* @ucode_write_waitq: wait queue for uCode load
9a716863	232	* @status - transport specific status flags
c6f600fc	233	* @cmd_queue - command queue number
b2cf410c JB	234	* @rx_buf_size_8k: 8 kB RX buffer size
b2cf410c JB	235	* @rx_page_order: page order for receive buffer size
7c5ba4a8	236	* @wd_timeout: queue watchdog timeout (jiffies)
e6bb4c9c EG	237	*/
e6bb4c9c EG	238	struct iwl_trans_pcie {
5a878bf6 EG	239	struct iwl_rx_queue rxq;
	240	struct work_struct rx_replenish;
	241	struct iwl_trans *trans;
9130bab1	242	struct iwl_drv *drv;
0c325769 EG	243
	244	/* INT ICT Table */
	245	__le32 *ict_tbl;
0c325769	246	dma_addr_t ict_tbl_dma;
0c325769 EG	247	int ict_index;
	248	u32 inta;
	249	bool use_ict;
57a1dc89	250	bool irq_requested;
0c325769	251	struct tasklet_struct irq_tasklet;
1f7b6172	252	struct isr_statistics isr_stats;
0c325769	253
75595536	254	unsigned int irq;
7b11488f	255	spinlock_t irq_lock;
0c325769	256	u32 inta_mask;
105183b1 EG	257	u32 scd_base_addr;
105183b1 EG	258	struct iwl_dma_ptr scd_bc_tbls;
9d6b2cb1	259	struct iwl_dma_ptr kw;
e13c0c59	260
8ad71bef	261	struct iwl_tx_queue *txq;
9eae88fa	262	unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
8ad71bef	263	unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
a42a1844 EG	264
	265	/* PCI bus related data */
	266	struct pci_dev *pci_dev;
	267	void __iomem *hw_base;
13df1aab JB	268
	269	bool ucode_write_complete;
	270	wait_queue_head_t ucode_write_waitq;
9a716863	271	unsigned long status;
c6f600fc	272	u8 cmd_queue;
b04db9ac	273	u8 cmd_fifo;
d663ee73 JB	274	u8 n_no_reclaim_cmds;
d663ee73 JB	275	u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS];
b2cf410c JB	276
	277	bool rx_buf_size_8k;
	278	u32 rx_page_order;
7c5ba4a8	279
d9fb6465	280	const char **command_names;
7c5ba4a8 JB	281
	282	/* queue watchdog */
	283	unsigned long wd_timeout;
e6bb4c9c EG	284	};
e6bb4c9c EG	285
01d651d4 DF	286	/*****************************************************
	287	* DRIVER STATUS FUNCTIONS
	288	******************************************************/
	289	#define STATUS_HCMD_ACTIVE 0
	290	#define STATUS_DEVICE_ENABLED 1
	291	#define STATUS_TPOWER_PMI 2
	292	#define STATUS_INT_ENABLED 3
	293
5a878bf6 EG	294	#define IWL_TRANS_GET_PCIE_TRANS(_iwl_trans) \
	295	((struct iwl_trans_pcie *) ((_iwl_trans)->trans_specific))
	296
7c5ba4a8 JB	297	static inline struct iwl_trans *
	298	iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie)
	299	{
	300	return container_of((void *)trans_pcie, struct iwl_trans,
	301	trans_specific);
	302	}
	303
d1ff5253 JB	304	struct iwl_trans iwl_trans_pcie_alloc(struct pci_dev pdev,
	305	const struct pci_device_id *ent,
	306	const struct iwl_cfg *cfg);
	307	void iwl_trans_pcie_free(struct iwl_trans *trans);
	308
253a634c EG	309	/*****************************************************
	310	* RX
	311	******************************************************/
ab697a9f	312	void iwl_bg_rx_replenish(struct work_struct *data);
0c325769	313	void iwl_irq_tasklet(struct iwl_trans *trans);
358a46d4	314	void iwl_rx_replenish(struct iwl_trans *trans);
5a878bf6	315	void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
20d3b647	316	struct iwl_rx_queue *q);
ab697a9f	317
1a361cd8 EG	318	/*****************************************************
	319	* ICT
	320	******************************************************/
ed6a3803	321	void iwl_reset_ict(struct iwl_trans *trans);
0c325769 EG	322	void iwl_disable_ict(struct iwl_trans *trans);
	323	int iwl_alloc_isr_ict(struct iwl_trans *trans);
	324	void iwl_free_isr_ict(struct iwl_trans *trans);
1a361cd8 EG	325	irqreturn_t iwl_isr_ict(int irq, void *data);
1a361cd8 EG	326
253a634c EG	327	/*****************************************************
	328	* TX / HCMD
	329	******************************************************/
fd656935	330	void iwl_txq_update_write_ptr(struct iwl_trans *trans,
20d3b647	331	struct iwl_tx_queue *txq);
6d8f6eeb	332	int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans,
253a634c EG	333	struct iwl_tx_queue *txq,
253a634c EG	334	dma_addr_t addr, u16 len, u8 reset);
6d8f6eeb EG	335	int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id);
6d8f6eeb EG	336	int iwl_trans_pcie_send_cmd(struct iwl_trans trans, struct iwl_host_cmd cmd);
3e10caeb	337	void iwl_tx_cmd_complete(struct iwl_trans *trans,
48a2d66f	338	struct iwl_rx_cmd_buffer *rxb, int handler_status);
6d8f6eeb	339	void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
20d3b647 JB	340	struct iwl_tx_queue *txq,
20d3b647 JB	341	u16 byte_cnt);
4beaf6c2 EG	342	void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, int fifo,
4beaf6c2 EG	343	int sta_id, int tid, int frame_limit, u16 ssn);
5bf9a89d	344	void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue);
bc2529c3 EG	345	void iwl_txq_free_tfd(struct iwl_trans trans, struct iwl_tx_queue txq,
bc2529c3 EG	346	enum dma_data_direction dma_dir);
464021ff EG	347	int iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index,
464021ff EG	348	struct sk_buff_head *skbs);
8ad71bef	349	int iwl_queue_space(const struct iwl_queue *q);
253a634c	350
7ff94706 EG	351	/*****************************************************
	352	* Error handling
	353	******************************************************/
94543a8d	354	int iwl_dump_fh(struct iwl_trans trans, char *buf);
16db88ba EG	355	void iwl_dump_csr(struct iwl_trans *trans);
16db88ba EG	356
8ad71bef EG	357	/*****************************************************
	358	* Helpers
	359	******************************************************/
0c325769 EG	360	static inline void iwl_disable_interrupts(struct iwl_trans *trans)
0c325769 EG	361	{
83626404 DF	362	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
83626404 DF	363	clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
0c325769 EG	364
0c325769 EG	365	/* disable interrupts from uCode/NIC to host */
1042db2a	366	iwl_write32(trans, CSR_INT_MASK, 0x00000000);
0c325769 EG	367
	368	/* acknowledge/clear/reset any interrupts still pending
	369	* from uCode or flow handler (Rx/Tx DMA) */
1042db2a EG	370	iwl_write32(trans, CSR_INT, 0xffffffff);
1042db2a EG	371	iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff);
0c325769 EG	372	IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
	373	}
	374
	375	static inline void iwl_enable_interrupts(struct iwl_trans *trans)
	376	{
83626404	377	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
0c325769 EG	378
0c325769 EG	379	IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
83626404	380	set_bit(STATUS_INT_ENABLED, &trans_pcie->status);
1042db2a	381	iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
0c325769 EG	382	}
0c325769 EG	383
8722c899 SG	384	static inline void iwl_enable_rfkill_int(struct iwl_trans *trans)
	385	{
	386	IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
	387	iwl_write32(trans, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
	388	}
	389
e20d4341	390	static inline void iwl_wake_queue(struct iwl_trans *trans,
bada991b	391	struct iwl_tx_queue *txq)
e20d4341	392	{
9eae88fa JB	393	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	394
	395	if (test_and_clear_bit(txq->q.id, trans_pcie->queue_stopped)) {
	396	IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->q.id);
	397	iwl_op_mode_queue_not_full(trans->op_mode, txq->q.id);
81a3de1c	398	}
e20d4341 EG	399	}
	400
	401	static inline void iwl_stop_queue(struct iwl_trans *trans,
bada991b	402	struct iwl_tx_queue *txq)
e20d4341	403	{
9eae88fa	404	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
8ad71bef	405
9eae88fa JB	406	if (!test_and_set_bit(txq->q.id, trans_pcie->queue_stopped)) {
	407	iwl_op_mode_queue_full(trans->op_mode, txq->q.id);
	408	IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->q.id);
	409	} else
	410	IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n",
	411	txq->q.id);
8ad71bef EG	412	}
	413
	414	static inline int iwl_queue_used(const struct iwl_queue *q, int i)
	415	{
	416	return q->write_ptr >= q->read_ptr ?
	417	(i >= q->read_ptr && i < q->write_ptr) :
	418	!(i < q->read_ptr && i >= q->write_ptr);
	419	}
	420
	421	static inline u8 get_cmd_index(struct iwl_queue *q, u32 index)
	422	{
	423	return index & (q->n_window - 1);
	424	}
	425
d9fb6465 JB	426	static inline const char *
	427	trans_pcie_get_cmd_string(struct iwl_trans_pcie *trans_pcie, u8 cmd)
	428	{
	429	if (!trans_pcie->command_names \|\| !trans_pcie->command_names[cmd])
	430	return "UNKNOWN";
	431	return trans_pcie->command_names[cmd];
	432	}
	433
8d425517 EG	434	static inline bool iwl_is_rfkill_set(struct iwl_trans *trans)
	435	{
	436	return !(iwl_read32(trans, CSR_GP_CNTRL) &
	437	CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
	438	}
	439
ab697a9f	440	#endif /* __iwl_trans_int_pcie_h__ */