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ab697a9f EG |
1 | /****************************************************************************** |
2 | * | |
fb4961db | 3 | * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved. |
ab697a9f EG |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
25 | * Intel Linux Wireless <ilw@linux.intel.com> | |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
27 | * | |
28 | *****************************************************************************/ | |
29 | #include <linux/sched.h> | |
30 | #include <linux/wait.h> | |
1a361cd8 | 31 | #include <linux/gfp.h> |
ab697a9f | 32 | |
1b29dc94 | 33 | #include "iwl-prph.h" |
ab697a9f | 34 | #include "iwl-io.h" |
6468a01a | 35 | #include "internal.h" |
db70f290 | 36 | #include "iwl-op-mode.h" |
ab697a9f EG |
37 | |
38 | /****************************************************************************** | |
39 | * | |
40 | * RX path functions | |
41 | * | |
42 | ******************************************************************************/ | |
43 | ||
44 | /* | |
45 | * Rx theory of operation | |
46 | * | |
47 | * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs), | |
48 | * each of which point to Receive Buffers to be filled by the NIC. These get | |
49 | * used not only for Rx frames, but for any command response or notification | |
50 | * from the NIC. The driver and NIC manage the Rx buffers by means | |
51 | * of indexes into the circular buffer. | |
52 | * | |
53 | * Rx Queue Indexes | |
54 | * The host/firmware share two index registers for managing the Rx buffers. | |
55 | * | |
56 | * The READ index maps to the first position that the firmware may be writing | |
57 | * to -- the driver can read up to (but not including) this position and get | |
58 | * good data. | |
59 | * The READ index is managed by the firmware once the card is enabled. | |
60 | * | |
61 | * The WRITE index maps to the last position the driver has read from -- the | |
62 | * position preceding WRITE is the last slot the firmware can place a packet. | |
63 | * | |
64 | * The queue is empty (no good data) if WRITE = READ - 1, and is full if | |
65 | * WRITE = READ. | |
66 | * | |
67 | * During initialization, the host sets up the READ queue position to the first | |
68 | * INDEX position, and WRITE to the last (READ - 1 wrapped) | |
69 | * | |
70 | * When the firmware places a packet in a buffer, it will advance the READ index | |
71 | * and fire the RX interrupt. The driver can then query the READ index and | |
72 | * process as many packets as possible, moving the WRITE index forward as it | |
73 | * resets the Rx queue buffers with new memory. | |
74 | * | |
75 | * The management in the driver is as follows: | |
76 | * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When | |
77 | * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled | |
78 | * to replenish the iwl->rxq->rx_free. | |
79 | * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the | |
80 | * iwl->rxq is replenished and the READ INDEX is updated (updating the | |
81 | * 'processed' and 'read' driver indexes as well) | |
82 | * + A received packet is processed and handed to the kernel network stack, | |
83 | * detached from the iwl->rxq. The driver 'processed' index is updated. | |
84 | * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free | |
85 | * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ | |
86 | * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there | |
87 | * were enough free buffers and RX_STALLED is set it is cleared. | |
88 | * | |
89 | * | |
90 | * Driver sequence: | |
91 | * | |
92 | * iwl_rx_queue_alloc() Allocates rx_free | |
93 | * iwl_rx_replenish() Replenishes rx_free list from rx_used, and calls | |
94 | * iwl_rx_queue_restock | |
95 | * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx | |
96 | * queue, updates firmware pointers, and updates | |
97 | * the WRITE index. If insufficient rx_free buffers | |
98 | * are available, schedules iwl_rx_replenish | |
99 | * | |
100 | * -- enable interrupts -- | |
101 | * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the | |
102 | * READ INDEX, detaching the SKB from the pool. | |
103 | * Moves the packet buffer from queue to rx_used. | |
104 | * Calls iwl_rx_queue_restock to refill any empty | |
105 | * slots. | |
106 | * ... | |
107 | * | |
108 | */ | |
109 | ||
110 | /** | |
111 | * iwl_rx_queue_space - Return number of free slots available in queue. | |
112 | */ | |
113 | static int iwl_rx_queue_space(const struct iwl_rx_queue *q) | |
114 | { | |
115 | int s = q->read - q->write; | |
116 | if (s <= 0) | |
117 | s += RX_QUEUE_SIZE; | |
118 | /* keep some buffer to not confuse full and empty queue */ | |
119 | s -= 2; | |
120 | if (s < 0) | |
121 | s = 0; | |
122 | return s; | |
123 | } | |
124 | ||
125 | /** | |
126 | * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue | |
127 | */ | |
5a878bf6 | 128 | void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans, |
20d3b647 | 129 | struct iwl_rx_queue *q) |
ab697a9f EG |
130 | { |
131 | unsigned long flags; | |
132 | u32 reg; | |
133 | ||
134 | spin_lock_irqsave(&q->lock, flags); | |
135 | ||
136 | if (q->need_update == 0) | |
137 | goto exit_unlock; | |
138 | ||
035f7ff2 | 139 | if (trans->cfg->base_params->shadow_reg_enable) { |
ab697a9f EG |
140 | /* shadow register enabled */ |
141 | /* Device expects a multiple of 8 */ | |
142 | q->write_actual = (q->write & ~0x7); | |
1042db2a | 143 | iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, q->write_actual); |
ab697a9f | 144 | } else { |
47107e84 DF |
145 | struct iwl_trans_pcie *trans_pcie = |
146 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
147 | ||
ab697a9f | 148 | /* If power-saving is in use, make sure device is awake */ |
01d651d4 | 149 | if (test_bit(STATUS_TPOWER_PMI, &trans_pcie->status)) { |
1042db2a | 150 | reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); |
ab697a9f EG |
151 | |
152 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
5a878bf6 | 153 | IWL_DEBUG_INFO(trans, |
ab697a9f EG |
154 | "Rx queue requesting wakeup," |
155 | " GP1 = 0x%x\n", reg); | |
1042db2a | 156 | iwl_set_bit(trans, CSR_GP_CNTRL, |
ab697a9f EG |
157 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
158 | goto exit_unlock; | |
159 | } | |
160 | ||
161 | q->write_actual = (q->write & ~0x7); | |
1042db2a | 162 | iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR, |
ab697a9f EG |
163 | q->write_actual); |
164 | ||
165 | /* Else device is assumed to be awake */ | |
166 | } else { | |
167 | /* Device expects a multiple of 8 */ | |
168 | q->write_actual = (q->write & ~0x7); | |
1042db2a | 169 | iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR, |
ab697a9f EG |
170 | q->write_actual); |
171 | } | |
172 | } | |
173 | q->need_update = 0; | |
174 | ||
175 | exit_unlock: | |
176 | spin_unlock_irqrestore(&q->lock, flags); | |
177 | } | |
178 | ||
179 | /** | |
358a46d4 | 180 | * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr |
ab697a9f | 181 | */ |
358a46d4 | 182 | static inline __le32 iwl_dma_addr2rbd_ptr(dma_addr_t dma_addr) |
ab697a9f EG |
183 | { |
184 | return cpu_to_le32((u32)(dma_addr >> 8)); | |
185 | } | |
186 | ||
187 | /** | |
358a46d4 | 188 | * iwl_rx_queue_restock - refill RX queue from pre-allocated pool |
ab697a9f EG |
189 | * |
190 | * If there are slots in the RX queue that need to be restocked, | |
191 | * and we have free pre-allocated buffers, fill the ranks as much | |
192 | * as we can, pulling from rx_free. | |
193 | * | |
194 | * This moves the 'write' index forward to catch up with 'processed', and | |
195 | * also updates the memory address in the firmware to reference the new | |
196 | * target buffer. | |
197 | */ | |
358a46d4 | 198 | static void iwl_rx_queue_restock(struct iwl_trans *trans) |
ab697a9f | 199 | { |
20d3b647 | 200 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
5a878bf6 | 201 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; |
ab697a9f EG |
202 | struct list_head *element; |
203 | struct iwl_rx_mem_buffer *rxb; | |
204 | unsigned long flags; | |
205 | ||
7439046d EG |
206 | /* |
207 | * If the device isn't enabled - not need to try to add buffers... | |
208 | * This can happen when we stop the device and still have an interrupt | |
209 | * pending. We stop the APM before we sync the interrupts / tasklets | |
210 | * because we have to (see comment there). On the other hand, since | |
211 | * the APM is stopped, we cannot access the HW (in particular not prph). | |
212 | * So don't try to restock if the APM has been already stopped. | |
213 | */ | |
214 | if (!test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) | |
215 | return; | |
216 | ||
ab697a9f EG |
217 | spin_lock_irqsave(&rxq->lock, flags); |
218 | while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) { | |
219 | /* The overwritten rxb must be a used one */ | |
220 | rxb = rxq->queue[rxq->write]; | |
221 | BUG_ON(rxb && rxb->page); | |
222 | ||
223 | /* Get next free Rx buffer, remove from free list */ | |
224 | element = rxq->rx_free.next; | |
225 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); | |
226 | list_del(element); | |
227 | ||
228 | /* Point to Rx buffer via next RBD in circular buffer */ | |
358a46d4 | 229 | rxq->bd[rxq->write] = iwl_dma_addr2rbd_ptr(rxb->page_dma); |
ab697a9f EG |
230 | rxq->queue[rxq->write] = rxb; |
231 | rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; | |
232 | rxq->free_count--; | |
233 | } | |
234 | spin_unlock_irqrestore(&rxq->lock, flags); | |
235 | /* If the pre-allocated buffer pool is dropping low, schedule to | |
236 | * refill it */ | |
237 | if (rxq->free_count <= RX_LOW_WATERMARK) | |
1ee158d8 | 238 | schedule_work(&trans_pcie->rx_replenish); |
ab697a9f | 239 | |
ab697a9f EG |
240 | /* If we've added more space for the firmware to place data, tell it. |
241 | * Increment device's write pointer in multiples of 8. */ | |
242 | if (rxq->write_actual != (rxq->write & ~0x7)) { | |
243 | spin_lock_irqsave(&rxq->lock, flags); | |
244 | rxq->need_update = 1; | |
245 | spin_unlock_irqrestore(&rxq->lock, flags); | |
5a878bf6 | 246 | iwl_rx_queue_update_write_ptr(trans, rxq); |
ab697a9f EG |
247 | } |
248 | } | |
249 | ||
358a46d4 EG |
250 | /* |
251 | * iwl_rx_allocate - allocate a page for each used RBD | |
ab697a9f | 252 | * |
358a46d4 EG |
253 | * A used RBD is an Rx buffer that has been given to the stack. To use it again |
254 | * a page must be allocated and the RBD must point to the page. This function | |
255 | * doesn't change the HW pointer but handles the list of pages that is used by | |
256 | * iwl_rx_queue_restock. The latter function will update the HW to use the newly | |
257 | * allocated buffers. | |
ab697a9f | 258 | */ |
358a46d4 | 259 | static void iwl_rx_allocate(struct iwl_trans *trans, gfp_t priority) |
ab697a9f | 260 | { |
20d3b647 | 261 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
5a878bf6 | 262 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; |
ab697a9f EG |
263 | struct list_head *element; |
264 | struct iwl_rx_mem_buffer *rxb; | |
265 | struct page *page; | |
266 | unsigned long flags; | |
267 | gfp_t gfp_mask = priority; | |
268 | ||
269 | while (1) { | |
270 | spin_lock_irqsave(&rxq->lock, flags); | |
271 | if (list_empty(&rxq->rx_used)) { | |
272 | spin_unlock_irqrestore(&rxq->lock, flags); | |
273 | return; | |
274 | } | |
275 | spin_unlock_irqrestore(&rxq->lock, flags); | |
276 | ||
277 | if (rxq->free_count > RX_LOW_WATERMARK) | |
278 | gfp_mask |= __GFP_NOWARN; | |
279 | ||
b2cf410c | 280 | if (trans_pcie->rx_page_order > 0) |
ab697a9f EG |
281 | gfp_mask |= __GFP_COMP; |
282 | ||
283 | /* Alloc a new receive buffer */ | |
20d3b647 | 284 | page = alloc_pages(gfp_mask, trans_pcie->rx_page_order); |
ab697a9f EG |
285 | if (!page) { |
286 | if (net_ratelimit()) | |
5a878bf6 | 287 | IWL_DEBUG_INFO(trans, "alloc_pages failed, " |
d6189124 | 288 | "order: %d\n", |
b2cf410c | 289 | trans_pcie->rx_page_order); |
ab697a9f EG |
290 | |
291 | if ((rxq->free_count <= RX_LOW_WATERMARK) && | |
292 | net_ratelimit()) | |
5a878bf6 | 293 | IWL_CRIT(trans, "Failed to alloc_pages with %s." |
ab697a9f EG |
294 | "Only %u free buffers remaining.\n", |
295 | priority == GFP_ATOMIC ? | |
296 | "GFP_ATOMIC" : "GFP_KERNEL", | |
297 | rxq->free_count); | |
298 | /* We don't reschedule replenish work here -- we will | |
299 | * call the restock method and if it still needs | |
300 | * more buffers it will schedule replenish */ | |
301 | return; | |
302 | } | |
303 | ||
304 | spin_lock_irqsave(&rxq->lock, flags); | |
305 | ||
306 | if (list_empty(&rxq->rx_used)) { | |
307 | spin_unlock_irqrestore(&rxq->lock, flags); | |
b2cf410c | 308 | __free_pages(page, trans_pcie->rx_page_order); |
ab697a9f EG |
309 | return; |
310 | } | |
311 | element = rxq->rx_used.next; | |
312 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); | |
313 | list_del(element); | |
314 | ||
315 | spin_unlock_irqrestore(&rxq->lock, flags); | |
316 | ||
317 | BUG_ON(rxb->page); | |
318 | rxb->page = page; | |
319 | /* Get physical address of the RB */ | |
20d3b647 JB |
320 | rxb->page_dma = |
321 | dma_map_page(trans->dev, page, 0, | |
322 | PAGE_SIZE << trans_pcie->rx_page_order, | |
323 | DMA_FROM_DEVICE); | |
ab697a9f EG |
324 | /* dma address must be no more than 36 bits */ |
325 | BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36)); | |
326 | /* and also 256 byte aligned! */ | |
327 | BUG_ON(rxb->page_dma & DMA_BIT_MASK(8)); | |
328 | ||
329 | spin_lock_irqsave(&rxq->lock, flags); | |
330 | ||
331 | list_add_tail(&rxb->list, &rxq->rx_free); | |
332 | rxq->free_count++; | |
333 | ||
334 | spin_unlock_irqrestore(&rxq->lock, flags); | |
335 | } | |
336 | } | |
337 | ||
358a46d4 EG |
338 | /* |
339 | * iwl_rx_replenish - Move all used buffers from rx_used to rx_free | |
340 | * | |
341 | * When moving to rx_free an page is allocated for the slot. | |
342 | * | |
343 | * Also restock the Rx queue via iwl_rx_queue_restock. | |
344 | * This is called as a scheduled work item (except for during initialization) | |
345 | */ | |
346 | void iwl_rx_replenish(struct iwl_trans *trans) | |
ab697a9f | 347 | { |
7b11488f | 348 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
ab697a9f EG |
349 | unsigned long flags; |
350 | ||
358a46d4 | 351 | iwl_rx_allocate(trans, GFP_KERNEL); |
ab697a9f | 352 | |
7b11488f | 353 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
358a46d4 | 354 | iwl_rx_queue_restock(trans); |
7b11488f | 355 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
ab697a9f EG |
356 | } |
357 | ||
358a46d4 | 358 | static void iwl_rx_replenish_now(struct iwl_trans *trans) |
ab697a9f | 359 | { |
358a46d4 | 360 | iwl_rx_allocate(trans, GFP_ATOMIC); |
ab697a9f | 361 | |
358a46d4 | 362 | iwl_rx_queue_restock(trans); |
ab697a9f EG |
363 | } |
364 | ||
365 | void iwl_bg_rx_replenish(struct work_struct *data) | |
366 | { | |
5a878bf6 EG |
367 | struct iwl_trans_pcie *trans_pcie = |
368 | container_of(data, struct iwl_trans_pcie, rx_replenish); | |
ab697a9f | 369 | |
358a46d4 | 370 | iwl_rx_replenish(trans_pcie->trans); |
ab697a9f EG |
371 | } |
372 | ||
df2f3216 JB |
373 | static void iwl_rx_handle_rxbuf(struct iwl_trans *trans, |
374 | struct iwl_rx_mem_buffer *rxb) | |
375 | { | |
376 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
377 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
c6f600fc | 378 | struct iwl_tx_queue *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
df2f3216 | 379 | unsigned long flags; |
0c19744c | 380 | bool page_stolen = false; |
b2cf410c | 381 | int max_len = PAGE_SIZE << trans_pcie->rx_page_order; |
0c19744c | 382 | u32 offset = 0; |
df2f3216 JB |
383 | |
384 | if (WARN_ON(!rxb)) | |
385 | return; | |
386 | ||
0c19744c JB |
387 | dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE); |
388 | ||
389 | while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) { | |
390 | struct iwl_rx_packet *pkt; | |
391 | struct iwl_device_cmd *cmd; | |
392 | u16 sequence; | |
393 | bool reclaim; | |
394 | int index, cmd_index, err, len; | |
395 | struct iwl_rx_cmd_buffer rxcb = { | |
396 | ._offset = offset, | |
397 | ._page = rxb->page, | |
398 | ._page_stolen = false, | |
0d6c4a2e | 399 | .truesize = max_len, |
0c19744c JB |
400 | }; |
401 | ||
402 | pkt = rxb_addr(&rxcb); | |
403 | ||
404 | if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID)) | |
405 | break; | |
406 | ||
407 | IWL_DEBUG_RX(trans, "cmd at offset %d: %s (0x%.2x)\n", | |
d9fb6465 JB |
408 | rxcb._offset, |
409 | trans_pcie_get_cmd_string(trans_pcie, pkt->hdr.cmd), | |
410 | pkt->hdr.cmd); | |
0c19744c JB |
411 | |
412 | len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; | |
413 | len += sizeof(u32); /* account for status word */ | |
f042c2eb JB |
414 | trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len); |
415 | trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len); | |
0c19744c JB |
416 | |
417 | /* Reclaim a command buffer only if this packet is a response | |
418 | * to a (driver-originated) command. | |
419 | * If the packet (e.g. Rx frame) originated from uCode, | |
420 | * there is no command buffer to reclaim. | |
421 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
422 | * but apparently a few don't get set; catch them here. */ | |
423 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME); | |
424 | if (reclaim) { | |
425 | int i; | |
426 | ||
427 | for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) { | |
428 | if (trans_pcie->no_reclaim_cmds[i] == | |
429 | pkt->hdr.cmd) { | |
430 | reclaim = false; | |
431 | break; | |
432 | } | |
d663ee73 JB |
433 | } |
434 | } | |
df2f3216 | 435 | |
0c19744c JB |
436 | sequence = le16_to_cpu(pkt->hdr.sequence); |
437 | index = SEQ_TO_INDEX(sequence); | |
438 | cmd_index = get_cmd_index(&txq->q, index); | |
439 | ||
96791422 EG |
440 | if (reclaim) { |
441 | struct iwl_pcie_tx_queue_entry *ent; | |
442 | ent = &txq->entries[cmd_index]; | |
443 | cmd = ent->copy_cmd; | |
444 | WARN_ON_ONCE(!cmd && ent->meta.flags & CMD_WANT_HCMD); | |
445 | } else { | |
0c19744c | 446 | cmd = NULL; |
96791422 | 447 | } |
0c19744c JB |
448 | |
449 | err = iwl_op_mode_rx(trans->op_mode, &rxcb, cmd); | |
450 | ||
96791422 EG |
451 | if (reclaim) { |
452 | /* The original command isn't needed any more */ | |
453 | kfree(txq->entries[cmd_index].copy_cmd); | |
454 | txq->entries[cmd_index].copy_cmd = NULL; | |
f4feb8ac JB |
455 | /* nor is the duplicated part of the command */ |
456 | kfree(txq->entries[cmd_index].free_buf); | |
457 | txq->entries[cmd_index].free_buf = NULL; | |
96791422 EG |
458 | } |
459 | ||
0c19744c JB |
460 | /* |
461 | * After here, we should always check rxcb._page_stolen, | |
462 | * if it is true then one of the handlers took the page. | |
463 | */ | |
464 | ||
465 | if (reclaim) { | |
466 | /* Invoke any callbacks, transfer the buffer to caller, | |
467 | * and fire off the (possibly) blocking | |
468 | * iwl_trans_send_cmd() | |
469 | * as we reclaim the driver command queue */ | |
470 | if (!rxcb._page_stolen) | |
471 | iwl_tx_cmd_complete(trans, &rxcb, err); | |
472 | else | |
473 | IWL_WARN(trans, "Claim null rxb?\n"); | |
474 | } | |
475 | ||
476 | page_stolen |= rxcb._page_stolen; | |
477 | offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN); | |
df2f3216 JB |
478 | } |
479 | ||
0c19744c JB |
480 | /* page was stolen from us -- free our reference */ |
481 | if (page_stolen) { | |
b2cf410c | 482 | __free_pages(rxb->page, trans_pcie->rx_page_order); |
df2f3216 | 483 | rxb->page = NULL; |
0c19744c | 484 | } |
df2f3216 JB |
485 | |
486 | /* Reuse the page if possible. For notification packets and | |
487 | * SKBs that fail to Rx correctly, add them back into the | |
488 | * rx_free list for reuse later. */ | |
489 | spin_lock_irqsave(&rxq->lock, flags); | |
490 | if (rxb->page != NULL) { | |
491 | rxb->page_dma = | |
492 | dma_map_page(trans->dev, rxb->page, 0, | |
20d3b647 JB |
493 | PAGE_SIZE << trans_pcie->rx_page_order, |
494 | DMA_FROM_DEVICE); | |
df2f3216 JB |
495 | list_add_tail(&rxb->list, &rxq->rx_free); |
496 | rxq->free_count++; | |
497 | } else | |
498 | list_add_tail(&rxb->list, &rxq->rx_used); | |
499 | spin_unlock_irqrestore(&rxq->lock, flags); | |
500 | } | |
501 | ||
ab697a9f EG |
502 | /** |
503 | * iwl_rx_handle - Main entry function for receiving responses from uCode | |
504 | * | |
505 | * Uses the priv->rx_handlers callback function array to invoke | |
506 | * the appropriate handlers, including command responses, | |
507 | * frame-received notifications, and other notifications. | |
508 | */ | |
5a878bf6 | 509 | static void iwl_rx_handle(struct iwl_trans *trans) |
ab697a9f | 510 | { |
df2f3216 | 511 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
5a878bf6 | 512 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; |
ab697a9f | 513 | u32 r, i; |
ab697a9f EG |
514 | u8 fill_rx = 0; |
515 | u32 count = 8; | |
516 | int total_empty; | |
517 | ||
518 | /* uCode's read index (stored in shared DRAM) indicates the last Rx | |
519 | * buffer that the driver may process (last buffer filled by ucode). */ | |
520 | r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; | |
521 | i = rxq->read; | |
522 | ||
523 | /* Rx interrupt, but nothing sent from uCode */ | |
524 | if (i == r) | |
726f23fd | 525 | IWL_DEBUG_RX(trans, "HW = SW = %d\n", r); |
ab697a9f EG |
526 | |
527 | /* calculate total frames need to be restock after handling RX */ | |
528 | total_empty = r - rxq->write_actual; | |
529 | if (total_empty < 0) | |
530 | total_empty += RX_QUEUE_SIZE; | |
531 | ||
532 | if (total_empty > (RX_QUEUE_SIZE / 2)) | |
533 | fill_rx = 1; | |
534 | ||
535 | while (i != r) { | |
48a2d66f | 536 | struct iwl_rx_mem_buffer *rxb; |
ab697a9f EG |
537 | |
538 | rxb = rxq->queue[i]; | |
ab697a9f EG |
539 | rxq->queue[i] = NULL; |
540 | ||
726f23fd EG |
541 | IWL_DEBUG_RX(trans, "rxbuf: HW = %d, SW = %d (%p)\n", |
542 | r, i, rxb); | |
df2f3216 | 543 | iwl_rx_handle_rxbuf(trans, rxb); |
ab697a9f EG |
544 | |
545 | i = (i + 1) & RX_QUEUE_MASK; | |
546 | /* If there are a lot of unused frames, | |
547 | * restock the Rx queue so ucode wont assert. */ | |
548 | if (fill_rx) { | |
549 | count++; | |
550 | if (count >= 8) { | |
551 | rxq->read = i; | |
358a46d4 | 552 | iwl_rx_replenish_now(trans); |
ab697a9f EG |
553 | count = 0; |
554 | } | |
555 | } | |
556 | } | |
557 | ||
558 | /* Backtrack one entry */ | |
559 | rxq->read = i; | |
560 | if (fill_rx) | |
358a46d4 | 561 | iwl_rx_replenish_now(trans); |
ab697a9f | 562 | else |
358a46d4 | 563 | iwl_rx_queue_restock(trans); |
ab697a9f EG |
564 | } |
565 | ||
7ff94706 EG |
566 | /** |
567 | * iwl_irq_handle_error - called for HW or SW error interrupt from card | |
568 | */ | |
6bb78847 | 569 | static void iwl_irq_handle_error(struct iwl_trans *trans) |
7ff94706 | 570 | { |
f946b529 EG |
571 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
572 | ||
7ff94706 | 573 | /* W/A for WiFi/WiMAX coex and WiMAX own the RF */ |
035f7ff2 | 574 | if (trans->cfg->internal_wimax_coex && |
1042db2a | 575 | (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) & |
20d3b647 | 576 | APMS_CLK_VAL_MRB_FUNC_MODE) || |
1042db2a | 577 | (iwl_read_prph(trans, APMG_PS_CTRL_REG) & |
20d3b647 | 578 | APMG_PS_CTRL_VAL_RESET_REQ))) { |
74fda971 | 579 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); |
8a8bbdb4 | 580 | iwl_op_mode_wimax_active(trans->op_mode); |
f946b529 | 581 | wake_up(&trans_pcie->wait_command_queue); |
7ff94706 EG |
582 | return; |
583 | } | |
584 | ||
6bb78847 | 585 | iwl_dump_csr(trans); |
94543a8d | 586 | iwl_dump_fh(trans, NULL); |
7ff94706 | 587 | |
f946b529 EG |
588 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); |
589 | wake_up(&trans_pcie->wait_command_queue); | |
590 | ||
bcb9321c | 591 | iwl_op_mode_nic_error(trans->op_mode); |
7ff94706 EG |
592 | } |
593 | ||
ab697a9f | 594 | /* tasklet for iwlagn interrupt */ |
0c325769 | 595 | void iwl_irq_tasklet(struct iwl_trans *trans) |
ab697a9f | 596 | { |
20d3b647 JB |
597 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
598 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; | |
ab697a9f EG |
599 | u32 inta = 0; |
600 | u32 handled = 0; | |
601 | unsigned long flags; | |
602 | u32 i; | |
603 | #ifdef CONFIG_IWLWIFI_DEBUG | |
604 | u32 inta_mask; | |
605 | #endif | |
606 | ||
7b11488f | 607 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
ab697a9f EG |
608 | |
609 | /* Ack/clear/reset pending uCode interrupts. | |
610 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
611 | */ | |
612 | /* There is a hardware bug in the interrupt mask function that some | |
613 | * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if | |
614 | * they are disabled in the CSR_INT_MASK register. Furthermore the | |
615 | * ICT interrupt handling mechanism has another bug that might cause | |
616 | * these unmasked interrupts fail to be detected. We workaround the | |
617 | * hardware bugs here by ACKing all the possible interrupts so that | |
618 | * interrupt coalescing can still be achieved. | |
619 | */ | |
1042db2a | 620 | iwl_write32(trans, CSR_INT, |
20d3b647 | 621 | trans_pcie->inta | ~trans_pcie->inta_mask); |
ab697a9f | 622 | |
0c325769 | 623 | inta = trans_pcie->inta; |
ab697a9f EG |
624 | |
625 | #ifdef CONFIG_IWLWIFI_DEBUG | |
a8bceb39 | 626 | if (iwl_have_debug_level(IWL_DL_ISR)) { |
ab697a9f | 627 | /* just for debug */ |
1042db2a | 628 | inta_mask = iwl_read32(trans, CSR_INT_MASK); |
0ca24daf | 629 | IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n", |
20d3b647 | 630 | inta, inta_mask); |
ab697a9f EG |
631 | } |
632 | #endif | |
633 | ||
0c325769 EG |
634 | /* saved interrupt in inta variable now we can reset trans_pcie->inta */ |
635 | trans_pcie->inta = 0; | |
ab697a9f | 636 | |
7b11488f | 637 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
b49ba04a | 638 | |
ab697a9f EG |
639 | /* Now service all interrupt bits discovered above. */ |
640 | if (inta & CSR_INT_BIT_HW_ERR) { | |
0c325769 | 641 | IWL_ERR(trans, "Hardware error detected. Restarting.\n"); |
ab697a9f EG |
642 | |
643 | /* Tell the device to stop sending interrupts */ | |
0c325769 | 644 | iwl_disable_interrupts(trans); |
ab697a9f | 645 | |
1f7b6172 | 646 | isr_stats->hw++; |
6bb78847 | 647 | iwl_irq_handle_error(trans); |
ab697a9f EG |
648 | |
649 | handled |= CSR_INT_BIT_HW_ERR; | |
650 | ||
651 | return; | |
652 | } | |
653 | ||
654 | #ifdef CONFIG_IWLWIFI_DEBUG | |
a8bceb39 | 655 | if (iwl_have_debug_level(IWL_DL_ISR)) { |
ab697a9f EG |
656 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
657 | if (inta & CSR_INT_BIT_SCD) { | |
0c325769 | 658 | IWL_DEBUG_ISR(trans, "Scheduler finished to transmit " |
ab697a9f | 659 | "the frame/frames.\n"); |
1f7b6172 | 660 | isr_stats->sch++; |
ab697a9f EG |
661 | } |
662 | ||
663 | /* Alive notification via Rx interrupt will do the real work */ | |
664 | if (inta & CSR_INT_BIT_ALIVE) { | |
0c325769 | 665 | IWL_DEBUG_ISR(trans, "Alive interrupt\n"); |
1f7b6172 | 666 | isr_stats->alive++; |
ab697a9f EG |
667 | } |
668 | } | |
669 | #endif | |
670 | /* Safely ignore these bits for debug checks below */ | |
671 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); | |
672 | ||
673 | /* HW RF KILL switch toggled */ | |
674 | if (inta & CSR_INT_BIT_RF_KILL) { | |
c9eec95c | 675 | bool hw_rfkill; |
ab697a9f | 676 | |
8d425517 | 677 | hw_rfkill = iwl_is_rfkill_set(trans); |
0c325769 | 678 | IWL_WARN(trans, "RF_KILL bit toggled to %s.\n", |
20d3b647 | 679 | hw_rfkill ? "disable radio" : "enable radio"); |
ab697a9f | 680 | |
1f7b6172 | 681 | isr_stats->rfkill++; |
ab697a9f | 682 | |
c9eec95c | 683 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); |
f946b529 EG |
684 | if (hw_rfkill) { |
685 | set_bit(STATUS_RFKILL, &trans_pcie->status); | |
686 | if (test_and_clear_bit(STATUS_HCMD_ACTIVE, | |
687 | &trans_pcie->status)) | |
688 | IWL_DEBUG_RF_KILL(trans, | |
689 | "Rfkill while SYNC HCMD in flight\n"); | |
690 | wake_up(&trans_pcie->wait_command_queue); | |
691 | } else { | |
692 | clear_bit(STATUS_RFKILL, &trans_pcie->status); | |
693 | } | |
ab697a9f EG |
694 | |
695 | handled |= CSR_INT_BIT_RF_KILL; | |
696 | } | |
697 | ||
698 | /* Chip got too hot and stopped itself */ | |
699 | if (inta & CSR_INT_BIT_CT_KILL) { | |
0c325769 | 700 | IWL_ERR(trans, "Microcode CT kill error detected.\n"); |
1f7b6172 | 701 | isr_stats->ctkill++; |
ab697a9f EG |
702 | handled |= CSR_INT_BIT_CT_KILL; |
703 | } | |
704 | ||
705 | /* Error detected by uCode */ | |
706 | if (inta & CSR_INT_BIT_SW_ERR) { | |
0c325769 | 707 | IWL_ERR(trans, "Microcode SW error detected. " |
ab697a9f | 708 | " Restarting 0x%X.\n", inta); |
1f7b6172 | 709 | isr_stats->sw++; |
6bb78847 | 710 | iwl_irq_handle_error(trans); |
ab697a9f EG |
711 | handled |= CSR_INT_BIT_SW_ERR; |
712 | } | |
713 | ||
714 | /* uCode wakes up after power-down sleep */ | |
715 | if (inta & CSR_INT_BIT_WAKEUP) { | |
0c325769 EG |
716 | IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); |
717 | iwl_rx_queue_update_write_ptr(trans, &trans_pcie->rxq); | |
035f7ff2 | 718 | for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) |
fd656935 | 719 | iwl_txq_update_write_ptr(trans, |
8ad71bef | 720 | &trans_pcie->txq[i]); |
ab697a9f | 721 | |
1f7b6172 | 722 | isr_stats->wakeup++; |
ab697a9f EG |
723 | |
724 | handled |= CSR_INT_BIT_WAKEUP; | |
725 | } | |
726 | ||
727 | /* All uCode command responses, including Tx command responses, | |
728 | * Rx "responses" (frame-received notification), and other | |
729 | * notifications from uCode come through here*/ | |
730 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | | |
20d3b647 | 731 | CSR_INT_BIT_RX_PERIODIC)) { |
0c325769 | 732 | IWL_DEBUG_ISR(trans, "Rx interrupt\n"); |
ab697a9f EG |
733 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { |
734 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); | |
1042db2a | 735 | iwl_write32(trans, CSR_FH_INT_STATUS, |
ab697a9f EG |
736 | CSR_FH_INT_RX_MASK); |
737 | } | |
738 | if (inta & CSR_INT_BIT_RX_PERIODIC) { | |
739 | handled |= CSR_INT_BIT_RX_PERIODIC; | |
1042db2a | 740 | iwl_write32(trans, |
0c325769 | 741 | CSR_INT, CSR_INT_BIT_RX_PERIODIC); |
ab697a9f EG |
742 | } |
743 | /* Sending RX interrupt require many steps to be done in the | |
744 | * the device: | |
745 | * 1- write interrupt to current index in ICT table. | |
746 | * 2- dma RX frame. | |
747 | * 3- update RX shared data to indicate last write index. | |
748 | * 4- send interrupt. | |
749 | * This could lead to RX race, driver could receive RX interrupt | |
750 | * but the shared data changes does not reflect this; | |
751 | * periodic interrupt will detect any dangling Rx activity. | |
752 | */ | |
753 | ||
754 | /* Disable periodic interrupt; we use it as just a one-shot. */ | |
1042db2a | 755 | iwl_write8(trans, CSR_INT_PERIODIC_REG, |
ab697a9f | 756 | CSR_INT_PERIODIC_DIS); |
6379103e | 757 | |
0c325769 | 758 | iwl_rx_handle(trans); |
6379103e | 759 | |
ab697a9f EG |
760 | /* |
761 | * Enable periodic interrupt in 8 msec only if we received | |
762 | * real RX interrupt (instead of just periodic int), to catch | |
763 | * any dangling Rx interrupt. If it was just the periodic | |
764 | * interrupt, there was no dangling Rx activity, and no need | |
765 | * to extend the periodic interrupt; one-shot is enough. | |
766 | */ | |
767 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) | |
1042db2a | 768 | iwl_write8(trans, CSR_INT_PERIODIC_REG, |
20d3b647 | 769 | CSR_INT_PERIODIC_ENA); |
ab697a9f | 770 | |
1f7b6172 | 771 | isr_stats->rx++; |
ab697a9f EG |
772 | } |
773 | ||
774 | /* This "Tx" DMA channel is used only for loading uCode */ | |
775 | if (inta & CSR_INT_BIT_FH_TX) { | |
1042db2a | 776 | iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK); |
0c325769 | 777 | IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); |
1f7b6172 | 778 | isr_stats->tx++; |
ab697a9f EG |
779 | handled |= CSR_INT_BIT_FH_TX; |
780 | /* Wake up uCode load routine, now that load is complete */ | |
13df1aab JB |
781 | trans_pcie->ucode_write_complete = true; |
782 | wake_up(&trans_pcie->ucode_write_waitq); | |
ab697a9f EG |
783 | } |
784 | ||
785 | if (inta & ~handled) { | |
0c325769 | 786 | IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled); |
1f7b6172 | 787 | isr_stats->unhandled++; |
ab697a9f EG |
788 | } |
789 | ||
0c325769 EG |
790 | if (inta & ~(trans_pcie->inta_mask)) { |
791 | IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n", | |
792 | inta & ~trans_pcie->inta_mask); | |
ab697a9f EG |
793 | } |
794 | ||
795 | /* Re-enable all interrupts */ | |
796 | /* only Re-enable if disabled by irq */ | |
83626404 | 797 | if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status)) |
0c325769 | 798 | iwl_enable_interrupts(trans); |
ab697a9f | 799 | /* Re-enable RF_KILL if it occurred */ |
8722c899 SG |
800 | else if (handled & CSR_INT_BIT_RF_KILL) |
801 | iwl_enable_rfkill_int(trans); | |
ab697a9f EG |
802 | } |
803 | ||
1a361cd8 EG |
804 | /****************************************************************************** |
805 | * | |
806 | * ICT functions | |
807 | * | |
808 | ******************************************************************************/ | |
10667136 JB |
809 | |
810 | /* a device (PCI-E) page is 4096 bytes long */ | |
811 | #define ICT_SHIFT 12 | |
812 | #define ICT_SIZE (1 << ICT_SHIFT) | |
813 | #define ICT_COUNT (ICT_SIZE / sizeof(u32)) | |
1a361cd8 EG |
814 | |
815 | /* Free dram table */ | |
0c325769 | 816 | void iwl_free_isr_ict(struct iwl_trans *trans) |
1a361cd8 | 817 | { |
20d3b647 | 818 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
0c325769 | 819 | |
10667136 | 820 | if (trans_pcie->ict_tbl) { |
1042db2a | 821 | dma_free_coherent(trans->dev, ICT_SIZE, |
10667136 | 822 | trans_pcie->ict_tbl, |
0c325769 | 823 | trans_pcie->ict_tbl_dma); |
10667136 JB |
824 | trans_pcie->ict_tbl = NULL; |
825 | trans_pcie->ict_tbl_dma = 0; | |
1a361cd8 EG |
826 | } |
827 | } | |
828 | ||
829 | ||
10667136 JB |
830 | /* |
831 | * allocate dram shared table, it is an aligned memory | |
832 | * block of ICT_SIZE. | |
1a361cd8 EG |
833 | * also reset all data related to ICT table interrupt. |
834 | */ | |
0c325769 | 835 | int iwl_alloc_isr_ict(struct iwl_trans *trans) |
1a361cd8 | 836 | { |
20d3b647 | 837 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1a361cd8 | 838 | |
10667136 | 839 | trans_pcie->ict_tbl = |
1042db2a | 840 | dma_alloc_coherent(trans->dev, ICT_SIZE, |
10667136 JB |
841 | &trans_pcie->ict_tbl_dma, |
842 | GFP_KERNEL); | |
843 | if (!trans_pcie->ict_tbl) | |
1a361cd8 EG |
844 | return -ENOMEM; |
845 | ||
10667136 JB |
846 | /* just an API sanity check ... it is guaranteed to be aligned */ |
847 | if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) { | |
848 | iwl_free_isr_ict(trans); | |
849 | return -EINVAL; | |
850 | } | |
1a361cd8 | 851 | |
10667136 JB |
852 | IWL_DEBUG_ISR(trans, "ict dma addr %Lx\n", |
853 | (unsigned long long)trans_pcie->ict_tbl_dma); | |
1a361cd8 | 854 | |
10667136 | 855 | IWL_DEBUG_ISR(trans, "ict vir addr %p\n", trans_pcie->ict_tbl); |
1a361cd8 EG |
856 | |
857 | /* reset table and index to all 0 */ | |
10667136 | 858 | memset(trans_pcie->ict_tbl, 0, ICT_SIZE); |
0c325769 | 859 | trans_pcie->ict_index = 0; |
1a361cd8 EG |
860 | |
861 | /* add periodic RX interrupt */ | |
0c325769 | 862 | trans_pcie->inta_mask |= CSR_INT_BIT_RX_PERIODIC; |
1a361cd8 EG |
863 | return 0; |
864 | } | |
865 | ||
866 | /* Device is going up inform it about using ICT interrupt table, | |
867 | * also we need to tell the driver to start using ICT interrupt. | |
868 | */ | |
ed6a3803 | 869 | void iwl_reset_ict(struct iwl_trans *trans) |
1a361cd8 | 870 | { |
20d3b647 | 871 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1a361cd8 EG |
872 | u32 val; |
873 | unsigned long flags; | |
874 | ||
10667136 | 875 | if (!trans_pcie->ict_tbl) |
ed6a3803 | 876 | return; |
1a361cd8 | 877 | |
7b11488f | 878 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
0c325769 | 879 | iwl_disable_interrupts(trans); |
1a361cd8 | 880 | |
10667136 | 881 | memset(trans_pcie->ict_tbl, 0, ICT_SIZE); |
1a361cd8 | 882 | |
10667136 | 883 | val = trans_pcie->ict_tbl_dma >> ICT_SHIFT; |
1a361cd8 EG |
884 | |
885 | val |= CSR_DRAM_INT_TBL_ENABLE; | |
886 | val |= CSR_DRAM_INIT_TBL_WRAP_CHECK; | |
887 | ||
10667136 | 888 | IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val); |
1a361cd8 | 889 | |
1042db2a | 890 | iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val); |
0c325769 EG |
891 | trans_pcie->use_ict = true; |
892 | trans_pcie->ict_index = 0; | |
1042db2a | 893 | iwl_write32(trans, CSR_INT, trans_pcie->inta_mask); |
0c325769 | 894 | iwl_enable_interrupts(trans); |
7b11488f | 895 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
1a361cd8 EG |
896 | } |
897 | ||
898 | /* Device is going down disable ict interrupt usage */ | |
0c325769 | 899 | void iwl_disable_ict(struct iwl_trans *trans) |
1a361cd8 | 900 | { |
20d3b647 | 901 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1a361cd8 EG |
902 | unsigned long flags; |
903 | ||
7b11488f | 904 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
0c325769 | 905 | trans_pcie->use_ict = false; |
7b11488f | 906 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
1a361cd8 EG |
907 | } |
908 | ||
eb647644 | 909 | /* legacy (non-ICT) ISR. Assumes that trans_pcie->irq_lock is held */ |
1a361cd8 EG |
910 | static irqreturn_t iwl_isr(int irq, void *data) |
911 | { | |
0c325769 | 912 | struct iwl_trans *trans = data; |
eb647644 | 913 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1a361cd8 | 914 | u32 inta, inta_mask; |
1a361cd8 EG |
915 | #ifdef CONFIG_IWLWIFI_DEBUG |
916 | u32 inta_fh; | |
917 | #endif | |
eb647644 EG |
918 | |
919 | lockdep_assert_held(&trans_pcie->irq_lock); | |
920 | ||
6c1011e1 | 921 | trace_iwlwifi_dev_irq(trans->dev); |
b80667ee | 922 | |
1a361cd8 EG |
923 | /* Disable (but don't clear!) interrupts here to avoid |
924 | * back-to-back ISRs and sporadic interrupts from our NIC. | |
925 | * If we have something to service, the tasklet will re-enable ints. | |
926 | * If we *don't* have something, we'll re-enable before leaving here. */ | |
1042db2a EG |
927 | inta_mask = iwl_read32(trans, CSR_INT_MASK); /* just for debug */ |
928 | iwl_write32(trans, CSR_INT_MASK, 0x00000000); | |
1a361cd8 EG |
929 | |
930 | /* Discover which interrupts are active/pending */ | |
1042db2a | 931 | inta = iwl_read32(trans, CSR_INT); |
1a361cd8 EG |
932 | |
933 | /* Ignore interrupt if there's nothing in NIC to service. | |
934 | * This may be due to IRQ shared with another device, | |
935 | * or due to sporadic interrupts thrown from our NIC. */ | |
936 | if (!inta) { | |
0c325769 | 937 | IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); |
1a361cd8 EG |
938 | goto none; |
939 | } | |
940 | ||
941 | if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { | |
942 | /* Hardware disappeared. It might have already raised | |
943 | * an interrupt */ | |
0c325769 | 944 | IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta); |
eb647644 | 945 | return IRQ_HANDLED; |
1a361cd8 EG |
946 | } |
947 | ||
948 | #ifdef CONFIG_IWLWIFI_DEBUG | |
a8bceb39 | 949 | if (iwl_have_debug_level(IWL_DL_ISR)) { |
1042db2a | 950 | inta_fh = iwl_read32(trans, CSR_FH_INT_STATUS); |
0c325769 | 951 | IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x, " |
1a361cd8 EG |
952 | "fh 0x%08x\n", inta, inta_mask, inta_fh); |
953 | } | |
954 | #endif | |
955 | ||
0c325769 | 956 | trans_pcie->inta |= inta; |
1a361cd8 EG |
957 | /* iwl_irq_tasklet() will service interrupts and re-enable them */ |
958 | if (likely(inta)) | |
0c325769 | 959 | tasklet_schedule(&trans_pcie->irq_tasklet); |
83626404 | 960 | else if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) && |
20d3b647 | 961 | !trans_pcie->inta) |
0c325769 | 962 | iwl_enable_interrupts(trans); |
1a361cd8 | 963 | |
eb647644 | 964 | none: |
1a361cd8 EG |
965 | /* re-enable interrupts here since we don't have anything to service. */ |
966 | /* only Re-enable if disabled by irq and no schedules tasklet. */ | |
83626404 | 967 | if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) && |
20d3b647 | 968 | !trans_pcie->inta) |
0c325769 | 969 | iwl_enable_interrupts(trans); |
1a361cd8 | 970 | |
1a361cd8 EG |
971 | return IRQ_NONE; |
972 | } | |
973 | ||
974 | /* interrupt handler using ict table, with this interrupt driver will | |
975 | * stop using INTA register to get device's interrupt, reading this register | |
976 | * is expensive, device will write interrupts in ICT dram table, increment | |
977 | * index then will fire interrupt to driver, driver will OR all ICT table | |
978 | * entries from current index up to table entry with 0 value. the result is | |
979 | * the interrupt we need to service, driver will set the entries back to 0 and | |
980 | * set index. | |
981 | */ | |
982 | irqreturn_t iwl_isr_ict(int irq, void *data) | |
983 | { | |
0c325769 EG |
984 | struct iwl_trans *trans = data; |
985 | struct iwl_trans_pcie *trans_pcie; | |
1a361cd8 EG |
986 | u32 inta, inta_mask; |
987 | u32 val = 0; | |
b80667ee | 988 | u32 read; |
1a361cd8 EG |
989 | unsigned long flags; |
990 | ||
0c325769 | 991 | if (!trans) |
1a361cd8 EG |
992 | return IRQ_NONE; |
993 | ||
0c325769 EG |
994 | trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
995 | ||
eb647644 EG |
996 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
997 | ||
1a361cd8 EG |
998 | /* dram interrupt table not set yet, |
999 | * use legacy interrupt. | |
1000 | */ | |
eb647644 EG |
1001 | if (unlikely(!trans_pcie->use_ict)) { |
1002 | irqreturn_t ret = iwl_isr(irq, data); | |
1003 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); | |
1004 | return ret; | |
1005 | } | |
1a361cd8 | 1006 | |
6c1011e1 | 1007 | trace_iwlwifi_dev_irq(trans->dev); |
b80667ee | 1008 | |
1a361cd8 EG |
1009 | |
1010 | /* Disable (but don't clear!) interrupts here to avoid | |
1011 | * back-to-back ISRs and sporadic interrupts from our NIC. | |
1012 | * If we have something to service, the tasklet will re-enable ints. | |
1013 | * If we *don't* have something, we'll re-enable before leaving here. | |
1014 | */ | |
1042db2a EG |
1015 | inta_mask = iwl_read32(trans, CSR_INT_MASK); /* just for debug */ |
1016 | iwl_write32(trans, CSR_INT_MASK, 0x00000000); | |
1a361cd8 EG |
1017 | |
1018 | ||
1019 | /* Ignore interrupt if there's nothing in NIC to service. | |
1020 | * This may be due to IRQ shared with another device, | |
1021 | * or due to sporadic interrupts thrown from our NIC. */ | |
b80667ee | 1022 | read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); |
6c1011e1 | 1023 | trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read); |
b80667ee | 1024 | if (!read) { |
0c325769 | 1025 | IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); |
1a361cd8 EG |
1026 | goto none; |
1027 | } | |
1028 | ||
b80667ee JB |
1029 | /* |
1030 | * Collect all entries up to the first 0, starting from ict_index; | |
1031 | * note we already read at ict_index. | |
1032 | */ | |
1033 | do { | |
1034 | val |= read; | |
0c325769 | 1035 | IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n", |
b80667ee | 1036 | trans_pcie->ict_index, read); |
0c325769 EG |
1037 | trans_pcie->ict_tbl[trans_pcie->ict_index] = 0; |
1038 | trans_pcie->ict_index = | |
1039 | iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT); | |
1a361cd8 | 1040 | |
b80667ee | 1041 | read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); |
6c1011e1 | 1042 | trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, |
b80667ee JB |
1043 | read); |
1044 | } while (read); | |
1a361cd8 EG |
1045 | |
1046 | /* We should not get this value, just ignore it. */ | |
1047 | if (val == 0xffffffff) | |
1048 | val = 0; | |
1049 | ||
1050 | /* | |
1051 | * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit | |
1052 | * (bit 15 before shifting it to 31) to clear when using interrupt | |
1053 | * coalescing. fortunately, bits 18 and 19 stay set when this happens | |
1054 | * so we use them to decide on the real state of the Rx bit. | |
1055 | * In order words, bit 15 is set if bit 18 or bit 19 are set. | |
1056 | */ | |
1057 | if (val & 0xC0000) | |
1058 | val |= 0x8000; | |
1059 | ||
1060 | inta = (0xff & val) | ((0xff00 & val) << 16); | |
0c325769 | 1061 | IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n", |
20d3b647 | 1062 | inta, inta_mask, val); |
1a361cd8 | 1063 | |
0c325769 EG |
1064 | inta &= trans_pcie->inta_mask; |
1065 | trans_pcie->inta |= inta; | |
1a361cd8 EG |
1066 | |
1067 | /* iwl_irq_tasklet() will service interrupts and re-enable them */ | |
1068 | if (likely(inta)) | |
0c325769 | 1069 | tasklet_schedule(&trans_pcie->irq_tasklet); |
83626404 | 1070 | else if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) && |
b80667ee | 1071 | !trans_pcie->inta) { |
1a361cd8 EG |
1072 | /* Allow interrupt if was disabled by this handler and |
1073 | * no tasklet was schedules, We should not enable interrupt, | |
1074 | * tasklet will enable it. | |
1075 | */ | |
0c325769 | 1076 | iwl_enable_interrupts(trans); |
1a361cd8 EG |
1077 | } |
1078 | ||
7b11488f | 1079 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
1a361cd8 EG |
1080 | return IRQ_HANDLED; |
1081 | ||
1082 | none: | |
1083 | /* re-enable interrupts here since we don't have anything to service. | |
1084 | * only Re-enable if disabled by irq. | |
1085 | */ | |
83626404 | 1086 | if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) && |
b80667ee | 1087 | !trans_pcie->inta) |
0c325769 | 1088 | iwl_enable_interrupts(trans); |
1a361cd8 | 1089 | |
7b11488f | 1090 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
1a361cd8 EG |
1091 | return IRQ_NONE; |
1092 | } |