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c85eb619 EG |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
4e318262 | 8 | * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved. |
c85eb619 EG |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
22 | * USA | |
23 | * | |
24 | * The full GNU General Public License is included in this distribution | |
25 | * in the file called LICENSE.GPL. | |
26 | * | |
27 | * Contact Information: | |
28 | * Intel Linux Wireless <ilw@linux.intel.com> | |
29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
30 | * | |
31 | * BSD LICENSE | |
32 | * | |
4e318262 | 33 | * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved. |
c85eb619 EG |
34 | * All rights reserved. |
35 | * | |
36 | * Redistribution and use in source and binary forms, with or without | |
37 | * modification, are permitted provided that the following conditions | |
38 | * are met: | |
39 | * | |
40 | * * Redistributions of source code must retain the above copyright | |
41 | * notice, this list of conditions and the following disclaimer. | |
42 | * * Redistributions in binary form must reproduce the above copyright | |
43 | * notice, this list of conditions and the following disclaimer in | |
44 | * the documentation and/or other materials provided with the | |
45 | * distribution. | |
46 | * * Neither the name Intel Corporation nor the names of its | |
47 | * contributors may be used to endorse or promote products derived | |
48 | * from this software without specific prior written permission. | |
49 | * | |
50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
61 | * | |
62 | *****************************************************************************/ | |
a42a1844 EG |
63 | #include <linux/pci.h> |
64 | #include <linux/pci-aspm.h> | |
e6bb4c9c | 65 | #include <linux/interrupt.h> |
87e5666c | 66 | #include <linux/debugfs.h> |
cf614297 | 67 | #include <linux/sched.h> |
6d8f6eeb EG |
68 | #include <linux/bitops.h> |
69 | #include <linux/gfp.h> | |
e6bb4c9c | 70 | |
82575102 | 71 | #include "iwl-drv.h" |
c85eb619 | 72 | #include "iwl-trans.h" |
522376d2 EG |
73 | #include "iwl-csr.h" |
74 | #include "iwl-prph.h" | |
7a10e3e4 | 75 | #include "iwl-agn-hw.h" |
6468a01a | 76 | #include "internal.h" |
6238b008 | 77 | /* FIXME: need to abstract out TX command (once we know what it looks like) */ |
1023fdc4 | 78 | #include "dvm/commands.h" |
c85eb619 | 79 | |
c6f600fc | 80 | #define SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie) \ |
035f7ff2 | 81 | (((1<<trans->cfg->base_params->num_of_queues) - 1) &\ |
c6f600fc MV |
82 | (~(1<<(trans_pcie)->cmd_queue))) |
83 | ||
5a878bf6 | 84 | static int iwl_trans_rx_alloc(struct iwl_trans *trans) |
c85eb619 | 85 | { |
20d3b647 | 86 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
5a878bf6 | 87 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; |
1042db2a | 88 | struct device *dev = trans->dev; |
c85eb619 | 89 | |
5a878bf6 | 90 | memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq)); |
c85eb619 EG |
91 | |
92 | spin_lock_init(&rxq->lock); | |
c85eb619 EG |
93 | |
94 | if (WARN_ON(rxq->bd || rxq->rb_stts)) | |
95 | return -EINVAL; | |
96 | ||
97 | /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */ | |
84c816da DH |
98 | rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE, |
99 | &rxq->bd_dma, GFP_KERNEL); | |
c85eb619 EG |
100 | if (!rxq->bd) |
101 | goto err_bd; | |
c85eb619 EG |
102 | |
103 | /*Allocate the driver's pointer to receive buffer status */ | |
84c816da DH |
104 | rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts), |
105 | &rxq->rb_stts_dma, GFP_KERNEL); | |
c85eb619 EG |
106 | if (!rxq->rb_stts) |
107 | goto err_rb_stts; | |
c85eb619 EG |
108 | |
109 | return 0; | |
110 | ||
111 | err_rb_stts: | |
a0f6b0a2 | 112 | dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE, |
20d3b647 | 113 | rxq->bd, rxq->bd_dma); |
c85eb619 EG |
114 | memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma)); |
115 | rxq->bd = NULL; | |
116 | err_bd: | |
117 | return -ENOMEM; | |
118 | } | |
119 | ||
5a878bf6 | 120 | static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans) |
c85eb619 | 121 | { |
20d3b647 | 122 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
5a878bf6 | 123 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; |
a0f6b0a2 | 124 | int i; |
c85eb619 EG |
125 | |
126 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
127 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { | |
128 | /* In the reset function, these buffers may have been allocated | |
129 | * to an SKB, so we need to unmap and free potential storage */ | |
130 | if (rxq->pool[i].page != NULL) { | |
1042db2a | 131 | dma_unmap_page(trans->dev, rxq->pool[i].page_dma, |
20d3b647 JB |
132 | PAGE_SIZE << trans_pcie->rx_page_order, |
133 | DMA_FROM_DEVICE); | |
790428b6 | 134 | __free_pages(rxq->pool[i].page, |
b2cf410c | 135 | trans_pcie->rx_page_order); |
c85eb619 EG |
136 | rxq->pool[i].page = NULL; |
137 | } | |
138 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
139 | } | |
a0f6b0a2 EG |
140 | } |
141 | ||
fd656935 | 142 | static void iwl_trans_rx_hw_init(struct iwl_trans *trans, |
ab697a9f EG |
143 | struct iwl_rx_queue *rxq) |
144 | { | |
b2cf410c | 145 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
ab697a9f EG |
146 | u32 rb_size; |
147 | const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ | |
c17d0681 | 148 | u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */ |
ab697a9f | 149 | |
b2cf410c | 150 | if (trans_pcie->rx_buf_size_8k) |
ab697a9f EG |
151 | rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; |
152 | else | |
153 | rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; | |
154 | ||
155 | /* Stop Rx DMA */ | |
1042db2a | 156 | iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); |
ab697a9f EG |
157 | |
158 | /* Reset driver's Rx queue write index */ | |
1042db2a | 159 | iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); |
ab697a9f EG |
160 | |
161 | /* Tell device where to find RBD circular buffer in DRAM */ | |
1042db2a | 162 | iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG, |
ab697a9f EG |
163 | (u32)(rxq->bd_dma >> 8)); |
164 | ||
165 | /* Tell device where in DRAM to update its Rx status */ | |
1042db2a | 166 | iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG, |
ab697a9f EG |
167 | rxq->rb_stts_dma >> 4); |
168 | ||
169 | /* Enable Rx DMA | |
170 | * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in | |
171 | * the credit mechanism in 5000 HW RX FIFO | |
172 | * Direct rx interrupts to hosts | |
173 | * Rx buffer size 4 or 8k | |
174 | * RB timeout 0x10 | |
175 | * 256 RBDs | |
176 | */ | |
1042db2a | 177 | iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, |
ab697a9f EG |
178 | FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | |
179 | FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | | |
180 | FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | | |
ab697a9f EG |
181 | rb_size| |
182 | (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)| | |
183 | (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); | |
184 | ||
185 | /* Set interrupt coalescing timer to default (2048 usecs) */ | |
1042db2a | 186 | iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); |
ab697a9f EG |
187 | } |
188 | ||
5a878bf6 | 189 | static int iwl_rx_init(struct iwl_trans *trans) |
a0f6b0a2 | 190 | { |
20d3b647 | 191 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
5a878bf6 EG |
192 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; |
193 | ||
a0f6b0a2 EG |
194 | int i, err; |
195 | unsigned long flags; | |
196 | ||
197 | if (!rxq->bd) { | |
5a878bf6 | 198 | err = iwl_trans_rx_alloc(trans); |
a0f6b0a2 EG |
199 | if (err) |
200 | return err; | |
201 | } | |
202 | ||
203 | spin_lock_irqsave(&rxq->lock, flags); | |
204 | INIT_LIST_HEAD(&rxq->rx_free); | |
205 | INIT_LIST_HEAD(&rxq->rx_used); | |
206 | ||
5a878bf6 | 207 | iwl_trans_rxq_free_rx_bufs(trans); |
c85eb619 EG |
208 | |
209 | for (i = 0; i < RX_QUEUE_SIZE; i++) | |
210 | rxq->queue[i] = NULL; | |
211 | ||
212 | /* Set us so that we have processed and used all buffers, but have | |
213 | * not restocked the Rx queue with fresh buffers */ | |
214 | rxq->read = rxq->write = 0; | |
215 | rxq->write_actual = 0; | |
216 | rxq->free_count = 0; | |
217 | spin_unlock_irqrestore(&rxq->lock, flags); | |
218 | ||
5a878bf6 | 219 | iwlagn_rx_replenish(trans); |
ab697a9f | 220 | |
fd656935 | 221 | iwl_trans_rx_hw_init(trans, rxq); |
ab697a9f | 222 | |
7b11488f | 223 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
ab697a9f | 224 | rxq->need_update = 1; |
5a878bf6 | 225 | iwl_rx_queue_update_write_ptr(trans, rxq); |
7b11488f | 226 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
ab697a9f | 227 | |
c85eb619 EG |
228 | return 0; |
229 | } | |
230 | ||
5a878bf6 | 231 | static void iwl_trans_pcie_rx_free(struct iwl_trans *trans) |
a0f6b0a2 | 232 | { |
20d3b647 | 233 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
5a878bf6 | 234 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; |
a0f6b0a2 EG |
235 | unsigned long flags; |
236 | ||
237 | /*if rxq->bd is NULL, it means that nothing has been allocated, | |
238 | * exit now */ | |
239 | if (!rxq->bd) { | |
5a878bf6 | 240 | IWL_DEBUG_INFO(trans, "Free NULL rx context\n"); |
a0f6b0a2 EG |
241 | return; |
242 | } | |
243 | ||
244 | spin_lock_irqsave(&rxq->lock, flags); | |
5a878bf6 | 245 | iwl_trans_rxq_free_rx_bufs(trans); |
a0f6b0a2 EG |
246 | spin_unlock_irqrestore(&rxq->lock, flags); |
247 | ||
1042db2a | 248 | dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE, |
a0f6b0a2 EG |
249 | rxq->bd, rxq->bd_dma); |
250 | memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma)); | |
251 | rxq->bd = NULL; | |
252 | ||
253 | if (rxq->rb_stts) | |
1042db2a | 254 | dma_free_coherent(trans->dev, |
a0f6b0a2 EG |
255 | sizeof(struct iwl_rb_status), |
256 | rxq->rb_stts, rxq->rb_stts_dma); | |
257 | else | |
5a878bf6 | 258 | IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n"); |
a0f6b0a2 EG |
259 | memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma)); |
260 | rxq->rb_stts = NULL; | |
261 | } | |
262 | ||
6d8f6eeb | 263 | static int iwl_trans_rx_stop(struct iwl_trans *trans) |
c2c52e8b EG |
264 | { |
265 | ||
266 | /* stop Rx DMA */ | |
1042db2a EG |
267 | iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); |
268 | return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG, | |
20d3b647 | 269 | FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000); |
c2c52e8b EG |
270 | } |
271 | ||
20d3b647 JB |
272 | static int iwlagn_alloc_dma_ptr(struct iwl_trans *trans, |
273 | struct iwl_dma_ptr *ptr, size_t size) | |
02aca585 EG |
274 | { |
275 | if (WARN_ON(ptr->addr)) | |
276 | return -EINVAL; | |
277 | ||
1042db2a | 278 | ptr->addr = dma_alloc_coherent(trans->dev, size, |
02aca585 EG |
279 | &ptr->dma, GFP_KERNEL); |
280 | if (!ptr->addr) | |
281 | return -ENOMEM; | |
282 | ptr->size = size; | |
283 | return 0; | |
284 | } | |
285 | ||
20d3b647 JB |
286 | static void iwlagn_free_dma_ptr(struct iwl_trans *trans, |
287 | struct iwl_dma_ptr *ptr) | |
1359ca4f EG |
288 | { |
289 | if (unlikely(!ptr->addr)) | |
290 | return; | |
291 | ||
1042db2a | 292 | dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma); |
1359ca4f EG |
293 | memset(ptr, 0, sizeof(*ptr)); |
294 | } | |
295 | ||
7c5ba4a8 JB |
296 | static void iwl_trans_pcie_queue_stuck_timer(unsigned long data) |
297 | { | |
298 | struct iwl_tx_queue *txq = (void *)data; | |
299 | struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; | |
300 | struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie); | |
301 | ||
302 | spin_lock(&txq->lock); | |
303 | /* check if triggered erroneously */ | |
304 | if (txq->q.read_ptr == txq->q.write_ptr) { | |
305 | spin_unlock(&txq->lock); | |
306 | return; | |
307 | } | |
308 | spin_unlock(&txq->lock); | |
309 | ||
310 | ||
311 | IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id, | |
312 | jiffies_to_msecs(trans_pcie->wd_timeout)); | |
313 | IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", | |
314 | txq->q.read_ptr, txq->q.write_ptr); | |
315 | IWL_ERR(trans, "Current HW read_ptr %d write_ptr %d\n", | |
316 | iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq->q.id)) | |
317 | & (TFD_QUEUE_SIZE_MAX - 1), | |
318 | iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq->q.id))); | |
319 | ||
320 | iwl_op_mode_nic_error(trans->op_mode); | |
321 | } | |
322 | ||
6d8f6eeb | 323 | static int iwl_trans_txq_alloc(struct iwl_trans *trans, |
20d3b647 JB |
324 | struct iwl_tx_queue *txq, int slots_num, |
325 | u32 txq_id) | |
02aca585 | 326 | { |
20d3b647 | 327 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
ab9e212e | 328 | size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX; |
02aca585 EG |
329 | int i; |
330 | ||
bf8440e6 | 331 | if (WARN_ON(txq->entries || txq->tfds)) |
02aca585 EG |
332 | return -EINVAL; |
333 | ||
7c5ba4a8 JB |
334 | setup_timer(&txq->stuck_timer, iwl_trans_pcie_queue_stuck_timer, |
335 | (unsigned long)txq); | |
336 | txq->trans_pcie = trans_pcie; | |
337 | ||
1359ca4f EG |
338 | txq->q.n_window = slots_num; |
339 | ||
bf8440e6 JB |
340 | txq->entries = kcalloc(slots_num, |
341 | sizeof(struct iwl_pcie_tx_queue_entry), | |
342 | GFP_KERNEL); | |
02aca585 | 343 | |
bf8440e6 | 344 | if (!txq->entries) |
02aca585 EG |
345 | goto error; |
346 | ||
c6f600fc | 347 | if (txq_id == trans_pcie->cmd_queue) |
dfa2bdba | 348 | for (i = 0; i < slots_num; i++) { |
bf8440e6 JB |
349 | txq->entries[i].cmd = |
350 | kmalloc(sizeof(struct iwl_device_cmd), | |
351 | GFP_KERNEL); | |
352 | if (!txq->entries[i].cmd) | |
dfa2bdba EG |
353 | goto error; |
354 | } | |
02aca585 | 355 | |
02aca585 EG |
356 | /* Circular buffer of transmit frame descriptors (TFDs), |
357 | * shared with device */ | |
1042db2a | 358 | txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz, |
6d8f6eeb | 359 | &txq->q.dma_addr, GFP_KERNEL); |
02aca585 | 360 | if (!txq->tfds) { |
6d8f6eeb | 361 | IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz); |
02aca585 EG |
362 | goto error; |
363 | } | |
364 | txq->q.id = txq_id; | |
365 | ||
366 | return 0; | |
367 | error: | |
bf8440e6 | 368 | if (txq->entries && txq_id == trans_pcie->cmd_queue) |
02aca585 | 369 | for (i = 0; i < slots_num; i++) |
bf8440e6 JB |
370 | kfree(txq->entries[i].cmd); |
371 | kfree(txq->entries); | |
372 | txq->entries = NULL; | |
02aca585 EG |
373 | |
374 | return -ENOMEM; | |
375 | ||
376 | } | |
377 | ||
6d8f6eeb | 378 | static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq, |
9eae88fa | 379 | int slots_num, u32 txq_id) |
02aca585 EG |
380 | { |
381 | int ret; | |
382 | ||
383 | txq->need_update = 0; | |
02aca585 | 384 | |
02aca585 EG |
385 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise |
386 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ | |
387 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); | |
388 | ||
389 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
6d8f6eeb | 390 | ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num, |
02aca585 EG |
391 | txq_id); |
392 | if (ret) | |
393 | return ret; | |
394 | ||
015c15e1 JB |
395 | spin_lock_init(&txq->lock); |
396 | ||
02aca585 EG |
397 | /* |
398 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
399 | * given Tx queue, and enable the DMA channel used for that queue. | |
400 | * Circular buffer (TFD queue in DRAM) physical base address */ | |
1042db2a | 401 | iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id), |
02aca585 EG |
402 | txq->q.dma_addr >> 8); |
403 | ||
404 | return 0; | |
405 | } | |
406 | ||
c170b867 EG |
407 | /** |
408 | * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's | |
409 | */ | |
6d8f6eeb | 410 | static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id) |
c170b867 | 411 | { |
8ad71bef EG |
412 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
413 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; | |
c170b867 | 414 | struct iwl_queue *q = &txq->q; |
39644e9a | 415 | enum dma_data_direction dma_dir; |
c170b867 EG |
416 | |
417 | if (!q->n_bd) | |
418 | return; | |
419 | ||
39644e9a EG |
420 | /* In the command queue, all the TBs are mapped as BIDI |
421 | * so unmap them as such. | |
422 | */ | |
c6f600fc | 423 | if (txq_id == trans_pcie->cmd_queue) |
39644e9a | 424 | dma_dir = DMA_BIDIRECTIONAL; |
015c15e1 | 425 | else |
39644e9a EG |
426 | dma_dir = DMA_TO_DEVICE; |
427 | ||
015c15e1 | 428 | spin_lock_bh(&txq->lock); |
c170b867 | 429 | while (q->write_ptr != q->read_ptr) { |
bc2529c3 | 430 | iwl_txq_free_tfd(trans, txq, dma_dir); |
c170b867 EG |
431 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd); |
432 | } | |
015c15e1 | 433 | spin_unlock_bh(&txq->lock); |
c170b867 EG |
434 | } |
435 | ||
1359ca4f EG |
436 | /** |
437 | * iwl_tx_queue_free - Deallocate DMA queue. | |
438 | * @txq: Transmit queue to deallocate. | |
439 | * | |
440 | * Empty queue by removing and destroying all BD's. | |
441 | * Free all buffers. | |
442 | * 0-fill, but do not free "txq" descriptor structure. | |
443 | */ | |
6d8f6eeb | 444 | static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id) |
1359ca4f | 445 | { |
8ad71bef EG |
446 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
447 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; | |
1042db2a | 448 | struct device *dev = trans->dev; |
1359ca4f | 449 | int i; |
20d3b647 | 450 | |
1359ca4f EG |
451 | if (WARN_ON(!txq)) |
452 | return; | |
453 | ||
6d8f6eeb | 454 | iwl_tx_queue_unmap(trans, txq_id); |
1359ca4f EG |
455 | |
456 | /* De-alloc array of command/tx buffers */ | |
dfa2bdba | 457 | |
c6f600fc | 458 | if (txq_id == trans_pcie->cmd_queue) |
dfa2bdba | 459 | for (i = 0; i < txq->q.n_window; i++) |
bf8440e6 | 460 | kfree(txq->entries[i].cmd); |
1359ca4f EG |
461 | |
462 | /* De-alloc circular buffer of TFDs */ | |
463 | if (txq->q.n_bd) { | |
ab9e212e | 464 | dma_free_coherent(dev, sizeof(struct iwl_tfd) * |
1359ca4f EG |
465 | txq->q.n_bd, txq->tfds, txq->q.dma_addr); |
466 | memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr)); | |
467 | } | |
468 | ||
bf8440e6 JB |
469 | kfree(txq->entries); |
470 | txq->entries = NULL; | |
1359ca4f | 471 | |
7c5ba4a8 JB |
472 | del_timer_sync(&txq->stuck_timer); |
473 | ||
1359ca4f EG |
474 | /* 0-fill queue descriptor structure */ |
475 | memset(txq, 0, sizeof(*txq)); | |
476 | } | |
477 | ||
478 | /** | |
479 | * iwl_trans_tx_free - Free TXQ Context | |
480 | * | |
481 | * Destroy all TX DMA queues and structures | |
482 | */ | |
6d8f6eeb | 483 | static void iwl_trans_pcie_tx_free(struct iwl_trans *trans) |
1359ca4f EG |
484 | { |
485 | int txq_id; | |
8ad71bef | 486 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1359ca4f EG |
487 | |
488 | /* Tx queues */ | |
8ad71bef | 489 | if (trans_pcie->txq) { |
d6189124 | 490 | for (txq_id = 0; |
035f7ff2 | 491 | txq_id < trans->cfg->base_params->num_of_queues; txq_id++) |
6d8f6eeb | 492 | iwl_tx_queue_free(trans, txq_id); |
1359ca4f EG |
493 | } |
494 | ||
8ad71bef EG |
495 | kfree(trans_pcie->txq); |
496 | trans_pcie->txq = NULL; | |
1359ca4f | 497 | |
9d6b2cb1 | 498 | iwlagn_free_dma_ptr(trans, &trans_pcie->kw); |
1359ca4f | 499 | |
6d8f6eeb | 500 | iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls); |
1359ca4f EG |
501 | } |
502 | ||
02aca585 EG |
503 | /** |
504 | * iwl_trans_tx_alloc - allocate TX context | |
505 | * Allocate all Tx DMA structures and initialize them | |
506 | * | |
507 | * @param priv | |
508 | * @return error code | |
509 | */ | |
6d8f6eeb | 510 | static int iwl_trans_tx_alloc(struct iwl_trans *trans) |
02aca585 EG |
511 | { |
512 | int ret; | |
513 | int txq_id, slots_num; | |
8ad71bef | 514 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
02aca585 | 515 | |
035f7ff2 | 516 | u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues * |
ab9e212e EG |
517 | sizeof(struct iwlagn_scd_bc_tbl); |
518 | ||
02aca585 EG |
519 | /*It is not allowed to alloc twice, so warn when this happens. |
520 | * We cannot rely on the previous allocation, so free and fail */ | |
8ad71bef | 521 | if (WARN_ON(trans_pcie->txq)) { |
02aca585 EG |
522 | ret = -EINVAL; |
523 | goto error; | |
524 | } | |
525 | ||
6d8f6eeb | 526 | ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls, |
ab9e212e | 527 | scd_bc_tbls_size); |
02aca585 | 528 | if (ret) { |
6d8f6eeb | 529 | IWL_ERR(trans, "Scheduler BC Table allocation failed\n"); |
02aca585 EG |
530 | goto error; |
531 | } | |
532 | ||
533 | /* Alloc keep-warm buffer */ | |
9d6b2cb1 | 534 | ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE); |
02aca585 | 535 | if (ret) { |
6d8f6eeb | 536 | IWL_ERR(trans, "Keep Warm allocation failed\n"); |
02aca585 EG |
537 | goto error; |
538 | } | |
539 | ||
035f7ff2 | 540 | trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues, |
7f90dce1 | 541 | sizeof(struct iwl_tx_queue), GFP_KERNEL); |
8ad71bef | 542 | if (!trans_pcie->txq) { |
6d8f6eeb | 543 | IWL_ERR(trans, "Not enough memory for txq\n"); |
02aca585 EG |
544 | ret = ENOMEM; |
545 | goto error; | |
546 | } | |
547 | ||
548 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
035f7ff2 | 549 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; |
1745e440 | 550 | txq_id++) { |
9ba1947a | 551 | slots_num = (txq_id == trans_pcie->cmd_queue) ? |
02aca585 | 552 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; |
8ad71bef EG |
553 | ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id], |
554 | slots_num, txq_id); | |
02aca585 | 555 | if (ret) { |
6d8f6eeb | 556 | IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id); |
02aca585 EG |
557 | goto error; |
558 | } | |
559 | } | |
560 | ||
561 | return 0; | |
562 | ||
563 | error: | |
ae2c30bf | 564 | iwl_trans_pcie_tx_free(trans); |
02aca585 EG |
565 | |
566 | return ret; | |
567 | } | |
6d8f6eeb | 568 | static int iwl_tx_init(struct iwl_trans *trans) |
02aca585 | 569 | { |
20d3b647 | 570 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
02aca585 EG |
571 | int ret; |
572 | int txq_id, slots_num; | |
573 | unsigned long flags; | |
574 | bool alloc = false; | |
575 | ||
8ad71bef | 576 | if (!trans_pcie->txq) { |
6d8f6eeb | 577 | ret = iwl_trans_tx_alloc(trans); |
02aca585 EG |
578 | if (ret) |
579 | goto error; | |
580 | alloc = true; | |
581 | } | |
582 | ||
7b11488f | 583 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
02aca585 EG |
584 | |
585 | /* Turn off all Tx DMA fifos */ | |
1042db2a | 586 | iwl_write_prph(trans, SCD_TXFACT, 0); |
02aca585 EG |
587 | |
588 | /* Tell NIC where to find the "keep warm" buffer */ | |
1042db2a | 589 | iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, |
83ed9015 | 590 | trans_pcie->kw.dma >> 4); |
02aca585 | 591 | |
7b11488f | 592 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
02aca585 EG |
593 | |
594 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
035f7ff2 | 595 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; |
1745e440 | 596 | txq_id++) { |
9ba1947a | 597 | slots_num = (txq_id == trans_pcie->cmd_queue) ? |
02aca585 | 598 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; |
8ad71bef EG |
599 | ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id], |
600 | slots_num, txq_id); | |
02aca585 | 601 | if (ret) { |
6d8f6eeb | 602 | IWL_ERR(trans, "Tx %d queue init failed\n", txq_id); |
02aca585 EG |
603 | goto error; |
604 | } | |
605 | } | |
606 | ||
607 | return 0; | |
608 | error: | |
609 | /*Upon error, free only if we allocated something */ | |
610 | if (alloc) | |
ae2c30bf | 611 | iwl_trans_pcie_tx_free(trans); |
02aca585 EG |
612 | return ret; |
613 | } | |
614 | ||
3e10caeb | 615 | static void iwl_set_pwr_vmain(struct iwl_trans *trans) |
392f8b78 EG |
616 | { |
617 | /* | |
618 | * (for documentation purposes) | |
619 | * to set power to V_AUX, do: | |
620 | ||
621 | if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) | |
1042db2a | 622 | iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, |
392f8b78 EG |
623 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, |
624 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
625 | */ | |
626 | ||
1042db2a | 627 | iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, |
392f8b78 EG |
628 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, |
629 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
630 | } | |
631 | ||
af634bee EG |
632 | /* PCI registers */ |
633 | #define PCI_CFG_RETRY_TIMEOUT 0x041 | |
634 | #define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01 | |
635 | #define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02 | |
636 | ||
637 | static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans) | |
638 | { | |
20d3b647 | 639 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
af634bee EG |
640 | int pos; |
641 | u16 pci_lnk_ctl; | |
af634bee EG |
642 | |
643 | struct pci_dev *pci_dev = trans_pcie->pci_dev; | |
644 | ||
645 | pos = pci_pcie_cap(pci_dev); | |
646 | pci_read_config_word(pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl); | |
647 | return pci_lnk_ctl; | |
648 | } | |
649 | ||
650 | static void iwl_apm_config(struct iwl_trans *trans) | |
651 | { | |
652 | /* | |
653 | * HW bug W/A for instability in PCIe bus L0S->L1 transition. | |
654 | * Check if BIOS (or OS) enabled L1-ASPM on this device. | |
655 | * If so (likely), disable L0S, so device moves directly L0->L1; | |
656 | * costs negligible amount of power savings. | |
657 | * If not (unlikely), enable L0S, so there is at least some | |
658 | * power savings, even without L1. | |
659 | */ | |
660 | u16 lctl = iwl_pciexp_link_ctrl(trans); | |
661 | ||
662 | if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == | |
663 | PCI_CFG_LINK_CTRL_VAL_L1_EN) { | |
664 | /* L1-ASPM enabled; disable(!) L0S */ | |
665 | iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); | |
666 | dev_printk(KERN_INFO, trans->dev, | |
667 | "L1 Enabled; Disabling L0S\n"); | |
668 | } else { | |
669 | /* L1-ASPM disabled; enable(!) L0S */ | |
670 | iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); | |
671 | dev_printk(KERN_INFO, trans->dev, | |
672 | "L1 Disabled; Enabling L0S\n"); | |
673 | } | |
f6d0e9be | 674 | trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN); |
af634bee EG |
675 | } |
676 | ||
a6c684ee EG |
677 | /* |
678 | * Start up NIC's basic functionality after it has been reset | |
679 | * (e.g. after platform boot, or shutdown via iwl_apm_stop()) | |
680 | * NOTE: This does not load uCode nor start the embedded processor | |
681 | */ | |
682 | static int iwl_apm_init(struct iwl_trans *trans) | |
683 | { | |
83626404 | 684 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
a6c684ee EG |
685 | int ret = 0; |
686 | IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); | |
687 | ||
688 | /* | |
689 | * Use "set_bit" below rather than "write", to preserve any hardware | |
690 | * bits already set by default after reset. | |
691 | */ | |
692 | ||
693 | /* Disable L0S exit timer (platform NMI Work/Around) */ | |
694 | iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, | |
20d3b647 | 695 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); |
a6c684ee EG |
696 | |
697 | /* | |
698 | * Disable L0s without affecting L1; | |
699 | * don't wait for ICH L0s (ICH bug W/A) | |
700 | */ | |
701 | iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, | |
20d3b647 | 702 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); |
a6c684ee EG |
703 | |
704 | /* Set FH wait threshold to maximum (HW error during stress W/A) */ | |
705 | iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); | |
706 | ||
707 | /* | |
708 | * Enable HAP INTA (interrupt from management bus) to | |
709 | * wake device's PCI Express link L1a -> L0s | |
710 | */ | |
711 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, | |
20d3b647 | 712 | CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); |
a6c684ee | 713 | |
af634bee | 714 | iwl_apm_config(trans); |
a6c684ee EG |
715 | |
716 | /* Configure analog phase-lock-loop before activating to D0A */ | |
035f7ff2 | 717 | if (trans->cfg->base_params->pll_cfg_val) |
a6c684ee | 718 | iwl_set_bit(trans, CSR_ANA_PLL_CFG, |
035f7ff2 | 719 | trans->cfg->base_params->pll_cfg_val); |
a6c684ee EG |
720 | |
721 | /* | |
722 | * Set "initialization complete" bit to move adapter from | |
723 | * D0U* --> D0A* (powered-up active) state. | |
724 | */ | |
725 | iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
726 | ||
727 | /* | |
728 | * Wait for clock stabilization; once stabilized, access to | |
729 | * device-internal resources is supported, e.g. iwl_write_prph() | |
730 | * and accesses to uCode SRAM. | |
731 | */ | |
732 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
20d3b647 JB |
733 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, |
734 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
a6c684ee EG |
735 | if (ret < 0) { |
736 | IWL_DEBUG_INFO(trans, "Failed to init the card\n"); | |
737 | goto out; | |
738 | } | |
739 | ||
740 | /* | |
741 | * Enable DMA clock and wait for it to stabilize. | |
742 | * | |
743 | * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits | |
744 | * do not disable clocks. This preserves any hardware bits already | |
745 | * set by default in "CLK_CTRL_REG" after reset. | |
746 | */ | |
747 | iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); | |
748 | udelay(20); | |
749 | ||
750 | /* Disable L1-Active */ | |
751 | iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
752 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
753 | ||
83626404 | 754 | set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status); |
a6c684ee EG |
755 | |
756 | out: | |
757 | return ret; | |
758 | } | |
759 | ||
cc56feb2 EG |
760 | static int iwl_apm_stop_master(struct iwl_trans *trans) |
761 | { | |
762 | int ret = 0; | |
763 | ||
764 | /* stop device's busmaster DMA activity */ | |
765 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); | |
766 | ||
767 | ret = iwl_poll_bit(trans, CSR_RESET, | |
20d3b647 JB |
768 | CSR_RESET_REG_FLAG_MASTER_DISABLED, |
769 | CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); | |
cc56feb2 EG |
770 | if (ret) |
771 | IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); | |
772 | ||
773 | IWL_DEBUG_INFO(trans, "stop master\n"); | |
774 | ||
775 | return ret; | |
776 | } | |
777 | ||
778 | static void iwl_apm_stop(struct iwl_trans *trans) | |
779 | { | |
83626404 | 780 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
cc56feb2 EG |
781 | IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); |
782 | ||
83626404 | 783 | clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status); |
cc56feb2 EG |
784 | |
785 | /* Stop device's DMA activity */ | |
786 | iwl_apm_stop_master(trans); | |
787 | ||
788 | /* Reset the entire device */ | |
789 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
790 | ||
791 | udelay(10); | |
792 | ||
793 | /* | |
794 | * Clear "initialization complete" bit to move adapter from | |
795 | * D0A* (powered-up Active) --> D0U* (Uninitialized) state. | |
796 | */ | |
797 | iwl_clear_bit(trans, CSR_GP_CNTRL, | |
798 | CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
799 | } | |
800 | ||
6d8f6eeb | 801 | static int iwl_nic_init(struct iwl_trans *trans) |
392f8b78 | 802 | { |
7b11488f | 803 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
392f8b78 EG |
804 | unsigned long flags; |
805 | ||
806 | /* nic_init */ | |
7b11488f | 807 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
a6c684ee | 808 | iwl_apm_init(trans); |
392f8b78 EG |
809 | |
810 | /* Set interrupt coalescing calibration timer to default (512 usecs) */ | |
20d3b647 | 811 | iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF); |
392f8b78 | 812 | |
7b11488f | 813 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
392f8b78 | 814 | |
3e10caeb | 815 | iwl_set_pwr_vmain(trans); |
392f8b78 | 816 | |
ecdb975c | 817 | iwl_op_mode_nic_config(trans->op_mode); |
392f8b78 | 818 | |
a5916977 | 819 | #ifndef CONFIG_IWLWIFI_IDI |
392f8b78 | 820 | /* Allocate the RX queue, or reset if it is already allocated */ |
6d8f6eeb | 821 | iwl_rx_init(trans); |
a5916977 | 822 | #endif |
392f8b78 EG |
823 | |
824 | /* Allocate or reset and init all Tx and Command queues */ | |
6d8f6eeb | 825 | if (iwl_tx_init(trans)) |
392f8b78 EG |
826 | return -ENOMEM; |
827 | ||
035f7ff2 | 828 | if (trans->cfg->base_params->shadow_reg_enable) { |
392f8b78 | 829 | /* enable shadow regs in HW */ |
20d3b647 | 830 | iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); |
d38069d1 | 831 | IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); |
392f8b78 EG |
832 | } |
833 | ||
392f8b78 EG |
834 | return 0; |
835 | } | |
836 | ||
837 | #define HW_READY_TIMEOUT (50) | |
838 | ||
839 | /* Note: returns poll_bit return value, which is >= 0 if success */ | |
6d8f6eeb | 840 | static int iwl_set_hw_ready(struct iwl_trans *trans) |
392f8b78 EG |
841 | { |
842 | int ret; | |
843 | ||
1042db2a | 844 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 | 845 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); |
392f8b78 EG |
846 | |
847 | /* See if we got it */ | |
1042db2a | 848 | ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 JB |
849 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, |
850 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
851 | HW_READY_TIMEOUT); | |
392f8b78 | 852 | |
6d8f6eeb | 853 | IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); |
392f8b78 EG |
854 | return ret; |
855 | } | |
856 | ||
857 | /* Note: returns standard 0/-ERROR code */ | |
ebb7678d | 858 | static int iwl_prepare_card_hw(struct iwl_trans *trans) |
392f8b78 EG |
859 | { |
860 | int ret; | |
861 | ||
6d8f6eeb | 862 | IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); |
392f8b78 | 863 | |
6d8f6eeb | 864 | ret = iwl_set_hw_ready(trans); |
ebb7678d | 865 | /* If the card is ready, exit 0 */ |
392f8b78 EG |
866 | if (ret >= 0) |
867 | return 0; | |
868 | ||
869 | /* If HW is not ready, prepare the conditions to check again */ | |
1042db2a | 870 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 | 871 | CSR_HW_IF_CONFIG_REG_PREPARE); |
392f8b78 | 872 | |
1042db2a | 873 | ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 JB |
874 | ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, |
875 | CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000); | |
392f8b78 EG |
876 | |
877 | if (ret < 0) | |
878 | return ret; | |
879 | ||
880 | /* HW should be ready by now, check again. */ | |
6d8f6eeb | 881 | ret = iwl_set_hw_ready(trans); |
392f8b78 EG |
882 | if (ret >= 0) |
883 | return 0; | |
884 | return ret; | |
885 | } | |
886 | ||
cf614297 EG |
887 | /* |
888 | * ucode | |
889 | */ | |
6dfa8d01 DS |
890 | static int iwl_load_section(struct iwl_trans *trans, u8 section_num, |
891 | const struct fw_desc *section) | |
cf614297 | 892 | { |
13df1aab | 893 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
6dfa8d01 DS |
894 | dma_addr_t phy_addr = section->p_addr; |
895 | u32 byte_cnt = section->len; | |
896 | u32 dst_addr = section->offset; | |
cf614297 EG |
897 | int ret; |
898 | ||
13df1aab | 899 | trans_pcie->ucode_write_complete = false; |
cf614297 EG |
900 | |
901 | iwl_write_direct32(trans, | |
20d3b647 JB |
902 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), |
903 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); | |
cf614297 EG |
904 | |
905 | iwl_write_direct32(trans, | |
20d3b647 JB |
906 | FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), |
907 | dst_addr); | |
cf614297 EG |
908 | |
909 | iwl_write_direct32(trans, | |
910 | FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), | |
911 | phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); | |
912 | ||
913 | iwl_write_direct32(trans, | |
20d3b647 JB |
914 | FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), |
915 | (iwl_get_dma_hi_addr(phy_addr) | |
916 | << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); | |
cf614297 EG |
917 | |
918 | iwl_write_direct32(trans, | |
20d3b647 JB |
919 | FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), |
920 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | | |
921 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | | |
922 | FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); | |
cf614297 EG |
923 | |
924 | iwl_write_direct32(trans, | |
20d3b647 JB |
925 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), |
926 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
927 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | | |
928 | FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); | |
cf614297 | 929 | |
6dfa8d01 DS |
930 | IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", |
931 | section_num); | |
13df1aab JB |
932 | ret = wait_event_timeout(trans_pcie->ucode_write_waitq, |
933 | trans_pcie->ucode_write_complete, 5 * HZ); | |
cf614297 | 934 | if (!ret) { |
6dfa8d01 DS |
935 | IWL_ERR(trans, "Could not load the [%d] uCode section\n", |
936 | section_num); | |
cf614297 EG |
937 | return -ETIMEDOUT; |
938 | } | |
939 | ||
940 | return 0; | |
941 | } | |
942 | ||
0692fe41 JB |
943 | static int iwl_load_given_ucode(struct iwl_trans *trans, |
944 | const struct fw_img *image) | |
cf614297 EG |
945 | { |
946 | int ret = 0; | |
6dfa8d01 | 947 | int i; |
cf614297 | 948 | |
6dfa8d01 DS |
949 | for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) { |
950 | if (!image->sec[i].p_addr) | |
951 | break; | |
cf614297 | 952 | |
6dfa8d01 DS |
953 | ret = iwl_load_section(trans, i, &image->sec[i]); |
954 | if (ret) | |
955 | return ret; | |
956 | } | |
cf614297 EG |
957 | |
958 | /* Remove all resets to allow NIC to operate */ | |
959 | iwl_write32(trans, CSR_RESET, 0); | |
960 | ||
961 | return 0; | |
962 | } | |
963 | ||
0692fe41 JB |
964 | static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, |
965 | const struct fw_img *fw) | |
392f8b78 EG |
966 | { |
967 | int ret; | |
c9eec95c | 968 | bool hw_rfkill; |
392f8b78 | 969 | |
496bab39 JB |
970 | /* This may fail if AMT took ownership of the device */ |
971 | if (iwl_prepare_card_hw(trans)) { | |
6d8f6eeb | 972 | IWL_WARN(trans, "Exit HW not ready\n"); |
392f8b78 EG |
973 | return -EIO; |
974 | } | |
975 | ||
8c46bb70 EG |
976 | iwl_enable_rfkill_int(trans); |
977 | ||
392f8b78 | 978 | /* If platform's RF_KILL switch is NOT set to KILL */ |
8d425517 | 979 | hw_rfkill = iwl_is_rfkill_set(trans); |
c9eec95c | 980 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); |
8c46bb70 | 981 | if (hw_rfkill) |
392f8b78 | 982 | return -ERFKILL; |
392f8b78 | 983 | |
1042db2a | 984 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); |
392f8b78 | 985 | |
6d8f6eeb | 986 | ret = iwl_nic_init(trans); |
392f8b78 | 987 | if (ret) { |
6d8f6eeb | 988 | IWL_ERR(trans, "Unable to init nic\n"); |
392f8b78 EG |
989 | return ret; |
990 | } | |
991 | ||
992 | /* make sure rfkill handshake bits are cleared */ | |
1042db2a EG |
993 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
994 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, | |
392f8b78 EG |
995 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
996 | ||
997 | /* clear (again), then enable host interrupts */ | |
1042db2a | 998 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); |
6d8f6eeb | 999 | iwl_enable_interrupts(trans); |
392f8b78 EG |
1000 | |
1001 | /* really make sure rfkill handshake bits are cleared */ | |
1042db2a EG |
1002 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
1003 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
392f8b78 | 1004 | |
cf614297 | 1005 | /* Load the given image to the HW */ |
9441b85d | 1006 | return iwl_load_given_ucode(trans, fw); |
392f8b78 EG |
1007 | } |
1008 | ||
b3c2ce13 EG |
1009 | /* |
1010 | * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask | |
7b11488f | 1011 | * must be called under the irq lock and with MAC access |
b3c2ce13 | 1012 | */ |
6d8f6eeb | 1013 | static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask) |
b3c2ce13 | 1014 | { |
7b11488f JB |
1015 | struct iwl_trans_pcie __maybe_unused *trans_pcie = |
1016 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
1017 | ||
1018 | lockdep_assert_held(&trans_pcie->irq_lock); | |
1019 | ||
1042db2a | 1020 | iwl_write_prph(trans, SCD_TXFACT, mask); |
b3c2ce13 EG |
1021 | } |
1022 | ||
ed6a3803 | 1023 | static void iwl_tx_start(struct iwl_trans *trans) |
b3c2ce13 | 1024 | { |
9eae88fa | 1025 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
b3c2ce13 EG |
1026 | u32 a; |
1027 | unsigned long flags; | |
1028 | int i, chan; | |
1029 | u32 reg_val; | |
1030 | ||
7b11488f | 1031 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
b3c2ce13 | 1032 | |
83ed9015 | 1033 | trans_pcie->scd_base_addr = |
1042db2a | 1034 | iwl_read_prph(trans, SCD_SRAM_BASE_ADDR); |
105183b1 | 1035 | a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND; |
b3c2ce13 | 1036 | /* reset conext data memory */ |
105183b1 | 1037 | for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND; |
b3c2ce13 | 1038 | a += 4) |
1042db2a | 1039 | iwl_write_targ_mem(trans, a, 0); |
b3c2ce13 | 1040 | /* reset tx status memory */ |
105183b1 | 1041 | for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND; |
b3c2ce13 | 1042 | a += 4) |
1042db2a | 1043 | iwl_write_targ_mem(trans, a, 0); |
105183b1 | 1044 | for (; a < trans_pcie->scd_base_addr + |
1745e440 | 1045 | SCD_TRANS_TBL_OFFSET_QUEUE( |
035f7ff2 | 1046 | trans->cfg->base_params->num_of_queues); |
d6189124 | 1047 | a += 4) |
1042db2a | 1048 | iwl_write_targ_mem(trans, a, 0); |
b3c2ce13 | 1049 | |
1042db2a | 1050 | iwl_write_prph(trans, SCD_DRAM_BASE_ADDR, |
105183b1 | 1051 | trans_pcie->scd_bc_tbls.dma >> 10); |
b3c2ce13 EG |
1052 | |
1053 | /* Enable DMA channel */ | |
1054 | for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++) | |
1042db2a | 1055 | iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan), |
b3c2ce13 EG |
1056 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | |
1057 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); | |
1058 | ||
1059 | /* Update FH chicken bits */ | |
1042db2a EG |
1060 | reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG); |
1061 | iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG, | |
b3c2ce13 EG |
1062 | reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); |
1063 | ||
1042db2a | 1064 | iwl_write_prph(trans, SCD_QUEUECHAIN_SEL, |
20d3b647 | 1065 | SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie)); |
1042db2a | 1066 | iwl_write_prph(trans, SCD_AGGR_SEL, 0); |
b3c2ce13 EG |
1067 | |
1068 | /* initiate the queues */ | |
035f7ff2 | 1069 | for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { |
1042db2a EG |
1070 | iwl_write_prph(trans, SCD_QUEUE_RDPTR(i), 0); |
1071 | iwl_write_direct32(trans, HBUS_TARG_WRPTR, 0 | (i << 8)); | |
1072 | iwl_write_targ_mem(trans, trans_pcie->scd_base_addr + | |
b3c2ce13 | 1073 | SCD_CONTEXT_QUEUE_OFFSET(i), 0); |
1042db2a | 1074 | iwl_write_targ_mem(trans, trans_pcie->scd_base_addr + |
b3c2ce13 EG |
1075 | SCD_CONTEXT_QUEUE_OFFSET(i) + |
1076 | sizeof(u32), | |
1077 | ((SCD_WIN_SIZE << | |
1078 | SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
1079 | SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
1080 | ((SCD_FRAME_LIMIT << | |
1081 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
1082 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
1083 | } | |
1084 | ||
1042db2a | 1085 | iwl_write_prph(trans, SCD_INTERRUPT_MASK, |
20d3b647 | 1086 | IWL_MASK(0, trans->cfg->base_params->num_of_queues)); |
b3c2ce13 EG |
1087 | |
1088 | /* Activate all Tx DMA/FIFO channels */ | |
6d8f6eeb | 1089 | iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7)); |
b3c2ce13 | 1090 | |
c6f600fc | 1091 | iwl_trans_set_wr_ptrs(trans, trans_pcie->cmd_queue, 0); |
b3c2ce13 | 1092 | |
9eae88fa JB |
1093 | /* make sure all queue are not stopped/used */ |
1094 | memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); | |
1095 | memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); | |
b3c2ce13 | 1096 | |
9eae88fa JB |
1097 | for (i = 0; i < trans_pcie->n_q_to_fifo; i++) { |
1098 | int fifo = trans_pcie->setup_q_to_fifo[i]; | |
b3c2ce13 | 1099 | |
9eae88fa | 1100 | set_bit(i, trans_pcie->queue_used); |
b3c2ce13 | 1101 | |
8ad71bef | 1102 | iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i], |
9eae88fa | 1103 | fifo, true); |
b3c2ce13 EG |
1104 | } |
1105 | ||
7b11488f | 1106 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
b3c2ce13 EG |
1107 | |
1108 | /* Enable L1-Active */ | |
1042db2a | 1109 | iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, |
20d3b647 | 1110 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); |
b3c2ce13 EG |
1111 | } |
1112 | ||
ed6a3803 EG |
1113 | static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans) |
1114 | { | |
1115 | iwl_reset_ict(trans); | |
1116 | iwl_tx_start(trans); | |
1117 | } | |
1118 | ||
c170b867 EG |
1119 | /** |
1120 | * iwlagn_txq_ctx_stop - Stop all Tx DMA channels | |
1121 | */ | |
6d8f6eeb | 1122 | static int iwl_trans_tx_stop(struct iwl_trans *trans) |
c170b867 | 1123 | { |
20d3b647 | 1124 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
c2945f39 | 1125 | int ch, txq_id, ret; |
c170b867 EG |
1126 | unsigned long flags; |
1127 | ||
1128 | /* Turn off all Tx DMA fifos */ | |
7b11488f | 1129 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
c170b867 | 1130 | |
6d8f6eeb | 1131 | iwl_trans_txq_set_sched(trans, 0); |
c170b867 EG |
1132 | |
1133 | /* Stop each Tx DMA channel, and wait for it to be idle */ | |
02f6f659 | 1134 | for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { |
1042db2a | 1135 | iwl_write_direct32(trans, |
6d8f6eeb | 1136 | FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); |
c2945f39 | 1137 | ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG, |
20d3b647 | 1138 | FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000); |
c2945f39 | 1139 | if (ret < 0) |
20d3b647 JB |
1140 | IWL_ERR(trans, |
1141 | "Failing on timeout while stopping DMA channel %d [0x%08x]", | |
1142 | ch, | |
1143 | iwl_read_direct32(trans, | |
1144 | FH_TSSR_TX_STATUS_REG)); | |
c170b867 | 1145 | } |
7b11488f | 1146 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
c170b867 | 1147 | |
8ad71bef | 1148 | if (!trans_pcie->txq) { |
6d8f6eeb | 1149 | IWL_WARN(trans, "Stopping tx queues that aren't allocated..."); |
c170b867 EG |
1150 | return 0; |
1151 | } | |
1152 | ||
1153 | /* Unmap DMA from host system and free skb's */ | |
035f7ff2 | 1154 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; |
1745e440 | 1155 | txq_id++) |
6d8f6eeb | 1156 | iwl_tx_queue_unmap(trans, txq_id); |
c170b867 EG |
1157 | |
1158 | return 0; | |
1159 | } | |
1160 | ||
43e58856 | 1161 | static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) |
ae2c30bf | 1162 | { |
43e58856 | 1163 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
20d3b647 | 1164 | unsigned long flags; |
ae2c30bf | 1165 | |
43e58856 | 1166 | /* tell the device to stop sending interrupts */ |
7b11488f | 1167 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
ae2c30bf | 1168 | iwl_disable_interrupts(trans); |
7b11488f | 1169 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
ae2c30bf | 1170 | |
ab6cf8e8 | 1171 | /* device going down, Stop using ICT table */ |
6d8f6eeb | 1172 | iwl_disable_ict(trans); |
ab6cf8e8 EG |
1173 | |
1174 | /* | |
1175 | * If a HW restart happens during firmware loading, | |
1176 | * then the firmware loading might call this function | |
1177 | * and later it might be called again due to the | |
1178 | * restart. So don't process again if the device is | |
1179 | * already dead. | |
1180 | */ | |
83626404 | 1181 | if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) { |
6d8f6eeb | 1182 | iwl_trans_tx_stop(trans); |
a5916977 | 1183 | #ifndef CONFIG_IWLWIFI_IDI |
6d8f6eeb | 1184 | iwl_trans_rx_stop(trans); |
a5916977 | 1185 | #endif |
ab6cf8e8 | 1186 | /* Power-down device's busmaster DMA clocks */ |
1042db2a | 1187 | iwl_write_prph(trans, APMG_CLK_DIS_REG, |
ab6cf8e8 EG |
1188 | APMG_CLK_VAL_DMA_CLK_RQT); |
1189 | udelay(5); | |
1190 | } | |
1191 | ||
1192 | /* Make sure (redundant) we've released our request to stay awake */ | |
1042db2a | 1193 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
20d3b647 | 1194 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
ab6cf8e8 EG |
1195 | |
1196 | /* Stop the device, and put it in low power state */ | |
cc56feb2 | 1197 | iwl_apm_stop(trans); |
43e58856 EG |
1198 | |
1199 | /* Upon stop, the APM issues an interrupt if HW RF kill is set. | |
1200 | * Clean again the interrupt here | |
1201 | */ | |
7b11488f | 1202 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
43e58856 | 1203 | iwl_disable_interrupts(trans); |
7b11488f | 1204 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
43e58856 | 1205 | |
218733cf EG |
1206 | iwl_enable_rfkill_int(trans); |
1207 | ||
43e58856 | 1208 | /* wait to make sure we flush pending tasklet*/ |
75595536 | 1209 | synchronize_irq(trans_pcie->irq); |
43e58856 EG |
1210 | tasklet_kill(&trans_pcie->irq_tasklet); |
1211 | ||
1ee158d8 JB |
1212 | cancel_work_sync(&trans_pcie->rx_replenish); |
1213 | ||
43e58856 | 1214 | /* stop and reset the on-board processor */ |
1042db2a | 1215 | iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
74fda971 DF |
1216 | |
1217 | /* clear all status bits */ | |
1218 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); | |
1219 | clear_bit(STATUS_INT_ENABLED, &trans_pcie->status); | |
1220 | clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status); | |
01d651d4 | 1221 | clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status); |
ab6cf8e8 EG |
1222 | } |
1223 | ||
2dd4f9f7 JB |
1224 | static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans) |
1225 | { | |
1226 | /* let the ucode operate on its own */ | |
1227 | iwl_write32(trans, CSR_UCODE_DRV_GP1_SET, | |
1228 | CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE); | |
1229 | ||
1230 | iwl_disable_interrupts(trans); | |
1231 | iwl_clear_bit(trans, CSR_GP_CNTRL, | |
1232 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
1233 | } | |
1234 | ||
e13c0c59 | 1235 | static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, |
9eae88fa | 1236 | struct iwl_device_cmd *dev_cmd, int txq_id) |
47c1b496 | 1237 | { |
e13c0c59 EG |
1238 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1239 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
132f98c2 | 1240 | struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload; |
47c1b496 | 1241 | struct iwl_cmd_meta *out_meta; |
e13c0c59 EG |
1242 | struct iwl_tx_queue *txq; |
1243 | struct iwl_queue *q; | |
47c1b496 EG |
1244 | dma_addr_t phys_addr = 0; |
1245 | dma_addr_t txcmd_phys; | |
1246 | dma_addr_t scratch_phys; | |
1247 | u16 len, firstlen, secondlen; | |
1248 | u8 wait_write_ptr = 0; | |
e13c0c59 | 1249 | __le16 fc = hdr->frame_control; |
47c1b496 | 1250 | u8 hdr_len = ieee80211_hdrlen(fc); |
631b84c5 | 1251 | u16 __maybe_unused wifi_seq; |
47c1b496 | 1252 | |
8ad71bef | 1253 | txq = &trans_pcie->txq[txq_id]; |
e13c0c59 EG |
1254 | q = &txq->q; |
1255 | ||
9eae88fa JB |
1256 | if (unlikely(!test_bit(txq_id, trans_pcie->queue_used))) { |
1257 | WARN_ON_ONCE(1); | |
1258 | return -EINVAL; | |
1259 | } | |
015c15e1 | 1260 | |
9eae88fa | 1261 | spin_lock(&txq->lock); |
631b84c5 | 1262 | |
47c1b496 | 1263 | /* Set up driver data for this TFD */ |
bf8440e6 JB |
1264 | txq->entries[q->write_ptr].skb = skb; |
1265 | txq->entries[q->write_ptr].cmd = dev_cmd; | |
dfa2bdba EG |
1266 | |
1267 | dev_cmd->hdr.cmd = REPLY_TX; | |
20d3b647 JB |
1268 | dev_cmd->hdr.sequence = |
1269 | cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
1270 | INDEX_TO_SEQ(q->write_ptr))); | |
47c1b496 EG |
1271 | |
1272 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ | |
bf8440e6 | 1273 | out_meta = &txq->entries[q->write_ptr].meta; |
47c1b496 EG |
1274 | |
1275 | /* | |
1276 | * Use the first empty entry in this queue's command buffer array | |
1277 | * to contain the Tx command and MAC header concatenated together | |
1278 | * (payload data will be in another buffer). | |
1279 | * Size of this varies, due to varying MAC header length. | |
1280 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
1281 | * of the MAC header (device reads on dword boundaries). | |
1282 | * We'll tell device about this padding later. | |
1283 | */ | |
1284 | len = sizeof(struct iwl_tx_cmd) + | |
1285 | sizeof(struct iwl_cmd_header) + hdr_len; | |
1286 | firstlen = (len + 3) & ~3; | |
1287 | ||
1288 | /* Tell NIC about any 2-byte padding after MAC header */ | |
1289 | if (firstlen != len) | |
1290 | tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; | |
1291 | ||
1292 | /* Physical address of this Tx command's header (not MAC header!), | |
1293 | * within command buffer array. */ | |
1042db2a | 1294 | txcmd_phys = dma_map_single(trans->dev, |
47c1b496 EG |
1295 | &dev_cmd->hdr, firstlen, |
1296 | DMA_BIDIRECTIONAL); | |
1042db2a | 1297 | if (unlikely(dma_mapping_error(trans->dev, txcmd_phys))) |
015c15e1 | 1298 | goto out_err; |
47c1b496 EG |
1299 | dma_unmap_addr_set(out_meta, mapping, txcmd_phys); |
1300 | dma_unmap_len_set(out_meta, len, firstlen); | |
1301 | ||
1302 | if (!ieee80211_has_morefrags(fc)) { | |
1303 | txq->need_update = 1; | |
1304 | } else { | |
1305 | wait_write_ptr = 1; | |
1306 | txq->need_update = 0; | |
1307 | } | |
1308 | ||
1309 | /* Set up TFD's 2nd entry to point directly to remainder of skb, | |
1310 | * if any (802.11 null frames have no payload). */ | |
1311 | secondlen = skb->len - hdr_len; | |
1312 | if (secondlen > 0) { | |
1042db2a | 1313 | phys_addr = dma_map_single(trans->dev, skb->data + hdr_len, |
47c1b496 | 1314 | secondlen, DMA_TO_DEVICE); |
1042db2a EG |
1315 | if (unlikely(dma_mapping_error(trans->dev, phys_addr))) { |
1316 | dma_unmap_single(trans->dev, | |
47c1b496 EG |
1317 | dma_unmap_addr(out_meta, mapping), |
1318 | dma_unmap_len(out_meta, len), | |
1319 | DMA_BIDIRECTIONAL); | |
015c15e1 | 1320 | goto out_err; |
47c1b496 EG |
1321 | } |
1322 | } | |
1323 | ||
1324 | /* Attach buffers to TFD */ | |
e13c0c59 | 1325 | iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1); |
47c1b496 | 1326 | if (secondlen > 0) |
e13c0c59 | 1327 | iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr, |
47c1b496 EG |
1328 | secondlen, 0); |
1329 | ||
1330 | scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) + | |
1331 | offsetof(struct iwl_tx_cmd, scratch); | |
1332 | ||
1333 | /* take back ownership of DMA buffer to enable update */ | |
1042db2a | 1334 | dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen, |
20d3b647 | 1335 | DMA_BIDIRECTIONAL); |
47c1b496 EG |
1336 | tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); |
1337 | tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); | |
1338 | ||
e13c0c59 | 1339 | IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n", |
47c1b496 | 1340 | le16_to_cpu(dev_cmd->hdr.sequence)); |
e13c0c59 | 1341 | IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags)); |
47c1b496 EG |
1342 | |
1343 | /* Set up entry for this TFD in Tx byte-count array */ | |
96f1f05a | 1344 | iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len)); |
47c1b496 | 1345 | |
1042db2a | 1346 | dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen, |
20d3b647 | 1347 | DMA_BIDIRECTIONAL); |
47c1b496 | 1348 | |
6c1011e1 | 1349 | trace_iwlwifi_dev_tx(trans->dev, |
47c1b496 EG |
1350 | &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr], |
1351 | sizeof(struct iwl_tfd), | |
1352 | &dev_cmd->hdr, firstlen, | |
1353 | skb->data + hdr_len, secondlen); | |
1354 | ||
7c5ba4a8 JB |
1355 | /* start timer if queue currently empty */ |
1356 | if (q->read_ptr == q->write_ptr && trans_pcie->wd_timeout) | |
1357 | mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout); | |
1358 | ||
47c1b496 EG |
1359 | /* Tell device the write index *just past* this latest filled TFD */ |
1360 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
e13c0c59 EG |
1361 | iwl_txq_update_write_ptr(trans, txq); |
1362 | ||
47c1b496 EG |
1363 | /* |
1364 | * At this point the frame is "transmitted" successfully | |
1365 | * and we will get a TX status notification eventually, | |
1366 | * regardless of the value of ret. "ret" only indicates | |
1367 | * whether or not we should update the write pointer. | |
1368 | */ | |
a0eaad71 | 1369 | if (iwl_queue_space(q) < q->high_mark) { |
47c1b496 EG |
1370 | if (wait_write_ptr) { |
1371 | txq->need_update = 1; | |
e13c0c59 | 1372 | iwl_txq_update_write_ptr(trans, txq); |
47c1b496 | 1373 | } else { |
bada991b | 1374 | iwl_stop_queue(trans, txq); |
47c1b496 EG |
1375 | } |
1376 | } | |
015c15e1 | 1377 | spin_unlock(&txq->lock); |
47c1b496 | 1378 | return 0; |
015c15e1 JB |
1379 | out_err: |
1380 | spin_unlock(&txq->lock); | |
1381 | return -1; | |
47c1b496 EG |
1382 | } |
1383 | ||
57a1dc89 | 1384 | static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) |
e6bb4c9c | 1385 | { |
20d3b647 | 1386 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
e6bb4c9c | 1387 | int err; |
c9eec95c | 1388 | bool hw_rfkill; |
e6bb4c9c | 1389 | |
0c325769 EG |
1390 | trans_pcie->inta_mask = CSR_INI_SET_MASK; |
1391 | ||
57a1dc89 EG |
1392 | if (!trans_pcie->irq_requested) { |
1393 | tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long)) | |
1394 | iwl_irq_tasklet, (unsigned long)trans); | |
e6bb4c9c | 1395 | |
57a1dc89 | 1396 | iwl_alloc_isr_ict(trans); |
e6bb4c9c | 1397 | |
75595536 | 1398 | err = request_irq(trans_pcie->irq, iwl_isr_ict, IRQF_SHARED, |
20d3b647 | 1399 | DRV_NAME, trans); |
57a1dc89 EG |
1400 | if (err) { |
1401 | IWL_ERR(trans, "Error allocating IRQ %d\n", | |
75595536 | 1402 | trans_pcie->irq); |
ebb7678d | 1403 | goto error; |
57a1dc89 EG |
1404 | } |
1405 | ||
1406 | INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish); | |
1407 | trans_pcie->irq_requested = true; | |
e6bb4c9c EG |
1408 | } |
1409 | ||
ebb7678d EG |
1410 | err = iwl_prepare_card_hw(trans); |
1411 | if (err) { | |
1412 | IWL_ERR(trans, "Error while preparing HW: %d", err); | |
f057ac4e | 1413 | goto err_free_irq; |
ebb7678d | 1414 | } |
a6c684ee EG |
1415 | |
1416 | iwl_apm_init(trans); | |
1417 | ||
226c02ca EG |
1418 | /* From now on, the op_mode will be kept updated about RF kill state */ |
1419 | iwl_enable_rfkill_int(trans); | |
1420 | ||
8d425517 | 1421 | hw_rfkill = iwl_is_rfkill_set(trans); |
c9eec95c | 1422 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); |
d48e2074 | 1423 | |
ebb7678d EG |
1424 | return err; |
1425 | ||
f057ac4e | 1426 | err_free_irq: |
75595536 | 1427 | free_irq(trans_pcie->irq, trans); |
ebb7678d EG |
1428 | error: |
1429 | iwl_free_isr_ict(trans); | |
1430 | tasklet_kill(&trans_pcie->irq_tasklet); | |
1431 | return err; | |
e6bb4c9c EG |
1432 | } |
1433 | ||
218733cf EG |
1434 | static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans, |
1435 | bool op_mode_leaving) | |
cc56feb2 | 1436 | { |
20d3b647 | 1437 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
d23f78e6 | 1438 | bool hw_rfkill; |
218733cf | 1439 | unsigned long flags; |
d23f78e6 | 1440 | |
cc56feb2 EG |
1441 | iwl_apm_stop(trans); |
1442 | ||
218733cf EG |
1443 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
1444 | iwl_disable_interrupts(trans); | |
1445 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); | |
1df06bdc | 1446 | |
218733cf | 1447 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); |
d23f78e6 | 1448 | |
218733cf EG |
1449 | if (!op_mode_leaving) { |
1450 | /* | |
1451 | * Even if we stop the HW, we still want the RF kill | |
1452 | * interrupt | |
1453 | */ | |
1454 | iwl_enable_rfkill_int(trans); | |
1455 | ||
1456 | /* | |
1457 | * Check again since the RF kill state may have changed while | |
1458 | * all the interrupts were disabled, in this case we couldn't | |
1459 | * receive the RF kill interrupt and update the state in the | |
1460 | * op_mode. | |
1461 | */ | |
1462 | hw_rfkill = iwl_is_rfkill_set(trans); | |
1463 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); | |
1464 | } | |
cc56feb2 EG |
1465 | } |
1466 | ||
9eae88fa JB |
1467 | static void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, |
1468 | struct sk_buff_head *skbs) | |
464021ff | 1469 | { |
8ad71bef EG |
1470 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1471 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; | |
a0eaad71 EG |
1472 | /* n_bd is usually 256 => n_bd - 1 = 0xff */ |
1473 | int tfd_num = ssn & (txq->q.n_bd - 1); | |
464021ff | 1474 | int freed = 0; |
a0eaad71 | 1475 | |
015c15e1 JB |
1476 | spin_lock(&txq->lock); |
1477 | ||
a0eaad71 | 1478 | if (txq->q.read_ptr != tfd_num) { |
9eae88fa JB |
1479 | IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n", |
1480 | txq_id, txq->q.read_ptr, tfd_num, ssn); | |
464021ff | 1481 | freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs); |
e755f882 | 1482 | if (iwl_queue_space(&txq->q) > txq->q.low_mark) |
bada991b | 1483 | iwl_wake_queue(trans, txq); |
a0eaad71 | 1484 | } |
015c15e1 JB |
1485 | |
1486 | spin_unlock(&txq->lock); | |
a0eaad71 EG |
1487 | } |
1488 | ||
03905495 EG |
1489 | static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) |
1490 | { | |
05f5b97e | 1491 | writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
1492 | } |
1493 | ||
1494 | static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) | |
1495 | { | |
05f5b97e | 1496 | writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
1497 | } |
1498 | ||
1499 | static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) | |
1500 | { | |
05f5b97e | 1501 | return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
1502 | } |
1503 | ||
c6f600fc | 1504 | static void iwl_trans_pcie_configure(struct iwl_trans *trans, |
9eae88fa | 1505 | const struct iwl_trans_config *trans_cfg) |
c6f600fc MV |
1506 | { |
1507 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1508 | ||
1509 | trans_pcie->cmd_queue = trans_cfg->cmd_queue; | |
d663ee73 JB |
1510 | if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) |
1511 | trans_pcie->n_no_reclaim_cmds = 0; | |
1512 | else | |
1513 | trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; | |
1514 | if (trans_pcie->n_no_reclaim_cmds) | |
1515 | memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, | |
1516 | trans_pcie->n_no_reclaim_cmds * sizeof(u8)); | |
9eae88fa JB |
1517 | |
1518 | trans_pcie->n_q_to_fifo = trans_cfg->n_queue_to_fifo; | |
1519 | ||
1520 | if (WARN_ON(trans_pcie->n_q_to_fifo > IWL_MAX_HW_QUEUES)) | |
1521 | trans_pcie->n_q_to_fifo = IWL_MAX_HW_QUEUES; | |
1522 | ||
1523 | /* at least the command queue must be mapped */ | |
1524 | WARN_ON(!trans_pcie->n_q_to_fifo); | |
1525 | ||
1526 | memcpy(trans_pcie->setup_q_to_fifo, trans_cfg->queue_to_fifo, | |
1527 | trans_pcie->n_q_to_fifo * sizeof(u8)); | |
b2cf410c JB |
1528 | |
1529 | trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k; | |
1530 | if (trans_pcie->rx_buf_size_8k) | |
1531 | trans_pcie->rx_page_order = get_order(8 * 1024); | |
1532 | else | |
1533 | trans_pcie->rx_page_order = get_order(4 * 1024); | |
7c5ba4a8 JB |
1534 | |
1535 | trans_pcie->wd_timeout = | |
1536 | msecs_to_jiffies(trans_cfg->queue_watchdog_timeout); | |
d9fb6465 JB |
1537 | |
1538 | trans_pcie->command_names = trans_cfg->command_names; | |
c6f600fc MV |
1539 | } |
1540 | ||
d1ff5253 | 1541 | void iwl_trans_pcie_free(struct iwl_trans *trans) |
34c1b7ba | 1542 | { |
20d3b647 | 1543 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
a42a1844 | 1544 | |
ae2c30bf | 1545 | iwl_trans_pcie_tx_free(trans); |
a5916977 | 1546 | #ifndef CONFIG_IWLWIFI_IDI |
ae2c30bf | 1547 | iwl_trans_pcie_rx_free(trans); |
a5916977 | 1548 | #endif |
57a1dc89 | 1549 | if (trans_pcie->irq_requested == true) { |
75595536 | 1550 | free_irq(trans_pcie->irq, trans); |
57a1dc89 EG |
1551 | iwl_free_isr_ict(trans); |
1552 | } | |
a42a1844 EG |
1553 | |
1554 | pci_disable_msi(trans_pcie->pci_dev); | |
05f5b97e | 1555 | iounmap(trans_pcie->hw_base); |
a42a1844 EG |
1556 | pci_release_regions(trans_pcie->pci_dev); |
1557 | pci_disable_device(trans_pcie->pci_dev); | |
1558 | ||
6d8f6eeb | 1559 | kfree(trans); |
34c1b7ba EG |
1560 | } |
1561 | ||
47107e84 DF |
1562 | static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) |
1563 | { | |
1564 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1565 | ||
1566 | if (state) | |
01d651d4 | 1567 | set_bit(STATUS_TPOWER_PMI, &trans_pcie->status); |
47107e84 | 1568 | else |
01d651d4 | 1569 | clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status); |
47107e84 DF |
1570 | } |
1571 | ||
c01a4047 | 1572 | #ifdef CONFIG_PM_SLEEP |
57210f7c EG |
1573 | static int iwl_trans_pcie_suspend(struct iwl_trans *trans) |
1574 | { | |
57210f7c EG |
1575 | return 0; |
1576 | } | |
1577 | ||
1578 | static int iwl_trans_pcie_resume(struct iwl_trans *trans) | |
1579 | { | |
c9eec95c | 1580 | bool hw_rfkill; |
57210f7c | 1581 | |
8c46bb70 EG |
1582 | iwl_enable_rfkill_int(trans); |
1583 | ||
8d425517 | 1584 | hw_rfkill = iwl_is_rfkill_set(trans); |
8c46bb70 | 1585 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); |
8722c899 | 1586 | |
8c46bb70 | 1587 | if (!hw_rfkill) |
8722c899 SG |
1588 | iwl_enable_interrupts(trans); |
1589 | ||
57210f7c EG |
1590 | return 0; |
1591 | } | |
c01a4047 | 1592 | #endif /* CONFIG_PM_SLEEP */ |
57210f7c | 1593 | |
5f178cd2 EG |
1594 | #define IWL_FLUSH_WAIT_MS 2000 |
1595 | ||
1596 | static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans) | |
1597 | { | |
8ad71bef | 1598 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
5f178cd2 EG |
1599 | struct iwl_tx_queue *txq; |
1600 | struct iwl_queue *q; | |
1601 | int cnt; | |
1602 | unsigned long now = jiffies; | |
1603 | int ret = 0; | |
1604 | ||
1605 | /* waiting for all the tx frames complete might take a while */ | |
035f7ff2 | 1606 | for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { |
9ba1947a | 1607 | if (cnt == trans_pcie->cmd_queue) |
5f178cd2 | 1608 | continue; |
8ad71bef | 1609 | txq = &trans_pcie->txq[cnt]; |
5f178cd2 EG |
1610 | q = &txq->q; |
1611 | while (q->read_ptr != q->write_ptr && !time_after(jiffies, | |
1612 | now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) | |
1613 | msleep(1); | |
1614 | ||
1615 | if (q->read_ptr != q->write_ptr) { | |
1616 | IWL_ERR(trans, "fail to flush all tx fifo queues\n"); | |
1617 | ret = -ETIMEDOUT; | |
1618 | break; | |
1619 | } | |
1620 | } | |
1621 | return ret; | |
1622 | } | |
1623 | ||
ff620849 EG |
1624 | static const char *get_fh_string(int cmd) |
1625 | { | |
d9fb6465 | 1626 | #define IWL_CMD(x) case x: return #x |
ff620849 EG |
1627 | switch (cmd) { |
1628 | IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG); | |
1629 | IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG); | |
1630 | IWL_CMD(FH_RSCSR_CHNL0_WPTR); | |
1631 | IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG); | |
1632 | IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG); | |
1633 | IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG); | |
1634 | IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV); | |
1635 | IWL_CMD(FH_TSSR_TX_STATUS_REG); | |
1636 | IWL_CMD(FH_TSSR_TX_ERROR_REG); | |
1637 | default: | |
1638 | return "UNKNOWN"; | |
1639 | } | |
d9fb6465 | 1640 | #undef IWL_CMD |
ff620849 EG |
1641 | } |
1642 | ||
1643 | int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display) | |
1644 | { | |
1645 | int i; | |
1646 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1647 | int pos = 0; | |
1648 | size_t bufsz = 0; | |
1649 | #endif | |
1650 | static const u32 fh_tbl[] = { | |
1651 | FH_RSCSR_CHNL0_STTS_WPTR_REG, | |
1652 | FH_RSCSR_CHNL0_RBDCB_BASE_REG, | |
1653 | FH_RSCSR_CHNL0_WPTR, | |
1654 | FH_MEM_RCSR_CHNL0_CONFIG_REG, | |
1655 | FH_MEM_RSSR_SHARED_CTRL_REG, | |
1656 | FH_MEM_RSSR_RX_STATUS_REG, | |
1657 | FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV, | |
1658 | FH_TSSR_TX_STATUS_REG, | |
1659 | FH_TSSR_TX_ERROR_REG | |
1660 | }; | |
1661 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1662 | if (display) { | |
1663 | bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40; | |
1664 | *buf = kmalloc(bufsz, GFP_KERNEL); | |
1665 | if (!*buf) | |
1666 | return -ENOMEM; | |
1667 | pos += scnprintf(*buf + pos, bufsz - pos, | |
1668 | "FH register values:\n"); | |
1669 | for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) { | |
1670 | pos += scnprintf(*buf + pos, bufsz - pos, | |
1671 | " %34s: 0X%08x\n", | |
1672 | get_fh_string(fh_tbl[i]), | |
1042db2a | 1673 | iwl_read_direct32(trans, fh_tbl[i])); |
ff620849 EG |
1674 | } |
1675 | return pos; | |
1676 | } | |
1677 | #endif | |
1678 | IWL_ERR(trans, "FH register values:\n"); | |
1679 | for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) { | |
1680 | IWL_ERR(trans, " %34s: 0X%08x\n", | |
1681 | get_fh_string(fh_tbl[i]), | |
1042db2a | 1682 | iwl_read_direct32(trans, fh_tbl[i])); |
ff620849 EG |
1683 | } |
1684 | return 0; | |
1685 | } | |
1686 | ||
1687 | static const char *get_csr_string(int cmd) | |
1688 | { | |
d9fb6465 | 1689 | #define IWL_CMD(x) case x: return #x |
ff620849 EG |
1690 | switch (cmd) { |
1691 | IWL_CMD(CSR_HW_IF_CONFIG_REG); | |
1692 | IWL_CMD(CSR_INT_COALESCING); | |
1693 | IWL_CMD(CSR_INT); | |
1694 | IWL_CMD(CSR_INT_MASK); | |
1695 | IWL_CMD(CSR_FH_INT_STATUS); | |
1696 | IWL_CMD(CSR_GPIO_IN); | |
1697 | IWL_CMD(CSR_RESET); | |
1698 | IWL_CMD(CSR_GP_CNTRL); | |
1699 | IWL_CMD(CSR_HW_REV); | |
1700 | IWL_CMD(CSR_EEPROM_REG); | |
1701 | IWL_CMD(CSR_EEPROM_GP); | |
1702 | IWL_CMD(CSR_OTP_GP_REG); | |
1703 | IWL_CMD(CSR_GIO_REG); | |
1704 | IWL_CMD(CSR_GP_UCODE_REG); | |
1705 | IWL_CMD(CSR_GP_DRIVER_REG); | |
1706 | IWL_CMD(CSR_UCODE_DRV_GP1); | |
1707 | IWL_CMD(CSR_UCODE_DRV_GP2); | |
1708 | IWL_CMD(CSR_LED_REG); | |
1709 | IWL_CMD(CSR_DRAM_INT_TBL_REG); | |
1710 | IWL_CMD(CSR_GIO_CHICKEN_BITS); | |
1711 | IWL_CMD(CSR_ANA_PLL_CFG); | |
1712 | IWL_CMD(CSR_HW_REV_WA_REG); | |
1713 | IWL_CMD(CSR_DBG_HPET_MEM_REG); | |
1714 | default: | |
1715 | return "UNKNOWN"; | |
1716 | } | |
d9fb6465 | 1717 | #undef IWL_CMD |
ff620849 EG |
1718 | } |
1719 | ||
1720 | void iwl_dump_csr(struct iwl_trans *trans) | |
1721 | { | |
1722 | int i; | |
1723 | static const u32 csr_tbl[] = { | |
1724 | CSR_HW_IF_CONFIG_REG, | |
1725 | CSR_INT_COALESCING, | |
1726 | CSR_INT, | |
1727 | CSR_INT_MASK, | |
1728 | CSR_FH_INT_STATUS, | |
1729 | CSR_GPIO_IN, | |
1730 | CSR_RESET, | |
1731 | CSR_GP_CNTRL, | |
1732 | CSR_HW_REV, | |
1733 | CSR_EEPROM_REG, | |
1734 | CSR_EEPROM_GP, | |
1735 | CSR_OTP_GP_REG, | |
1736 | CSR_GIO_REG, | |
1737 | CSR_GP_UCODE_REG, | |
1738 | CSR_GP_DRIVER_REG, | |
1739 | CSR_UCODE_DRV_GP1, | |
1740 | CSR_UCODE_DRV_GP2, | |
1741 | CSR_LED_REG, | |
1742 | CSR_DRAM_INT_TBL_REG, | |
1743 | CSR_GIO_CHICKEN_BITS, | |
1744 | CSR_ANA_PLL_CFG, | |
1745 | CSR_HW_REV_WA_REG, | |
1746 | CSR_DBG_HPET_MEM_REG | |
1747 | }; | |
1748 | IWL_ERR(trans, "CSR values:\n"); | |
1749 | IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " | |
1750 | "CSR_INT_PERIODIC_REG)\n"); | |
1751 | for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { | |
1752 | IWL_ERR(trans, " %25s: 0X%08x\n", | |
1753 | get_csr_string(csr_tbl[i]), | |
1042db2a | 1754 | iwl_read32(trans, csr_tbl[i])); |
ff620849 EG |
1755 | } |
1756 | } | |
1757 | ||
87e5666c EG |
1758 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
1759 | /* create and remove of files */ | |
1760 | #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ | |
5a878bf6 | 1761 | if (!debugfs_create_file(#name, mode, parent, trans, \ |
87e5666c EG |
1762 | &iwl_dbgfs_##name##_ops)) \ |
1763 | return -ENOMEM; \ | |
1764 | } while (0) | |
1765 | ||
1766 | /* file operation */ | |
1767 | #define DEBUGFS_READ_FUNC(name) \ | |
1768 | static ssize_t iwl_dbgfs_##name##_read(struct file *file, \ | |
1769 | char __user *user_buf, \ | |
1770 | size_t count, loff_t *ppos); | |
1771 | ||
1772 | #define DEBUGFS_WRITE_FUNC(name) \ | |
1773 | static ssize_t iwl_dbgfs_##name##_write(struct file *file, \ | |
1774 | const char __user *user_buf, \ | |
1775 | size_t count, loff_t *ppos); | |
1776 | ||
1777 | ||
87e5666c EG |
1778 | #define DEBUGFS_READ_FILE_OPS(name) \ |
1779 | DEBUGFS_READ_FUNC(name); \ | |
1780 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
1781 | .read = iwl_dbgfs_##name##_read, \ | |
234e3405 | 1782 | .open = simple_open, \ |
87e5666c EG |
1783 | .llseek = generic_file_llseek, \ |
1784 | }; | |
1785 | ||
16db88ba EG |
1786 | #define DEBUGFS_WRITE_FILE_OPS(name) \ |
1787 | DEBUGFS_WRITE_FUNC(name); \ | |
1788 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
1789 | .write = iwl_dbgfs_##name##_write, \ | |
234e3405 | 1790 | .open = simple_open, \ |
16db88ba EG |
1791 | .llseek = generic_file_llseek, \ |
1792 | }; | |
1793 | ||
87e5666c EG |
1794 | #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ |
1795 | DEBUGFS_READ_FUNC(name); \ | |
1796 | DEBUGFS_WRITE_FUNC(name); \ | |
1797 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
1798 | .write = iwl_dbgfs_##name##_write, \ | |
1799 | .read = iwl_dbgfs_##name##_read, \ | |
234e3405 | 1800 | .open = simple_open, \ |
87e5666c EG |
1801 | .llseek = generic_file_llseek, \ |
1802 | }; | |
1803 | ||
87e5666c | 1804 | static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, |
20d3b647 JB |
1805 | char __user *user_buf, |
1806 | size_t count, loff_t *ppos) | |
8ad71bef | 1807 | { |
5a878bf6 | 1808 | struct iwl_trans *trans = file->private_data; |
8ad71bef | 1809 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
87e5666c EG |
1810 | struct iwl_tx_queue *txq; |
1811 | struct iwl_queue *q; | |
1812 | char *buf; | |
1813 | int pos = 0; | |
1814 | int cnt; | |
1815 | int ret; | |
1745e440 WYG |
1816 | size_t bufsz; |
1817 | ||
035f7ff2 | 1818 | bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues; |
87e5666c | 1819 | |
f9e75447 | 1820 | if (!trans_pcie->txq) |
87e5666c | 1821 | return -EAGAIN; |
f9e75447 | 1822 | |
87e5666c EG |
1823 | buf = kzalloc(bufsz, GFP_KERNEL); |
1824 | if (!buf) | |
1825 | return -ENOMEM; | |
1826 | ||
035f7ff2 | 1827 | for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { |
8ad71bef | 1828 | txq = &trans_pcie->txq[cnt]; |
87e5666c EG |
1829 | q = &txq->q; |
1830 | pos += scnprintf(buf + pos, bufsz - pos, | |
9eae88fa | 1831 | "hwq %.2d: read=%u write=%u use=%d stop=%d\n", |
87e5666c | 1832 | cnt, q->read_ptr, q->write_ptr, |
9eae88fa JB |
1833 | !!test_bit(cnt, trans_pcie->queue_used), |
1834 | !!test_bit(cnt, trans_pcie->queue_stopped)); | |
87e5666c EG |
1835 | } |
1836 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1837 | kfree(buf); | |
1838 | return ret; | |
1839 | } | |
1840 | ||
1841 | static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, | |
20d3b647 JB |
1842 | char __user *user_buf, |
1843 | size_t count, loff_t *ppos) | |
1844 | { | |
5a878bf6 | 1845 | struct iwl_trans *trans = file->private_data; |
20d3b647 | 1846 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
5a878bf6 | 1847 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; |
87e5666c EG |
1848 | char buf[256]; |
1849 | int pos = 0; | |
1850 | const size_t bufsz = sizeof(buf); | |
1851 | ||
1852 | pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n", | |
1853 | rxq->read); | |
1854 | pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n", | |
1855 | rxq->write); | |
1856 | pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n", | |
1857 | rxq->free_count); | |
1858 | if (rxq->rb_stts) { | |
1859 | pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n", | |
1860 | le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF); | |
1861 | } else { | |
1862 | pos += scnprintf(buf + pos, bufsz - pos, | |
1863 | "closed_rb_num: Not Allocated\n"); | |
1864 | } | |
1865 | return simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1866 | } | |
1867 | ||
1f7b6172 EG |
1868 | static ssize_t iwl_dbgfs_interrupt_read(struct file *file, |
1869 | char __user *user_buf, | |
20d3b647 JB |
1870 | size_t count, loff_t *ppos) |
1871 | { | |
1f7b6172 | 1872 | struct iwl_trans *trans = file->private_data; |
20d3b647 | 1873 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1f7b6172 EG |
1874 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; |
1875 | ||
1876 | int pos = 0; | |
1877 | char *buf; | |
1878 | int bufsz = 24 * 64; /* 24 items * 64 char per item */ | |
1879 | ssize_t ret; | |
1880 | ||
1881 | buf = kzalloc(bufsz, GFP_KERNEL); | |
f9e75447 | 1882 | if (!buf) |
1f7b6172 | 1883 | return -ENOMEM; |
1f7b6172 EG |
1884 | |
1885 | pos += scnprintf(buf + pos, bufsz - pos, | |
1886 | "Interrupt Statistics Report:\n"); | |
1887 | ||
1888 | pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", | |
1889 | isr_stats->hw); | |
1890 | pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", | |
1891 | isr_stats->sw); | |
1892 | if (isr_stats->sw || isr_stats->hw) { | |
1893 | pos += scnprintf(buf + pos, bufsz - pos, | |
1894 | "\tLast Restarting Code: 0x%X\n", | |
1895 | isr_stats->err_code); | |
1896 | } | |
1897 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1898 | pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", | |
1899 | isr_stats->sch); | |
1900 | pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", | |
1901 | isr_stats->alive); | |
1902 | #endif | |
1903 | pos += scnprintf(buf + pos, bufsz - pos, | |
1904 | "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); | |
1905 | ||
1906 | pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", | |
1907 | isr_stats->ctkill); | |
1908 | ||
1909 | pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", | |
1910 | isr_stats->wakeup); | |
1911 | ||
1912 | pos += scnprintf(buf + pos, bufsz - pos, | |
1913 | "Rx command responses:\t\t %u\n", isr_stats->rx); | |
1914 | ||
1915 | pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", | |
1916 | isr_stats->tx); | |
1917 | ||
1918 | pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", | |
1919 | isr_stats->unhandled); | |
1920 | ||
1921 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1922 | kfree(buf); | |
1923 | return ret; | |
1924 | } | |
1925 | ||
1926 | static ssize_t iwl_dbgfs_interrupt_write(struct file *file, | |
1927 | const char __user *user_buf, | |
1928 | size_t count, loff_t *ppos) | |
1929 | { | |
1930 | struct iwl_trans *trans = file->private_data; | |
20d3b647 | 1931 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1f7b6172 EG |
1932 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; |
1933 | ||
1934 | char buf[8]; | |
1935 | int buf_size; | |
1936 | u32 reset_flag; | |
1937 | ||
1938 | memset(buf, 0, sizeof(buf)); | |
1939 | buf_size = min(count, sizeof(buf) - 1); | |
1940 | if (copy_from_user(buf, user_buf, buf_size)) | |
1941 | return -EFAULT; | |
1942 | if (sscanf(buf, "%x", &reset_flag) != 1) | |
1943 | return -EFAULT; | |
1944 | if (reset_flag == 0) | |
1945 | memset(isr_stats, 0, sizeof(*isr_stats)); | |
1946 | ||
1947 | return count; | |
1948 | } | |
1949 | ||
16db88ba | 1950 | static ssize_t iwl_dbgfs_csr_write(struct file *file, |
20d3b647 JB |
1951 | const char __user *user_buf, |
1952 | size_t count, loff_t *ppos) | |
16db88ba EG |
1953 | { |
1954 | struct iwl_trans *trans = file->private_data; | |
1955 | char buf[8]; | |
1956 | int buf_size; | |
1957 | int csr; | |
1958 | ||
1959 | memset(buf, 0, sizeof(buf)); | |
1960 | buf_size = min(count, sizeof(buf) - 1); | |
1961 | if (copy_from_user(buf, user_buf, buf_size)) | |
1962 | return -EFAULT; | |
1963 | if (sscanf(buf, "%d", &csr) != 1) | |
1964 | return -EFAULT; | |
1965 | ||
1966 | iwl_dump_csr(trans); | |
1967 | ||
1968 | return count; | |
1969 | } | |
1970 | ||
16db88ba | 1971 | static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, |
20d3b647 JB |
1972 | char __user *user_buf, |
1973 | size_t count, loff_t *ppos) | |
16db88ba EG |
1974 | { |
1975 | struct iwl_trans *trans = file->private_data; | |
1976 | char *buf; | |
1977 | int pos = 0; | |
1978 | ssize_t ret = -EFAULT; | |
1979 | ||
1980 | ret = pos = iwl_dump_fh(trans, &buf, true); | |
1981 | if (buf) { | |
1982 | ret = simple_read_from_buffer(user_buf, | |
1983 | count, ppos, buf, pos); | |
1984 | kfree(buf); | |
1985 | } | |
1986 | ||
1987 | return ret; | |
1988 | } | |
1989 | ||
48dffd39 JB |
1990 | static ssize_t iwl_dbgfs_fw_restart_write(struct file *file, |
1991 | const char __user *user_buf, | |
1992 | size_t count, loff_t *ppos) | |
1993 | { | |
1994 | struct iwl_trans *trans = file->private_data; | |
1995 | ||
1996 | if (!trans->op_mode) | |
1997 | return -EAGAIN; | |
1998 | ||
1999 | iwl_op_mode_nic_error(trans->op_mode); | |
2000 | ||
2001 | return count; | |
2002 | } | |
2003 | ||
1f7b6172 | 2004 | DEBUGFS_READ_WRITE_FILE_OPS(interrupt); |
16db88ba | 2005 | DEBUGFS_READ_FILE_OPS(fh_reg); |
87e5666c EG |
2006 | DEBUGFS_READ_FILE_OPS(rx_queue); |
2007 | DEBUGFS_READ_FILE_OPS(tx_queue); | |
16db88ba | 2008 | DEBUGFS_WRITE_FILE_OPS(csr); |
48dffd39 | 2009 | DEBUGFS_WRITE_FILE_OPS(fw_restart); |
87e5666c EG |
2010 | |
2011 | /* | |
2012 | * Create the debugfs files and directories | |
2013 | * | |
2014 | */ | |
2015 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, | |
20d3b647 | 2016 | struct dentry *dir) |
87e5666c | 2017 | { |
87e5666c EG |
2018 | DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR); |
2019 | DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR); | |
1f7b6172 | 2020 | DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR); |
16db88ba EG |
2021 | DEBUGFS_ADD_FILE(csr, dir, S_IWUSR); |
2022 | DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR); | |
48dffd39 | 2023 | DEBUGFS_ADD_FILE(fw_restart, dir, S_IWUSR); |
87e5666c EG |
2024 | return 0; |
2025 | } | |
2026 | #else | |
2027 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, | |
20d3b647 JB |
2028 | struct dentry *dir) |
2029 | { | |
2030 | return 0; | |
2031 | } | |
87e5666c EG |
2032 | #endif /*CONFIG_IWLWIFI_DEBUGFS */ |
2033 | ||
d1ff5253 | 2034 | static const struct iwl_trans_ops trans_ops_pcie = { |
57a1dc89 | 2035 | .start_hw = iwl_trans_pcie_start_hw, |
cc56feb2 | 2036 | .stop_hw = iwl_trans_pcie_stop_hw, |
ed6a3803 | 2037 | .fw_alive = iwl_trans_pcie_fw_alive, |
cf614297 | 2038 | .start_fw = iwl_trans_pcie_start_fw, |
e6bb4c9c | 2039 | .stop_device = iwl_trans_pcie_stop_device, |
48d42c42 | 2040 | |
2dd4f9f7 JB |
2041 | .wowlan_suspend = iwl_trans_pcie_wowlan_suspend, |
2042 | ||
e6bb4c9c | 2043 | .send_cmd = iwl_trans_pcie_send_cmd, |
c85eb619 | 2044 | |
e6bb4c9c | 2045 | .tx = iwl_trans_pcie_tx, |
a0eaad71 | 2046 | .reclaim = iwl_trans_pcie_reclaim, |
34c1b7ba | 2047 | |
7f01d567 | 2048 | .tx_agg_disable = iwl_trans_pcie_tx_agg_disable, |
c91bd124 | 2049 | .tx_agg_setup = iwl_trans_pcie_tx_agg_setup, |
34c1b7ba | 2050 | |
87e5666c | 2051 | .dbgfs_register = iwl_trans_pcie_dbgfs_register, |
5f178cd2 EG |
2052 | |
2053 | .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty, | |
2054 | ||
c01a4047 | 2055 | #ifdef CONFIG_PM_SLEEP |
57210f7c EG |
2056 | .suspend = iwl_trans_pcie_suspend, |
2057 | .resume = iwl_trans_pcie_resume, | |
c01a4047 | 2058 | #endif |
03905495 EG |
2059 | .write8 = iwl_trans_pcie_write8, |
2060 | .write32 = iwl_trans_pcie_write32, | |
2061 | .read32 = iwl_trans_pcie_read32, | |
c6f600fc | 2062 | .configure = iwl_trans_pcie_configure, |
47107e84 | 2063 | .set_pmi = iwl_trans_pcie_set_pmi, |
e6bb4c9c | 2064 | }; |
a42a1844 | 2065 | |
87ce05a2 | 2066 | struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, |
035f7ff2 EG |
2067 | const struct pci_device_id *ent, |
2068 | const struct iwl_cfg *cfg) | |
a42a1844 | 2069 | { |
a42a1844 EG |
2070 | struct iwl_trans_pcie *trans_pcie; |
2071 | struct iwl_trans *trans; | |
2072 | u16 pci_cmd; | |
2073 | int err; | |
2074 | ||
2075 | trans = kzalloc(sizeof(struct iwl_trans) + | |
20d3b647 | 2076 | sizeof(struct iwl_trans_pcie), GFP_KERNEL); |
a42a1844 EG |
2077 | |
2078 | if (WARN_ON(!trans)) | |
2079 | return NULL; | |
2080 | ||
2081 | trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
2082 | ||
2083 | trans->ops = &trans_ops_pcie; | |
035f7ff2 | 2084 | trans->cfg = cfg; |
a42a1844 | 2085 | trans_pcie->trans = trans; |
7b11488f | 2086 | spin_lock_init(&trans_pcie->irq_lock); |
13df1aab | 2087 | init_waitqueue_head(&trans_pcie->ucode_write_waitq); |
a42a1844 EG |
2088 | |
2089 | /* W/A - seems to solve weird behavior. We need to remove this if we | |
2090 | * don't want to stay in L1 all the time. This wastes a lot of power */ | |
2091 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | | |
20d3b647 | 2092 | PCIE_LINK_STATE_CLKPM); |
a42a1844 EG |
2093 | |
2094 | if (pci_enable_device(pdev)) { | |
2095 | err = -ENODEV; | |
2096 | goto out_no_pci; | |
2097 | } | |
2098 | ||
2099 | pci_set_master(pdev); | |
2100 | ||
2101 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36)); | |
2102 | if (!err) | |
2103 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36)); | |
2104 | if (err) { | |
2105 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
2106 | if (!err) | |
2107 | err = pci_set_consistent_dma_mask(pdev, | |
20d3b647 | 2108 | DMA_BIT_MASK(32)); |
a42a1844 EG |
2109 | /* both attempts failed: */ |
2110 | if (err) { | |
2111 | dev_printk(KERN_ERR, &pdev->dev, | |
2112 | "No suitable DMA available.\n"); | |
2113 | goto out_pci_disable_device; | |
2114 | } | |
2115 | } | |
2116 | ||
2117 | err = pci_request_regions(pdev, DRV_NAME); | |
2118 | if (err) { | |
2119 | dev_printk(KERN_ERR, &pdev->dev, "pci_request_regions failed"); | |
2120 | goto out_pci_disable_device; | |
2121 | } | |
2122 | ||
05f5b97e | 2123 | trans_pcie->hw_base = pci_ioremap_bar(pdev, 0); |
a42a1844 | 2124 | if (!trans_pcie->hw_base) { |
05f5b97e | 2125 | dev_printk(KERN_ERR, &pdev->dev, "pci_ioremap_bar failed"); |
a42a1844 EG |
2126 | err = -ENODEV; |
2127 | goto out_pci_release_regions; | |
2128 | } | |
2129 | ||
a42a1844 | 2130 | dev_printk(KERN_INFO, &pdev->dev, |
20d3b647 JB |
2131 | "pci_resource_len = 0x%08llx\n", |
2132 | (unsigned long long) pci_resource_len(pdev, 0)); | |
a42a1844 | 2133 | dev_printk(KERN_INFO, &pdev->dev, |
20d3b647 | 2134 | "pci_resource_base = %p\n", trans_pcie->hw_base); |
a42a1844 EG |
2135 | |
2136 | dev_printk(KERN_INFO, &pdev->dev, | |
20d3b647 | 2137 | "HW Revision ID = 0x%X\n", pdev->revision); |
a42a1844 EG |
2138 | |
2139 | /* We disable the RETRY_TIMEOUT register (0x41) to keep | |
2140 | * PCI Tx retries from interfering with C3 CPU state */ | |
2141 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
2142 | ||
2143 | err = pci_enable_msi(pdev); | |
2144 | if (err) | |
2145 | dev_printk(KERN_ERR, &pdev->dev, | |
20d3b647 | 2146 | "pci_enable_msi failed(0X%x)", err); |
a42a1844 EG |
2147 | |
2148 | trans->dev = &pdev->dev; | |
75595536 | 2149 | trans_pcie->irq = pdev->irq; |
a42a1844 | 2150 | trans_pcie->pci_dev = pdev; |
08079a49 | 2151 | trans->hw_rev = iwl_read32(trans, CSR_HW_REV); |
99673ee5 | 2152 | trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; |
9ca85961 EG |
2153 | snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), |
2154 | "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); | |
a42a1844 EG |
2155 | |
2156 | /* TODO: Move this away, not needed if not MSI */ | |
2157 | /* enable rfkill interrupt: hw bug w/a */ | |
2158 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); | |
2159 | if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { | |
2160 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
2161 | pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); | |
2162 | } | |
2163 | ||
69a10b29 MV |
2164 | /* Initialize the wait queue for commands */ |
2165 | init_waitqueue_head(&trans->wait_command_queue); | |
8b5bed90 | 2166 | spin_lock_init(&trans->reg_lock); |
69a10b29 | 2167 | |
a42a1844 EG |
2168 | return trans; |
2169 | ||
2170 | out_pci_release_regions: | |
2171 | pci_release_regions(pdev); | |
2172 | out_pci_disable_device: | |
2173 | pci_disable_device(pdev); | |
2174 | out_no_pci: | |
2175 | kfree(trans); | |
2176 | return NULL; | |
2177 | } |