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c85eb619 EG |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
128e63ef | 8 | * Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved. |
c85eb619 EG |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
22 | * USA | |
23 | * | |
24 | * The full GNU General Public License is included in this distribution | |
25 | * in the file called LICENSE.GPL. | |
26 | * | |
27 | * Contact Information: | |
28 | * Intel Linux Wireless <ilw@linux.intel.com> | |
29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
30 | * | |
31 | * BSD LICENSE | |
32 | * | |
128e63ef | 33 | * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved. |
c85eb619 EG |
34 | * All rights reserved. |
35 | * | |
36 | * Redistribution and use in source and binary forms, with or without | |
37 | * modification, are permitted provided that the following conditions | |
38 | * are met: | |
39 | * | |
40 | * * Redistributions of source code must retain the above copyright | |
41 | * notice, this list of conditions and the following disclaimer. | |
42 | * * Redistributions in binary form must reproduce the above copyright | |
43 | * notice, this list of conditions and the following disclaimer in | |
44 | * the documentation and/or other materials provided with the | |
45 | * distribution. | |
46 | * * Neither the name Intel Corporation nor the names of its | |
47 | * contributors may be used to endorse or promote products derived | |
48 | * from this software without specific prior written permission. | |
49 | * | |
50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
61 | * | |
62 | *****************************************************************************/ | |
a42a1844 EG |
63 | #include <linux/pci.h> |
64 | #include <linux/pci-aspm.h> | |
e6bb4c9c | 65 | #include <linux/interrupt.h> |
87e5666c | 66 | #include <linux/debugfs.h> |
cf614297 | 67 | #include <linux/sched.h> |
6d8f6eeb EG |
68 | #include <linux/bitops.h> |
69 | #include <linux/gfp.h> | |
e6bb4c9c | 70 | |
82575102 | 71 | #include "iwl-drv.h" |
c85eb619 | 72 | #include "iwl-trans.h" |
522376d2 EG |
73 | #include "iwl-csr.h" |
74 | #include "iwl-prph.h" | |
7a10e3e4 | 75 | #include "iwl-agn-hw.h" |
6468a01a | 76 | #include "internal.h" |
0439bb62 | 77 | |
e139dc4a LE |
78 | static void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, |
79 | u32 reg, u32 mask, u32 value) | |
80 | { | |
81 | u32 v; | |
82 | ||
83 | #ifdef CONFIG_IWLWIFI_DEBUG | |
84 | WARN_ON_ONCE(value & ~mask); | |
85 | #endif | |
86 | ||
87 | v = iwl_read32(trans, reg); | |
88 | v &= ~mask; | |
89 | v |= value; | |
90 | iwl_write32(trans, reg, v); | |
91 | } | |
92 | ||
93 | static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans, | |
94 | u32 reg, u32 mask) | |
95 | { | |
96 | __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0); | |
97 | } | |
98 | ||
99 | static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans, | |
100 | u32 reg, u32 mask) | |
101 | { | |
102 | __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask); | |
103 | } | |
104 | ||
ddaf5a5b | 105 | static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) |
392f8b78 | 106 | { |
ddaf5a5b JB |
107 | if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) |
108 | iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, | |
109 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, | |
110 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
111 | else | |
112 | iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, | |
113 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, | |
114 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
392f8b78 EG |
115 | } |
116 | ||
af634bee EG |
117 | /* PCI registers */ |
118 | #define PCI_CFG_RETRY_TIMEOUT 0x041 | |
af634bee | 119 | |
7afe3705 | 120 | static void iwl_pcie_apm_config(struct iwl_trans *trans) |
af634bee | 121 | { |
20d3b647 | 122 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
7afe3705 | 123 | u16 lctl; |
af634bee | 124 | |
af634bee EG |
125 | /* |
126 | * HW bug W/A for instability in PCIe bus L0S->L1 transition. | |
127 | * Check if BIOS (or OS) enabled L1-ASPM on this device. | |
128 | * If so (likely), disable L0S, so device moves directly L0->L1; | |
129 | * costs negligible amount of power savings. | |
130 | * If not (unlikely), enable L0S, so there is at least some | |
131 | * power savings, even without L1. | |
132 | */ | |
7afe3705 | 133 | pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); |
438a0f0a | 134 | if (lctl & PCI_EXP_LNKCTL_ASPM_L1) { |
af634bee EG |
135 | /* L1-ASPM enabled; disable(!) L0S */ |
136 | iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); | |
6a4b09f8 | 137 | dev_info(trans->dev, "L1 Enabled; Disabling L0S\n"); |
af634bee EG |
138 | } else { |
139 | /* L1-ASPM disabled; enable(!) L0S */ | |
140 | iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); | |
6a4b09f8 | 141 | dev_info(trans->dev, "L1 Disabled; Enabling L0S\n"); |
af634bee | 142 | } |
438a0f0a | 143 | trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); |
af634bee EG |
144 | } |
145 | ||
a6c684ee EG |
146 | /* |
147 | * Start up NIC's basic functionality after it has been reset | |
7afe3705 | 148 | * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) |
a6c684ee EG |
149 | * NOTE: This does not load uCode nor start the embedded processor |
150 | */ | |
7afe3705 | 151 | static int iwl_pcie_apm_init(struct iwl_trans *trans) |
a6c684ee | 152 | { |
83626404 | 153 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
a6c684ee EG |
154 | int ret = 0; |
155 | IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); | |
156 | ||
157 | /* | |
158 | * Use "set_bit" below rather than "write", to preserve any hardware | |
159 | * bits already set by default after reset. | |
160 | */ | |
161 | ||
162 | /* Disable L0S exit timer (platform NMI Work/Around) */ | |
163 | iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, | |
20d3b647 | 164 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); |
a6c684ee EG |
165 | |
166 | /* | |
167 | * Disable L0s without affecting L1; | |
168 | * don't wait for ICH L0s (ICH bug W/A) | |
169 | */ | |
170 | iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, | |
20d3b647 | 171 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); |
a6c684ee EG |
172 | |
173 | /* Set FH wait threshold to maximum (HW error during stress W/A) */ | |
174 | iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); | |
175 | ||
176 | /* | |
177 | * Enable HAP INTA (interrupt from management bus) to | |
178 | * wake device's PCI Express link L1a -> L0s | |
179 | */ | |
180 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, | |
20d3b647 | 181 | CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); |
a6c684ee | 182 | |
7afe3705 | 183 | iwl_pcie_apm_config(trans); |
a6c684ee EG |
184 | |
185 | /* Configure analog phase-lock-loop before activating to D0A */ | |
035f7ff2 | 186 | if (trans->cfg->base_params->pll_cfg_val) |
a6c684ee | 187 | iwl_set_bit(trans, CSR_ANA_PLL_CFG, |
035f7ff2 | 188 | trans->cfg->base_params->pll_cfg_val); |
a6c684ee EG |
189 | |
190 | /* | |
191 | * Set "initialization complete" bit to move adapter from | |
192 | * D0U* --> D0A* (powered-up active) state. | |
193 | */ | |
194 | iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
195 | ||
196 | /* | |
197 | * Wait for clock stabilization; once stabilized, access to | |
198 | * device-internal resources is supported, e.g. iwl_write_prph() | |
199 | * and accesses to uCode SRAM. | |
200 | */ | |
201 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
20d3b647 JB |
202 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, |
203 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
a6c684ee EG |
204 | if (ret < 0) { |
205 | IWL_DEBUG_INFO(trans, "Failed to init the card\n"); | |
206 | goto out; | |
207 | } | |
208 | ||
209 | /* | |
210 | * Enable DMA clock and wait for it to stabilize. | |
211 | * | |
212 | * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits | |
213 | * do not disable clocks. This preserves any hardware bits already | |
214 | * set by default in "CLK_CTRL_REG" after reset. | |
215 | */ | |
216 | iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); | |
217 | udelay(20); | |
218 | ||
219 | /* Disable L1-Active */ | |
220 | iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
221 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
222 | ||
83626404 | 223 | set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status); |
a6c684ee EG |
224 | |
225 | out: | |
226 | return ret; | |
227 | } | |
228 | ||
7afe3705 | 229 | static int iwl_pcie_apm_stop_master(struct iwl_trans *trans) |
cc56feb2 EG |
230 | { |
231 | int ret = 0; | |
232 | ||
233 | /* stop device's busmaster DMA activity */ | |
234 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); | |
235 | ||
236 | ret = iwl_poll_bit(trans, CSR_RESET, | |
20d3b647 JB |
237 | CSR_RESET_REG_FLAG_MASTER_DISABLED, |
238 | CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); | |
cc56feb2 EG |
239 | if (ret) |
240 | IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); | |
241 | ||
242 | IWL_DEBUG_INFO(trans, "stop master\n"); | |
243 | ||
244 | return ret; | |
245 | } | |
246 | ||
7afe3705 | 247 | static void iwl_pcie_apm_stop(struct iwl_trans *trans) |
cc56feb2 | 248 | { |
83626404 | 249 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
cc56feb2 EG |
250 | IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); |
251 | ||
83626404 | 252 | clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status); |
cc56feb2 EG |
253 | |
254 | /* Stop device's DMA activity */ | |
7afe3705 | 255 | iwl_pcie_apm_stop_master(trans); |
cc56feb2 EG |
256 | |
257 | /* Reset the entire device */ | |
258 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
259 | ||
260 | udelay(10); | |
261 | ||
262 | /* | |
263 | * Clear "initialization complete" bit to move adapter from | |
264 | * D0A* (powered-up Active) --> D0U* (Uninitialized) state. | |
265 | */ | |
266 | iwl_clear_bit(trans, CSR_GP_CNTRL, | |
267 | CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
268 | } | |
269 | ||
7afe3705 | 270 | static int iwl_pcie_nic_init(struct iwl_trans *trans) |
392f8b78 | 271 | { |
7b11488f | 272 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
392f8b78 EG |
273 | unsigned long flags; |
274 | ||
275 | /* nic_init */ | |
7b11488f | 276 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
7afe3705 | 277 | iwl_pcie_apm_init(trans); |
392f8b78 EG |
278 | |
279 | /* Set interrupt coalescing calibration timer to default (512 usecs) */ | |
20d3b647 | 280 | iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF); |
392f8b78 | 281 | |
7b11488f | 282 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
392f8b78 | 283 | |
ddaf5a5b | 284 | iwl_pcie_set_pwr(trans, false); |
392f8b78 | 285 | |
ecdb975c | 286 | iwl_op_mode_nic_config(trans->op_mode); |
392f8b78 EG |
287 | |
288 | /* Allocate the RX queue, or reset if it is already allocated */ | |
9805c446 | 289 | iwl_pcie_rx_init(trans); |
392f8b78 EG |
290 | |
291 | /* Allocate or reset and init all Tx and Command queues */ | |
f02831be | 292 | if (iwl_pcie_tx_init(trans)) |
392f8b78 EG |
293 | return -ENOMEM; |
294 | ||
035f7ff2 | 295 | if (trans->cfg->base_params->shadow_reg_enable) { |
392f8b78 | 296 | /* enable shadow regs in HW */ |
20d3b647 | 297 | iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); |
d38069d1 | 298 | IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); |
392f8b78 EG |
299 | } |
300 | ||
392f8b78 EG |
301 | return 0; |
302 | } | |
303 | ||
304 | #define HW_READY_TIMEOUT (50) | |
305 | ||
306 | /* Note: returns poll_bit return value, which is >= 0 if success */ | |
7afe3705 | 307 | static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) |
392f8b78 EG |
308 | { |
309 | int ret; | |
310 | ||
1042db2a | 311 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 | 312 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); |
392f8b78 EG |
313 | |
314 | /* See if we got it */ | |
1042db2a | 315 | ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 JB |
316 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, |
317 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
318 | HW_READY_TIMEOUT); | |
392f8b78 | 319 | |
6d8f6eeb | 320 | IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); |
392f8b78 EG |
321 | return ret; |
322 | } | |
323 | ||
324 | /* Note: returns standard 0/-ERROR code */ | |
7afe3705 | 325 | static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) |
392f8b78 EG |
326 | { |
327 | int ret; | |
289e5501 | 328 | int t = 0; |
392f8b78 | 329 | |
6d8f6eeb | 330 | IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); |
392f8b78 | 331 | |
7afe3705 | 332 | ret = iwl_pcie_set_hw_ready(trans); |
ebb7678d | 333 | /* If the card is ready, exit 0 */ |
392f8b78 EG |
334 | if (ret >= 0) |
335 | return 0; | |
336 | ||
337 | /* If HW is not ready, prepare the conditions to check again */ | |
1042db2a | 338 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 | 339 | CSR_HW_IF_CONFIG_REG_PREPARE); |
392f8b78 | 340 | |
289e5501 | 341 | do { |
7afe3705 | 342 | ret = iwl_pcie_set_hw_ready(trans); |
289e5501 EG |
343 | if (ret >= 0) |
344 | return 0; | |
392f8b78 | 345 | |
289e5501 EG |
346 | usleep_range(200, 1000); |
347 | t += 200; | |
348 | } while (t < 150000); | |
392f8b78 | 349 | |
392f8b78 EG |
350 | return ret; |
351 | } | |
352 | ||
cf614297 EG |
353 | /* |
354 | * ucode | |
355 | */ | |
7afe3705 | 356 | static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr, |
83f84d7b | 357 | dma_addr_t phy_addr, u32 byte_cnt) |
cf614297 | 358 | { |
13df1aab | 359 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
cf614297 EG |
360 | int ret; |
361 | ||
13df1aab | 362 | trans_pcie->ucode_write_complete = false; |
cf614297 EG |
363 | |
364 | iwl_write_direct32(trans, | |
20d3b647 JB |
365 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), |
366 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); | |
cf614297 EG |
367 | |
368 | iwl_write_direct32(trans, | |
20d3b647 JB |
369 | FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), |
370 | dst_addr); | |
cf614297 EG |
371 | |
372 | iwl_write_direct32(trans, | |
83f84d7b JB |
373 | FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), |
374 | phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); | |
cf614297 EG |
375 | |
376 | iwl_write_direct32(trans, | |
20d3b647 JB |
377 | FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), |
378 | (iwl_get_dma_hi_addr(phy_addr) | |
379 | << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); | |
cf614297 EG |
380 | |
381 | iwl_write_direct32(trans, | |
20d3b647 JB |
382 | FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), |
383 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | | |
384 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | | |
385 | FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); | |
cf614297 EG |
386 | |
387 | iwl_write_direct32(trans, | |
20d3b647 JB |
388 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), |
389 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
390 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | | |
391 | FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); | |
cf614297 | 392 | |
13df1aab JB |
393 | ret = wait_event_timeout(trans_pcie->ucode_write_waitq, |
394 | trans_pcie->ucode_write_complete, 5 * HZ); | |
cf614297 | 395 | if (!ret) { |
83f84d7b | 396 | IWL_ERR(trans, "Failed to load firmware chunk!\n"); |
cf614297 EG |
397 | return -ETIMEDOUT; |
398 | } | |
399 | ||
400 | return 0; | |
401 | } | |
402 | ||
7afe3705 | 403 | static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, |
83f84d7b | 404 | const struct fw_desc *section) |
cf614297 | 405 | { |
83f84d7b JB |
406 | u8 *v_addr; |
407 | dma_addr_t p_addr; | |
408 | u32 offset; | |
cf614297 EG |
409 | int ret = 0; |
410 | ||
83f84d7b JB |
411 | IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", |
412 | section_num); | |
413 | ||
414 | v_addr = dma_alloc_coherent(trans->dev, PAGE_SIZE, &p_addr, GFP_KERNEL); | |
415 | if (!v_addr) | |
416 | return -ENOMEM; | |
417 | ||
418 | for (offset = 0; offset < section->len; offset += PAGE_SIZE) { | |
419 | u32 copy_size; | |
420 | ||
421 | copy_size = min_t(u32, PAGE_SIZE, section->len - offset); | |
cf614297 | 422 | |
83f84d7b | 423 | memcpy(v_addr, (u8 *)section->data + offset, copy_size); |
7afe3705 EG |
424 | ret = iwl_pcie_load_firmware_chunk(trans, |
425 | section->offset + offset, | |
426 | p_addr, copy_size); | |
83f84d7b JB |
427 | if (ret) { |
428 | IWL_ERR(trans, | |
429 | "Could not load the [%d] uCode section\n", | |
430 | section_num); | |
431 | break; | |
6dfa8d01 | 432 | } |
83f84d7b JB |
433 | } |
434 | ||
435 | dma_free_coherent(trans->dev, PAGE_SIZE, v_addr, p_addr); | |
436 | return ret; | |
437 | } | |
438 | ||
7afe3705 | 439 | static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, |
0692fe41 | 440 | const struct fw_img *image) |
cf614297 | 441 | { |
2d1c0044 | 442 | int i, ret = 0; |
cf614297 | 443 | |
2d1c0044 | 444 | for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) { |
83f84d7b | 445 | if (!image->sec[i].data) |
2d1c0044 | 446 | break; |
cf614297 | 447 | |
7afe3705 | 448 | ret = iwl_pcie_load_section(trans, i, &image->sec[i]); |
2d1c0044 JB |
449 | if (ret) |
450 | return ret; | |
451 | } | |
cf614297 EG |
452 | |
453 | /* Remove all resets to allow NIC to operate */ | |
454 | iwl_write32(trans, CSR_RESET, 0); | |
455 | ||
456 | return 0; | |
457 | } | |
458 | ||
0692fe41 | 459 | static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, |
6ae02f3e | 460 | const struct fw_img *fw, bool run_in_rfkill) |
392f8b78 | 461 | { |
d18aa87f | 462 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
392f8b78 | 463 | int ret; |
c9eec95c | 464 | bool hw_rfkill; |
392f8b78 | 465 | |
496bab39 | 466 | /* This may fail if AMT took ownership of the device */ |
7afe3705 | 467 | if (iwl_pcie_prepare_card_hw(trans)) { |
6d8f6eeb | 468 | IWL_WARN(trans, "Exit HW not ready\n"); |
392f8b78 EG |
469 | return -EIO; |
470 | } | |
471 | ||
d18aa87f JB |
472 | clear_bit(STATUS_FW_ERROR, &trans_pcie->status); |
473 | ||
8c46bb70 EG |
474 | iwl_enable_rfkill_int(trans); |
475 | ||
392f8b78 | 476 | /* If platform's RF_KILL switch is NOT set to KILL */ |
8d425517 | 477 | hw_rfkill = iwl_is_rfkill_set(trans); |
c9eec95c | 478 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); |
6ae02f3e | 479 | if (hw_rfkill && !run_in_rfkill) |
392f8b78 | 480 | return -ERFKILL; |
392f8b78 | 481 | |
1042db2a | 482 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); |
392f8b78 | 483 | |
7afe3705 | 484 | ret = iwl_pcie_nic_init(trans); |
392f8b78 | 485 | if (ret) { |
6d8f6eeb | 486 | IWL_ERR(trans, "Unable to init nic\n"); |
392f8b78 EG |
487 | return ret; |
488 | } | |
489 | ||
490 | /* make sure rfkill handshake bits are cleared */ | |
1042db2a EG |
491 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
492 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, | |
392f8b78 EG |
493 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
494 | ||
495 | /* clear (again), then enable host interrupts */ | |
1042db2a | 496 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); |
6d8f6eeb | 497 | iwl_enable_interrupts(trans); |
392f8b78 EG |
498 | |
499 | /* really make sure rfkill handshake bits are cleared */ | |
1042db2a EG |
500 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
501 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
392f8b78 | 502 | |
cf614297 | 503 | /* Load the given image to the HW */ |
7afe3705 | 504 | return iwl_pcie_load_given_ucode(trans, fw); |
b3c2ce13 EG |
505 | } |
506 | ||
adca1235 | 507 | static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) |
ed6a3803 | 508 | { |
990aa6d7 | 509 | iwl_pcie_reset_ict(trans); |
f02831be | 510 | iwl_pcie_tx_start(trans, scd_addr); |
c170b867 EG |
511 | } |
512 | ||
43e58856 | 513 | static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) |
ae2c30bf | 514 | { |
43e58856 | 515 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
20d3b647 | 516 | unsigned long flags; |
ae2c30bf | 517 | |
43e58856 | 518 | /* tell the device to stop sending interrupts */ |
7b11488f | 519 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
ae2c30bf | 520 | iwl_disable_interrupts(trans); |
7b11488f | 521 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
ae2c30bf | 522 | |
ab6cf8e8 | 523 | /* device going down, Stop using ICT table */ |
990aa6d7 | 524 | iwl_pcie_disable_ict(trans); |
ab6cf8e8 EG |
525 | |
526 | /* | |
527 | * If a HW restart happens during firmware loading, | |
528 | * then the firmware loading might call this function | |
529 | * and later it might be called again due to the | |
530 | * restart. So don't process again if the device is | |
531 | * already dead. | |
532 | */ | |
83626404 | 533 | if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) { |
f02831be | 534 | iwl_pcie_tx_stop(trans); |
9805c446 | 535 | iwl_pcie_rx_stop(trans); |
6379103e | 536 | |
ab6cf8e8 | 537 | /* Power-down device's busmaster DMA clocks */ |
1042db2a | 538 | iwl_write_prph(trans, APMG_CLK_DIS_REG, |
ab6cf8e8 EG |
539 | APMG_CLK_VAL_DMA_CLK_RQT); |
540 | udelay(5); | |
541 | } | |
542 | ||
543 | /* Make sure (redundant) we've released our request to stay awake */ | |
1042db2a | 544 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
20d3b647 | 545 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
ab6cf8e8 EG |
546 | |
547 | /* Stop the device, and put it in low power state */ | |
7afe3705 | 548 | iwl_pcie_apm_stop(trans); |
43e58856 EG |
549 | |
550 | /* Upon stop, the APM issues an interrupt if HW RF kill is set. | |
551 | * Clean again the interrupt here | |
552 | */ | |
7b11488f | 553 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
43e58856 | 554 | iwl_disable_interrupts(trans); |
7b11488f | 555 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
43e58856 | 556 | |
218733cf EG |
557 | iwl_enable_rfkill_int(trans); |
558 | ||
43e58856 | 559 | /* stop and reset the on-board processor */ |
1042db2a | 560 | iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
74fda971 DF |
561 | |
562 | /* clear all status bits */ | |
563 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); | |
564 | clear_bit(STATUS_INT_ENABLED, &trans_pcie->status); | |
565 | clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status); | |
01d651d4 | 566 | clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status); |
f946b529 | 567 | clear_bit(STATUS_RFKILL, &trans_pcie->status); |
ab6cf8e8 EG |
568 | } |
569 | ||
ddaf5a5b | 570 | static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans) |
2dd4f9f7 JB |
571 | { |
572 | /* let the ucode operate on its own */ | |
573 | iwl_write32(trans, CSR_UCODE_DRV_GP1_SET, | |
574 | CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE); | |
575 | ||
576 | iwl_disable_interrupts(trans); | |
ddaf5a5b JB |
577 | iwl_pcie_disable_ict(trans); |
578 | ||
2dd4f9f7 JB |
579 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
580 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
ddaf5a5b JB |
581 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
582 | CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
583 | ||
584 | /* | |
585 | * reset TX queues -- some of their registers reset during S3 | |
586 | * so if we don't reset everything here the D3 image would try | |
587 | * to execute some invalid memory upon resume | |
588 | */ | |
589 | iwl_trans_pcie_tx_reset(trans); | |
590 | ||
591 | iwl_pcie_set_pwr(trans, true); | |
592 | } | |
593 | ||
594 | static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, | |
595 | enum iwl_d3_status *status) | |
596 | { | |
597 | u32 val; | |
598 | int ret; | |
599 | ||
600 | iwl_pcie_set_pwr(trans, false); | |
601 | ||
602 | val = iwl_read32(trans, CSR_RESET); | |
603 | if (val & CSR_RESET_REG_FLAG_NEVO_RESET) { | |
604 | *status = IWL_D3_STATUS_RESET; | |
605 | return 0; | |
606 | } | |
607 | ||
608 | /* | |
609 | * Also enables interrupts - none will happen as the device doesn't | |
610 | * know we're waking it up, only when the opmode actually tells it | |
611 | * after this call. | |
612 | */ | |
613 | iwl_pcie_reset_ict(trans); | |
614 | ||
615 | iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
616 | iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
617 | ||
618 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
619 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
620 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
621 | 25000); | |
622 | if (ret) { | |
623 | IWL_ERR(trans, "Failed to resume the device (mac ready)\n"); | |
624 | return ret; | |
625 | } | |
626 | ||
627 | iwl_trans_pcie_tx_reset(trans); | |
628 | ||
629 | ret = iwl_pcie_rx_init(trans); | |
630 | if (ret) { | |
631 | IWL_ERR(trans, "Failed to resume the device (RX reset)\n"); | |
632 | return ret; | |
633 | } | |
634 | ||
635 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, | |
636 | CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE); | |
637 | ||
638 | *status = IWL_D3_STATUS_ALIVE; | |
639 | return 0; | |
2dd4f9f7 JB |
640 | } |
641 | ||
57a1dc89 | 642 | static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) |
e6bb4c9c | 643 | { |
c9eec95c | 644 | bool hw_rfkill; |
a8b691e6 | 645 | int err; |
e6bb4c9c | 646 | |
7afe3705 | 647 | err = iwl_pcie_prepare_card_hw(trans); |
ebb7678d | 648 | if (err) { |
d6f1c316 | 649 | IWL_ERR(trans, "Error while preparing HW: %d\n", err); |
a8b691e6 | 650 | return err; |
ebb7678d | 651 | } |
a6c684ee | 652 | |
7afe3705 | 653 | iwl_pcie_apm_init(trans); |
a6c684ee | 654 | |
226c02ca EG |
655 | /* From now on, the op_mode will be kept updated about RF kill state */ |
656 | iwl_enable_rfkill_int(trans); | |
657 | ||
8d425517 | 658 | hw_rfkill = iwl_is_rfkill_set(trans); |
c9eec95c | 659 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); |
d48e2074 | 660 | |
a8b691e6 | 661 | return 0; |
e6bb4c9c EG |
662 | } |
663 | ||
218733cf EG |
664 | static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans, |
665 | bool op_mode_leaving) | |
cc56feb2 | 666 | { |
20d3b647 | 667 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
d23f78e6 | 668 | bool hw_rfkill; |
218733cf | 669 | unsigned long flags; |
d23f78e6 | 670 | |
ee7d737c DS |
671 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
672 | iwl_disable_interrupts(trans); | |
673 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); | |
674 | ||
7afe3705 | 675 | iwl_pcie_apm_stop(trans); |
cc56feb2 | 676 | |
218733cf EG |
677 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
678 | iwl_disable_interrupts(trans); | |
679 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); | |
1df06bdc | 680 | |
8d96bb61 EG |
681 | iwl_pcie_disable_ict(trans); |
682 | ||
218733cf EG |
683 | if (!op_mode_leaving) { |
684 | /* | |
685 | * Even if we stop the HW, we still want the RF kill | |
686 | * interrupt | |
687 | */ | |
688 | iwl_enable_rfkill_int(trans); | |
689 | ||
690 | /* | |
691 | * Check again since the RF kill state may have changed while | |
692 | * all the interrupts were disabled, in this case we couldn't | |
693 | * receive the RF kill interrupt and update the state in the | |
694 | * op_mode. | |
695 | */ | |
696 | hw_rfkill = iwl_is_rfkill_set(trans); | |
697 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); | |
698 | } | |
cc56feb2 EG |
699 | } |
700 | ||
03905495 EG |
701 | static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) |
702 | { | |
05f5b97e | 703 | writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
704 | } |
705 | ||
706 | static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) | |
707 | { | |
05f5b97e | 708 | writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
709 | } |
710 | ||
711 | static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) | |
712 | { | |
05f5b97e | 713 | return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
714 | } |
715 | ||
6a06b6c1 EG |
716 | static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) |
717 | { | |
718 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, reg | (3 << 24)); | |
719 | return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); | |
720 | } | |
721 | ||
722 | static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, | |
723 | u32 val) | |
724 | { | |
725 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, | |
726 | ((addr & 0x0000FFFF) | (3 << 24))); | |
727 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); | |
728 | } | |
729 | ||
c6f600fc | 730 | static void iwl_trans_pcie_configure(struct iwl_trans *trans, |
9eae88fa | 731 | const struct iwl_trans_config *trans_cfg) |
c6f600fc MV |
732 | { |
733 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
734 | ||
735 | trans_pcie->cmd_queue = trans_cfg->cmd_queue; | |
b04db9ac | 736 | trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; |
d663ee73 JB |
737 | if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) |
738 | trans_pcie->n_no_reclaim_cmds = 0; | |
739 | else | |
740 | trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; | |
741 | if (trans_pcie->n_no_reclaim_cmds) | |
742 | memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, | |
743 | trans_pcie->n_no_reclaim_cmds * sizeof(u8)); | |
9eae88fa | 744 | |
b2cf410c JB |
745 | trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k; |
746 | if (trans_pcie->rx_buf_size_8k) | |
747 | trans_pcie->rx_page_order = get_order(8 * 1024); | |
748 | else | |
749 | trans_pcie->rx_page_order = get_order(4 * 1024); | |
7c5ba4a8 JB |
750 | |
751 | trans_pcie->wd_timeout = | |
752 | msecs_to_jiffies(trans_cfg->queue_watchdog_timeout); | |
d9fb6465 JB |
753 | |
754 | trans_pcie->command_names = trans_cfg->command_names; | |
046db346 | 755 | trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; |
c6f600fc MV |
756 | } |
757 | ||
d1ff5253 | 758 | void iwl_trans_pcie_free(struct iwl_trans *trans) |
34c1b7ba | 759 | { |
20d3b647 | 760 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
a42a1844 | 761 | |
0aa86df6 | 762 | synchronize_irq(trans_pcie->pci_dev->irq); |
0aa86df6 | 763 | |
f02831be | 764 | iwl_pcie_tx_free(trans); |
9805c446 | 765 | iwl_pcie_rx_free(trans); |
6379103e | 766 | |
a8b691e6 JB |
767 | free_irq(trans_pcie->pci_dev->irq, trans); |
768 | iwl_pcie_free_ict(trans); | |
a42a1844 EG |
769 | |
770 | pci_disable_msi(trans_pcie->pci_dev); | |
05f5b97e | 771 | iounmap(trans_pcie->hw_base); |
a42a1844 EG |
772 | pci_release_regions(trans_pcie->pci_dev); |
773 | pci_disable_device(trans_pcie->pci_dev); | |
59c647b6 | 774 | kmem_cache_destroy(trans->dev_cmd_pool); |
a42a1844 | 775 | |
6d8f6eeb | 776 | kfree(trans); |
34c1b7ba EG |
777 | } |
778 | ||
47107e84 DF |
779 | static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) |
780 | { | |
781 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
782 | ||
783 | if (state) | |
01d651d4 | 784 | set_bit(STATUS_TPOWER_PMI, &trans_pcie->status); |
47107e84 | 785 | else |
01d651d4 | 786 | clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status); |
47107e84 DF |
787 | } |
788 | ||
c01a4047 | 789 | #ifdef CONFIG_PM_SLEEP |
57210f7c EG |
790 | static int iwl_trans_pcie_suspend(struct iwl_trans *trans) |
791 | { | |
57210f7c EG |
792 | return 0; |
793 | } | |
794 | ||
795 | static int iwl_trans_pcie_resume(struct iwl_trans *trans) | |
796 | { | |
c9eec95c | 797 | bool hw_rfkill; |
57210f7c | 798 | |
8c46bb70 EG |
799 | iwl_enable_rfkill_int(trans); |
800 | ||
8d425517 | 801 | hw_rfkill = iwl_is_rfkill_set(trans); |
8c46bb70 | 802 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); |
8722c899 | 803 | |
57210f7c EG |
804 | return 0; |
805 | } | |
c01a4047 | 806 | #endif /* CONFIG_PM_SLEEP */ |
57210f7c | 807 | |
e56b04ef LE |
808 | static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent, |
809 | unsigned long *flags) | |
7a65d170 EG |
810 | { |
811 | int ret; | |
e56b04ef LE |
812 | struct iwl_trans_pcie *pcie_trans = IWL_TRANS_GET_PCIE_TRANS(trans); |
813 | spin_lock_irqsave(&pcie_trans->reg_lock, *flags); | |
7a65d170 EG |
814 | |
815 | /* this bit wakes up the NIC */ | |
e139dc4a LE |
816 | __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, |
817 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
7a65d170 EG |
818 | |
819 | /* | |
820 | * These bits say the device is running, and should keep running for | |
821 | * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), | |
822 | * but they do not indicate that embedded SRAM is restored yet; | |
823 | * 3945 and 4965 have volatile SRAM, and must save/restore contents | |
824 | * to/from host DRAM when sleeping/waking for power-saving. | |
825 | * Each direction takes approximately 1/4 millisecond; with this | |
826 | * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a | |
827 | * series of register accesses are expected (e.g. reading Event Log), | |
828 | * to keep device from sleeping. | |
829 | * | |
830 | * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that | |
831 | * SRAM is okay/restored. We don't check that here because this call | |
832 | * is just for hardware register access; but GP1 MAC_SLEEP check is a | |
833 | * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log). | |
834 | * | |
835 | * 5000 series and later (including 1000 series) have non-volatile SRAM, | |
836 | * and do not save/restore SRAM when power cycling. | |
837 | */ | |
838 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
839 | CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, | |
840 | (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | | |
841 | CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); | |
842 | if (unlikely(ret < 0)) { | |
843 | iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI); | |
844 | if (!silent) { | |
845 | u32 val = iwl_read32(trans, CSR_GP_CNTRL); | |
846 | WARN_ONCE(1, | |
847 | "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", | |
848 | val); | |
e56b04ef | 849 | spin_unlock_irqrestore(&pcie_trans->reg_lock, *flags); |
7a65d170 EG |
850 | return false; |
851 | } | |
852 | } | |
853 | ||
e56b04ef LE |
854 | /* |
855 | * Fool sparse by faking we release the lock - sparse will | |
856 | * track nic_access anyway. | |
857 | */ | |
858 | __release(&pcie_trans->reg_lock); | |
7a65d170 EG |
859 | return true; |
860 | } | |
861 | ||
e56b04ef LE |
862 | static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, |
863 | unsigned long *flags) | |
7a65d170 | 864 | { |
e56b04ef LE |
865 | struct iwl_trans_pcie *pcie_trans = IWL_TRANS_GET_PCIE_TRANS(trans); |
866 | ||
867 | lockdep_assert_held(&pcie_trans->reg_lock); | |
868 | ||
869 | /* | |
870 | * Fool sparse by faking we acquiring the lock - sparse will | |
871 | * track nic_access anyway. | |
872 | */ | |
873 | __acquire(&pcie_trans->reg_lock); | |
874 | ||
e139dc4a LE |
875 | __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, |
876 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
7a65d170 EG |
877 | /* |
878 | * Above we read the CSR_GP_CNTRL register, which will flush | |
879 | * any previous writes, but we need the write that clears the | |
880 | * MAC_ACCESS_REQ bit to be performed before any other writes | |
881 | * scheduled on different CPUs (after we drop reg_lock). | |
882 | */ | |
883 | mmiowb(); | |
e56b04ef | 884 | spin_unlock_irqrestore(&pcie_trans->reg_lock, *flags); |
7a65d170 EG |
885 | } |
886 | ||
4fd442db EG |
887 | static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, |
888 | void *buf, int dwords) | |
889 | { | |
890 | unsigned long flags; | |
891 | int offs, ret = 0; | |
892 | u32 *vals = buf; | |
893 | ||
e56b04ef | 894 | if (iwl_trans_grab_nic_access(trans, false, &flags)) { |
4fd442db EG |
895 | iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); |
896 | for (offs = 0; offs < dwords; offs++) | |
897 | vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); | |
e56b04ef | 898 | iwl_trans_release_nic_access(trans, &flags); |
4fd442db EG |
899 | } else { |
900 | ret = -EBUSY; | |
901 | } | |
4fd442db EG |
902 | return ret; |
903 | } | |
904 | ||
905 | static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, | |
906 | void *buf, int dwords) | |
907 | { | |
908 | unsigned long flags; | |
909 | int offs, ret = 0; | |
910 | u32 *vals = buf; | |
911 | ||
e56b04ef | 912 | if (iwl_trans_grab_nic_access(trans, false, &flags)) { |
4fd442db EG |
913 | iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); |
914 | for (offs = 0; offs < dwords; offs++) | |
01387ffd EG |
915 | iwl_write32(trans, HBUS_TARG_MEM_WDAT, |
916 | vals ? vals[offs] : 0); | |
e56b04ef | 917 | iwl_trans_release_nic_access(trans, &flags); |
4fd442db EG |
918 | } else { |
919 | ret = -EBUSY; | |
920 | } | |
4fd442db EG |
921 | return ret; |
922 | } | |
7a65d170 | 923 | |
5f178cd2 EG |
924 | #define IWL_FLUSH_WAIT_MS 2000 |
925 | ||
990aa6d7 | 926 | static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans) |
5f178cd2 | 927 | { |
8ad71bef | 928 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 929 | struct iwl_txq *txq; |
5f178cd2 EG |
930 | struct iwl_queue *q; |
931 | int cnt; | |
932 | unsigned long now = jiffies; | |
1c3fea82 EG |
933 | u32 scd_sram_addr; |
934 | u8 buf[16]; | |
5f178cd2 EG |
935 | int ret = 0; |
936 | ||
937 | /* waiting for all the tx frames complete might take a while */ | |
035f7ff2 | 938 | for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { |
9ba1947a | 939 | if (cnt == trans_pcie->cmd_queue) |
5f178cd2 | 940 | continue; |
8ad71bef | 941 | txq = &trans_pcie->txq[cnt]; |
5f178cd2 EG |
942 | q = &txq->q; |
943 | while (q->read_ptr != q->write_ptr && !time_after(jiffies, | |
944 | now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) | |
945 | msleep(1); | |
946 | ||
947 | if (q->read_ptr != q->write_ptr) { | |
1c3fea82 EG |
948 | IWL_ERR(trans, |
949 | "fail to flush all tx fifo queues Q %d\n", cnt); | |
5f178cd2 EG |
950 | ret = -ETIMEDOUT; |
951 | break; | |
952 | } | |
953 | } | |
1c3fea82 EG |
954 | |
955 | if (!ret) | |
956 | return 0; | |
957 | ||
958 | IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", | |
959 | txq->q.read_ptr, txq->q.write_ptr); | |
960 | ||
961 | scd_sram_addr = trans_pcie->scd_base_addr + | |
962 | SCD_TX_STTS_QUEUE_OFFSET(txq->q.id); | |
963 | iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf)); | |
964 | ||
965 | iwl_print_hex_error(trans, buf, sizeof(buf)); | |
966 | ||
967 | for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++) | |
968 | IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt, | |
969 | iwl_read_direct32(trans, FH_TX_TRB_REG(cnt))); | |
970 | ||
971 | for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { | |
972 | u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt)); | |
973 | u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; | |
974 | bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); | |
975 | u32 tbl_dw = | |
976 | iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr + | |
977 | SCD_TRANS_TBL_OFFSET_QUEUE(cnt)); | |
978 | ||
979 | if (cnt & 0x1) | |
980 | tbl_dw = (tbl_dw & 0xFFFF0000) >> 16; | |
981 | else | |
982 | tbl_dw = tbl_dw & 0x0000FFFF; | |
983 | ||
984 | IWL_ERR(trans, | |
985 | "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n", | |
986 | cnt, active ? "" : "in", fifo, tbl_dw, | |
987 | iwl_read_prph(trans, | |
988 | SCD_QUEUE_RDPTR(cnt)) & (txq->q.n_bd - 1), | |
989 | iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt))); | |
990 | } | |
991 | ||
5f178cd2 EG |
992 | return ret; |
993 | } | |
994 | ||
e139dc4a LE |
995 | static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, |
996 | u32 mask, u32 value) | |
997 | { | |
e56b04ef | 998 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
e139dc4a LE |
999 | unsigned long flags; |
1000 | ||
e56b04ef | 1001 | spin_lock_irqsave(&trans_pcie->reg_lock, flags); |
e139dc4a | 1002 | __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); |
e56b04ef | 1003 | spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); |
e139dc4a LE |
1004 | } |
1005 | ||
ff620849 EG |
1006 | static const char *get_fh_string(int cmd) |
1007 | { | |
d9fb6465 | 1008 | #define IWL_CMD(x) case x: return #x |
ff620849 EG |
1009 | switch (cmd) { |
1010 | IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG); | |
1011 | IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG); | |
1012 | IWL_CMD(FH_RSCSR_CHNL0_WPTR); | |
1013 | IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG); | |
1014 | IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG); | |
1015 | IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG); | |
1016 | IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV); | |
1017 | IWL_CMD(FH_TSSR_TX_STATUS_REG); | |
1018 | IWL_CMD(FH_TSSR_TX_ERROR_REG); | |
1019 | default: | |
1020 | return "UNKNOWN"; | |
1021 | } | |
d9fb6465 | 1022 | #undef IWL_CMD |
ff620849 EG |
1023 | } |
1024 | ||
990aa6d7 | 1025 | int iwl_pcie_dump_fh(struct iwl_trans *trans, char **buf) |
ff620849 EG |
1026 | { |
1027 | int i; | |
ff620849 EG |
1028 | static const u32 fh_tbl[] = { |
1029 | FH_RSCSR_CHNL0_STTS_WPTR_REG, | |
1030 | FH_RSCSR_CHNL0_RBDCB_BASE_REG, | |
1031 | FH_RSCSR_CHNL0_WPTR, | |
1032 | FH_MEM_RCSR_CHNL0_CONFIG_REG, | |
1033 | FH_MEM_RSSR_SHARED_CTRL_REG, | |
1034 | FH_MEM_RSSR_RX_STATUS_REG, | |
1035 | FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV, | |
1036 | FH_TSSR_TX_STATUS_REG, | |
1037 | FH_TSSR_TX_ERROR_REG | |
1038 | }; | |
94543a8d JB |
1039 | |
1040 | #ifdef CONFIG_IWLWIFI_DEBUGFS | |
1041 | if (buf) { | |
1042 | int pos = 0; | |
1043 | size_t bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40; | |
1044 | ||
ff620849 EG |
1045 | *buf = kmalloc(bufsz, GFP_KERNEL); |
1046 | if (!*buf) | |
1047 | return -ENOMEM; | |
94543a8d | 1048 | |
ff620849 EG |
1049 | pos += scnprintf(*buf + pos, bufsz - pos, |
1050 | "FH register values:\n"); | |
94543a8d JB |
1051 | |
1052 | for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) | |
ff620849 EG |
1053 | pos += scnprintf(*buf + pos, bufsz - pos, |
1054 | " %34s: 0X%08x\n", | |
1055 | get_fh_string(fh_tbl[i]), | |
1042db2a | 1056 | iwl_read_direct32(trans, fh_tbl[i])); |
94543a8d | 1057 | |
ff620849 EG |
1058 | return pos; |
1059 | } | |
1060 | #endif | |
94543a8d | 1061 | |
ff620849 | 1062 | IWL_ERR(trans, "FH register values:\n"); |
94543a8d | 1063 | for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) |
ff620849 EG |
1064 | IWL_ERR(trans, " %34s: 0X%08x\n", |
1065 | get_fh_string(fh_tbl[i]), | |
1042db2a | 1066 | iwl_read_direct32(trans, fh_tbl[i])); |
94543a8d | 1067 | |
ff620849 EG |
1068 | return 0; |
1069 | } | |
1070 | ||
1071 | static const char *get_csr_string(int cmd) | |
1072 | { | |
d9fb6465 | 1073 | #define IWL_CMD(x) case x: return #x |
ff620849 EG |
1074 | switch (cmd) { |
1075 | IWL_CMD(CSR_HW_IF_CONFIG_REG); | |
1076 | IWL_CMD(CSR_INT_COALESCING); | |
1077 | IWL_CMD(CSR_INT); | |
1078 | IWL_CMD(CSR_INT_MASK); | |
1079 | IWL_CMD(CSR_FH_INT_STATUS); | |
1080 | IWL_CMD(CSR_GPIO_IN); | |
1081 | IWL_CMD(CSR_RESET); | |
1082 | IWL_CMD(CSR_GP_CNTRL); | |
1083 | IWL_CMD(CSR_HW_REV); | |
1084 | IWL_CMD(CSR_EEPROM_REG); | |
1085 | IWL_CMD(CSR_EEPROM_GP); | |
1086 | IWL_CMD(CSR_OTP_GP_REG); | |
1087 | IWL_CMD(CSR_GIO_REG); | |
1088 | IWL_CMD(CSR_GP_UCODE_REG); | |
1089 | IWL_CMD(CSR_GP_DRIVER_REG); | |
1090 | IWL_CMD(CSR_UCODE_DRV_GP1); | |
1091 | IWL_CMD(CSR_UCODE_DRV_GP2); | |
1092 | IWL_CMD(CSR_LED_REG); | |
1093 | IWL_CMD(CSR_DRAM_INT_TBL_REG); | |
1094 | IWL_CMD(CSR_GIO_CHICKEN_BITS); | |
1095 | IWL_CMD(CSR_ANA_PLL_CFG); | |
1096 | IWL_CMD(CSR_HW_REV_WA_REG); | |
1097 | IWL_CMD(CSR_DBG_HPET_MEM_REG); | |
1098 | default: | |
1099 | return "UNKNOWN"; | |
1100 | } | |
d9fb6465 | 1101 | #undef IWL_CMD |
ff620849 EG |
1102 | } |
1103 | ||
990aa6d7 | 1104 | void iwl_pcie_dump_csr(struct iwl_trans *trans) |
ff620849 EG |
1105 | { |
1106 | int i; | |
1107 | static const u32 csr_tbl[] = { | |
1108 | CSR_HW_IF_CONFIG_REG, | |
1109 | CSR_INT_COALESCING, | |
1110 | CSR_INT, | |
1111 | CSR_INT_MASK, | |
1112 | CSR_FH_INT_STATUS, | |
1113 | CSR_GPIO_IN, | |
1114 | CSR_RESET, | |
1115 | CSR_GP_CNTRL, | |
1116 | CSR_HW_REV, | |
1117 | CSR_EEPROM_REG, | |
1118 | CSR_EEPROM_GP, | |
1119 | CSR_OTP_GP_REG, | |
1120 | CSR_GIO_REG, | |
1121 | CSR_GP_UCODE_REG, | |
1122 | CSR_GP_DRIVER_REG, | |
1123 | CSR_UCODE_DRV_GP1, | |
1124 | CSR_UCODE_DRV_GP2, | |
1125 | CSR_LED_REG, | |
1126 | CSR_DRAM_INT_TBL_REG, | |
1127 | CSR_GIO_CHICKEN_BITS, | |
1128 | CSR_ANA_PLL_CFG, | |
1129 | CSR_HW_REV_WA_REG, | |
1130 | CSR_DBG_HPET_MEM_REG | |
1131 | }; | |
1132 | IWL_ERR(trans, "CSR values:\n"); | |
1133 | IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " | |
1134 | "CSR_INT_PERIODIC_REG)\n"); | |
1135 | for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { | |
1136 | IWL_ERR(trans, " %25s: 0X%08x\n", | |
1137 | get_csr_string(csr_tbl[i]), | |
1042db2a | 1138 | iwl_read32(trans, csr_tbl[i])); |
ff620849 EG |
1139 | } |
1140 | } | |
1141 | ||
87e5666c EG |
1142 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
1143 | /* create and remove of files */ | |
1144 | #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ | |
5a878bf6 | 1145 | if (!debugfs_create_file(#name, mode, parent, trans, \ |
87e5666c | 1146 | &iwl_dbgfs_##name##_ops)) \ |
9da987ac | 1147 | goto err; \ |
87e5666c EG |
1148 | } while (0) |
1149 | ||
1150 | /* file operation */ | |
1151 | #define DEBUGFS_READ_FUNC(name) \ | |
1152 | static ssize_t iwl_dbgfs_##name##_read(struct file *file, \ | |
1153 | char __user *user_buf, \ | |
1154 | size_t count, loff_t *ppos); | |
1155 | ||
1156 | #define DEBUGFS_WRITE_FUNC(name) \ | |
1157 | static ssize_t iwl_dbgfs_##name##_write(struct file *file, \ | |
1158 | const char __user *user_buf, \ | |
1159 | size_t count, loff_t *ppos); | |
1160 | ||
87e5666c EG |
1161 | #define DEBUGFS_READ_FILE_OPS(name) \ |
1162 | DEBUGFS_READ_FUNC(name); \ | |
1163 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
1164 | .read = iwl_dbgfs_##name##_read, \ | |
234e3405 | 1165 | .open = simple_open, \ |
87e5666c EG |
1166 | .llseek = generic_file_llseek, \ |
1167 | }; | |
1168 | ||
16db88ba EG |
1169 | #define DEBUGFS_WRITE_FILE_OPS(name) \ |
1170 | DEBUGFS_WRITE_FUNC(name); \ | |
1171 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
1172 | .write = iwl_dbgfs_##name##_write, \ | |
234e3405 | 1173 | .open = simple_open, \ |
16db88ba EG |
1174 | .llseek = generic_file_llseek, \ |
1175 | }; | |
1176 | ||
87e5666c EG |
1177 | #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ |
1178 | DEBUGFS_READ_FUNC(name); \ | |
1179 | DEBUGFS_WRITE_FUNC(name); \ | |
1180 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
1181 | .write = iwl_dbgfs_##name##_write, \ | |
1182 | .read = iwl_dbgfs_##name##_read, \ | |
234e3405 | 1183 | .open = simple_open, \ |
87e5666c EG |
1184 | .llseek = generic_file_llseek, \ |
1185 | }; | |
1186 | ||
87e5666c | 1187 | static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, |
20d3b647 JB |
1188 | char __user *user_buf, |
1189 | size_t count, loff_t *ppos) | |
8ad71bef | 1190 | { |
5a878bf6 | 1191 | struct iwl_trans *trans = file->private_data; |
8ad71bef | 1192 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1193 | struct iwl_txq *txq; |
87e5666c EG |
1194 | struct iwl_queue *q; |
1195 | char *buf; | |
1196 | int pos = 0; | |
1197 | int cnt; | |
1198 | int ret; | |
1745e440 WYG |
1199 | size_t bufsz; |
1200 | ||
035f7ff2 | 1201 | bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues; |
87e5666c | 1202 | |
f9e75447 | 1203 | if (!trans_pcie->txq) |
87e5666c | 1204 | return -EAGAIN; |
f9e75447 | 1205 | |
87e5666c EG |
1206 | buf = kzalloc(bufsz, GFP_KERNEL); |
1207 | if (!buf) | |
1208 | return -ENOMEM; | |
1209 | ||
035f7ff2 | 1210 | for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { |
8ad71bef | 1211 | txq = &trans_pcie->txq[cnt]; |
87e5666c EG |
1212 | q = &txq->q; |
1213 | pos += scnprintf(buf + pos, bufsz - pos, | |
9eae88fa | 1214 | "hwq %.2d: read=%u write=%u use=%d stop=%d\n", |
87e5666c | 1215 | cnt, q->read_ptr, q->write_ptr, |
9eae88fa JB |
1216 | !!test_bit(cnt, trans_pcie->queue_used), |
1217 | !!test_bit(cnt, trans_pcie->queue_stopped)); | |
87e5666c EG |
1218 | } |
1219 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1220 | kfree(buf); | |
1221 | return ret; | |
1222 | } | |
1223 | ||
1224 | static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, | |
20d3b647 JB |
1225 | char __user *user_buf, |
1226 | size_t count, loff_t *ppos) | |
1227 | { | |
5a878bf6 | 1228 | struct iwl_trans *trans = file->private_data; |
20d3b647 | 1229 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1230 | struct iwl_rxq *rxq = &trans_pcie->rxq; |
87e5666c EG |
1231 | char buf[256]; |
1232 | int pos = 0; | |
1233 | const size_t bufsz = sizeof(buf); | |
1234 | ||
1235 | pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n", | |
1236 | rxq->read); | |
1237 | pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n", | |
1238 | rxq->write); | |
1239 | pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n", | |
1240 | rxq->free_count); | |
1241 | if (rxq->rb_stts) { | |
1242 | pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n", | |
1243 | le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF); | |
1244 | } else { | |
1245 | pos += scnprintf(buf + pos, bufsz - pos, | |
1246 | "closed_rb_num: Not Allocated\n"); | |
1247 | } | |
1248 | return simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1249 | } | |
1250 | ||
1f7b6172 EG |
1251 | static ssize_t iwl_dbgfs_interrupt_read(struct file *file, |
1252 | char __user *user_buf, | |
20d3b647 JB |
1253 | size_t count, loff_t *ppos) |
1254 | { | |
1f7b6172 | 1255 | struct iwl_trans *trans = file->private_data; |
20d3b647 | 1256 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1f7b6172 EG |
1257 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; |
1258 | ||
1259 | int pos = 0; | |
1260 | char *buf; | |
1261 | int bufsz = 24 * 64; /* 24 items * 64 char per item */ | |
1262 | ssize_t ret; | |
1263 | ||
1264 | buf = kzalloc(bufsz, GFP_KERNEL); | |
f9e75447 | 1265 | if (!buf) |
1f7b6172 | 1266 | return -ENOMEM; |
1f7b6172 EG |
1267 | |
1268 | pos += scnprintf(buf + pos, bufsz - pos, | |
1269 | "Interrupt Statistics Report:\n"); | |
1270 | ||
1271 | pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", | |
1272 | isr_stats->hw); | |
1273 | pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", | |
1274 | isr_stats->sw); | |
1275 | if (isr_stats->sw || isr_stats->hw) { | |
1276 | pos += scnprintf(buf + pos, bufsz - pos, | |
1277 | "\tLast Restarting Code: 0x%X\n", | |
1278 | isr_stats->err_code); | |
1279 | } | |
1280 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1281 | pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", | |
1282 | isr_stats->sch); | |
1283 | pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", | |
1284 | isr_stats->alive); | |
1285 | #endif | |
1286 | pos += scnprintf(buf + pos, bufsz - pos, | |
1287 | "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); | |
1288 | ||
1289 | pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", | |
1290 | isr_stats->ctkill); | |
1291 | ||
1292 | pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", | |
1293 | isr_stats->wakeup); | |
1294 | ||
1295 | pos += scnprintf(buf + pos, bufsz - pos, | |
1296 | "Rx command responses:\t\t %u\n", isr_stats->rx); | |
1297 | ||
1298 | pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", | |
1299 | isr_stats->tx); | |
1300 | ||
1301 | pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", | |
1302 | isr_stats->unhandled); | |
1303 | ||
1304 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1305 | kfree(buf); | |
1306 | return ret; | |
1307 | } | |
1308 | ||
1309 | static ssize_t iwl_dbgfs_interrupt_write(struct file *file, | |
1310 | const char __user *user_buf, | |
1311 | size_t count, loff_t *ppos) | |
1312 | { | |
1313 | struct iwl_trans *trans = file->private_data; | |
20d3b647 | 1314 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1f7b6172 EG |
1315 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; |
1316 | ||
1317 | char buf[8]; | |
1318 | int buf_size; | |
1319 | u32 reset_flag; | |
1320 | ||
1321 | memset(buf, 0, sizeof(buf)); | |
1322 | buf_size = min(count, sizeof(buf) - 1); | |
1323 | if (copy_from_user(buf, user_buf, buf_size)) | |
1324 | return -EFAULT; | |
1325 | if (sscanf(buf, "%x", &reset_flag) != 1) | |
1326 | return -EFAULT; | |
1327 | if (reset_flag == 0) | |
1328 | memset(isr_stats, 0, sizeof(*isr_stats)); | |
1329 | ||
1330 | return count; | |
1331 | } | |
1332 | ||
16db88ba | 1333 | static ssize_t iwl_dbgfs_csr_write(struct file *file, |
20d3b647 JB |
1334 | const char __user *user_buf, |
1335 | size_t count, loff_t *ppos) | |
16db88ba EG |
1336 | { |
1337 | struct iwl_trans *trans = file->private_data; | |
1338 | char buf[8]; | |
1339 | int buf_size; | |
1340 | int csr; | |
1341 | ||
1342 | memset(buf, 0, sizeof(buf)); | |
1343 | buf_size = min(count, sizeof(buf) - 1); | |
1344 | if (copy_from_user(buf, user_buf, buf_size)) | |
1345 | return -EFAULT; | |
1346 | if (sscanf(buf, "%d", &csr) != 1) | |
1347 | return -EFAULT; | |
1348 | ||
990aa6d7 | 1349 | iwl_pcie_dump_csr(trans); |
16db88ba EG |
1350 | |
1351 | return count; | |
1352 | } | |
1353 | ||
16db88ba | 1354 | static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, |
20d3b647 JB |
1355 | char __user *user_buf, |
1356 | size_t count, loff_t *ppos) | |
16db88ba EG |
1357 | { |
1358 | struct iwl_trans *trans = file->private_data; | |
94543a8d | 1359 | char *buf = NULL; |
16db88ba EG |
1360 | int pos = 0; |
1361 | ssize_t ret = -EFAULT; | |
1362 | ||
990aa6d7 | 1363 | ret = pos = iwl_pcie_dump_fh(trans, &buf); |
16db88ba EG |
1364 | if (buf) { |
1365 | ret = simple_read_from_buffer(user_buf, | |
1366 | count, ppos, buf, pos); | |
1367 | kfree(buf); | |
1368 | } | |
1369 | ||
1370 | return ret; | |
1371 | } | |
1372 | ||
48dffd39 JB |
1373 | static ssize_t iwl_dbgfs_fw_restart_write(struct file *file, |
1374 | const char __user *user_buf, | |
1375 | size_t count, loff_t *ppos) | |
1376 | { | |
1377 | struct iwl_trans *trans = file->private_data; | |
1378 | ||
1379 | if (!trans->op_mode) | |
1380 | return -EAGAIN; | |
1381 | ||
24172f39 | 1382 | local_bh_disable(); |
48dffd39 | 1383 | iwl_op_mode_nic_error(trans->op_mode); |
24172f39 | 1384 | local_bh_enable(); |
48dffd39 JB |
1385 | |
1386 | return count; | |
1387 | } | |
1388 | ||
1f7b6172 | 1389 | DEBUGFS_READ_WRITE_FILE_OPS(interrupt); |
16db88ba | 1390 | DEBUGFS_READ_FILE_OPS(fh_reg); |
87e5666c EG |
1391 | DEBUGFS_READ_FILE_OPS(rx_queue); |
1392 | DEBUGFS_READ_FILE_OPS(tx_queue); | |
16db88ba | 1393 | DEBUGFS_WRITE_FILE_OPS(csr); |
48dffd39 | 1394 | DEBUGFS_WRITE_FILE_OPS(fw_restart); |
87e5666c EG |
1395 | |
1396 | /* | |
1397 | * Create the debugfs files and directories | |
1398 | * | |
1399 | */ | |
1400 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, | |
20d3b647 | 1401 | struct dentry *dir) |
87e5666c | 1402 | { |
87e5666c EG |
1403 | DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR); |
1404 | DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR); | |
1f7b6172 | 1405 | DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR); |
16db88ba EG |
1406 | DEBUGFS_ADD_FILE(csr, dir, S_IWUSR); |
1407 | DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR); | |
48dffd39 | 1408 | DEBUGFS_ADD_FILE(fw_restart, dir, S_IWUSR); |
87e5666c | 1409 | return 0; |
9da987ac MV |
1410 | |
1411 | err: | |
1412 | IWL_ERR(trans, "failed to create the trans debugfs entry\n"); | |
1413 | return -ENOMEM; | |
87e5666c EG |
1414 | } |
1415 | #else | |
1416 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, | |
20d3b647 JB |
1417 | struct dentry *dir) |
1418 | { | |
1419 | return 0; | |
1420 | } | |
87e5666c EG |
1421 | #endif /*CONFIG_IWLWIFI_DEBUGFS */ |
1422 | ||
d1ff5253 | 1423 | static const struct iwl_trans_ops trans_ops_pcie = { |
57a1dc89 | 1424 | .start_hw = iwl_trans_pcie_start_hw, |
cc56feb2 | 1425 | .stop_hw = iwl_trans_pcie_stop_hw, |
ed6a3803 | 1426 | .fw_alive = iwl_trans_pcie_fw_alive, |
cf614297 | 1427 | .start_fw = iwl_trans_pcie_start_fw, |
e6bb4c9c | 1428 | .stop_device = iwl_trans_pcie_stop_device, |
48d42c42 | 1429 | |
ddaf5a5b JB |
1430 | .d3_suspend = iwl_trans_pcie_d3_suspend, |
1431 | .d3_resume = iwl_trans_pcie_d3_resume, | |
2dd4f9f7 | 1432 | |
f02831be | 1433 | .send_cmd = iwl_trans_pcie_send_hcmd, |
c85eb619 | 1434 | |
e6bb4c9c | 1435 | .tx = iwl_trans_pcie_tx, |
a0eaad71 | 1436 | .reclaim = iwl_trans_pcie_reclaim, |
34c1b7ba | 1437 | |
d0624be6 | 1438 | .txq_disable = iwl_trans_pcie_txq_disable, |
4beaf6c2 | 1439 | .txq_enable = iwl_trans_pcie_txq_enable, |
34c1b7ba | 1440 | |
87e5666c | 1441 | .dbgfs_register = iwl_trans_pcie_dbgfs_register, |
5f178cd2 | 1442 | |
990aa6d7 | 1443 | .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty, |
5f178cd2 | 1444 | |
c01a4047 | 1445 | #ifdef CONFIG_PM_SLEEP |
57210f7c EG |
1446 | .suspend = iwl_trans_pcie_suspend, |
1447 | .resume = iwl_trans_pcie_resume, | |
c01a4047 | 1448 | #endif |
03905495 EG |
1449 | .write8 = iwl_trans_pcie_write8, |
1450 | .write32 = iwl_trans_pcie_write32, | |
1451 | .read32 = iwl_trans_pcie_read32, | |
6a06b6c1 EG |
1452 | .read_prph = iwl_trans_pcie_read_prph, |
1453 | .write_prph = iwl_trans_pcie_write_prph, | |
4fd442db EG |
1454 | .read_mem = iwl_trans_pcie_read_mem, |
1455 | .write_mem = iwl_trans_pcie_write_mem, | |
c6f600fc | 1456 | .configure = iwl_trans_pcie_configure, |
47107e84 | 1457 | .set_pmi = iwl_trans_pcie_set_pmi, |
7a65d170 | 1458 | .grab_nic_access = iwl_trans_pcie_grab_nic_access, |
e139dc4a LE |
1459 | .release_nic_access = iwl_trans_pcie_release_nic_access, |
1460 | .set_bits_mask = iwl_trans_pcie_set_bits_mask, | |
e6bb4c9c | 1461 | }; |
a42a1844 | 1462 | |
87ce05a2 | 1463 | struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, |
035f7ff2 EG |
1464 | const struct pci_device_id *ent, |
1465 | const struct iwl_cfg *cfg) | |
a42a1844 | 1466 | { |
a42a1844 EG |
1467 | struct iwl_trans_pcie *trans_pcie; |
1468 | struct iwl_trans *trans; | |
1469 | u16 pci_cmd; | |
1470 | int err; | |
1471 | ||
1472 | trans = kzalloc(sizeof(struct iwl_trans) + | |
20d3b647 | 1473 | sizeof(struct iwl_trans_pcie), GFP_KERNEL); |
a42a1844 | 1474 | |
dbeca583 | 1475 | if (!trans) |
a42a1844 EG |
1476 | return NULL; |
1477 | ||
1478 | trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1479 | ||
1480 | trans->ops = &trans_ops_pcie; | |
035f7ff2 | 1481 | trans->cfg = cfg; |
2bfb5092 | 1482 | trans_lockdep_init(trans); |
a42a1844 | 1483 | trans_pcie->trans = trans; |
7b11488f | 1484 | spin_lock_init(&trans_pcie->irq_lock); |
e56b04ef | 1485 | spin_lock_init(&trans_pcie->reg_lock); |
13df1aab | 1486 | init_waitqueue_head(&trans_pcie->ucode_write_waitq); |
a42a1844 EG |
1487 | |
1488 | /* W/A - seems to solve weird behavior. We need to remove this if we | |
1489 | * don't want to stay in L1 all the time. This wastes a lot of power */ | |
1490 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | | |
20d3b647 | 1491 | PCIE_LINK_STATE_CLKPM); |
a42a1844 EG |
1492 | |
1493 | if (pci_enable_device(pdev)) { | |
1494 | err = -ENODEV; | |
1495 | goto out_no_pci; | |
1496 | } | |
1497 | ||
1498 | pci_set_master(pdev); | |
1499 | ||
1500 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36)); | |
1501 | if (!err) | |
1502 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36)); | |
1503 | if (err) { | |
1504 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
1505 | if (!err) | |
1506 | err = pci_set_consistent_dma_mask(pdev, | |
20d3b647 | 1507 | DMA_BIT_MASK(32)); |
a42a1844 EG |
1508 | /* both attempts failed: */ |
1509 | if (err) { | |
6a4b09f8 | 1510 | dev_err(&pdev->dev, "No suitable DMA available\n"); |
a42a1844 EG |
1511 | goto out_pci_disable_device; |
1512 | } | |
1513 | } | |
1514 | ||
1515 | err = pci_request_regions(pdev, DRV_NAME); | |
1516 | if (err) { | |
6a4b09f8 | 1517 | dev_err(&pdev->dev, "pci_request_regions failed\n"); |
a42a1844 EG |
1518 | goto out_pci_disable_device; |
1519 | } | |
1520 | ||
05f5b97e | 1521 | trans_pcie->hw_base = pci_ioremap_bar(pdev, 0); |
a42a1844 | 1522 | if (!trans_pcie->hw_base) { |
6a4b09f8 | 1523 | dev_err(&pdev->dev, "pci_ioremap_bar failed\n"); |
a42a1844 EG |
1524 | err = -ENODEV; |
1525 | goto out_pci_release_regions; | |
1526 | } | |
1527 | ||
a42a1844 EG |
1528 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
1529 | * PCI Tx retries from interfering with C3 CPU state */ | |
1530 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
1531 | ||
1532 | err = pci_enable_msi(pdev); | |
9f904b38 | 1533 | if (err) { |
6a4b09f8 | 1534 | dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err); |
9f904b38 EG |
1535 | /* enable rfkill interrupt: hw bug w/a */ |
1536 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); | |
1537 | if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { | |
1538 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
1539 | pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); | |
1540 | } | |
1541 | } | |
a42a1844 EG |
1542 | |
1543 | trans->dev = &pdev->dev; | |
a42a1844 | 1544 | trans_pcie->pci_dev = pdev; |
08079a49 | 1545 | trans->hw_rev = iwl_read32(trans, CSR_HW_REV); |
99673ee5 | 1546 | trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; |
9ca85961 EG |
1547 | snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), |
1548 | "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); | |
a42a1844 | 1549 | |
69a10b29 | 1550 | /* Initialize the wait queue for commands */ |
f946b529 | 1551 | init_waitqueue_head(&trans_pcie->wait_command_queue); |
69a10b29 | 1552 | |
3ec45882 JB |
1553 | snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name), |
1554 | "iwl_cmd_pool:%s", dev_name(trans->dev)); | |
59c647b6 EG |
1555 | |
1556 | trans->dev_cmd_headroom = 0; | |
1557 | trans->dev_cmd_pool = | |
3ec45882 | 1558 | kmem_cache_create(trans->dev_cmd_pool_name, |
59c647b6 EG |
1559 | sizeof(struct iwl_device_cmd) |
1560 | + trans->dev_cmd_headroom, | |
1561 | sizeof(void *), | |
1562 | SLAB_HWCACHE_ALIGN, | |
1563 | NULL); | |
1564 | ||
1565 | if (!trans->dev_cmd_pool) | |
1566 | goto out_pci_disable_msi; | |
1567 | ||
a8b691e6 JB |
1568 | trans_pcie->inta_mask = CSR_INI_SET_MASK; |
1569 | ||
a8b691e6 JB |
1570 | if (iwl_pcie_alloc_ict(trans)) |
1571 | goto out_free_cmd_pool; | |
1572 | ||
2bfb5092 JB |
1573 | if (request_threaded_irq(pdev->irq, iwl_pcie_isr_ict, |
1574 | iwl_pcie_irq_handler, | |
1575 | IRQF_SHARED, DRV_NAME, trans)) { | |
a8b691e6 JB |
1576 | IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); |
1577 | goto out_free_ict; | |
1578 | } | |
1579 | ||
a42a1844 EG |
1580 | return trans; |
1581 | ||
a8b691e6 JB |
1582 | out_free_ict: |
1583 | iwl_pcie_free_ict(trans); | |
1584 | out_free_cmd_pool: | |
1585 | kmem_cache_destroy(trans->dev_cmd_pool); | |
59c647b6 EG |
1586 | out_pci_disable_msi: |
1587 | pci_disable_msi(pdev); | |
a42a1844 EG |
1588 | out_pci_release_regions: |
1589 | pci_release_regions(pdev); | |
1590 | out_pci_disable_device: | |
1591 | pci_disable_device(pdev); | |
1592 | out_no_pci: | |
1593 | kfree(trans); | |
1594 | return NULL; | |
1595 | } |