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Merge tag 'samsung-fixes-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / pcie / trans.c
CommitLineData
c85eb619
EG		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
51368bf7 8 * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
8b4139dc 9 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
c85eb619
EG		 10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
23 * USA
24 *
25 * The full GNU General Public License is included in this distribution
410dc5aa 26 * in the file called COPYING.
c85eb619
EG		 27 *
28 * Contact Information:
29 * Intel Linux Wireless <ilw@linux.intel.com>
30 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 *
32 * BSD LICENSE
33 *
51368bf7 34 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
8b4139dc 35 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
c85eb619
EG		 36 * All rights reserved.
37 *
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
40 * are met:
41 *
42 * * Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * * Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in
46 * the documentation and/or other materials provided with the
47 * distribution.
48 * * Neither the name Intel Corporation nor the names of its
49 * contributors may be used to endorse or promote products derived
50 * from this software without specific prior written permission.
51 *
52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *
64 *****************************************************************************/
a42a1844
EG		 65#include <linux/pci.h>
66#include <linux/pci-aspm.h>
e6bb4c9c 67#include <linux/interrupt.h>
87e5666c 68#include <linux/debugfs.h>
cf614297 69#include <linux/sched.h>
6d8f6eeb
EG		 70#include <linux/bitops.h>
71#include <linux/gfp.h>
48eb7b34 72#include <linux/vmalloc.h>
e6bb4c9c 73
82575102 74#include "iwl-drv.h"
c85eb619 75#include "iwl-trans.h"
522376d2
EG		 76#include "iwl-csr.h"
77#include "iwl-prph.h"
7a10e3e4 78#include "iwl-agn-hw.h"
4d075007 79#include "iwl-fw-error-dump.h"
6468a01a 80#include "internal.h"
0439bb62 81
c2d20201
EG		 82static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
83{
84 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
85
86 if (!trans_pcie->fw_mon_page)
87 return;
88
89 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
90 trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
91 __free_pages(trans_pcie->fw_mon_page,
92 get_order(trans_pcie->fw_mon_size));
93 trans_pcie->fw_mon_page = NULL;
94 trans_pcie->fw_mon_phys = 0;
95 trans_pcie->fw_mon_size = 0;
96}
97
98static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans)
99{
100 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
101 struct page *page;
102 dma_addr_t phys;
103 u32 size;
104 u8 power;
105
106 if (trans_pcie->fw_mon_page) {
107 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
108 trans_pcie->fw_mon_size,
109 DMA_FROM_DEVICE);
110 return;
111 }
112
113 phys = 0;
114 for (power = 26; power >= 11; power--) {
115 int order;
116
117 size = BIT(power);
118 order = get_order(size);
119 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
120 order);
121 if (!page)
122 continue;
123
124 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
125 DMA_FROM_DEVICE);
126 if (dma_mapping_error(trans->dev, phys)) {
127 __free_pages(page, order);
128 continue;
129 }
130 IWL_INFO(trans,
131 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
132 size, order);
133 break;
134 }
135
136 if (!page)
137 return;
138
139 trans_pcie->fw_mon_page = page;
140 trans_pcie->fw_mon_phys = phys;
141 trans_pcie->fw_mon_size = size;
142}
143
a812cba9
AB		 144static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
145{
146 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
147 ((reg & 0x0000ffff) | (2 << 28)));
148 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
149}
150
151static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
152{
153 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
154 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
155 ((reg & 0x0000ffff) | (3 << 28)));
156}
157
ddaf5a5b 158static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
392f8b78 159{
ddaf5a5b
JB		 160 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
161 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
162 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
163 ~APMG_PS_CTRL_MSK_PWR_SRC);
164 else
165 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
166 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
167 ~APMG_PS_CTRL_MSK_PWR_SRC);
392f8b78
EG		 168}
169
af634bee
EG		 170/* PCI registers */
171#define PCI_CFG_RETRY_TIMEOUT 0x041
af634bee 172
7afe3705 173static void iwl_pcie_apm_config(struct iwl_trans *trans)
af634bee 174{
20d3b647 175 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7afe3705 176 u16 lctl;
9180ac50 177 u16 cap;
af634bee 178
af634bee
EG		 179 /*
180 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
181 * Check if BIOS (or OS) enabled L1-ASPM on this device.
182 * If so (likely), disable L0S, so device moves directly L0->L1;
183 * costs negligible amount of power savings.
184 * If not (unlikely), enable L0S, so there is at least some
185 * power savings, even without L1.
186 */
7afe3705 187 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
9180ac50 188 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
af634bee 189 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
9180ac50 190 else
af634bee 191 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
438a0f0a 192 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
9180ac50
EG		 193
194 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
195 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
196 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
197 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
198 trans->ltr_enabled ? "En" : "Dis");
af634bee
EG		 199}
200
a6c684ee
EG		 201/*
202 * Start up NIC's basic functionality after it has been reset
7afe3705 203 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
a6c684ee
EG		 204 * NOTE: This does not load uCode nor start the embedded processor
205 */
7afe3705 206static int iwl_pcie_apm_init(struct iwl_trans *trans)
a6c684ee
EG		 207{
208 int ret = 0;
209 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
210
211 /*
212 * Use "set_bit" below rather than "write", to preserve any hardware
213 * bits already set by default after reset.
214 */
215
216 /* Disable L0S exit timer (platform NMI Work/Around) */
e4a9f8ce
EH		 217 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
218 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
219 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
a6c684ee
EG		 220
221 /*
222 * Disable L0s without affecting L1;
223 * don't wait for ICH L0s (ICH bug W/A)
224 */
225 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
20d3b647 226 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
a6c684ee
EG		 227
228 /* Set FH wait threshold to maximum (HW error during stress W/A) */
229 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
230
231 /*
232 * Enable HAP INTA (interrupt from management bus) to
233 * wake device's PCI Express link L1a -> L0s
234 */
235 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 236 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
a6c684ee 237
7afe3705 238 iwl_pcie_apm_config(trans);
a6c684ee
EG		 239
240 /* Configure analog phase-lock-loop before activating to D0A */
035f7ff2 241 if (trans->cfg->base_params->pll_cfg_val)
a6c684ee 242 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
035f7ff2 243 trans->cfg->base_params->pll_cfg_val);
a6c684ee
EG		 244
245 /*
246 * Set "initialization complete" bit to move adapter from
247 * D0U* --> D0A* (powered-up active) state.
248 */
249 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
250
251 /*
252 * Wait for clock stabilization; once stabilized, access to
253 * device-internal resources is supported, e.g. iwl_write_prph()
254 * and accesses to uCode SRAM.
255 */
256 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
20d3b647
JB		 257 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
258 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
a6c684ee
EG		 259 if (ret < 0) {
260 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
261 goto out;
262 }
263
2d93aee1
EG		 264 if (trans->cfg->host_interrupt_operation_mode) {
265 /*
266 * This is a bit of an abuse - This is needed for 7260 / 3160
267 * only check host_interrupt_operation_mode even if this is
268 * not related to host_interrupt_operation_mode.
269 *
270 * Enable the oscillator to count wake up time for L1 exit. This
271 * consumes slightly more power (100uA) - but allows to be sure
272 * that we wake up from L1 on time.
273 *
274 * This looks weird: read twice the same register, discard the
275 * value, set a bit, and yet again, read that same register
276 * just to discard the value. But that's the way the hardware
277 * seems to like it.
278 */
279 iwl_read_prph(trans, OSC_CLK);
280 iwl_read_prph(trans, OSC_CLK);
281 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
282 iwl_read_prph(trans, OSC_CLK);
283 iwl_read_prph(trans, OSC_CLK);
284 }
285
a6c684ee
EG		 286 /*
287 * Enable DMA clock and wait for it to stabilize.
288 *
3073d8c0
EH		 289 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
290 * bits do not disable clocks. This preserves any hardware
291 * bits already set by default in "CLK_CTRL_REG" after reset.
a6c684ee 292 */
3073d8c0
EH		 293 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) {
294 iwl_write_prph(trans, APMG_CLK_EN_REG,
295 APMG_CLK_VAL_DMA_CLK_RQT);
296 udelay(20);
297
298 /* Disable L1-Active */
299 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
300 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
301
302 /* Clear the interrupt in APMG if the NIC is in RFKILL */
303 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
304 APMG_RTC_INT_STT_RFKILL);
305 }
889b1696 306
eb7ff77e 307 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
a6c684ee
EG		 308
309out:
310 return ret;
311}
312
a812cba9
AB		 313/*
314 * Enable LP XTAL to avoid HW bug where device may consume much power if
315 * FW is not loaded after device reset. LP XTAL is disabled by default
316 * after device HW reset. Do it only if XTAL is fed by internal source.
317 * Configure device's "persistence" mode to avoid resetting XTAL again when
318 * SHRD_HW_RST occurs in S3.
319 */
320static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
321{
322 int ret;
323 u32 apmg_gp1_reg;
324 u32 apmg_xtal_cfg_reg;
325 u32 dl_cfg_reg;
326
327 /* Force XTAL ON */
328 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
329 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
330
331 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
332 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
333
334 udelay(10);
335
336 /*
337 * Set "initialization complete" bit to move adapter from
338 * D0U* --> D0A* (powered-up active) state.
339 */
340 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
341
342 /*
343 * Wait for clock stabilization; once stabilized, access to
344 * device-internal resources is possible.
345 */
346 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
347 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
348 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
349 25000);
350 if (WARN_ON(ret < 0)) {
351 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
352 /* Release XTAL ON request */
353 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
354 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
355 return;
356 }
357
358 /*
359 * Clear "disable persistence" to avoid LP XTAL resetting when
360 * SHRD_HW_RST is applied in S3.
361 */
362 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
363 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
364
365 /*
366 * Force APMG XTAL to be active to prevent its disabling by HW
367 * caused by APMG idle state.
368 */
369 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
370 SHR_APMG_XTAL_CFG_REG);
371 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
372 apmg_xtal_cfg_reg |
373 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
374
375 /*
376 * Reset entire device again - do controller reset (results in
377 * SHRD_HW_RST). Turn MAC off before proceeding.
378 */
379 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
380
381 udelay(10);
382
383 /* Enable LP XTAL by indirect access through CSR */
384 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
385 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
386 SHR_APMG_GP1_WF_XTAL_LP_EN |
387 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
388
389 /* Clear delay line clock power up */
390 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
391 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
392 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
393
394 /*
395 * Enable persistence mode to avoid LP XTAL resetting when
396 * SHRD_HW_RST is applied in S3.
397 */
398 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
399 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
400
401 /*
402 * Clear "initialization complete" bit to move adapter from
403 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
404 */
405 iwl_clear_bit(trans, CSR_GP_CNTRL,
406 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
407
408 /* Activates XTAL resources monitor */
409 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
410 CSR_MONITOR_XTAL_RESOURCES);
411
412 /* Release XTAL ON request */
413 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
414 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
415 udelay(10);
416
417 /* Release APMG XTAL */
418 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
419 apmg_xtal_cfg_reg &
420 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
421}
422
7afe3705 423static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
cc56feb2
EG		 424{
425 int ret = 0;
426
427 /* stop device's busmaster DMA activity */
428 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
429
430 ret = iwl_poll_bit(trans, CSR_RESET,
20d3b647
JB		 431 CSR_RESET_REG_FLAG_MASTER_DISABLED,
432 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
7f2ac8fb 433 if (ret < 0)
cc56feb2
EG		 434 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
435
436 IWL_DEBUG_INFO(trans, "stop master\n");
437
438 return ret;
439}
440
7afe3705 441static void iwl_pcie_apm_stop(struct iwl_trans *trans)
cc56feb2
EG		 442{
443 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
444
eb7ff77e 445 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
cc56feb2
EG		 446
447 /* Stop device's DMA activity */
7afe3705 448 iwl_pcie_apm_stop_master(trans);
cc56feb2 449
a812cba9
AB		 450 if (trans->cfg->lp_xtal_workaround) {
451 iwl_pcie_apm_lp_xtal_enable(trans);
452 return;
453 }
454
cc56feb2
EG		 455 /* Reset the entire device */
456 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
457
458 udelay(10);
459
460 /*
461 * Clear "initialization complete" bit to move adapter from
462 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
463 */
464 iwl_clear_bit(trans, CSR_GP_CNTRL,
465 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
466}
467
7afe3705 468static int iwl_pcie_nic_init(struct iwl_trans *trans)
392f8b78 469{
7b11488f 470 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
392f8b78
EG		 471
472 /* nic_init */
7b70bd63 473 spin_lock(&trans_pcie->irq_lock);
7afe3705 474 iwl_pcie_apm_init(trans);
392f8b78 475
7b70bd63 476 spin_unlock(&trans_pcie->irq_lock);
392f8b78 477
3073d8c0
EH		 478 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
479 iwl_pcie_set_pwr(trans, false);
392f8b78 480
ecdb975c 481 iwl_op_mode_nic_config(trans->op_mode);
392f8b78
EG		 482
483 /* Allocate the RX queue, or reset if it is already allocated */
9805c446 484 iwl_pcie_rx_init(trans);
392f8b78
EG		 485
486 /* Allocate or reset and init all Tx and Command queues */
f02831be 487 if (iwl_pcie_tx_init(trans))
392f8b78
EG		 488 return -ENOMEM;
489
035f7ff2 490 if (trans->cfg->base_params->shadow_reg_enable) {
392f8b78 491 /* enable shadow regs in HW */
20d3b647 492 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
d38069d1 493 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
392f8b78
EG		 494 }
495
392f8b78
EG		 496 return 0;
497}
498
499#define HW_READY_TIMEOUT (50)
500
501/* Note: returns poll_bit return value, which is >= 0 if success */
7afe3705 502static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
392f8b78
EG		 503{
504 int ret;
505
1042db2a 506 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 507 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
392f8b78
EG		 508
509 /* See if we got it */
1042db2a 510 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647
JB		 511 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
512 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
513 HW_READY_TIMEOUT);
392f8b78 514
6d8f6eeb 515 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
392f8b78
EG		 516 return ret;
517}
518
519/* Note: returns standard 0/-ERROR code */
7afe3705 520static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
392f8b78
EG		 521{
522 int ret;
289e5501 523 int t = 0;
501fd989 524 int iter;
392f8b78 525
6d8f6eeb 526 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
392f8b78 527
7afe3705 528 ret = iwl_pcie_set_hw_ready(trans);
ebb7678d 529 /* If the card is ready, exit 0 */
392f8b78
EG		 530 if (ret >= 0)
531 return 0;
532
501fd989
EG		 533 for (iter = 0; iter < 10; iter++) {
534 /* If HW is not ready, prepare the conditions to check again */
535 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
536 CSR_HW_IF_CONFIG_REG_PREPARE);
537
538 do {
539 ret = iwl_pcie_set_hw_ready(trans);
540 if (ret >= 0)
541 return 0;
392f8b78 542
501fd989
EG		 543 usleep_range(200, 1000);
544 t += 200;
545 } while (t < 150000);
546 msleep(25);
547 }
392f8b78 548
7f2ac8fb 549 IWL_ERR(trans, "Couldn't prepare the card\n");
392f8b78 550
392f8b78
EG		 551 return ret;
552}
553
cf614297
EG		 554/*
555 * ucode
556 */
7afe3705 557static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
83f84d7b 558 dma_addr_t phy_addr, u32 byte_cnt)
cf614297 559{
13df1aab 560 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
cf614297
EG		 561 int ret;
562
13df1aab 563 trans_pcie->ucode_write_complete = false;
cf614297
EG		 564
565 iwl_write_direct32(trans,
20d3b647
JB		 566 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
567 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
cf614297
EG		 568
569 iwl_write_direct32(trans,
20d3b647
JB		 570 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
571 dst_addr);
cf614297
EG		 572
573 iwl_write_direct32(trans,
83f84d7b
JB		 574 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
575 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
cf614297
EG		 576
577 iwl_write_direct32(trans,
20d3b647
JB		 578 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
579 (iwl_get_dma_hi_addr(phy_addr)
580 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
cf614297
EG		 581
582 iwl_write_direct32(trans,
20d3b647
JB		 583 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
584 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
585 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
586 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
cf614297
EG		 587
588 iwl_write_direct32(trans,
20d3b647
JB		 589 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
590 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
591 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
592 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
cf614297 593
13df1aab
JB		 594 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
595 trans_pcie->ucode_write_complete, 5 * HZ);
cf614297 596 if (!ret) {
83f84d7b 597 IWL_ERR(trans, "Failed to load firmware chunk!\n");
cf614297
EG		 598 return -ETIMEDOUT;
599 }
600
601 return 0;
602}
603
7afe3705 604static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
83f84d7b 605 const struct fw_desc *section)
cf614297 606{
83f84d7b
JB		 607 u8 *v_addr;
608 dma_addr_t p_addr;
c571573a 609 u32 offset, chunk_sz = section->len;
cf614297
EG		 610 int ret = 0;
611
83f84d7b
JB		 612 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
613 section_num);
614
c571573a
EG		 615 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
616 GFP_KERNEL | __GFP_NOWARN);
617 if (!v_addr) {
618 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
619 chunk_sz = PAGE_SIZE;
620 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
621 &p_addr, GFP_KERNEL);
622 if (!v_addr)
623 return -ENOMEM;
624 }
83f84d7b 625
c571573a 626 for (offset = 0; offset < section->len; offset += chunk_sz) {
83f84d7b
JB		 627 u32 copy_size;
628
c571573a 629 copy_size = min_t(u32, chunk_sz, section->len - offset);
cf614297 630
83f84d7b 631 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
7afe3705
EG		 632 ret = iwl_pcie_load_firmware_chunk(trans,
633 section->offset + offset,
634 p_addr, copy_size);
83f84d7b
JB		 635 if (ret) {
636 IWL_ERR(trans,
637 "Could not load the [%d] uCode section\n",
638 section_num);
639 break;
6dfa8d01 640 }
83f84d7b
JB		 641 }
642
c571573a 643 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
83f84d7b
JB		 644 return ret;
645}
646
189fa2fa
EH		 647static int iwl_pcie_load_cpu_secured_sections(struct iwl_trans *trans,
648 const struct fw_img *image,
034846cf
EH		 649 int cpu,
650 int *first_ucode_section)
e2d6f4e7
EH		 651{
652 int shift_param;
189fa2fa 653 int i, ret = 0;
034846cf 654 u32 last_read_idx = 0;
e2d6f4e7
EH		 655
656 if (cpu == 1) {
657 shift_param = 0;
034846cf 658 *first_ucode_section = 0;
e2d6f4e7
EH		 659 } else {
660 shift_param = 16;
034846cf 661 (*first_ucode_section)++;
e2d6f4e7
EH		 662 }
663
034846cf
EH		 664 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
665 last_read_idx = i;
666
667 if (!image->sec[i].data ||
668 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
669 IWL_DEBUG_FW(trans,
670 "Break since Data not valid or Empty section, sec = %d\n",
671 i);
189fa2fa 672 break;
034846cf
EH		 673 }
674
675 if (i == (*first_ucode_section) + 1)
189fa2fa
EH		 676 /* set CPU to started */
677 iwl_set_bits_prph(trans,
678 CSR_UCODE_LOAD_STATUS_ADDR,
679 LMPM_CPU_HDRS_LOADING_COMPLETED
680 << shift_param);
e2d6f4e7 681
189fa2fa
EH		 682 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
683 if (ret)
684 return ret;
e2d6f4e7 685 }
189fa2fa
EH		 686 /* image loading complete */
687 iwl_set_bits_prph(trans,
688 CSR_UCODE_LOAD_STATUS_ADDR,
689 LMPM_CPU_UCODE_LOADING_COMPLETED << shift_param);
e2d6f4e7 690
034846cf
EH		 691 *first_ucode_section = last_read_idx;
692
189fa2fa
EH		 693 return 0;
694}
e2d6f4e7 695
189fa2fa
EH		 696static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
697 const struct fw_img *image,
034846cf
EH		 698 int cpu,
699 int *first_ucode_section)
189fa2fa
EH		 700{
701 int shift_param;
189fa2fa 702 int i, ret = 0;
034846cf 703 u32 last_read_idx = 0;
189fa2fa
EH		 704
705 if (cpu == 1) {
706 shift_param = 0;
034846cf 707 *first_ucode_section = 0;
189fa2fa
EH		 708 } else {
709 shift_param = 16;
034846cf 710 (*first_ucode_section)++;
189fa2fa
EH		 711 }
712
034846cf
EH		 713 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
714 last_read_idx = i;
715
716 if (!image->sec[i].data ||
717 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
718 IWL_DEBUG_FW(trans,
719 "Break since Data not valid or Empty section, sec = %d\n",
720 i);
189fa2fa 721 break;
034846cf
EH		 722 }
723
189fa2fa
EH		 724 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
725 if (ret)
726 return ret;
e2d6f4e7
EH		 727 }
728
189fa2fa
EH		 729 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
730 iwl_set_bits_prph(trans,
731 CSR_UCODE_LOAD_STATUS_ADDR,
732 (LMPM_CPU_UCODE_LOADING_COMPLETED |
733 LMPM_CPU_HDRS_LOADING_COMPLETED |
734 LMPM_CPU_UCODE_LOADING_STARTED) <<
735 shift_param);
736
034846cf
EH		 737 *first_ucode_section = last_read_idx;
738
e2d6f4e7
EH		 739 return 0;
740}
741
7afe3705 742static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
0692fe41 743 const struct fw_img *image)
cf614297 744{
c2d20201 745 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
189fa2fa 746 int ret = 0;
034846cf 747 int first_ucode_section;
cf614297 748
e2d6f4e7
EH		 749 IWL_DEBUG_FW(trans,
750 "working with %s image\n",
751 image->is_secure ? "Secured" : "Non Secured");
752 IWL_DEBUG_FW(trans,
753 "working with %s CPU\n",
754 image->is_dual_cpus ? "Dual" : "Single");
755
756 /* configure the ucode to be ready to get the secured image */
757 if (image->is_secure) {
758 /* set secure boot inspector addresses */
189fa2fa
EH		 759 iwl_write_prph(trans,
760 LMPM_SECURE_INSPECTOR_CODE_ADDR,
761 LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE);
e2d6f4e7 762
189fa2fa
EH		 763 iwl_write_prph(trans,
764 LMPM_SECURE_INSPECTOR_DATA_ADDR,
765 LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE);
e2d6f4e7 766
189fa2fa
EH		 767 /* set CPU1 header address */
768 iwl_write_prph(trans,
769 LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR,
770 LMPM_SECURE_CPU1_HDR_MEM_SPACE);
771
772 /* load to FW the binary Secured sections of CPU1 */
034846cf
EH		 773 ret = iwl_pcie_load_cpu_secured_sections(trans, image, 1,
774 &first_ucode_section);
2d1c0044
JB		 775 if (ret)
776 return ret;
cf614297 777
189fa2fa
EH		 778 } else {
779 /* load to FW the binary Non secured sections of CPU1 */
034846cf
EH		 780 ret = iwl_pcie_load_cpu_sections(trans, image, 1,
781 &first_ucode_section);
e2d6f4e7
EH		 782 if (ret)
783 return ret;
e2d6f4e7
EH		 784 }
785
786 if (image->is_dual_cpus) {
189fa2fa
EH		 787 /* set CPU2 header address */
788 iwl_write_prph(trans,
789 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
790 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
e2d6f4e7 791
189fa2fa
EH		 792 /* load to FW the binary sections of CPU2 */
793 if (image->is_secure)
034846cf
EH		 794 ret = iwl_pcie_load_cpu_secured_sections(
795 trans, image, 2,
796 &first_ucode_section);
189fa2fa 797 else
034846cf
EH		 798 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
799 &first_ucode_section);
189fa2fa
EH		 800 if (ret)
801 return ret;
e2d6f4e7 802 }
cf614297 803
c2d20201
EG		 804 /* supported for 7000 only for the moment */
805 if (iwlwifi_mod_params.fw_monitor &&
806 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
807 iwl_pcie_alloc_fw_monitor(trans);
808
809 if (trans_pcie->fw_mon_size) {
810 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
811 trans_pcie->fw_mon_phys >> 4);
812 iwl_write_prph(trans, MON_BUFF_END_ADDR,
813 (trans_pcie->fw_mon_phys +
814 trans_pcie->fw_mon_size) >> 4);
815 }
816 }
817
e12ba844
EH		 818 /* release CPU reset */
819 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
820 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
821 else
822 iwl_write32(trans, CSR_RESET, 0);
823
189fa2fa
EH		 824 if (image->is_secure) {
825 /* wait for image verification to complete */
826 ret = iwl_poll_prph_bit(trans,
827 LMPM_SECURE_BOOT_CPU1_STATUS_ADDR,
828 LMPM_SECURE_BOOT_STATUS_SUCCESS,
829 LMPM_SECURE_BOOT_STATUS_SUCCESS,
830 LMPM_SECURE_TIME_OUT);
831
832 if (ret < 0) {
833 IWL_ERR(trans, "Time out on secure boot process\n");
834 return ret;
835 }
836 }
837
cf614297
EG		 838 return 0;
839}
840
0692fe41 841static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
6ae02f3e 842 const struct fw_img *fw, bool run_in_rfkill)
392f8b78
EG		 843{
844 int ret;
c9eec95c 845 bool hw_rfkill;
392f8b78 846
496bab39 847 /* This may fail if AMT took ownership of the device */
7afe3705 848 if (iwl_pcie_prepare_card_hw(trans)) {
6d8f6eeb 849 IWL_WARN(trans, "Exit HW not ready\n");
392f8b78
EG		 850 return -EIO;
851 }
852
8c46bb70
EG		 853 iwl_enable_rfkill_int(trans);
854
392f8b78 855 /* If platform's RF_KILL switch is NOT set to KILL */
8d425517 856 hw_rfkill = iwl_is_rfkill_set(trans);
4620020b 857 if (hw_rfkill)
eb7ff77e 858 set_bit(STATUS_RFKILL, &trans->status);
4620020b 859 else
eb7ff77e 860 clear_bit(STATUS_RFKILL, &trans->status);
14cfca71 861 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
6ae02f3e 862 if (hw_rfkill && !run_in_rfkill)
392f8b78 863 return -ERFKILL;
392f8b78 864
1042db2a 865 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
392f8b78 866
7afe3705 867 ret = iwl_pcie_nic_init(trans);
392f8b78 868 if (ret) {
6d8f6eeb 869 IWL_ERR(trans, "Unable to init nic\n");
392f8b78
EG		 870 return ret;
871 }
872
873 /* make sure rfkill handshake bits are cleared */
1042db2a
EG		 874 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
875 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
392f8b78
EG		 876 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
877
878 /* clear (again), then enable host interrupts */
1042db2a 879 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
6d8f6eeb 880 iwl_enable_interrupts(trans);
392f8b78
EG		 881
882 /* really make sure rfkill handshake bits are cleared */
1042db2a
EG		 883 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
884 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
392f8b78 885
cf614297 886 /* Load the given image to the HW */
7afe3705 887 return iwl_pcie_load_given_ucode(trans, fw);
b3c2ce13
EG		 888}
889
adca1235 890static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
ed6a3803 891{
990aa6d7 892 iwl_pcie_reset_ict(trans);
f02831be 893 iwl_pcie_tx_start(trans, scd_addr);
c170b867
EG		 894}
895
43e58856 896static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
ae2c30bf 897{
43e58856 898 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3dc3374f
EG		 899 bool hw_rfkill, was_hw_rfkill;
900
901 was_hw_rfkill = iwl_is_rfkill_set(trans);
ae2c30bf 902
43e58856 903 /* tell the device to stop sending interrupts */
7b70bd63 904 spin_lock(&trans_pcie->irq_lock);
ae2c30bf 905 iwl_disable_interrupts(trans);
7b70bd63 906 spin_unlock(&trans_pcie->irq_lock);
ae2c30bf 907
ab6cf8e8 908 /* device going down, Stop using ICT table */
990aa6d7 909 iwl_pcie_disable_ict(trans);
ab6cf8e8
EG		 910
911 /*
912 * If a HW restart happens during firmware loading,
913 * then the firmware loading might call this function
914 * and later it might be called again due to the
915 * restart. So don't process again if the device is
916 * already dead.
917 */
31b8b343
EG		 918 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
919 IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n");
f02831be 920 iwl_pcie_tx_stop(trans);
9805c446 921 iwl_pcie_rx_stop(trans);
6379103e 922
ab6cf8e8 923 /* Power-down device's busmaster DMA clocks */
1042db2a 924 iwl_write_prph(trans, APMG_CLK_DIS_REG,
ab6cf8e8
EG		 925 APMG_CLK_VAL_DMA_CLK_RQT);
926 udelay(5);
927 }
928
929 /* Make sure (redundant) we've released our request to stay awake */
1042db2a 930 iwl_clear_bit(trans, CSR_GP_CNTRL,
20d3b647 931 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ab6cf8e8
EG		 932
933 /* Stop the device, and put it in low power state */
7afe3705 934 iwl_pcie_apm_stop(trans);
43e58856
EG		 935
936 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
937 * Clean again the interrupt here
938 */
7b70bd63 939 spin_lock(&trans_pcie->irq_lock);
43e58856 940 iwl_disable_interrupts(trans);
7b70bd63 941 spin_unlock(&trans_pcie->irq_lock);
43e58856 942
43e58856 943 /* stop and reset the on-board processor */
1042db2a 944 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
74fda971
DF		 945
946 /* clear all status bits */
eb7ff77e
AN		 947 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
948 clear_bit(STATUS_INT_ENABLED, &trans->status);
eb7ff77e
AN		 949 clear_bit(STATUS_TPOWER_PMI, &trans->status);
950 clear_bit(STATUS_RFKILL, &trans->status);
a4082843
AN		 951
952 /*
953 * Even if we stop the HW, we still want the RF kill
954 * interrupt
955 */
956 iwl_enable_rfkill_int(trans);
957
958 /*
959 * Check again since the RF kill state may have changed while
960 * all the interrupts were disabled, in this case we couldn't
961 * receive the RF kill interrupt and update the state in the
962 * op_mode.
3dc3374f
EG		 963 * Don't call the op_mode if the rkfill state hasn't changed.
964 * This allows the op_mode to call stop_device from the rfkill
965 * notification without endless recursion. Under very rare
966 * circumstances, we might have a small recursion if the rfkill
967 * state changed exactly now while we were called from stop_device.
968 * This is very unlikely but can happen and is supported.
a4082843
AN		 969 */
970 hw_rfkill = iwl_is_rfkill_set(trans);
971 if (hw_rfkill)
eb7ff77e 972 set_bit(STATUS_RFKILL, &trans->status);
a4082843 973 else
eb7ff77e 974 clear_bit(STATUS_RFKILL, &trans->status);
3dc3374f 975 if (hw_rfkill != was_hw_rfkill)
14cfca71
JB		 976 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
977}
978
979void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
980{
981 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
982 iwl_trans_pcie_stop_device(trans);
ab6cf8e8
EG		 983}
984
debff618 985static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
2dd4f9f7 986{
2dd4f9f7 987 iwl_disable_interrupts(trans);
debff618
JB		 988
989 /*
990 * in testing mode, the host stays awake and the
991 * hardware won't be reset (not even partially)
992 */
993 if (test)
994 return;
995
ddaf5a5b
JB		 996 iwl_pcie_disable_ict(trans);
997
2dd4f9f7
JB		 998 iwl_clear_bit(trans, CSR_GP_CNTRL,
999 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ddaf5a5b
JB		 1000 iwl_clear_bit(trans, CSR_GP_CNTRL,
1001 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1002
1003 /*
1004 * reset TX queues -- some of their registers reset during S3
1005 * so if we don't reset everything here the D3 image would try
1006 * to execute some invalid memory upon resume
1007 */
1008 iwl_trans_pcie_tx_reset(trans);
1009
1010 iwl_pcie_set_pwr(trans, true);
1011}
1012
1013static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
debff618
JB		 1014 enum iwl_d3_status *status,
1015 bool test)
ddaf5a5b
JB		 1016{
1017 u32 val;
1018 int ret;
1019
debff618
JB		 1020 if (test) {
1021 iwl_enable_interrupts(trans);
1022 *status = IWL_D3_STATUS_ALIVE;
1023 return 0;
1024 }
1025
ddaf5a5b
JB		 1026 iwl_pcie_set_pwr(trans, false);
1027
1028 val = iwl_read32(trans, CSR_RESET);
1029 if (val & CSR_RESET_REG_FLAG_NEVO_RESET) {
1030 *status = IWL_D3_STATUS_RESET;
1031 return 0;
1032 }
1033
1034 /*
1035 * Also enables interrupts - none will happen as the device doesn't
1036 * know we're waking it up, only when the opmode actually tells it
1037 * after this call.
1038 */
1039 iwl_pcie_reset_ict(trans);
1040
1041 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1042 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1043
1044 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1045 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1046 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1047 25000);
7f2ac8fb 1048 if (ret < 0) {
ddaf5a5b
JB		 1049 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1050 return ret;
1051 }
1052
1053 iwl_trans_pcie_tx_reset(trans);
1054
1055 ret = iwl_pcie_rx_init(trans);
1056 if (ret) {
1057 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
1058 return ret;
1059 }
1060
ddaf5a5b
JB		 1061 *status = IWL_D3_STATUS_ALIVE;
1062 return 0;
2dd4f9f7
JB		 1063}
1064
57a1dc89 1065static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
e6bb4c9c 1066{
c9eec95c 1067 bool hw_rfkill;
a8b691e6 1068 int err;
e6bb4c9c 1069
7afe3705 1070 err = iwl_pcie_prepare_card_hw(trans);
ebb7678d 1071 if (err) {
d6f1c316 1072 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
a8b691e6 1073 return err;
ebb7678d 1074 }
a6c684ee 1075
2997494f 1076 /* Reset the entire device */
ce836c76 1077 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
2997494f
EG		 1078
1079 usleep_range(10, 15);
1080
7afe3705 1081 iwl_pcie_apm_init(trans);
a6c684ee 1082
226c02ca
EG		 1083 /* From now on, the op_mode will be kept updated about RF kill state */
1084 iwl_enable_rfkill_int(trans);
1085
8d425517 1086 hw_rfkill = iwl_is_rfkill_set(trans);
4620020b 1087 if (hw_rfkill)
eb7ff77e 1088 set_bit(STATUS_RFKILL, &trans->status);
4620020b 1089 else
eb7ff77e 1090 clear_bit(STATUS_RFKILL, &trans->status);
14cfca71 1091 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
d48e2074 1092
a8b691e6 1093 return 0;
e6bb4c9c
EG		 1094}
1095
a4082843 1096static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
cc56feb2 1097{
20d3b647 1098 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
d23f78e6 1099
a4082843 1100 /* disable interrupts - don't enable HW RF kill interrupt */
7b70bd63 1101 spin_lock(&trans_pcie->irq_lock);
ee7d737c 1102 iwl_disable_interrupts(trans);
7b70bd63 1103 spin_unlock(&trans_pcie->irq_lock);
ee7d737c 1104
7afe3705 1105 iwl_pcie_apm_stop(trans);
cc56feb2 1106
7b70bd63 1107 spin_lock(&trans_pcie->irq_lock);
218733cf 1108 iwl_disable_interrupts(trans);
7b70bd63 1109 spin_unlock(&trans_pcie->irq_lock);
1df06bdc 1110
8d96bb61 1111 iwl_pcie_disable_ict(trans);
cc56feb2
EG		 1112}
1113
03905495
EG		 1114static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1115{
05f5b97e 1116 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1117}
1118
1119static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1120{
05f5b97e 1121 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1122}
1123
1124static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1125{
05f5b97e 1126 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1127}
1128
6a06b6c1
EG		 1129static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1130{
f9477c17
AP		 1131 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1132 ((reg & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1133 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1134}
1135
1136static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1137 u32 val)
1138{
1139 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
f9477c17 1140 ((addr & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1141 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1142}
1143
f14d6b39
JB		 1144static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1145{
1146 WARN_ON(1);
1147 return 0;
1148}
1149
c6f600fc 1150static void iwl_trans_pcie_configure(struct iwl_trans *trans,
9eae88fa 1151 const struct iwl_trans_config *trans_cfg)
c6f600fc
MV		 1152{
1153 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1154
1155 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
b04db9ac 1156 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
d663ee73
JB		 1157 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1158 trans_pcie->n_no_reclaim_cmds = 0;
1159 else
1160 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1161 if (trans_pcie->n_no_reclaim_cmds)
1162 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1163 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
9eae88fa 1164
b2cf410c
JB		 1165 trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1166 if (trans_pcie->rx_buf_size_8k)
1167 trans_pcie->rx_page_order = get_order(8 * 1024);
1168 else
1169 trans_pcie->rx_page_order = get_order(4 * 1024);
7c5ba4a8
JB		 1170
1171 trans_pcie->wd_timeout =
1172 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
d9fb6465
JB		 1173
1174 trans_pcie->command_names = trans_cfg->command_names;
046db346 1175 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
3a736bcb 1176 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
f14d6b39
JB		 1177
1178 /* Initialize NAPI here - it should be before registering to mac80211
1179 * in the opmode but after the HW struct is allocated.
1180 * As this function may be called again in some corner cases don't
1181 * do anything if NAPI was already initialized.
1182 */
1183 if (!trans_pcie->napi.poll && trans->op_mode->ops->napi_add) {
1184 init_dummy_netdev(&trans_pcie->napi_dev);
1185 iwl_op_mode_napi_add(trans->op_mode, &trans_pcie->napi,
1186 &trans_pcie->napi_dev,
1187 iwl_pcie_dummy_napi_poll, 64);
1188 }
c6f600fc
MV		 1189}
1190
d1ff5253 1191void iwl_trans_pcie_free(struct iwl_trans *trans)
34c1b7ba 1192{
20d3b647 1193 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
a42a1844 1194
0aa86df6 1195 synchronize_irq(trans_pcie->pci_dev->irq);
0aa86df6 1196
f02831be 1197 iwl_pcie_tx_free(trans);
9805c446 1198 iwl_pcie_rx_free(trans);
6379103e 1199
a8b691e6
JB		 1200 free_irq(trans_pcie->pci_dev->irq, trans);
1201 iwl_pcie_free_ict(trans);
a42a1844
EG		 1202
1203 pci_disable_msi(trans_pcie->pci_dev);
05f5b97e 1204 iounmap(trans_pcie->hw_base);
a42a1844
EG		 1205 pci_release_regions(trans_pcie->pci_dev);
1206 pci_disable_device(trans_pcie->pci_dev);
59c647b6 1207 kmem_cache_destroy(trans->dev_cmd_pool);
a42a1844 1208
f14d6b39
JB		 1209 if (trans_pcie->napi.poll)
1210 netif_napi_del(&trans_pcie->napi);
1211
c2d20201
EG		 1212 iwl_pcie_free_fw_monitor(trans);
1213
6d8f6eeb 1214 kfree(trans);
34c1b7ba
EG		 1215}
1216
47107e84
DF		 1217static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1218{
47107e84 1219 if (state)
eb7ff77e 1220 set_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84 1221 else
eb7ff77e 1222 clear_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84
DF		 1223}
1224
e56b04ef
LE		 1225static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
1226 unsigned long *flags)
7a65d170
EG		 1227{
1228 int ret;
cfb4e624
JB		 1229 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1230
1231 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
7a65d170 1232
b9439491
EG		 1233 if (trans_pcie->cmd_in_flight)
1234 goto out;
1235
7a65d170 1236 /* this bit wakes up the NIC */
e139dc4a
LE		 1237 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1238 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
7a65d170
EG		 1239
1240 /*
1241 * These bits say the device is running, and should keep running for
1242 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1243 * but they do not indicate that embedded SRAM is restored yet;
1244 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1245 * to/from host DRAM when sleeping/waking for power-saving.
1246 * Each direction takes approximately 1/4 millisecond; with this
1247 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1248 * series of register accesses are expected (e.g. reading Event Log),
1249 * to keep device from sleeping.
1250 *
1251 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1252 * SRAM is okay/restored. We don't check that here because this call
1253 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1254 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1255 *
1256 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1257 * and do not save/restore SRAM when power cycling.
1258 */
1259 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1260 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1261 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1262 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1263 if (unlikely(ret < 0)) {
1264 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1265 if (!silent) {
1266 u32 val = iwl_read32(trans, CSR_GP_CNTRL);
1267 WARN_ONCE(1,
1268 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1269 val);
cfb4e624 1270 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 1271 return false;
1272 }
1273 }
1274
b9439491 1275out:
e56b04ef
LE		 1276 /*
1277 * Fool sparse by faking we release the lock - sparse will
1278 * track nic_access anyway.
1279 */
cfb4e624 1280 __release(&trans_pcie->reg_lock);
7a65d170
EG		 1281 return true;
1282}
1283
e56b04ef
LE		 1284static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1285 unsigned long *flags)
7a65d170 1286{
cfb4e624 1287 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e56b04ef 1288
cfb4e624 1289 lockdep_assert_held(&trans_pcie->reg_lock);
e56b04ef
LE		 1290
1291 /*
1292 * Fool sparse by faking we acquiring the lock - sparse will
1293 * track nic_access anyway.
1294 */
cfb4e624 1295 __acquire(&trans_pcie->reg_lock);
e56b04ef 1296
b9439491
EG		 1297 if (trans_pcie->cmd_in_flight)
1298 goto out;
1299
e139dc4a
LE		 1300 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1301 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
7a65d170
EG		 1302 /*
1303 * Above we read the CSR_GP_CNTRL register, which will flush
1304 * any previous writes, but we need the write that clears the
1305 * MAC_ACCESS_REQ bit to be performed before any other writes
1306 * scheduled on different CPUs (after we drop reg_lock).
1307 */
1308 mmiowb();
b9439491 1309out:
cfb4e624 1310 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 1311}
1312
4fd442db
EG		 1313static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1314 void *buf, int dwords)
1315{
1316 unsigned long flags;
1317 int offs, ret = 0;
1318 u32 *vals = buf;
1319
e56b04ef 1320 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
4fd442db
EG		 1321 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1322 for (offs = 0; offs < dwords; offs++)
1323 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
e56b04ef 1324 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1325 } else {
1326 ret = -EBUSY;
1327 }
4fd442db
EG		 1328 return ret;
1329}
1330
1331static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
bf0fd5da 1332 const void *buf, int dwords)
4fd442db
EG		 1333{
1334 unsigned long flags;
1335 int offs, ret = 0;
bf0fd5da 1336 const u32 *vals = buf;
4fd442db 1337
e56b04ef 1338 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
4fd442db
EG		 1339 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1340 for (offs = 0; offs < dwords; offs++)
01387ffd
EG		 1341 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1342 vals ? vals[offs] : 0);
e56b04ef 1343 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1344 } else {
1345 ret = -EBUSY;
1346 }
4fd442db
EG		 1347 return ret;
1348}
7a65d170 1349
5f178cd2
EG		 1350#define IWL_FLUSH_WAIT_MS 2000
1351
3cafdbe6 1352static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
5f178cd2 1353{
8ad71bef 1354 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1355 struct iwl_txq *txq;
5f178cd2
EG		 1356 struct iwl_queue *q;
1357 int cnt;
1358 unsigned long now = jiffies;
1c3fea82
EG		 1359 u32 scd_sram_addr;
1360 u8 buf[16];
5f178cd2
EG		 1361 int ret = 0;
1362
1363 /* waiting for all the tx frames complete might take a while */
035f7ff2 1364 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
fa1a91fd
EG		 1365 u8 wr_ptr;
1366
9ba1947a 1367 if (cnt == trans_pcie->cmd_queue)
5f178cd2 1368 continue;
3cafdbe6
EG		 1369 if (!test_bit(cnt, trans_pcie->queue_used))
1370 continue;
1371 if (!(BIT(cnt) & txq_bm))
1372 continue;
748fa67c
EG		 1373
1374 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
8ad71bef 1375 txq = &trans_pcie->txq[cnt];
5f178cd2 1376 q = &txq->q;
fa1a91fd
EG		 1377 wr_ptr = ACCESS_ONCE(q->write_ptr);
1378
1379 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1380 !time_after(jiffies,
1381 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1382 u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1383
1384 if (WARN_ONCE(wr_ptr != write_ptr,
1385 "WR pointer moved while flushing %d -> %d\n",
1386 wr_ptr, write_ptr))
1387 return -ETIMEDOUT;
5f178cd2 1388 msleep(1);
fa1a91fd 1389 }
5f178cd2
EG		 1390
1391 if (q->read_ptr != q->write_ptr) {
1c3fea82
EG		 1392 IWL_ERR(trans,
1393 "fail to flush all tx fifo queues Q %d\n", cnt);
5f178cd2
EG		 1394 ret = -ETIMEDOUT;
1395 break;
1396 }
748fa67c 1397 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
5f178cd2 1398 }
1c3fea82
EG		 1399
1400 if (!ret)
1401 return 0;
1402
1403 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1404 txq->q.read_ptr, txq->q.write_ptr);
1405
1406 scd_sram_addr = trans_pcie->scd_base_addr +
1407 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1408 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1409
1410 iwl_print_hex_error(trans, buf, sizeof(buf));
1411
1412 for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1413 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1414 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1415
1416 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1417 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1418 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1419 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1420 u32 tbl_dw =
1421 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1422 SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1423
1424 if (cnt & 0x1)
1425 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1426 else
1427 tbl_dw = tbl_dw & 0x0000FFFF;
1428
1429 IWL_ERR(trans,
1430 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1431 cnt, active ? "" : "in", fifo, tbl_dw,
83f32a4b
JB		 1432 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1433 (TFD_QUEUE_SIZE_MAX - 1),
1c3fea82
EG		 1434 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1435 }
1436
5f178cd2
EG		 1437 return ret;
1438}
1439
e139dc4a
LE		 1440static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1441 u32 mask, u32 value)
1442{
e56b04ef 1443 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e139dc4a
LE		 1444 unsigned long flags;
1445
e56b04ef 1446 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
e139dc4a 1447 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
e56b04ef 1448 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
e139dc4a
LE		 1449}
1450
ff620849
EG		 1451static const char *get_csr_string(int cmd)
1452{
d9fb6465 1453#define IWL_CMD(x) case x: return #x
ff620849
EG		 1454 switch (cmd) {
1455 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1456 IWL_CMD(CSR_INT_COALESCING);
1457 IWL_CMD(CSR_INT);
1458 IWL_CMD(CSR_INT_MASK);
1459 IWL_CMD(CSR_FH_INT_STATUS);
1460 IWL_CMD(CSR_GPIO_IN);
1461 IWL_CMD(CSR_RESET);
1462 IWL_CMD(CSR_GP_CNTRL);
1463 IWL_CMD(CSR_HW_REV);
1464 IWL_CMD(CSR_EEPROM_REG);
1465 IWL_CMD(CSR_EEPROM_GP);
1466 IWL_CMD(CSR_OTP_GP_REG);
1467 IWL_CMD(CSR_GIO_REG);
1468 IWL_CMD(CSR_GP_UCODE_REG);
1469 IWL_CMD(CSR_GP_DRIVER_REG);
1470 IWL_CMD(CSR_UCODE_DRV_GP1);
1471 IWL_CMD(CSR_UCODE_DRV_GP2);
1472 IWL_CMD(CSR_LED_REG);
1473 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1474 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1475 IWL_CMD(CSR_ANA_PLL_CFG);
1476 IWL_CMD(CSR_HW_REV_WA_REG);
a812cba9 1477 IWL_CMD(CSR_MONITOR_STATUS_REG);
ff620849
EG		 1478 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1479 default:
1480 return "UNKNOWN";
1481 }
d9fb6465 1482#undef IWL_CMD
ff620849
EG		 1483}
1484
990aa6d7 1485void iwl_pcie_dump_csr(struct iwl_trans *trans)
ff620849
EG		 1486{
1487 int i;
1488 static const u32 csr_tbl[] = {
1489 CSR_HW_IF_CONFIG_REG,
1490 CSR_INT_COALESCING,
1491 CSR_INT,
1492 CSR_INT_MASK,
1493 CSR_FH_INT_STATUS,
1494 CSR_GPIO_IN,
1495 CSR_RESET,
1496 CSR_GP_CNTRL,
1497 CSR_HW_REV,
1498 CSR_EEPROM_REG,
1499 CSR_EEPROM_GP,
1500 CSR_OTP_GP_REG,
1501 CSR_GIO_REG,
1502 CSR_GP_UCODE_REG,
1503 CSR_GP_DRIVER_REG,
1504 CSR_UCODE_DRV_GP1,
1505 CSR_UCODE_DRV_GP2,
1506 CSR_LED_REG,
1507 CSR_DRAM_INT_TBL_REG,
1508 CSR_GIO_CHICKEN_BITS,
1509 CSR_ANA_PLL_CFG,
a812cba9 1510 CSR_MONITOR_STATUS_REG,
ff620849
EG		 1511 CSR_HW_REV_WA_REG,
1512 CSR_DBG_HPET_MEM_REG
1513 };
1514 IWL_ERR(trans, "CSR values:\n");
1515 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1516 "CSR_INT_PERIODIC_REG)\n");
1517 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1518 IWL_ERR(trans, " %25s: 0X%08x\n",
1519 get_csr_string(csr_tbl[i]),
1042db2a 1520 iwl_read32(trans, csr_tbl[i]));
ff620849
EG		 1521 }
1522}
1523
87e5666c
EG		 1524#ifdef CONFIG_IWLWIFI_DEBUGFS
1525/* create and remove of files */
1526#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
5a878bf6 1527 if (!debugfs_create_file(#name, mode, parent, trans, \
87e5666c 1528 &iwl_dbgfs_##name##_ops)) \
9da987ac 1529 goto err; \
87e5666c
EG		 1530} while (0)
1531
1532/* file operation */
87e5666c 1533#define DEBUGFS_READ_FILE_OPS(name) \
87e5666c
EG		 1534static const struct file_operations iwl_dbgfs_##name##_ops = { \
1535 .read = iwl_dbgfs_##name##_read, \
234e3405 1536 .open = simple_open, \
87e5666c
EG		 1537 .llseek = generic_file_llseek, \
1538};
1539
16db88ba 1540#define DEBUGFS_WRITE_FILE_OPS(name) \
16db88ba
EG		 1541static const struct file_operations iwl_dbgfs_##name##_ops = { \
1542 .write = iwl_dbgfs_##name##_write, \
234e3405 1543 .open = simple_open, \
16db88ba
EG		 1544 .llseek = generic_file_llseek, \
1545};
1546
87e5666c 1547#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
87e5666c
EG		 1548static const struct file_operations iwl_dbgfs_##name##_ops = { \
1549 .write = iwl_dbgfs_##name##_write, \
1550 .read = iwl_dbgfs_##name##_read, \
234e3405 1551 .open = simple_open, \
87e5666c
EG		 1552 .llseek = generic_file_llseek, \
1553};
1554
87e5666c 1555static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
20d3b647
JB		 1556 char __user *user_buf,
1557 size_t count, loff_t *ppos)
8ad71bef 1558{
5a878bf6 1559 struct iwl_trans *trans = file->private_data;
8ad71bef 1560 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1561 struct iwl_txq *txq;
87e5666c
EG		 1562 struct iwl_queue *q;
1563 char *buf;
1564 int pos = 0;
1565 int cnt;
1566 int ret;
1745e440
WYG		 1567 size_t bufsz;
1568
035f7ff2 1569 bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
87e5666c 1570
f9e75447 1571 if (!trans_pcie->txq)
87e5666c 1572 return -EAGAIN;
f9e75447 1573
87e5666c
EG		 1574 buf = kzalloc(bufsz, GFP_KERNEL);
1575 if (!buf)
1576 return -ENOMEM;
1577
035f7ff2 1578 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
8ad71bef 1579 txq = &trans_pcie->txq[cnt];
87e5666c
EG		 1580 q = &txq->q;
1581 pos += scnprintf(buf + pos, bufsz - pos,
f40faf62 1582 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d%s\n",
87e5666c 1583 cnt, q->read_ptr, q->write_ptr,
9eae88fa 1584 !!test_bit(cnt, trans_pcie->queue_used),
f40faf62
AL		 1585 !!test_bit(cnt, trans_pcie->queue_stopped),
1586 txq->need_update,
1587 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
87e5666c
EG		 1588 }
1589 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1590 kfree(buf);
1591 return ret;
1592}
1593
1594static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
20d3b647
JB		 1595 char __user *user_buf,
1596 size_t count, loff_t *ppos)
1597{
5a878bf6 1598 struct iwl_trans *trans = file->private_data;
20d3b647 1599 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1600 struct iwl_rxq *rxq = &trans_pcie->rxq;
87e5666c
EG		 1601 char buf[256];
1602 int pos = 0;
1603 const size_t bufsz = sizeof(buf);
1604
1605 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1606 rxq->read);
1607 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1608 rxq->write);
f40faf62
AL		 1609 pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n",
1610 rxq->write_actual);
1611 pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n",
1612 rxq->need_update);
87e5666c
EG		 1613 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1614 rxq->free_count);
1615 if (rxq->rb_stts) {
1616 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1617 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1618 } else {
1619 pos += scnprintf(buf + pos, bufsz - pos,
1620 "closed_rb_num: Not Allocated\n");
1621 }
1622 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1623}
1624
1f7b6172
EG		 1625static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1626 char __user *user_buf,
20d3b647
JB		 1627 size_t count, loff_t *ppos)
1628{
1f7b6172 1629 struct iwl_trans *trans = file->private_data;
20d3b647 1630 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 1631 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1632
1633 int pos = 0;
1634 char *buf;
1635 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1636 ssize_t ret;
1637
1638 buf = kzalloc(bufsz, GFP_KERNEL);
f9e75447 1639 if (!buf)
1f7b6172 1640 return -ENOMEM;
1f7b6172
EG		 1641
1642 pos += scnprintf(buf + pos, bufsz - pos,
1643 "Interrupt Statistics Report:\n");
1644
1645 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1646 isr_stats->hw);
1647 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1648 isr_stats->sw);
1649 if (isr_stats->sw || isr_stats->hw) {
1650 pos += scnprintf(buf + pos, bufsz - pos,
1651 "\tLast Restarting Code: 0x%X\n",
1652 isr_stats->err_code);
1653 }
1654#ifdef CONFIG_IWLWIFI_DEBUG
1655 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1656 isr_stats->sch);
1657 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1658 isr_stats->alive);
1659#endif
1660 pos += scnprintf(buf + pos, bufsz - pos,
1661 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1662
1663 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1664 isr_stats->ctkill);
1665
1666 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1667 isr_stats->wakeup);
1668
1669 pos += scnprintf(buf + pos, bufsz - pos,
1670 "Rx command responses:\t\t %u\n", isr_stats->rx);
1671
1672 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1673 isr_stats->tx);
1674
1675 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1676 isr_stats->unhandled);
1677
1678 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1679 kfree(buf);
1680 return ret;
1681}
1682
1683static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1684 const char __user *user_buf,
1685 size_t count, loff_t *ppos)
1686{
1687 struct iwl_trans *trans = file->private_data;
20d3b647 1688 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 1689 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1690
1691 char buf[8];
1692 int buf_size;
1693 u32 reset_flag;
1694
1695 memset(buf, 0, sizeof(buf));
1696 buf_size = min(count, sizeof(buf) - 1);
1697 if (copy_from_user(buf, user_buf, buf_size))
1698 return -EFAULT;
1699 if (sscanf(buf, "%x", &reset_flag) != 1)
1700 return -EFAULT;
1701 if (reset_flag == 0)
1702 memset(isr_stats, 0, sizeof(*isr_stats));
1703
1704 return count;
1705}
1706
16db88ba 1707static ssize_t iwl_dbgfs_csr_write(struct file *file,
20d3b647
JB		 1708 const char __user *user_buf,
1709 size_t count, loff_t *ppos)
16db88ba
EG		 1710{
1711 struct iwl_trans *trans = file->private_data;
1712 char buf[8];
1713 int buf_size;
1714 int csr;
1715
1716 memset(buf, 0, sizeof(buf));
1717 buf_size = min(count, sizeof(buf) - 1);
1718 if (copy_from_user(buf, user_buf, buf_size))
1719 return -EFAULT;
1720 if (sscanf(buf, "%d", &csr) != 1)
1721 return -EFAULT;
1722
990aa6d7 1723 iwl_pcie_dump_csr(trans);
16db88ba
EG		 1724
1725 return count;
1726}
1727
16db88ba 1728static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
20d3b647
JB		 1729 char __user *user_buf,
1730 size_t count, loff_t *ppos)
16db88ba
EG		 1731{
1732 struct iwl_trans *trans = file->private_data;
94543a8d 1733 char *buf = NULL;
56c2477f 1734 ssize_t ret;
16db88ba 1735
56c2477f
JB		 1736 ret = iwl_dump_fh(trans, &buf);
1737 if (ret < 0)
1738 return ret;
1739 if (!buf)
1740 return -EINVAL;
1741 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
1742 kfree(buf);
16db88ba
EG		 1743 return ret;
1744}
1745
1f7b6172 1746DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
16db88ba 1747DEBUGFS_READ_FILE_OPS(fh_reg);
87e5666c
EG		 1748DEBUGFS_READ_FILE_OPS(rx_queue);
1749DEBUGFS_READ_FILE_OPS(tx_queue);
16db88ba 1750DEBUGFS_WRITE_FILE_OPS(csr);
87e5666c
EG		 1751
1752/*
1753 * Create the debugfs files and directories
1754 *
1755 */
1756static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
20d3b647 1757 struct dentry *dir)
87e5666c 1758{
87e5666c
EG		 1759 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1760 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1f7b6172 1761 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
16db88ba
EG		 1762 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1763 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
87e5666c 1764 return 0;
9da987ac
MV		 1765
1766err:
1767 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1768 return -ENOMEM;
87e5666c 1769}
4d075007
JB		 1770
1771static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
1772{
1773 u32 cmdlen = 0;
1774 int i;
1775
1776 for (i = 0; i < IWL_NUM_OF_TBS; i++)
1777 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
1778
1779 return cmdlen;
1780}
1781
67c65f2c
EG		 1782static const struct {
1783 u32 start, end;
1784} iwl_prph_dump_addr[] = {
1785 { .start = 0x00a00000, .end = 0x00a00000 },
1786 { .start = 0x00a0000c, .end = 0x00a00024 },
1787 { .start = 0x00a0002c, .end = 0x00a0003c },
1788 { .start = 0x00a00410, .end = 0x00a00418 },
1789 { .start = 0x00a00420, .end = 0x00a00420 },
1790 { .start = 0x00a00428, .end = 0x00a00428 },
1791 { .start = 0x00a00430, .end = 0x00a0043c },
1792 { .start = 0x00a00444, .end = 0x00a00444 },
1793 { .start = 0x00a004c0, .end = 0x00a004cc },
1794 { .start = 0x00a004d8, .end = 0x00a004d8 },
1795 { .start = 0x00a004e0, .end = 0x00a004f0 },
1796 { .start = 0x00a00840, .end = 0x00a00840 },
1797 { .start = 0x00a00850, .end = 0x00a00858 },
1798 { .start = 0x00a01004, .end = 0x00a01008 },
1799 { .start = 0x00a01010, .end = 0x00a01010 },
1800 { .start = 0x00a01018, .end = 0x00a01018 },
1801 { .start = 0x00a01024, .end = 0x00a01024 },
1802 { .start = 0x00a0102c, .end = 0x00a01034 },
1803 { .start = 0x00a0103c, .end = 0x00a01040 },
1804 { .start = 0x00a01048, .end = 0x00a01094 },
1805 { .start = 0x00a01c00, .end = 0x00a01c20 },
1806 { .start = 0x00a01c58, .end = 0x00a01c58 },
1807 { .start = 0x00a01c7c, .end = 0x00a01c7c },
1808 { .start = 0x00a01c28, .end = 0x00a01c54 },
1809 { .start = 0x00a01c5c, .end = 0x00a01c5c },
1810 { .start = 0x00a01c84, .end = 0x00a01c84 },
1811 { .start = 0x00a01ce0, .end = 0x00a01d0c },
1812 { .start = 0x00a01d18, .end = 0x00a01d20 },
1813 { .start = 0x00a01d2c, .end = 0x00a01d30 },
1814 { .start = 0x00a01d40, .end = 0x00a01d5c },
1815 { .start = 0x00a01d80, .end = 0x00a01d80 },
1816 { .start = 0x00a01d98, .end = 0x00a01d98 },
1817 { .start = 0x00a01dc0, .end = 0x00a01dfc },
1818 { .start = 0x00a01e00, .end = 0x00a01e2c },
1819 { .start = 0x00a01e40, .end = 0x00a01e60 },
1820 { .start = 0x00a01e84, .end = 0x00a01e90 },
1821 { .start = 0x00a01e9c, .end = 0x00a01ec4 },
1822 { .start = 0x00a01ed0, .end = 0x00a01ed0 },
1823 { .start = 0x00a01f00, .end = 0x00a01f14 },
1824 { .start = 0x00a01f44, .end = 0x00a01f58 },
1825 { .start = 0x00a01f80, .end = 0x00a01fa8 },
1826 { .start = 0x00a01fb0, .end = 0x00a01fbc },
1827 { .start = 0x00a01ff8, .end = 0x00a01ffc },
1828 { .start = 0x00a02000, .end = 0x00a02048 },
1829 { .start = 0x00a02068, .end = 0x00a020f0 },
1830 { .start = 0x00a02100, .end = 0x00a02118 },
1831 { .start = 0x00a02140, .end = 0x00a0214c },
1832 { .start = 0x00a02168, .end = 0x00a0218c },
1833 { .start = 0x00a021c0, .end = 0x00a021c0 },
1834 { .start = 0x00a02400, .end = 0x00a02410 },
1835 { .start = 0x00a02418, .end = 0x00a02420 },
1836 { .start = 0x00a02428, .end = 0x00a0242c },
1837 { .start = 0x00a02434, .end = 0x00a02434 },
1838 { .start = 0x00a02440, .end = 0x00a02460 },
1839 { .start = 0x00a02468, .end = 0x00a024b0 },
1840 { .start = 0x00a024c8, .end = 0x00a024cc },
1841 { .start = 0x00a02500, .end = 0x00a02504 },
1842 { .start = 0x00a0250c, .end = 0x00a02510 },
1843 { .start = 0x00a02540, .end = 0x00a02554 },
1844 { .start = 0x00a02580, .end = 0x00a025f4 },
1845 { .start = 0x00a02600, .end = 0x00a0260c },
1846 { .start = 0x00a02648, .end = 0x00a02650 },
1847 { .start = 0x00a02680, .end = 0x00a02680 },
1848 { .start = 0x00a026c0, .end = 0x00a026d0 },
1849 { .start = 0x00a02700, .end = 0x00a0270c },
1850 { .start = 0x00a02804, .end = 0x00a02804 },
1851 { .start = 0x00a02818, .end = 0x00a0281c },
1852 { .start = 0x00a02c00, .end = 0x00a02db4 },
1853 { .start = 0x00a02df4, .end = 0x00a02fb0 },
1854 { .start = 0x00a03000, .end = 0x00a03014 },
1855 { .start = 0x00a0301c, .end = 0x00a0302c },
1856 { .start = 0x00a03034, .end = 0x00a03038 },
1857 { .start = 0x00a03040, .end = 0x00a03048 },
1858 { .start = 0x00a03060, .end = 0x00a03068 },
1859 { .start = 0x00a03070, .end = 0x00a03074 },
1860 { .start = 0x00a0307c, .end = 0x00a0307c },
1861 { .start = 0x00a03080, .end = 0x00a03084 },
1862 { .start = 0x00a0308c, .end = 0x00a03090 },
1863 { .start = 0x00a03098, .end = 0x00a03098 },
1864 { .start = 0x00a030a0, .end = 0x00a030a0 },
1865 { .start = 0x00a030a8, .end = 0x00a030b4 },
1866 { .start = 0x00a030bc, .end = 0x00a030bc },
1867 { .start = 0x00a030c0, .end = 0x00a0312c },
1868 { .start = 0x00a03c00, .end = 0x00a03c5c },
1869 { .start = 0x00a04400, .end = 0x00a04454 },
1870 { .start = 0x00a04460, .end = 0x00a04474 },
1871 { .start = 0x00a044c0, .end = 0x00a044ec },
1872 { .start = 0x00a04500, .end = 0x00a04504 },
1873 { .start = 0x00a04510, .end = 0x00a04538 },
1874 { .start = 0x00a04540, .end = 0x00a04548 },
1875 { .start = 0x00a04560, .end = 0x00a0457c },
1876 { .start = 0x00a04590, .end = 0x00a04598 },
1877 { .start = 0x00a045c0, .end = 0x00a045f4 },
1878};
1879
1880static u32 iwl_trans_pcie_dump_prph(struct iwl_trans *trans,
1881 struct iwl_fw_error_dump_data **data)
1882{
1883 struct iwl_fw_error_dump_prph *prph;
1884 unsigned long flags;
1885 u32 prph_len = 0, i;
1886
1887 if (!iwl_trans_grab_nic_access(trans, false, &flags))
1888 return 0;
1889
1890 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
1891 /* The range includes both boundaries */
1892 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
1893 iwl_prph_dump_addr[i].start + 4;
1894 int reg;
1895 __le32 *val;
1896
87dd634a 1897 prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk;
67c65f2c
EG		 1898
1899 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
1900 (*data)->len = cpu_to_le32(sizeof(*prph) +
1901 num_bytes_in_chunk);
1902 prph = (void *)(*data)->data;
1903 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
1904 val = (void *)prph->data;
1905
1906 for (reg = iwl_prph_dump_addr[i].start;
1907 reg <= iwl_prph_dump_addr[i].end;
1908 reg += 4)
1909 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
1910 reg));
1911 *data = iwl_fw_error_next_data(*data);
1912 }
1913
1914 iwl_trans_release_nic_access(trans, &flags);
1915
1916 return prph_len;
1917}
1918
473ad712
EG		 1919#define IWL_CSR_TO_DUMP (0x250)
1920
1921static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
1922 struct iwl_fw_error_dump_data **data)
1923{
1924 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
1925 __le32 *val;
1926 int i;
1927
1928 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
1929 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
1930 val = (void *)(*data)->data;
1931
1932 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
1933 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
1934
1935 *data = iwl_fw_error_next_data(*data);
1936
1937 return csr_len;
1938}
1939
48eb7b34
EG		 1940static
1941struct iwl_trans_dump_data *iwl_trans_pcie_dump_data(struct iwl_trans *trans)
4d075007
JB		 1942{
1943 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1944 struct iwl_fw_error_dump_data *data;
1945 struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
1946 struct iwl_fw_error_dump_txcmd *txcmd;
48eb7b34 1947 struct iwl_trans_dump_data *dump_data;
4d075007
JB		 1948 u32 len;
1949 int i, ptr;
1950
473ad712
EG		 1951 /* transport dump header */
1952 len = sizeof(*dump_data);
1953
1954 /* host commands */
1955 len += sizeof(*data) +
c2d20201
EG		 1956 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
1957
473ad712
EG		 1958 /* CSR registers */
1959 len += sizeof(*data) + IWL_CSR_TO_DUMP;
1960
1961 /* PRPH registers */
67c65f2c
EG		 1962 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
1963 /* The range includes both boundaries */
1964 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
1965 iwl_prph_dump_addr[i].start + 4;
1966
1967 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_prph) +
1968 num_bytes_in_chunk;
1969 }
1970
473ad712 1971 /* FW monitor */
c2d20201 1972 if (trans_pcie->fw_mon_page)
c544e9c4 1973 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
c2d20201
EG		 1974 trans_pcie->fw_mon_size;
1975
48eb7b34
EG		 1976 dump_data = vzalloc(len);
1977 if (!dump_data)
1978 return NULL;
4d075007
JB		 1979
1980 len = 0;
48eb7b34 1981 data = (void *)dump_data->data;
4d075007
JB		 1982 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
1983 txcmd = (void *)data->data;
1984 spin_lock_bh(&cmdq->lock);
1985 ptr = cmdq->q.write_ptr;
1986 for (i = 0; i < cmdq->q.n_window; i++) {
1987 u8 idx = get_cmd_index(&cmdq->q, ptr);
1988 u32 caplen, cmdlen;
1989
1990 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
1991 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
1992
1993 if (cmdlen) {
1994 len += sizeof(*txcmd) + caplen;
1995 txcmd->cmdlen = cpu_to_le32(cmdlen);
1996 txcmd->caplen = cpu_to_le32(caplen);
1997 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
1998 txcmd = (void *)((u8 *)txcmd->data + caplen);
1999 }
2000
2001 ptr = iwl_queue_dec_wrap(ptr);
2002 }
2003 spin_unlock_bh(&cmdq->lock);
2004
2005 data->len = cpu_to_le32(len);
c2d20201 2006 len += sizeof(*data);
67c65f2c
EG		 2007 data = iwl_fw_error_next_data(data);
2008
2009 len += iwl_trans_pcie_dump_prph(trans, &data);
473ad712 2010 len += iwl_trans_pcie_dump_csr(trans, &data);
67c65f2c 2011 /* data is already pointing to the next section */
c2d20201
EG		 2012
2013 if (trans_pcie->fw_mon_page) {
c544e9c4 2014 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
c2d20201 2015
c2d20201
EG		 2016 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2017 data->len = cpu_to_le32(trans_pcie->fw_mon_size +
2018 sizeof(*fw_mon_data));
2019 fw_mon_data = (void *)data->data;
2020 fw_mon_data->fw_mon_wr_ptr =
2021 cpu_to_le32(iwl_read_prph(trans, MON_BUFF_WRPTR));
2022 fw_mon_data->fw_mon_cycle_cnt =
2023 cpu_to_le32(iwl_read_prph(trans, MON_BUFF_CYCLE_CNT));
2024 fw_mon_data->fw_mon_base_ptr =
2025 cpu_to_le32(iwl_read_prph(trans, MON_BUFF_BASE_ADDR));
2026
2027 /*
2028 * The firmware is now asserted, it won't write anything to
2029 * the buffer. CPU can take ownership to fetch the data.
2030 * The buffer will be handed back to the device before the
2031 * firmware will be restarted.
2032 */
2033 dma_sync_single_for_cpu(trans->dev, trans_pcie->fw_mon_phys,
2034 trans_pcie->fw_mon_size,
2035 DMA_FROM_DEVICE);
2036 memcpy(fw_mon_data->data, page_address(trans_pcie->fw_mon_page),
2037 trans_pcie->fw_mon_size);
2038
2039 len += sizeof(*data) + sizeof(*fw_mon_data) +
2040 trans_pcie->fw_mon_size;
2041 }
2042
48eb7b34
EG		 2043 dump_data->len = len;
2044
2045 return dump_data;
4d075007 2046}
87e5666c
EG		 2047#else
2048static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
20d3b647
JB		 2049 struct dentry *dir)
2050{
2051 return 0;
2052}
87e5666c
EG		 2053#endif /*CONFIG_IWLWIFI_DEBUGFS */
2054
d1ff5253 2055static const struct iwl_trans_ops trans_ops_pcie = {
57a1dc89 2056 .start_hw = iwl_trans_pcie_start_hw,
a4082843 2057 .op_mode_leave = iwl_trans_pcie_op_mode_leave,
ed6a3803 2058 .fw_alive = iwl_trans_pcie_fw_alive,
cf614297 2059 .start_fw = iwl_trans_pcie_start_fw,
e6bb4c9c 2060 .stop_device = iwl_trans_pcie_stop_device,
48d42c42 2061
ddaf5a5b
JB		 2062 .d3_suspend = iwl_trans_pcie_d3_suspend,
2063 .d3_resume = iwl_trans_pcie_d3_resume,
2dd4f9f7 2064
f02831be 2065 .send_cmd = iwl_trans_pcie_send_hcmd,
c85eb619 2066
e6bb4c9c 2067 .tx = iwl_trans_pcie_tx,
a0eaad71 2068 .reclaim = iwl_trans_pcie_reclaim,
34c1b7ba 2069
d0624be6 2070 .txq_disable = iwl_trans_pcie_txq_disable,
4beaf6c2 2071 .txq_enable = iwl_trans_pcie_txq_enable,
34c1b7ba 2072
87e5666c 2073 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
5f178cd2 2074
990aa6d7 2075 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
5f178cd2 2076
03905495
EG		 2077 .write8 = iwl_trans_pcie_write8,
2078 .write32 = iwl_trans_pcie_write32,
2079 .read32 = iwl_trans_pcie_read32,
6a06b6c1
EG		 2080 .read_prph = iwl_trans_pcie_read_prph,
2081 .write_prph = iwl_trans_pcie_write_prph,
4fd442db
EG		 2082 .read_mem = iwl_trans_pcie_read_mem,
2083 .write_mem = iwl_trans_pcie_write_mem,
c6f600fc 2084 .configure = iwl_trans_pcie_configure,
47107e84 2085 .set_pmi = iwl_trans_pcie_set_pmi,
7a65d170 2086 .grab_nic_access = iwl_trans_pcie_grab_nic_access,
e139dc4a
LE		 2087 .release_nic_access = iwl_trans_pcie_release_nic_access,
2088 .set_bits_mask = iwl_trans_pcie_set_bits_mask,
4d075007
JB		 2089
2090#ifdef CONFIG_IWLWIFI_DEBUGFS
2091 .dump_data = iwl_trans_pcie_dump_data,
2092#endif
e6bb4c9c 2093};
a42a1844 2094
87ce05a2 2095struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
035f7ff2
EG		 2096 const struct pci_device_id *ent,
2097 const struct iwl_cfg *cfg)
a42a1844 2098{
a42a1844
EG		 2099 struct iwl_trans_pcie *trans_pcie;
2100 struct iwl_trans *trans;
2101 u16 pci_cmd;
2102 int err;
2103
2104 trans = kzalloc(sizeof(struct iwl_trans) +
20d3b647 2105 sizeof(struct iwl_trans_pcie), GFP_KERNEL);
6965a354
LC		 2106 if (!trans) {
2107 err = -ENOMEM;
2108 goto out;
2109 }
a42a1844
EG		 2110
2111 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2112
2113 trans->ops = &trans_ops_pcie;
035f7ff2 2114 trans->cfg = cfg;
2bfb5092 2115 trans_lockdep_init(trans);
a42a1844 2116 trans_pcie->trans = trans;
7b11488f 2117 spin_lock_init(&trans_pcie->irq_lock);
e56b04ef 2118 spin_lock_init(&trans_pcie->reg_lock);
13df1aab 2119 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
a42a1844 2120
d819c6cf
JB		 2121 err = pci_enable_device(pdev);
2122 if (err)
2123 goto out_no_pci;
2124
f2532b04
EG		 2125 if (!cfg->base_params->pcie_l1_allowed) {
2126 /*
2127 * W/A - seems to solve weird behavior. We need to remove this
2128 * if we don't want to stay in L1 all the time. This wastes a
2129 * lot of power.
2130 */
2131 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2132 PCIE_LINK_STATE_L1 |
2133 PCIE_LINK_STATE_CLKPM);
2134 }
a42a1844 2135
a42a1844
EG		 2136 pci_set_master(pdev);
2137
2138 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2139 if (!err)
2140 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2141 if (err) {
2142 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2143 if (!err)
2144 err = pci_set_consistent_dma_mask(pdev,
20d3b647 2145 DMA_BIT_MASK(32));
a42a1844
EG		 2146 /* both attempts failed: */
2147 if (err) {
6a4b09f8 2148 dev_err(&pdev->dev, "No suitable DMA available\n");
a42a1844
EG		 2149 goto out_pci_disable_device;
2150 }
2151 }
2152
2153 err = pci_request_regions(pdev, DRV_NAME);
2154 if (err) {
6a4b09f8 2155 dev_err(&pdev->dev, "pci_request_regions failed\n");
a42a1844
EG		 2156 goto out_pci_disable_device;
2157 }
2158
05f5b97e 2159 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
a42a1844 2160 if (!trans_pcie->hw_base) {
6a4b09f8 2161 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
a42a1844
EG		 2162 err = -ENODEV;
2163 goto out_pci_release_regions;
2164 }
2165
a42a1844
EG		 2166 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2167 * PCI Tx retries from interfering with C3 CPU state */
2168 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2169
83f7a85f
EG		 2170 trans->dev = &pdev->dev;
2171 trans_pcie->pci_dev = pdev;
2172 iwl_disable_interrupts(trans);
2173
a42a1844 2174 err = pci_enable_msi(pdev);
9f904b38 2175 if (err) {
6a4b09f8 2176 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
9f904b38
EG		 2177 /* enable rfkill interrupt: hw bug w/a */
2178 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2179 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2180 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2181 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2182 }
2183 }
a42a1844 2184
08079a49 2185 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
b513ee7f
LK		 2186 /*
2187 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2188 * changed, and now the revision step also includes bit 0-1 (no more
2189 * "dash" value). To keep hw_rev backwards compatible - we'll store it
2190 * in the old format.
2191 */
2192 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
2193 trans->hw_rev = (trans->hw_rev & 0xfff0) |
1fc0e221 2194 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
b513ee7f 2195
99673ee5 2196 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
9ca85961
EG		 2197 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2198 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
a42a1844 2199
69a10b29 2200 /* Initialize the wait queue for commands */
f946b529 2201 init_waitqueue_head(&trans_pcie->wait_command_queue);
69a10b29 2202
3ec45882
JB		 2203 snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
2204 "iwl_cmd_pool:%s", dev_name(trans->dev));
59c647b6
EG		 2205
2206 trans->dev_cmd_headroom = 0;
2207 trans->dev_cmd_pool =
3ec45882 2208 kmem_cache_create(trans->dev_cmd_pool_name,
59c647b6
EG		 2209 sizeof(struct iwl_device_cmd)
2210 + trans->dev_cmd_headroom,
2211 sizeof(void *),
2212 SLAB_HWCACHE_ALIGN,
2213 NULL);
2214
6965a354
LC		 2215 if (!trans->dev_cmd_pool) {
2216 err = -ENOMEM;
59c647b6 2217 goto out_pci_disable_msi;
6965a354 2218 }
59c647b6 2219
a8b691e6
JB		 2220 if (iwl_pcie_alloc_ict(trans))
2221 goto out_free_cmd_pool;
2222
85bf9da1 2223 err = request_threaded_irq(pdev->irq, iwl_pcie_isr,
6965a354
LC		 2224 iwl_pcie_irq_handler,
2225 IRQF_SHARED, DRV_NAME, trans);
2226 if (err) {
a8b691e6
JB		 2227 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2228 goto out_free_ict;
2229 }
2230
83f7a85f
EG		 2231 trans_pcie->inta_mask = CSR_INI_SET_MASK;
2232
a42a1844
EG		 2233 return trans;
2234
a8b691e6
JB		 2235out_free_ict:
2236 iwl_pcie_free_ict(trans);
2237out_free_cmd_pool:
2238 kmem_cache_destroy(trans->dev_cmd_pool);
59c647b6
EG		 2239out_pci_disable_msi:
2240 pci_disable_msi(pdev);
a42a1844
EG		 2241out_pci_release_regions:
2242 pci_release_regions(pdev);
2243out_pci_disable_device:
2244 pci_disable_device(pdev);
2245out_no_pci:
2246 kfree(trans);
6965a354
LC		 2247out:
2248 return ERR_PTR(err);
a42a1844 2249}
Linux kernel - Deliverables
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