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1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
51368bf7 | 3 | * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. |
1053d35f RR |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
1053d35f RR |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
fd4abac5 | 29 | #include <linux/etherdevice.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
253a634c | 31 | #include <linux/sched.h> |
253a634c | 32 | |
522376d2 EG |
33 | #include "iwl-debug.h" |
34 | #include "iwl-csr.h" | |
35 | #include "iwl-prph.h" | |
1053d35f | 36 | #include "iwl-io.h" |
ed277c93 | 37 | #include "iwl-op-mode.h" |
6468a01a | 38 | #include "internal.h" |
6238b008 | 39 | /* FIXME: need to abstract out TX command (once we know what it looks like) */ |
1023fdc4 | 40 | #include "dvm/commands.h" |
1053d35f | 41 | |
522376d2 EG |
42 | #define IWL_TX_CRC_SIZE 4 |
43 | #define IWL_TX_DELIMITER_SIZE 4 | |
44 | ||
f02831be EG |
45 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
46 | * DMA services | |
47 | * | |
48 | * Theory of operation | |
49 | * | |
50 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
51 | * of buffer descriptors, each of which points to one or more data buffers for | |
52 | * the device to read from or fill. Driver and device exchange status of each | |
53 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
54 | * entries in each circular buffer, to protect against confusing empty and full | |
55 | * queue states. | |
56 | * | |
57 | * The device reads or writes the data in the queues via the device's several | |
58 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
59 | * | |
60 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
61 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
62 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
63 | * Tx queue resumed. | |
64 | * | |
65 | ***************************************************/ | |
66 | static int iwl_queue_space(const struct iwl_queue *q) | |
67 | { | |
a9b29246 IY |
68 | unsigned int max; |
69 | unsigned int used; | |
f02831be | 70 | |
a9b29246 IY |
71 | /* |
72 | * To avoid ambiguity between empty and completely full queues, there | |
73 | * should always be less than q->n_bd elements in the queue. | |
74 | * If q->n_window is smaller than q->n_bd, there is no need to reserve | |
75 | * any queue entries for this purpose. | |
76 | */ | |
77 | if (q->n_window < q->n_bd) | |
78 | max = q->n_window; | |
79 | else | |
80 | max = q->n_bd - 1; | |
f02831be | 81 | |
a9b29246 IY |
82 | /* |
83 | * q->n_bd is a power of 2, so the following is equivalent to modulo by | |
84 | * q->n_bd and is well defined for negative dividends. | |
85 | */ | |
86 | used = (q->write_ptr - q->read_ptr) & (q->n_bd - 1); | |
87 | ||
88 | if (WARN_ON(used > max)) | |
89 | return 0; | |
90 | ||
91 | return max - used; | |
f02831be EG |
92 | } |
93 | ||
94 | /* | |
95 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes | |
96 | */ | |
97 | static int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id) | |
98 | { | |
99 | q->n_bd = count; | |
100 | q->n_window = slots_num; | |
101 | q->id = id; | |
102 | ||
103 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap | |
104 | * and iwl_queue_dec_wrap are broken. */ | |
105 | if (WARN_ON(!is_power_of_2(count))) | |
106 | return -EINVAL; | |
107 | ||
108 | /* slots_num must be power-of-two size, otherwise | |
109 | * get_cmd_index is broken. */ | |
110 | if (WARN_ON(!is_power_of_2(slots_num))) | |
111 | return -EINVAL; | |
112 | ||
113 | q->low_mark = q->n_window / 4; | |
114 | if (q->low_mark < 4) | |
115 | q->low_mark = 4; | |
116 | ||
117 | q->high_mark = q->n_window / 8; | |
118 | if (q->high_mark < 2) | |
119 | q->high_mark = 2; | |
120 | ||
121 | q->write_ptr = 0; | |
122 | q->read_ptr = 0; | |
123 | ||
124 | return 0; | |
125 | } | |
126 | ||
f02831be EG |
127 | static int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans, |
128 | struct iwl_dma_ptr *ptr, size_t size) | |
129 | { | |
130 | if (WARN_ON(ptr->addr)) | |
131 | return -EINVAL; | |
132 | ||
133 | ptr->addr = dma_alloc_coherent(trans->dev, size, | |
134 | &ptr->dma, GFP_KERNEL); | |
135 | if (!ptr->addr) | |
136 | return -ENOMEM; | |
137 | ptr->size = size; | |
138 | return 0; | |
139 | } | |
140 | ||
141 | static void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, | |
142 | struct iwl_dma_ptr *ptr) | |
143 | { | |
144 | if (unlikely(!ptr->addr)) | |
145 | return; | |
146 | ||
147 | dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma); | |
148 | memset(ptr, 0, sizeof(*ptr)); | |
149 | } | |
150 | ||
151 | static void iwl_pcie_txq_stuck_timer(unsigned long data) | |
152 | { | |
153 | struct iwl_txq *txq = (void *)data; | |
154 | struct iwl_queue *q = &txq->q; | |
155 | struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; | |
156 | struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie); | |
157 | u32 scd_sram_addr = trans_pcie->scd_base_addr + | |
158 | SCD_TX_STTS_QUEUE_OFFSET(txq->q.id); | |
159 | u8 buf[16]; | |
160 | int i; | |
161 | ||
162 | spin_lock(&txq->lock); | |
163 | /* check if triggered erroneously */ | |
164 | if (txq->q.read_ptr == txq->q.write_ptr) { | |
165 | spin_unlock(&txq->lock); | |
166 | return; | |
167 | } | |
168 | spin_unlock(&txq->lock); | |
169 | ||
170 | IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id, | |
171 | jiffies_to_msecs(trans_pcie->wd_timeout)); | |
172 | IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", | |
173 | txq->q.read_ptr, txq->q.write_ptr); | |
174 | ||
4fd442db | 175 | iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf)); |
f02831be EG |
176 | |
177 | iwl_print_hex_error(trans, buf, sizeof(buf)); | |
178 | ||
179 | for (i = 0; i < FH_TCSR_CHNL_NUM; i++) | |
180 | IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i, | |
181 | iwl_read_direct32(trans, FH_TX_TRB_REG(i))); | |
182 | ||
183 | for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { | |
184 | u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i)); | |
185 | u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; | |
186 | bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); | |
187 | u32 tbl_dw = | |
4fd442db EG |
188 | iwl_trans_read_mem32(trans, |
189 | trans_pcie->scd_base_addr + | |
190 | SCD_TRANS_TBL_OFFSET_QUEUE(i)); | |
f02831be EG |
191 | |
192 | if (i & 0x1) | |
193 | tbl_dw = (tbl_dw & 0xFFFF0000) >> 16; | |
194 | else | |
195 | tbl_dw = tbl_dw & 0x0000FFFF; | |
196 | ||
197 | IWL_ERR(trans, | |
198 | "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n", | |
199 | i, active ? "" : "in", fifo, tbl_dw, | |
200 | iwl_read_prph(trans, | |
201 | SCD_QUEUE_RDPTR(i)) & (txq->q.n_bd - 1), | |
202 | iwl_read_prph(trans, SCD_QUEUE_WRPTR(i))); | |
203 | } | |
204 | ||
205 | for (i = q->read_ptr; i != q->write_ptr; | |
38c0f334 | 206 | i = iwl_queue_inc_wrap(i, q->n_bd)) |
f02831be | 207 | IWL_ERR(trans, "scratch %d = 0x%08x\n", i, |
38c0f334 | 208 | le32_to_cpu(txq->scratchbufs[i].scratch)); |
f02831be | 209 | |
cfadc3ff | 210 | iwl_write_prph(trans, DEVICE_SET_NMI_REG, 1); |
f02831be EG |
211 | } |
212 | ||
990aa6d7 EG |
213 | /* |
214 | * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array | |
48d42c42 | 215 | */ |
f02831be EG |
216 | static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans, |
217 | struct iwl_txq *txq, u16 byte_cnt) | |
48d42c42 | 218 | { |
105183b1 | 219 | struct iwlagn_scd_bc_tbl *scd_bc_tbl; |
20d3b647 | 220 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
48d42c42 EG |
221 | int write_ptr = txq->q.write_ptr; |
222 | int txq_id = txq->q.id; | |
223 | u8 sec_ctl = 0; | |
224 | u8 sta_id = 0; | |
225 | u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; | |
226 | __le16 bc_ent; | |
132f98c2 | 227 | struct iwl_tx_cmd *tx_cmd = |
bf8440e6 | 228 | (void *) txq->entries[txq->q.write_ptr].cmd->payload; |
48d42c42 | 229 | |
105183b1 EG |
230 | scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; |
231 | ||
48d42c42 EG |
232 | WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX); |
233 | ||
132f98c2 EG |
234 | sta_id = tx_cmd->sta_id; |
235 | sec_ctl = tx_cmd->sec_ctl; | |
48d42c42 EG |
236 | |
237 | switch (sec_ctl & TX_CMD_SEC_MSK) { | |
238 | case TX_CMD_SEC_CCM: | |
4325f6ca | 239 | len += IEEE80211_CCMP_MIC_LEN; |
48d42c42 EG |
240 | break; |
241 | case TX_CMD_SEC_TKIP: | |
4325f6ca | 242 | len += IEEE80211_TKIP_ICV_LEN; |
48d42c42 EG |
243 | break; |
244 | case TX_CMD_SEC_WEP: | |
4325f6ca | 245 | len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN; |
48d42c42 EG |
246 | break; |
247 | } | |
248 | ||
046db346 EG |
249 | if (trans_pcie->bc_table_dword) |
250 | len = DIV_ROUND_UP(len, 4); | |
251 | ||
252 | bc_ent = cpu_to_le16(len | (sta_id << 12)); | |
48d42c42 EG |
253 | |
254 | scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; | |
255 | ||
256 | if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
257 | scd_bc_tbl[txq_id]. | |
258 | tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; | |
259 | } | |
260 | ||
f02831be EG |
261 | static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans, |
262 | struct iwl_txq *txq) | |
263 | { | |
264 | struct iwl_trans_pcie *trans_pcie = | |
265 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
266 | struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; | |
267 | int txq_id = txq->q.id; | |
268 | int read_ptr = txq->q.read_ptr; | |
269 | u8 sta_id = 0; | |
270 | __le16 bc_ent; | |
271 | struct iwl_tx_cmd *tx_cmd = | |
272 | (void *)txq->entries[txq->q.read_ptr].cmd->payload; | |
273 | ||
274 | WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); | |
275 | ||
276 | if (txq_id != trans_pcie->cmd_queue) | |
277 | sta_id = tx_cmd->sta_id; | |
278 | ||
279 | bc_ent = cpu_to_le16(1 | (sta_id << 12)); | |
280 | scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; | |
281 | ||
282 | if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
283 | scd_bc_tbl[txq_id]. | |
284 | tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; | |
285 | } | |
286 | ||
990aa6d7 EG |
287 | /* |
288 | * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware | |
fd4abac5 | 289 | */ |
990aa6d7 | 290 | void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_txq *txq) |
fd4abac5 | 291 | { |
23e76d1a | 292 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
fd4abac5 | 293 | u32 reg = 0; |
fd4abac5 TW |
294 | int txq_id = txq->q.id; |
295 | ||
43aa616f | 296 | if (!txq->need_update) |
7bfedc59 | 297 | return; |
fd4abac5 | 298 | |
5045388c EP |
299 | /* |
300 | * explicitly wake up the NIC if: | |
301 | * 1. shadow registers aren't enabled | |
302 | * 2. NIC is woken up for CMD regardless of shadow outside this function | |
303 | * 3. there is a chance that the NIC is asleep | |
304 | */ | |
305 | if (!trans->cfg->base_params->shadow_reg_enable && | |
306 | txq_id != trans_pcie->cmd_queue && | |
307 | test_bit(STATUS_TPOWER_PMI, &trans->status)) { | |
f81c1f48 | 308 | /* |
5045388c EP |
309 | * wake up nic if it's powered down ... |
310 | * uCode will wake up, and interrupt us again, so next | |
311 | * time we'll skip this part. | |
f81c1f48 | 312 | */ |
5045388c EP |
313 | reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); |
314 | ||
315 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
316 | IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n", | |
317 | txq_id, reg); | |
318 | iwl_set_bit(trans, CSR_GP_CNTRL, | |
319 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
320 | return; | |
321 | } | |
f81c1f48 | 322 | } |
5045388c EP |
323 | |
324 | /* | |
325 | * if not in power-save mode, uCode will never sleep when we're | |
326 | * trying to tx (during RFKILL, we're not trying to tx). | |
327 | */ | |
328 | IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->q.write_ptr); | |
329 | iwl_write32(trans, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8)); | |
330 | ||
43aa616f | 331 | txq->need_update = false; |
fd4abac5 | 332 | } |
fd4abac5 | 333 | |
f02831be | 334 | static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
214d14d4 JB |
335 | { |
336 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
337 | ||
338 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
339 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
340 | addr |= | |
341 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
342 | ||
343 | return addr; | |
344 | } | |
345 | ||
f02831be | 346 | static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) |
214d14d4 JB |
347 | { |
348 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
349 | ||
350 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
351 | } | |
352 | ||
f02831be EG |
353 | static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, |
354 | dma_addr_t addr, u16 len) | |
214d14d4 JB |
355 | { |
356 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
357 | u16 hi_n_len = len << 4; | |
358 | ||
359 | put_unaligned_le32(addr, &tb->lo); | |
360 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
361 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
362 | ||
363 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
364 | ||
365 | tfd->num_tbs = idx + 1; | |
366 | } | |
367 | ||
f02831be | 368 | static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_tfd *tfd) |
214d14d4 JB |
369 | { |
370 | return tfd->num_tbs & 0x1f; | |
371 | } | |
372 | ||
f02831be | 373 | static void iwl_pcie_tfd_unmap(struct iwl_trans *trans, |
98891754 JB |
374 | struct iwl_cmd_meta *meta, |
375 | struct iwl_tfd *tfd) | |
214d14d4 | 376 | { |
214d14d4 JB |
377 | int i; |
378 | int num_tbs; | |
379 | ||
214d14d4 | 380 | /* Sanity check on number of chunks */ |
f02831be | 381 | num_tbs = iwl_pcie_tfd_get_num_tbs(tfd); |
214d14d4 JB |
382 | |
383 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
6d8f6eeb | 384 | IWL_ERR(trans, "Too many chunks: %i\n", num_tbs); |
214d14d4 JB |
385 | /* @todo issue fatal error, it is quite serious situation */ |
386 | return; | |
387 | } | |
388 | ||
38c0f334 | 389 | /* first TB is never freed - it's the scratchbuf data */ |
214d14d4 | 390 | |
214d14d4 | 391 | for (i = 1; i < num_tbs; i++) |
f02831be | 392 | dma_unmap_single(trans->dev, iwl_pcie_tfd_tb_get_addr(tfd, i), |
98891754 JB |
393 | iwl_pcie_tfd_tb_get_len(tfd, i), |
394 | DMA_TO_DEVICE); | |
ebed633c EG |
395 | |
396 | tfd->num_tbs = 0; | |
4ce7cc2b JB |
397 | } |
398 | ||
990aa6d7 EG |
399 | /* |
400 | * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
6d8f6eeb | 401 | * @trans - transport private data |
4ce7cc2b | 402 | * @txq - tx queue |
ebed633c | 403 | * @dma_dir - the direction of the DMA mapping |
4ce7cc2b JB |
404 | * |
405 | * Does NOT advance any TFD circular buffer read/write indexes | |
406 | * Does NOT free the TFD itself (which is within circular buffer) | |
407 | */ | |
98891754 | 408 | static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq) |
4ce7cc2b JB |
409 | { |
410 | struct iwl_tfd *tfd_tmp = txq->tfds; | |
4ce7cc2b | 411 | |
ebed633c EG |
412 | /* rd_ptr is bounded by n_bd and idx is bounded by n_window */ |
413 | int rd_ptr = txq->q.read_ptr; | |
414 | int idx = get_cmd_index(&txq->q, rd_ptr); | |
415 | ||
015c15e1 JB |
416 | lockdep_assert_held(&txq->lock); |
417 | ||
ebed633c | 418 | /* We have only q->n_window txq->entries, but we use q->n_bd tfds */ |
98891754 | 419 | iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr]); |
214d14d4 JB |
420 | |
421 | /* free SKB */ | |
bf8440e6 | 422 | if (txq->entries) { |
214d14d4 JB |
423 | struct sk_buff *skb; |
424 | ||
ebed633c | 425 | skb = txq->entries[idx].skb; |
214d14d4 | 426 | |
909e9b23 EG |
427 | /* Can be called from irqs-disabled context |
428 | * If skb is not NULL, it means that the whole queue is being | |
429 | * freed and that the queue is not empty - free the skb | |
430 | */ | |
214d14d4 | 431 | if (skb) { |
ed277c93 | 432 | iwl_op_mode_free_skb(trans->op_mode, skb); |
ebed633c | 433 | txq->entries[idx].skb = NULL; |
214d14d4 JB |
434 | } |
435 | } | |
436 | } | |
437 | ||
f02831be EG |
438 | static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq, |
439 | dma_addr_t addr, u16 len, u8 reset) | |
214d14d4 JB |
440 | { |
441 | struct iwl_queue *q; | |
442 | struct iwl_tfd *tfd, *tfd_tmp; | |
443 | u32 num_tbs; | |
444 | ||
445 | q = &txq->q; | |
4ce7cc2b | 446 | tfd_tmp = txq->tfds; |
214d14d4 JB |
447 | tfd = &tfd_tmp[q->write_ptr]; |
448 | ||
f02831be EG |
449 | if (reset) |
450 | memset(tfd, 0, sizeof(*tfd)); | |
451 | ||
452 | num_tbs = iwl_pcie_tfd_get_num_tbs(tfd); | |
453 | ||
454 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
455 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
456 | IWL_ERR(trans, "Error can not send more than %d chunks\n", | |
457 | IWL_NUM_OF_TBS); | |
458 | return -EINVAL; | |
459 | } | |
460 | ||
1092b9bc EP |
461 | if (WARN(addr & ~IWL_TX_DMA_MASK, |
462 | "Unaligned address = %llx\n", (unsigned long long)addr)) | |
f02831be EG |
463 | return -EINVAL; |
464 | ||
f02831be EG |
465 | iwl_pcie_tfd_set_tb(tfd, num_tbs, addr, len); |
466 | ||
467 | return 0; | |
468 | } | |
469 | ||
470 | static int iwl_pcie_txq_alloc(struct iwl_trans *trans, | |
471 | struct iwl_txq *txq, int slots_num, | |
472 | u32 txq_id) | |
473 | { | |
474 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
475 | size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX; | |
38c0f334 | 476 | size_t scratchbuf_sz; |
f02831be EG |
477 | int i; |
478 | ||
479 | if (WARN_ON(txq->entries || txq->tfds)) | |
480 | return -EINVAL; | |
481 | ||
482 | setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer, | |
483 | (unsigned long)txq); | |
484 | txq->trans_pcie = trans_pcie; | |
485 | ||
486 | txq->q.n_window = slots_num; | |
487 | ||
488 | txq->entries = kcalloc(slots_num, | |
489 | sizeof(struct iwl_pcie_txq_entry), | |
490 | GFP_KERNEL); | |
491 | ||
492 | if (!txq->entries) | |
493 | goto error; | |
494 | ||
495 | if (txq_id == trans_pcie->cmd_queue) | |
496 | for (i = 0; i < slots_num; i++) { | |
497 | txq->entries[i].cmd = | |
498 | kmalloc(sizeof(struct iwl_device_cmd), | |
499 | GFP_KERNEL); | |
500 | if (!txq->entries[i].cmd) | |
501 | goto error; | |
502 | } | |
503 | ||
504 | /* Circular buffer of transmit frame descriptors (TFDs), | |
505 | * shared with device */ | |
506 | txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz, | |
507 | &txq->q.dma_addr, GFP_KERNEL); | |
d0320f75 | 508 | if (!txq->tfds) |
f02831be | 509 | goto error; |
38c0f334 JB |
510 | |
511 | BUILD_BUG_ON(IWL_HCMD_SCRATCHBUF_SIZE != sizeof(*txq->scratchbufs)); | |
512 | BUILD_BUG_ON(offsetof(struct iwl_pcie_txq_scratch_buf, scratch) != | |
513 | sizeof(struct iwl_cmd_header) + | |
514 | offsetof(struct iwl_tx_cmd, scratch)); | |
515 | ||
516 | scratchbuf_sz = sizeof(*txq->scratchbufs) * slots_num; | |
517 | ||
518 | txq->scratchbufs = dma_alloc_coherent(trans->dev, scratchbuf_sz, | |
519 | &txq->scratchbufs_dma, | |
520 | GFP_KERNEL); | |
521 | if (!txq->scratchbufs) | |
522 | goto err_free_tfds; | |
523 | ||
f02831be EG |
524 | txq->q.id = txq_id; |
525 | ||
526 | return 0; | |
38c0f334 JB |
527 | err_free_tfds: |
528 | dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->q.dma_addr); | |
f02831be EG |
529 | error: |
530 | if (txq->entries && txq_id == trans_pcie->cmd_queue) | |
531 | for (i = 0; i < slots_num; i++) | |
532 | kfree(txq->entries[i].cmd); | |
533 | kfree(txq->entries); | |
534 | txq->entries = NULL; | |
535 | ||
536 | return -ENOMEM; | |
537 | ||
538 | } | |
539 | ||
540 | static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq, | |
541 | int slots_num, u32 txq_id) | |
542 | { | |
543 | int ret; | |
544 | ||
43aa616f | 545 | txq->need_update = false; |
f02831be EG |
546 | |
547 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise | |
548 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ | |
549 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); | |
550 | ||
551 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
552 | ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num, | |
553 | txq_id); | |
554 | if (ret) | |
555 | return ret; | |
556 | ||
557 | spin_lock_init(&txq->lock); | |
558 | ||
559 | /* | |
560 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
561 | * given Tx queue, and enable the DMA channel used for that queue. | |
562 | * Circular buffer (TFD queue in DRAM) physical base address */ | |
563 | iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id), | |
564 | txq->q.dma_addr >> 8); | |
565 | ||
566 | return 0; | |
567 | } | |
568 | ||
569 | /* | |
570 | * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's | |
571 | */ | |
572 | static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id) | |
573 | { | |
574 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
575 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
576 | struct iwl_queue *q = &txq->q; | |
f02831be EG |
577 | |
578 | if (!q->n_bd) | |
579 | return; | |
580 | ||
f02831be EG |
581 | spin_lock_bh(&txq->lock); |
582 | while (q->write_ptr != q->read_ptr) { | |
b967613d EG |
583 | IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n", |
584 | txq_id, q->read_ptr); | |
98891754 | 585 | iwl_pcie_txq_free_tfd(trans, txq); |
f02831be EG |
586 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd); |
587 | } | |
b967613d | 588 | txq->active = false; |
f02831be | 589 | spin_unlock_bh(&txq->lock); |
8a487b1a EG |
590 | |
591 | /* just in case - this queue may have been stopped */ | |
592 | iwl_wake_queue(trans, txq); | |
f02831be EG |
593 | } |
594 | ||
595 | /* | |
596 | * iwl_pcie_txq_free - Deallocate DMA queue. | |
597 | * @txq: Transmit queue to deallocate. | |
598 | * | |
599 | * Empty queue by removing and destroying all BD's. | |
600 | * Free all buffers. | |
601 | * 0-fill, but do not free "txq" descriptor structure. | |
602 | */ | |
603 | static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id) | |
604 | { | |
605 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
606 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
607 | struct device *dev = trans->dev; | |
608 | int i; | |
609 | ||
610 | if (WARN_ON(!txq)) | |
611 | return; | |
612 | ||
613 | iwl_pcie_txq_unmap(trans, txq_id); | |
614 | ||
615 | /* De-alloc array of command/tx buffers */ | |
616 | if (txq_id == trans_pcie->cmd_queue) | |
617 | for (i = 0; i < txq->q.n_window; i++) { | |
618 | kfree(txq->entries[i].cmd); | |
f02831be EG |
619 | kfree(txq->entries[i].free_buf); |
620 | } | |
621 | ||
622 | /* De-alloc circular buffer of TFDs */ | |
623 | if (txq->q.n_bd) { | |
624 | dma_free_coherent(dev, sizeof(struct iwl_tfd) * | |
625 | txq->q.n_bd, txq->tfds, txq->q.dma_addr); | |
d21fa2da | 626 | txq->q.dma_addr = 0; |
38c0f334 JB |
627 | |
628 | dma_free_coherent(dev, | |
629 | sizeof(*txq->scratchbufs) * txq->q.n_window, | |
630 | txq->scratchbufs, txq->scratchbufs_dma); | |
f02831be EG |
631 | } |
632 | ||
633 | kfree(txq->entries); | |
634 | txq->entries = NULL; | |
635 | ||
636 | del_timer_sync(&txq->stuck_timer); | |
637 | ||
638 | /* 0-fill queue descriptor structure */ | |
639 | memset(txq, 0, sizeof(*txq)); | |
640 | } | |
641 | ||
642 | /* | |
643 | * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask | |
644 | */ | |
645 | static void iwl_pcie_txq_set_sched(struct iwl_trans *trans, u32 mask) | |
646 | { | |
647 | struct iwl_trans_pcie __maybe_unused *trans_pcie = | |
648 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
649 | ||
650 | iwl_write_prph(trans, SCD_TXFACT, mask); | |
651 | } | |
652 | ||
653 | void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr) | |
654 | { | |
655 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
22dc3c95 | 656 | int nq = trans->cfg->base_params->num_of_queues; |
f02831be EG |
657 | int chan; |
658 | u32 reg_val; | |
22dc3c95 JB |
659 | int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) - |
660 | SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32); | |
f02831be EG |
661 | |
662 | /* make sure all queue are not stopped/used */ | |
663 | memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); | |
664 | memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); | |
665 | ||
666 | trans_pcie->scd_base_addr = | |
667 | iwl_read_prph(trans, SCD_SRAM_BASE_ADDR); | |
668 | ||
669 | WARN_ON(scd_base_addr != 0 && | |
670 | scd_base_addr != trans_pcie->scd_base_addr); | |
671 | ||
22dc3c95 JB |
672 | /* reset context data, TX status and translation data */ |
673 | iwl_trans_write_mem(trans, trans_pcie->scd_base_addr + | |
674 | SCD_CONTEXT_MEM_LOWER_BOUND, | |
675 | NULL, clear_dwords); | |
f02831be EG |
676 | |
677 | iwl_write_prph(trans, SCD_DRAM_BASE_ADDR, | |
678 | trans_pcie->scd_bc_tbls.dma >> 10); | |
679 | ||
680 | /* The chain extension of the SCD doesn't work well. This feature is | |
681 | * enabled by default by the HW, so we need to disable it manually. | |
682 | */ | |
683 | iwl_write_prph(trans, SCD_CHAINEXT_EN, 0); | |
684 | ||
685 | iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue, | |
686 | trans_pcie->cmd_fifo); | |
687 | ||
688 | /* Activate all Tx DMA/FIFO channels */ | |
689 | iwl_pcie_txq_set_sched(trans, IWL_MASK(0, 7)); | |
690 | ||
691 | /* Enable DMA channel */ | |
692 | for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++) | |
693 | iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan), | |
694 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
695 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); | |
696 | ||
697 | /* Update FH chicken bits */ | |
698 | reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG); | |
699 | iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG, | |
700 | reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); | |
701 | ||
702 | /* Enable L1-Active */ | |
3073d8c0 EH |
703 | if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) |
704 | iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
705 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
f02831be EG |
706 | } |
707 | ||
ddaf5a5b JB |
708 | void iwl_trans_pcie_tx_reset(struct iwl_trans *trans) |
709 | { | |
710 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
711 | int txq_id; | |
712 | ||
713 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
714 | txq_id++) { | |
715 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
716 | ||
717 | iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id), | |
718 | txq->q.dma_addr >> 8); | |
719 | iwl_pcie_txq_unmap(trans, txq_id); | |
720 | txq->q.read_ptr = 0; | |
721 | txq->q.write_ptr = 0; | |
722 | } | |
723 | ||
724 | /* Tell NIC where to find the "keep warm" buffer */ | |
725 | iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, | |
726 | trans_pcie->kw.dma >> 4); | |
727 | ||
728 | iwl_pcie_tx_start(trans, trans_pcie->scd_base_addr); | |
729 | } | |
730 | ||
f02831be EG |
731 | /* |
732 | * iwl_pcie_tx_stop - Stop all Tx DMA channels | |
733 | */ | |
734 | int iwl_pcie_tx_stop(struct iwl_trans *trans) | |
735 | { | |
736 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
737 | int ch, txq_id, ret; | |
f02831be EG |
738 | |
739 | /* Turn off all Tx DMA fifos */ | |
7b70bd63 | 740 | spin_lock(&trans_pcie->irq_lock); |
f02831be EG |
741 | |
742 | iwl_pcie_txq_set_sched(trans, 0); | |
743 | ||
744 | /* Stop each Tx DMA channel, and wait for it to be idle */ | |
745 | for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { | |
746 | iwl_write_direct32(trans, | |
747 | FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); | |
748 | ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG, | |
749 | FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000); | |
750 | if (ret < 0) | |
751 | IWL_ERR(trans, | |
752 | "Failing on timeout while stopping DMA channel %d [0x%08x]\n", | |
753 | ch, | |
754 | iwl_read_direct32(trans, | |
755 | FH_TSSR_TX_STATUS_REG)); | |
756 | } | |
7b70bd63 | 757 | spin_unlock(&trans_pcie->irq_lock); |
f02831be | 758 | |
fba1c627 EG |
759 | /* |
760 | * This function can be called before the op_mode disabled the | |
761 | * queues. This happens when we have an rfkill interrupt. | |
762 | * Since we stop Tx altogether - mark the queues as stopped. | |
763 | */ | |
764 | memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); | |
765 | memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); | |
766 | ||
767 | /* This can happen: start_hw, stop_device */ | |
768 | if (!trans_pcie->txq) | |
f02831be | 769 | return 0; |
f02831be EG |
770 | |
771 | /* Unmap DMA from host system and free skb's */ | |
772 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
773 | txq_id++) | |
774 | iwl_pcie_txq_unmap(trans, txq_id); | |
775 | ||
776 | return 0; | |
777 | } | |
778 | ||
779 | /* | |
780 | * iwl_trans_tx_free - Free TXQ Context | |
781 | * | |
782 | * Destroy all TX DMA queues and structures | |
783 | */ | |
784 | void iwl_pcie_tx_free(struct iwl_trans *trans) | |
785 | { | |
786 | int txq_id; | |
787 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
788 | ||
789 | /* Tx queues */ | |
790 | if (trans_pcie->txq) { | |
791 | for (txq_id = 0; | |
792 | txq_id < trans->cfg->base_params->num_of_queues; txq_id++) | |
793 | iwl_pcie_txq_free(trans, txq_id); | |
794 | } | |
795 | ||
796 | kfree(trans_pcie->txq); | |
797 | trans_pcie->txq = NULL; | |
798 | ||
799 | iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw); | |
800 | ||
801 | iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls); | |
802 | } | |
803 | ||
804 | /* | |
805 | * iwl_pcie_tx_alloc - allocate TX context | |
806 | * Allocate all Tx DMA structures and initialize them | |
807 | */ | |
808 | static int iwl_pcie_tx_alloc(struct iwl_trans *trans) | |
809 | { | |
810 | int ret; | |
811 | int txq_id, slots_num; | |
812 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
813 | ||
814 | u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues * | |
815 | sizeof(struct iwlagn_scd_bc_tbl); | |
816 | ||
817 | /*It is not allowed to alloc twice, so warn when this happens. | |
818 | * We cannot rely on the previous allocation, so free and fail */ | |
819 | if (WARN_ON(trans_pcie->txq)) { | |
820 | ret = -EINVAL; | |
821 | goto error; | |
822 | } | |
823 | ||
824 | ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls, | |
825 | scd_bc_tbls_size); | |
826 | if (ret) { | |
827 | IWL_ERR(trans, "Scheduler BC Table allocation failed\n"); | |
828 | goto error; | |
829 | } | |
830 | ||
831 | /* Alloc keep-warm buffer */ | |
832 | ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE); | |
833 | if (ret) { | |
834 | IWL_ERR(trans, "Keep Warm allocation failed\n"); | |
835 | goto error; | |
836 | } | |
837 | ||
838 | trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues, | |
839 | sizeof(struct iwl_txq), GFP_KERNEL); | |
840 | if (!trans_pcie->txq) { | |
841 | IWL_ERR(trans, "Not enough memory for txq\n"); | |
2ab9ba0f | 842 | ret = -ENOMEM; |
f02831be EG |
843 | goto error; |
844 | } | |
845 | ||
846 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
847 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
848 | txq_id++) { | |
849 | slots_num = (txq_id == trans_pcie->cmd_queue) ? | |
850 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
851 | ret = iwl_pcie_txq_alloc(trans, &trans_pcie->txq[txq_id], | |
852 | slots_num, txq_id); | |
853 | if (ret) { | |
854 | IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id); | |
855 | goto error; | |
856 | } | |
857 | } | |
858 | ||
859 | return 0; | |
860 | ||
861 | error: | |
862 | iwl_pcie_tx_free(trans); | |
863 | ||
864 | return ret; | |
865 | } | |
866 | int iwl_pcie_tx_init(struct iwl_trans *trans) | |
867 | { | |
868 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
869 | int ret; | |
870 | int txq_id, slots_num; | |
f02831be EG |
871 | bool alloc = false; |
872 | ||
873 | if (!trans_pcie->txq) { | |
874 | ret = iwl_pcie_tx_alloc(trans); | |
875 | if (ret) | |
876 | goto error; | |
877 | alloc = true; | |
878 | } | |
879 | ||
7b70bd63 | 880 | spin_lock(&trans_pcie->irq_lock); |
f02831be EG |
881 | |
882 | /* Turn off all Tx DMA fifos */ | |
883 | iwl_write_prph(trans, SCD_TXFACT, 0); | |
884 | ||
885 | /* Tell NIC where to find the "keep warm" buffer */ | |
886 | iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, | |
887 | trans_pcie->kw.dma >> 4); | |
888 | ||
7b70bd63 | 889 | spin_unlock(&trans_pcie->irq_lock); |
f02831be EG |
890 | |
891 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
892 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
893 | txq_id++) { | |
894 | slots_num = (txq_id == trans_pcie->cmd_queue) ? | |
895 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
896 | ret = iwl_pcie_txq_init(trans, &trans_pcie->txq[txq_id], | |
897 | slots_num, txq_id); | |
898 | if (ret) { | |
899 | IWL_ERR(trans, "Tx %d queue init failed\n", txq_id); | |
900 | goto error; | |
901 | } | |
902 | } | |
903 | ||
904 | return 0; | |
905 | error: | |
906 | /*Upon error, free only if we allocated something */ | |
907 | if (alloc) | |
908 | iwl_pcie_tx_free(trans); | |
909 | return ret; | |
910 | } | |
911 | ||
912 | static inline void iwl_pcie_txq_progress(struct iwl_trans_pcie *trans_pcie, | |
913 | struct iwl_txq *txq) | |
914 | { | |
915 | if (!trans_pcie->wd_timeout) | |
916 | return; | |
917 | ||
918 | /* | |
919 | * if empty delete timer, otherwise move timer forward | |
920 | * since we're making progress on this queue | |
921 | */ | |
922 | if (txq->q.read_ptr == txq->q.write_ptr) | |
923 | del_timer(&txq->stuck_timer); | |
924 | else | |
925 | mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout); | |
926 | } | |
927 | ||
928 | /* Frees buffers until index _not_ inclusive */ | |
f6d497cd EG |
929 | void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, |
930 | struct sk_buff_head *skbs) | |
f02831be EG |
931 | { |
932 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
933 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
f6d497cd EG |
934 | /* n_bd is usually 256 => n_bd - 1 = 0xff */ |
935 | int tfd_num = ssn & (txq->q.n_bd - 1); | |
f02831be EG |
936 | struct iwl_queue *q = &txq->q; |
937 | int last_to_free; | |
f02831be EG |
938 | |
939 | /* This function is not meant to release cmd queue*/ | |
940 | if (WARN_ON(txq_id == trans_pcie->cmd_queue)) | |
f6d497cd | 941 | return; |
214d14d4 | 942 | |
2bfb5092 | 943 | spin_lock_bh(&txq->lock); |
f6d497cd | 944 | |
b967613d EG |
945 | if (!txq->active) { |
946 | IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n", | |
947 | txq_id, ssn); | |
948 | goto out; | |
949 | } | |
950 | ||
f6d497cd EG |
951 | if (txq->q.read_ptr == tfd_num) |
952 | goto out; | |
953 | ||
954 | IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n", | |
955 | txq_id, txq->q.read_ptr, tfd_num, ssn); | |
214d14d4 | 956 | |
f02831be EG |
957 | /*Since we free until index _not_ inclusive, the one before index is |
958 | * the last we will free. This one must be used */ | |
f6d497cd | 959 | last_to_free = iwl_queue_dec_wrap(tfd_num, q->n_bd); |
f02831be | 960 | |
6ca6ebc1 | 961 | if (!iwl_queue_used(q, last_to_free)) { |
f02831be EG |
962 | IWL_ERR(trans, |
963 | "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n", | |
964 | __func__, txq_id, last_to_free, q->n_bd, | |
965 | q->write_ptr, q->read_ptr); | |
f6d497cd | 966 | goto out; |
214d14d4 JB |
967 | } |
968 | ||
f02831be | 969 | if (WARN_ON(!skb_queue_empty(skbs))) |
f6d497cd | 970 | goto out; |
214d14d4 | 971 | |
f02831be | 972 | for (; |
f6d497cd | 973 | q->read_ptr != tfd_num; |
f02831be | 974 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { |
214d14d4 | 975 | |
f02831be EG |
976 | if (WARN_ON_ONCE(txq->entries[txq->q.read_ptr].skb == NULL)) |
977 | continue; | |
214d14d4 | 978 | |
f02831be | 979 | __skb_queue_tail(skbs, txq->entries[txq->q.read_ptr].skb); |
214d14d4 | 980 | |
f02831be | 981 | txq->entries[txq->q.read_ptr].skb = NULL; |
fd4abac5 | 982 | |
f02831be | 983 | iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq); |
fd4abac5 | 984 | |
98891754 | 985 | iwl_pcie_txq_free_tfd(trans, txq); |
f02831be | 986 | } |
fd4abac5 | 987 | |
f02831be EG |
988 | iwl_pcie_txq_progress(trans_pcie, txq); |
989 | ||
f6d497cd EG |
990 | if (iwl_queue_space(&txq->q) > txq->q.low_mark) |
991 | iwl_wake_queue(trans, txq); | |
992 | out: | |
2bfb5092 | 993 | spin_unlock_bh(&txq->lock); |
1053d35f RR |
994 | } |
995 | ||
f02831be EG |
996 | /* |
997 | * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd | |
998 | * | |
999 | * When FW advances 'R' index, all entries between old and new 'R' index | |
1000 | * need to be reclaimed. As result, some free space forms. If there is | |
1001 | * enough free space (> low mark), wake the stack that feeds us. | |
1002 | */ | |
1003 | static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx) | |
48d42c42 | 1004 | { |
f02831be EG |
1005 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1006 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
1007 | struct iwl_queue *q = &txq->q; | |
b9439491 | 1008 | unsigned long flags; |
f02831be | 1009 | int nfreed = 0; |
48d42c42 | 1010 | |
f02831be | 1011 | lockdep_assert_held(&txq->lock); |
48d42c42 | 1012 | |
6ca6ebc1 | 1013 | if ((idx >= q->n_bd) || (!iwl_queue_used(q, idx))) { |
f02831be EG |
1014 | IWL_ERR(trans, |
1015 | "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n", | |
1016 | __func__, txq_id, idx, q->n_bd, | |
1017 | q->write_ptr, q->read_ptr); | |
1018 | return; | |
1019 | } | |
48d42c42 | 1020 | |
f02831be EG |
1021 | for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; |
1022 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
48d42c42 | 1023 | |
f02831be EG |
1024 | if (nfreed++ > 0) { |
1025 | IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", | |
1026 | idx, q->write_ptr, q->read_ptr); | |
cfadc3ff | 1027 | iwl_write_prph(trans, DEVICE_SET_NMI_REG, 1); |
f02831be EG |
1028 | } |
1029 | } | |
1030 | ||
e7f76340 EG |
1031 | if (trans->cfg->base_params->apmg_wake_up_wa && |
1032 | q->read_ptr == q->write_ptr) { | |
b9439491 EG |
1033 | spin_lock_irqsave(&trans_pcie->reg_lock, flags); |
1034 | WARN_ON(!trans_pcie->cmd_in_flight); | |
1035 | trans_pcie->cmd_in_flight = false; | |
1036 | __iwl_trans_pcie_clear_bit(trans, | |
1037 | CSR_GP_CNTRL, | |
1038 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
1039 | spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); | |
1040 | } | |
1041 | ||
f02831be | 1042 | iwl_pcie_txq_progress(trans_pcie, txq); |
48d42c42 EG |
1043 | } |
1044 | ||
f02831be | 1045 | static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid, |
1ce8658c | 1046 | u16 txq_id) |
48d42c42 | 1047 | { |
20d3b647 | 1048 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
48d42c42 EG |
1049 | u32 tbl_dw_addr; |
1050 | u32 tbl_dw; | |
1051 | u16 scd_q2ratid; | |
1052 | ||
1053 | scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; | |
1054 | ||
105183b1 | 1055 | tbl_dw_addr = trans_pcie->scd_base_addr + |
48d42c42 EG |
1056 | SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); |
1057 | ||
4fd442db | 1058 | tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr); |
48d42c42 EG |
1059 | |
1060 | if (txq_id & 0x1) | |
1061 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); | |
1062 | else | |
1063 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); | |
1064 | ||
4fd442db | 1065 | iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw); |
48d42c42 EG |
1066 | |
1067 | return 0; | |
1068 | } | |
1069 | ||
f02831be EG |
1070 | static inline void iwl_pcie_txq_set_inactive(struct iwl_trans *trans, |
1071 | u16 txq_id) | |
48d42c42 EG |
1072 | { |
1073 | /* Simply stop the queue, but don't change any configuration; | |
1074 | * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ | |
1042db2a | 1075 | iwl_write_prph(trans, |
48d42c42 EG |
1076 | SCD_QUEUE_STATUS_BITS(txq_id), |
1077 | (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)| | |
1078 | (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); | |
1079 | } | |
1080 | ||
bd5f6a34 EG |
1081 | /* Receiver address (actually, Rx station's index into station table), |
1082 | * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */ | |
1083 | #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid)) | |
1084 | ||
f02831be EG |
1085 | void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, int fifo, |
1086 | int sta_id, int tid, int frame_limit, u16 ssn) | |
48d42c42 | 1087 | { |
9eae88fa | 1088 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
4beaf6c2 | 1089 | |
9eae88fa JB |
1090 | if (test_and_set_bit(txq_id, trans_pcie->queue_used)) |
1091 | WARN_ONCE(1, "queue %d already used - expect issues", txq_id); | |
48d42c42 | 1092 | |
48d42c42 | 1093 | /* Stop this Tx queue before configuring it */ |
f02831be | 1094 | iwl_pcie_txq_set_inactive(trans, txq_id); |
48d42c42 | 1095 | |
4beaf6c2 EG |
1096 | /* Set this queue as a chain-building queue unless it is CMD queue */ |
1097 | if (txq_id != trans_pcie->cmd_queue) | |
1098 | iwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, BIT(txq_id)); | |
1099 | ||
1100 | /* If this queue is mapped to a certain station: it is an AGG queue */ | |
881acd89 | 1101 | if (sta_id >= 0) { |
4beaf6c2 | 1102 | u16 ra_tid = BUILD_RAxTID(sta_id, tid); |
48d42c42 | 1103 | |
4beaf6c2 | 1104 | /* Map receiver-address / traffic-ID to this queue */ |
f02831be | 1105 | iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id); |
48d42c42 | 1106 | |
4beaf6c2 EG |
1107 | /* enable aggregations for the queue */ |
1108 | iwl_set_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id)); | |
68972c46 | 1109 | trans_pcie->txq[txq_id].ampdu = true; |
1ce8658c EG |
1110 | } else { |
1111 | /* | |
1112 | * disable aggregations for the queue, this will also make the | |
1113 | * ra_tid mapping configuration irrelevant since it is now a | |
1114 | * non-AGG queue. | |
1115 | */ | |
1116 | iwl_clear_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id)); | |
f4772520 EG |
1117 | |
1118 | ssn = trans_pcie->txq[txq_id].q.read_ptr; | |
4beaf6c2 | 1119 | } |
48d42c42 EG |
1120 | |
1121 | /* Place first TFD at index corresponding to start sequence number. | |
1122 | * Assumes that ssn_idx is valid (!= 0xFFF) */ | |
822e8b2a EG |
1123 | trans_pcie->txq[txq_id].q.read_ptr = (ssn & 0xff); |
1124 | trans_pcie->txq[txq_id].q.write_ptr = (ssn & 0xff); | |
1ce8658c EG |
1125 | |
1126 | iwl_write_direct32(trans, HBUS_TARG_WRPTR, | |
1127 | (ssn & 0xff) | (txq_id << 8)); | |
1128 | iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn); | |
48d42c42 EG |
1129 | |
1130 | /* Set up Tx window size and frame limit for this queue */ | |
4fd442db | 1131 | iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr + |
4beaf6c2 | 1132 | SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0); |
4fd442db | 1133 | iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr + |
9eae88fa JB |
1134 | SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), |
1135 | ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
1136 | SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
1137 | ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
1138 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
48d42c42 | 1139 | |
48d42c42 | 1140 | /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ |
1ce8658c EG |
1141 | iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id), |
1142 | (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) | | |
1143 | (fifo << SCD_QUEUE_STTS_REG_POS_TXF) | | |
1144 | (1 << SCD_QUEUE_STTS_REG_POS_WSL) | | |
1145 | SCD_QUEUE_STTS_REG_MSK); | |
b967613d | 1146 | trans_pcie->txq[txq_id].active = true; |
1ce8658c EG |
1147 | IWL_DEBUG_TX_QUEUES(trans, "Activate queue %d on FIFO %d WrPtr: %d\n", |
1148 | txq_id, fifo, ssn & 0xff); | |
4beaf6c2 EG |
1149 | } |
1150 | ||
f02831be | 1151 | void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id) |
288712a6 | 1152 | { |
8ad71bef | 1153 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
986ea6c9 EG |
1154 | u32 stts_addr = trans_pcie->scd_base_addr + |
1155 | SCD_TX_STTS_QUEUE_OFFSET(txq_id); | |
1156 | static const u32 zero_val[4] = {}; | |
288712a6 | 1157 | |
fba1c627 EG |
1158 | /* |
1159 | * Upon HW Rfkill - we stop the device, and then stop the queues | |
1160 | * in the op_mode. Just for the sake of the simplicity of the op_mode, | |
1161 | * allow the op_mode to call txq_disable after it already called | |
1162 | * stop_device. | |
1163 | */ | |
9eae88fa | 1164 | if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) { |
fba1c627 EG |
1165 | WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status), |
1166 | "queue %d not used", txq_id); | |
9eae88fa | 1167 | return; |
48d42c42 EG |
1168 | } |
1169 | ||
f02831be | 1170 | iwl_pcie_txq_set_inactive(trans, txq_id); |
ac928f8d | 1171 | |
4fd442db EG |
1172 | iwl_trans_write_mem(trans, stts_addr, (void *)zero_val, |
1173 | ARRAY_SIZE(zero_val)); | |
986ea6c9 | 1174 | |
990aa6d7 | 1175 | iwl_pcie_txq_unmap(trans, txq_id); |
68972c46 | 1176 | trans_pcie->txq[txq_id].ampdu = false; |
6c3fd3f0 | 1177 | |
1ce8658c | 1178 | IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id); |
48d42c42 EG |
1179 | } |
1180 | ||
fd4abac5 TW |
1181 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ |
1182 | ||
990aa6d7 | 1183 | /* |
f02831be | 1184 | * iwl_pcie_enqueue_hcmd - enqueue a uCode command |
fd4abac5 | 1185 | * @priv: device private data point |
e89044d7 | 1186 | * @cmd: a pointer to the ucode command structure |
fd4abac5 | 1187 | * |
e89044d7 EP |
1188 | * The function returns < 0 values to indicate the operation |
1189 | * failed. On success, it returns the index (>= 0) of command in the | |
fd4abac5 TW |
1190 | * command queue. |
1191 | */ | |
f02831be EG |
1192 | static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans, |
1193 | struct iwl_host_cmd *cmd) | |
fd4abac5 | 1194 | { |
8ad71bef | 1195 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1196 | struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
fd4abac5 | 1197 | struct iwl_queue *q = &txq->q; |
c2acea8e JB |
1198 | struct iwl_device_cmd *out_cmd; |
1199 | struct iwl_cmd_meta *out_meta; | |
b9439491 | 1200 | unsigned long flags; |
f4feb8ac | 1201 | void *dup_buf = NULL; |
fd4abac5 | 1202 | dma_addr_t phys_addr; |
f4feb8ac | 1203 | int idx; |
38c0f334 | 1204 | u16 copy_size, cmd_size, scratch_size; |
4ce7cc2b | 1205 | bool had_nocopy = false; |
b9439491 | 1206 | int i, ret; |
96791422 | 1207 | u32 cmd_pos; |
1afbfb60 JB |
1208 | const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD]; |
1209 | u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD]; | |
fd4abac5 | 1210 | |
4ce7cc2b JB |
1211 | copy_size = sizeof(out_cmd->hdr); |
1212 | cmd_size = sizeof(out_cmd->hdr); | |
1213 | ||
1214 | /* need one for the header if the first is NOCOPY */ | |
1afbfb60 | 1215 | BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1); |
4ce7cc2b | 1216 | |
1afbfb60 | 1217 | for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { |
8a964f44 JB |
1218 | cmddata[i] = cmd->data[i]; |
1219 | cmdlen[i] = cmd->len[i]; | |
1220 | ||
4ce7cc2b JB |
1221 | if (!cmd->len[i]) |
1222 | continue; | |
8a964f44 | 1223 | |
38c0f334 JB |
1224 | /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */ |
1225 | if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) { | |
1226 | int copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size; | |
8a964f44 JB |
1227 | |
1228 | if (copy > cmdlen[i]) | |
1229 | copy = cmdlen[i]; | |
1230 | cmdlen[i] -= copy; | |
1231 | cmddata[i] += copy; | |
1232 | copy_size += copy; | |
1233 | } | |
1234 | ||
4ce7cc2b JB |
1235 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { |
1236 | had_nocopy = true; | |
f4feb8ac JB |
1237 | if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) { |
1238 | idx = -EINVAL; | |
1239 | goto free_dup_buf; | |
1240 | } | |
1241 | } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) { | |
1242 | /* | |
1243 | * This is also a chunk that isn't copied | |
1244 | * to the static buffer so set had_nocopy. | |
1245 | */ | |
1246 | had_nocopy = true; | |
1247 | ||
1248 | /* only allowed once */ | |
1249 | if (WARN_ON(dup_buf)) { | |
1250 | idx = -EINVAL; | |
1251 | goto free_dup_buf; | |
1252 | } | |
1253 | ||
8a964f44 | 1254 | dup_buf = kmemdup(cmddata[i], cmdlen[i], |
f4feb8ac JB |
1255 | GFP_ATOMIC); |
1256 | if (!dup_buf) | |
1257 | return -ENOMEM; | |
4ce7cc2b JB |
1258 | } else { |
1259 | /* NOCOPY must not be followed by normal! */ | |
f4feb8ac JB |
1260 | if (WARN_ON(had_nocopy)) { |
1261 | idx = -EINVAL; | |
1262 | goto free_dup_buf; | |
1263 | } | |
8a964f44 | 1264 | copy_size += cmdlen[i]; |
4ce7cc2b JB |
1265 | } |
1266 | cmd_size += cmd->len[i]; | |
1267 | } | |
fd4abac5 | 1268 | |
3e41ace5 JB |
1269 | /* |
1270 | * If any of the command structures end up being larger than | |
4ce7cc2b JB |
1271 | * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically |
1272 | * allocated into separate TFDs, then we will need to | |
1273 | * increase the size of the buffers. | |
3e41ace5 | 1274 | */ |
2a79e45e JB |
1275 | if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE, |
1276 | "Command %s (%#x) is too large (%d bytes)\n", | |
990aa6d7 | 1277 | get_cmd_string(trans_pcie, cmd->id), cmd->id, copy_size)) { |
f4feb8ac JB |
1278 | idx = -EINVAL; |
1279 | goto free_dup_buf; | |
1280 | } | |
fd4abac5 | 1281 | |
015c15e1 | 1282 | spin_lock_bh(&txq->lock); |
3598e177 | 1283 | |
c2acea8e | 1284 | if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { |
015c15e1 | 1285 | spin_unlock_bh(&txq->lock); |
3598e177 | 1286 | |
6d8f6eeb | 1287 | IWL_ERR(trans, "No space in command queue\n"); |
0e781842 | 1288 | iwl_op_mode_cmd_queue_full(trans->op_mode); |
f4feb8ac JB |
1289 | idx = -ENOSPC; |
1290 | goto free_dup_buf; | |
fd4abac5 TW |
1291 | } |
1292 | ||
4ce7cc2b | 1293 | idx = get_cmd_index(q, q->write_ptr); |
bf8440e6 JB |
1294 | out_cmd = txq->entries[idx].cmd; |
1295 | out_meta = &txq->entries[idx].meta; | |
c2acea8e | 1296 | |
8ce73f3a | 1297 | memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ |
c2acea8e JB |
1298 | if (cmd->flags & CMD_WANT_SKB) |
1299 | out_meta->source = cmd; | |
fd4abac5 | 1300 | |
4ce7cc2b | 1301 | /* set up the header */ |
fd4abac5 | 1302 | |
4ce7cc2b | 1303 | out_cmd->hdr.cmd = cmd->id; |
fd4abac5 | 1304 | out_cmd->hdr.flags = 0; |
cefeaa5f | 1305 | out_cmd->hdr.sequence = |
c6f600fc | 1306 | cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | |
cefeaa5f | 1307 | INDEX_TO_SEQ(q->write_ptr)); |
4ce7cc2b JB |
1308 | |
1309 | /* and copy the data that needs to be copied */ | |
96791422 | 1310 | cmd_pos = offsetof(struct iwl_device_cmd, payload); |
8a964f44 | 1311 | copy_size = sizeof(out_cmd->hdr); |
1afbfb60 | 1312 | for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { |
8a964f44 JB |
1313 | int copy = 0; |
1314 | ||
cc904c71 | 1315 | if (!cmd->len[i]) |
4ce7cc2b | 1316 | continue; |
8a964f44 | 1317 | |
38c0f334 JB |
1318 | /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */ |
1319 | if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) { | |
1320 | copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size; | |
8a964f44 JB |
1321 | |
1322 | if (copy > cmd->len[i]) | |
1323 | copy = cmd->len[i]; | |
1324 | } | |
1325 | ||
1326 | /* copy everything if not nocopy/dup */ | |
1327 | if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | | |
1328 | IWL_HCMD_DFL_DUP))) | |
1329 | copy = cmd->len[i]; | |
1330 | ||
1331 | if (copy) { | |
1332 | memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); | |
1333 | cmd_pos += copy; | |
1334 | copy_size += copy; | |
1335 | } | |
96791422 EG |
1336 | } |
1337 | ||
d9fb6465 | 1338 | IWL_DEBUG_HC(trans, |
20d3b647 | 1339 | "Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n", |
990aa6d7 | 1340 | get_cmd_string(trans_pcie, out_cmd->hdr.cmd), |
20d3b647 JB |
1341 | out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence), |
1342 | cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue); | |
4ce7cc2b | 1343 | |
38c0f334 JB |
1344 | /* start the TFD with the scratchbuf */ |
1345 | scratch_size = min_t(int, copy_size, IWL_HCMD_SCRATCHBUF_SIZE); | |
1346 | memcpy(&txq->scratchbufs[q->write_ptr], &out_cmd->hdr, scratch_size); | |
1347 | iwl_pcie_txq_build_tfd(trans, txq, | |
1348 | iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr), | |
1349 | scratch_size, 1); | |
1350 | ||
1351 | /* map first command fragment, if any remains */ | |
1352 | if (copy_size > scratch_size) { | |
1353 | phys_addr = dma_map_single(trans->dev, | |
1354 | ((u8 *)&out_cmd->hdr) + scratch_size, | |
1355 | copy_size - scratch_size, | |
1356 | DMA_TO_DEVICE); | |
1357 | if (dma_mapping_error(trans->dev, phys_addr)) { | |
1358 | iwl_pcie_tfd_unmap(trans, out_meta, | |
1359 | &txq->tfds[q->write_ptr]); | |
1360 | idx = -ENOMEM; | |
1361 | goto out; | |
1362 | } | |
8a964f44 | 1363 | |
38c0f334 JB |
1364 | iwl_pcie_txq_build_tfd(trans, txq, phys_addr, |
1365 | copy_size - scratch_size, 0); | |
2c46f72e JB |
1366 | } |
1367 | ||
8a964f44 | 1368 | /* map the remaining (adjusted) nocopy/dup fragments */ |
1afbfb60 | 1369 | for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { |
8a964f44 | 1370 | const void *data = cmddata[i]; |
f4feb8ac | 1371 | |
8a964f44 | 1372 | if (!cmdlen[i]) |
4ce7cc2b | 1373 | continue; |
f4feb8ac JB |
1374 | if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | |
1375 | IWL_HCMD_DFL_DUP))) | |
4ce7cc2b | 1376 | continue; |
f4feb8ac JB |
1377 | if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) |
1378 | data = dup_buf; | |
1379 | phys_addr = dma_map_single(trans->dev, (void *)data, | |
98891754 | 1380 | cmdlen[i], DMA_TO_DEVICE); |
1042db2a | 1381 | if (dma_mapping_error(trans->dev, phys_addr)) { |
f02831be | 1382 | iwl_pcie_tfd_unmap(trans, out_meta, |
98891754 | 1383 | &txq->tfds[q->write_ptr]); |
4ce7cc2b JB |
1384 | idx = -ENOMEM; |
1385 | goto out; | |
1386 | } | |
1387 | ||
8a964f44 | 1388 | iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], 0); |
4ce7cc2b | 1389 | } |
df833b1d | 1390 | |
afaf6b57 | 1391 | out_meta->flags = cmd->flags; |
f4feb8ac JB |
1392 | if (WARN_ON_ONCE(txq->entries[idx].free_buf)) |
1393 | kfree(txq->entries[idx].free_buf); | |
1394 | txq->entries[idx].free_buf = dup_buf; | |
2c46f72e | 1395 | |
43aa616f | 1396 | txq->need_update = true; |
2c46f72e | 1397 | |
8a964f44 | 1398 | trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr); |
df833b1d | 1399 | |
7c5ba4a8 JB |
1400 | /* start timer if queue currently empty */ |
1401 | if (q->read_ptr == q->write_ptr && trans_pcie->wd_timeout) | |
1402 | mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout); | |
1403 | ||
b9439491 EG |
1404 | spin_lock_irqsave(&trans_pcie->reg_lock, flags); |
1405 | ||
1406 | /* | |
1407 | * wake up the NIC to make sure that the firmware will see the host | |
1408 | * command - we will let the NIC sleep once all the host commands | |
e7f76340 EG |
1409 | * returned. This needs to be done only on NICs that have |
1410 | * apmg_wake_up_wa set. | |
b9439491 | 1411 | */ |
e7f76340 EG |
1412 | if (trans->cfg->base_params->apmg_wake_up_wa && |
1413 | !trans_pcie->cmd_in_flight) { | |
b9439491 EG |
1414 | trans_pcie->cmd_in_flight = true; |
1415 | __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, | |
1416 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
1417 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
1418 | CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, | |
1419 | (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | | |
1420 | CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), | |
1421 | 15000); | |
1422 | if (ret < 0) { | |
1423 | __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, | |
1424 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
1425 | spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); | |
1426 | trans_pcie->cmd_in_flight = false; | |
1427 | idx = -EIO; | |
1428 | goto out; | |
1429 | } | |
1430 | } | |
1431 | ||
fd4abac5 TW |
1432 | /* Increment and update queue's write index */ |
1433 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
990aa6d7 | 1434 | iwl_pcie_txq_inc_wr_ptr(trans, txq); |
fd4abac5 | 1435 | |
b9439491 EG |
1436 | spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); |
1437 | ||
2c46f72e | 1438 | out: |
015c15e1 | 1439 | spin_unlock_bh(&txq->lock); |
f4feb8ac JB |
1440 | free_dup_buf: |
1441 | if (idx < 0) | |
1442 | kfree(dup_buf); | |
7bfedc59 | 1443 | return idx; |
fd4abac5 TW |
1444 | } |
1445 | ||
990aa6d7 EG |
1446 | /* |
1447 | * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them | |
17b88929 | 1448 | * @rxb: Rx buffer to reclaim |
247c61d6 EG |
1449 | * @handler_status: return value of the handler of the command |
1450 | * (put in setup_rx_handlers) | |
17b88929 TW |
1451 | * |
1452 | * If an Rx buffer has an async callback associated with it the callback | |
1453 | * will be executed. The attached skb (if present) will only be freed | |
1454 | * if the callback returns 1 | |
1455 | */ | |
990aa6d7 EG |
1456 | void iwl_pcie_hcmd_complete(struct iwl_trans *trans, |
1457 | struct iwl_rx_cmd_buffer *rxb, int handler_status) | |
17b88929 | 1458 | { |
2f301227 | 1459 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
17b88929 TW |
1460 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
1461 | int txq_id = SEQ_TO_QUEUE(sequence); | |
1462 | int index = SEQ_TO_INDEX(sequence); | |
17b88929 | 1463 | int cmd_index; |
c2acea8e JB |
1464 | struct iwl_device_cmd *cmd; |
1465 | struct iwl_cmd_meta *meta; | |
8ad71bef | 1466 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1467 | struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
17b88929 TW |
1468 | |
1469 | /* If a Tx command is being handled and it isn't in the actual | |
1470 | * command queue then there a command routing bug has been introduced | |
1471 | * in the queue management code. */ | |
c6f600fc | 1472 | if (WARN(txq_id != trans_pcie->cmd_queue, |
13bb9483 | 1473 | "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", |
20d3b647 JB |
1474 | txq_id, trans_pcie->cmd_queue, sequence, |
1475 | trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr, | |
1476 | trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) { | |
3e10caeb | 1477 | iwl_print_hex_error(trans, pkt, 32); |
55d6a3cd | 1478 | return; |
01ef9323 | 1479 | } |
17b88929 | 1480 | |
2bfb5092 | 1481 | spin_lock_bh(&txq->lock); |
015c15e1 | 1482 | |
4ce7cc2b | 1483 | cmd_index = get_cmd_index(&txq->q, index); |
bf8440e6 JB |
1484 | cmd = txq->entries[cmd_index].cmd; |
1485 | meta = &txq->entries[cmd_index].meta; | |
17b88929 | 1486 | |
98891754 | 1487 | iwl_pcie_tfd_unmap(trans, meta, &txq->tfds[index]); |
c33de625 | 1488 | |
17b88929 | 1489 | /* Input error checking is done when commands are added to queue. */ |
c2acea8e | 1490 | if (meta->flags & CMD_WANT_SKB) { |
48a2d66f | 1491 | struct page *p = rxb_steal_page(rxb); |
65b94a4a | 1492 | |
65b94a4a JB |
1493 | meta->source->resp_pkt = pkt; |
1494 | meta->source->_rx_page_addr = (unsigned long)page_address(p); | |
b2cf410c | 1495 | meta->source->_rx_page_order = trans_pcie->rx_page_order; |
247c61d6 | 1496 | meta->source->handler_status = handler_status; |
247c61d6 | 1497 | } |
2624e96c | 1498 | |
f02831be | 1499 | iwl_pcie_cmdq_reclaim(trans, txq_id, index); |
17b88929 | 1500 | |
c2acea8e | 1501 | if (!(meta->flags & CMD_ASYNC)) { |
eb7ff77e | 1502 | if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) { |
05c89b91 WYG |
1503 | IWL_WARN(trans, |
1504 | "HCMD_ACTIVE already clear for command %s\n", | |
990aa6d7 | 1505 | get_cmd_string(trans_pcie, cmd->hdr.cmd)); |
05c89b91 | 1506 | } |
eb7ff77e | 1507 | clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); |
6d8f6eeb | 1508 | IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", |
990aa6d7 | 1509 | get_cmd_string(trans_pcie, cmd->hdr.cmd)); |
f946b529 | 1510 | wake_up(&trans_pcie->wait_command_queue); |
17b88929 | 1511 | } |
3598e177 | 1512 | |
dd487449 | 1513 | meta->flags = 0; |
3598e177 | 1514 | |
2bfb5092 | 1515 | spin_unlock_bh(&txq->lock); |
17b88929 | 1516 | } |
253a634c | 1517 | |
9439eac7 | 1518 | #define HOST_COMPLETE_TIMEOUT (2 * HZ) |
253a634c | 1519 | |
f02831be EG |
1520 | static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans, |
1521 | struct iwl_host_cmd *cmd) | |
253a634c | 1522 | { |
d9fb6465 | 1523 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
253a634c EG |
1524 | int ret; |
1525 | ||
1526 | /* An asynchronous command can not expect an SKB to be set. */ | |
1527 | if (WARN_ON(cmd->flags & CMD_WANT_SKB)) | |
1528 | return -EINVAL; | |
1529 | ||
f02831be | 1530 | ret = iwl_pcie_enqueue_hcmd(trans, cmd); |
253a634c | 1531 | if (ret < 0) { |
721c32f7 | 1532 | IWL_ERR(trans, |
b36b110c | 1533 | "Error sending %s: enqueue_hcmd failed: %d\n", |
990aa6d7 | 1534 | get_cmd_string(trans_pcie, cmd->id), ret); |
253a634c EG |
1535 | return ret; |
1536 | } | |
1537 | return 0; | |
1538 | } | |
1539 | ||
f02831be EG |
1540 | static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans, |
1541 | struct iwl_host_cmd *cmd) | |
253a634c | 1542 | { |
8ad71bef | 1543 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
253a634c EG |
1544 | int cmd_idx; |
1545 | int ret; | |
1546 | ||
6d8f6eeb | 1547 | IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", |
990aa6d7 | 1548 | get_cmd_string(trans_pcie, cmd->id)); |
253a634c | 1549 | |
eb7ff77e AN |
1550 | if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE, |
1551 | &trans->status), | |
bcbb8c9c JB |
1552 | "Command %s: a command is already active!\n", |
1553 | get_cmd_string(trans_pcie, cmd->id))) | |
2cc39c94 | 1554 | return -EIO; |
2cc39c94 | 1555 | |
6d8f6eeb | 1556 | IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", |
990aa6d7 | 1557 | get_cmd_string(trans_pcie, cmd->id)); |
253a634c | 1558 | |
f02831be | 1559 | cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd); |
253a634c EG |
1560 | if (cmd_idx < 0) { |
1561 | ret = cmd_idx; | |
eb7ff77e | 1562 | clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); |
721c32f7 | 1563 | IWL_ERR(trans, |
b36b110c | 1564 | "Error sending %s: enqueue_hcmd failed: %d\n", |
990aa6d7 | 1565 | get_cmd_string(trans_pcie, cmd->id), ret); |
253a634c EG |
1566 | return ret; |
1567 | } | |
1568 | ||
b9439491 EG |
1569 | ret = wait_event_timeout(trans_pcie->wait_command_queue, |
1570 | !test_bit(STATUS_SYNC_HCMD_ACTIVE, | |
1571 | &trans->status), | |
1572 | HOST_COMPLETE_TIMEOUT); | |
253a634c | 1573 | if (!ret) { |
6dde8c48 JB |
1574 | struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
1575 | struct iwl_queue *q = &txq->q; | |
d10630af | 1576 | |
6dde8c48 JB |
1577 | IWL_ERR(trans, "Error sending %s: time out after %dms.\n", |
1578 | get_cmd_string(trans_pcie, cmd->id), | |
1579 | jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); | |
253a634c | 1580 | |
6dde8c48 JB |
1581 | IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n", |
1582 | q->read_ptr, q->write_ptr); | |
d10630af | 1583 | |
eb7ff77e | 1584 | clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); |
6dde8c48 JB |
1585 | IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", |
1586 | get_cmd_string(trans_pcie, cmd->id)); | |
1587 | ret = -ETIMEDOUT; | |
42550a53 | 1588 | |
cfadc3ff | 1589 | iwl_write_prph(trans, DEVICE_SET_NMI_REG, 1); |
2a988e98 | 1590 | iwl_trans_fw_error(trans); |
42550a53 | 1591 | |
6dde8c48 | 1592 | goto cancel; |
253a634c EG |
1593 | } |
1594 | ||
eb7ff77e | 1595 | if (test_bit(STATUS_FW_ERROR, &trans->status)) { |
d18aa87f | 1596 | IWL_ERR(trans, "FW error in SYNC CMD %s\n", |
990aa6d7 | 1597 | get_cmd_string(trans_pcie, cmd->id)); |
b656fa33 | 1598 | dump_stack(); |
d18aa87f JB |
1599 | ret = -EIO; |
1600 | goto cancel; | |
1601 | } | |
1602 | ||
1094fa26 | 1603 | if (!(cmd->flags & CMD_SEND_IN_RFKILL) && |
eb7ff77e | 1604 | test_bit(STATUS_RFKILL, &trans->status)) { |
f946b529 EG |
1605 | IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n"); |
1606 | ret = -ERFKILL; | |
1607 | goto cancel; | |
1608 | } | |
1609 | ||
65b94a4a | 1610 | if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) { |
6d8f6eeb | 1611 | IWL_ERR(trans, "Error: Response NULL in '%s'\n", |
990aa6d7 | 1612 | get_cmd_string(trans_pcie, cmd->id)); |
253a634c EG |
1613 | ret = -EIO; |
1614 | goto cancel; | |
1615 | } | |
1616 | ||
1617 | return 0; | |
1618 | ||
1619 | cancel: | |
1620 | if (cmd->flags & CMD_WANT_SKB) { | |
1621 | /* | |
1622 | * Cancel the CMD_WANT_SKB flag for the cmd in the | |
1623 | * TX cmd queue. Otherwise in case the cmd comes | |
1624 | * in later, it will possibly set an invalid | |
1625 | * address (cmd->meta.source). | |
1626 | */ | |
bf8440e6 JB |
1627 | trans_pcie->txq[trans_pcie->cmd_queue]. |
1628 | entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB; | |
253a634c | 1629 | } |
9cac4943 | 1630 | |
65b94a4a JB |
1631 | if (cmd->resp_pkt) { |
1632 | iwl_free_resp(cmd); | |
1633 | cmd->resp_pkt = NULL; | |
253a634c EG |
1634 | } |
1635 | ||
1636 | return ret; | |
1637 | } | |
1638 | ||
f02831be | 1639 | int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c | 1640 | { |
4f59334b | 1641 | if (!(cmd->flags & CMD_SEND_IN_RFKILL) && |
eb7ff77e | 1642 | test_bit(STATUS_RFKILL, &trans->status)) { |
754d7d9e EG |
1643 | IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n", |
1644 | cmd->id); | |
f946b529 | 1645 | return -ERFKILL; |
754d7d9e | 1646 | } |
f946b529 | 1647 | |
253a634c | 1648 | if (cmd->flags & CMD_ASYNC) |
f02831be | 1649 | return iwl_pcie_send_hcmd_async(trans, cmd); |
253a634c | 1650 | |
f946b529 | 1651 | /* We still can fail on RFKILL that can be asserted while we wait */ |
f02831be | 1652 | return iwl_pcie_send_hcmd_sync(trans, cmd); |
253a634c EG |
1653 | } |
1654 | ||
f02831be EG |
1655 | int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, |
1656 | struct iwl_device_cmd *dev_cmd, int txq_id) | |
a0eaad71 | 1657 | { |
8ad71bef | 1658 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
f02831be EG |
1659 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
1660 | struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload; | |
1661 | struct iwl_cmd_meta *out_meta; | |
1662 | struct iwl_txq *txq; | |
1663 | struct iwl_queue *q; | |
38c0f334 JB |
1664 | dma_addr_t tb0_phys, tb1_phys, scratch_phys; |
1665 | void *tb1_addr; | |
1666 | u16 len, tb1_len, tb2_len; | |
43aa616f | 1667 | bool wait_write_ptr = false; |
f02831be EG |
1668 | __le16 fc = hdr->frame_control; |
1669 | u8 hdr_len = ieee80211_hdrlen(fc); | |
68972c46 | 1670 | u16 wifi_seq; |
f02831be EG |
1671 | |
1672 | txq = &trans_pcie->txq[txq_id]; | |
1673 | q = &txq->q; | |
a0eaad71 | 1674 | |
961de6a5 JB |
1675 | if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used), |
1676 | "TX on unused queue %d\n", txq_id)) | |
f02831be | 1677 | return -EINVAL; |
39644e9a | 1678 | |
f02831be | 1679 | spin_lock(&txq->lock); |
015c15e1 | 1680 | |
f02831be EG |
1681 | /* In AGG mode, the index in the ring must correspond to the WiFi |
1682 | * sequence number. This is a HW requirements to help the SCD to parse | |
1683 | * the BA. | |
1684 | * Check here that the packets are in the right place on the ring. | |
1685 | */ | |
9a886586 | 1686 | wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); |
1092b9bc | 1687 | WARN_ONCE(txq->ampdu && |
68972c46 | 1688 | (wifi_seq & 0xff) != q->write_ptr, |
f02831be EG |
1689 | "Q: %d WiFi Seq %d tfdNum %d", |
1690 | txq_id, wifi_seq, q->write_ptr); | |
f02831be EG |
1691 | |
1692 | /* Set up driver data for this TFD */ | |
1693 | txq->entries[q->write_ptr].skb = skb; | |
1694 | txq->entries[q->write_ptr].cmd = dev_cmd; | |
1695 | ||
f02831be EG |
1696 | dev_cmd->hdr.sequence = |
1697 | cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
1698 | INDEX_TO_SEQ(q->write_ptr))); | |
1699 | ||
38c0f334 JB |
1700 | tb0_phys = iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr); |
1701 | scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) + | |
1702 | offsetof(struct iwl_tx_cmd, scratch); | |
1703 | ||
1704 | tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); | |
1705 | tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); | |
1706 | ||
f02831be EG |
1707 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ |
1708 | out_meta = &txq->entries[q->write_ptr].meta; | |
a0eaad71 | 1709 | |
f02831be | 1710 | /* |
38c0f334 JB |
1711 | * The second TB (tb1) points to the remainder of the TX command |
1712 | * and the 802.11 header - dword aligned size | |
1713 | * (This calculation modifies the TX command, so do it before the | |
1714 | * setup of the first TB) | |
f02831be | 1715 | */ |
38c0f334 JB |
1716 | len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) + |
1717 | hdr_len - IWL_HCMD_SCRATCHBUF_SIZE; | |
1092b9bc | 1718 | tb1_len = ALIGN(len, 4); |
f02831be EG |
1719 | |
1720 | /* Tell NIC about any 2-byte padding after MAC header */ | |
38c0f334 | 1721 | if (tb1_len != len) |
f02831be EG |
1722 | tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; |
1723 | ||
38c0f334 JB |
1724 | /* The first TB points to the scratchbuf data - min_copy bytes */ |
1725 | memcpy(&txq->scratchbufs[q->write_ptr], &dev_cmd->hdr, | |
1726 | IWL_HCMD_SCRATCHBUF_SIZE); | |
1727 | iwl_pcie_txq_build_tfd(trans, txq, tb0_phys, | |
1728 | IWL_HCMD_SCRATCHBUF_SIZE, 1); | |
f02831be | 1729 | |
38c0f334 JB |
1730 | /* there must be data left over for TB1 or this code must be changed */ |
1731 | BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_HCMD_SCRATCHBUF_SIZE); | |
1732 | ||
1733 | /* map the data for TB1 */ | |
1734 | tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_HCMD_SCRATCHBUF_SIZE; | |
1735 | tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE); | |
1736 | if (unlikely(dma_mapping_error(trans->dev, tb1_phys))) | |
1737 | goto out_err; | |
1738 | iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, 0); | |
a0eaad71 | 1739 | |
38c0f334 JB |
1740 | /* |
1741 | * Set up TFD's third entry to point directly to remainder | |
1742 | * of skb, if any (802.11 null frames have no payload). | |
1743 | */ | |
1744 | tb2_len = skb->len - hdr_len; | |
1745 | if (tb2_len > 0) { | |
1746 | dma_addr_t tb2_phys = dma_map_single(trans->dev, | |
1747 | skb->data + hdr_len, | |
1748 | tb2_len, DMA_TO_DEVICE); | |
1749 | if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) { | |
1750 | iwl_pcie_tfd_unmap(trans, out_meta, | |
1751 | &txq->tfds[q->write_ptr]); | |
f02831be EG |
1752 | goto out_err; |
1753 | } | |
38c0f334 | 1754 | iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, 0); |
f02831be | 1755 | } |
a0eaad71 | 1756 | |
f02831be EG |
1757 | /* Set up entry for this TFD in Tx byte-count array */ |
1758 | iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len)); | |
a0eaad71 | 1759 | |
f02831be EG |
1760 | trace_iwlwifi_dev_tx(trans->dev, skb, |
1761 | &txq->tfds[txq->q.write_ptr], | |
1762 | sizeof(struct iwl_tfd), | |
38c0f334 JB |
1763 | &dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len, |
1764 | skb->data + hdr_len, tb2_len); | |
f02831be | 1765 | trace_iwlwifi_dev_tx_data(trans->dev, skb, |
38c0f334 JB |
1766 | skb->data + hdr_len, tb2_len); |
1767 | ||
1768 | if (!ieee80211_has_morefrags(fc)) { | |
43aa616f | 1769 | txq->need_update = true; |
38c0f334 | 1770 | } else { |
43aa616f JB |
1771 | wait_write_ptr = true; |
1772 | txq->need_update = false; | |
38c0f334 | 1773 | } |
7c5ba4a8 | 1774 | |
f02831be EG |
1775 | /* start timer if queue currently empty */ |
1776 | if (txq->need_update && q->read_ptr == q->write_ptr && | |
1777 | trans_pcie->wd_timeout) | |
1778 | mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout); | |
1779 | ||
1780 | /* Tell device the write index *just past* this latest filled TFD */ | |
1781 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
1782 | iwl_pcie_txq_inc_wr_ptr(trans, txq); | |
1783 | ||
1784 | /* | |
1785 | * At this point the frame is "transmitted" successfully | |
43aa616f | 1786 | * and we will get a TX status notification eventually. |
f02831be EG |
1787 | */ |
1788 | if (iwl_queue_space(q) < q->high_mark) { | |
1789 | if (wait_write_ptr) { | |
43aa616f | 1790 | txq->need_update = true; |
f02831be EG |
1791 | iwl_pcie_txq_inc_wr_ptr(trans, txq); |
1792 | } else { | |
1793 | iwl_stop_queue(trans, txq); | |
1794 | } | |
1795 | } | |
1796 | spin_unlock(&txq->lock); | |
1797 | return 0; | |
1798 | out_err: | |
1799 | spin_unlock(&txq->lock); | |
1800 | return -1; | |
a0eaad71 | 1801 | } |