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1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
fb4961db | 3 | * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved. |
1053d35f RR |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
1053d35f RR |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
fd4abac5 | 29 | #include <linux/etherdevice.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
253a634c | 31 | #include <linux/sched.h> |
253a634c | 32 | |
522376d2 EG |
33 | #include "iwl-debug.h" |
34 | #include "iwl-csr.h" | |
35 | #include "iwl-prph.h" | |
1053d35f | 36 | #include "iwl-io.h" |
ed277c93 | 37 | #include "iwl-op-mode.h" |
6468a01a | 38 | #include "internal.h" |
6238b008 | 39 | /* FIXME: need to abstract out TX command (once we know what it looks like) */ |
1023fdc4 | 40 | #include "dvm/commands.h" |
1053d35f | 41 | |
522376d2 EG |
42 | #define IWL_TX_CRC_SIZE 4 |
43 | #define IWL_TX_DELIMITER_SIZE 4 | |
44 | ||
f02831be EG |
45 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
46 | * DMA services | |
47 | * | |
48 | * Theory of operation | |
49 | * | |
50 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
51 | * of buffer descriptors, each of which points to one or more data buffers for | |
52 | * the device to read from or fill. Driver and device exchange status of each | |
53 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
54 | * entries in each circular buffer, to protect against confusing empty and full | |
55 | * queue states. | |
56 | * | |
57 | * The device reads or writes the data in the queues via the device's several | |
58 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
59 | * | |
60 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
61 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
62 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
63 | * Tx queue resumed. | |
64 | * | |
65 | ***************************************************/ | |
66 | static int iwl_queue_space(const struct iwl_queue *q) | |
67 | { | |
68 | int s = q->read_ptr - q->write_ptr; | |
69 | ||
70 | if (q->read_ptr > q->write_ptr) | |
71 | s -= q->n_bd; | |
72 | ||
73 | if (s <= 0) | |
74 | s += q->n_window; | |
75 | /* keep some reserve to not confuse empty and full situations */ | |
76 | s -= 2; | |
77 | if (s < 0) | |
78 | s = 0; | |
79 | return s; | |
80 | } | |
81 | ||
82 | /* | |
83 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes | |
84 | */ | |
85 | static int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id) | |
86 | { | |
87 | q->n_bd = count; | |
88 | q->n_window = slots_num; | |
89 | q->id = id; | |
90 | ||
91 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap | |
92 | * and iwl_queue_dec_wrap are broken. */ | |
93 | if (WARN_ON(!is_power_of_2(count))) | |
94 | return -EINVAL; | |
95 | ||
96 | /* slots_num must be power-of-two size, otherwise | |
97 | * get_cmd_index is broken. */ | |
98 | if (WARN_ON(!is_power_of_2(slots_num))) | |
99 | return -EINVAL; | |
100 | ||
101 | q->low_mark = q->n_window / 4; | |
102 | if (q->low_mark < 4) | |
103 | q->low_mark = 4; | |
104 | ||
105 | q->high_mark = q->n_window / 8; | |
106 | if (q->high_mark < 2) | |
107 | q->high_mark = 2; | |
108 | ||
109 | q->write_ptr = 0; | |
110 | q->read_ptr = 0; | |
111 | ||
112 | return 0; | |
113 | } | |
114 | ||
f02831be EG |
115 | static int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans, |
116 | struct iwl_dma_ptr *ptr, size_t size) | |
117 | { | |
118 | if (WARN_ON(ptr->addr)) | |
119 | return -EINVAL; | |
120 | ||
121 | ptr->addr = dma_alloc_coherent(trans->dev, size, | |
122 | &ptr->dma, GFP_KERNEL); | |
123 | if (!ptr->addr) | |
124 | return -ENOMEM; | |
125 | ptr->size = size; | |
126 | return 0; | |
127 | } | |
128 | ||
129 | static void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, | |
130 | struct iwl_dma_ptr *ptr) | |
131 | { | |
132 | if (unlikely(!ptr->addr)) | |
133 | return; | |
134 | ||
135 | dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma); | |
136 | memset(ptr, 0, sizeof(*ptr)); | |
137 | } | |
138 | ||
139 | static void iwl_pcie_txq_stuck_timer(unsigned long data) | |
140 | { | |
141 | struct iwl_txq *txq = (void *)data; | |
142 | struct iwl_queue *q = &txq->q; | |
143 | struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; | |
144 | struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie); | |
145 | u32 scd_sram_addr = trans_pcie->scd_base_addr + | |
146 | SCD_TX_STTS_QUEUE_OFFSET(txq->q.id); | |
147 | u8 buf[16]; | |
148 | int i; | |
149 | ||
150 | spin_lock(&txq->lock); | |
151 | /* check if triggered erroneously */ | |
152 | if (txq->q.read_ptr == txq->q.write_ptr) { | |
153 | spin_unlock(&txq->lock); | |
154 | return; | |
155 | } | |
156 | spin_unlock(&txq->lock); | |
157 | ||
158 | IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id, | |
159 | jiffies_to_msecs(trans_pcie->wd_timeout)); | |
160 | IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", | |
161 | txq->q.read_ptr, txq->q.write_ptr); | |
162 | ||
163 | iwl_read_targ_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf)); | |
164 | ||
165 | iwl_print_hex_error(trans, buf, sizeof(buf)); | |
166 | ||
167 | for (i = 0; i < FH_TCSR_CHNL_NUM; i++) | |
168 | IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i, | |
169 | iwl_read_direct32(trans, FH_TX_TRB_REG(i))); | |
170 | ||
171 | for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { | |
172 | u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i)); | |
173 | u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; | |
174 | bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); | |
175 | u32 tbl_dw = | |
176 | iwl_read_targ_mem(trans, | |
177 | trans_pcie->scd_base_addr + | |
178 | SCD_TRANS_TBL_OFFSET_QUEUE(i)); | |
179 | ||
180 | if (i & 0x1) | |
181 | tbl_dw = (tbl_dw & 0xFFFF0000) >> 16; | |
182 | else | |
183 | tbl_dw = tbl_dw & 0x0000FFFF; | |
184 | ||
185 | IWL_ERR(trans, | |
186 | "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n", | |
187 | i, active ? "" : "in", fifo, tbl_dw, | |
188 | iwl_read_prph(trans, | |
189 | SCD_QUEUE_RDPTR(i)) & (txq->q.n_bd - 1), | |
190 | iwl_read_prph(trans, SCD_QUEUE_WRPTR(i))); | |
191 | } | |
192 | ||
193 | for (i = q->read_ptr; i != q->write_ptr; | |
194 | i = iwl_queue_inc_wrap(i, q->n_bd)) { | |
195 | struct iwl_tx_cmd *tx_cmd = | |
196 | (struct iwl_tx_cmd *)txq->entries[i].cmd->payload; | |
197 | IWL_ERR(trans, "scratch %d = 0x%08x\n", i, | |
198 | get_unaligned_le32(&tx_cmd->scratch)); | |
199 | } | |
200 | ||
201 | iwl_op_mode_nic_error(trans->op_mode); | |
202 | } | |
203 | ||
990aa6d7 EG |
204 | /* |
205 | * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array | |
48d42c42 | 206 | */ |
f02831be EG |
207 | static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans, |
208 | struct iwl_txq *txq, u16 byte_cnt) | |
48d42c42 | 209 | { |
105183b1 | 210 | struct iwlagn_scd_bc_tbl *scd_bc_tbl; |
20d3b647 | 211 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
48d42c42 EG |
212 | int write_ptr = txq->q.write_ptr; |
213 | int txq_id = txq->q.id; | |
214 | u8 sec_ctl = 0; | |
215 | u8 sta_id = 0; | |
216 | u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; | |
217 | __le16 bc_ent; | |
132f98c2 | 218 | struct iwl_tx_cmd *tx_cmd = |
bf8440e6 | 219 | (void *) txq->entries[txq->q.write_ptr].cmd->payload; |
48d42c42 | 220 | |
105183b1 EG |
221 | scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; |
222 | ||
48d42c42 EG |
223 | WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX); |
224 | ||
132f98c2 EG |
225 | sta_id = tx_cmd->sta_id; |
226 | sec_ctl = tx_cmd->sec_ctl; | |
48d42c42 EG |
227 | |
228 | switch (sec_ctl & TX_CMD_SEC_MSK) { | |
229 | case TX_CMD_SEC_CCM: | |
230 | len += CCMP_MIC_LEN; | |
231 | break; | |
232 | case TX_CMD_SEC_TKIP: | |
233 | len += TKIP_ICV_LEN; | |
234 | break; | |
235 | case TX_CMD_SEC_WEP: | |
236 | len += WEP_IV_LEN + WEP_ICV_LEN; | |
237 | break; | |
238 | } | |
239 | ||
046db346 EG |
240 | if (trans_pcie->bc_table_dword) |
241 | len = DIV_ROUND_UP(len, 4); | |
242 | ||
243 | bc_ent = cpu_to_le16(len | (sta_id << 12)); | |
48d42c42 EG |
244 | |
245 | scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; | |
246 | ||
247 | if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
248 | scd_bc_tbl[txq_id]. | |
249 | tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; | |
250 | } | |
251 | ||
f02831be EG |
252 | static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans, |
253 | struct iwl_txq *txq) | |
254 | { | |
255 | struct iwl_trans_pcie *trans_pcie = | |
256 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
257 | struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; | |
258 | int txq_id = txq->q.id; | |
259 | int read_ptr = txq->q.read_ptr; | |
260 | u8 sta_id = 0; | |
261 | __le16 bc_ent; | |
262 | struct iwl_tx_cmd *tx_cmd = | |
263 | (void *)txq->entries[txq->q.read_ptr].cmd->payload; | |
264 | ||
265 | WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); | |
266 | ||
267 | if (txq_id != trans_pcie->cmd_queue) | |
268 | sta_id = tx_cmd->sta_id; | |
269 | ||
270 | bc_ent = cpu_to_le16(1 | (sta_id << 12)); | |
271 | scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; | |
272 | ||
273 | if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
274 | scd_bc_tbl[txq_id]. | |
275 | tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; | |
276 | } | |
277 | ||
990aa6d7 EG |
278 | /* |
279 | * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware | |
fd4abac5 | 280 | */ |
990aa6d7 | 281 | void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_txq *txq) |
fd4abac5 TW |
282 | { |
283 | u32 reg = 0; | |
fd4abac5 TW |
284 | int txq_id = txq->q.id; |
285 | ||
286 | if (txq->need_update == 0) | |
7bfedc59 | 287 | return; |
fd4abac5 | 288 | |
035f7ff2 | 289 | if (trans->cfg->base_params->shadow_reg_enable) { |
f81c1f48 | 290 | /* shadow register enabled */ |
1042db2a | 291 | iwl_write32(trans, HBUS_TARG_WRPTR, |
f81c1f48 WYG |
292 | txq->q.write_ptr | (txq_id << 8)); |
293 | } else { | |
47107e84 DF |
294 | struct iwl_trans_pcie *trans_pcie = |
295 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
f81c1f48 | 296 | /* if we're trying to save power */ |
01d651d4 | 297 | if (test_bit(STATUS_TPOWER_PMI, &trans_pcie->status)) { |
f81c1f48 WYG |
298 | /* wake up nic if it's powered down ... |
299 | * uCode will wake up, and interrupt us again, so next | |
300 | * time we'll skip this part. */ | |
1042db2a | 301 | reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); |
fd4abac5 | 302 | |
f81c1f48 | 303 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { |
fd656935 | 304 | IWL_DEBUG_INFO(trans, |
f81c1f48 WYG |
305 | "Tx queue %d requesting wakeup," |
306 | " GP1 = 0x%x\n", txq_id, reg); | |
1042db2a | 307 | iwl_set_bit(trans, CSR_GP_CNTRL, |
f81c1f48 WYG |
308 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
309 | return; | |
310 | } | |
fd4abac5 | 311 | |
1042db2a | 312 | iwl_write_direct32(trans, HBUS_TARG_WRPTR, |
fd4abac5 | 313 | txq->q.write_ptr | (txq_id << 8)); |
fd4abac5 | 314 | |
f81c1f48 WYG |
315 | /* |
316 | * else not in power-save mode, | |
317 | * uCode will never sleep when we're | |
318 | * trying to tx (during RFKILL, we're not trying to tx). | |
319 | */ | |
320 | } else | |
1042db2a | 321 | iwl_write32(trans, HBUS_TARG_WRPTR, |
f81c1f48 WYG |
322 | txq->q.write_ptr | (txq_id << 8)); |
323 | } | |
fd4abac5 | 324 | txq->need_update = 0; |
fd4abac5 | 325 | } |
fd4abac5 | 326 | |
f02831be | 327 | static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
214d14d4 JB |
328 | { |
329 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
330 | ||
331 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
332 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
333 | addr |= | |
334 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
335 | ||
336 | return addr; | |
337 | } | |
338 | ||
f02831be | 339 | static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) |
214d14d4 JB |
340 | { |
341 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
342 | ||
343 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
344 | } | |
345 | ||
f02831be EG |
346 | static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, |
347 | dma_addr_t addr, u16 len) | |
214d14d4 JB |
348 | { |
349 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
350 | u16 hi_n_len = len << 4; | |
351 | ||
352 | put_unaligned_le32(addr, &tb->lo); | |
353 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
354 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
355 | ||
356 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
357 | ||
358 | tfd->num_tbs = idx + 1; | |
359 | } | |
360 | ||
f02831be | 361 | static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_tfd *tfd) |
214d14d4 JB |
362 | { |
363 | return tfd->num_tbs & 0x1f; | |
364 | } | |
365 | ||
f02831be EG |
366 | static void iwl_pcie_tfd_unmap(struct iwl_trans *trans, |
367 | struct iwl_cmd_meta *meta, struct iwl_tfd *tfd, | |
368 | enum dma_data_direction dma_dir) | |
214d14d4 | 369 | { |
214d14d4 JB |
370 | int i; |
371 | int num_tbs; | |
372 | ||
214d14d4 | 373 | /* Sanity check on number of chunks */ |
f02831be | 374 | num_tbs = iwl_pcie_tfd_get_num_tbs(tfd); |
214d14d4 JB |
375 | |
376 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
6d8f6eeb | 377 | IWL_ERR(trans, "Too many chunks: %i\n", num_tbs); |
214d14d4 JB |
378 | /* @todo issue fatal error, it is quite serious situation */ |
379 | return; | |
380 | } | |
381 | ||
382 | /* Unmap tx_cmd */ | |
383 | if (num_tbs) | |
1042db2a | 384 | dma_unmap_single(trans->dev, |
4ce7cc2b JB |
385 | dma_unmap_addr(meta, mapping), |
386 | dma_unmap_len(meta, len), | |
795414db | 387 | DMA_BIDIRECTIONAL); |
214d14d4 JB |
388 | |
389 | /* Unmap chunks, if any. */ | |
390 | for (i = 1; i < num_tbs; i++) | |
f02831be EG |
391 | dma_unmap_single(trans->dev, iwl_pcie_tfd_tb_get_addr(tfd, i), |
392 | iwl_pcie_tfd_tb_get_len(tfd, i), dma_dir); | |
ebed633c EG |
393 | |
394 | tfd->num_tbs = 0; | |
4ce7cc2b JB |
395 | } |
396 | ||
990aa6d7 EG |
397 | /* |
398 | * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
6d8f6eeb | 399 | * @trans - transport private data |
4ce7cc2b | 400 | * @txq - tx queue |
ebed633c | 401 | * @dma_dir - the direction of the DMA mapping |
4ce7cc2b JB |
402 | * |
403 | * Does NOT advance any TFD circular buffer read/write indexes | |
404 | * Does NOT free the TFD itself (which is within circular buffer) | |
405 | */ | |
f02831be EG |
406 | static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq, |
407 | enum dma_data_direction dma_dir) | |
4ce7cc2b JB |
408 | { |
409 | struct iwl_tfd *tfd_tmp = txq->tfds; | |
4ce7cc2b | 410 | |
ebed633c EG |
411 | /* rd_ptr is bounded by n_bd and idx is bounded by n_window */ |
412 | int rd_ptr = txq->q.read_ptr; | |
413 | int idx = get_cmd_index(&txq->q, rd_ptr); | |
414 | ||
015c15e1 JB |
415 | lockdep_assert_held(&txq->lock); |
416 | ||
ebed633c | 417 | /* We have only q->n_window txq->entries, but we use q->n_bd tfds */ |
f02831be EG |
418 | iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr], |
419 | dma_dir); | |
214d14d4 JB |
420 | |
421 | /* free SKB */ | |
bf8440e6 | 422 | if (txq->entries) { |
214d14d4 JB |
423 | struct sk_buff *skb; |
424 | ||
ebed633c | 425 | skb = txq->entries[idx].skb; |
214d14d4 | 426 | |
909e9b23 EG |
427 | /* Can be called from irqs-disabled context |
428 | * If skb is not NULL, it means that the whole queue is being | |
429 | * freed and that the queue is not empty - free the skb | |
430 | */ | |
214d14d4 | 431 | if (skb) { |
ed277c93 | 432 | iwl_op_mode_free_skb(trans->op_mode, skb); |
ebed633c | 433 | txq->entries[idx].skb = NULL; |
214d14d4 JB |
434 | } |
435 | } | |
436 | } | |
437 | ||
f02831be EG |
438 | static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq, |
439 | dma_addr_t addr, u16 len, u8 reset) | |
214d14d4 JB |
440 | { |
441 | struct iwl_queue *q; | |
442 | struct iwl_tfd *tfd, *tfd_tmp; | |
443 | u32 num_tbs; | |
444 | ||
445 | q = &txq->q; | |
4ce7cc2b | 446 | tfd_tmp = txq->tfds; |
214d14d4 JB |
447 | tfd = &tfd_tmp[q->write_ptr]; |
448 | ||
f02831be EG |
449 | if (reset) |
450 | memset(tfd, 0, sizeof(*tfd)); | |
451 | ||
452 | num_tbs = iwl_pcie_tfd_get_num_tbs(tfd); | |
453 | ||
454 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
455 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
456 | IWL_ERR(trans, "Error can not send more than %d chunks\n", | |
457 | IWL_NUM_OF_TBS); | |
458 | return -EINVAL; | |
459 | } | |
460 | ||
461 | if (WARN_ON(addr & ~DMA_BIT_MASK(36))) | |
462 | return -EINVAL; | |
463 | ||
464 | if (unlikely(addr & ~IWL_TX_DMA_MASK)) | |
465 | IWL_ERR(trans, "Unaligned address = %llx\n", | |
466 | (unsigned long long)addr); | |
467 | ||
468 | iwl_pcie_tfd_set_tb(tfd, num_tbs, addr, len); | |
469 | ||
470 | return 0; | |
471 | } | |
472 | ||
473 | static int iwl_pcie_txq_alloc(struct iwl_trans *trans, | |
474 | struct iwl_txq *txq, int slots_num, | |
475 | u32 txq_id) | |
476 | { | |
477 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
478 | size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX; | |
479 | int i; | |
480 | ||
481 | if (WARN_ON(txq->entries || txq->tfds)) | |
482 | return -EINVAL; | |
483 | ||
484 | setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer, | |
485 | (unsigned long)txq); | |
486 | txq->trans_pcie = trans_pcie; | |
487 | ||
488 | txq->q.n_window = slots_num; | |
489 | ||
490 | txq->entries = kcalloc(slots_num, | |
491 | sizeof(struct iwl_pcie_txq_entry), | |
492 | GFP_KERNEL); | |
493 | ||
494 | if (!txq->entries) | |
495 | goto error; | |
496 | ||
497 | if (txq_id == trans_pcie->cmd_queue) | |
498 | for (i = 0; i < slots_num; i++) { | |
499 | txq->entries[i].cmd = | |
500 | kmalloc(sizeof(struct iwl_device_cmd), | |
501 | GFP_KERNEL); | |
502 | if (!txq->entries[i].cmd) | |
503 | goto error; | |
504 | } | |
505 | ||
506 | /* Circular buffer of transmit frame descriptors (TFDs), | |
507 | * shared with device */ | |
508 | txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz, | |
509 | &txq->q.dma_addr, GFP_KERNEL); | |
510 | if (!txq->tfds) { | |
511 | IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz); | |
512 | goto error; | |
513 | } | |
514 | txq->q.id = txq_id; | |
515 | ||
516 | return 0; | |
517 | error: | |
518 | if (txq->entries && txq_id == trans_pcie->cmd_queue) | |
519 | for (i = 0; i < slots_num; i++) | |
520 | kfree(txq->entries[i].cmd); | |
521 | kfree(txq->entries); | |
522 | txq->entries = NULL; | |
523 | ||
524 | return -ENOMEM; | |
525 | ||
526 | } | |
527 | ||
528 | static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq, | |
529 | int slots_num, u32 txq_id) | |
530 | { | |
531 | int ret; | |
532 | ||
533 | txq->need_update = 0; | |
534 | ||
535 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise | |
536 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ | |
537 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); | |
538 | ||
539 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
540 | ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num, | |
541 | txq_id); | |
542 | if (ret) | |
543 | return ret; | |
544 | ||
545 | spin_lock_init(&txq->lock); | |
546 | ||
547 | /* | |
548 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
549 | * given Tx queue, and enable the DMA channel used for that queue. | |
550 | * Circular buffer (TFD queue in DRAM) physical base address */ | |
551 | iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id), | |
552 | txq->q.dma_addr >> 8); | |
553 | ||
554 | return 0; | |
555 | } | |
556 | ||
557 | /* | |
558 | * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's | |
559 | */ | |
560 | static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id) | |
561 | { | |
562 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
563 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
564 | struct iwl_queue *q = &txq->q; | |
565 | enum dma_data_direction dma_dir; | |
566 | ||
567 | if (!q->n_bd) | |
568 | return; | |
569 | ||
570 | /* In the command queue, all the TBs are mapped as BIDI | |
571 | * so unmap them as such. | |
572 | */ | |
573 | if (txq_id == trans_pcie->cmd_queue) | |
574 | dma_dir = DMA_BIDIRECTIONAL; | |
575 | else | |
576 | dma_dir = DMA_TO_DEVICE; | |
577 | ||
578 | spin_lock_bh(&txq->lock); | |
579 | while (q->write_ptr != q->read_ptr) { | |
580 | iwl_pcie_txq_free_tfd(trans, txq, dma_dir); | |
581 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd); | |
582 | } | |
583 | spin_unlock_bh(&txq->lock); | |
584 | } | |
585 | ||
586 | /* | |
587 | * iwl_pcie_txq_free - Deallocate DMA queue. | |
588 | * @txq: Transmit queue to deallocate. | |
589 | * | |
590 | * Empty queue by removing and destroying all BD's. | |
591 | * Free all buffers. | |
592 | * 0-fill, but do not free "txq" descriptor structure. | |
593 | */ | |
594 | static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id) | |
595 | { | |
596 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
597 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
598 | struct device *dev = trans->dev; | |
599 | int i; | |
600 | ||
601 | if (WARN_ON(!txq)) | |
602 | return; | |
603 | ||
604 | iwl_pcie_txq_unmap(trans, txq_id); | |
605 | ||
606 | /* De-alloc array of command/tx buffers */ | |
607 | if (txq_id == trans_pcie->cmd_queue) | |
608 | for (i = 0; i < txq->q.n_window; i++) { | |
609 | kfree(txq->entries[i].cmd); | |
610 | kfree(txq->entries[i].copy_cmd); | |
611 | kfree(txq->entries[i].free_buf); | |
612 | } | |
613 | ||
614 | /* De-alloc circular buffer of TFDs */ | |
615 | if (txq->q.n_bd) { | |
616 | dma_free_coherent(dev, sizeof(struct iwl_tfd) * | |
617 | txq->q.n_bd, txq->tfds, txq->q.dma_addr); | |
618 | memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr)); | |
619 | } | |
620 | ||
621 | kfree(txq->entries); | |
622 | txq->entries = NULL; | |
623 | ||
624 | del_timer_sync(&txq->stuck_timer); | |
625 | ||
626 | /* 0-fill queue descriptor structure */ | |
627 | memset(txq, 0, sizeof(*txq)); | |
628 | } | |
629 | ||
630 | /* | |
631 | * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask | |
632 | */ | |
633 | static void iwl_pcie_txq_set_sched(struct iwl_trans *trans, u32 mask) | |
634 | { | |
635 | struct iwl_trans_pcie __maybe_unused *trans_pcie = | |
636 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
637 | ||
638 | iwl_write_prph(trans, SCD_TXFACT, mask); | |
639 | } | |
640 | ||
641 | void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr) | |
642 | { | |
643 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
644 | u32 a; | |
645 | int chan; | |
646 | u32 reg_val; | |
647 | ||
648 | /* make sure all queue are not stopped/used */ | |
649 | memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); | |
650 | memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); | |
651 | ||
652 | trans_pcie->scd_base_addr = | |
653 | iwl_read_prph(trans, SCD_SRAM_BASE_ADDR); | |
654 | ||
655 | WARN_ON(scd_base_addr != 0 && | |
656 | scd_base_addr != trans_pcie->scd_base_addr); | |
657 | ||
658 | a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND; | |
659 | /* reset conext data memory */ | |
660 | for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND; | |
661 | a += 4) | |
662 | iwl_write_targ_mem(trans, a, 0); | |
663 | /* reset tx status memory */ | |
664 | for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND; | |
665 | a += 4) | |
666 | iwl_write_targ_mem(trans, a, 0); | |
667 | for (; a < trans_pcie->scd_base_addr + | |
668 | SCD_TRANS_TBL_OFFSET_QUEUE( | |
669 | trans->cfg->base_params->num_of_queues); | |
670 | a += 4) | |
671 | iwl_write_targ_mem(trans, a, 0); | |
672 | ||
673 | iwl_write_prph(trans, SCD_DRAM_BASE_ADDR, | |
674 | trans_pcie->scd_bc_tbls.dma >> 10); | |
675 | ||
676 | /* The chain extension of the SCD doesn't work well. This feature is | |
677 | * enabled by default by the HW, so we need to disable it manually. | |
678 | */ | |
679 | iwl_write_prph(trans, SCD_CHAINEXT_EN, 0); | |
680 | ||
681 | iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue, | |
682 | trans_pcie->cmd_fifo); | |
683 | ||
684 | /* Activate all Tx DMA/FIFO channels */ | |
685 | iwl_pcie_txq_set_sched(trans, IWL_MASK(0, 7)); | |
686 | ||
687 | /* Enable DMA channel */ | |
688 | for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++) | |
689 | iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan), | |
690 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
691 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); | |
692 | ||
693 | /* Update FH chicken bits */ | |
694 | reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG); | |
695 | iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG, | |
696 | reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); | |
697 | ||
698 | /* Enable L1-Active */ | |
699 | iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
700 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
701 | } | |
702 | ||
703 | /* | |
704 | * iwl_pcie_tx_stop - Stop all Tx DMA channels | |
705 | */ | |
706 | int iwl_pcie_tx_stop(struct iwl_trans *trans) | |
707 | { | |
708 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
709 | int ch, txq_id, ret; | |
710 | unsigned long flags; | |
711 | ||
712 | /* Turn off all Tx DMA fifos */ | |
713 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); | |
714 | ||
715 | iwl_pcie_txq_set_sched(trans, 0); | |
716 | ||
717 | /* Stop each Tx DMA channel, and wait for it to be idle */ | |
718 | for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { | |
719 | iwl_write_direct32(trans, | |
720 | FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); | |
721 | ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG, | |
722 | FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000); | |
723 | if (ret < 0) | |
724 | IWL_ERR(trans, | |
725 | "Failing on timeout while stopping DMA channel %d [0x%08x]\n", | |
726 | ch, | |
727 | iwl_read_direct32(trans, | |
728 | FH_TSSR_TX_STATUS_REG)); | |
729 | } | |
730 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); | |
731 | ||
732 | if (!trans_pcie->txq) { | |
733 | IWL_WARN(trans, | |
734 | "Stopping tx queues that aren't allocated...\n"); | |
735 | return 0; | |
736 | } | |
737 | ||
738 | /* Unmap DMA from host system and free skb's */ | |
739 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
740 | txq_id++) | |
741 | iwl_pcie_txq_unmap(trans, txq_id); | |
742 | ||
743 | return 0; | |
744 | } | |
745 | ||
746 | /* | |
747 | * iwl_trans_tx_free - Free TXQ Context | |
748 | * | |
749 | * Destroy all TX DMA queues and structures | |
750 | */ | |
751 | void iwl_pcie_tx_free(struct iwl_trans *trans) | |
752 | { | |
753 | int txq_id; | |
754 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
755 | ||
756 | /* Tx queues */ | |
757 | if (trans_pcie->txq) { | |
758 | for (txq_id = 0; | |
759 | txq_id < trans->cfg->base_params->num_of_queues; txq_id++) | |
760 | iwl_pcie_txq_free(trans, txq_id); | |
761 | } | |
762 | ||
763 | kfree(trans_pcie->txq); | |
764 | trans_pcie->txq = NULL; | |
765 | ||
766 | iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw); | |
767 | ||
768 | iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls); | |
769 | } | |
770 | ||
771 | /* | |
772 | * iwl_pcie_tx_alloc - allocate TX context | |
773 | * Allocate all Tx DMA structures and initialize them | |
774 | */ | |
775 | static int iwl_pcie_tx_alloc(struct iwl_trans *trans) | |
776 | { | |
777 | int ret; | |
778 | int txq_id, slots_num; | |
779 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
780 | ||
781 | u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues * | |
782 | sizeof(struct iwlagn_scd_bc_tbl); | |
783 | ||
784 | /*It is not allowed to alloc twice, so warn when this happens. | |
785 | * We cannot rely on the previous allocation, so free and fail */ | |
786 | if (WARN_ON(trans_pcie->txq)) { | |
787 | ret = -EINVAL; | |
788 | goto error; | |
789 | } | |
790 | ||
791 | ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls, | |
792 | scd_bc_tbls_size); | |
793 | if (ret) { | |
794 | IWL_ERR(trans, "Scheduler BC Table allocation failed\n"); | |
795 | goto error; | |
796 | } | |
797 | ||
798 | /* Alloc keep-warm buffer */ | |
799 | ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE); | |
800 | if (ret) { | |
801 | IWL_ERR(trans, "Keep Warm allocation failed\n"); | |
802 | goto error; | |
803 | } | |
804 | ||
805 | trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues, | |
806 | sizeof(struct iwl_txq), GFP_KERNEL); | |
807 | if (!trans_pcie->txq) { | |
808 | IWL_ERR(trans, "Not enough memory for txq\n"); | |
809 | ret = ENOMEM; | |
810 | goto error; | |
811 | } | |
812 | ||
813 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
814 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
815 | txq_id++) { | |
816 | slots_num = (txq_id == trans_pcie->cmd_queue) ? | |
817 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
818 | ret = iwl_pcie_txq_alloc(trans, &trans_pcie->txq[txq_id], | |
819 | slots_num, txq_id); | |
820 | if (ret) { | |
821 | IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id); | |
822 | goto error; | |
823 | } | |
824 | } | |
825 | ||
826 | return 0; | |
827 | ||
828 | error: | |
829 | iwl_pcie_tx_free(trans); | |
830 | ||
831 | return ret; | |
832 | } | |
833 | int iwl_pcie_tx_init(struct iwl_trans *trans) | |
834 | { | |
835 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
836 | int ret; | |
837 | int txq_id, slots_num; | |
838 | unsigned long flags; | |
839 | bool alloc = false; | |
840 | ||
841 | if (!trans_pcie->txq) { | |
842 | ret = iwl_pcie_tx_alloc(trans); | |
843 | if (ret) | |
844 | goto error; | |
845 | alloc = true; | |
846 | } | |
847 | ||
848 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); | |
849 | ||
850 | /* Turn off all Tx DMA fifos */ | |
851 | iwl_write_prph(trans, SCD_TXFACT, 0); | |
852 | ||
853 | /* Tell NIC where to find the "keep warm" buffer */ | |
854 | iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, | |
855 | trans_pcie->kw.dma >> 4); | |
856 | ||
857 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); | |
858 | ||
859 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
860 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
861 | txq_id++) { | |
862 | slots_num = (txq_id == trans_pcie->cmd_queue) ? | |
863 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
864 | ret = iwl_pcie_txq_init(trans, &trans_pcie->txq[txq_id], | |
865 | slots_num, txq_id); | |
866 | if (ret) { | |
867 | IWL_ERR(trans, "Tx %d queue init failed\n", txq_id); | |
868 | goto error; | |
869 | } | |
870 | } | |
871 | ||
872 | return 0; | |
873 | error: | |
874 | /*Upon error, free only if we allocated something */ | |
875 | if (alloc) | |
876 | iwl_pcie_tx_free(trans); | |
877 | return ret; | |
878 | } | |
879 | ||
880 | static inline void iwl_pcie_txq_progress(struct iwl_trans_pcie *trans_pcie, | |
881 | struct iwl_txq *txq) | |
882 | { | |
883 | if (!trans_pcie->wd_timeout) | |
884 | return; | |
885 | ||
886 | /* | |
887 | * if empty delete timer, otherwise move timer forward | |
888 | * since we're making progress on this queue | |
889 | */ | |
890 | if (txq->q.read_ptr == txq->q.write_ptr) | |
891 | del_timer(&txq->stuck_timer); | |
892 | else | |
893 | mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout); | |
894 | } | |
895 | ||
896 | /* Frees buffers until index _not_ inclusive */ | |
f6d497cd EG |
897 | void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, |
898 | struct sk_buff_head *skbs) | |
f02831be EG |
899 | { |
900 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
901 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
f6d497cd EG |
902 | /* n_bd is usually 256 => n_bd - 1 = 0xff */ |
903 | int tfd_num = ssn & (txq->q.n_bd - 1); | |
f02831be EG |
904 | struct iwl_queue *q = &txq->q; |
905 | int last_to_free; | |
f02831be EG |
906 | |
907 | /* This function is not meant to release cmd queue*/ | |
908 | if (WARN_ON(txq_id == trans_pcie->cmd_queue)) | |
f6d497cd | 909 | return; |
214d14d4 | 910 | |
f6d497cd EG |
911 | spin_lock(&txq->lock); |
912 | ||
913 | if (txq->q.read_ptr == tfd_num) | |
914 | goto out; | |
915 | ||
916 | IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n", | |
917 | txq_id, txq->q.read_ptr, tfd_num, ssn); | |
214d14d4 | 918 | |
f02831be EG |
919 | /*Since we free until index _not_ inclusive, the one before index is |
920 | * the last we will free. This one must be used */ | |
f6d497cd | 921 | last_to_free = iwl_queue_dec_wrap(tfd_num, q->n_bd); |
f02831be | 922 | |
6ca6ebc1 | 923 | if (!iwl_queue_used(q, last_to_free)) { |
f02831be EG |
924 | IWL_ERR(trans, |
925 | "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n", | |
926 | __func__, txq_id, last_to_free, q->n_bd, | |
927 | q->write_ptr, q->read_ptr); | |
f6d497cd | 928 | goto out; |
214d14d4 JB |
929 | } |
930 | ||
f02831be | 931 | if (WARN_ON(!skb_queue_empty(skbs))) |
f6d497cd | 932 | goto out; |
214d14d4 | 933 | |
f02831be | 934 | for (; |
f6d497cd | 935 | q->read_ptr != tfd_num; |
f02831be | 936 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { |
214d14d4 | 937 | |
f02831be EG |
938 | if (WARN_ON_ONCE(txq->entries[txq->q.read_ptr].skb == NULL)) |
939 | continue; | |
214d14d4 | 940 | |
f02831be | 941 | __skb_queue_tail(skbs, txq->entries[txq->q.read_ptr].skb); |
214d14d4 | 942 | |
f02831be | 943 | txq->entries[txq->q.read_ptr].skb = NULL; |
fd4abac5 | 944 | |
f02831be | 945 | iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq); |
fd4abac5 | 946 | |
f02831be | 947 | iwl_pcie_txq_free_tfd(trans, txq, DMA_TO_DEVICE); |
f02831be | 948 | } |
fd4abac5 | 949 | |
f02831be EG |
950 | iwl_pcie_txq_progress(trans_pcie, txq); |
951 | ||
f6d497cd EG |
952 | if (iwl_queue_space(&txq->q) > txq->q.low_mark) |
953 | iwl_wake_queue(trans, txq); | |
954 | out: | |
f02831be | 955 | spin_unlock(&txq->lock); |
1053d35f RR |
956 | } |
957 | ||
f02831be EG |
958 | /* |
959 | * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd | |
960 | * | |
961 | * When FW advances 'R' index, all entries between old and new 'R' index | |
962 | * need to be reclaimed. As result, some free space forms. If there is | |
963 | * enough free space (> low mark), wake the stack that feeds us. | |
964 | */ | |
965 | static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx) | |
48d42c42 | 966 | { |
f02831be EG |
967 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
968 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
969 | struct iwl_queue *q = &txq->q; | |
970 | int nfreed = 0; | |
48d42c42 | 971 | |
f02831be | 972 | lockdep_assert_held(&txq->lock); |
48d42c42 | 973 | |
6ca6ebc1 | 974 | if ((idx >= q->n_bd) || (!iwl_queue_used(q, idx))) { |
f02831be EG |
975 | IWL_ERR(trans, |
976 | "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n", | |
977 | __func__, txq_id, idx, q->n_bd, | |
978 | q->write_ptr, q->read_ptr); | |
979 | return; | |
980 | } | |
48d42c42 | 981 | |
f02831be EG |
982 | for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; |
983 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
48d42c42 | 984 | |
f02831be EG |
985 | if (nfreed++ > 0) { |
986 | IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", | |
987 | idx, q->write_ptr, q->read_ptr); | |
988 | iwl_op_mode_nic_error(trans->op_mode); | |
989 | } | |
990 | } | |
991 | ||
992 | iwl_pcie_txq_progress(trans_pcie, txq); | |
48d42c42 EG |
993 | } |
994 | ||
f02831be | 995 | static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid, |
1ce8658c | 996 | u16 txq_id) |
48d42c42 | 997 | { |
20d3b647 | 998 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
48d42c42 EG |
999 | u32 tbl_dw_addr; |
1000 | u32 tbl_dw; | |
1001 | u16 scd_q2ratid; | |
1002 | ||
1003 | scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; | |
1004 | ||
105183b1 | 1005 | tbl_dw_addr = trans_pcie->scd_base_addr + |
48d42c42 EG |
1006 | SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); |
1007 | ||
1042db2a | 1008 | tbl_dw = iwl_read_targ_mem(trans, tbl_dw_addr); |
48d42c42 EG |
1009 | |
1010 | if (txq_id & 0x1) | |
1011 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); | |
1012 | else | |
1013 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); | |
1014 | ||
1042db2a | 1015 | iwl_write_targ_mem(trans, tbl_dw_addr, tbl_dw); |
48d42c42 EG |
1016 | |
1017 | return 0; | |
1018 | } | |
1019 | ||
f02831be EG |
1020 | static inline void iwl_pcie_txq_set_inactive(struct iwl_trans *trans, |
1021 | u16 txq_id) | |
48d42c42 EG |
1022 | { |
1023 | /* Simply stop the queue, but don't change any configuration; | |
1024 | * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ | |
1042db2a | 1025 | iwl_write_prph(trans, |
48d42c42 EG |
1026 | SCD_QUEUE_STATUS_BITS(txq_id), |
1027 | (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)| | |
1028 | (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); | |
1029 | } | |
1030 | ||
f02831be EG |
1031 | void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, int fifo, |
1032 | int sta_id, int tid, int frame_limit, u16 ssn) | |
48d42c42 | 1033 | { |
9eae88fa | 1034 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
4beaf6c2 | 1035 | |
9eae88fa JB |
1036 | if (test_and_set_bit(txq_id, trans_pcie->queue_used)) |
1037 | WARN_ONCE(1, "queue %d already used - expect issues", txq_id); | |
48d42c42 | 1038 | |
48d42c42 | 1039 | /* Stop this Tx queue before configuring it */ |
f02831be | 1040 | iwl_pcie_txq_set_inactive(trans, txq_id); |
48d42c42 | 1041 | |
4beaf6c2 EG |
1042 | /* Set this queue as a chain-building queue unless it is CMD queue */ |
1043 | if (txq_id != trans_pcie->cmd_queue) | |
1044 | iwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, BIT(txq_id)); | |
1045 | ||
1046 | /* If this queue is mapped to a certain station: it is an AGG queue */ | |
1047 | if (sta_id != IWL_INVALID_STATION) { | |
1048 | u16 ra_tid = BUILD_RAxTID(sta_id, tid); | |
48d42c42 | 1049 | |
4beaf6c2 | 1050 | /* Map receiver-address / traffic-ID to this queue */ |
f02831be | 1051 | iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id); |
48d42c42 | 1052 | |
4beaf6c2 EG |
1053 | /* enable aggregations for the queue */ |
1054 | iwl_set_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id)); | |
1ce8658c EG |
1055 | } else { |
1056 | /* | |
1057 | * disable aggregations for the queue, this will also make the | |
1058 | * ra_tid mapping configuration irrelevant since it is now a | |
1059 | * non-AGG queue. | |
1060 | */ | |
1061 | iwl_clear_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id)); | |
4beaf6c2 | 1062 | } |
48d42c42 EG |
1063 | |
1064 | /* Place first TFD at index corresponding to start sequence number. | |
1065 | * Assumes that ssn_idx is valid (!= 0xFFF) */ | |
822e8b2a EG |
1066 | trans_pcie->txq[txq_id].q.read_ptr = (ssn & 0xff); |
1067 | trans_pcie->txq[txq_id].q.write_ptr = (ssn & 0xff); | |
1ce8658c EG |
1068 | |
1069 | iwl_write_direct32(trans, HBUS_TARG_WRPTR, | |
1070 | (ssn & 0xff) | (txq_id << 8)); | |
1071 | iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn); | |
48d42c42 EG |
1072 | |
1073 | /* Set up Tx window size and frame limit for this queue */ | |
4beaf6c2 EG |
1074 | iwl_write_targ_mem(trans, trans_pcie->scd_base_addr + |
1075 | SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0); | |
1042db2a | 1076 | iwl_write_targ_mem(trans, trans_pcie->scd_base_addr + |
9eae88fa JB |
1077 | SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), |
1078 | ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
1079 | SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
1080 | ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
1081 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
48d42c42 | 1082 | |
48d42c42 | 1083 | /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ |
1ce8658c EG |
1084 | iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id), |
1085 | (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) | | |
1086 | (fifo << SCD_QUEUE_STTS_REG_POS_TXF) | | |
1087 | (1 << SCD_QUEUE_STTS_REG_POS_WSL) | | |
1088 | SCD_QUEUE_STTS_REG_MSK); | |
1089 | IWL_DEBUG_TX_QUEUES(trans, "Activate queue %d on FIFO %d WrPtr: %d\n", | |
1090 | txq_id, fifo, ssn & 0xff); | |
4beaf6c2 EG |
1091 | } |
1092 | ||
f02831be | 1093 | void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id) |
288712a6 | 1094 | { |
8ad71bef | 1095 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
986ea6c9 EG |
1096 | u32 stts_addr = trans_pcie->scd_base_addr + |
1097 | SCD_TX_STTS_QUEUE_OFFSET(txq_id); | |
1098 | static const u32 zero_val[4] = {}; | |
288712a6 | 1099 | |
9eae88fa JB |
1100 | if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) { |
1101 | WARN_ONCE(1, "queue %d not used", txq_id); | |
1102 | return; | |
48d42c42 EG |
1103 | } |
1104 | ||
f02831be | 1105 | iwl_pcie_txq_set_inactive(trans, txq_id); |
ac928f8d | 1106 | |
986ea6c9 EG |
1107 | _iwl_write_targ_mem_dwords(trans, stts_addr, |
1108 | zero_val, ARRAY_SIZE(zero_val)); | |
1109 | ||
990aa6d7 | 1110 | iwl_pcie_txq_unmap(trans, txq_id); |
6c3fd3f0 | 1111 | |
1ce8658c | 1112 | IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id); |
48d42c42 EG |
1113 | } |
1114 | ||
fd4abac5 TW |
1115 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ |
1116 | ||
990aa6d7 | 1117 | /* |
f02831be | 1118 | * iwl_pcie_enqueue_hcmd - enqueue a uCode command |
fd4abac5 TW |
1119 | * @priv: device private data point |
1120 | * @cmd: a point to the ucode command structure | |
1121 | * | |
1122 | * The function returns < 0 values to indicate the operation is | |
1123 | * failed. On success, it turns the index (> 0) of command in the | |
1124 | * command queue. | |
1125 | */ | |
f02831be EG |
1126 | static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans, |
1127 | struct iwl_host_cmd *cmd) | |
fd4abac5 | 1128 | { |
8ad71bef | 1129 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1130 | struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
fd4abac5 | 1131 | struct iwl_queue *q = &txq->q; |
c2acea8e JB |
1132 | struct iwl_device_cmd *out_cmd; |
1133 | struct iwl_cmd_meta *out_meta; | |
f4feb8ac | 1134 | void *dup_buf = NULL; |
fd4abac5 | 1135 | dma_addr_t phys_addr; |
f4feb8ac | 1136 | int idx; |
4ce7cc2b | 1137 | u16 copy_size, cmd_size; |
4ce7cc2b JB |
1138 | bool had_nocopy = false; |
1139 | int i; | |
96791422 | 1140 | u32 cmd_pos; |
fd4abac5 | 1141 | |
4ce7cc2b JB |
1142 | copy_size = sizeof(out_cmd->hdr); |
1143 | cmd_size = sizeof(out_cmd->hdr); | |
1144 | ||
1145 | /* need one for the header if the first is NOCOPY */ | |
1146 | BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1); | |
1147 | ||
1148 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
1149 | if (!cmd->len[i]) | |
1150 | continue; | |
1151 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { | |
1152 | had_nocopy = true; | |
f4feb8ac JB |
1153 | if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) { |
1154 | idx = -EINVAL; | |
1155 | goto free_dup_buf; | |
1156 | } | |
1157 | } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) { | |
1158 | /* | |
1159 | * This is also a chunk that isn't copied | |
1160 | * to the static buffer so set had_nocopy. | |
1161 | */ | |
1162 | had_nocopy = true; | |
1163 | ||
1164 | /* only allowed once */ | |
1165 | if (WARN_ON(dup_buf)) { | |
1166 | idx = -EINVAL; | |
1167 | goto free_dup_buf; | |
1168 | } | |
1169 | ||
1170 | dup_buf = kmemdup(cmd->data[i], cmd->len[i], | |
1171 | GFP_ATOMIC); | |
1172 | if (!dup_buf) | |
1173 | return -ENOMEM; | |
4ce7cc2b JB |
1174 | } else { |
1175 | /* NOCOPY must not be followed by normal! */ | |
f4feb8ac JB |
1176 | if (WARN_ON(had_nocopy)) { |
1177 | idx = -EINVAL; | |
1178 | goto free_dup_buf; | |
1179 | } | |
4ce7cc2b JB |
1180 | copy_size += cmd->len[i]; |
1181 | } | |
1182 | cmd_size += cmd->len[i]; | |
1183 | } | |
fd4abac5 | 1184 | |
3e41ace5 JB |
1185 | /* |
1186 | * If any of the command structures end up being larger than | |
4ce7cc2b JB |
1187 | * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically |
1188 | * allocated into separate TFDs, then we will need to | |
1189 | * increase the size of the buffers. | |
3e41ace5 | 1190 | */ |
2a79e45e JB |
1191 | if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE, |
1192 | "Command %s (%#x) is too large (%d bytes)\n", | |
990aa6d7 | 1193 | get_cmd_string(trans_pcie, cmd->id), cmd->id, copy_size)) { |
f4feb8ac JB |
1194 | idx = -EINVAL; |
1195 | goto free_dup_buf; | |
1196 | } | |
fd4abac5 | 1197 | |
015c15e1 | 1198 | spin_lock_bh(&txq->lock); |
3598e177 | 1199 | |
c2acea8e | 1200 | if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { |
015c15e1 | 1201 | spin_unlock_bh(&txq->lock); |
3598e177 | 1202 | |
6d8f6eeb | 1203 | IWL_ERR(trans, "No space in command queue\n"); |
0e781842 | 1204 | iwl_op_mode_cmd_queue_full(trans->op_mode); |
f4feb8ac JB |
1205 | idx = -ENOSPC; |
1206 | goto free_dup_buf; | |
fd4abac5 TW |
1207 | } |
1208 | ||
4ce7cc2b | 1209 | idx = get_cmd_index(q, q->write_ptr); |
bf8440e6 JB |
1210 | out_cmd = txq->entries[idx].cmd; |
1211 | out_meta = &txq->entries[idx].meta; | |
c2acea8e | 1212 | |
8ce73f3a | 1213 | memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ |
c2acea8e JB |
1214 | if (cmd->flags & CMD_WANT_SKB) |
1215 | out_meta->source = cmd; | |
fd4abac5 | 1216 | |
4ce7cc2b | 1217 | /* set up the header */ |
fd4abac5 | 1218 | |
4ce7cc2b | 1219 | out_cmd->hdr.cmd = cmd->id; |
fd4abac5 | 1220 | out_cmd->hdr.flags = 0; |
cefeaa5f | 1221 | out_cmd->hdr.sequence = |
c6f600fc | 1222 | cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | |
cefeaa5f | 1223 | INDEX_TO_SEQ(q->write_ptr)); |
4ce7cc2b JB |
1224 | |
1225 | /* and copy the data that needs to be copied */ | |
96791422 | 1226 | cmd_pos = offsetof(struct iwl_device_cmd, payload); |
4ce7cc2b JB |
1227 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { |
1228 | if (!cmd->len[i]) | |
1229 | continue; | |
f4feb8ac JB |
1230 | if (cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | |
1231 | IWL_HCMD_DFL_DUP)) | |
4ce7cc2b | 1232 | break; |
96791422 EG |
1233 | memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], cmd->len[i]); |
1234 | cmd_pos += cmd->len[i]; | |
1235 | } | |
1236 | ||
1237 | WARN_ON_ONCE(txq->entries[idx].copy_cmd); | |
1238 | ||
1239 | /* | |
1240 | * since out_cmd will be the source address of the FH, it will write | |
1241 | * the retry count there. So when the user needs to receivce the HCMD | |
1242 | * that corresponds to the response in the response handler, it needs | |
1243 | * to set CMD_WANT_HCMD. | |
1244 | */ | |
1245 | if (cmd->flags & CMD_WANT_HCMD) { | |
1246 | txq->entries[idx].copy_cmd = | |
1247 | kmemdup(out_cmd, cmd_pos, GFP_ATOMIC); | |
1248 | if (unlikely(!txq->entries[idx].copy_cmd)) { | |
1249 | idx = -ENOMEM; | |
1250 | goto out; | |
1251 | } | |
ded2ae7c | 1252 | } |
4ce7cc2b | 1253 | |
d9fb6465 | 1254 | IWL_DEBUG_HC(trans, |
20d3b647 | 1255 | "Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n", |
990aa6d7 | 1256 | get_cmd_string(trans_pcie, out_cmd->hdr.cmd), |
20d3b647 JB |
1257 | out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence), |
1258 | cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue); | |
4ce7cc2b | 1259 | |
1042db2a | 1260 | phys_addr = dma_map_single(trans->dev, &out_cmd->hdr, copy_size, |
20d3b647 | 1261 | DMA_BIDIRECTIONAL); |
1042db2a | 1262 | if (unlikely(dma_mapping_error(trans->dev, phys_addr))) { |
2c46f72e JB |
1263 | idx = -ENOMEM; |
1264 | goto out; | |
1265 | } | |
1266 | ||
2e724443 | 1267 | dma_unmap_addr_set(out_meta, mapping, phys_addr); |
4ce7cc2b JB |
1268 | dma_unmap_len_set(out_meta, len, copy_size); |
1269 | ||
f02831be | 1270 | iwl_pcie_txq_build_tfd(trans, txq, phys_addr, copy_size, 1); |
4ce7cc2b JB |
1271 | |
1272 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
f4feb8ac JB |
1273 | const void *data = cmd->data[i]; |
1274 | ||
4ce7cc2b JB |
1275 | if (!cmd->len[i]) |
1276 | continue; | |
f4feb8ac JB |
1277 | if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | |
1278 | IWL_HCMD_DFL_DUP))) | |
4ce7cc2b | 1279 | continue; |
f4feb8ac JB |
1280 | if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) |
1281 | data = dup_buf; | |
1282 | phys_addr = dma_map_single(trans->dev, (void *)data, | |
3be3fdb5 | 1283 | cmd->len[i], DMA_BIDIRECTIONAL); |
1042db2a | 1284 | if (dma_mapping_error(trans->dev, phys_addr)) { |
f02831be EG |
1285 | iwl_pcie_tfd_unmap(trans, out_meta, |
1286 | &txq->tfds[q->write_ptr], | |
1287 | DMA_BIDIRECTIONAL); | |
4ce7cc2b JB |
1288 | idx = -ENOMEM; |
1289 | goto out; | |
1290 | } | |
1291 | ||
f02831be | 1292 | iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmd->len[i], 0); |
4ce7cc2b | 1293 | } |
df833b1d | 1294 | |
afaf6b57 | 1295 | out_meta->flags = cmd->flags; |
f4feb8ac JB |
1296 | if (WARN_ON_ONCE(txq->entries[idx].free_buf)) |
1297 | kfree(txq->entries[idx].free_buf); | |
1298 | txq->entries[idx].free_buf = dup_buf; | |
2c46f72e JB |
1299 | |
1300 | txq->need_update = 1; | |
1301 | ||
45eab7cc JB |
1302 | trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, |
1303 | &out_cmd->hdr, copy_size); | |
df833b1d | 1304 | |
7c5ba4a8 JB |
1305 | /* start timer if queue currently empty */ |
1306 | if (q->read_ptr == q->write_ptr && trans_pcie->wd_timeout) | |
1307 | mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout); | |
1308 | ||
fd4abac5 TW |
1309 | /* Increment and update queue's write index */ |
1310 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
990aa6d7 | 1311 | iwl_pcie_txq_inc_wr_ptr(trans, txq); |
fd4abac5 | 1312 | |
2c46f72e | 1313 | out: |
015c15e1 | 1314 | spin_unlock_bh(&txq->lock); |
f4feb8ac JB |
1315 | free_dup_buf: |
1316 | if (idx < 0) | |
1317 | kfree(dup_buf); | |
7bfedc59 | 1318 | return idx; |
fd4abac5 TW |
1319 | } |
1320 | ||
990aa6d7 EG |
1321 | /* |
1322 | * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them | |
17b88929 | 1323 | * @rxb: Rx buffer to reclaim |
247c61d6 EG |
1324 | * @handler_status: return value of the handler of the command |
1325 | * (put in setup_rx_handlers) | |
17b88929 TW |
1326 | * |
1327 | * If an Rx buffer has an async callback associated with it the callback | |
1328 | * will be executed. The attached skb (if present) will only be freed | |
1329 | * if the callback returns 1 | |
1330 | */ | |
990aa6d7 EG |
1331 | void iwl_pcie_hcmd_complete(struct iwl_trans *trans, |
1332 | struct iwl_rx_cmd_buffer *rxb, int handler_status) | |
17b88929 | 1333 | { |
2f301227 | 1334 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
17b88929 TW |
1335 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
1336 | int txq_id = SEQ_TO_QUEUE(sequence); | |
1337 | int index = SEQ_TO_INDEX(sequence); | |
17b88929 | 1338 | int cmd_index; |
c2acea8e JB |
1339 | struct iwl_device_cmd *cmd; |
1340 | struct iwl_cmd_meta *meta; | |
8ad71bef | 1341 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1342 | struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
17b88929 TW |
1343 | |
1344 | /* If a Tx command is being handled and it isn't in the actual | |
1345 | * command queue then there a command routing bug has been introduced | |
1346 | * in the queue management code. */ | |
c6f600fc | 1347 | if (WARN(txq_id != trans_pcie->cmd_queue, |
13bb9483 | 1348 | "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", |
20d3b647 JB |
1349 | txq_id, trans_pcie->cmd_queue, sequence, |
1350 | trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr, | |
1351 | trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) { | |
3e10caeb | 1352 | iwl_print_hex_error(trans, pkt, 32); |
55d6a3cd | 1353 | return; |
01ef9323 | 1354 | } |
17b88929 | 1355 | |
015c15e1 JB |
1356 | spin_lock(&txq->lock); |
1357 | ||
4ce7cc2b | 1358 | cmd_index = get_cmd_index(&txq->q, index); |
bf8440e6 JB |
1359 | cmd = txq->entries[cmd_index].cmd; |
1360 | meta = &txq->entries[cmd_index].meta; | |
17b88929 | 1361 | |
f02831be | 1362 | iwl_pcie_tfd_unmap(trans, meta, &txq->tfds[index], DMA_BIDIRECTIONAL); |
c33de625 | 1363 | |
17b88929 | 1364 | /* Input error checking is done when commands are added to queue. */ |
c2acea8e | 1365 | if (meta->flags & CMD_WANT_SKB) { |
48a2d66f | 1366 | struct page *p = rxb_steal_page(rxb); |
65b94a4a | 1367 | |
65b94a4a JB |
1368 | meta->source->resp_pkt = pkt; |
1369 | meta->source->_rx_page_addr = (unsigned long)page_address(p); | |
b2cf410c | 1370 | meta->source->_rx_page_order = trans_pcie->rx_page_order; |
247c61d6 | 1371 | meta->source->handler_status = handler_status; |
247c61d6 | 1372 | } |
2624e96c | 1373 | |
f02831be | 1374 | iwl_pcie_cmdq_reclaim(trans, txq_id, index); |
17b88929 | 1375 | |
c2acea8e | 1376 | if (!(meta->flags & CMD_ASYNC)) { |
74fda971 | 1377 | if (!test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) { |
05c89b91 WYG |
1378 | IWL_WARN(trans, |
1379 | "HCMD_ACTIVE already clear for command %s\n", | |
990aa6d7 | 1380 | get_cmd_string(trans_pcie, cmd->hdr.cmd)); |
05c89b91 | 1381 | } |
74fda971 | 1382 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); |
6d8f6eeb | 1383 | IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", |
990aa6d7 | 1384 | get_cmd_string(trans_pcie, cmd->hdr.cmd)); |
f946b529 | 1385 | wake_up(&trans_pcie->wait_command_queue); |
17b88929 | 1386 | } |
3598e177 | 1387 | |
dd487449 | 1388 | meta->flags = 0; |
3598e177 | 1389 | |
015c15e1 | 1390 | spin_unlock(&txq->lock); |
17b88929 | 1391 | } |
253a634c | 1392 | |
253a634c EG |
1393 | #define HOST_COMPLETE_TIMEOUT (2 * HZ) |
1394 | ||
f02831be EG |
1395 | static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans, |
1396 | struct iwl_host_cmd *cmd) | |
253a634c | 1397 | { |
d9fb6465 | 1398 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
253a634c EG |
1399 | int ret; |
1400 | ||
1401 | /* An asynchronous command can not expect an SKB to be set. */ | |
1402 | if (WARN_ON(cmd->flags & CMD_WANT_SKB)) | |
1403 | return -EINVAL; | |
1404 | ||
f02831be | 1405 | ret = iwl_pcie_enqueue_hcmd(trans, cmd); |
253a634c | 1406 | if (ret < 0) { |
721c32f7 | 1407 | IWL_ERR(trans, |
b36b110c | 1408 | "Error sending %s: enqueue_hcmd failed: %d\n", |
990aa6d7 | 1409 | get_cmd_string(trans_pcie, cmd->id), ret); |
253a634c EG |
1410 | return ret; |
1411 | } | |
1412 | return 0; | |
1413 | } | |
1414 | ||
f02831be EG |
1415 | static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans, |
1416 | struct iwl_host_cmd *cmd) | |
253a634c | 1417 | { |
8ad71bef | 1418 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
253a634c EG |
1419 | int cmd_idx; |
1420 | int ret; | |
1421 | ||
6d8f6eeb | 1422 | IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", |
990aa6d7 | 1423 | get_cmd_string(trans_pcie, cmd->id)); |
253a634c | 1424 | |
2cc39c94 | 1425 | if (WARN_ON(test_and_set_bit(STATUS_HCMD_ACTIVE, |
74fda971 | 1426 | &trans_pcie->status))) { |
2cc39c94 | 1427 | IWL_ERR(trans, "Command %s: a command is already active!\n", |
990aa6d7 | 1428 | get_cmd_string(trans_pcie, cmd->id)); |
2cc39c94 JB |
1429 | return -EIO; |
1430 | } | |
1431 | ||
6d8f6eeb | 1432 | IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", |
990aa6d7 | 1433 | get_cmd_string(trans_pcie, cmd->id)); |
253a634c | 1434 | |
f02831be | 1435 | cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd); |
253a634c EG |
1436 | if (cmd_idx < 0) { |
1437 | ret = cmd_idx; | |
74fda971 | 1438 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); |
721c32f7 | 1439 | IWL_ERR(trans, |
b36b110c | 1440 | "Error sending %s: enqueue_hcmd failed: %d\n", |
990aa6d7 | 1441 | get_cmd_string(trans_pcie, cmd->id), ret); |
253a634c EG |
1442 | return ret; |
1443 | } | |
1444 | ||
f946b529 | 1445 | ret = wait_event_timeout(trans_pcie->wait_command_queue, |
20d3b647 JB |
1446 | !test_bit(STATUS_HCMD_ACTIVE, |
1447 | &trans_pcie->status), | |
1448 | HOST_COMPLETE_TIMEOUT); | |
253a634c | 1449 | if (!ret) { |
74fda971 | 1450 | if (test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) { |
990aa6d7 | 1451 | struct iwl_txq *txq = |
c6f600fc | 1452 | &trans_pcie->txq[trans_pcie->cmd_queue]; |
d10630af WYG |
1453 | struct iwl_queue *q = &txq->q; |
1454 | ||
721c32f7 | 1455 | IWL_ERR(trans, |
253a634c | 1456 | "Error sending %s: time out after %dms.\n", |
990aa6d7 | 1457 | get_cmd_string(trans_pcie, cmd->id), |
253a634c EG |
1458 | jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); |
1459 | ||
721c32f7 | 1460 | IWL_ERR(trans, |
d10630af WYG |
1461 | "Current CMD queue read_ptr %d write_ptr %d\n", |
1462 | q->read_ptr, q->write_ptr); | |
1463 | ||
74fda971 | 1464 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); |
d9fb6465 JB |
1465 | IWL_DEBUG_INFO(trans, |
1466 | "Clearing HCMD_ACTIVE for command %s\n", | |
990aa6d7 | 1467 | get_cmd_string(trans_pcie, cmd->id)); |
253a634c EG |
1468 | ret = -ETIMEDOUT; |
1469 | goto cancel; | |
1470 | } | |
1471 | } | |
1472 | ||
d18aa87f JB |
1473 | if (test_bit(STATUS_FW_ERROR, &trans_pcie->status)) { |
1474 | IWL_ERR(trans, "FW error in SYNC CMD %s\n", | |
990aa6d7 | 1475 | get_cmd_string(trans_pcie, cmd->id)); |
d18aa87f JB |
1476 | ret = -EIO; |
1477 | goto cancel; | |
1478 | } | |
1479 | ||
f946b529 EG |
1480 | if (test_bit(STATUS_RFKILL, &trans_pcie->status)) { |
1481 | IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n"); | |
1482 | ret = -ERFKILL; | |
1483 | goto cancel; | |
1484 | } | |
1485 | ||
65b94a4a | 1486 | if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) { |
6d8f6eeb | 1487 | IWL_ERR(trans, "Error: Response NULL in '%s'\n", |
990aa6d7 | 1488 | get_cmd_string(trans_pcie, cmd->id)); |
253a634c EG |
1489 | ret = -EIO; |
1490 | goto cancel; | |
1491 | } | |
1492 | ||
1493 | return 0; | |
1494 | ||
1495 | cancel: | |
1496 | if (cmd->flags & CMD_WANT_SKB) { | |
1497 | /* | |
1498 | * Cancel the CMD_WANT_SKB flag for the cmd in the | |
1499 | * TX cmd queue. Otherwise in case the cmd comes | |
1500 | * in later, it will possibly set an invalid | |
1501 | * address (cmd->meta.source). | |
1502 | */ | |
bf8440e6 JB |
1503 | trans_pcie->txq[trans_pcie->cmd_queue]. |
1504 | entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB; | |
253a634c | 1505 | } |
9cac4943 | 1506 | |
65b94a4a JB |
1507 | if (cmd->resp_pkt) { |
1508 | iwl_free_resp(cmd); | |
1509 | cmd->resp_pkt = NULL; | |
253a634c EG |
1510 | } |
1511 | ||
1512 | return ret; | |
1513 | } | |
1514 | ||
f02831be | 1515 | int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c | 1516 | { |
f946b529 EG |
1517 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1518 | ||
d18aa87f JB |
1519 | if (test_bit(STATUS_FW_ERROR, &trans_pcie->status)) |
1520 | return -EIO; | |
1521 | ||
f946b529 EG |
1522 | if (test_bit(STATUS_RFKILL, &trans_pcie->status)) |
1523 | return -ERFKILL; | |
1524 | ||
253a634c | 1525 | if (cmd->flags & CMD_ASYNC) |
f02831be | 1526 | return iwl_pcie_send_hcmd_async(trans, cmd); |
253a634c | 1527 | |
f946b529 | 1528 | /* We still can fail on RFKILL that can be asserted while we wait */ |
f02831be | 1529 | return iwl_pcie_send_hcmd_sync(trans, cmd); |
253a634c EG |
1530 | } |
1531 | ||
f02831be EG |
1532 | int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, |
1533 | struct iwl_device_cmd *dev_cmd, int txq_id) | |
a0eaad71 | 1534 | { |
8ad71bef | 1535 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
f02831be EG |
1536 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
1537 | struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload; | |
1538 | struct iwl_cmd_meta *out_meta; | |
1539 | struct iwl_txq *txq; | |
1540 | struct iwl_queue *q; | |
1541 | dma_addr_t phys_addr = 0; | |
1542 | dma_addr_t txcmd_phys; | |
1543 | dma_addr_t scratch_phys; | |
1544 | u16 len, firstlen, secondlen; | |
1545 | u8 wait_write_ptr = 0; | |
1546 | __le16 fc = hdr->frame_control; | |
1547 | u8 hdr_len = ieee80211_hdrlen(fc); | |
1548 | u16 __maybe_unused wifi_seq; | |
1549 | ||
1550 | txq = &trans_pcie->txq[txq_id]; | |
1551 | q = &txq->q; | |
a0eaad71 | 1552 | |
f02831be EG |
1553 | if (unlikely(!test_bit(txq_id, trans_pcie->queue_used))) { |
1554 | WARN_ON_ONCE(1); | |
1555 | return -EINVAL; | |
1556 | } | |
39644e9a | 1557 | |
f02831be | 1558 | spin_lock(&txq->lock); |
015c15e1 | 1559 | |
f02831be EG |
1560 | /* In AGG mode, the index in the ring must correspond to the WiFi |
1561 | * sequence number. This is a HW requirements to help the SCD to parse | |
1562 | * the BA. | |
1563 | * Check here that the packets are in the right place on the ring. | |
1564 | */ | |
1565 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1566 | wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); | |
1567 | WARN_ONCE((iwl_read_prph(trans, SCD_AGGR_SEL) & BIT(txq_id)) && | |
1568 | ((wifi_seq & 0xff) != q->write_ptr), | |
1569 | "Q: %d WiFi Seq %d tfdNum %d", | |
1570 | txq_id, wifi_seq, q->write_ptr); | |
1571 | #endif | |
1572 | ||
1573 | /* Set up driver data for this TFD */ | |
1574 | txq->entries[q->write_ptr].skb = skb; | |
1575 | txq->entries[q->write_ptr].cmd = dev_cmd; | |
1576 | ||
1577 | dev_cmd->hdr.cmd = REPLY_TX; | |
1578 | dev_cmd->hdr.sequence = | |
1579 | cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
1580 | INDEX_TO_SEQ(q->write_ptr))); | |
1581 | ||
1582 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ | |
1583 | out_meta = &txq->entries[q->write_ptr].meta; | |
a0eaad71 | 1584 | |
f02831be EG |
1585 | /* |
1586 | * Use the first empty entry in this queue's command buffer array | |
1587 | * to contain the Tx command and MAC header concatenated together | |
1588 | * (payload data will be in another buffer). | |
1589 | * Size of this varies, due to varying MAC header length. | |
1590 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
1591 | * of the MAC header (device reads on dword boundaries). | |
1592 | * We'll tell device about this padding later. | |
1593 | */ | |
1594 | len = sizeof(struct iwl_tx_cmd) + | |
1595 | sizeof(struct iwl_cmd_header) + hdr_len; | |
1596 | firstlen = (len + 3) & ~3; | |
1597 | ||
1598 | /* Tell NIC about any 2-byte padding after MAC header */ | |
1599 | if (firstlen != len) | |
1600 | tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; | |
1601 | ||
1602 | /* Physical address of this Tx command's header (not MAC header!), | |
1603 | * within command buffer array. */ | |
1604 | txcmd_phys = dma_map_single(trans->dev, | |
1605 | &dev_cmd->hdr, firstlen, | |
1606 | DMA_BIDIRECTIONAL); | |
1607 | if (unlikely(dma_mapping_error(trans->dev, txcmd_phys))) | |
1608 | goto out_err; | |
1609 | dma_unmap_addr_set(out_meta, mapping, txcmd_phys); | |
1610 | dma_unmap_len_set(out_meta, len, firstlen); | |
1611 | ||
1612 | if (!ieee80211_has_morefrags(fc)) { | |
1613 | txq->need_update = 1; | |
1614 | } else { | |
1615 | wait_write_ptr = 1; | |
1616 | txq->need_update = 0; | |
a0eaad71 EG |
1617 | } |
1618 | ||
f02831be EG |
1619 | /* Set up TFD's 2nd entry to point directly to remainder of skb, |
1620 | * if any (802.11 null frames have no payload). */ | |
1621 | secondlen = skb->len - hdr_len; | |
1622 | if (secondlen > 0) { | |
1623 | phys_addr = dma_map_single(trans->dev, skb->data + hdr_len, | |
1624 | secondlen, DMA_TO_DEVICE); | |
1625 | if (unlikely(dma_mapping_error(trans->dev, phys_addr))) { | |
1626 | dma_unmap_single(trans->dev, | |
1627 | dma_unmap_addr(out_meta, mapping), | |
1628 | dma_unmap_len(out_meta, len), | |
1629 | DMA_BIDIRECTIONAL); | |
1630 | goto out_err; | |
1631 | } | |
1632 | } | |
a0eaad71 | 1633 | |
f02831be EG |
1634 | /* Attach buffers to TFD */ |
1635 | iwl_pcie_txq_build_tfd(trans, txq, txcmd_phys, firstlen, 1); | |
1636 | if (secondlen > 0) | |
1637 | iwl_pcie_txq_build_tfd(trans, txq, phys_addr, secondlen, 0); | |
a0eaad71 | 1638 | |
f02831be EG |
1639 | scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) + |
1640 | offsetof(struct iwl_tx_cmd, scratch); | |
a0eaad71 | 1641 | |
f02831be EG |
1642 | /* take back ownership of DMA buffer to enable update */ |
1643 | dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen, | |
1644 | DMA_BIDIRECTIONAL); | |
1645 | tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); | |
1646 | tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); | |
a0eaad71 | 1647 | |
f02831be EG |
1648 | IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n", |
1649 | le16_to_cpu(dev_cmd->hdr.sequence)); | |
1650 | IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags)); | |
a0eaad71 | 1651 | |
f02831be EG |
1652 | /* Set up entry for this TFD in Tx byte-count array */ |
1653 | iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len)); | |
a0eaad71 | 1654 | |
f02831be EG |
1655 | dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen, |
1656 | DMA_BIDIRECTIONAL); | |
7c5ba4a8 | 1657 | |
f02831be EG |
1658 | trace_iwlwifi_dev_tx(trans->dev, skb, |
1659 | &txq->tfds[txq->q.write_ptr], | |
1660 | sizeof(struct iwl_tfd), | |
1661 | &dev_cmd->hdr, firstlen, | |
1662 | skb->data + hdr_len, secondlen); | |
1663 | trace_iwlwifi_dev_tx_data(trans->dev, skb, | |
1664 | skb->data + hdr_len, secondlen); | |
7c5ba4a8 | 1665 | |
f02831be EG |
1666 | /* start timer if queue currently empty */ |
1667 | if (txq->need_update && q->read_ptr == q->write_ptr && | |
1668 | trans_pcie->wd_timeout) | |
1669 | mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout); | |
1670 | ||
1671 | /* Tell device the write index *just past* this latest filled TFD */ | |
1672 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
1673 | iwl_pcie_txq_inc_wr_ptr(trans, txq); | |
1674 | ||
1675 | /* | |
1676 | * At this point the frame is "transmitted" successfully | |
1677 | * and we will get a TX status notification eventually, | |
1678 | * regardless of the value of ret. "ret" only indicates | |
1679 | * whether or not we should update the write pointer. | |
1680 | */ | |
1681 | if (iwl_queue_space(q) < q->high_mark) { | |
1682 | if (wait_write_ptr) { | |
1683 | txq->need_update = 1; | |
1684 | iwl_pcie_txq_inc_wr_ptr(trans, txq); | |
1685 | } else { | |
1686 | iwl_stop_queue(trans, txq); | |
1687 | } | |
1688 | } | |
1689 | spin_unlock(&txq->lock); | |
1690 | return 0; | |
1691 | out_err: | |
1692 | spin_unlock(&txq->lock); | |
1693 | return -1; | |
a0eaad71 | 1694 | } |