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1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
51368bf7 | 3 | * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. |
8b4139dc | 4 | * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH |
1053d35f RR |
5 | * |
6 | * Portions of this file are derived from the ipw3945 project, as well | |
7 | * as portions of the ieee80211 subsystem header files. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of version 2 of the GNU General Public License as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program; if not, write to the Free Software Foundation, Inc., | |
20 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
21 | * | |
22 | * The full GNU General Public License is included in this distribution in the | |
23 | * file called LICENSE. | |
24 | * | |
25 | * Contact Information: | |
759ef89f | 26 | * Intel Linux Wireless <ilw@linux.intel.com> |
1053d35f RR |
27 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
28 | * | |
29 | *****************************************************************************/ | |
fd4abac5 | 30 | #include <linux/etherdevice.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
253a634c | 32 | #include <linux/sched.h> |
253a634c | 33 | |
522376d2 EG |
34 | #include "iwl-debug.h" |
35 | #include "iwl-csr.h" | |
36 | #include "iwl-prph.h" | |
1053d35f | 37 | #include "iwl-io.h" |
680073b7 | 38 | #include "iwl-scd.h" |
ed277c93 | 39 | #include "iwl-op-mode.h" |
6468a01a | 40 | #include "internal.h" |
6238b008 | 41 | /* FIXME: need to abstract out TX command (once we know what it looks like) */ |
1023fdc4 | 42 | #include "dvm/commands.h" |
1053d35f | 43 | |
522376d2 EG |
44 | #define IWL_TX_CRC_SIZE 4 |
45 | #define IWL_TX_DELIMITER_SIZE 4 | |
46 | ||
f02831be EG |
47 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
48 | * DMA services | |
49 | * | |
50 | * Theory of operation | |
51 | * | |
52 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
53 | * of buffer descriptors, each of which points to one or more data buffers for | |
54 | * the device to read from or fill. Driver and device exchange status of each | |
55 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
56 | * entries in each circular buffer, to protect against confusing empty and full | |
57 | * queue states. | |
58 | * | |
59 | * The device reads or writes the data in the queues via the device's several | |
60 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
61 | * | |
62 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
63 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
64 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
65 | * Tx queue resumed. | |
66 | * | |
67 | ***************************************************/ | |
68 | static int iwl_queue_space(const struct iwl_queue *q) | |
69 | { | |
a9b29246 IY |
70 | unsigned int max; |
71 | unsigned int used; | |
f02831be | 72 | |
a9b29246 IY |
73 | /* |
74 | * To avoid ambiguity between empty and completely full queues, there | |
83f32a4b JB |
75 | * should always be less than TFD_QUEUE_SIZE_MAX elements in the queue. |
76 | * If q->n_window is smaller than TFD_QUEUE_SIZE_MAX, there is no need | |
77 | * to reserve any queue entries for this purpose. | |
a9b29246 | 78 | */ |
83f32a4b | 79 | if (q->n_window < TFD_QUEUE_SIZE_MAX) |
a9b29246 IY |
80 | max = q->n_window; |
81 | else | |
83f32a4b | 82 | max = TFD_QUEUE_SIZE_MAX - 1; |
f02831be | 83 | |
a9b29246 | 84 | /* |
83f32a4b JB |
85 | * TFD_QUEUE_SIZE_MAX is a power of 2, so the following is equivalent to |
86 | * modulo by TFD_QUEUE_SIZE_MAX and is well defined. | |
a9b29246 | 87 | */ |
83f32a4b | 88 | used = (q->write_ptr - q->read_ptr) & (TFD_QUEUE_SIZE_MAX - 1); |
a9b29246 IY |
89 | |
90 | if (WARN_ON(used > max)) | |
91 | return 0; | |
92 | ||
93 | return max - used; | |
f02831be EG |
94 | } |
95 | ||
96 | /* | |
97 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes | |
98 | */ | |
83f32a4b | 99 | static int iwl_queue_init(struct iwl_queue *q, int slots_num, u32 id) |
f02831be | 100 | { |
f02831be EG |
101 | q->n_window = slots_num; |
102 | q->id = id; | |
103 | ||
f02831be EG |
104 | /* slots_num must be power-of-two size, otherwise |
105 | * get_cmd_index is broken. */ | |
106 | if (WARN_ON(!is_power_of_2(slots_num))) | |
107 | return -EINVAL; | |
108 | ||
109 | q->low_mark = q->n_window / 4; | |
110 | if (q->low_mark < 4) | |
111 | q->low_mark = 4; | |
112 | ||
113 | q->high_mark = q->n_window / 8; | |
114 | if (q->high_mark < 2) | |
115 | q->high_mark = 2; | |
116 | ||
117 | q->write_ptr = 0; | |
118 | q->read_ptr = 0; | |
119 | ||
120 | return 0; | |
121 | } | |
122 | ||
f02831be EG |
123 | static int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans, |
124 | struct iwl_dma_ptr *ptr, size_t size) | |
125 | { | |
126 | if (WARN_ON(ptr->addr)) | |
127 | return -EINVAL; | |
128 | ||
129 | ptr->addr = dma_alloc_coherent(trans->dev, size, | |
130 | &ptr->dma, GFP_KERNEL); | |
131 | if (!ptr->addr) | |
132 | return -ENOMEM; | |
133 | ptr->size = size; | |
134 | return 0; | |
135 | } | |
136 | ||
137 | static void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, | |
138 | struct iwl_dma_ptr *ptr) | |
139 | { | |
140 | if (unlikely(!ptr->addr)) | |
141 | return; | |
142 | ||
143 | dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma); | |
144 | memset(ptr, 0, sizeof(*ptr)); | |
145 | } | |
146 | ||
147 | static void iwl_pcie_txq_stuck_timer(unsigned long data) | |
148 | { | |
149 | struct iwl_txq *txq = (void *)data; | |
f02831be EG |
150 | struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; |
151 | struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie); | |
152 | u32 scd_sram_addr = trans_pcie->scd_base_addr + | |
153 | SCD_TX_STTS_QUEUE_OFFSET(txq->q.id); | |
154 | u8 buf[16]; | |
155 | int i; | |
156 | ||
157 | spin_lock(&txq->lock); | |
158 | /* check if triggered erroneously */ | |
159 | if (txq->q.read_ptr == txq->q.write_ptr) { | |
160 | spin_unlock(&txq->lock); | |
161 | return; | |
162 | } | |
163 | spin_unlock(&txq->lock); | |
164 | ||
165 | IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id, | |
4cf677fd | 166 | jiffies_to_msecs(txq->wd_timeout)); |
f02831be EG |
167 | IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", |
168 | txq->q.read_ptr, txq->q.write_ptr); | |
169 | ||
4fd442db | 170 | iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf)); |
f02831be EG |
171 | |
172 | iwl_print_hex_error(trans, buf, sizeof(buf)); | |
173 | ||
174 | for (i = 0; i < FH_TCSR_CHNL_NUM; i++) | |
175 | IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i, | |
176 | iwl_read_direct32(trans, FH_TX_TRB_REG(i))); | |
177 | ||
178 | for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { | |
179 | u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i)); | |
180 | u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; | |
181 | bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); | |
182 | u32 tbl_dw = | |
4fd442db EG |
183 | iwl_trans_read_mem32(trans, |
184 | trans_pcie->scd_base_addr + | |
185 | SCD_TRANS_TBL_OFFSET_QUEUE(i)); | |
f02831be EG |
186 | |
187 | if (i & 0x1) | |
188 | tbl_dw = (tbl_dw & 0xFFFF0000) >> 16; | |
189 | else | |
190 | tbl_dw = tbl_dw & 0x0000FFFF; | |
191 | ||
192 | IWL_ERR(trans, | |
193 | "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n", | |
194 | i, active ? "" : "in", fifo, tbl_dw, | |
83f32a4b JB |
195 | iwl_read_prph(trans, SCD_QUEUE_RDPTR(i)) & |
196 | (TFD_QUEUE_SIZE_MAX - 1), | |
f02831be EG |
197 | iwl_read_prph(trans, SCD_QUEUE_WRPTR(i))); |
198 | } | |
199 | ||
4c9706dc | 200 | iwl_force_nmi(trans); |
f02831be EG |
201 | } |
202 | ||
990aa6d7 EG |
203 | /* |
204 | * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array | |
48d42c42 | 205 | */ |
f02831be EG |
206 | static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans, |
207 | struct iwl_txq *txq, u16 byte_cnt) | |
48d42c42 | 208 | { |
105183b1 | 209 | struct iwlagn_scd_bc_tbl *scd_bc_tbl; |
20d3b647 | 210 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
48d42c42 EG |
211 | int write_ptr = txq->q.write_ptr; |
212 | int txq_id = txq->q.id; | |
213 | u8 sec_ctl = 0; | |
214 | u8 sta_id = 0; | |
215 | u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; | |
216 | __le16 bc_ent; | |
132f98c2 | 217 | struct iwl_tx_cmd *tx_cmd = |
bf8440e6 | 218 | (void *) txq->entries[txq->q.write_ptr].cmd->payload; |
48d42c42 | 219 | |
105183b1 EG |
220 | scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; |
221 | ||
132f98c2 EG |
222 | sta_id = tx_cmd->sta_id; |
223 | sec_ctl = tx_cmd->sec_ctl; | |
48d42c42 EG |
224 | |
225 | switch (sec_ctl & TX_CMD_SEC_MSK) { | |
226 | case TX_CMD_SEC_CCM: | |
4325f6ca | 227 | len += IEEE80211_CCMP_MIC_LEN; |
48d42c42 EG |
228 | break; |
229 | case TX_CMD_SEC_TKIP: | |
4325f6ca | 230 | len += IEEE80211_TKIP_ICV_LEN; |
48d42c42 EG |
231 | break; |
232 | case TX_CMD_SEC_WEP: | |
4325f6ca | 233 | len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN; |
48d42c42 EG |
234 | break; |
235 | } | |
236 | ||
046db346 EG |
237 | if (trans_pcie->bc_table_dword) |
238 | len = DIV_ROUND_UP(len, 4); | |
239 | ||
31f920b6 EG |
240 | if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX)) |
241 | return; | |
242 | ||
046db346 | 243 | bc_ent = cpu_to_le16(len | (sta_id << 12)); |
48d42c42 EG |
244 | |
245 | scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; | |
246 | ||
247 | if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
248 | scd_bc_tbl[txq_id]. | |
249 | tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; | |
250 | } | |
251 | ||
f02831be EG |
252 | static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans, |
253 | struct iwl_txq *txq) | |
254 | { | |
255 | struct iwl_trans_pcie *trans_pcie = | |
256 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
257 | struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; | |
258 | int txq_id = txq->q.id; | |
259 | int read_ptr = txq->q.read_ptr; | |
260 | u8 sta_id = 0; | |
261 | __le16 bc_ent; | |
262 | struct iwl_tx_cmd *tx_cmd = | |
263 | (void *)txq->entries[txq->q.read_ptr].cmd->payload; | |
264 | ||
265 | WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); | |
266 | ||
267 | if (txq_id != trans_pcie->cmd_queue) | |
268 | sta_id = tx_cmd->sta_id; | |
269 | ||
270 | bc_ent = cpu_to_le16(1 | (sta_id << 12)); | |
271 | scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; | |
272 | ||
273 | if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
274 | scd_bc_tbl[txq_id]. | |
275 | tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; | |
276 | } | |
277 | ||
990aa6d7 EG |
278 | /* |
279 | * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware | |
fd4abac5 | 280 | */ |
ea68f460 JB |
281 | static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, |
282 | struct iwl_txq *txq) | |
fd4abac5 | 283 | { |
23e76d1a | 284 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
fd4abac5 | 285 | u32 reg = 0; |
fd4abac5 TW |
286 | int txq_id = txq->q.id; |
287 | ||
ea68f460 | 288 | lockdep_assert_held(&txq->lock); |
fd4abac5 | 289 | |
5045388c EP |
290 | /* |
291 | * explicitly wake up the NIC if: | |
292 | * 1. shadow registers aren't enabled | |
293 | * 2. NIC is woken up for CMD regardless of shadow outside this function | |
294 | * 3. there is a chance that the NIC is asleep | |
295 | */ | |
296 | if (!trans->cfg->base_params->shadow_reg_enable && | |
297 | txq_id != trans_pcie->cmd_queue && | |
298 | test_bit(STATUS_TPOWER_PMI, &trans->status)) { | |
f81c1f48 | 299 | /* |
5045388c EP |
300 | * wake up nic if it's powered down ... |
301 | * uCode will wake up, and interrupt us again, so next | |
302 | * time we'll skip this part. | |
f81c1f48 | 303 | */ |
5045388c EP |
304 | reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); |
305 | ||
306 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
307 | IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n", | |
308 | txq_id, reg); | |
309 | iwl_set_bit(trans, CSR_GP_CNTRL, | |
310 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
ea68f460 | 311 | txq->need_update = true; |
5045388c EP |
312 | return; |
313 | } | |
f81c1f48 | 314 | } |
5045388c EP |
315 | |
316 | /* | |
317 | * if not in power-save mode, uCode will never sleep when we're | |
318 | * trying to tx (during RFKILL, we're not trying to tx). | |
319 | */ | |
320 | IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->q.write_ptr); | |
321 | iwl_write32(trans, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8)); | |
ea68f460 | 322 | } |
5045388c | 323 | |
ea68f460 JB |
324 | void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans) |
325 | { | |
326 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
327 | int i; | |
328 | ||
329 | for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { | |
330 | struct iwl_txq *txq = &trans_pcie->txq[i]; | |
331 | ||
d090f878 | 332 | spin_lock_bh(&txq->lock); |
ea68f460 JB |
333 | if (trans_pcie->txq[i].need_update) { |
334 | iwl_pcie_txq_inc_wr_ptr(trans, txq); | |
335 | trans_pcie->txq[i].need_update = false; | |
336 | } | |
d090f878 | 337 | spin_unlock_bh(&txq->lock); |
ea68f460 | 338 | } |
fd4abac5 | 339 | } |
fd4abac5 | 340 | |
f02831be | 341 | static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
214d14d4 JB |
342 | { |
343 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
344 | ||
345 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
346 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
347 | addr |= | |
348 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
349 | ||
350 | return addr; | |
351 | } | |
352 | ||
f02831be EG |
353 | static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, |
354 | dma_addr_t addr, u16 len) | |
214d14d4 JB |
355 | { |
356 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
357 | u16 hi_n_len = len << 4; | |
358 | ||
359 | put_unaligned_le32(addr, &tb->lo); | |
360 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
361 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
362 | ||
363 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
364 | ||
365 | tfd->num_tbs = idx + 1; | |
366 | } | |
367 | ||
f02831be | 368 | static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_tfd *tfd) |
214d14d4 JB |
369 | { |
370 | return tfd->num_tbs & 0x1f; | |
371 | } | |
372 | ||
f02831be | 373 | static void iwl_pcie_tfd_unmap(struct iwl_trans *trans, |
98891754 JB |
374 | struct iwl_cmd_meta *meta, |
375 | struct iwl_tfd *tfd) | |
214d14d4 | 376 | { |
214d14d4 JB |
377 | int i; |
378 | int num_tbs; | |
379 | ||
214d14d4 | 380 | /* Sanity check on number of chunks */ |
f02831be | 381 | num_tbs = iwl_pcie_tfd_get_num_tbs(tfd); |
214d14d4 JB |
382 | |
383 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
6d8f6eeb | 384 | IWL_ERR(trans, "Too many chunks: %i\n", num_tbs); |
214d14d4 JB |
385 | /* @todo issue fatal error, it is quite serious situation */ |
386 | return; | |
387 | } | |
388 | ||
38c0f334 | 389 | /* first TB is never freed - it's the scratchbuf data */ |
214d14d4 | 390 | |
206eea78 JB |
391 | for (i = 1; i < num_tbs; i++) { |
392 | if (meta->flags & BIT(i + CMD_TB_BITMAP_POS)) | |
393 | dma_unmap_page(trans->dev, | |
394 | iwl_pcie_tfd_tb_get_addr(tfd, i), | |
395 | iwl_pcie_tfd_tb_get_len(tfd, i), | |
396 | DMA_TO_DEVICE); | |
397 | else | |
398 | dma_unmap_single(trans->dev, | |
399 | iwl_pcie_tfd_tb_get_addr(tfd, i), | |
400 | iwl_pcie_tfd_tb_get_len(tfd, i), | |
401 | DMA_TO_DEVICE); | |
402 | } | |
ebed633c | 403 | tfd->num_tbs = 0; |
4ce7cc2b JB |
404 | } |
405 | ||
990aa6d7 EG |
406 | /* |
407 | * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
6d8f6eeb | 408 | * @trans - transport private data |
4ce7cc2b | 409 | * @txq - tx queue |
ebed633c | 410 | * @dma_dir - the direction of the DMA mapping |
4ce7cc2b JB |
411 | * |
412 | * Does NOT advance any TFD circular buffer read/write indexes | |
413 | * Does NOT free the TFD itself (which is within circular buffer) | |
414 | */ | |
98891754 | 415 | static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq) |
4ce7cc2b JB |
416 | { |
417 | struct iwl_tfd *tfd_tmp = txq->tfds; | |
4ce7cc2b | 418 | |
83f32a4b JB |
419 | /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and |
420 | * idx is bounded by n_window | |
421 | */ | |
ebed633c EG |
422 | int rd_ptr = txq->q.read_ptr; |
423 | int idx = get_cmd_index(&txq->q, rd_ptr); | |
424 | ||
015c15e1 JB |
425 | lockdep_assert_held(&txq->lock); |
426 | ||
83f32a4b JB |
427 | /* We have only q->n_window txq->entries, but we use |
428 | * TFD_QUEUE_SIZE_MAX tfds | |
429 | */ | |
98891754 | 430 | iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr]); |
214d14d4 JB |
431 | |
432 | /* free SKB */ | |
bf8440e6 | 433 | if (txq->entries) { |
214d14d4 JB |
434 | struct sk_buff *skb; |
435 | ||
ebed633c | 436 | skb = txq->entries[idx].skb; |
214d14d4 | 437 | |
909e9b23 EG |
438 | /* Can be called from irqs-disabled context |
439 | * If skb is not NULL, it means that the whole queue is being | |
440 | * freed and that the queue is not empty - free the skb | |
441 | */ | |
214d14d4 | 442 | if (skb) { |
ed277c93 | 443 | iwl_op_mode_free_skb(trans->op_mode, skb); |
ebed633c | 444 | txq->entries[idx].skb = NULL; |
214d14d4 JB |
445 | } |
446 | } | |
447 | } | |
448 | ||
f02831be | 449 | static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq, |
6d6e68f8 | 450 | dma_addr_t addr, u16 len, bool reset) |
214d14d4 JB |
451 | { |
452 | struct iwl_queue *q; | |
453 | struct iwl_tfd *tfd, *tfd_tmp; | |
454 | u32 num_tbs; | |
455 | ||
456 | q = &txq->q; | |
4ce7cc2b | 457 | tfd_tmp = txq->tfds; |
214d14d4 JB |
458 | tfd = &tfd_tmp[q->write_ptr]; |
459 | ||
f02831be EG |
460 | if (reset) |
461 | memset(tfd, 0, sizeof(*tfd)); | |
462 | ||
463 | num_tbs = iwl_pcie_tfd_get_num_tbs(tfd); | |
464 | ||
465 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
466 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
467 | IWL_ERR(trans, "Error can not send more than %d chunks\n", | |
468 | IWL_NUM_OF_TBS); | |
469 | return -EINVAL; | |
470 | } | |
471 | ||
1092b9bc EP |
472 | if (WARN(addr & ~IWL_TX_DMA_MASK, |
473 | "Unaligned address = %llx\n", (unsigned long long)addr)) | |
f02831be EG |
474 | return -EINVAL; |
475 | ||
f02831be EG |
476 | iwl_pcie_tfd_set_tb(tfd, num_tbs, addr, len); |
477 | ||
206eea78 | 478 | return num_tbs; |
f02831be EG |
479 | } |
480 | ||
481 | static int iwl_pcie_txq_alloc(struct iwl_trans *trans, | |
482 | struct iwl_txq *txq, int slots_num, | |
483 | u32 txq_id) | |
484 | { | |
485 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
486 | size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX; | |
38c0f334 | 487 | size_t scratchbuf_sz; |
f02831be EG |
488 | int i; |
489 | ||
490 | if (WARN_ON(txq->entries || txq->tfds)) | |
491 | return -EINVAL; | |
492 | ||
493 | setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer, | |
494 | (unsigned long)txq); | |
495 | txq->trans_pcie = trans_pcie; | |
496 | ||
497 | txq->q.n_window = slots_num; | |
498 | ||
499 | txq->entries = kcalloc(slots_num, | |
500 | sizeof(struct iwl_pcie_txq_entry), | |
501 | GFP_KERNEL); | |
502 | ||
503 | if (!txq->entries) | |
504 | goto error; | |
505 | ||
506 | if (txq_id == trans_pcie->cmd_queue) | |
507 | for (i = 0; i < slots_num; i++) { | |
508 | txq->entries[i].cmd = | |
509 | kmalloc(sizeof(struct iwl_device_cmd), | |
510 | GFP_KERNEL); | |
511 | if (!txq->entries[i].cmd) | |
512 | goto error; | |
513 | } | |
514 | ||
515 | /* Circular buffer of transmit frame descriptors (TFDs), | |
516 | * shared with device */ | |
517 | txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz, | |
518 | &txq->q.dma_addr, GFP_KERNEL); | |
d0320f75 | 519 | if (!txq->tfds) |
f02831be | 520 | goto error; |
38c0f334 JB |
521 | |
522 | BUILD_BUG_ON(IWL_HCMD_SCRATCHBUF_SIZE != sizeof(*txq->scratchbufs)); | |
523 | BUILD_BUG_ON(offsetof(struct iwl_pcie_txq_scratch_buf, scratch) != | |
524 | sizeof(struct iwl_cmd_header) + | |
525 | offsetof(struct iwl_tx_cmd, scratch)); | |
526 | ||
527 | scratchbuf_sz = sizeof(*txq->scratchbufs) * slots_num; | |
528 | ||
529 | txq->scratchbufs = dma_alloc_coherent(trans->dev, scratchbuf_sz, | |
530 | &txq->scratchbufs_dma, | |
531 | GFP_KERNEL); | |
532 | if (!txq->scratchbufs) | |
533 | goto err_free_tfds; | |
534 | ||
f02831be EG |
535 | txq->q.id = txq_id; |
536 | ||
537 | return 0; | |
38c0f334 JB |
538 | err_free_tfds: |
539 | dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->q.dma_addr); | |
f02831be EG |
540 | error: |
541 | if (txq->entries && txq_id == trans_pcie->cmd_queue) | |
542 | for (i = 0; i < slots_num; i++) | |
543 | kfree(txq->entries[i].cmd); | |
544 | kfree(txq->entries); | |
545 | txq->entries = NULL; | |
546 | ||
547 | return -ENOMEM; | |
548 | ||
549 | } | |
550 | ||
551 | static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq, | |
552 | int slots_num, u32 txq_id) | |
553 | { | |
554 | int ret; | |
555 | ||
43aa616f | 556 | txq->need_update = false; |
f02831be EG |
557 | |
558 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise | |
559 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ | |
560 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); | |
561 | ||
562 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
83f32a4b | 563 | ret = iwl_queue_init(&txq->q, slots_num, txq_id); |
f02831be EG |
564 | if (ret) |
565 | return ret; | |
566 | ||
567 | spin_lock_init(&txq->lock); | |
568 | ||
569 | /* | |
570 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
571 | * given Tx queue, and enable the DMA channel used for that queue. | |
572 | * Circular buffer (TFD queue in DRAM) physical base address */ | |
573 | iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id), | |
574 | txq->q.dma_addr >> 8); | |
575 | ||
576 | return 0; | |
577 | } | |
578 | ||
579 | /* | |
580 | * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's | |
581 | */ | |
582 | static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id) | |
583 | { | |
584 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
585 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
586 | struct iwl_queue *q = &txq->q; | |
f02831be | 587 | |
f02831be EG |
588 | spin_lock_bh(&txq->lock); |
589 | while (q->write_ptr != q->read_ptr) { | |
b967613d EG |
590 | IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n", |
591 | txq_id, q->read_ptr); | |
98891754 | 592 | iwl_pcie_txq_free_tfd(trans, txq); |
83f32a4b | 593 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr); |
f02831be | 594 | } |
b967613d | 595 | txq->active = false; |
f02831be | 596 | spin_unlock_bh(&txq->lock); |
8a487b1a EG |
597 | |
598 | /* just in case - this queue may have been stopped */ | |
599 | iwl_wake_queue(trans, txq); | |
f02831be EG |
600 | } |
601 | ||
602 | /* | |
603 | * iwl_pcie_txq_free - Deallocate DMA queue. | |
604 | * @txq: Transmit queue to deallocate. | |
605 | * | |
606 | * Empty queue by removing and destroying all BD's. | |
607 | * Free all buffers. | |
608 | * 0-fill, but do not free "txq" descriptor structure. | |
609 | */ | |
610 | static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id) | |
611 | { | |
612 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
613 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
614 | struct device *dev = trans->dev; | |
615 | int i; | |
616 | ||
617 | if (WARN_ON(!txq)) | |
618 | return; | |
619 | ||
620 | iwl_pcie_txq_unmap(trans, txq_id); | |
621 | ||
622 | /* De-alloc array of command/tx buffers */ | |
623 | if (txq_id == trans_pcie->cmd_queue) | |
624 | for (i = 0; i < txq->q.n_window; i++) { | |
5d4185ae JB |
625 | kzfree(txq->entries[i].cmd); |
626 | kzfree(txq->entries[i].free_buf); | |
f02831be EG |
627 | } |
628 | ||
629 | /* De-alloc circular buffer of TFDs */ | |
83f32a4b JB |
630 | if (txq->tfds) { |
631 | dma_free_coherent(dev, | |
632 | sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX, | |
633 | txq->tfds, txq->q.dma_addr); | |
d21fa2da | 634 | txq->q.dma_addr = 0; |
83f32a4b | 635 | txq->tfds = NULL; |
38c0f334 JB |
636 | |
637 | dma_free_coherent(dev, | |
638 | sizeof(*txq->scratchbufs) * txq->q.n_window, | |
639 | txq->scratchbufs, txq->scratchbufs_dma); | |
f02831be EG |
640 | } |
641 | ||
642 | kfree(txq->entries); | |
643 | txq->entries = NULL; | |
644 | ||
645 | del_timer_sync(&txq->stuck_timer); | |
646 | ||
647 | /* 0-fill queue descriptor structure */ | |
648 | memset(txq, 0, sizeof(*txq)); | |
649 | } | |
650 | ||
f02831be EG |
651 | void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr) |
652 | { | |
653 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
22dc3c95 | 654 | int nq = trans->cfg->base_params->num_of_queues; |
f02831be EG |
655 | int chan; |
656 | u32 reg_val; | |
22dc3c95 JB |
657 | int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) - |
658 | SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32); | |
f02831be EG |
659 | |
660 | /* make sure all queue are not stopped/used */ | |
661 | memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); | |
662 | memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); | |
663 | ||
664 | trans_pcie->scd_base_addr = | |
665 | iwl_read_prph(trans, SCD_SRAM_BASE_ADDR); | |
666 | ||
667 | WARN_ON(scd_base_addr != 0 && | |
668 | scd_base_addr != trans_pcie->scd_base_addr); | |
669 | ||
22dc3c95 JB |
670 | /* reset context data, TX status and translation data */ |
671 | iwl_trans_write_mem(trans, trans_pcie->scd_base_addr + | |
672 | SCD_CONTEXT_MEM_LOWER_BOUND, | |
673 | NULL, clear_dwords); | |
f02831be EG |
674 | |
675 | iwl_write_prph(trans, SCD_DRAM_BASE_ADDR, | |
676 | trans_pcie->scd_bc_tbls.dma >> 10); | |
677 | ||
678 | /* The chain extension of the SCD doesn't work well. This feature is | |
679 | * enabled by default by the HW, so we need to disable it manually. | |
680 | */ | |
e03bbb62 EG |
681 | if (trans->cfg->base_params->scd_chain_ext_wa) |
682 | iwl_write_prph(trans, SCD_CHAINEXT_EN, 0); | |
f02831be EG |
683 | |
684 | iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue, | |
4cf677fd EG |
685 | trans_pcie->cmd_fifo, |
686 | trans_pcie->cmd_q_wdg_timeout); | |
f02831be EG |
687 | |
688 | /* Activate all Tx DMA/FIFO channels */ | |
680073b7 | 689 | iwl_scd_activate_fifos(trans); |
f02831be EG |
690 | |
691 | /* Enable DMA channel */ | |
692 | for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++) | |
693 | iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan), | |
694 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
695 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); | |
696 | ||
697 | /* Update FH chicken bits */ | |
698 | reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG); | |
699 | iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG, | |
700 | reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); | |
701 | ||
702 | /* Enable L1-Active */ | |
3073d8c0 EH |
703 | if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) |
704 | iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
705 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
f02831be EG |
706 | } |
707 | ||
ddaf5a5b JB |
708 | void iwl_trans_pcie_tx_reset(struct iwl_trans *trans) |
709 | { | |
710 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
711 | int txq_id; | |
712 | ||
713 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
714 | txq_id++) { | |
715 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
716 | ||
717 | iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id), | |
718 | txq->q.dma_addr >> 8); | |
719 | iwl_pcie_txq_unmap(trans, txq_id); | |
720 | txq->q.read_ptr = 0; | |
721 | txq->q.write_ptr = 0; | |
722 | } | |
723 | ||
724 | /* Tell NIC where to find the "keep warm" buffer */ | |
725 | iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, | |
726 | trans_pcie->kw.dma >> 4); | |
727 | ||
cd8f4384 EG |
728 | /* |
729 | * Send 0 as the scd_base_addr since the device may have be reset | |
730 | * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will | |
731 | * contain garbage. | |
732 | */ | |
733 | iwl_pcie_tx_start(trans, 0); | |
ddaf5a5b JB |
734 | } |
735 | ||
36277234 EG |
736 | static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans) |
737 | { | |
738 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
739 | unsigned long flags; | |
740 | int ch, ret; | |
741 | u32 mask = 0; | |
742 | ||
743 | spin_lock(&trans_pcie->irq_lock); | |
744 | ||
745 | if (!iwl_trans_grab_nic_access(trans, false, &flags)) | |
746 | goto out; | |
747 | ||
748 | /* Stop each Tx DMA channel */ | |
749 | for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { | |
750 | iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); | |
751 | mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch); | |
752 | } | |
753 | ||
754 | /* Wait for DMA channels to be idle */ | |
755 | ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000); | |
756 | if (ret < 0) | |
757 | IWL_ERR(trans, | |
758 | "Failing on timeout while stopping DMA channel %d [0x%08x]\n", | |
759 | ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG)); | |
760 | ||
761 | iwl_trans_release_nic_access(trans, &flags); | |
762 | ||
763 | out: | |
764 | spin_unlock(&trans_pcie->irq_lock); | |
765 | } | |
766 | ||
f02831be EG |
767 | /* |
768 | * iwl_pcie_tx_stop - Stop all Tx DMA channels | |
769 | */ | |
770 | int iwl_pcie_tx_stop(struct iwl_trans *trans) | |
771 | { | |
772 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
36277234 | 773 | int txq_id; |
f02831be EG |
774 | |
775 | /* Turn off all Tx DMA fifos */ | |
680073b7 | 776 | iwl_scd_deactivate_fifos(trans); |
f02831be | 777 | |
36277234 EG |
778 | /* Turn off all Tx DMA channels */ |
779 | iwl_pcie_tx_stop_fh(trans); | |
f02831be | 780 | |
fba1c627 EG |
781 | /* |
782 | * This function can be called before the op_mode disabled the | |
783 | * queues. This happens when we have an rfkill interrupt. | |
784 | * Since we stop Tx altogether - mark the queues as stopped. | |
785 | */ | |
786 | memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); | |
787 | memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); | |
788 | ||
789 | /* This can happen: start_hw, stop_device */ | |
790 | if (!trans_pcie->txq) | |
f02831be | 791 | return 0; |
f02831be EG |
792 | |
793 | /* Unmap DMA from host system and free skb's */ | |
794 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
795 | txq_id++) | |
796 | iwl_pcie_txq_unmap(trans, txq_id); | |
797 | ||
798 | return 0; | |
799 | } | |
800 | ||
801 | /* | |
802 | * iwl_trans_tx_free - Free TXQ Context | |
803 | * | |
804 | * Destroy all TX DMA queues and structures | |
805 | */ | |
806 | void iwl_pcie_tx_free(struct iwl_trans *trans) | |
807 | { | |
808 | int txq_id; | |
809 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
810 | ||
811 | /* Tx queues */ | |
812 | if (trans_pcie->txq) { | |
813 | for (txq_id = 0; | |
814 | txq_id < trans->cfg->base_params->num_of_queues; txq_id++) | |
815 | iwl_pcie_txq_free(trans, txq_id); | |
816 | } | |
817 | ||
818 | kfree(trans_pcie->txq); | |
819 | trans_pcie->txq = NULL; | |
820 | ||
821 | iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw); | |
822 | ||
823 | iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls); | |
824 | } | |
825 | ||
826 | /* | |
827 | * iwl_pcie_tx_alloc - allocate TX context | |
828 | * Allocate all Tx DMA structures and initialize them | |
829 | */ | |
830 | static int iwl_pcie_tx_alloc(struct iwl_trans *trans) | |
831 | { | |
832 | int ret; | |
833 | int txq_id, slots_num; | |
834 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
835 | ||
836 | u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues * | |
837 | sizeof(struct iwlagn_scd_bc_tbl); | |
838 | ||
839 | /*It is not allowed to alloc twice, so warn when this happens. | |
840 | * We cannot rely on the previous allocation, so free and fail */ | |
841 | if (WARN_ON(trans_pcie->txq)) { | |
842 | ret = -EINVAL; | |
843 | goto error; | |
844 | } | |
845 | ||
846 | ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls, | |
847 | scd_bc_tbls_size); | |
848 | if (ret) { | |
849 | IWL_ERR(trans, "Scheduler BC Table allocation failed\n"); | |
850 | goto error; | |
851 | } | |
852 | ||
853 | /* Alloc keep-warm buffer */ | |
854 | ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE); | |
855 | if (ret) { | |
856 | IWL_ERR(trans, "Keep Warm allocation failed\n"); | |
857 | goto error; | |
858 | } | |
859 | ||
860 | trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues, | |
861 | sizeof(struct iwl_txq), GFP_KERNEL); | |
862 | if (!trans_pcie->txq) { | |
863 | IWL_ERR(trans, "Not enough memory for txq\n"); | |
2ab9ba0f | 864 | ret = -ENOMEM; |
f02831be EG |
865 | goto error; |
866 | } | |
867 | ||
868 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
869 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
870 | txq_id++) { | |
871 | slots_num = (txq_id == trans_pcie->cmd_queue) ? | |
872 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
873 | ret = iwl_pcie_txq_alloc(trans, &trans_pcie->txq[txq_id], | |
874 | slots_num, txq_id); | |
875 | if (ret) { | |
876 | IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id); | |
877 | goto error; | |
878 | } | |
879 | } | |
880 | ||
881 | return 0; | |
882 | ||
883 | error: | |
884 | iwl_pcie_tx_free(trans); | |
885 | ||
886 | return ret; | |
887 | } | |
888 | int iwl_pcie_tx_init(struct iwl_trans *trans) | |
889 | { | |
890 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
891 | int ret; | |
892 | int txq_id, slots_num; | |
f02831be EG |
893 | bool alloc = false; |
894 | ||
895 | if (!trans_pcie->txq) { | |
896 | ret = iwl_pcie_tx_alloc(trans); | |
897 | if (ret) | |
898 | goto error; | |
899 | alloc = true; | |
900 | } | |
901 | ||
7b70bd63 | 902 | spin_lock(&trans_pcie->irq_lock); |
f02831be EG |
903 | |
904 | /* Turn off all Tx DMA fifos */ | |
680073b7 | 905 | iwl_scd_deactivate_fifos(trans); |
f02831be EG |
906 | |
907 | /* Tell NIC where to find the "keep warm" buffer */ | |
908 | iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, | |
909 | trans_pcie->kw.dma >> 4); | |
910 | ||
7b70bd63 | 911 | spin_unlock(&trans_pcie->irq_lock); |
f02831be EG |
912 | |
913 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
914 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
915 | txq_id++) { | |
916 | slots_num = (txq_id == trans_pcie->cmd_queue) ? | |
917 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
918 | ret = iwl_pcie_txq_init(trans, &trans_pcie->txq[txq_id], | |
919 | slots_num, txq_id); | |
920 | if (ret) { | |
921 | IWL_ERR(trans, "Tx %d queue init failed\n", txq_id); | |
922 | goto error; | |
923 | } | |
924 | } | |
925 | ||
94ce9e5e | 926 | iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE); |
cb6bb128 EG |
927 | if (trans->cfg->base_params->num_of_queues > 20) |
928 | iwl_set_bits_prph(trans, SCD_GP_CTRL, | |
929 | SCD_GP_CTRL_ENABLE_31_QUEUES); | |
930 | ||
f02831be EG |
931 | return 0; |
932 | error: | |
933 | /*Upon error, free only if we allocated something */ | |
934 | if (alloc) | |
935 | iwl_pcie_tx_free(trans); | |
936 | return ret; | |
937 | } | |
938 | ||
4cf677fd | 939 | static inline void iwl_pcie_txq_progress(struct iwl_txq *txq) |
f02831be | 940 | { |
e0b8d405 EG |
941 | lockdep_assert_held(&txq->lock); |
942 | ||
4cf677fd | 943 | if (!txq->wd_timeout) |
f02831be EG |
944 | return; |
945 | ||
e0b8d405 EG |
946 | /* |
947 | * station is asleep and we send data - that must | |
948 | * be uAPSD or PS-Poll. Don't rearm the timer. | |
949 | */ | |
950 | if (txq->frozen) | |
951 | return; | |
952 | ||
f02831be EG |
953 | /* |
954 | * if empty delete timer, otherwise move timer forward | |
955 | * since we're making progress on this queue | |
956 | */ | |
957 | if (txq->q.read_ptr == txq->q.write_ptr) | |
958 | del_timer(&txq->stuck_timer); | |
959 | else | |
4cf677fd | 960 | mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout); |
f02831be EG |
961 | } |
962 | ||
963 | /* Frees buffers until index _not_ inclusive */ | |
f6d497cd EG |
964 | void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, |
965 | struct sk_buff_head *skbs) | |
f02831be EG |
966 | { |
967 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
968 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
83f32a4b | 969 | int tfd_num = ssn & (TFD_QUEUE_SIZE_MAX - 1); |
f02831be EG |
970 | struct iwl_queue *q = &txq->q; |
971 | int last_to_free; | |
f02831be EG |
972 | |
973 | /* This function is not meant to release cmd queue*/ | |
974 | if (WARN_ON(txq_id == trans_pcie->cmd_queue)) | |
f6d497cd | 975 | return; |
214d14d4 | 976 | |
2bfb5092 | 977 | spin_lock_bh(&txq->lock); |
f6d497cd | 978 | |
b967613d EG |
979 | if (!txq->active) { |
980 | IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n", | |
981 | txq_id, ssn); | |
982 | goto out; | |
983 | } | |
984 | ||
f6d497cd EG |
985 | if (txq->q.read_ptr == tfd_num) |
986 | goto out; | |
987 | ||
988 | IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n", | |
989 | txq_id, txq->q.read_ptr, tfd_num, ssn); | |
214d14d4 | 990 | |
f02831be EG |
991 | /*Since we free until index _not_ inclusive, the one before index is |
992 | * the last we will free. This one must be used */ | |
83f32a4b | 993 | last_to_free = iwl_queue_dec_wrap(tfd_num); |
f02831be | 994 | |
6ca6ebc1 | 995 | if (!iwl_queue_used(q, last_to_free)) { |
f02831be EG |
996 | IWL_ERR(trans, |
997 | "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n", | |
83f32a4b | 998 | __func__, txq_id, last_to_free, TFD_QUEUE_SIZE_MAX, |
f02831be | 999 | q->write_ptr, q->read_ptr); |
f6d497cd | 1000 | goto out; |
214d14d4 JB |
1001 | } |
1002 | ||
f02831be | 1003 | if (WARN_ON(!skb_queue_empty(skbs))) |
f6d497cd | 1004 | goto out; |
214d14d4 | 1005 | |
f02831be | 1006 | for (; |
f6d497cd | 1007 | q->read_ptr != tfd_num; |
83f32a4b | 1008 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) { |
214d14d4 | 1009 | |
f02831be EG |
1010 | if (WARN_ON_ONCE(txq->entries[txq->q.read_ptr].skb == NULL)) |
1011 | continue; | |
214d14d4 | 1012 | |
f02831be | 1013 | __skb_queue_tail(skbs, txq->entries[txq->q.read_ptr].skb); |
214d14d4 | 1014 | |
f02831be | 1015 | txq->entries[txq->q.read_ptr].skb = NULL; |
fd4abac5 | 1016 | |
f02831be | 1017 | iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq); |
fd4abac5 | 1018 | |
98891754 | 1019 | iwl_pcie_txq_free_tfd(trans, txq); |
f02831be | 1020 | } |
fd4abac5 | 1021 | |
4cf677fd | 1022 | iwl_pcie_txq_progress(txq); |
f02831be | 1023 | |
f6d497cd EG |
1024 | if (iwl_queue_space(&txq->q) > txq->q.low_mark) |
1025 | iwl_wake_queue(trans, txq); | |
7616f334 EP |
1026 | |
1027 | if (q->read_ptr == q->write_ptr) { | |
1028 | IWL_DEBUG_RPM(trans, "Q %d - last tx reclaimed\n", q->id); | |
1029 | iwl_trans_pcie_unref(trans); | |
1030 | } | |
1031 | ||
f6d497cd | 1032 | out: |
2bfb5092 | 1033 | spin_unlock_bh(&txq->lock); |
1053d35f RR |
1034 | } |
1035 | ||
7616f334 EP |
1036 | static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans, |
1037 | const struct iwl_host_cmd *cmd) | |
804d4c5a EP |
1038 | { |
1039 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1040 | int ret; | |
1041 | ||
1042 | lockdep_assert_held(&trans_pcie->reg_lock); | |
1043 | ||
7616f334 EP |
1044 | if (!(cmd->flags & CMD_SEND_IN_IDLE) && |
1045 | !trans_pcie->ref_cmd_in_flight) { | |
1046 | trans_pcie->ref_cmd_in_flight = true; | |
1047 | IWL_DEBUG_RPM(trans, "set ref_cmd_in_flight - ref\n"); | |
1048 | iwl_trans_pcie_ref(trans); | |
1049 | } | |
1050 | ||
804d4c5a EP |
1051 | /* |
1052 | * wake up the NIC to make sure that the firmware will see the host | |
1053 | * command - we will let the NIC sleep once all the host commands | |
1054 | * returned. This needs to be done only on NICs that have | |
1055 | * apmg_wake_up_wa set. | |
1056 | */ | |
fc8a350d IP |
1057 | if (trans->cfg->base_params->apmg_wake_up_wa && |
1058 | !trans_pcie->cmd_hold_nic_awake) { | |
804d4c5a EP |
1059 | __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, |
1060 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
804d4c5a EP |
1061 | |
1062 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
1063 | CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, | |
1064 | (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | | |
1065 | CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), | |
1066 | 15000); | |
1067 | if (ret < 0) { | |
1068 | __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, | |
1069 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
804d4c5a EP |
1070 | IWL_ERR(trans, "Failed to wake NIC for hcmd\n"); |
1071 | return -EIO; | |
1072 | } | |
fc8a350d | 1073 | trans_pcie->cmd_hold_nic_awake = true; |
804d4c5a EP |
1074 | } |
1075 | ||
1076 | return 0; | |
1077 | } | |
1078 | ||
1079 | static int iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans) | |
1080 | { | |
1081 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1082 | ||
1083 | lockdep_assert_held(&trans_pcie->reg_lock); | |
1084 | ||
7616f334 EP |
1085 | if (trans_pcie->ref_cmd_in_flight) { |
1086 | trans_pcie->ref_cmd_in_flight = false; | |
1087 | IWL_DEBUG_RPM(trans, "clear ref_cmd_in_flight - unref\n"); | |
1088 | iwl_trans_pcie_unref(trans); | |
1089 | } | |
1090 | ||
fc8a350d IP |
1091 | if (trans->cfg->base_params->apmg_wake_up_wa) { |
1092 | if (WARN_ON(!trans_pcie->cmd_hold_nic_awake)) | |
1093 | return 0; | |
804d4c5a | 1094 | |
fc8a350d | 1095 | trans_pcie->cmd_hold_nic_awake = false; |
804d4c5a | 1096 | __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, |
fc8a350d IP |
1097 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
1098 | } | |
804d4c5a EP |
1099 | return 0; |
1100 | } | |
1101 | ||
f02831be EG |
1102 | /* |
1103 | * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd | |
1104 | * | |
1105 | * When FW advances 'R' index, all entries between old and new 'R' index | |
1106 | * need to be reclaimed. As result, some free space forms. If there is | |
1107 | * enough free space (> low mark), wake the stack that feeds us. | |
1108 | */ | |
1109 | static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx) | |
48d42c42 | 1110 | { |
f02831be EG |
1111 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1112 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
1113 | struct iwl_queue *q = &txq->q; | |
b9439491 | 1114 | unsigned long flags; |
f02831be | 1115 | int nfreed = 0; |
48d42c42 | 1116 | |
f02831be | 1117 | lockdep_assert_held(&txq->lock); |
48d42c42 | 1118 | |
83f32a4b | 1119 | if ((idx >= TFD_QUEUE_SIZE_MAX) || (!iwl_queue_used(q, idx))) { |
f02831be EG |
1120 | IWL_ERR(trans, |
1121 | "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n", | |
83f32a4b | 1122 | __func__, txq_id, idx, TFD_QUEUE_SIZE_MAX, |
f02831be EG |
1123 | q->write_ptr, q->read_ptr); |
1124 | return; | |
1125 | } | |
48d42c42 | 1126 | |
83f32a4b JB |
1127 | for (idx = iwl_queue_inc_wrap(idx); q->read_ptr != idx; |
1128 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) { | |
48d42c42 | 1129 | |
f02831be EG |
1130 | if (nfreed++ > 0) { |
1131 | IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", | |
1132 | idx, q->write_ptr, q->read_ptr); | |
4c9706dc | 1133 | iwl_force_nmi(trans); |
f02831be EG |
1134 | } |
1135 | } | |
1136 | ||
804d4c5a | 1137 | if (q->read_ptr == q->write_ptr) { |
b9439491 | 1138 | spin_lock_irqsave(&trans_pcie->reg_lock, flags); |
804d4c5a | 1139 | iwl_pcie_clear_cmd_in_flight(trans); |
b9439491 EG |
1140 | spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); |
1141 | } | |
1142 | ||
4cf677fd | 1143 | iwl_pcie_txq_progress(txq); |
48d42c42 EG |
1144 | } |
1145 | ||
f02831be | 1146 | static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid, |
1ce8658c | 1147 | u16 txq_id) |
48d42c42 | 1148 | { |
20d3b647 | 1149 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
48d42c42 EG |
1150 | u32 tbl_dw_addr; |
1151 | u32 tbl_dw; | |
1152 | u16 scd_q2ratid; | |
1153 | ||
1154 | scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; | |
1155 | ||
105183b1 | 1156 | tbl_dw_addr = trans_pcie->scd_base_addr + |
48d42c42 EG |
1157 | SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); |
1158 | ||
4fd442db | 1159 | tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr); |
48d42c42 EG |
1160 | |
1161 | if (txq_id & 0x1) | |
1162 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); | |
1163 | else | |
1164 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); | |
1165 | ||
4fd442db | 1166 | iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw); |
48d42c42 EG |
1167 | |
1168 | return 0; | |
1169 | } | |
1170 | ||
bd5f6a34 EG |
1171 | /* Receiver address (actually, Rx station's index into station table), |
1172 | * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */ | |
1173 | #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid)) | |
1174 | ||
fea7795f | 1175 | void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn, |
4cf677fd EG |
1176 | const struct iwl_trans_txq_scd_cfg *cfg, |
1177 | unsigned int wdg_timeout) | |
48d42c42 | 1178 | { |
9eae88fa | 1179 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
4cf677fd | 1180 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; |
d4578ea8 | 1181 | int fifo = -1; |
4beaf6c2 | 1182 | |
9eae88fa JB |
1183 | if (test_and_set_bit(txq_id, trans_pcie->queue_used)) |
1184 | WARN_ONCE(1, "queue %d already used - expect issues", txq_id); | |
48d42c42 | 1185 | |
4cf677fd EG |
1186 | txq->wd_timeout = msecs_to_jiffies(wdg_timeout); |
1187 | ||
d4578ea8 JB |
1188 | if (cfg) { |
1189 | fifo = cfg->fifo; | |
48d42c42 | 1190 | |
002a9e26 | 1191 | /* Disable the scheduler prior configuring the cmd queue */ |
3a736bcb EG |
1192 | if (txq_id == trans_pcie->cmd_queue && |
1193 | trans_pcie->scd_set_active) | |
002a9e26 AA |
1194 | iwl_scd_enable_set_active(trans, 0); |
1195 | ||
d4578ea8 JB |
1196 | /* Stop this Tx queue before configuring it */ |
1197 | iwl_scd_txq_set_inactive(trans, txq_id); | |
4beaf6c2 | 1198 | |
d4578ea8 JB |
1199 | /* Set this queue as a chain-building queue unless it is CMD */ |
1200 | if (txq_id != trans_pcie->cmd_queue) | |
1201 | iwl_scd_txq_set_chain(trans, txq_id); | |
48d42c42 | 1202 | |
64ba8930 | 1203 | if (cfg->aggregate) { |
d4578ea8 | 1204 | u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid); |
48d42c42 | 1205 | |
d4578ea8 JB |
1206 | /* Map receiver-address / traffic-ID to this queue */ |
1207 | iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id); | |
f4772520 | 1208 | |
d4578ea8 JB |
1209 | /* enable aggregations for the queue */ |
1210 | iwl_scd_txq_enable_agg(trans, txq_id); | |
4cf677fd | 1211 | txq->ampdu = true; |
d4578ea8 JB |
1212 | } else { |
1213 | /* | |
1214 | * disable aggregations for the queue, this will also | |
1215 | * make the ra_tid mapping configuration irrelevant | |
1216 | * since it is now a non-AGG queue. | |
1217 | */ | |
1218 | iwl_scd_txq_disable_agg(trans, txq_id); | |
1219 | ||
4cf677fd | 1220 | ssn = txq->q.read_ptr; |
d4578ea8 | 1221 | } |
4beaf6c2 | 1222 | } |
48d42c42 EG |
1223 | |
1224 | /* Place first TFD at index corresponding to start sequence number. | |
1225 | * Assumes that ssn_idx is valid (!= 0xFFF) */ | |
4cf677fd EG |
1226 | txq->q.read_ptr = (ssn & 0xff); |
1227 | txq->q.write_ptr = (ssn & 0xff); | |
0294d9ee EG |
1228 | iwl_write_direct32(trans, HBUS_TARG_WRPTR, |
1229 | (ssn & 0xff) | (txq_id << 8)); | |
1ce8658c | 1230 | |
d4578ea8 JB |
1231 | if (cfg) { |
1232 | u8 frame_limit = cfg->frame_limit; | |
48d42c42 | 1233 | |
d4578ea8 JB |
1234 | iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn); |
1235 | ||
1236 | /* Set up Tx window size and frame limit for this queue */ | |
1237 | iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr + | |
1238 | SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0); | |
1239 | iwl_trans_write_mem32(trans, | |
1240 | trans_pcie->scd_base_addr + | |
9eae88fa JB |
1241 | SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), |
1242 | ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
d4578ea8 | 1243 | SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | |
9eae88fa | 1244 | ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & |
d4578ea8 JB |
1245 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); |
1246 | ||
1247 | /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */ | |
1248 | iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id), | |
1249 | (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) | | |
1250 | (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) | | |
1251 | (1 << SCD_QUEUE_STTS_REG_POS_WSL) | | |
1252 | SCD_QUEUE_STTS_REG_MSK); | |
002a9e26 AA |
1253 | |
1254 | /* enable the scheduler for this queue (only) */ | |
3a736bcb EG |
1255 | if (txq_id == trans_pcie->cmd_queue && |
1256 | trans_pcie->scd_set_active) | |
002a9e26 | 1257 | iwl_scd_enable_set_active(trans, BIT(txq_id)); |
0294d9ee EG |
1258 | |
1259 | IWL_DEBUG_TX_QUEUES(trans, | |
1260 | "Activate queue %d on FIFO %d WrPtr: %d\n", | |
1261 | txq_id, fifo, ssn & 0xff); | |
1262 | } else { | |
1263 | IWL_DEBUG_TX_QUEUES(trans, | |
1264 | "Activate queue %d WrPtr: %d\n", | |
1265 | txq_id, ssn & 0xff); | |
d4578ea8 JB |
1266 | } |
1267 | ||
4cf677fd | 1268 | txq->active = true; |
4beaf6c2 EG |
1269 | } |
1270 | ||
d4578ea8 JB |
1271 | void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id, |
1272 | bool configure_scd) | |
288712a6 | 1273 | { |
8ad71bef | 1274 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
986ea6c9 EG |
1275 | u32 stts_addr = trans_pcie->scd_base_addr + |
1276 | SCD_TX_STTS_QUEUE_OFFSET(txq_id); | |
1277 | static const u32 zero_val[4] = {}; | |
288712a6 | 1278 | |
e0b8d405 EG |
1279 | trans_pcie->txq[txq_id].frozen_expiry_remainder = 0; |
1280 | trans_pcie->txq[txq_id].frozen = false; | |
1281 | ||
fba1c627 EG |
1282 | /* |
1283 | * Upon HW Rfkill - we stop the device, and then stop the queues | |
1284 | * in the op_mode. Just for the sake of the simplicity of the op_mode, | |
1285 | * allow the op_mode to call txq_disable after it already called | |
1286 | * stop_device. | |
1287 | */ | |
9eae88fa | 1288 | if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) { |
fba1c627 EG |
1289 | WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status), |
1290 | "queue %d not used", txq_id); | |
9eae88fa | 1291 | return; |
48d42c42 EG |
1292 | } |
1293 | ||
d4578ea8 JB |
1294 | if (configure_scd) { |
1295 | iwl_scd_txq_set_inactive(trans, txq_id); | |
ac928f8d | 1296 | |
d4578ea8 JB |
1297 | iwl_trans_write_mem(trans, stts_addr, (void *)zero_val, |
1298 | ARRAY_SIZE(zero_val)); | |
1299 | } | |
986ea6c9 | 1300 | |
990aa6d7 | 1301 | iwl_pcie_txq_unmap(trans, txq_id); |
68972c46 | 1302 | trans_pcie->txq[txq_id].ampdu = false; |
6c3fd3f0 | 1303 | |
1ce8658c | 1304 | IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id); |
48d42c42 EG |
1305 | } |
1306 | ||
fd4abac5 TW |
1307 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ |
1308 | ||
990aa6d7 | 1309 | /* |
f02831be | 1310 | * iwl_pcie_enqueue_hcmd - enqueue a uCode command |
fd4abac5 | 1311 | * @priv: device private data point |
e89044d7 | 1312 | * @cmd: a pointer to the ucode command structure |
fd4abac5 | 1313 | * |
e89044d7 EP |
1314 | * The function returns < 0 values to indicate the operation |
1315 | * failed. On success, it returns the index (>= 0) of command in the | |
fd4abac5 TW |
1316 | * command queue. |
1317 | */ | |
f02831be EG |
1318 | static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans, |
1319 | struct iwl_host_cmd *cmd) | |
fd4abac5 | 1320 | { |
8ad71bef | 1321 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1322 | struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
fd4abac5 | 1323 | struct iwl_queue *q = &txq->q; |
c2acea8e JB |
1324 | struct iwl_device_cmd *out_cmd; |
1325 | struct iwl_cmd_meta *out_meta; | |
b9439491 | 1326 | unsigned long flags; |
f4feb8ac | 1327 | void *dup_buf = NULL; |
fd4abac5 | 1328 | dma_addr_t phys_addr; |
f4feb8ac | 1329 | int idx; |
38c0f334 | 1330 | u16 copy_size, cmd_size, scratch_size; |
4ce7cc2b | 1331 | bool had_nocopy = false; |
ab02165c | 1332 | u8 group_id = iwl_cmd_groupid(cmd->id); |
b9439491 | 1333 | int i, ret; |
96791422 | 1334 | u32 cmd_pos; |
1afbfb60 JB |
1335 | const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD]; |
1336 | u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD]; | |
fd4abac5 | 1337 | |
88742c9e JB |
1338 | if (WARN(!trans_pcie->wide_cmd_header && |
1339 | group_id > IWL_ALWAYS_LONG_GROUP, | |
ab02165c AE |
1340 | "unsupported wide command %#x\n", cmd->id)) |
1341 | return -EINVAL; | |
1342 | ||
1343 | if (group_id != 0) { | |
1344 | copy_size = sizeof(struct iwl_cmd_header_wide); | |
1345 | cmd_size = sizeof(struct iwl_cmd_header_wide); | |
1346 | } else { | |
1347 | copy_size = sizeof(struct iwl_cmd_header); | |
1348 | cmd_size = sizeof(struct iwl_cmd_header); | |
1349 | } | |
4ce7cc2b JB |
1350 | |
1351 | /* need one for the header if the first is NOCOPY */ | |
1afbfb60 | 1352 | BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1); |
4ce7cc2b | 1353 | |
1afbfb60 | 1354 | for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { |
8a964f44 JB |
1355 | cmddata[i] = cmd->data[i]; |
1356 | cmdlen[i] = cmd->len[i]; | |
1357 | ||
4ce7cc2b JB |
1358 | if (!cmd->len[i]) |
1359 | continue; | |
8a964f44 | 1360 | |
38c0f334 JB |
1361 | /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */ |
1362 | if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) { | |
1363 | int copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size; | |
8a964f44 JB |
1364 | |
1365 | if (copy > cmdlen[i]) | |
1366 | copy = cmdlen[i]; | |
1367 | cmdlen[i] -= copy; | |
1368 | cmddata[i] += copy; | |
1369 | copy_size += copy; | |
1370 | } | |
1371 | ||
4ce7cc2b JB |
1372 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { |
1373 | had_nocopy = true; | |
f4feb8ac JB |
1374 | if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) { |
1375 | idx = -EINVAL; | |
1376 | goto free_dup_buf; | |
1377 | } | |
1378 | } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) { | |
1379 | /* | |
1380 | * This is also a chunk that isn't copied | |
1381 | * to the static buffer so set had_nocopy. | |
1382 | */ | |
1383 | had_nocopy = true; | |
1384 | ||
1385 | /* only allowed once */ | |
1386 | if (WARN_ON(dup_buf)) { | |
1387 | idx = -EINVAL; | |
1388 | goto free_dup_buf; | |
1389 | } | |
1390 | ||
8a964f44 | 1391 | dup_buf = kmemdup(cmddata[i], cmdlen[i], |
f4feb8ac JB |
1392 | GFP_ATOMIC); |
1393 | if (!dup_buf) | |
1394 | return -ENOMEM; | |
4ce7cc2b JB |
1395 | } else { |
1396 | /* NOCOPY must not be followed by normal! */ | |
f4feb8ac JB |
1397 | if (WARN_ON(had_nocopy)) { |
1398 | idx = -EINVAL; | |
1399 | goto free_dup_buf; | |
1400 | } | |
8a964f44 | 1401 | copy_size += cmdlen[i]; |
4ce7cc2b JB |
1402 | } |
1403 | cmd_size += cmd->len[i]; | |
1404 | } | |
fd4abac5 | 1405 | |
3e41ace5 JB |
1406 | /* |
1407 | * If any of the command structures end up being larger than | |
4ce7cc2b JB |
1408 | * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically |
1409 | * allocated into separate TFDs, then we will need to | |
1410 | * increase the size of the buffers. | |
3e41ace5 | 1411 | */ |
2a79e45e JB |
1412 | if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE, |
1413 | "Command %s (%#x) is too large (%d bytes)\n", | |
990aa6d7 | 1414 | get_cmd_string(trans_pcie, cmd->id), cmd->id, copy_size)) { |
f4feb8ac JB |
1415 | idx = -EINVAL; |
1416 | goto free_dup_buf; | |
1417 | } | |
fd4abac5 | 1418 | |
015c15e1 | 1419 | spin_lock_bh(&txq->lock); |
3598e177 | 1420 | |
c2acea8e | 1421 | if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { |
015c15e1 | 1422 | spin_unlock_bh(&txq->lock); |
3598e177 | 1423 | |
6d8f6eeb | 1424 | IWL_ERR(trans, "No space in command queue\n"); |
0e781842 | 1425 | iwl_op_mode_cmd_queue_full(trans->op_mode); |
f4feb8ac JB |
1426 | idx = -ENOSPC; |
1427 | goto free_dup_buf; | |
fd4abac5 TW |
1428 | } |
1429 | ||
4ce7cc2b | 1430 | idx = get_cmd_index(q, q->write_ptr); |
bf8440e6 JB |
1431 | out_cmd = txq->entries[idx].cmd; |
1432 | out_meta = &txq->entries[idx].meta; | |
c2acea8e | 1433 | |
8ce73f3a | 1434 | memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ |
c2acea8e JB |
1435 | if (cmd->flags & CMD_WANT_SKB) |
1436 | out_meta->source = cmd; | |
fd4abac5 | 1437 | |
4ce7cc2b | 1438 | /* set up the header */ |
ab02165c AE |
1439 | if (group_id != 0) { |
1440 | out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id); | |
1441 | out_cmd->hdr_wide.group_id = group_id; | |
1442 | out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id); | |
1443 | out_cmd->hdr_wide.length = | |
1444 | cpu_to_le16(cmd_size - | |
1445 | sizeof(struct iwl_cmd_header_wide)); | |
1446 | out_cmd->hdr_wide.reserved = 0; | |
1447 | out_cmd->hdr_wide.sequence = | |
1448 | cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | | |
1449 | INDEX_TO_SEQ(q->write_ptr)); | |
1450 | ||
1451 | cmd_pos = sizeof(struct iwl_cmd_header_wide); | |
1452 | copy_size = sizeof(struct iwl_cmd_header_wide); | |
1453 | } else { | |
1454 | out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id); | |
1455 | out_cmd->hdr.sequence = | |
1456 | cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | | |
1457 | INDEX_TO_SEQ(q->write_ptr)); | |
1458 | out_cmd->hdr.group_id = 0; | |
1459 | ||
1460 | cmd_pos = sizeof(struct iwl_cmd_header); | |
1461 | copy_size = sizeof(struct iwl_cmd_header); | |
1462 | } | |
4ce7cc2b JB |
1463 | |
1464 | /* and copy the data that needs to be copied */ | |
1afbfb60 | 1465 | for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { |
4d075007 | 1466 | int copy; |
8a964f44 | 1467 | |
cc904c71 | 1468 | if (!cmd->len[i]) |
4ce7cc2b | 1469 | continue; |
8a964f44 | 1470 | |
8a964f44 JB |
1471 | /* copy everything if not nocopy/dup */ |
1472 | if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | | |
4d075007 | 1473 | IWL_HCMD_DFL_DUP))) { |
8a964f44 JB |
1474 | copy = cmd->len[i]; |
1475 | ||
8a964f44 JB |
1476 | memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); |
1477 | cmd_pos += copy; | |
1478 | copy_size += copy; | |
4d075007 JB |
1479 | continue; |
1480 | } | |
1481 | ||
1482 | /* | |
1483 | * Otherwise we need at least IWL_HCMD_SCRATCHBUF_SIZE copied | |
1484 | * in total (for the scratchbuf handling), but copy up to what | |
1485 | * we can fit into the payload for debug dump purposes. | |
1486 | */ | |
1487 | copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]); | |
1488 | ||
1489 | memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); | |
1490 | cmd_pos += copy; | |
1491 | ||
1492 | /* However, treat copy_size the proper way, we need it below */ | |
1493 | if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) { | |
1494 | copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size; | |
1495 | ||
1496 | if (copy > cmd->len[i]) | |
1497 | copy = cmd->len[i]; | |
1498 | copy_size += copy; | |
8a964f44 | 1499 | } |
96791422 EG |
1500 | } |
1501 | ||
d9fb6465 | 1502 | IWL_DEBUG_HC(trans, |
ab02165c | 1503 | "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n", |
990aa6d7 | 1504 | get_cmd_string(trans_pcie, out_cmd->hdr.cmd), |
ab02165c AE |
1505 | group_id, out_cmd->hdr.cmd, |
1506 | le16_to_cpu(out_cmd->hdr.sequence), | |
20d3b647 | 1507 | cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue); |
4ce7cc2b | 1508 | |
38c0f334 JB |
1509 | /* start the TFD with the scratchbuf */ |
1510 | scratch_size = min_t(int, copy_size, IWL_HCMD_SCRATCHBUF_SIZE); | |
1511 | memcpy(&txq->scratchbufs[q->write_ptr], &out_cmd->hdr, scratch_size); | |
1512 | iwl_pcie_txq_build_tfd(trans, txq, | |
1513 | iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr), | |
6d6e68f8 | 1514 | scratch_size, true); |
38c0f334 JB |
1515 | |
1516 | /* map first command fragment, if any remains */ | |
1517 | if (copy_size > scratch_size) { | |
1518 | phys_addr = dma_map_single(trans->dev, | |
1519 | ((u8 *)&out_cmd->hdr) + scratch_size, | |
1520 | copy_size - scratch_size, | |
1521 | DMA_TO_DEVICE); | |
1522 | if (dma_mapping_error(trans->dev, phys_addr)) { | |
1523 | iwl_pcie_tfd_unmap(trans, out_meta, | |
1524 | &txq->tfds[q->write_ptr]); | |
1525 | idx = -ENOMEM; | |
1526 | goto out; | |
1527 | } | |
8a964f44 | 1528 | |
38c0f334 | 1529 | iwl_pcie_txq_build_tfd(trans, txq, phys_addr, |
6d6e68f8 | 1530 | copy_size - scratch_size, false); |
2c46f72e JB |
1531 | } |
1532 | ||
8a964f44 | 1533 | /* map the remaining (adjusted) nocopy/dup fragments */ |
1afbfb60 | 1534 | for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { |
8a964f44 | 1535 | const void *data = cmddata[i]; |
f4feb8ac | 1536 | |
8a964f44 | 1537 | if (!cmdlen[i]) |
4ce7cc2b | 1538 | continue; |
f4feb8ac JB |
1539 | if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | |
1540 | IWL_HCMD_DFL_DUP))) | |
4ce7cc2b | 1541 | continue; |
f4feb8ac JB |
1542 | if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) |
1543 | data = dup_buf; | |
1544 | phys_addr = dma_map_single(trans->dev, (void *)data, | |
98891754 | 1545 | cmdlen[i], DMA_TO_DEVICE); |
1042db2a | 1546 | if (dma_mapping_error(trans->dev, phys_addr)) { |
f02831be | 1547 | iwl_pcie_tfd_unmap(trans, out_meta, |
98891754 | 1548 | &txq->tfds[q->write_ptr]); |
4ce7cc2b JB |
1549 | idx = -ENOMEM; |
1550 | goto out; | |
1551 | } | |
1552 | ||
6d6e68f8 | 1553 | iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false); |
4ce7cc2b | 1554 | } |
df833b1d | 1555 | |
206eea78 JB |
1556 | BUILD_BUG_ON(IWL_NUM_OF_TBS + CMD_TB_BITMAP_POS > |
1557 | sizeof(out_meta->flags) * BITS_PER_BYTE); | |
afaf6b57 | 1558 | out_meta->flags = cmd->flags; |
f4feb8ac | 1559 | if (WARN_ON_ONCE(txq->entries[idx].free_buf)) |
5d4185ae | 1560 | kzfree(txq->entries[idx].free_buf); |
f4feb8ac | 1561 | txq->entries[idx].free_buf = dup_buf; |
2c46f72e | 1562 | |
ab02165c | 1563 | trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide); |
df833b1d | 1564 | |
7c5ba4a8 | 1565 | /* start timer if queue currently empty */ |
4cf677fd EG |
1566 | if (q->read_ptr == q->write_ptr && txq->wd_timeout) |
1567 | mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout); | |
7c5ba4a8 | 1568 | |
b9439491 | 1569 | spin_lock_irqsave(&trans_pcie->reg_lock, flags); |
7616f334 | 1570 | ret = iwl_pcie_set_cmd_in_flight(trans, cmd); |
804d4c5a EP |
1571 | if (ret < 0) { |
1572 | idx = ret; | |
1573 | spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); | |
1574 | goto out; | |
b9439491 EG |
1575 | } |
1576 | ||
fd4abac5 | 1577 | /* Increment and update queue's write index */ |
83f32a4b | 1578 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr); |
990aa6d7 | 1579 | iwl_pcie_txq_inc_wr_ptr(trans, txq); |
fd4abac5 | 1580 | |
b9439491 EG |
1581 | spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); |
1582 | ||
2c46f72e | 1583 | out: |
015c15e1 | 1584 | spin_unlock_bh(&txq->lock); |
f4feb8ac JB |
1585 | free_dup_buf: |
1586 | if (idx < 0) | |
1587 | kfree(dup_buf); | |
7bfedc59 | 1588 | return idx; |
fd4abac5 TW |
1589 | } |
1590 | ||
990aa6d7 EG |
1591 | /* |
1592 | * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them | |
17b88929 TW |
1593 | * @rxb: Rx buffer to reclaim |
1594 | * | |
1595 | * If an Rx buffer has an async callback associated with it the callback | |
1596 | * will be executed. The attached skb (if present) will only be freed | |
1597 | * if the callback returns 1 | |
1598 | */ | |
990aa6d7 | 1599 | void iwl_pcie_hcmd_complete(struct iwl_trans *trans, |
f7e6469f | 1600 | struct iwl_rx_cmd_buffer *rxb) |
17b88929 | 1601 | { |
2f301227 | 1602 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
17b88929 TW |
1603 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
1604 | int txq_id = SEQ_TO_QUEUE(sequence); | |
1605 | int index = SEQ_TO_INDEX(sequence); | |
17b88929 | 1606 | int cmd_index; |
c2acea8e JB |
1607 | struct iwl_device_cmd *cmd; |
1608 | struct iwl_cmd_meta *meta; | |
8ad71bef | 1609 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1610 | struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
17b88929 TW |
1611 | |
1612 | /* If a Tx command is being handled and it isn't in the actual | |
1613 | * command queue then there a command routing bug has been introduced | |
1614 | * in the queue management code. */ | |
c6f600fc | 1615 | if (WARN(txq_id != trans_pcie->cmd_queue, |
13bb9483 | 1616 | "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", |
20d3b647 JB |
1617 | txq_id, trans_pcie->cmd_queue, sequence, |
1618 | trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr, | |
1619 | trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) { | |
3e10caeb | 1620 | iwl_print_hex_error(trans, pkt, 32); |
55d6a3cd | 1621 | return; |
01ef9323 | 1622 | } |
17b88929 | 1623 | |
2bfb5092 | 1624 | spin_lock_bh(&txq->lock); |
015c15e1 | 1625 | |
4ce7cc2b | 1626 | cmd_index = get_cmd_index(&txq->q, index); |
bf8440e6 JB |
1627 | cmd = txq->entries[cmd_index].cmd; |
1628 | meta = &txq->entries[cmd_index].meta; | |
17b88929 | 1629 | |
98891754 | 1630 | iwl_pcie_tfd_unmap(trans, meta, &txq->tfds[index]); |
c33de625 | 1631 | |
17b88929 | 1632 | /* Input error checking is done when commands are added to queue. */ |
c2acea8e | 1633 | if (meta->flags & CMD_WANT_SKB) { |
48a2d66f | 1634 | struct page *p = rxb_steal_page(rxb); |
65b94a4a | 1635 | |
65b94a4a JB |
1636 | meta->source->resp_pkt = pkt; |
1637 | meta->source->_rx_page_addr = (unsigned long)page_address(p); | |
b2cf410c | 1638 | meta->source->_rx_page_order = trans_pcie->rx_page_order; |
247c61d6 | 1639 | } |
2624e96c | 1640 | |
f02831be | 1641 | iwl_pcie_cmdq_reclaim(trans, txq_id, index); |
17b88929 | 1642 | |
c2acea8e | 1643 | if (!(meta->flags & CMD_ASYNC)) { |
eb7ff77e | 1644 | if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) { |
05c89b91 WYG |
1645 | IWL_WARN(trans, |
1646 | "HCMD_ACTIVE already clear for command %s\n", | |
990aa6d7 | 1647 | get_cmd_string(trans_pcie, cmd->hdr.cmd)); |
05c89b91 | 1648 | } |
eb7ff77e | 1649 | clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); |
6d8f6eeb | 1650 | IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", |
990aa6d7 | 1651 | get_cmd_string(trans_pcie, cmd->hdr.cmd)); |
f946b529 | 1652 | wake_up(&trans_pcie->wait_command_queue); |
17b88929 | 1653 | } |
3598e177 | 1654 | |
dd487449 | 1655 | meta->flags = 0; |
3598e177 | 1656 | |
2bfb5092 | 1657 | spin_unlock_bh(&txq->lock); |
17b88929 | 1658 | } |
253a634c | 1659 | |
9439eac7 | 1660 | #define HOST_COMPLETE_TIMEOUT (2 * HZ) |
253a634c | 1661 | |
f02831be EG |
1662 | static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans, |
1663 | struct iwl_host_cmd *cmd) | |
253a634c | 1664 | { |
d9fb6465 | 1665 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
253a634c EG |
1666 | int ret; |
1667 | ||
1668 | /* An asynchronous command can not expect an SKB to be set. */ | |
1669 | if (WARN_ON(cmd->flags & CMD_WANT_SKB)) | |
1670 | return -EINVAL; | |
1671 | ||
f02831be | 1672 | ret = iwl_pcie_enqueue_hcmd(trans, cmd); |
253a634c | 1673 | if (ret < 0) { |
721c32f7 | 1674 | IWL_ERR(trans, |
b36b110c | 1675 | "Error sending %s: enqueue_hcmd failed: %d\n", |
990aa6d7 | 1676 | get_cmd_string(trans_pcie, cmd->id), ret); |
253a634c EG |
1677 | return ret; |
1678 | } | |
1679 | return 0; | |
1680 | } | |
1681 | ||
f02831be EG |
1682 | static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans, |
1683 | struct iwl_host_cmd *cmd) | |
253a634c | 1684 | { |
8ad71bef | 1685 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
253a634c EG |
1686 | int cmd_idx; |
1687 | int ret; | |
1688 | ||
6d8f6eeb | 1689 | IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", |
990aa6d7 | 1690 | get_cmd_string(trans_pcie, cmd->id)); |
253a634c | 1691 | |
eb7ff77e AN |
1692 | if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE, |
1693 | &trans->status), | |
bcbb8c9c JB |
1694 | "Command %s: a command is already active!\n", |
1695 | get_cmd_string(trans_pcie, cmd->id))) | |
2cc39c94 | 1696 | return -EIO; |
2cc39c94 | 1697 | |
6d8f6eeb | 1698 | IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", |
990aa6d7 | 1699 | get_cmd_string(trans_pcie, cmd->id)); |
253a634c | 1700 | |
f02831be | 1701 | cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd); |
253a634c EG |
1702 | if (cmd_idx < 0) { |
1703 | ret = cmd_idx; | |
eb7ff77e | 1704 | clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); |
721c32f7 | 1705 | IWL_ERR(trans, |
b36b110c | 1706 | "Error sending %s: enqueue_hcmd failed: %d\n", |
990aa6d7 | 1707 | get_cmd_string(trans_pcie, cmd->id), ret); |
253a634c EG |
1708 | return ret; |
1709 | } | |
1710 | ||
b9439491 EG |
1711 | ret = wait_event_timeout(trans_pcie->wait_command_queue, |
1712 | !test_bit(STATUS_SYNC_HCMD_ACTIVE, | |
1713 | &trans->status), | |
1714 | HOST_COMPLETE_TIMEOUT); | |
253a634c | 1715 | if (!ret) { |
6dde8c48 JB |
1716 | struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
1717 | struct iwl_queue *q = &txq->q; | |
d10630af | 1718 | |
6dde8c48 JB |
1719 | IWL_ERR(trans, "Error sending %s: time out after %dms.\n", |
1720 | get_cmd_string(trans_pcie, cmd->id), | |
1721 | jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); | |
253a634c | 1722 | |
6dde8c48 JB |
1723 | IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n", |
1724 | q->read_ptr, q->write_ptr); | |
d10630af | 1725 | |
eb7ff77e | 1726 | clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); |
6dde8c48 JB |
1727 | IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", |
1728 | get_cmd_string(trans_pcie, cmd->id)); | |
1729 | ret = -ETIMEDOUT; | |
42550a53 | 1730 | |
4c9706dc | 1731 | iwl_force_nmi(trans); |
2a988e98 | 1732 | iwl_trans_fw_error(trans); |
42550a53 | 1733 | |
6dde8c48 | 1734 | goto cancel; |
253a634c EG |
1735 | } |
1736 | ||
eb7ff77e | 1737 | if (test_bit(STATUS_FW_ERROR, &trans->status)) { |
d18aa87f | 1738 | IWL_ERR(trans, "FW error in SYNC CMD %s\n", |
990aa6d7 | 1739 | get_cmd_string(trans_pcie, cmd->id)); |
b656fa33 | 1740 | dump_stack(); |
d18aa87f JB |
1741 | ret = -EIO; |
1742 | goto cancel; | |
1743 | } | |
1744 | ||
1094fa26 | 1745 | if (!(cmd->flags & CMD_SEND_IN_RFKILL) && |
eb7ff77e | 1746 | test_bit(STATUS_RFKILL, &trans->status)) { |
f946b529 EG |
1747 | IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n"); |
1748 | ret = -ERFKILL; | |
1749 | goto cancel; | |
1750 | } | |
1751 | ||
65b94a4a | 1752 | if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) { |
6d8f6eeb | 1753 | IWL_ERR(trans, "Error: Response NULL in '%s'\n", |
990aa6d7 | 1754 | get_cmd_string(trans_pcie, cmd->id)); |
253a634c EG |
1755 | ret = -EIO; |
1756 | goto cancel; | |
1757 | } | |
1758 | ||
1759 | return 0; | |
1760 | ||
1761 | cancel: | |
1762 | if (cmd->flags & CMD_WANT_SKB) { | |
1763 | /* | |
1764 | * Cancel the CMD_WANT_SKB flag for the cmd in the | |
1765 | * TX cmd queue. Otherwise in case the cmd comes | |
1766 | * in later, it will possibly set an invalid | |
1767 | * address (cmd->meta.source). | |
1768 | */ | |
bf8440e6 JB |
1769 | trans_pcie->txq[trans_pcie->cmd_queue]. |
1770 | entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB; | |
253a634c | 1771 | } |
9cac4943 | 1772 | |
65b94a4a JB |
1773 | if (cmd->resp_pkt) { |
1774 | iwl_free_resp(cmd); | |
1775 | cmd->resp_pkt = NULL; | |
253a634c EG |
1776 | } |
1777 | ||
1778 | return ret; | |
1779 | } | |
1780 | ||
f02831be | 1781 | int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c | 1782 | { |
4f59334b | 1783 | if (!(cmd->flags & CMD_SEND_IN_RFKILL) && |
eb7ff77e | 1784 | test_bit(STATUS_RFKILL, &trans->status)) { |
754d7d9e EG |
1785 | IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n", |
1786 | cmd->id); | |
f946b529 | 1787 | return -ERFKILL; |
754d7d9e | 1788 | } |
f946b529 | 1789 | |
253a634c | 1790 | if (cmd->flags & CMD_ASYNC) |
f02831be | 1791 | return iwl_pcie_send_hcmd_async(trans, cmd); |
253a634c | 1792 | |
f946b529 | 1793 | /* We still can fail on RFKILL that can be asserted while we wait */ |
f02831be | 1794 | return iwl_pcie_send_hcmd_sync(trans, cmd); |
253a634c EG |
1795 | } |
1796 | ||
f02831be EG |
1797 | int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, |
1798 | struct iwl_device_cmd *dev_cmd, int txq_id) | |
a0eaad71 | 1799 | { |
8ad71bef | 1800 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
206eea78 | 1801 | struct ieee80211_hdr *hdr; |
f02831be EG |
1802 | struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload; |
1803 | struct iwl_cmd_meta *out_meta; | |
1804 | struct iwl_txq *txq; | |
1805 | struct iwl_queue *q; | |
38c0f334 JB |
1806 | dma_addr_t tb0_phys, tb1_phys, scratch_phys; |
1807 | void *tb1_addr; | |
1808 | u16 len, tb1_len, tb2_len; | |
ea68f460 | 1809 | bool wait_write_ptr; |
206eea78 JB |
1810 | __le16 fc; |
1811 | u8 hdr_len; | |
68972c46 | 1812 | u16 wifi_seq; |
206eea78 | 1813 | int i; |
f02831be EG |
1814 | |
1815 | txq = &trans_pcie->txq[txq_id]; | |
1816 | q = &txq->q; | |
a0eaad71 | 1817 | |
961de6a5 JB |
1818 | if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used), |
1819 | "TX on unused queue %d\n", txq_id)) | |
f02831be | 1820 | return -EINVAL; |
39644e9a | 1821 | |
206eea78 JB |
1822 | if (skb_is_nonlinear(skb) && |
1823 | skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS && | |
1824 | __skb_linearize(skb)) | |
1825 | return -ENOMEM; | |
1826 | ||
1827 | /* mac80211 always puts the full header into the SKB's head, | |
1828 | * so there's no need to check if it's readable there | |
1829 | */ | |
1830 | hdr = (struct ieee80211_hdr *)skb->data; | |
1831 | fc = hdr->frame_control; | |
1832 | hdr_len = ieee80211_hdrlen(fc); | |
1833 | ||
f02831be | 1834 | spin_lock(&txq->lock); |
015c15e1 | 1835 | |
f02831be EG |
1836 | /* In AGG mode, the index in the ring must correspond to the WiFi |
1837 | * sequence number. This is a HW requirements to help the SCD to parse | |
1838 | * the BA. | |
1839 | * Check here that the packets are in the right place on the ring. | |
1840 | */ | |
9a886586 | 1841 | wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); |
1092b9bc | 1842 | WARN_ONCE(txq->ampdu && |
68972c46 | 1843 | (wifi_seq & 0xff) != q->write_ptr, |
f02831be EG |
1844 | "Q: %d WiFi Seq %d tfdNum %d", |
1845 | txq_id, wifi_seq, q->write_ptr); | |
f02831be EG |
1846 | |
1847 | /* Set up driver data for this TFD */ | |
1848 | txq->entries[q->write_ptr].skb = skb; | |
1849 | txq->entries[q->write_ptr].cmd = dev_cmd; | |
1850 | ||
f02831be EG |
1851 | dev_cmd->hdr.sequence = |
1852 | cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
1853 | INDEX_TO_SEQ(q->write_ptr))); | |
1854 | ||
38c0f334 JB |
1855 | tb0_phys = iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr); |
1856 | scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) + | |
1857 | offsetof(struct iwl_tx_cmd, scratch); | |
1858 | ||
1859 | tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); | |
1860 | tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); | |
1861 | ||
f02831be EG |
1862 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ |
1863 | out_meta = &txq->entries[q->write_ptr].meta; | |
206eea78 | 1864 | out_meta->flags = 0; |
a0eaad71 | 1865 | |
f02831be | 1866 | /* |
38c0f334 JB |
1867 | * The second TB (tb1) points to the remainder of the TX command |
1868 | * and the 802.11 header - dword aligned size | |
1869 | * (This calculation modifies the TX command, so do it before the | |
1870 | * setup of the first TB) | |
f02831be | 1871 | */ |
38c0f334 JB |
1872 | len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) + |
1873 | hdr_len - IWL_HCMD_SCRATCHBUF_SIZE; | |
1092b9bc | 1874 | tb1_len = ALIGN(len, 4); |
f02831be EG |
1875 | |
1876 | /* Tell NIC about any 2-byte padding after MAC header */ | |
38c0f334 | 1877 | if (tb1_len != len) |
f02831be EG |
1878 | tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; |
1879 | ||
38c0f334 JB |
1880 | /* The first TB points to the scratchbuf data - min_copy bytes */ |
1881 | memcpy(&txq->scratchbufs[q->write_ptr], &dev_cmd->hdr, | |
1882 | IWL_HCMD_SCRATCHBUF_SIZE); | |
1883 | iwl_pcie_txq_build_tfd(trans, txq, tb0_phys, | |
6d6e68f8 | 1884 | IWL_HCMD_SCRATCHBUF_SIZE, true); |
f02831be | 1885 | |
38c0f334 JB |
1886 | /* there must be data left over for TB1 or this code must be changed */ |
1887 | BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_HCMD_SCRATCHBUF_SIZE); | |
1888 | ||
1889 | /* map the data for TB1 */ | |
1890 | tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_HCMD_SCRATCHBUF_SIZE; | |
1891 | tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE); | |
1892 | if (unlikely(dma_mapping_error(trans->dev, tb1_phys))) | |
1893 | goto out_err; | |
6d6e68f8 | 1894 | iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false); |
a0eaad71 | 1895 | |
38c0f334 JB |
1896 | /* |
1897 | * Set up TFD's third entry to point directly to remainder | |
206eea78 | 1898 | * of skb's head, if any |
38c0f334 | 1899 | */ |
206eea78 | 1900 | tb2_len = skb_headlen(skb) - hdr_len; |
38c0f334 JB |
1901 | if (tb2_len > 0) { |
1902 | dma_addr_t tb2_phys = dma_map_single(trans->dev, | |
1903 | skb->data + hdr_len, | |
1904 | tb2_len, DMA_TO_DEVICE); | |
1905 | if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) { | |
1906 | iwl_pcie_tfd_unmap(trans, out_meta, | |
1907 | &txq->tfds[q->write_ptr]); | |
f02831be EG |
1908 | goto out_err; |
1909 | } | |
6d6e68f8 | 1910 | iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, false); |
f02831be | 1911 | } |
a0eaad71 | 1912 | |
206eea78 JB |
1913 | /* set up the remaining entries to point to the data */ |
1914 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
1915 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
1916 | dma_addr_t tb_phys; | |
1917 | int tb_idx; | |
1918 | ||
1919 | if (!skb_frag_size(frag)) | |
1920 | continue; | |
1921 | ||
1922 | tb_phys = skb_frag_dma_map(trans->dev, frag, 0, | |
1923 | skb_frag_size(frag), DMA_TO_DEVICE); | |
1924 | ||
1925 | if (unlikely(dma_mapping_error(trans->dev, tb_phys))) { | |
1926 | iwl_pcie_tfd_unmap(trans, out_meta, | |
1927 | &txq->tfds[q->write_ptr]); | |
1928 | goto out_err; | |
1929 | } | |
1930 | tb_idx = iwl_pcie_txq_build_tfd(trans, txq, tb_phys, | |
1931 | skb_frag_size(frag), false); | |
1932 | ||
1933 | out_meta->flags |= BIT(tb_idx + CMD_TB_BITMAP_POS); | |
1934 | } | |
1935 | ||
f02831be EG |
1936 | /* Set up entry for this TFD in Tx byte-count array */ |
1937 | iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len)); | |
a0eaad71 | 1938 | |
f02831be EG |
1939 | trace_iwlwifi_dev_tx(trans->dev, skb, |
1940 | &txq->tfds[txq->q.write_ptr], | |
1941 | sizeof(struct iwl_tfd), | |
38c0f334 JB |
1942 | &dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len, |
1943 | skb->data + hdr_len, tb2_len); | |
f02831be | 1944 | trace_iwlwifi_dev_tx_data(trans->dev, skb, |
206eea78 | 1945 | hdr_len, skb->len - hdr_len); |
38c0f334 | 1946 | |
ea68f460 | 1947 | wait_write_ptr = ieee80211_has_morefrags(fc); |
7c5ba4a8 | 1948 | |
f02831be | 1949 | /* start timer if queue currently empty */ |
7616f334 | 1950 | if (q->read_ptr == q->write_ptr) { |
aecdc63d EG |
1951 | if (txq->wd_timeout) { |
1952 | /* | |
1953 | * If the TXQ is active, then set the timer, if not, | |
1954 | * set the timer in remainder so that the timer will | |
1955 | * be armed with the right value when the station will | |
1956 | * wake up. | |
1957 | */ | |
1958 | if (!txq->frozen) | |
1959 | mod_timer(&txq->stuck_timer, | |
1960 | jiffies + txq->wd_timeout); | |
1961 | else | |
1962 | txq->frozen_expiry_remainder = txq->wd_timeout; | |
1963 | } | |
7616f334 EP |
1964 | IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", q->id); |
1965 | iwl_trans_pcie_ref(trans); | |
1966 | } | |
f02831be EG |
1967 | |
1968 | /* Tell device the write index *just past* this latest filled TFD */ | |
83f32a4b | 1969 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr); |
ea68f460 JB |
1970 | if (!wait_write_ptr) |
1971 | iwl_pcie_txq_inc_wr_ptr(trans, txq); | |
f02831be EG |
1972 | |
1973 | /* | |
1974 | * At this point the frame is "transmitted" successfully | |
43aa616f | 1975 | * and we will get a TX status notification eventually. |
f02831be EG |
1976 | */ |
1977 | if (iwl_queue_space(q) < q->high_mark) { | |
ea68f460 | 1978 | if (wait_write_ptr) |
f02831be | 1979 | iwl_pcie_txq_inc_wr_ptr(trans, txq); |
ea68f460 | 1980 | else |
f02831be | 1981 | iwl_stop_queue(trans, txq); |
f02831be EG |
1982 | } |
1983 | spin_unlock(&txq->lock); | |
1984 | return 0; | |
1985 | out_err: | |
1986 | spin_unlock(&txq->lock); | |
1987 | return -1; | |
a0eaad71 | 1988 | } |