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1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
fb4961db | 3 | * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved. |
1053d35f RR |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
1053d35f RR |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
fd4abac5 | 29 | #include <linux/etherdevice.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
253a634c | 31 | #include <linux/sched.h> |
253a634c | 32 | |
522376d2 EG |
33 | #include "iwl-debug.h" |
34 | #include "iwl-csr.h" | |
35 | #include "iwl-prph.h" | |
1053d35f | 36 | #include "iwl-io.h" |
ed277c93 | 37 | #include "iwl-op-mode.h" |
6468a01a | 38 | #include "internal.h" |
6238b008 | 39 | /* FIXME: need to abstract out TX command (once we know what it looks like) */ |
1023fdc4 | 40 | #include "dvm/commands.h" |
1053d35f | 41 | |
522376d2 EG |
42 | #define IWL_TX_CRC_SIZE 4 |
43 | #define IWL_TX_DELIMITER_SIZE 4 | |
44 | ||
990aa6d7 EG |
45 | /* |
46 | * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array | |
48d42c42 | 47 | */ |
990aa6d7 EG |
48 | void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans, |
49 | struct iwl_txq *txq, u16 byte_cnt) | |
48d42c42 | 50 | { |
105183b1 | 51 | struct iwlagn_scd_bc_tbl *scd_bc_tbl; |
20d3b647 | 52 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
48d42c42 EG |
53 | int write_ptr = txq->q.write_ptr; |
54 | int txq_id = txq->q.id; | |
55 | u8 sec_ctl = 0; | |
56 | u8 sta_id = 0; | |
57 | u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; | |
58 | __le16 bc_ent; | |
132f98c2 | 59 | struct iwl_tx_cmd *tx_cmd = |
bf8440e6 | 60 | (void *) txq->entries[txq->q.write_ptr].cmd->payload; |
48d42c42 | 61 | |
105183b1 EG |
62 | scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; |
63 | ||
48d42c42 EG |
64 | WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX); |
65 | ||
132f98c2 EG |
66 | sta_id = tx_cmd->sta_id; |
67 | sec_ctl = tx_cmd->sec_ctl; | |
48d42c42 EG |
68 | |
69 | switch (sec_ctl & TX_CMD_SEC_MSK) { | |
70 | case TX_CMD_SEC_CCM: | |
71 | len += CCMP_MIC_LEN; | |
72 | break; | |
73 | case TX_CMD_SEC_TKIP: | |
74 | len += TKIP_ICV_LEN; | |
75 | break; | |
76 | case TX_CMD_SEC_WEP: | |
77 | len += WEP_IV_LEN + WEP_ICV_LEN; | |
78 | break; | |
79 | } | |
80 | ||
81 | bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12)); | |
82 | ||
83 | scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; | |
84 | ||
85 | if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
86 | scd_bc_tbl[txq_id]. | |
87 | tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; | |
88 | } | |
89 | ||
990aa6d7 EG |
90 | /* |
91 | * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware | |
fd4abac5 | 92 | */ |
990aa6d7 | 93 | void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_txq *txq) |
fd4abac5 TW |
94 | { |
95 | u32 reg = 0; | |
fd4abac5 TW |
96 | int txq_id = txq->q.id; |
97 | ||
98 | if (txq->need_update == 0) | |
7bfedc59 | 99 | return; |
fd4abac5 | 100 | |
035f7ff2 | 101 | if (trans->cfg->base_params->shadow_reg_enable) { |
f81c1f48 | 102 | /* shadow register enabled */ |
1042db2a | 103 | iwl_write32(trans, HBUS_TARG_WRPTR, |
f81c1f48 WYG |
104 | txq->q.write_ptr | (txq_id << 8)); |
105 | } else { | |
47107e84 DF |
106 | struct iwl_trans_pcie *trans_pcie = |
107 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
f81c1f48 | 108 | /* if we're trying to save power */ |
01d651d4 | 109 | if (test_bit(STATUS_TPOWER_PMI, &trans_pcie->status)) { |
f81c1f48 WYG |
110 | /* wake up nic if it's powered down ... |
111 | * uCode will wake up, and interrupt us again, so next | |
112 | * time we'll skip this part. */ | |
1042db2a | 113 | reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); |
fd4abac5 | 114 | |
f81c1f48 | 115 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { |
fd656935 | 116 | IWL_DEBUG_INFO(trans, |
f81c1f48 WYG |
117 | "Tx queue %d requesting wakeup," |
118 | " GP1 = 0x%x\n", txq_id, reg); | |
1042db2a | 119 | iwl_set_bit(trans, CSR_GP_CNTRL, |
f81c1f48 WYG |
120 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
121 | return; | |
122 | } | |
fd4abac5 | 123 | |
1042db2a | 124 | iwl_write_direct32(trans, HBUS_TARG_WRPTR, |
fd4abac5 | 125 | txq->q.write_ptr | (txq_id << 8)); |
fd4abac5 | 126 | |
f81c1f48 WYG |
127 | /* |
128 | * else not in power-save mode, | |
129 | * uCode will never sleep when we're | |
130 | * trying to tx (during RFKILL, we're not trying to tx). | |
131 | */ | |
132 | } else | |
1042db2a | 133 | iwl_write32(trans, HBUS_TARG_WRPTR, |
f81c1f48 WYG |
134 | txq->q.write_ptr | (txq_id << 8)); |
135 | } | |
fd4abac5 | 136 | txq->need_update = 0; |
fd4abac5 | 137 | } |
fd4abac5 | 138 | |
214d14d4 JB |
139 | static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
140 | { | |
141 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
142 | ||
143 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
144 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
145 | addr |= | |
146 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
147 | ||
148 | return addr; | |
149 | } | |
150 | ||
151 | static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) | |
152 | { | |
153 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
154 | ||
155 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
156 | } | |
157 | ||
158 | static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, | |
159 | dma_addr_t addr, u16 len) | |
160 | { | |
161 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
162 | u16 hi_n_len = len << 4; | |
163 | ||
164 | put_unaligned_le32(addr, &tb->lo); | |
165 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
166 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
167 | ||
168 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
169 | ||
170 | tfd->num_tbs = idx + 1; | |
171 | } | |
172 | ||
173 | static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd) | |
174 | { | |
175 | return tfd->num_tbs & 0x1f; | |
176 | } | |
177 | ||
eec373f0 EG |
178 | static void iwl_unmap_tfd(struct iwl_trans *trans, struct iwl_cmd_meta *meta, |
179 | struct iwl_tfd *tfd, enum dma_data_direction dma_dir) | |
214d14d4 | 180 | { |
214d14d4 JB |
181 | int i; |
182 | int num_tbs; | |
183 | ||
214d14d4 JB |
184 | /* Sanity check on number of chunks */ |
185 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
186 | ||
187 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
6d8f6eeb | 188 | IWL_ERR(trans, "Too many chunks: %i\n", num_tbs); |
214d14d4 JB |
189 | /* @todo issue fatal error, it is quite serious situation */ |
190 | return; | |
191 | } | |
192 | ||
193 | /* Unmap tx_cmd */ | |
194 | if (num_tbs) | |
1042db2a | 195 | dma_unmap_single(trans->dev, |
4ce7cc2b JB |
196 | dma_unmap_addr(meta, mapping), |
197 | dma_unmap_len(meta, len), | |
795414db | 198 | DMA_BIDIRECTIONAL); |
214d14d4 JB |
199 | |
200 | /* Unmap chunks, if any. */ | |
201 | for (i = 1; i < num_tbs; i++) | |
1042db2a | 202 | dma_unmap_single(trans->dev, iwl_tfd_tb_get_addr(tfd, i), |
e815407d | 203 | iwl_tfd_tb_get_len(tfd, i), dma_dir); |
ebed633c EG |
204 | |
205 | tfd->num_tbs = 0; | |
4ce7cc2b JB |
206 | } |
207 | ||
990aa6d7 EG |
208 | /* |
209 | * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
6d8f6eeb | 210 | * @trans - transport private data |
4ce7cc2b | 211 | * @txq - tx queue |
ebed633c | 212 | * @dma_dir - the direction of the DMA mapping |
4ce7cc2b JB |
213 | * |
214 | * Does NOT advance any TFD circular buffer read/write indexes | |
215 | * Does NOT free the TFD itself (which is within circular buffer) | |
216 | */ | |
990aa6d7 EG |
217 | void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq, |
218 | enum dma_data_direction dma_dir) | |
4ce7cc2b JB |
219 | { |
220 | struct iwl_tfd *tfd_tmp = txq->tfds; | |
4ce7cc2b | 221 | |
ebed633c EG |
222 | /* rd_ptr is bounded by n_bd and idx is bounded by n_window */ |
223 | int rd_ptr = txq->q.read_ptr; | |
224 | int idx = get_cmd_index(&txq->q, rd_ptr); | |
225 | ||
015c15e1 JB |
226 | lockdep_assert_held(&txq->lock); |
227 | ||
ebed633c | 228 | /* We have only q->n_window txq->entries, but we use q->n_bd tfds */ |
eec373f0 EG |
229 | iwl_unmap_tfd(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr], |
230 | dma_dir); | |
214d14d4 JB |
231 | |
232 | /* free SKB */ | |
bf8440e6 | 233 | if (txq->entries) { |
214d14d4 JB |
234 | struct sk_buff *skb; |
235 | ||
ebed633c | 236 | skb = txq->entries[idx].skb; |
214d14d4 | 237 | |
909e9b23 EG |
238 | /* Can be called from irqs-disabled context |
239 | * If skb is not NULL, it means that the whole queue is being | |
240 | * freed and that the queue is not empty - free the skb | |
241 | */ | |
214d14d4 | 242 | if (skb) { |
ed277c93 | 243 | iwl_op_mode_free_skb(trans->op_mode, skb); |
ebed633c | 244 | txq->entries[idx].skb = NULL; |
214d14d4 JB |
245 | } |
246 | } | |
247 | } | |
248 | ||
990aa6d7 EG |
249 | int iwl_pcie_tx_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq, |
250 | dma_addr_t addr, u16 len, u8 reset) | |
214d14d4 JB |
251 | { |
252 | struct iwl_queue *q; | |
253 | struct iwl_tfd *tfd, *tfd_tmp; | |
254 | u32 num_tbs; | |
255 | ||
256 | q = &txq->q; | |
4ce7cc2b | 257 | tfd_tmp = txq->tfds; |
214d14d4 JB |
258 | tfd = &tfd_tmp[q->write_ptr]; |
259 | ||
260 | if (reset) | |
261 | memset(tfd, 0, sizeof(*tfd)); | |
262 | ||
263 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
264 | ||
265 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
266 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
6d8f6eeb | 267 | IWL_ERR(trans, "Error can not send more than %d chunks\n", |
20d3b647 | 268 | IWL_NUM_OF_TBS); |
214d14d4 JB |
269 | return -EINVAL; |
270 | } | |
271 | ||
272 | if (WARN_ON(addr & ~DMA_BIT_MASK(36))) | |
273 | return -EINVAL; | |
274 | ||
275 | if (unlikely(addr & ~IWL_TX_DMA_MASK)) | |
6d8f6eeb | 276 | IWL_ERR(trans, "Unaligned address = %llx\n", |
20d3b647 | 277 | (unsigned long long)addr); |
214d14d4 JB |
278 | |
279 | iwl_tfd_set_tb(tfd, num_tbs, addr, len); | |
280 | ||
281 | return 0; | |
282 | } | |
283 | ||
fd4abac5 TW |
284 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
285 | * DMA services | |
286 | * | |
287 | * Theory of operation | |
288 | * | |
289 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
290 | * of buffer descriptors, each of which points to one or more data buffers for | |
291 | * the device to read from or fill. Driver and device exchange status of each | |
292 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
293 | * entries in each circular buffer, to protect against confusing empty and full | |
294 | * queue states. | |
295 | * | |
296 | * The device reads or writes the data in the queues via the device's several | |
297 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
298 | * | |
299 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
300 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
301 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
302 | * Tx queue resumed. | |
303 | * | |
fd4abac5 TW |
304 | ***************************************************/ |
305 | ||
306 | int iwl_queue_space(const struct iwl_queue *q) | |
307 | { | |
308 | int s = q->read_ptr - q->write_ptr; | |
309 | ||
310 | if (q->read_ptr > q->write_ptr) | |
311 | s -= q->n_bd; | |
312 | ||
313 | if (s <= 0) | |
314 | s += q->n_window; | |
315 | /* keep some reserve to not confuse empty and full situations */ | |
316 | s -= 2; | |
317 | if (s < 0) | |
318 | s = 0; | |
319 | return s; | |
320 | } | |
fd4abac5 | 321 | |
990aa6d7 | 322 | /* |
1053d35f RR |
323 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes |
324 | */ | |
6d8f6eeb | 325 | int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id) |
1053d35f RR |
326 | { |
327 | q->n_bd = count; | |
328 | q->n_window = slots_num; | |
329 | q->id = id; | |
330 | ||
331 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap | |
332 | * and iwl_queue_dec_wrap are broken. */ | |
3e41ace5 JB |
333 | if (WARN_ON(!is_power_of_2(count))) |
334 | return -EINVAL; | |
1053d35f RR |
335 | |
336 | /* slots_num must be power-of-two size, otherwise | |
337 | * get_cmd_index is broken. */ | |
3e41ace5 JB |
338 | if (WARN_ON(!is_power_of_2(slots_num))) |
339 | return -EINVAL; | |
1053d35f RR |
340 | |
341 | q->low_mark = q->n_window / 4; | |
342 | if (q->low_mark < 4) | |
343 | q->low_mark = 4; | |
344 | ||
345 | q->high_mark = q->n_window / 8; | |
346 | if (q->high_mark < 2) | |
347 | q->high_mark = 2; | |
348 | ||
349 | q->write_ptr = q->read_ptr = 0; | |
350 | ||
351 | return 0; | |
352 | } | |
353 | ||
6d8f6eeb | 354 | static void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_trans *trans, |
990aa6d7 | 355 | struct iwl_txq *txq) |
48d42c42 | 356 | { |
105183b1 EG |
357 | struct iwl_trans_pcie *trans_pcie = |
358 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
6d8f6eeb | 359 | struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; |
48d42c42 EG |
360 | int txq_id = txq->q.id; |
361 | int read_ptr = txq->q.read_ptr; | |
362 | u8 sta_id = 0; | |
363 | __le16 bc_ent; | |
132f98c2 | 364 | struct iwl_tx_cmd *tx_cmd = |
bf8440e6 | 365 | (void *)txq->entries[txq->q.read_ptr].cmd->payload; |
48d42c42 EG |
366 | |
367 | WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); | |
368 | ||
c6f600fc | 369 | if (txq_id != trans_pcie->cmd_queue) |
132f98c2 | 370 | sta_id = tx_cmd->sta_id; |
48d42c42 EG |
371 | |
372 | bc_ent = cpu_to_le16(1 | (sta_id << 12)); | |
373 | scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; | |
374 | ||
375 | if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
376 | scd_bc_tbl[txq_id]. | |
377 | tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; | |
378 | } | |
379 | ||
1ce8658c EG |
380 | static int iwl_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid, |
381 | u16 txq_id) | |
48d42c42 | 382 | { |
20d3b647 | 383 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
48d42c42 EG |
384 | u32 tbl_dw_addr; |
385 | u32 tbl_dw; | |
386 | u16 scd_q2ratid; | |
387 | ||
388 | scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; | |
389 | ||
105183b1 | 390 | tbl_dw_addr = trans_pcie->scd_base_addr + |
48d42c42 EG |
391 | SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); |
392 | ||
1042db2a | 393 | tbl_dw = iwl_read_targ_mem(trans, tbl_dw_addr); |
48d42c42 EG |
394 | |
395 | if (txq_id & 0x1) | |
396 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); | |
397 | else | |
398 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); | |
399 | ||
1042db2a | 400 | iwl_write_targ_mem(trans, tbl_dw_addr, tbl_dw); |
48d42c42 EG |
401 | |
402 | return 0; | |
403 | } | |
404 | ||
1ce8658c | 405 | static inline void iwl_txq_set_inactive(struct iwl_trans *trans, u16 txq_id) |
48d42c42 EG |
406 | { |
407 | /* Simply stop the queue, but don't change any configuration; | |
408 | * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ | |
1042db2a | 409 | iwl_write_prph(trans, |
48d42c42 EG |
410 | SCD_QUEUE_STATUS_BITS(txq_id), |
411 | (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)| | |
412 | (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); | |
413 | } | |
414 | ||
990aa6d7 EG |
415 | void iwl_pcie_txq_enable(struct iwl_trans *trans, int txq_id, int fifo, |
416 | int sta_id, int tid, int frame_limit, u16 ssn) | |
48d42c42 | 417 | { |
9eae88fa | 418 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
4beaf6c2 | 419 | |
9eae88fa JB |
420 | if (test_and_set_bit(txq_id, trans_pcie->queue_used)) |
421 | WARN_ONCE(1, "queue %d already used - expect issues", txq_id); | |
48d42c42 | 422 | |
48d42c42 | 423 | /* Stop this Tx queue before configuring it */ |
1ce8658c | 424 | iwl_txq_set_inactive(trans, txq_id); |
48d42c42 | 425 | |
4beaf6c2 EG |
426 | /* Set this queue as a chain-building queue unless it is CMD queue */ |
427 | if (txq_id != trans_pcie->cmd_queue) | |
428 | iwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, BIT(txq_id)); | |
429 | ||
430 | /* If this queue is mapped to a certain station: it is an AGG queue */ | |
431 | if (sta_id != IWL_INVALID_STATION) { | |
432 | u16 ra_tid = BUILD_RAxTID(sta_id, tid); | |
48d42c42 | 433 | |
4beaf6c2 | 434 | /* Map receiver-address / traffic-ID to this queue */ |
1ce8658c | 435 | iwl_txq_set_ratid_map(trans, ra_tid, txq_id); |
48d42c42 | 436 | |
4beaf6c2 EG |
437 | /* enable aggregations for the queue */ |
438 | iwl_set_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id)); | |
1ce8658c EG |
439 | } else { |
440 | /* | |
441 | * disable aggregations for the queue, this will also make the | |
442 | * ra_tid mapping configuration irrelevant since it is now a | |
443 | * non-AGG queue. | |
444 | */ | |
445 | iwl_clear_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id)); | |
4beaf6c2 | 446 | } |
48d42c42 EG |
447 | |
448 | /* Place first TFD at index corresponding to start sequence number. | |
449 | * Assumes that ssn_idx is valid (!= 0xFFF) */ | |
822e8b2a EG |
450 | trans_pcie->txq[txq_id].q.read_ptr = (ssn & 0xff); |
451 | trans_pcie->txq[txq_id].q.write_ptr = (ssn & 0xff); | |
1ce8658c EG |
452 | |
453 | iwl_write_direct32(trans, HBUS_TARG_WRPTR, | |
454 | (ssn & 0xff) | (txq_id << 8)); | |
455 | iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn); | |
48d42c42 EG |
456 | |
457 | /* Set up Tx window size and frame limit for this queue */ | |
4beaf6c2 EG |
458 | iwl_write_targ_mem(trans, trans_pcie->scd_base_addr + |
459 | SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0); | |
1042db2a | 460 | iwl_write_targ_mem(trans, trans_pcie->scd_base_addr + |
9eae88fa JB |
461 | SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), |
462 | ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
463 | SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
464 | ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
465 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
48d42c42 | 466 | |
48d42c42 | 467 | /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ |
1ce8658c EG |
468 | iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id), |
469 | (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) | | |
470 | (fifo << SCD_QUEUE_STTS_REG_POS_TXF) | | |
471 | (1 << SCD_QUEUE_STTS_REG_POS_WSL) | | |
472 | SCD_QUEUE_STTS_REG_MSK); | |
473 | IWL_DEBUG_TX_QUEUES(trans, "Activate queue %d on FIFO %d WrPtr: %d\n", | |
474 | txq_id, fifo, ssn & 0xff); | |
4beaf6c2 EG |
475 | } |
476 | ||
990aa6d7 | 477 | void iwl_pcie_txq_disable(struct iwl_trans *trans, int txq_id) |
288712a6 | 478 | { |
8ad71bef | 479 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
986ea6c9 EG |
480 | u32 stts_addr = trans_pcie->scd_base_addr + |
481 | SCD_TX_STTS_QUEUE_OFFSET(txq_id); | |
482 | static const u32 zero_val[4] = {}; | |
288712a6 | 483 | |
9eae88fa JB |
484 | if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) { |
485 | WARN_ONCE(1, "queue %d not used", txq_id); | |
486 | return; | |
48d42c42 EG |
487 | } |
488 | ||
ac928f8d EG |
489 | iwl_txq_set_inactive(trans, txq_id); |
490 | ||
986ea6c9 EG |
491 | _iwl_write_targ_mem_dwords(trans, stts_addr, |
492 | zero_val, ARRAY_SIZE(zero_val)); | |
493 | ||
990aa6d7 | 494 | iwl_pcie_txq_unmap(trans, txq_id); |
6c3fd3f0 | 495 | |
1ce8658c | 496 | IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id); |
48d42c42 EG |
497 | } |
498 | ||
fd4abac5 TW |
499 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ |
500 | ||
990aa6d7 | 501 | /* |
fd4abac5 TW |
502 | * iwl_enqueue_hcmd - enqueue a uCode command |
503 | * @priv: device private data point | |
504 | * @cmd: a point to the ucode command structure | |
505 | * | |
506 | * The function returns < 0 values to indicate the operation is | |
507 | * failed. On success, it turns the index (> 0) of command in the | |
508 | * command queue. | |
509 | */ | |
6d8f6eeb | 510 | static int iwl_enqueue_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
fd4abac5 | 511 | { |
8ad71bef | 512 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 513 | struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
fd4abac5 | 514 | struct iwl_queue *q = &txq->q; |
c2acea8e JB |
515 | struct iwl_device_cmd *out_cmd; |
516 | struct iwl_cmd_meta *out_meta; | |
f4feb8ac | 517 | void *dup_buf = NULL; |
fd4abac5 | 518 | dma_addr_t phys_addr; |
f4feb8ac | 519 | int idx; |
4ce7cc2b | 520 | u16 copy_size, cmd_size; |
4ce7cc2b JB |
521 | bool had_nocopy = false; |
522 | int i; | |
96791422 | 523 | u32 cmd_pos; |
fd4abac5 | 524 | |
4ce7cc2b JB |
525 | copy_size = sizeof(out_cmd->hdr); |
526 | cmd_size = sizeof(out_cmd->hdr); | |
527 | ||
528 | /* need one for the header if the first is NOCOPY */ | |
529 | BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1); | |
530 | ||
531 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
532 | if (!cmd->len[i]) | |
533 | continue; | |
534 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { | |
535 | had_nocopy = true; | |
f4feb8ac JB |
536 | if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) { |
537 | idx = -EINVAL; | |
538 | goto free_dup_buf; | |
539 | } | |
540 | } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) { | |
541 | /* | |
542 | * This is also a chunk that isn't copied | |
543 | * to the static buffer so set had_nocopy. | |
544 | */ | |
545 | had_nocopy = true; | |
546 | ||
547 | /* only allowed once */ | |
548 | if (WARN_ON(dup_buf)) { | |
549 | idx = -EINVAL; | |
550 | goto free_dup_buf; | |
551 | } | |
552 | ||
553 | dup_buf = kmemdup(cmd->data[i], cmd->len[i], | |
554 | GFP_ATOMIC); | |
555 | if (!dup_buf) | |
556 | return -ENOMEM; | |
4ce7cc2b JB |
557 | } else { |
558 | /* NOCOPY must not be followed by normal! */ | |
f4feb8ac JB |
559 | if (WARN_ON(had_nocopy)) { |
560 | idx = -EINVAL; | |
561 | goto free_dup_buf; | |
562 | } | |
4ce7cc2b JB |
563 | copy_size += cmd->len[i]; |
564 | } | |
565 | cmd_size += cmd->len[i]; | |
566 | } | |
fd4abac5 | 567 | |
3e41ace5 JB |
568 | /* |
569 | * If any of the command structures end up being larger than | |
4ce7cc2b JB |
570 | * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically |
571 | * allocated into separate TFDs, then we will need to | |
572 | * increase the size of the buffers. | |
3e41ace5 | 573 | */ |
2a79e45e JB |
574 | if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE, |
575 | "Command %s (%#x) is too large (%d bytes)\n", | |
990aa6d7 | 576 | get_cmd_string(trans_pcie, cmd->id), cmd->id, copy_size)) { |
f4feb8ac JB |
577 | idx = -EINVAL; |
578 | goto free_dup_buf; | |
579 | } | |
fd4abac5 | 580 | |
015c15e1 | 581 | spin_lock_bh(&txq->lock); |
3598e177 | 582 | |
c2acea8e | 583 | if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { |
015c15e1 | 584 | spin_unlock_bh(&txq->lock); |
3598e177 | 585 | |
6d8f6eeb | 586 | IWL_ERR(trans, "No space in command queue\n"); |
0e781842 | 587 | iwl_op_mode_cmd_queue_full(trans->op_mode); |
f4feb8ac JB |
588 | idx = -ENOSPC; |
589 | goto free_dup_buf; | |
fd4abac5 TW |
590 | } |
591 | ||
4ce7cc2b | 592 | idx = get_cmd_index(q, q->write_ptr); |
bf8440e6 JB |
593 | out_cmd = txq->entries[idx].cmd; |
594 | out_meta = &txq->entries[idx].meta; | |
c2acea8e | 595 | |
8ce73f3a | 596 | memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ |
c2acea8e JB |
597 | if (cmd->flags & CMD_WANT_SKB) |
598 | out_meta->source = cmd; | |
fd4abac5 | 599 | |
4ce7cc2b | 600 | /* set up the header */ |
fd4abac5 | 601 | |
4ce7cc2b | 602 | out_cmd->hdr.cmd = cmd->id; |
fd4abac5 | 603 | out_cmd->hdr.flags = 0; |
cefeaa5f | 604 | out_cmd->hdr.sequence = |
c6f600fc | 605 | cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | |
cefeaa5f | 606 | INDEX_TO_SEQ(q->write_ptr)); |
4ce7cc2b JB |
607 | |
608 | /* and copy the data that needs to be copied */ | |
96791422 | 609 | cmd_pos = offsetof(struct iwl_device_cmd, payload); |
4ce7cc2b JB |
610 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { |
611 | if (!cmd->len[i]) | |
612 | continue; | |
f4feb8ac JB |
613 | if (cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | |
614 | IWL_HCMD_DFL_DUP)) | |
4ce7cc2b | 615 | break; |
96791422 EG |
616 | memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], cmd->len[i]); |
617 | cmd_pos += cmd->len[i]; | |
618 | } | |
619 | ||
620 | WARN_ON_ONCE(txq->entries[idx].copy_cmd); | |
621 | ||
622 | /* | |
623 | * since out_cmd will be the source address of the FH, it will write | |
624 | * the retry count there. So when the user needs to receivce the HCMD | |
625 | * that corresponds to the response in the response handler, it needs | |
626 | * to set CMD_WANT_HCMD. | |
627 | */ | |
628 | if (cmd->flags & CMD_WANT_HCMD) { | |
629 | txq->entries[idx].copy_cmd = | |
630 | kmemdup(out_cmd, cmd_pos, GFP_ATOMIC); | |
631 | if (unlikely(!txq->entries[idx].copy_cmd)) { | |
632 | idx = -ENOMEM; | |
633 | goto out; | |
634 | } | |
ded2ae7c | 635 | } |
4ce7cc2b | 636 | |
d9fb6465 | 637 | IWL_DEBUG_HC(trans, |
20d3b647 | 638 | "Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n", |
990aa6d7 | 639 | get_cmd_string(trans_pcie, out_cmd->hdr.cmd), |
20d3b647 JB |
640 | out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence), |
641 | cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue); | |
4ce7cc2b | 642 | |
1042db2a | 643 | phys_addr = dma_map_single(trans->dev, &out_cmd->hdr, copy_size, |
20d3b647 | 644 | DMA_BIDIRECTIONAL); |
1042db2a | 645 | if (unlikely(dma_mapping_error(trans->dev, phys_addr))) { |
2c46f72e JB |
646 | idx = -ENOMEM; |
647 | goto out; | |
648 | } | |
649 | ||
2e724443 | 650 | dma_unmap_addr_set(out_meta, mapping, phys_addr); |
4ce7cc2b JB |
651 | dma_unmap_len_set(out_meta, len, copy_size); |
652 | ||
990aa6d7 | 653 | iwl_pcie_tx_build_tfd(trans, txq, phys_addr, copy_size, 1); |
4ce7cc2b JB |
654 | |
655 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
f4feb8ac JB |
656 | const void *data = cmd->data[i]; |
657 | ||
4ce7cc2b JB |
658 | if (!cmd->len[i]) |
659 | continue; | |
f4feb8ac JB |
660 | if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | |
661 | IWL_HCMD_DFL_DUP))) | |
4ce7cc2b | 662 | continue; |
f4feb8ac JB |
663 | if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) |
664 | data = dup_buf; | |
665 | phys_addr = dma_map_single(trans->dev, (void *)data, | |
3be3fdb5 | 666 | cmd->len[i], DMA_BIDIRECTIONAL); |
1042db2a | 667 | if (dma_mapping_error(trans->dev, phys_addr)) { |
eec373f0 EG |
668 | iwl_unmap_tfd(trans, out_meta, |
669 | &txq->tfds[q->write_ptr], | |
670 | DMA_BIDIRECTIONAL); | |
4ce7cc2b JB |
671 | idx = -ENOMEM; |
672 | goto out; | |
673 | } | |
674 | ||
990aa6d7 | 675 | iwl_pcie_tx_build_tfd(trans, txq, phys_addr, cmd->len[i], 0); |
4ce7cc2b | 676 | } |
df833b1d | 677 | |
afaf6b57 | 678 | out_meta->flags = cmd->flags; |
f4feb8ac JB |
679 | if (WARN_ON_ONCE(txq->entries[idx].free_buf)) |
680 | kfree(txq->entries[idx].free_buf); | |
681 | txq->entries[idx].free_buf = dup_buf; | |
2c46f72e JB |
682 | |
683 | txq->need_update = 1; | |
684 | ||
45eab7cc JB |
685 | trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, |
686 | &out_cmd->hdr, copy_size); | |
df833b1d | 687 | |
7c5ba4a8 JB |
688 | /* start timer if queue currently empty */ |
689 | if (q->read_ptr == q->write_ptr && trans_pcie->wd_timeout) | |
690 | mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout); | |
691 | ||
fd4abac5 TW |
692 | /* Increment and update queue's write index */ |
693 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
990aa6d7 | 694 | iwl_pcie_txq_inc_wr_ptr(trans, txq); |
fd4abac5 | 695 | |
2c46f72e | 696 | out: |
015c15e1 | 697 | spin_unlock_bh(&txq->lock); |
f4feb8ac JB |
698 | free_dup_buf: |
699 | if (idx < 0) | |
700 | kfree(dup_buf); | |
7bfedc59 | 701 | return idx; |
fd4abac5 TW |
702 | } |
703 | ||
7c5ba4a8 | 704 | static inline void iwl_queue_progress(struct iwl_trans_pcie *trans_pcie, |
990aa6d7 | 705 | struct iwl_txq *txq) |
7c5ba4a8 JB |
706 | { |
707 | if (!trans_pcie->wd_timeout) | |
708 | return; | |
709 | ||
710 | /* | |
711 | * if empty delete timer, otherwise move timer forward | |
712 | * since we're making progress on this queue | |
713 | */ | |
714 | if (txq->q.read_ptr == txq->q.write_ptr) | |
715 | del_timer(&txq->stuck_timer); | |
716 | else | |
717 | mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout); | |
718 | } | |
719 | ||
990aa6d7 | 720 | /* |
17b88929 TW |
721 | * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd |
722 | * | |
723 | * When FW advances 'R' index, all entries between old and new 'R' index | |
724 | * need to be reclaimed. As result, some free space forms. If there is | |
725 | * enough free space (> low mark), wake the stack that feeds us. | |
726 | */ | |
3e10caeb EG |
727 | static void iwl_hcmd_queue_reclaim(struct iwl_trans *trans, int txq_id, |
728 | int idx) | |
17b88929 | 729 | { |
3e10caeb | 730 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 731 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; |
17b88929 TW |
732 | struct iwl_queue *q = &txq->q; |
733 | int nfreed = 0; | |
734 | ||
015c15e1 JB |
735 | lockdep_assert_held(&txq->lock); |
736 | ||
499b1883 | 737 | if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) { |
20d3b647 JB |
738 | IWL_ERR(trans, |
739 | "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n", | |
740 | __func__, txq_id, idx, q->n_bd, | |
741 | q->write_ptr, q->read_ptr); | |
17b88929 TW |
742 | return; |
743 | } | |
744 | ||
499b1883 TW |
745 | for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; |
746 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
17b88929 | 747 | |
499b1883 | 748 | if (nfreed++ > 0) { |
20d3b647 JB |
749 | IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", |
750 | idx, q->write_ptr, q->read_ptr); | |
bcb9321c | 751 | iwl_op_mode_nic_error(trans->op_mode); |
17b88929 | 752 | } |
da99c4b6 | 753 | |
17b88929 | 754 | } |
7c5ba4a8 JB |
755 | |
756 | iwl_queue_progress(trans_pcie, txq); | |
17b88929 TW |
757 | } |
758 | ||
990aa6d7 EG |
759 | /* |
760 | * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them | |
17b88929 | 761 | * @rxb: Rx buffer to reclaim |
247c61d6 EG |
762 | * @handler_status: return value of the handler of the command |
763 | * (put in setup_rx_handlers) | |
17b88929 TW |
764 | * |
765 | * If an Rx buffer has an async callback associated with it the callback | |
766 | * will be executed. The attached skb (if present) will only be freed | |
767 | * if the callback returns 1 | |
768 | */ | |
990aa6d7 EG |
769 | void iwl_pcie_hcmd_complete(struct iwl_trans *trans, |
770 | struct iwl_rx_cmd_buffer *rxb, int handler_status) | |
17b88929 | 771 | { |
2f301227 | 772 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
17b88929 TW |
773 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
774 | int txq_id = SEQ_TO_QUEUE(sequence); | |
775 | int index = SEQ_TO_INDEX(sequence); | |
17b88929 | 776 | int cmd_index; |
c2acea8e JB |
777 | struct iwl_device_cmd *cmd; |
778 | struct iwl_cmd_meta *meta; | |
8ad71bef | 779 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 780 | struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
17b88929 TW |
781 | |
782 | /* If a Tx command is being handled and it isn't in the actual | |
783 | * command queue then there a command routing bug has been introduced | |
784 | * in the queue management code. */ | |
c6f600fc | 785 | if (WARN(txq_id != trans_pcie->cmd_queue, |
13bb9483 | 786 | "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", |
20d3b647 JB |
787 | txq_id, trans_pcie->cmd_queue, sequence, |
788 | trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr, | |
789 | trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) { | |
3e10caeb | 790 | iwl_print_hex_error(trans, pkt, 32); |
55d6a3cd | 791 | return; |
01ef9323 | 792 | } |
17b88929 | 793 | |
015c15e1 JB |
794 | spin_lock(&txq->lock); |
795 | ||
4ce7cc2b | 796 | cmd_index = get_cmd_index(&txq->q, index); |
bf8440e6 JB |
797 | cmd = txq->entries[cmd_index].cmd; |
798 | meta = &txq->entries[cmd_index].meta; | |
17b88929 | 799 | |
eec373f0 | 800 | iwl_unmap_tfd(trans, meta, &txq->tfds[index], DMA_BIDIRECTIONAL); |
c33de625 | 801 | |
17b88929 | 802 | /* Input error checking is done when commands are added to queue. */ |
c2acea8e | 803 | if (meta->flags & CMD_WANT_SKB) { |
48a2d66f | 804 | struct page *p = rxb_steal_page(rxb); |
65b94a4a | 805 | |
65b94a4a JB |
806 | meta->source->resp_pkt = pkt; |
807 | meta->source->_rx_page_addr = (unsigned long)page_address(p); | |
b2cf410c | 808 | meta->source->_rx_page_order = trans_pcie->rx_page_order; |
247c61d6 | 809 | meta->source->handler_status = handler_status; |
247c61d6 | 810 | } |
2624e96c | 811 | |
3e10caeb | 812 | iwl_hcmd_queue_reclaim(trans, txq_id, index); |
17b88929 | 813 | |
c2acea8e | 814 | if (!(meta->flags & CMD_ASYNC)) { |
74fda971 | 815 | if (!test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) { |
05c89b91 WYG |
816 | IWL_WARN(trans, |
817 | "HCMD_ACTIVE already clear for command %s\n", | |
990aa6d7 | 818 | get_cmd_string(trans_pcie, cmd->hdr.cmd)); |
05c89b91 | 819 | } |
74fda971 | 820 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); |
6d8f6eeb | 821 | IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", |
990aa6d7 | 822 | get_cmd_string(trans_pcie, cmd->hdr.cmd)); |
f946b529 | 823 | wake_up(&trans_pcie->wait_command_queue); |
17b88929 | 824 | } |
3598e177 | 825 | |
dd487449 | 826 | meta->flags = 0; |
3598e177 | 827 | |
015c15e1 | 828 | spin_unlock(&txq->lock); |
17b88929 | 829 | } |
253a634c | 830 | |
253a634c EG |
831 | #define HOST_COMPLETE_TIMEOUT (2 * HZ) |
832 | ||
6d8f6eeb | 833 | static int iwl_send_cmd_async(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c | 834 | { |
d9fb6465 | 835 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
253a634c EG |
836 | int ret; |
837 | ||
838 | /* An asynchronous command can not expect an SKB to be set. */ | |
839 | if (WARN_ON(cmd->flags & CMD_WANT_SKB)) | |
840 | return -EINVAL; | |
841 | ||
253a634c | 842 | |
6d8f6eeb | 843 | ret = iwl_enqueue_hcmd(trans, cmd); |
253a634c | 844 | if (ret < 0) { |
721c32f7 | 845 | IWL_ERR(trans, |
b36b110c | 846 | "Error sending %s: enqueue_hcmd failed: %d\n", |
990aa6d7 | 847 | get_cmd_string(trans_pcie, cmd->id), ret); |
253a634c EG |
848 | return ret; |
849 | } | |
850 | return 0; | |
851 | } | |
852 | ||
6d8f6eeb | 853 | static int iwl_send_cmd_sync(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c | 854 | { |
8ad71bef | 855 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
253a634c EG |
856 | int cmd_idx; |
857 | int ret; | |
858 | ||
6d8f6eeb | 859 | IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", |
990aa6d7 | 860 | get_cmd_string(trans_pcie, cmd->id)); |
253a634c | 861 | |
2cc39c94 | 862 | if (WARN_ON(test_and_set_bit(STATUS_HCMD_ACTIVE, |
74fda971 | 863 | &trans_pcie->status))) { |
2cc39c94 | 864 | IWL_ERR(trans, "Command %s: a command is already active!\n", |
990aa6d7 | 865 | get_cmd_string(trans_pcie, cmd->id)); |
2cc39c94 JB |
866 | return -EIO; |
867 | } | |
868 | ||
6d8f6eeb | 869 | IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", |
990aa6d7 | 870 | get_cmd_string(trans_pcie, cmd->id)); |
253a634c | 871 | |
6d8f6eeb | 872 | cmd_idx = iwl_enqueue_hcmd(trans, cmd); |
253a634c EG |
873 | if (cmd_idx < 0) { |
874 | ret = cmd_idx; | |
74fda971 | 875 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); |
721c32f7 | 876 | IWL_ERR(trans, |
b36b110c | 877 | "Error sending %s: enqueue_hcmd failed: %d\n", |
990aa6d7 | 878 | get_cmd_string(trans_pcie, cmd->id), ret); |
253a634c EG |
879 | return ret; |
880 | } | |
881 | ||
f946b529 | 882 | ret = wait_event_timeout(trans_pcie->wait_command_queue, |
20d3b647 JB |
883 | !test_bit(STATUS_HCMD_ACTIVE, |
884 | &trans_pcie->status), | |
885 | HOST_COMPLETE_TIMEOUT); | |
253a634c | 886 | if (!ret) { |
74fda971 | 887 | if (test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) { |
990aa6d7 | 888 | struct iwl_txq *txq = |
c6f600fc | 889 | &trans_pcie->txq[trans_pcie->cmd_queue]; |
d10630af WYG |
890 | struct iwl_queue *q = &txq->q; |
891 | ||
721c32f7 | 892 | IWL_ERR(trans, |
253a634c | 893 | "Error sending %s: time out after %dms.\n", |
990aa6d7 | 894 | get_cmd_string(trans_pcie, cmd->id), |
253a634c EG |
895 | jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); |
896 | ||
721c32f7 | 897 | IWL_ERR(trans, |
d10630af WYG |
898 | "Current CMD queue read_ptr %d write_ptr %d\n", |
899 | q->read_ptr, q->write_ptr); | |
900 | ||
74fda971 | 901 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); |
d9fb6465 JB |
902 | IWL_DEBUG_INFO(trans, |
903 | "Clearing HCMD_ACTIVE for command %s\n", | |
990aa6d7 | 904 | get_cmd_string(trans_pcie, cmd->id)); |
253a634c EG |
905 | ret = -ETIMEDOUT; |
906 | goto cancel; | |
907 | } | |
908 | } | |
909 | ||
d18aa87f JB |
910 | if (test_bit(STATUS_FW_ERROR, &trans_pcie->status)) { |
911 | IWL_ERR(trans, "FW error in SYNC CMD %s\n", | |
990aa6d7 | 912 | get_cmd_string(trans_pcie, cmd->id)); |
d18aa87f JB |
913 | ret = -EIO; |
914 | goto cancel; | |
915 | } | |
916 | ||
f946b529 EG |
917 | if (test_bit(STATUS_RFKILL, &trans_pcie->status)) { |
918 | IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n"); | |
919 | ret = -ERFKILL; | |
920 | goto cancel; | |
921 | } | |
922 | ||
65b94a4a | 923 | if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) { |
6d8f6eeb | 924 | IWL_ERR(trans, "Error: Response NULL in '%s'\n", |
990aa6d7 | 925 | get_cmd_string(trans_pcie, cmd->id)); |
253a634c EG |
926 | ret = -EIO; |
927 | goto cancel; | |
928 | } | |
929 | ||
930 | return 0; | |
931 | ||
932 | cancel: | |
933 | if (cmd->flags & CMD_WANT_SKB) { | |
934 | /* | |
935 | * Cancel the CMD_WANT_SKB flag for the cmd in the | |
936 | * TX cmd queue. Otherwise in case the cmd comes | |
937 | * in later, it will possibly set an invalid | |
938 | * address (cmd->meta.source). | |
939 | */ | |
bf8440e6 JB |
940 | trans_pcie->txq[trans_pcie->cmd_queue]. |
941 | entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB; | |
253a634c | 942 | } |
9cac4943 | 943 | |
65b94a4a JB |
944 | if (cmd->resp_pkt) { |
945 | iwl_free_resp(cmd); | |
946 | cmd->resp_pkt = NULL; | |
253a634c EG |
947 | } |
948 | ||
949 | return ret; | |
950 | } | |
951 | ||
990aa6d7 | 952 | int iwl_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c | 953 | { |
f946b529 EG |
954 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
955 | ||
d18aa87f JB |
956 | if (test_bit(STATUS_FW_ERROR, &trans_pcie->status)) |
957 | return -EIO; | |
958 | ||
f946b529 EG |
959 | if (test_bit(STATUS_RFKILL, &trans_pcie->status)) |
960 | return -ERFKILL; | |
961 | ||
253a634c | 962 | if (cmd->flags & CMD_ASYNC) |
6d8f6eeb | 963 | return iwl_send_cmd_async(trans, cmd); |
253a634c | 964 | |
f946b529 | 965 | /* We still can fail on RFKILL that can be asserted while we wait */ |
6d8f6eeb | 966 | return iwl_send_cmd_sync(trans, cmd); |
253a634c EG |
967 | } |
968 | ||
a0eaad71 | 969 | /* Frees buffers until index _not_ inclusive */ |
990aa6d7 | 970 | int iwl_pcie_txq_reclaim(struct iwl_trans *trans, int txq_id, int index, |
464021ff | 971 | struct sk_buff_head *skbs) |
a0eaad71 | 972 | { |
8ad71bef | 973 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 974 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; |
a0eaad71 | 975 | struct iwl_queue *q = &txq->q; |
a0eaad71 | 976 | int last_to_free; |
464021ff | 977 | int freed = 0; |
a0eaad71 | 978 | |
39644e9a | 979 | /* This function is not meant to release cmd queue*/ |
c6f600fc | 980 | if (WARN_ON(txq_id == trans_pcie->cmd_queue)) |
39644e9a EG |
981 | return 0; |
982 | ||
015c15e1 JB |
983 | lockdep_assert_held(&txq->lock); |
984 | ||
a0eaad71 EG |
985 | /*Since we free until index _not_ inclusive, the one before index is |
986 | * the last we will free. This one must be used */ | |
987 | last_to_free = iwl_queue_dec_wrap(index, q->n_bd); | |
988 | ||
989 | if ((index >= q->n_bd) || | |
990 | (iwl_queue_used(q, last_to_free) == 0)) { | |
20d3b647 JB |
991 | IWL_ERR(trans, |
992 | "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n", | |
993 | __func__, txq_id, last_to_free, q->n_bd, | |
994 | q->write_ptr, q->read_ptr); | |
464021ff | 995 | return 0; |
a0eaad71 EG |
996 | } |
997 | ||
a0eaad71 | 998 | if (WARN_ON(!skb_queue_empty(skbs))) |
464021ff | 999 | return 0; |
a0eaad71 EG |
1000 | |
1001 | for (; | |
1002 | q->read_ptr != index; | |
1003 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
1004 | ||
bf8440e6 | 1005 | if (WARN_ON_ONCE(txq->entries[txq->q.read_ptr].skb == NULL)) |
a0eaad71 EG |
1006 | continue; |
1007 | ||
bf8440e6 | 1008 | __skb_queue_tail(skbs, txq->entries[txq->q.read_ptr].skb); |
a0eaad71 | 1009 | |
bf8440e6 | 1010 | txq->entries[txq->q.read_ptr].skb = NULL; |
a0eaad71 | 1011 | |
6d8f6eeb | 1012 | iwlagn_txq_inval_byte_cnt_tbl(trans, txq); |
a0eaad71 | 1013 | |
990aa6d7 | 1014 | iwl_pcie_txq_free_tfd(trans, txq, DMA_TO_DEVICE); |
464021ff | 1015 | freed++; |
a0eaad71 | 1016 | } |
7c5ba4a8 JB |
1017 | |
1018 | iwl_queue_progress(trans_pcie, txq); | |
1019 | ||
464021ff | 1020 | return freed; |
a0eaad71 | 1021 | } |