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1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
128e63ef | 3 | * Copyright(c) 2003 - 2013 Intel Corporation. All rights reserved. |
1053d35f RR |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
1053d35f RR |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
fd4abac5 | 29 | #include <linux/etherdevice.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
253a634c | 31 | #include <linux/sched.h> |
253a634c | 32 | |
522376d2 EG |
33 | #include "iwl-debug.h" |
34 | #include "iwl-csr.h" | |
35 | #include "iwl-prph.h" | |
1053d35f | 36 | #include "iwl-io.h" |
ed277c93 | 37 | #include "iwl-op-mode.h" |
6468a01a | 38 | #include "internal.h" |
6238b008 | 39 | /* FIXME: need to abstract out TX command (once we know what it looks like) */ |
1023fdc4 | 40 | #include "dvm/commands.h" |
1053d35f | 41 | |
522376d2 EG |
42 | #define IWL_TX_CRC_SIZE 4 |
43 | #define IWL_TX_DELIMITER_SIZE 4 | |
44 | ||
f02831be EG |
45 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
46 | * DMA services | |
47 | * | |
48 | * Theory of operation | |
49 | * | |
50 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
51 | * of buffer descriptors, each of which points to one or more data buffers for | |
52 | * the device to read from or fill. Driver and device exchange status of each | |
53 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
54 | * entries in each circular buffer, to protect against confusing empty and full | |
55 | * queue states. | |
56 | * | |
57 | * The device reads or writes the data in the queues via the device's several | |
58 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
59 | * | |
60 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
61 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
62 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
63 | * Tx queue resumed. | |
64 | * | |
65 | ***************************************************/ | |
66 | static int iwl_queue_space(const struct iwl_queue *q) | |
67 | { | |
68 | int s = q->read_ptr - q->write_ptr; | |
69 | ||
70 | if (q->read_ptr > q->write_ptr) | |
71 | s -= q->n_bd; | |
72 | ||
73 | if (s <= 0) | |
74 | s += q->n_window; | |
75 | /* keep some reserve to not confuse empty and full situations */ | |
76 | s -= 2; | |
77 | if (s < 0) | |
78 | s = 0; | |
79 | return s; | |
80 | } | |
81 | ||
82 | /* | |
83 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes | |
84 | */ | |
85 | static int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id) | |
86 | { | |
87 | q->n_bd = count; | |
88 | q->n_window = slots_num; | |
89 | q->id = id; | |
90 | ||
91 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap | |
92 | * and iwl_queue_dec_wrap are broken. */ | |
93 | if (WARN_ON(!is_power_of_2(count))) | |
94 | return -EINVAL; | |
95 | ||
96 | /* slots_num must be power-of-two size, otherwise | |
97 | * get_cmd_index is broken. */ | |
98 | if (WARN_ON(!is_power_of_2(slots_num))) | |
99 | return -EINVAL; | |
100 | ||
101 | q->low_mark = q->n_window / 4; | |
102 | if (q->low_mark < 4) | |
103 | q->low_mark = 4; | |
104 | ||
105 | q->high_mark = q->n_window / 8; | |
106 | if (q->high_mark < 2) | |
107 | q->high_mark = 2; | |
108 | ||
109 | q->write_ptr = 0; | |
110 | q->read_ptr = 0; | |
111 | ||
112 | return 0; | |
113 | } | |
114 | ||
f02831be EG |
115 | static int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans, |
116 | struct iwl_dma_ptr *ptr, size_t size) | |
117 | { | |
118 | if (WARN_ON(ptr->addr)) | |
119 | return -EINVAL; | |
120 | ||
121 | ptr->addr = dma_alloc_coherent(trans->dev, size, | |
122 | &ptr->dma, GFP_KERNEL); | |
123 | if (!ptr->addr) | |
124 | return -ENOMEM; | |
125 | ptr->size = size; | |
126 | return 0; | |
127 | } | |
128 | ||
129 | static void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, | |
130 | struct iwl_dma_ptr *ptr) | |
131 | { | |
132 | if (unlikely(!ptr->addr)) | |
133 | return; | |
134 | ||
135 | dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma); | |
136 | memset(ptr, 0, sizeof(*ptr)); | |
137 | } | |
138 | ||
139 | static void iwl_pcie_txq_stuck_timer(unsigned long data) | |
140 | { | |
141 | struct iwl_txq *txq = (void *)data; | |
142 | struct iwl_queue *q = &txq->q; | |
143 | struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; | |
144 | struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie); | |
145 | u32 scd_sram_addr = trans_pcie->scd_base_addr + | |
146 | SCD_TX_STTS_QUEUE_OFFSET(txq->q.id); | |
147 | u8 buf[16]; | |
148 | int i; | |
149 | ||
150 | spin_lock(&txq->lock); | |
151 | /* check if triggered erroneously */ | |
152 | if (txq->q.read_ptr == txq->q.write_ptr) { | |
153 | spin_unlock(&txq->lock); | |
154 | return; | |
155 | } | |
156 | spin_unlock(&txq->lock); | |
157 | ||
158 | IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id, | |
159 | jiffies_to_msecs(trans_pcie->wd_timeout)); | |
160 | IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", | |
161 | txq->q.read_ptr, txq->q.write_ptr); | |
162 | ||
4fd442db | 163 | iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf)); |
f02831be EG |
164 | |
165 | iwl_print_hex_error(trans, buf, sizeof(buf)); | |
166 | ||
167 | for (i = 0; i < FH_TCSR_CHNL_NUM; i++) | |
168 | IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i, | |
169 | iwl_read_direct32(trans, FH_TX_TRB_REG(i))); | |
170 | ||
171 | for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { | |
172 | u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i)); | |
173 | u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; | |
174 | bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); | |
175 | u32 tbl_dw = | |
4fd442db EG |
176 | iwl_trans_read_mem32(trans, |
177 | trans_pcie->scd_base_addr + | |
178 | SCD_TRANS_TBL_OFFSET_QUEUE(i)); | |
f02831be EG |
179 | |
180 | if (i & 0x1) | |
181 | tbl_dw = (tbl_dw & 0xFFFF0000) >> 16; | |
182 | else | |
183 | tbl_dw = tbl_dw & 0x0000FFFF; | |
184 | ||
185 | IWL_ERR(trans, | |
186 | "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n", | |
187 | i, active ? "" : "in", fifo, tbl_dw, | |
188 | iwl_read_prph(trans, | |
189 | SCD_QUEUE_RDPTR(i)) & (txq->q.n_bd - 1), | |
190 | iwl_read_prph(trans, SCD_QUEUE_WRPTR(i))); | |
191 | } | |
192 | ||
193 | for (i = q->read_ptr; i != q->write_ptr; | |
38c0f334 | 194 | i = iwl_queue_inc_wrap(i, q->n_bd)) |
f02831be | 195 | IWL_ERR(trans, "scratch %d = 0x%08x\n", i, |
38c0f334 | 196 | le32_to_cpu(txq->scratchbufs[i].scratch)); |
f02831be EG |
197 | |
198 | iwl_op_mode_nic_error(trans->op_mode); | |
199 | } | |
200 | ||
990aa6d7 EG |
201 | /* |
202 | * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array | |
48d42c42 | 203 | */ |
f02831be EG |
204 | static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans, |
205 | struct iwl_txq *txq, u16 byte_cnt) | |
48d42c42 | 206 | { |
105183b1 | 207 | struct iwlagn_scd_bc_tbl *scd_bc_tbl; |
20d3b647 | 208 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
48d42c42 EG |
209 | int write_ptr = txq->q.write_ptr; |
210 | int txq_id = txq->q.id; | |
211 | u8 sec_ctl = 0; | |
212 | u8 sta_id = 0; | |
213 | u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; | |
214 | __le16 bc_ent; | |
132f98c2 | 215 | struct iwl_tx_cmd *tx_cmd = |
bf8440e6 | 216 | (void *) txq->entries[txq->q.write_ptr].cmd->payload; |
48d42c42 | 217 | |
105183b1 EG |
218 | scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; |
219 | ||
48d42c42 EG |
220 | WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX); |
221 | ||
132f98c2 EG |
222 | sta_id = tx_cmd->sta_id; |
223 | sec_ctl = tx_cmd->sec_ctl; | |
48d42c42 EG |
224 | |
225 | switch (sec_ctl & TX_CMD_SEC_MSK) { | |
226 | case TX_CMD_SEC_CCM: | |
4325f6ca | 227 | len += IEEE80211_CCMP_MIC_LEN; |
48d42c42 EG |
228 | break; |
229 | case TX_CMD_SEC_TKIP: | |
4325f6ca | 230 | len += IEEE80211_TKIP_ICV_LEN; |
48d42c42 EG |
231 | break; |
232 | case TX_CMD_SEC_WEP: | |
4325f6ca | 233 | len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN; |
48d42c42 EG |
234 | break; |
235 | } | |
236 | ||
046db346 EG |
237 | if (trans_pcie->bc_table_dword) |
238 | len = DIV_ROUND_UP(len, 4); | |
239 | ||
240 | bc_ent = cpu_to_le16(len | (sta_id << 12)); | |
48d42c42 EG |
241 | |
242 | scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; | |
243 | ||
244 | if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
245 | scd_bc_tbl[txq_id]. | |
246 | tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; | |
247 | } | |
248 | ||
f02831be EG |
249 | static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans, |
250 | struct iwl_txq *txq) | |
251 | { | |
252 | struct iwl_trans_pcie *trans_pcie = | |
253 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
254 | struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; | |
255 | int txq_id = txq->q.id; | |
256 | int read_ptr = txq->q.read_ptr; | |
257 | u8 sta_id = 0; | |
258 | __le16 bc_ent; | |
259 | struct iwl_tx_cmd *tx_cmd = | |
260 | (void *)txq->entries[txq->q.read_ptr].cmd->payload; | |
261 | ||
262 | WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); | |
263 | ||
264 | if (txq_id != trans_pcie->cmd_queue) | |
265 | sta_id = tx_cmd->sta_id; | |
266 | ||
267 | bc_ent = cpu_to_le16(1 | (sta_id << 12)); | |
268 | scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; | |
269 | ||
270 | if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
271 | scd_bc_tbl[txq_id]. | |
272 | tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; | |
273 | } | |
274 | ||
990aa6d7 EG |
275 | /* |
276 | * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware | |
fd4abac5 | 277 | */ |
990aa6d7 | 278 | void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_txq *txq) |
fd4abac5 TW |
279 | { |
280 | u32 reg = 0; | |
fd4abac5 TW |
281 | int txq_id = txq->q.id; |
282 | ||
283 | if (txq->need_update == 0) | |
7bfedc59 | 284 | return; |
fd4abac5 | 285 | |
035f7ff2 | 286 | if (trans->cfg->base_params->shadow_reg_enable) { |
f81c1f48 | 287 | /* shadow register enabled */ |
1042db2a | 288 | iwl_write32(trans, HBUS_TARG_WRPTR, |
f81c1f48 WYG |
289 | txq->q.write_ptr | (txq_id << 8)); |
290 | } else { | |
47107e84 DF |
291 | struct iwl_trans_pcie *trans_pcie = |
292 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
f81c1f48 | 293 | /* if we're trying to save power */ |
01d651d4 | 294 | if (test_bit(STATUS_TPOWER_PMI, &trans_pcie->status)) { |
f81c1f48 WYG |
295 | /* wake up nic if it's powered down ... |
296 | * uCode will wake up, and interrupt us again, so next | |
297 | * time we'll skip this part. */ | |
1042db2a | 298 | reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); |
fd4abac5 | 299 | |
f81c1f48 | 300 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { |
fd656935 | 301 | IWL_DEBUG_INFO(trans, |
f81c1f48 WYG |
302 | "Tx queue %d requesting wakeup," |
303 | " GP1 = 0x%x\n", txq_id, reg); | |
1042db2a | 304 | iwl_set_bit(trans, CSR_GP_CNTRL, |
f81c1f48 WYG |
305 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
306 | return; | |
307 | } | |
fd4abac5 | 308 | |
1c3fea82 EG |
309 | IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, |
310 | txq->q.write_ptr); | |
311 | ||
1042db2a | 312 | iwl_write_direct32(trans, HBUS_TARG_WRPTR, |
fd4abac5 | 313 | txq->q.write_ptr | (txq_id << 8)); |
fd4abac5 | 314 | |
f81c1f48 WYG |
315 | /* |
316 | * else not in power-save mode, | |
317 | * uCode will never sleep when we're | |
318 | * trying to tx (during RFKILL, we're not trying to tx). | |
319 | */ | |
320 | } else | |
1042db2a | 321 | iwl_write32(trans, HBUS_TARG_WRPTR, |
f81c1f48 WYG |
322 | txq->q.write_ptr | (txq_id << 8)); |
323 | } | |
fd4abac5 | 324 | txq->need_update = 0; |
fd4abac5 | 325 | } |
fd4abac5 | 326 | |
f02831be | 327 | static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
214d14d4 JB |
328 | { |
329 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
330 | ||
331 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
332 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
333 | addr |= | |
334 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
335 | ||
336 | return addr; | |
337 | } | |
338 | ||
f02831be | 339 | static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) |
214d14d4 JB |
340 | { |
341 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
342 | ||
343 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
344 | } | |
345 | ||
f02831be EG |
346 | static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, |
347 | dma_addr_t addr, u16 len) | |
214d14d4 JB |
348 | { |
349 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
350 | u16 hi_n_len = len << 4; | |
351 | ||
352 | put_unaligned_le32(addr, &tb->lo); | |
353 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
354 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
355 | ||
356 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
357 | ||
358 | tfd->num_tbs = idx + 1; | |
359 | } | |
360 | ||
f02831be | 361 | static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_tfd *tfd) |
214d14d4 JB |
362 | { |
363 | return tfd->num_tbs & 0x1f; | |
364 | } | |
365 | ||
f02831be | 366 | static void iwl_pcie_tfd_unmap(struct iwl_trans *trans, |
98891754 JB |
367 | struct iwl_cmd_meta *meta, |
368 | struct iwl_tfd *tfd) | |
214d14d4 | 369 | { |
214d14d4 JB |
370 | int i; |
371 | int num_tbs; | |
372 | ||
214d14d4 | 373 | /* Sanity check on number of chunks */ |
f02831be | 374 | num_tbs = iwl_pcie_tfd_get_num_tbs(tfd); |
214d14d4 JB |
375 | |
376 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
6d8f6eeb | 377 | IWL_ERR(trans, "Too many chunks: %i\n", num_tbs); |
214d14d4 JB |
378 | /* @todo issue fatal error, it is quite serious situation */ |
379 | return; | |
380 | } | |
381 | ||
38c0f334 | 382 | /* first TB is never freed - it's the scratchbuf data */ |
214d14d4 | 383 | |
214d14d4 | 384 | for (i = 1; i < num_tbs; i++) |
f02831be | 385 | dma_unmap_single(trans->dev, iwl_pcie_tfd_tb_get_addr(tfd, i), |
98891754 JB |
386 | iwl_pcie_tfd_tb_get_len(tfd, i), |
387 | DMA_TO_DEVICE); | |
ebed633c EG |
388 | |
389 | tfd->num_tbs = 0; | |
4ce7cc2b JB |
390 | } |
391 | ||
990aa6d7 EG |
392 | /* |
393 | * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
6d8f6eeb | 394 | * @trans - transport private data |
4ce7cc2b | 395 | * @txq - tx queue |
ebed633c | 396 | * @dma_dir - the direction of the DMA mapping |
4ce7cc2b JB |
397 | * |
398 | * Does NOT advance any TFD circular buffer read/write indexes | |
399 | * Does NOT free the TFD itself (which is within circular buffer) | |
400 | */ | |
98891754 | 401 | static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq) |
4ce7cc2b JB |
402 | { |
403 | struct iwl_tfd *tfd_tmp = txq->tfds; | |
4ce7cc2b | 404 | |
ebed633c EG |
405 | /* rd_ptr is bounded by n_bd and idx is bounded by n_window */ |
406 | int rd_ptr = txq->q.read_ptr; | |
407 | int idx = get_cmd_index(&txq->q, rd_ptr); | |
408 | ||
015c15e1 JB |
409 | lockdep_assert_held(&txq->lock); |
410 | ||
ebed633c | 411 | /* We have only q->n_window txq->entries, but we use q->n_bd tfds */ |
98891754 | 412 | iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr]); |
214d14d4 JB |
413 | |
414 | /* free SKB */ | |
bf8440e6 | 415 | if (txq->entries) { |
214d14d4 JB |
416 | struct sk_buff *skb; |
417 | ||
ebed633c | 418 | skb = txq->entries[idx].skb; |
214d14d4 | 419 | |
909e9b23 EG |
420 | /* Can be called from irqs-disabled context |
421 | * If skb is not NULL, it means that the whole queue is being | |
422 | * freed and that the queue is not empty - free the skb | |
423 | */ | |
214d14d4 | 424 | if (skb) { |
ed277c93 | 425 | iwl_op_mode_free_skb(trans->op_mode, skb); |
ebed633c | 426 | txq->entries[idx].skb = NULL; |
214d14d4 JB |
427 | } |
428 | } | |
429 | } | |
430 | ||
f02831be EG |
431 | static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq, |
432 | dma_addr_t addr, u16 len, u8 reset) | |
214d14d4 JB |
433 | { |
434 | struct iwl_queue *q; | |
435 | struct iwl_tfd *tfd, *tfd_tmp; | |
436 | u32 num_tbs; | |
437 | ||
438 | q = &txq->q; | |
4ce7cc2b | 439 | tfd_tmp = txq->tfds; |
214d14d4 JB |
440 | tfd = &tfd_tmp[q->write_ptr]; |
441 | ||
f02831be EG |
442 | if (reset) |
443 | memset(tfd, 0, sizeof(*tfd)); | |
444 | ||
445 | num_tbs = iwl_pcie_tfd_get_num_tbs(tfd); | |
446 | ||
447 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
448 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
449 | IWL_ERR(trans, "Error can not send more than %d chunks\n", | |
450 | IWL_NUM_OF_TBS); | |
451 | return -EINVAL; | |
452 | } | |
453 | ||
454 | if (WARN_ON(addr & ~DMA_BIT_MASK(36))) | |
455 | return -EINVAL; | |
456 | ||
457 | if (unlikely(addr & ~IWL_TX_DMA_MASK)) | |
458 | IWL_ERR(trans, "Unaligned address = %llx\n", | |
459 | (unsigned long long)addr); | |
460 | ||
461 | iwl_pcie_tfd_set_tb(tfd, num_tbs, addr, len); | |
462 | ||
463 | return 0; | |
464 | } | |
465 | ||
466 | static int iwl_pcie_txq_alloc(struct iwl_trans *trans, | |
467 | struct iwl_txq *txq, int slots_num, | |
468 | u32 txq_id) | |
469 | { | |
470 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
471 | size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX; | |
38c0f334 | 472 | size_t scratchbuf_sz; |
f02831be EG |
473 | int i; |
474 | ||
475 | if (WARN_ON(txq->entries || txq->tfds)) | |
476 | return -EINVAL; | |
477 | ||
478 | setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer, | |
479 | (unsigned long)txq); | |
480 | txq->trans_pcie = trans_pcie; | |
481 | ||
482 | txq->q.n_window = slots_num; | |
483 | ||
484 | txq->entries = kcalloc(slots_num, | |
485 | sizeof(struct iwl_pcie_txq_entry), | |
486 | GFP_KERNEL); | |
487 | ||
488 | if (!txq->entries) | |
489 | goto error; | |
490 | ||
491 | if (txq_id == trans_pcie->cmd_queue) | |
492 | for (i = 0; i < slots_num; i++) { | |
493 | txq->entries[i].cmd = | |
494 | kmalloc(sizeof(struct iwl_device_cmd), | |
495 | GFP_KERNEL); | |
496 | if (!txq->entries[i].cmd) | |
497 | goto error; | |
498 | } | |
499 | ||
500 | /* Circular buffer of transmit frame descriptors (TFDs), | |
501 | * shared with device */ | |
502 | txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz, | |
503 | &txq->q.dma_addr, GFP_KERNEL); | |
d0320f75 | 504 | if (!txq->tfds) |
f02831be | 505 | goto error; |
38c0f334 JB |
506 | |
507 | BUILD_BUG_ON(IWL_HCMD_SCRATCHBUF_SIZE != sizeof(*txq->scratchbufs)); | |
508 | BUILD_BUG_ON(offsetof(struct iwl_pcie_txq_scratch_buf, scratch) != | |
509 | sizeof(struct iwl_cmd_header) + | |
510 | offsetof(struct iwl_tx_cmd, scratch)); | |
511 | ||
512 | scratchbuf_sz = sizeof(*txq->scratchbufs) * slots_num; | |
513 | ||
514 | txq->scratchbufs = dma_alloc_coherent(trans->dev, scratchbuf_sz, | |
515 | &txq->scratchbufs_dma, | |
516 | GFP_KERNEL); | |
517 | if (!txq->scratchbufs) | |
518 | goto err_free_tfds; | |
519 | ||
f02831be EG |
520 | txq->q.id = txq_id; |
521 | ||
522 | return 0; | |
38c0f334 JB |
523 | err_free_tfds: |
524 | dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->q.dma_addr); | |
f02831be EG |
525 | error: |
526 | if (txq->entries && txq_id == trans_pcie->cmd_queue) | |
527 | for (i = 0; i < slots_num; i++) | |
528 | kfree(txq->entries[i].cmd); | |
529 | kfree(txq->entries); | |
530 | txq->entries = NULL; | |
531 | ||
532 | return -ENOMEM; | |
533 | ||
534 | } | |
535 | ||
536 | static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq, | |
537 | int slots_num, u32 txq_id) | |
538 | { | |
539 | int ret; | |
540 | ||
541 | txq->need_update = 0; | |
542 | ||
543 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise | |
544 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ | |
545 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); | |
546 | ||
547 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
548 | ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num, | |
549 | txq_id); | |
550 | if (ret) | |
551 | return ret; | |
552 | ||
553 | spin_lock_init(&txq->lock); | |
554 | ||
555 | /* | |
556 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
557 | * given Tx queue, and enable the DMA channel used for that queue. | |
558 | * Circular buffer (TFD queue in DRAM) physical base address */ | |
559 | iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id), | |
560 | txq->q.dma_addr >> 8); | |
561 | ||
562 | return 0; | |
563 | } | |
564 | ||
565 | /* | |
566 | * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's | |
567 | */ | |
568 | static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id) | |
569 | { | |
570 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
571 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
572 | struct iwl_queue *q = &txq->q; | |
f02831be EG |
573 | |
574 | if (!q->n_bd) | |
575 | return; | |
576 | ||
f02831be EG |
577 | spin_lock_bh(&txq->lock); |
578 | while (q->write_ptr != q->read_ptr) { | |
98891754 | 579 | iwl_pcie_txq_free_tfd(trans, txq); |
f02831be EG |
580 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd); |
581 | } | |
582 | spin_unlock_bh(&txq->lock); | |
583 | } | |
584 | ||
585 | /* | |
586 | * iwl_pcie_txq_free - Deallocate DMA queue. | |
587 | * @txq: Transmit queue to deallocate. | |
588 | * | |
589 | * Empty queue by removing and destroying all BD's. | |
590 | * Free all buffers. | |
591 | * 0-fill, but do not free "txq" descriptor structure. | |
592 | */ | |
593 | static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id) | |
594 | { | |
595 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
596 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
597 | struct device *dev = trans->dev; | |
598 | int i; | |
599 | ||
600 | if (WARN_ON(!txq)) | |
601 | return; | |
602 | ||
603 | iwl_pcie_txq_unmap(trans, txq_id); | |
604 | ||
605 | /* De-alloc array of command/tx buffers */ | |
606 | if (txq_id == trans_pcie->cmd_queue) | |
607 | for (i = 0; i < txq->q.n_window; i++) { | |
608 | kfree(txq->entries[i].cmd); | |
f02831be EG |
609 | kfree(txq->entries[i].free_buf); |
610 | } | |
611 | ||
612 | /* De-alloc circular buffer of TFDs */ | |
613 | if (txq->q.n_bd) { | |
614 | dma_free_coherent(dev, sizeof(struct iwl_tfd) * | |
615 | txq->q.n_bd, txq->tfds, txq->q.dma_addr); | |
d21fa2da | 616 | txq->q.dma_addr = 0; |
38c0f334 JB |
617 | |
618 | dma_free_coherent(dev, | |
619 | sizeof(*txq->scratchbufs) * txq->q.n_window, | |
620 | txq->scratchbufs, txq->scratchbufs_dma); | |
f02831be EG |
621 | } |
622 | ||
623 | kfree(txq->entries); | |
624 | txq->entries = NULL; | |
625 | ||
626 | del_timer_sync(&txq->stuck_timer); | |
627 | ||
628 | /* 0-fill queue descriptor structure */ | |
629 | memset(txq, 0, sizeof(*txq)); | |
630 | } | |
631 | ||
632 | /* | |
633 | * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask | |
634 | */ | |
635 | static void iwl_pcie_txq_set_sched(struct iwl_trans *trans, u32 mask) | |
636 | { | |
637 | struct iwl_trans_pcie __maybe_unused *trans_pcie = | |
638 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
639 | ||
640 | iwl_write_prph(trans, SCD_TXFACT, mask); | |
641 | } | |
642 | ||
643 | void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr) | |
644 | { | |
645 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
22dc3c95 | 646 | int nq = trans->cfg->base_params->num_of_queues; |
f02831be EG |
647 | int chan; |
648 | u32 reg_val; | |
22dc3c95 JB |
649 | int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) - |
650 | SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32); | |
f02831be EG |
651 | |
652 | /* make sure all queue are not stopped/used */ | |
653 | memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); | |
654 | memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); | |
655 | ||
656 | trans_pcie->scd_base_addr = | |
657 | iwl_read_prph(trans, SCD_SRAM_BASE_ADDR); | |
658 | ||
659 | WARN_ON(scd_base_addr != 0 && | |
660 | scd_base_addr != trans_pcie->scd_base_addr); | |
661 | ||
22dc3c95 JB |
662 | /* reset context data, TX status and translation data */ |
663 | iwl_trans_write_mem(trans, trans_pcie->scd_base_addr + | |
664 | SCD_CONTEXT_MEM_LOWER_BOUND, | |
665 | NULL, clear_dwords); | |
f02831be EG |
666 | |
667 | iwl_write_prph(trans, SCD_DRAM_BASE_ADDR, | |
668 | trans_pcie->scd_bc_tbls.dma >> 10); | |
669 | ||
670 | /* The chain extension of the SCD doesn't work well. This feature is | |
671 | * enabled by default by the HW, so we need to disable it manually. | |
672 | */ | |
673 | iwl_write_prph(trans, SCD_CHAINEXT_EN, 0); | |
674 | ||
675 | iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue, | |
676 | trans_pcie->cmd_fifo); | |
677 | ||
678 | /* Activate all Tx DMA/FIFO channels */ | |
679 | iwl_pcie_txq_set_sched(trans, IWL_MASK(0, 7)); | |
680 | ||
681 | /* Enable DMA channel */ | |
682 | for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++) | |
683 | iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan), | |
684 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
685 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); | |
686 | ||
687 | /* Update FH chicken bits */ | |
688 | reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG); | |
689 | iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG, | |
690 | reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); | |
691 | ||
692 | /* Enable L1-Active */ | |
693 | iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
694 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
695 | } | |
696 | ||
ddaf5a5b JB |
697 | void iwl_trans_pcie_tx_reset(struct iwl_trans *trans) |
698 | { | |
699 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
700 | int txq_id; | |
701 | ||
702 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
703 | txq_id++) { | |
704 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
705 | ||
706 | iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id), | |
707 | txq->q.dma_addr >> 8); | |
708 | iwl_pcie_txq_unmap(trans, txq_id); | |
709 | txq->q.read_ptr = 0; | |
710 | txq->q.write_ptr = 0; | |
711 | } | |
712 | ||
713 | /* Tell NIC where to find the "keep warm" buffer */ | |
714 | iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, | |
715 | trans_pcie->kw.dma >> 4); | |
716 | ||
717 | iwl_pcie_tx_start(trans, trans_pcie->scd_base_addr); | |
718 | } | |
719 | ||
f02831be EG |
720 | /* |
721 | * iwl_pcie_tx_stop - Stop all Tx DMA channels | |
722 | */ | |
723 | int iwl_pcie_tx_stop(struct iwl_trans *trans) | |
724 | { | |
725 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
726 | int ch, txq_id, ret; | |
727 | unsigned long flags; | |
728 | ||
729 | /* Turn off all Tx DMA fifos */ | |
730 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); | |
731 | ||
732 | iwl_pcie_txq_set_sched(trans, 0); | |
733 | ||
734 | /* Stop each Tx DMA channel, and wait for it to be idle */ | |
735 | for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { | |
736 | iwl_write_direct32(trans, | |
737 | FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); | |
738 | ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG, | |
739 | FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000); | |
740 | if (ret < 0) | |
741 | IWL_ERR(trans, | |
742 | "Failing on timeout while stopping DMA channel %d [0x%08x]\n", | |
743 | ch, | |
744 | iwl_read_direct32(trans, | |
745 | FH_TSSR_TX_STATUS_REG)); | |
746 | } | |
747 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); | |
748 | ||
749 | if (!trans_pcie->txq) { | |
750 | IWL_WARN(trans, | |
751 | "Stopping tx queues that aren't allocated...\n"); | |
752 | return 0; | |
753 | } | |
754 | ||
755 | /* Unmap DMA from host system and free skb's */ | |
756 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
757 | txq_id++) | |
758 | iwl_pcie_txq_unmap(trans, txq_id); | |
759 | ||
760 | return 0; | |
761 | } | |
762 | ||
763 | /* | |
764 | * iwl_trans_tx_free - Free TXQ Context | |
765 | * | |
766 | * Destroy all TX DMA queues and structures | |
767 | */ | |
768 | void iwl_pcie_tx_free(struct iwl_trans *trans) | |
769 | { | |
770 | int txq_id; | |
771 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
772 | ||
773 | /* Tx queues */ | |
774 | if (trans_pcie->txq) { | |
775 | for (txq_id = 0; | |
776 | txq_id < trans->cfg->base_params->num_of_queues; txq_id++) | |
777 | iwl_pcie_txq_free(trans, txq_id); | |
778 | } | |
779 | ||
780 | kfree(trans_pcie->txq); | |
781 | trans_pcie->txq = NULL; | |
782 | ||
783 | iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw); | |
784 | ||
785 | iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls); | |
786 | } | |
787 | ||
788 | /* | |
789 | * iwl_pcie_tx_alloc - allocate TX context | |
790 | * Allocate all Tx DMA structures and initialize them | |
791 | */ | |
792 | static int iwl_pcie_tx_alloc(struct iwl_trans *trans) | |
793 | { | |
794 | int ret; | |
795 | int txq_id, slots_num; | |
796 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
797 | ||
798 | u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues * | |
799 | sizeof(struct iwlagn_scd_bc_tbl); | |
800 | ||
801 | /*It is not allowed to alloc twice, so warn when this happens. | |
802 | * We cannot rely on the previous allocation, so free and fail */ | |
803 | if (WARN_ON(trans_pcie->txq)) { | |
804 | ret = -EINVAL; | |
805 | goto error; | |
806 | } | |
807 | ||
808 | ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls, | |
809 | scd_bc_tbls_size); | |
810 | if (ret) { | |
811 | IWL_ERR(trans, "Scheduler BC Table allocation failed\n"); | |
812 | goto error; | |
813 | } | |
814 | ||
815 | /* Alloc keep-warm buffer */ | |
816 | ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE); | |
817 | if (ret) { | |
818 | IWL_ERR(trans, "Keep Warm allocation failed\n"); | |
819 | goto error; | |
820 | } | |
821 | ||
822 | trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues, | |
823 | sizeof(struct iwl_txq), GFP_KERNEL); | |
824 | if (!trans_pcie->txq) { | |
825 | IWL_ERR(trans, "Not enough memory for txq\n"); | |
826 | ret = ENOMEM; | |
827 | goto error; | |
828 | } | |
829 | ||
830 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
831 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
832 | txq_id++) { | |
833 | slots_num = (txq_id == trans_pcie->cmd_queue) ? | |
834 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
835 | ret = iwl_pcie_txq_alloc(trans, &trans_pcie->txq[txq_id], | |
836 | slots_num, txq_id); | |
837 | if (ret) { | |
838 | IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id); | |
839 | goto error; | |
840 | } | |
841 | } | |
842 | ||
843 | return 0; | |
844 | ||
845 | error: | |
846 | iwl_pcie_tx_free(trans); | |
847 | ||
848 | return ret; | |
849 | } | |
850 | int iwl_pcie_tx_init(struct iwl_trans *trans) | |
851 | { | |
852 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
853 | int ret; | |
854 | int txq_id, slots_num; | |
855 | unsigned long flags; | |
856 | bool alloc = false; | |
857 | ||
858 | if (!trans_pcie->txq) { | |
859 | ret = iwl_pcie_tx_alloc(trans); | |
860 | if (ret) | |
861 | goto error; | |
862 | alloc = true; | |
863 | } | |
864 | ||
865 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); | |
866 | ||
867 | /* Turn off all Tx DMA fifos */ | |
868 | iwl_write_prph(trans, SCD_TXFACT, 0); | |
869 | ||
870 | /* Tell NIC where to find the "keep warm" buffer */ | |
871 | iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, | |
872 | trans_pcie->kw.dma >> 4); | |
873 | ||
874 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); | |
875 | ||
876 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
877 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
878 | txq_id++) { | |
879 | slots_num = (txq_id == trans_pcie->cmd_queue) ? | |
880 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
881 | ret = iwl_pcie_txq_init(trans, &trans_pcie->txq[txq_id], | |
882 | slots_num, txq_id); | |
883 | if (ret) { | |
884 | IWL_ERR(trans, "Tx %d queue init failed\n", txq_id); | |
885 | goto error; | |
886 | } | |
887 | } | |
888 | ||
889 | return 0; | |
890 | error: | |
891 | /*Upon error, free only if we allocated something */ | |
892 | if (alloc) | |
893 | iwl_pcie_tx_free(trans); | |
894 | return ret; | |
895 | } | |
896 | ||
897 | static inline void iwl_pcie_txq_progress(struct iwl_trans_pcie *trans_pcie, | |
898 | struct iwl_txq *txq) | |
899 | { | |
900 | if (!trans_pcie->wd_timeout) | |
901 | return; | |
902 | ||
903 | /* | |
904 | * if empty delete timer, otherwise move timer forward | |
905 | * since we're making progress on this queue | |
906 | */ | |
907 | if (txq->q.read_ptr == txq->q.write_ptr) | |
908 | del_timer(&txq->stuck_timer); | |
909 | else | |
910 | mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout); | |
911 | } | |
912 | ||
913 | /* Frees buffers until index _not_ inclusive */ | |
f6d497cd EG |
914 | void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, |
915 | struct sk_buff_head *skbs) | |
f02831be EG |
916 | { |
917 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
918 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
f6d497cd EG |
919 | /* n_bd is usually 256 => n_bd - 1 = 0xff */ |
920 | int tfd_num = ssn & (txq->q.n_bd - 1); | |
f02831be EG |
921 | struct iwl_queue *q = &txq->q; |
922 | int last_to_free; | |
f02831be EG |
923 | |
924 | /* This function is not meant to release cmd queue*/ | |
925 | if (WARN_ON(txq_id == trans_pcie->cmd_queue)) | |
f6d497cd | 926 | return; |
214d14d4 | 927 | |
2bfb5092 | 928 | spin_lock_bh(&txq->lock); |
f6d497cd EG |
929 | |
930 | if (txq->q.read_ptr == tfd_num) | |
931 | goto out; | |
932 | ||
933 | IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n", | |
934 | txq_id, txq->q.read_ptr, tfd_num, ssn); | |
214d14d4 | 935 | |
f02831be EG |
936 | /*Since we free until index _not_ inclusive, the one before index is |
937 | * the last we will free. This one must be used */ | |
f6d497cd | 938 | last_to_free = iwl_queue_dec_wrap(tfd_num, q->n_bd); |
f02831be | 939 | |
6ca6ebc1 | 940 | if (!iwl_queue_used(q, last_to_free)) { |
f02831be EG |
941 | IWL_ERR(trans, |
942 | "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n", | |
943 | __func__, txq_id, last_to_free, q->n_bd, | |
944 | q->write_ptr, q->read_ptr); | |
f6d497cd | 945 | goto out; |
214d14d4 JB |
946 | } |
947 | ||
f02831be | 948 | if (WARN_ON(!skb_queue_empty(skbs))) |
f6d497cd | 949 | goto out; |
214d14d4 | 950 | |
f02831be | 951 | for (; |
f6d497cd | 952 | q->read_ptr != tfd_num; |
f02831be | 953 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { |
214d14d4 | 954 | |
f02831be EG |
955 | if (WARN_ON_ONCE(txq->entries[txq->q.read_ptr].skb == NULL)) |
956 | continue; | |
214d14d4 | 957 | |
f02831be | 958 | __skb_queue_tail(skbs, txq->entries[txq->q.read_ptr].skb); |
214d14d4 | 959 | |
f02831be | 960 | txq->entries[txq->q.read_ptr].skb = NULL; |
fd4abac5 | 961 | |
f02831be | 962 | iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq); |
fd4abac5 | 963 | |
98891754 | 964 | iwl_pcie_txq_free_tfd(trans, txq); |
f02831be | 965 | } |
fd4abac5 | 966 | |
f02831be EG |
967 | iwl_pcie_txq_progress(trans_pcie, txq); |
968 | ||
f6d497cd EG |
969 | if (iwl_queue_space(&txq->q) > txq->q.low_mark) |
970 | iwl_wake_queue(trans, txq); | |
971 | out: | |
2bfb5092 | 972 | spin_unlock_bh(&txq->lock); |
1053d35f RR |
973 | } |
974 | ||
f02831be EG |
975 | /* |
976 | * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd | |
977 | * | |
978 | * When FW advances 'R' index, all entries between old and new 'R' index | |
979 | * need to be reclaimed. As result, some free space forms. If there is | |
980 | * enough free space (> low mark), wake the stack that feeds us. | |
981 | */ | |
982 | static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx) | |
48d42c42 | 983 | { |
f02831be EG |
984 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
985 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
986 | struct iwl_queue *q = &txq->q; | |
987 | int nfreed = 0; | |
48d42c42 | 988 | |
f02831be | 989 | lockdep_assert_held(&txq->lock); |
48d42c42 | 990 | |
6ca6ebc1 | 991 | if ((idx >= q->n_bd) || (!iwl_queue_used(q, idx))) { |
f02831be EG |
992 | IWL_ERR(trans, |
993 | "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n", | |
994 | __func__, txq_id, idx, q->n_bd, | |
995 | q->write_ptr, q->read_ptr); | |
996 | return; | |
997 | } | |
48d42c42 | 998 | |
f02831be EG |
999 | for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; |
1000 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
48d42c42 | 1001 | |
f02831be EG |
1002 | if (nfreed++ > 0) { |
1003 | IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", | |
1004 | idx, q->write_ptr, q->read_ptr); | |
1005 | iwl_op_mode_nic_error(trans->op_mode); | |
1006 | } | |
1007 | } | |
1008 | ||
1009 | iwl_pcie_txq_progress(trans_pcie, txq); | |
48d42c42 EG |
1010 | } |
1011 | ||
f02831be | 1012 | static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid, |
1ce8658c | 1013 | u16 txq_id) |
48d42c42 | 1014 | { |
20d3b647 | 1015 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
48d42c42 EG |
1016 | u32 tbl_dw_addr; |
1017 | u32 tbl_dw; | |
1018 | u16 scd_q2ratid; | |
1019 | ||
1020 | scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; | |
1021 | ||
105183b1 | 1022 | tbl_dw_addr = trans_pcie->scd_base_addr + |
48d42c42 EG |
1023 | SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); |
1024 | ||
4fd442db | 1025 | tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr); |
48d42c42 EG |
1026 | |
1027 | if (txq_id & 0x1) | |
1028 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); | |
1029 | else | |
1030 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); | |
1031 | ||
4fd442db | 1032 | iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw); |
48d42c42 EG |
1033 | |
1034 | return 0; | |
1035 | } | |
1036 | ||
f02831be EG |
1037 | static inline void iwl_pcie_txq_set_inactive(struct iwl_trans *trans, |
1038 | u16 txq_id) | |
48d42c42 EG |
1039 | { |
1040 | /* Simply stop the queue, but don't change any configuration; | |
1041 | * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ | |
1042db2a | 1042 | iwl_write_prph(trans, |
48d42c42 EG |
1043 | SCD_QUEUE_STATUS_BITS(txq_id), |
1044 | (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)| | |
1045 | (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); | |
1046 | } | |
1047 | ||
bd5f6a34 EG |
1048 | /* Receiver address (actually, Rx station's index into station table), |
1049 | * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */ | |
1050 | #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid)) | |
1051 | ||
f02831be EG |
1052 | void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, int fifo, |
1053 | int sta_id, int tid, int frame_limit, u16 ssn) | |
48d42c42 | 1054 | { |
9eae88fa | 1055 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
4beaf6c2 | 1056 | |
9eae88fa JB |
1057 | if (test_and_set_bit(txq_id, trans_pcie->queue_used)) |
1058 | WARN_ONCE(1, "queue %d already used - expect issues", txq_id); | |
48d42c42 | 1059 | |
48d42c42 | 1060 | /* Stop this Tx queue before configuring it */ |
f02831be | 1061 | iwl_pcie_txq_set_inactive(trans, txq_id); |
48d42c42 | 1062 | |
4beaf6c2 EG |
1063 | /* Set this queue as a chain-building queue unless it is CMD queue */ |
1064 | if (txq_id != trans_pcie->cmd_queue) | |
1065 | iwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, BIT(txq_id)); | |
1066 | ||
1067 | /* If this queue is mapped to a certain station: it is an AGG queue */ | |
881acd89 | 1068 | if (sta_id >= 0) { |
4beaf6c2 | 1069 | u16 ra_tid = BUILD_RAxTID(sta_id, tid); |
48d42c42 | 1070 | |
4beaf6c2 | 1071 | /* Map receiver-address / traffic-ID to this queue */ |
f02831be | 1072 | iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id); |
48d42c42 | 1073 | |
4beaf6c2 EG |
1074 | /* enable aggregations for the queue */ |
1075 | iwl_set_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id)); | |
1ce8658c EG |
1076 | } else { |
1077 | /* | |
1078 | * disable aggregations for the queue, this will also make the | |
1079 | * ra_tid mapping configuration irrelevant since it is now a | |
1080 | * non-AGG queue. | |
1081 | */ | |
1082 | iwl_clear_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id)); | |
4beaf6c2 | 1083 | } |
48d42c42 EG |
1084 | |
1085 | /* Place first TFD at index corresponding to start sequence number. | |
1086 | * Assumes that ssn_idx is valid (!= 0xFFF) */ | |
822e8b2a EG |
1087 | trans_pcie->txq[txq_id].q.read_ptr = (ssn & 0xff); |
1088 | trans_pcie->txq[txq_id].q.write_ptr = (ssn & 0xff); | |
1ce8658c EG |
1089 | |
1090 | iwl_write_direct32(trans, HBUS_TARG_WRPTR, | |
1091 | (ssn & 0xff) | (txq_id << 8)); | |
1092 | iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn); | |
48d42c42 EG |
1093 | |
1094 | /* Set up Tx window size and frame limit for this queue */ | |
4fd442db | 1095 | iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr + |
4beaf6c2 | 1096 | SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0); |
4fd442db | 1097 | iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr + |
9eae88fa JB |
1098 | SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), |
1099 | ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
1100 | SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
1101 | ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
1102 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
48d42c42 | 1103 | |
48d42c42 | 1104 | /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ |
1ce8658c EG |
1105 | iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id), |
1106 | (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) | | |
1107 | (fifo << SCD_QUEUE_STTS_REG_POS_TXF) | | |
1108 | (1 << SCD_QUEUE_STTS_REG_POS_WSL) | | |
1109 | SCD_QUEUE_STTS_REG_MSK); | |
1110 | IWL_DEBUG_TX_QUEUES(trans, "Activate queue %d on FIFO %d WrPtr: %d\n", | |
1111 | txq_id, fifo, ssn & 0xff); | |
4beaf6c2 EG |
1112 | } |
1113 | ||
f02831be | 1114 | void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id) |
288712a6 | 1115 | { |
8ad71bef | 1116 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
986ea6c9 EG |
1117 | u32 stts_addr = trans_pcie->scd_base_addr + |
1118 | SCD_TX_STTS_QUEUE_OFFSET(txq_id); | |
1119 | static const u32 zero_val[4] = {}; | |
288712a6 | 1120 | |
9eae88fa JB |
1121 | if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) { |
1122 | WARN_ONCE(1, "queue %d not used", txq_id); | |
1123 | return; | |
48d42c42 EG |
1124 | } |
1125 | ||
f02831be | 1126 | iwl_pcie_txq_set_inactive(trans, txq_id); |
ac928f8d | 1127 | |
4fd442db EG |
1128 | iwl_trans_write_mem(trans, stts_addr, (void *)zero_val, |
1129 | ARRAY_SIZE(zero_val)); | |
986ea6c9 | 1130 | |
990aa6d7 | 1131 | iwl_pcie_txq_unmap(trans, txq_id); |
6c3fd3f0 | 1132 | |
1ce8658c | 1133 | IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id); |
48d42c42 EG |
1134 | } |
1135 | ||
fd4abac5 TW |
1136 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ |
1137 | ||
990aa6d7 | 1138 | /* |
f02831be | 1139 | * iwl_pcie_enqueue_hcmd - enqueue a uCode command |
fd4abac5 TW |
1140 | * @priv: device private data point |
1141 | * @cmd: a point to the ucode command structure | |
1142 | * | |
1143 | * The function returns < 0 values to indicate the operation is | |
1144 | * failed. On success, it turns the index (> 0) of command in the | |
1145 | * command queue. | |
1146 | */ | |
f02831be EG |
1147 | static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans, |
1148 | struct iwl_host_cmd *cmd) | |
fd4abac5 | 1149 | { |
8ad71bef | 1150 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1151 | struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
fd4abac5 | 1152 | struct iwl_queue *q = &txq->q; |
c2acea8e JB |
1153 | struct iwl_device_cmd *out_cmd; |
1154 | struct iwl_cmd_meta *out_meta; | |
f4feb8ac | 1155 | void *dup_buf = NULL; |
fd4abac5 | 1156 | dma_addr_t phys_addr; |
f4feb8ac | 1157 | int idx; |
38c0f334 | 1158 | u16 copy_size, cmd_size, scratch_size; |
4ce7cc2b JB |
1159 | bool had_nocopy = false; |
1160 | int i; | |
96791422 | 1161 | u32 cmd_pos; |
1afbfb60 JB |
1162 | const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD]; |
1163 | u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD]; | |
fd4abac5 | 1164 | |
4ce7cc2b JB |
1165 | copy_size = sizeof(out_cmd->hdr); |
1166 | cmd_size = sizeof(out_cmd->hdr); | |
1167 | ||
1168 | /* need one for the header if the first is NOCOPY */ | |
1afbfb60 | 1169 | BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1); |
4ce7cc2b | 1170 | |
1afbfb60 | 1171 | for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { |
8a964f44 JB |
1172 | cmddata[i] = cmd->data[i]; |
1173 | cmdlen[i] = cmd->len[i]; | |
1174 | ||
4ce7cc2b JB |
1175 | if (!cmd->len[i]) |
1176 | continue; | |
8a964f44 | 1177 | |
38c0f334 JB |
1178 | /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */ |
1179 | if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) { | |
1180 | int copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size; | |
8a964f44 JB |
1181 | |
1182 | if (copy > cmdlen[i]) | |
1183 | copy = cmdlen[i]; | |
1184 | cmdlen[i] -= copy; | |
1185 | cmddata[i] += copy; | |
1186 | copy_size += copy; | |
1187 | } | |
1188 | ||
4ce7cc2b JB |
1189 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { |
1190 | had_nocopy = true; | |
f4feb8ac JB |
1191 | if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) { |
1192 | idx = -EINVAL; | |
1193 | goto free_dup_buf; | |
1194 | } | |
1195 | } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) { | |
1196 | /* | |
1197 | * This is also a chunk that isn't copied | |
1198 | * to the static buffer so set had_nocopy. | |
1199 | */ | |
1200 | had_nocopy = true; | |
1201 | ||
1202 | /* only allowed once */ | |
1203 | if (WARN_ON(dup_buf)) { | |
1204 | idx = -EINVAL; | |
1205 | goto free_dup_buf; | |
1206 | } | |
1207 | ||
8a964f44 | 1208 | dup_buf = kmemdup(cmddata[i], cmdlen[i], |
f4feb8ac JB |
1209 | GFP_ATOMIC); |
1210 | if (!dup_buf) | |
1211 | return -ENOMEM; | |
4ce7cc2b JB |
1212 | } else { |
1213 | /* NOCOPY must not be followed by normal! */ | |
f4feb8ac JB |
1214 | if (WARN_ON(had_nocopy)) { |
1215 | idx = -EINVAL; | |
1216 | goto free_dup_buf; | |
1217 | } | |
8a964f44 | 1218 | copy_size += cmdlen[i]; |
4ce7cc2b JB |
1219 | } |
1220 | cmd_size += cmd->len[i]; | |
1221 | } | |
fd4abac5 | 1222 | |
3e41ace5 JB |
1223 | /* |
1224 | * If any of the command structures end up being larger than | |
4ce7cc2b JB |
1225 | * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically |
1226 | * allocated into separate TFDs, then we will need to | |
1227 | * increase the size of the buffers. | |
3e41ace5 | 1228 | */ |
2a79e45e JB |
1229 | if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE, |
1230 | "Command %s (%#x) is too large (%d bytes)\n", | |
990aa6d7 | 1231 | get_cmd_string(trans_pcie, cmd->id), cmd->id, copy_size)) { |
f4feb8ac JB |
1232 | idx = -EINVAL; |
1233 | goto free_dup_buf; | |
1234 | } | |
fd4abac5 | 1235 | |
015c15e1 | 1236 | spin_lock_bh(&txq->lock); |
3598e177 | 1237 | |
c2acea8e | 1238 | if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { |
015c15e1 | 1239 | spin_unlock_bh(&txq->lock); |
3598e177 | 1240 | |
6d8f6eeb | 1241 | IWL_ERR(trans, "No space in command queue\n"); |
0e781842 | 1242 | iwl_op_mode_cmd_queue_full(trans->op_mode); |
f4feb8ac JB |
1243 | idx = -ENOSPC; |
1244 | goto free_dup_buf; | |
fd4abac5 TW |
1245 | } |
1246 | ||
4ce7cc2b | 1247 | idx = get_cmd_index(q, q->write_ptr); |
bf8440e6 JB |
1248 | out_cmd = txq->entries[idx].cmd; |
1249 | out_meta = &txq->entries[idx].meta; | |
c2acea8e | 1250 | |
8ce73f3a | 1251 | memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ |
c2acea8e JB |
1252 | if (cmd->flags & CMD_WANT_SKB) |
1253 | out_meta->source = cmd; | |
fd4abac5 | 1254 | |
4ce7cc2b | 1255 | /* set up the header */ |
fd4abac5 | 1256 | |
4ce7cc2b | 1257 | out_cmd->hdr.cmd = cmd->id; |
fd4abac5 | 1258 | out_cmd->hdr.flags = 0; |
cefeaa5f | 1259 | out_cmd->hdr.sequence = |
c6f600fc | 1260 | cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | |
cefeaa5f | 1261 | INDEX_TO_SEQ(q->write_ptr)); |
4ce7cc2b JB |
1262 | |
1263 | /* and copy the data that needs to be copied */ | |
96791422 | 1264 | cmd_pos = offsetof(struct iwl_device_cmd, payload); |
8a964f44 | 1265 | copy_size = sizeof(out_cmd->hdr); |
1afbfb60 | 1266 | for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { |
8a964f44 JB |
1267 | int copy = 0; |
1268 | ||
cc904c71 | 1269 | if (!cmd->len[i]) |
4ce7cc2b | 1270 | continue; |
8a964f44 | 1271 | |
38c0f334 JB |
1272 | /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */ |
1273 | if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) { | |
1274 | copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size; | |
8a964f44 JB |
1275 | |
1276 | if (copy > cmd->len[i]) | |
1277 | copy = cmd->len[i]; | |
1278 | } | |
1279 | ||
1280 | /* copy everything if not nocopy/dup */ | |
1281 | if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | | |
1282 | IWL_HCMD_DFL_DUP))) | |
1283 | copy = cmd->len[i]; | |
1284 | ||
1285 | if (copy) { | |
1286 | memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); | |
1287 | cmd_pos += copy; | |
1288 | copy_size += copy; | |
1289 | } | |
96791422 EG |
1290 | } |
1291 | ||
d9fb6465 | 1292 | IWL_DEBUG_HC(trans, |
20d3b647 | 1293 | "Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n", |
990aa6d7 | 1294 | get_cmd_string(trans_pcie, out_cmd->hdr.cmd), |
20d3b647 JB |
1295 | out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence), |
1296 | cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue); | |
4ce7cc2b | 1297 | |
38c0f334 JB |
1298 | /* start the TFD with the scratchbuf */ |
1299 | scratch_size = min_t(int, copy_size, IWL_HCMD_SCRATCHBUF_SIZE); | |
1300 | memcpy(&txq->scratchbufs[q->write_ptr], &out_cmd->hdr, scratch_size); | |
1301 | iwl_pcie_txq_build_tfd(trans, txq, | |
1302 | iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr), | |
1303 | scratch_size, 1); | |
1304 | ||
1305 | /* map first command fragment, if any remains */ | |
1306 | if (copy_size > scratch_size) { | |
1307 | phys_addr = dma_map_single(trans->dev, | |
1308 | ((u8 *)&out_cmd->hdr) + scratch_size, | |
1309 | copy_size - scratch_size, | |
1310 | DMA_TO_DEVICE); | |
1311 | if (dma_mapping_error(trans->dev, phys_addr)) { | |
1312 | iwl_pcie_tfd_unmap(trans, out_meta, | |
1313 | &txq->tfds[q->write_ptr]); | |
1314 | idx = -ENOMEM; | |
1315 | goto out; | |
1316 | } | |
8a964f44 | 1317 | |
38c0f334 JB |
1318 | iwl_pcie_txq_build_tfd(trans, txq, phys_addr, |
1319 | copy_size - scratch_size, 0); | |
2c46f72e JB |
1320 | } |
1321 | ||
8a964f44 | 1322 | /* map the remaining (adjusted) nocopy/dup fragments */ |
1afbfb60 | 1323 | for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { |
8a964f44 | 1324 | const void *data = cmddata[i]; |
f4feb8ac | 1325 | |
8a964f44 | 1326 | if (!cmdlen[i]) |
4ce7cc2b | 1327 | continue; |
f4feb8ac JB |
1328 | if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | |
1329 | IWL_HCMD_DFL_DUP))) | |
4ce7cc2b | 1330 | continue; |
f4feb8ac JB |
1331 | if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) |
1332 | data = dup_buf; | |
1333 | phys_addr = dma_map_single(trans->dev, (void *)data, | |
98891754 | 1334 | cmdlen[i], DMA_TO_DEVICE); |
1042db2a | 1335 | if (dma_mapping_error(trans->dev, phys_addr)) { |
f02831be | 1336 | iwl_pcie_tfd_unmap(trans, out_meta, |
98891754 | 1337 | &txq->tfds[q->write_ptr]); |
4ce7cc2b JB |
1338 | idx = -ENOMEM; |
1339 | goto out; | |
1340 | } | |
1341 | ||
8a964f44 | 1342 | iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], 0); |
4ce7cc2b | 1343 | } |
df833b1d | 1344 | |
afaf6b57 | 1345 | out_meta->flags = cmd->flags; |
f4feb8ac JB |
1346 | if (WARN_ON_ONCE(txq->entries[idx].free_buf)) |
1347 | kfree(txq->entries[idx].free_buf); | |
1348 | txq->entries[idx].free_buf = dup_buf; | |
2c46f72e JB |
1349 | |
1350 | txq->need_update = 1; | |
1351 | ||
8a964f44 | 1352 | trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr); |
df833b1d | 1353 | |
7c5ba4a8 JB |
1354 | /* start timer if queue currently empty */ |
1355 | if (q->read_ptr == q->write_ptr && trans_pcie->wd_timeout) | |
1356 | mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout); | |
1357 | ||
fd4abac5 TW |
1358 | /* Increment and update queue's write index */ |
1359 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
990aa6d7 | 1360 | iwl_pcie_txq_inc_wr_ptr(trans, txq); |
fd4abac5 | 1361 | |
2c46f72e | 1362 | out: |
015c15e1 | 1363 | spin_unlock_bh(&txq->lock); |
f4feb8ac JB |
1364 | free_dup_buf: |
1365 | if (idx < 0) | |
1366 | kfree(dup_buf); | |
7bfedc59 | 1367 | return idx; |
fd4abac5 TW |
1368 | } |
1369 | ||
990aa6d7 EG |
1370 | /* |
1371 | * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them | |
17b88929 | 1372 | * @rxb: Rx buffer to reclaim |
247c61d6 EG |
1373 | * @handler_status: return value of the handler of the command |
1374 | * (put in setup_rx_handlers) | |
17b88929 TW |
1375 | * |
1376 | * If an Rx buffer has an async callback associated with it the callback | |
1377 | * will be executed. The attached skb (if present) will only be freed | |
1378 | * if the callback returns 1 | |
1379 | */ | |
990aa6d7 EG |
1380 | void iwl_pcie_hcmd_complete(struct iwl_trans *trans, |
1381 | struct iwl_rx_cmd_buffer *rxb, int handler_status) | |
17b88929 | 1382 | { |
2f301227 | 1383 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
17b88929 TW |
1384 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
1385 | int txq_id = SEQ_TO_QUEUE(sequence); | |
1386 | int index = SEQ_TO_INDEX(sequence); | |
17b88929 | 1387 | int cmd_index; |
c2acea8e JB |
1388 | struct iwl_device_cmd *cmd; |
1389 | struct iwl_cmd_meta *meta; | |
8ad71bef | 1390 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1391 | struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
17b88929 TW |
1392 | |
1393 | /* If a Tx command is being handled and it isn't in the actual | |
1394 | * command queue then there a command routing bug has been introduced | |
1395 | * in the queue management code. */ | |
c6f600fc | 1396 | if (WARN(txq_id != trans_pcie->cmd_queue, |
13bb9483 | 1397 | "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", |
20d3b647 JB |
1398 | txq_id, trans_pcie->cmd_queue, sequence, |
1399 | trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr, | |
1400 | trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) { | |
3e10caeb | 1401 | iwl_print_hex_error(trans, pkt, 32); |
55d6a3cd | 1402 | return; |
01ef9323 | 1403 | } |
17b88929 | 1404 | |
2bfb5092 | 1405 | spin_lock_bh(&txq->lock); |
015c15e1 | 1406 | |
4ce7cc2b | 1407 | cmd_index = get_cmd_index(&txq->q, index); |
bf8440e6 JB |
1408 | cmd = txq->entries[cmd_index].cmd; |
1409 | meta = &txq->entries[cmd_index].meta; | |
17b88929 | 1410 | |
98891754 | 1411 | iwl_pcie_tfd_unmap(trans, meta, &txq->tfds[index]); |
c33de625 | 1412 | |
17b88929 | 1413 | /* Input error checking is done when commands are added to queue. */ |
c2acea8e | 1414 | if (meta->flags & CMD_WANT_SKB) { |
48a2d66f | 1415 | struct page *p = rxb_steal_page(rxb); |
65b94a4a | 1416 | |
65b94a4a JB |
1417 | meta->source->resp_pkt = pkt; |
1418 | meta->source->_rx_page_addr = (unsigned long)page_address(p); | |
b2cf410c | 1419 | meta->source->_rx_page_order = trans_pcie->rx_page_order; |
247c61d6 | 1420 | meta->source->handler_status = handler_status; |
247c61d6 | 1421 | } |
2624e96c | 1422 | |
f02831be | 1423 | iwl_pcie_cmdq_reclaim(trans, txq_id, index); |
17b88929 | 1424 | |
c2acea8e | 1425 | if (!(meta->flags & CMD_ASYNC)) { |
74fda971 | 1426 | if (!test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) { |
05c89b91 WYG |
1427 | IWL_WARN(trans, |
1428 | "HCMD_ACTIVE already clear for command %s\n", | |
990aa6d7 | 1429 | get_cmd_string(trans_pcie, cmd->hdr.cmd)); |
05c89b91 | 1430 | } |
74fda971 | 1431 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); |
6d8f6eeb | 1432 | IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", |
990aa6d7 | 1433 | get_cmd_string(trans_pcie, cmd->hdr.cmd)); |
f946b529 | 1434 | wake_up(&trans_pcie->wait_command_queue); |
17b88929 | 1435 | } |
3598e177 | 1436 | |
dd487449 | 1437 | meta->flags = 0; |
3598e177 | 1438 | |
2bfb5092 | 1439 | spin_unlock_bh(&txq->lock); |
17b88929 | 1440 | } |
253a634c | 1441 | |
253a634c EG |
1442 | #define HOST_COMPLETE_TIMEOUT (2 * HZ) |
1443 | ||
f02831be EG |
1444 | static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans, |
1445 | struct iwl_host_cmd *cmd) | |
253a634c | 1446 | { |
d9fb6465 | 1447 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
253a634c EG |
1448 | int ret; |
1449 | ||
1450 | /* An asynchronous command can not expect an SKB to be set. */ | |
1451 | if (WARN_ON(cmd->flags & CMD_WANT_SKB)) | |
1452 | return -EINVAL; | |
1453 | ||
f02831be | 1454 | ret = iwl_pcie_enqueue_hcmd(trans, cmd); |
253a634c | 1455 | if (ret < 0) { |
721c32f7 | 1456 | IWL_ERR(trans, |
b36b110c | 1457 | "Error sending %s: enqueue_hcmd failed: %d\n", |
990aa6d7 | 1458 | get_cmd_string(trans_pcie, cmd->id), ret); |
253a634c EG |
1459 | return ret; |
1460 | } | |
1461 | return 0; | |
1462 | } | |
1463 | ||
f02831be EG |
1464 | static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans, |
1465 | struct iwl_host_cmd *cmd) | |
253a634c | 1466 | { |
8ad71bef | 1467 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
253a634c EG |
1468 | int cmd_idx; |
1469 | int ret; | |
1470 | ||
6d8f6eeb | 1471 | IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", |
990aa6d7 | 1472 | get_cmd_string(trans_pcie, cmd->id)); |
253a634c | 1473 | |
2cc39c94 | 1474 | if (WARN_ON(test_and_set_bit(STATUS_HCMD_ACTIVE, |
74fda971 | 1475 | &trans_pcie->status))) { |
2cc39c94 | 1476 | IWL_ERR(trans, "Command %s: a command is already active!\n", |
990aa6d7 | 1477 | get_cmd_string(trans_pcie, cmd->id)); |
2cc39c94 JB |
1478 | return -EIO; |
1479 | } | |
1480 | ||
6d8f6eeb | 1481 | IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", |
990aa6d7 | 1482 | get_cmd_string(trans_pcie, cmd->id)); |
253a634c | 1483 | |
f02831be | 1484 | cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd); |
253a634c EG |
1485 | if (cmd_idx < 0) { |
1486 | ret = cmd_idx; | |
74fda971 | 1487 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); |
721c32f7 | 1488 | IWL_ERR(trans, |
b36b110c | 1489 | "Error sending %s: enqueue_hcmd failed: %d\n", |
990aa6d7 | 1490 | get_cmd_string(trans_pcie, cmd->id), ret); |
253a634c EG |
1491 | return ret; |
1492 | } | |
1493 | ||
f946b529 | 1494 | ret = wait_event_timeout(trans_pcie->wait_command_queue, |
20d3b647 JB |
1495 | !test_bit(STATUS_HCMD_ACTIVE, |
1496 | &trans_pcie->status), | |
1497 | HOST_COMPLETE_TIMEOUT); | |
253a634c | 1498 | if (!ret) { |
74fda971 | 1499 | if (test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) { |
990aa6d7 | 1500 | struct iwl_txq *txq = |
c6f600fc | 1501 | &trans_pcie->txq[trans_pcie->cmd_queue]; |
d10630af WYG |
1502 | struct iwl_queue *q = &txq->q; |
1503 | ||
721c32f7 | 1504 | IWL_ERR(trans, |
253a634c | 1505 | "Error sending %s: time out after %dms.\n", |
990aa6d7 | 1506 | get_cmd_string(trans_pcie, cmd->id), |
253a634c EG |
1507 | jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); |
1508 | ||
721c32f7 | 1509 | IWL_ERR(trans, |
d10630af WYG |
1510 | "Current CMD queue read_ptr %d write_ptr %d\n", |
1511 | q->read_ptr, q->write_ptr); | |
1512 | ||
74fda971 | 1513 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); |
d9fb6465 JB |
1514 | IWL_DEBUG_INFO(trans, |
1515 | "Clearing HCMD_ACTIVE for command %s\n", | |
990aa6d7 | 1516 | get_cmd_string(trans_pcie, cmd->id)); |
253a634c EG |
1517 | ret = -ETIMEDOUT; |
1518 | goto cancel; | |
1519 | } | |
1520 | } | |
1521 | ||
d18aa87f JB |
1522 | if (test_bit(STATUS_FW_ERROR, &trans_pcie->status)) { |
1523 | IWL_ERR(trans, "FW error in SYNC CMD %s\n", | |
990aa6d7 | 1524 | get_cmd_string(trans_pcie, cmd->id)); |
b656fa33 | 1525 | dump_stack(); |
d18aa87f JB |
1526 | ret = -EIO; |
1527 | goto cancel; | |
1528 | } | |
1529 | ||
1094fa26 EH |
1530 | if (!(cmd->flags & CMD_SEND_IN_RFKILL) && |
1531 | test_bit(STATUS_RFKILL, &trans_pcie->status)) { | |
f946b529 EG |
1532 | IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n"); |
1533 | ret = -ERFKILL; | |
1534 | goto cancel; | |
1535 | } | |
1536 | ||
65b94a4a | 1537 | if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) { |
6d8f6eeb | 1538 | IWL_ERR(trans, "Error: Response NULL in '%s'\n", |
990aa6d7 | 1539 | get_cmd_string(trans_pcie, cmd->id)); |
253a634c EG |
1540 | ret = -EIO; |
1541 | goto cancel; | |
1542 | } | |
1543 | ||
1544 | return 0; | |
1545 | ||
1546 | cancel: | |
1547 | if (cmd->flags & CMD_WANT_SKB) { | |
1548 | /* | |
1549 | * Cancel the CMD_WANT_SKB flag for the cmd in the | |
1550 | * TX cmd queue. Otherwise in case the cmd comes | |
1551 | * in later, it will possibly set an invalid | |
1552 | * address (cmd->meta.source). | |
1553 | */ | |
bf8440e6 JB |
1554 | trans_pcie->txq[trans_pcie->cmd_queue]. |
1555 | entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB; | |
253a634c | 1556 | } |
9cac4943 | 1557 | |
65b94a4a JB |
1558 | if (cmd->resp_pkt) { |
1559 | iwl_free_resp(cmd); | |
1560 | cmd->resp_pkt = NULL; | |
253a634c EG |
1561 | } |
1562 | ||
1563 | return ret; | |
1564 | } | |
1565 | ||
f02831be | 1566 | int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c | 1567 | { |
f946b529 EG |
1568 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1569 | ||
d18aa87f JB |
1570 | if (test_bit(STATUS_FW_ERROR, &trans_pcie->status)) |
1571 | return -EIO; | |
1572 | ||
4f59334b EH |
1573 | if (!(cmd->flags & CMD_SEND_IN_RFKILL) && |
1574 | test_bit(STATUS_RFKILL, &trans_pcie->status)) { | |
754d7d9e EG |
1575 | IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n", |
1576 | cmd->id); | |
f946b529 | 1577 | return -ERFKILL; |
754d7d9e | 1578 | } |
f946b529 | 1579 | |
253a634c | 1580 | if (cmd->flags & CMD_ASYNC) |
f02831be | 1581 | return iwl_pcie_send_hcmd_async(trans, cmd); |
253a634c | 1582 | |
f946b529 | 1583 | /* We still can fail on RFKILL that can be asserted while we wait */ |
f02831be | 1584 | return iwl_pcie_send_hcmd_sync(trans, cmd); |
253a634c EG |
1585 | } |
1586 | ||
f02831be EG |
1587 | int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, |
1588 | struct iwl_device_cmd *dev_cmd, int txq_id) | |
a0eaad71 | 1589 | { |
8ad71bef | 1590 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
f02831be EG |
1591 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
1592 | struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload; | |
1593 | struct iwl_cmd_meta *out_meta; | |
1594 | struct iwl_txq *txq; | |
1595 | struct iwl_queue *q; | |
38c0f334 JB |
1596 | dma_addr_t tb0_phys, tb1_phys, scratch_phys; |
1597 | void *tb1_addr; | |
1598 | u16 len, tb1_len, tb2_len; | |
f02831be EG |
1599 | u8 wait_write_ptr = 0; |
1600 | __le16 fc = hdr->frame_control; | |
1601 | u8 hdr_len = ieee80211_hdrlen(fc); | |
1602 | u16 __maybe_unused wifi_seq; | |
1603 | ||
1604 | txq = &trans_pcie->txq[txq_id]; | |
1605 | q = &txq->q; | |
a0eaad71 | 1606 | |
f02831be EG |
1607 | if (unlikely(!test_bit(txq_id, trans_pcie->queue_used))) { |
1608 | WARN_ON_ONCE(1); | |
1609 | return -EINVAL; | |
1610 | } | |
39644e9a | 1611 | |
f02831be | 1612 | spin_lock(&txq->lock); |
015c15e1 | 1613 | |
f02831be EG |
1614 | /* In AGG mode, the index in the ring must correspond to the WiFi |
1615 | * sequence number. This is a HW requirements to help the SCD to parse | |
1616 | * the BA. | |
1617 | * Check here that the packets are in the right place on the ring. | |
1618 | */ | |
1619 | #ifdef CONFIG_IWLWIFI_DEBUG | |
9a886586 | 1620 | wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); |
f02831be EG |
1621 | WARN_ONCE((iwl_read_prph(trans, SCD_AGGR_SEL) & BIT(txq_id)) && |
1622 | ((wifi_seq & 0xff) != q->write_ptr), | |
1623 | "Q: %d WiFi Seq %d tfdNum %d", | |
1624 | txq_id, wifi_seq, q->write_ptr); | |
1625 | #endif | |
1626 | ||
1627 | /* Set up driver data for this TFD */ | |
1628 | txq->entries[q->write_ptr].skb = skb; | |
1629 | txq->entries[q->write_ptr].cmd = dev_cmd; | |
1630 | ||
1631 | dev_cmd->hdr.cmd = REPLY_TX; | |
1632 | dev_cmd->hdr.sequence = | |
1633 | cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
1634 | INDEX_TO_SEQ(q->write_ptr))); | |
1635 | ||
38c0f334 JB |
1636 | tb0_phys = iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr); |
1637 | scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) + | |
1638 | offsetof(struct iwl_tx_cmd, scratch); | |
1639 | ||
1640 | tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); | |
1641 | tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); | |
1642 | ||
f02831be EG |
1643 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ |
1644 | out_meta = &txq->entries[q->write_ptr].meta; | |
a0eaad71 | 1645 | |
f02831be | 1646 | /* |
38c0f334 JB |
1647 | * The second TB (tb1) points to the remainder of the TX command |
1648 | * and the 802.11 header - dword aligned size | |
1649 | * (This calculation modifies the TX command, so do it before the | |
1650 | * setup of the first TB) | |
f02831be | 1651 | */ |
38c0f334 JB |
1652 | len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) + |
1653 | hdr_len - IWL_HCMD_SCRATCHBUF_SIZE; | |
1654 | tb1_len = (len + 3) & ~3; | |
f02831be EG |
1655 | |
1656 | /* Tell NIC about any 2-byte padding after MAC header */ | |
38c0f334 | 1657 | if (tb1_len != len) |
f02831be EG |
1658 | tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; |
1659 | ||
38c0f334 JB |
1660 | /* The first TB points to the scratchbuf data - min_copy bytes */ |
1661 | memcpy(&txq->scratchbufs[q->write_ptr], &dev_cmd->hdr, | |
1662 | IWL_HCMD_SCRATCHBUF_SIZE); | |
1663 | iwl_pcie_txq_build_tfd(trans, txq, tb0_phys, | |
1664 | IWL_HCMD_SCRATCHBUF_SIZE, 1); | |
f02831be | 1665 | |
38c0f334 JB |
1666 | /* there must be data left over for TB1 or this code must be changed */ |
1667 | BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_HCMD_SCRATCHBUF_SIZE); | |
1668 | ||
1669 | /* map the data for TB1 */ | |
1670 | tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_HCMD_SCRATCHBUF_SIZE; | |
1671 | tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE); | |
1672 | if (unlikely(dma_mapping_error(trans->dev, tb1_phys))) | |
1673 | goto out_err; | |
1674 | iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, 0); | |
a0eaad71 | 1675 | |
38c0f334 JB |
1676 | /* |
1677 | * Set up TFD's third entry to point directly to remainder | |
1678 | * of skb, if any (802.11 null frames have no payload). | |
1679 | */ | |
1680 | tb2_len = skb->len - hdr_len; | |
1681 | if (tb2_len > 0) { | |
1682 | dma_addr_t tb2_phys = dma_map_single(trans->dev, | |
1683 | skb->data + hdr_len, | |
1684 | tb2_len, DMA_TO_DEVICE); | |
1685 | if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) { | |
1686 | iwl_pcie_tfd_unmap(trans, out_meta, | |
1687 | &txq->tfds[q->write_ptr]); | |
f02831be EG |
1688 | goto out_err; |
1689 | } | |
38c0f334 | 1690 | iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, 0); |
f02831be | 1691 | } |
a0eaad71 | 1692 | |
f02831be EG |
1693 | /* Set up entry for this TFD in Tx byte-count array */ |
1694 | iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len)); | |
a0eaad71 | 1695 | |
f02831be EG |
1696 | trace_iwlwifi_dev_tx(trans->dev, skb, |
1697 | &txq->tfds[txq->q.write_ptr], | |
1698 | sizeof(struct iwl_tfd), | |
38c0f334 JB |
1699 | &dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len, |
1700 | skb->data + hdr_len, tb2_len); | |
f02831be | 1701 | trace_iwlwifi_dev_tx_data(trans->dev, skb, |
38c0f334 JB |
1702 | skb->data + hdr_len, tb2_len); |
1703 | ||
1704 | if (!ieee80211_has_morefrags(fc)) { | |
1705 | txq->need_update = 1; | |
1706 | } else { | |
1707 | wait_write_ptr = 1; | |
1708 | txq->need_update = 0; | |
1709 | } | |
7c5ba4a8 | 1710 | |
f02831be EG |
1711 | /* start timer if queue currently empty */ |
1712 | if (txq->need_update && q->read_ptr == q->write_ptr && | |
1713 | trans_pcie->wd_timeout) | |
1714 | mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout); | |
1715 | ||
1716 | /* Tell device the write index *just past* this latest filled TFD */ | |
1717 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
1718 | iwl_pcie_txq_inc_wr_ptr(trans, txq); | |
1719 | ||
1720 | /* | |
1721 | * At this point the frame is "transmitted" successfully | |
1722 | * and we will get a TX status notification eventually, | |
1723 | * regardless of the value of ret. "ret" only indicates | |
1724 | * whether or not we should update the write pointer. | |
1725 | */ | |
1726 | if (iwl_queue_space(q) < q->high_mark) { | |
1727 | if (wait_write_ptr) { | |
1728 | txq->need_update = 1; | |
1729 | iwl_pcie_txq_inc_wr_ptr(trans, txq); | |
1730 | } else { | |
1731 | iwl_stop_queue(trans, txq); | |
1732 | } | |
1733 | } | |
1734 | spin_unlock(&txq->lock); | |
1735 | return 0; | |
1736 | out_err: | |
1737 | spin_unlock(&txq->lock); | |
1738 | return -1; | |
a0eaad71 | 1739 | } |