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1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
128e63ef | 3 | * Copyright(c) 2003 - 2013 Intel Corporation. All rights reserved. |
1053d35f RR |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
1053d35f RR |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
fd4abac5 | 29 | #include <linux/etherdevice.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
253a634c | 31 | #include <linux/sched.h> |
253a634c | 32 | |
522376d2 EG |
33 | #include "iwl-debug.h" |
34 | #include "iwl-csr.h" | |
35 | #include "iwl-prph.h" | |
1053d35f | 36 | #include "iwl-io.h" |
ed277c93 | 37 | #include "iwl-op-mode.h" |
6468a01a | 38 | #include "internal.h" |
6238b008 | 39 | /* FIXME: need to abstract out TX command (once we know what it looks like) */ |
1023fdc4 | 40 | #include "dvm/commands.h" |
1053d35f | 41 | |
522376d2 EG |
42 | #define IWL_TX_CRC_SIZE 4 |
43 | #define IWL_TX_DELIMITER_SIZE 4 | |
44 | ||
f02831be EG |
45 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
46 | * DMA services | |
47 | * | |
48 | * Theory of operation | |
49 | * | |
50 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
51 | * of buffer descriptors, each of which points to one or more data buffers for | |
52 | * the device to read from or fill. Driver and device exchange status of each | |
53 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
54 | * entries in each circular buffer, to protect against confusing empty and full | |
55 | * queue states. | |
56 | * | |
57 | * The device reads or writes the data in the queues via the device's several | |
58 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
59 | * | |
60 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
61 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
62 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
63 | * Tx queue resumed. | |
64 | * | |
65 | ***************************************************/ | |
66 | static int iwl_queue_space(const struct iwl_queue *q) | |
67 | { | |
68 | int s = q->read_ptr - q->write_ptr; | |
69 | ||
70 | if (q->read_ptr > q->write_ptr) | |
71 | s -= q->n_bd; | |
72 | ||
73 | if (s <= 0) | |
74 | s += q->n_window; | |
75 | /* keep some reserve to not confuse empty and full situations */ | |
76 | s -= 2; | |
77 | if (s < 0) | |
78 | s = 0; | |
79 | return s; | |
80 | } | |
81 | ||
82 | /* | |
83 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes | |
84 | */ | |
85 | static int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id) | |
86 | { | |
87 | q->n_bd = count; | |
88 | q->n_window = slots_num; | |
89 | q->id = id; | |
90 | ||
91 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap | |
92 | * and iwl_queue_dec_wrap are broken. */ | |
93 | if (WARN_ON(!is_power_of_2(count))) | |
94 | return -EINVAL; | |
95 | ||
96 | /* slots_num must be power-of-two size, otherwise | |
97 | * get_cmd_index is broken. */ | |
98 | if (WARN_ON(!is_power_of_2(slots_num))) | |
99 | return -EINVAL; | |
100 | ||
101 | q->low_mark = q->n_window / 4; | |
102 | if (q->low_mark < 4) | |
103 | q->low_mark = 4; | |
104 | ||
105 | q->high_mark = q->n_window / 8; | |
106 | if (q->high_mark < 2) | |
107 | q->high_mark = 2; | |
108 | ||
109 | q->write_ptr = 0; | |
110 | q->read_ptr = 0; | |
111 | ||
112 | return 0; | |
113 | } | |
114 | ||
f02831be EG |
115 | static int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans, |
116 | struct iwl_dma_ptr *ptr, size_t size) | |
117 | { | |
118 | if (WARN_ON(ptr->addr)) | |
119 | return -EINVAL; | |
120 | ||
121 | ptr->addr = dma_alloc_coherent(trans->dev, size, | |
122 | &ptr->dma, GFP_KERNEL); | |
123 | if (!ptr->addr) | |
124 | return -ENOMEM; | |
125 | ptr->size = size; | |
126 | return 0; | |
127 | } | |
128 | ||
129 | static void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, | |
130 | struct iwl_dma_ptr *ptr) | |
131 | { | |
132 | if (unlikely(!ptr->addr)) | |
133 | return; | |
134 | ||
135 | dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma); | |
136 | memset(ptr, 0, sizeof(*ptr)); | |
137 | } | |
138 | ||
139 | static void iwl_pcie_txq_stuck_timer(unsigned long data) | |
140 | { | |
141 | struct iwl_txq *txq = (void *)data; | |
142 | struct iwl_queue *q = &txq->q; | |
143 | struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; | |
144 | struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie); | |
145 | u32 scd_sram_addr = trans_pcie->scd_base_addr + | |
146 | SCD_TX_STTS_QUEUE_OFFSET(txq->q.id); | |
147 | u8 buf[16]; | |
148 | int i; | |
149 | ||
150 | spin_lock(&txq->lock); | |
151 | /* check if triggered erroneously */ | |
152 | if (txq->q.read_ptr == txq->q.write_ptr) { | |
153 | spin_unlock(&txq->lock); | |
154 | return; | |
155 | } | |
156 | spin_unlock(&txq->lock); | |
157 | ||
158 | IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id, | |
159 | jiffies_to_msecs(trans_pcie->wd_timeout)); | |
160 | IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", | |
161 | txq->q.read_ptr, txq->q.write_ptr); | |
162 | ||
4fd442db | 163 | iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf)); |
f02831be EG |
164 | |
165 | iwl_print_hex_error(trans, buf, sizeof(buf)); | |
166 | ||
167 | for (i = 0; i < FH_TCSR_CHNL_NUM; i++) | |
168 | IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i, | |
169 | iwl_read_direct32(trans, FH_TX_TRB_REG(i))); | |
170 | ||
171 | for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { | |
172 | u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i)); | |
173 | u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; | |
174 | bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); | |
175 | u32 tbl_dw = | |
4fd442db EG |
176 | iwl_trans_read_mem32(trans, |
177 | trans_pcie->scd_base_addr + | |
178 | SCD_TRANS_TBL_OFFSET_QUEUE(i)); | |
f02831be EG |
179 | |
180 | if (i & 0x1) | |
181 | tbl_dw = (tbl_dw & 0xFFFF0000) >> 16; | |
182 | else | |
183 | tbl_dw = tbl_dw & 0x0000FFFF; | |
184 | ||
185 | IWL_ERR(trans, | |
186 | "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n", | |
187 | i, active ? "" : "in", fifo, tbl_dw, | |
188 | iwl_read_prph(trans, | |
189 | SCD_QUEUE_RDPTR(i)) & (txq->q.n_bd - 1), | |
190 | iwl_read_prph(trans, SCD_QUEUE_WRPTR(i))); | |
191 | } | |
192 | ||
193 | for (i = q->read_ptr; i != q->write_ptr; | |
194 | i = iwl_queue_inc_wrap(i, q->n_bd)) { | |
195 | struct iwl_tx_cmd *tx_cmd = | |
196 | (struct iwl_tx_cmd *)txq->entries[i].cmd->payload; | |
197 | IWL_ERR(trans, "scratch %d = 0x%08x\n", i, | |
198 | get_unaligned_le32(&tx_cmd->scratch)); | |
199 | } | |
200 | ||
201 | iwl_op_mode_nic_error(trans->op_mode); | |
202 | } | |
203 | ||
990aa6d7 EG |
204 | /* |
205 | * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array | |
48d42c42 | 206 | */ |
f02831be EG |
207 | static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans, |
208 | struct iwl_txq *txq, u16 byte_cnt) | |
48d42c42 | 209 | { |
105183b1 | 210 | struct iwlagn_scd_bc_tbl *scd_bc_tbl; |
20d3b647 | 211 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
48d42c42 EG |
212 | int write_ptr = txq->q.write_ptr; |
213 | int txq_id = txq->q.id; | |
214 | u8 sec_ctl = 0; | |
215 | u8 sta_id = 0; | |
216 | u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; | |
217 | __le16 bc_ent; | |
132f98c2 | 218 | struct iwl_tx_cmd *tx_cmd = |
bf8440e6 | 219 | (void *) txq->entries[txq->q.write_ptr].cmd->payload; |
48d42c42 | 220 | |
105183b1 EG |
221 | scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; |
222 | ||
48d42c42 EG |
223 | WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX); |
224 | ||
132f98c2 EG |
225 | sta_id = tx_cmd->sta_id; |
226 | sec_ctl = tx_cmd->sec_ctl; | |
48d42c42 EG |
227 | |
228 | switch (sec_ctl & TX_CMD_SEC_MSK) { | |
229 | case TX_CMD_SEC_CCM: | |
230 | len += CCMP_MIC_LEN; | |
231 | break; | |
232 | case TX_CMD_SEC_TKIP: | |
233 | len += TKIP_ICV_LEN; | |
234 | break; | |
235 | case TX_CMD_SEC_WEP: | |
236 | len += WEP_IV_LEN + WEP_ICV_LEN; | |
237 | break; | |
238 | } | |
239 | ||
046db346 EG |
240 | if (trans_pcie->bc_table_dword) |
241 | len = DIV_ROUND_UP(len, 4); | |
242 | ||
243 | bc_ent = cpu_to_le16(len | (sta_id << 12)); | |
48d42c42 EG |
244 | |
245 | scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; | |
246 | ||
247 | if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
248 | scd_bc_tbl[txq_id]. | |
249 | tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; | |
250 | } | |
251 | ||
f02831be EG |
252 | static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans, |
253 | struct iwl_txq *txq) | |
254 | { | |
255 | struct iwl_trans_pcie *trans_pcie = | |
256 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
257 | struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; | |
258 | int txq_id = txq->q.id; | |
259 | int read_ptr = txq->q.read_ptr; | |
260 | u8 sta_id = 0; | |
261 | __le16 bc_ent; | |
262 | struct iwl_tx_cmd *tx_cmd = | |
263 | (void *)txq->entries[txq->q.read_ptr].cmd->payload; | |
264 | ||
265 | WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); | |
266 | ||
267 | if (txq_id != trans_pcie->cmd_queue) | |
268 | sta_id = tx_cmd->sta_id; | |
269 | ||
270 | bc_ent = cpu_to_le16(1 | (sta_id << 12)); | |
271 | scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; | |
272 | ||
273 | if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
274 | scd_bc_tbl[txq_id]. | |
275 | tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; | |
276 | } | |
277 | ||
990aa6d7 EG |
278 | /* |
279 | * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware | |
fd4abac5 | 280 | */ |
990aa6d7 | 281 | void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_txq *txq) |
fd4abac5 TW |
282 | { |
283 | u32 reg = 0; | |
fd4abac5 TW |
284 | int txq_id = txq->q.id; |
285 | ||
286 | if (txq->need_update == 0) | |
7bfedc59 | 287 | return; |
fd4abac5 | 288 | |
035f7ff2 | 289 | if (trans->cfg->base_params->shadow_reg_enable) { |
f81c1f48 | 290 | /* shadow register enabled */ |
1042db2a | 291 | iwl_write32(trans, HBUS_TARG_WRPTR, |
f81c1f48 WYG |
292 | txq->q.write_ptr | (txq_id << 8)); |
293 | } else { | |
47107e84 DF |
294 | struct iwl_trans_pcie *trans_pcie = |
295 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
f81c1f48 | 296 | /* if we're trying to save power */ |
01d651d4 | 297 | if (test_bit(STATUS_TPOWER_PMI, &trans_pcie->status)) { |
f81c1f48 WYG |
298 | /* wake up nic if it's powered down ... |
299 | * uCode will wake up, and interrupt us again, so next | |
300 | * time we'll skip this part. */ | |
1042db2a | 301 | reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); |
fd4abac5 | 302 | |
f81c1f48 | 303 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { |
fd656935 | 304 | IWL_DEBUG_INFO(trans, |
f81c1f48 WYG |
305 | "Tx queue %d requesting wakeup," |
306 | " GP1 = 0x%x\n", txq_id, reg); | |
1042db2a | 307 | iwl_set_bit(trans, CSR_GP_CNTRL, |
f81c1f48 WYG |
308 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
309 | return; | |
310 | } | |
fd4abac5 | 311 | |
1c3fea82 EG |
312 | IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, |
313 | txq->q.write_ptr); | |
314 | ||
1042db2a | 315 | iwl_write_direct32(trans, HBUS_TARG_WRPTR, |
fd4abac5 | 316 | txq->q.write_ptr | (txq_id << 8)); |
fd4abac5 | 317 | |
f81c1f48 WYG |
318 | /* |
319 | * else not in power-save mode, | |
320 | * uCode will never sleep when we're | |
321 | * trying to tx (during RFKILL, we're not trying to tx). | |
322 | */ | |
323 | } else | |
1042db2a | 324 | iwl_write32(trans, HBUS_TARG_WRPTR, |
f81c1f48 WYG |
325 | txq->q.write_ptr | (txq_id << 8)); |
326 | } | |
fd4abac5 | 327 | txq->need_update = 0; |
fd4abac5 | 328 | } |
fd4abac5 | 329 | |
f02831be | 330 | static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
214d14d4 JB |
331 | { |
332 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
333 | ||
334 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
335 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
336 | addr |= | |
337 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
338 | ||
339 | return addr; | |
340 | } | |
341 | ||
f02831be | 342 | static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) |
214d14d4 JB |
343 | { |
344 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
345 | ||
346 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
347 | } | |
348 | ||
f02831be EG |
349 | static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, |
350 | dma_addr_t addr, u16 len) | |
214d14d4 JB |
351 | { |
352 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
353 | u16 hi_n_len = len << 4; | |
354 | ||
355 | put_unaligned_le32(addr, &tb->lo); | |
356 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
357 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
358 | ||
359 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
360 | ||
361 | tfd->num_tbs = idx + 1; | |
362 | } | |
363 | ||
f02831be | 364 | static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_tfd *tfd) |
214d14d4 JB |
365 | { |
366 | return tfd->num_tbs & 0x1f; | |
367 | } | |
368 | ||
f02831be EG |
369 | static void iwl_pcie_tfd_unmap(struct iwl_trans *trans, |
370 | struct iwl_cmd_meta *meta, struct iwl_tfd *tfd, | |
371 | enum dma_data_direction dma_dir) | |
214d14d4 | 372 | { |
214d14d4 JB |
373 | int i; |
374 | int num_tbs; | |
375 | ||
214d14d4 | 376 | /* Sanity check on number of chunks */ |
f02831be | 377 | num_tbs = iwl_pcie_tfd_get_num_tbs(tfd); |
214d14d4 JB |
378 | |
379 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
6d8f6eeb | 380 | IWL_ERR(trans, "Too many chunks: %i\n", num_tbs); |
214d14d4 JB |
381 | /* @todo issue fatal error, it is quite serious situation */ |
382 | return; | |
383 | } | |
384 | ||
385 | /* Unmap tx_cmd */ | |
386 | if (num_tbs) | |
1042db2a | 387 | dma_unmap_single(trans->dev, |
4ce7cc2b JB |
388 | dma_unmap_addr(meta, mapping), |
389 | dma_unmap_len(meta, len), | |
795414db | 390 | DMA_BIDIRECTIONAL); |
214d14d4 JB |
391 | |
392 | /* Unmap chunks, if any. */ | |
393 | for (i = 1; i < num_tbs; i++) | |
f02831be EG |
394 | dma_unmap_single(trans->dev, iwl_pcie_tfd_tb_get_addr(tfd, i), |
395 | iwl_pcie_tfd_tb_get_len(tfd, i), dma_dir); | |
ebed633c EG |
396 | |
397 | tfd->num_tbs = 0; | |
4ce7cc2b JB |
398 | } |
399 | ||
990aa6d7 EG |
400 | /* |
401 | * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
6d8f6eeb | 402 | * @trans - transport private data |
4ce7cc2b | 403 | * @txq - tx queue |
ebed633c | 404 | * @dma_dir - the direction of the DMA mapping |
4ce7cc2b JB |
405 | * |
406 | * Does NOT advance any TFD circular buffer read/write indexes | |
407 | * Does NOT free the TFD itself (which is within circular buffer) | |
408 | */ | |
f02831be EG |
409 | static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq, |
410 | enum dma_data_direction dma_dir) | |
4ce7cc2b JB |
411 | { |
412 | struct iwl_tfd *tfd_tmp = txq->tfds; | |
4ce7cc2b | 413 | |
ebed633c EG |
414 | /* rd_ptr is bounded by n_bd and idx is bounded by n_window */ |
415 | int rd_ptr = txq->q.read_ptr; | |
416 | int idx = get_cmd_index(&txq->q, rd_ptr); | |
417 | ||
015c15e1 JB |
418 | lockdep_assert_held(&txq->lock); |
419 | ||
ebed633c | 420 | /* We have only q->n_window txq->entries, but we use q->n_bd tfds */ |
f02831be EG |
421 | iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr], |
422 | dma_dir); | |
214d14d4 JB |
423 | |
424 | /* free SKB */ | |
bf8440e6 | 425 | if (txq->entries) { |
214d14d4 JB |
426 | struct sk_buff *skb; |
427 | ||
ebed633c | 428 | skb = txq->entries[idx].skb; |
214d14d4 | 429 | |
909e9b23 EG |
430 | /* Can be called from irqs-disabled context |
431 | * If skb is not NULL, it means that the whole queue is being | |
432 | * freed and that the queue is not empty - free the skb | |
433 | */ | |
214d14d4 | 434 | if (skb) { |
ed277c93 | 435 | iwl_op_mode_free_skb(trans->op_mode, skb); |
ebed633c | 436 | txq->entries[idx].skb = NULL; |
214d14d4 JB |
437 | } |
438 | } | |
439 | } | |
440 | ||
f02831be EG |
441 | static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq, |
442 | dma_addr_t addr, u16 len, u8 reset) | |
214d14d4 JB |
443 | { |
444 | struct iwl_queue *q; | |
445 | struct iwl_tfd *tfd, *tfd_tmp; | |
446 | u32 num_tbs; | |
447 | ||
448 | q = &txq->q; | |
4ce7cc2b | 449 | tfd_tmp = txq->tfds; |
214d14d4 JB |
450 | tfd = &tfd_tmp[q->write_ptr]; |
451 | ||
f02831be EG |
452 | if (reset) |
453 | memset(tfd, 0, sizeof(*tfd)); | |
454 | ||
455 | num_tbs = iwl_pcie_tfd_get_num_tbs(tfd); | |
456 | ||
457 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
458 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
459 | IWL_ERR(trans, "Error can not send more than %d chunks\n", | |
460 | IWL_NUM_OF_TBS); | |
461 | return -EINVAL; | |
462 | } | |
463 | ||
464 | if (WARN_ON(addr & ~DMA_BIT_MASK(36))) | |
465 | return -EINVAL; | |
466 | ||
467 | if (unlikely(addr & ~IWL_TX_DMA_MASK)) | |
468 | IWL_ERR(trans, "Unaligned address = %llx\n", | |
469 | (unsigned long long)addr); | |
470 | ||
471 | iwl_pcie_tfd_set_tb(tfd, num_tbs, addr, len); | |
472 | ||
473 | return 0; | |
474 | } | |
475 | ||
476 | static int iwl_pcie_txq_alloc(struct iwl_trans *trans, | |
477 | struct iwl_txq *txq, int slots_num, | |
478 | u32 txq_id) | |
479 | { | |
480 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
481 | size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX; | |
482 | int i; | |
483 | ||
484 | if (WARN_ON(txq->entries || txq->tfds)) | |
485 | return -EINVAL; | |
486 | ||
487 | setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer, | |
488 | (unsigned long)txq); | |
489 | txq->trans_pcie = trans_pcie; | |
490 | ||
491 | txq->q.n_window = slots_num; | |
492 | ||
493 | txq->entries = kcalloc(slots_num, | |
494 | sizeof(struct iwl_pcie_txq_entry), | |
495 | GFP_KERNEL); | |
496 | ||
497 | if (!txq->entries) | |
498 | goto error; | |
499 | ||
500 | if (txq_id == trans_pcie->cmd_queue) | |
501 | for (i = 0; i < slots_num; i++) { | |
502 | txq->entries[i].cmd = | |
503 | kmalloc(sizeof(struct iwl_device_cmd), | |
504 | GFP_KERNEL); | |
505 | if (!txq->entries[i].cmd) | |
506 | goto error; | |
507 | } | |
508 | ||
509 | /* Circular buffer of transmit frame descriptors (TFDs), | |
510 | * shared with device */ | |
511 | txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz, | |
512 | &txq->q.dma_addr, GFP_KERNEL); | |
513 | if (!txq->tfds) { | |
514 | IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz); | |
515 | goto error; | |
516 | } | |
517 | txq->q.id = txq_id; | |
518 | ||
519 | return 0; | |
520 | error: | |
521 | if (txq->entries && txq_id == trans_pcie->cmd_queue) | |
522 | for (i = 0; i < slots_num; i++) | |
523 | kfree(txq->entries[i].cmd); | |
524 | kfree(txq->entries); | |
525 | txq->entries = NULL; | |
526 | ||
527 | return -ENOMEM; | |
528 | ||
529 | } | |
530 | ||
531 | static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq, | |
532 | int slots_num, u32 txq_id) | |
533 | { | |
534 | int ret; | |
535 | ||
536 | txq->need_update = 0; | |
537 | ||
538 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise | |
539 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ | |
540 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); | |
541 | ||
542 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
543 | ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num, | |
544 | txq_id); | |
545 | if (ret) | |
546 | return ret; | |
547 | ||
548 | spin_lock_init(&txq->lock); | |
549 | ||
550 | /* | |
551 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
552 | * given Tx queue, and enable the DMA channel used for that queue. | |
553 | * Circular buffer (TFD queue in DRAM) physical base address */ | |
554 | iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id), | |
555 | txq->q.dma_addr >> 8); | |
556 | ||
557 | return 0; | |
558 | } | |
559 | ||
560 | /* | |
561 | * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's | |
562 | */ | |
563 | static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id) | |
564 | { | |
565 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
566 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
567 | struct iwl_queue *q = &txq->q; | |
568 | enum dma_data_direction dma_dir; | |
569 | ||
570 | if (!q->n_bd) | |
571 | return; | |
572 | ||
573 | /* In the command queue, all the TBs are mapped as BIDI | |
574 | * so unmap them as such. | |
575 | */ | |
576 | if (txq_id == trans_pcie->cmd_queue) | |
577 | dma_dir = DMA_BIDIRECTIONAL; | |
578 | else | |
579 | dma_dir = DMA_TO_DEVICE; | |
580 | ||
581 | spin_lock_bh(&txq->lock); | |
582 | while (q->write_ptr != q->read_ptr) { | |
583 | iwl_pcie_txq_free_tfd(trans, txq, dma_dir); | |
584 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd); | |
585 | } | |
586 | spin_unlock_bh(&txq->lock); | |
587 | } | |
588 | ||
589 | /* | |
590 | * iwl_pcie_txq_free - Deallocate DMA queue. | |
591 | * @txq: Transmit queue to deallocate. | |
592 | * | |
593 | * Empty queue by removing and destroying all BD's. | |
594 | * Free all buffers. | |
595 | * 0-fill, but do not free "txq" descriptor structure. | |
596 | */ | |
597 | static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id) | |
598 | { | |
599 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
600 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
601 | struct device *dev = trans->dev; | |
602 | int i; | |
603 | ||
604 | if (WARN_ON(!txq)) | |
605 | return; | |
606 | ||
607 | iwl_pcie_txq_unmap(trans, txq_id); | |
608 | ||
609 | /* De-alloc array of command/tx buffers */ | |
610 | if (txq_id == trans_pcie->cmd_queue) | |
611 | for (i = 0; i < txq->q.n_window; i++) { | |
612 | kfree(txq->entries[i].cmd); | |
613 | kfree(txq->entries[i].copy_cmd); | |
614 | kfree(txq->entries[i].free_buf); | |
615 | } | |
616 | ||
617 | /* De-alloc circular buffer of TFDs */ | |
618 | if (txq->q.n_bd) { | |
619 | dma_free_coherent(dev, sizeof(struct iwl_tfd) * | |
620 | txq->q.n_bd, txq->tfds, txq->q.dma_addr); | |
d21fa2da | 621 | txq->q.dma_addr = 0; |
f02831be EG |
622 | } |
623 | ||
624 | kfree(txq->entries); | |
625 | txq->entries = NULL; | |
626 | ||
627 | del_timer_sync(&txq->stuck_timer); | |
628 | ||
629 | /* 0-fill queue descriptor structure */ | |
630 | memset(txq, 0, sizeof(*txq)); | |
631 | } | |
632 | ||
633 | /* | |
634 | * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask | |
635 | */ | |
636 | static void iwl_pcie_txq_set_sched(struct iwl_trans *trans, u32 mask) | |
637 | { | |
638 | struct iwl_trans_pcie __maybe_unused *trans_pcie = | |
639 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
640 | ||
641 | iwl_write_prph(trans, SCD_TXFACT, mask); | |
642 | } | |
643 | ||
644 | void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr) | |
645 | { | |
646 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
22dc3c95 | 647 | int nq = trans->cfg->base_params->num_of_queues; |
f02831be EG |
648 | int chan; |
649 | u32 reg_val; | |
22dc3c95 JB |
650 | int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) - |
651 | SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32); | |
f02831be EG |
652 | |
653 | /* make sure all queue are not stopped/used */ | |
654 | memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); | |
655 | memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); | |
656 | ||
657 | trans_pcie->scd_base_addr = | |
658 | iwl_read_prph(trans, SCD_SRAM_BASE_ADDR); | |
659 | ||
660 | WARN_ON(scd_base_addr != 0 && | |
661 | scd_base_addr != trans_pcie->scd_base_addr); | |
662 | ||
22dc3c95 JB |
663 | /* reset context data, TX status and translation data */ |
664 | iwl_trans_write_mem(trans, trans_pcie->scd_base_addr + | |
665 | SCD_CONTEXT_MEM_LOWER_BOUND, | |
666 | NULL, clear_dwords); | |
f02831be EG |
667 | |
668 | iwl_write_prph(trans, SCD_DRAM_BASE_ADDR, | |
669 | trans_pcie->scd_bc_tbls.dma >> 10); | |
670 | ||
671 | /* The chain extension of the SCD doesn't work well. This feature is | |
672 | * enabled by default by the HW, so we need to disable it manually. | |
673 | */ | |
674 | iwl_write_prph(trans, SCD_CHAINEXT_EN, 0); | |
675 | ||
676 | iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue, | |
677 | trans_pcie->cmd_fifo); | |
678 | ||
679 | /* Activate all Tx DMA/FIFO channels */ | |
680 | iwl_pcie_txq_set_sched(trans, IWL_MASK(0, 7)); | |
681 | ||
682 | /* Enable DMA channel */ | |
683 | for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++) | |
684 | iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan), | |
685 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
686 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); | |
687 | ||
688 | /* Update FH chicken bits */ | |
689 | reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG); | |
690 | iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG, | |
691 | reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); | |
692 | ||
693 | /* Enable L1-Active */ | |
694 | iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
695 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
696 | } | |
697 | ||
ddaf5a5b JB |
698 | void iwl_trans_pcie_tx_reset(struct iwl_trans *trans) |
699 | { | |
700 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
701 | int txq_id; | |
702 | ||
703 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
704 | txq_id++) { | |
705 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
706 | ||
707 | iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id), | |
708 | txq->q.dma_addr >> 8); | |
709 | iwl_pcie_txq_unmap(trans, txq_id); | |
710 | txq->q.read_ptr = 0; | |
711 | txq->q.write_ptr = 0; | |
712 | } | |
713 | ||
714 | /* Tell NIC where to find the "keep warm" buffer */ | |
715 | iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, | |
716 | trans_pcie->kw.dma >> 4); | |
717 | ||
718 | iwl_pcie_tx_start(trans, trans_pcie->scd_base_addr); | |
719 | } | |
720 | ||
f02831be EG |
721 | /* |
722 | * iwl_pcie_tx_stop - Stop all Tx DMA channels | |
723 | */ | |
724 | int iwl_pcie_tx_stop(struct iwl_trans *trans) | |
725 | { | |
726 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
727 | int ch, txq_id, ret; | |
728 | unsigned long flags; | |
729 | ||
730 | /* Turn off all Tx DMA fifos */ | |
731 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); | |
732 | ||
733 | iwl_pcie_txq_set_sched(trans, 0); | |
734 | ||
735 | /* Stop each Tx DMA channel, and wait for it to be idle */ | |
736 | for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { | |
737 | iwl_write_direct32(trans, | |
738 | FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); | |
739 | ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG, | |
740 | FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000); | |
741 | if (ret < 0) | |
742 | IWL_ERR(trans, | |
743 | "Failing on timeout while stopping DMA channel %d [0x%08x]\n", | |
744 | ch, | |
745 | iwl_read_direct32(trans, | |
746 | FH_TSSR_TX_STATUS_REG)); | |
747 | } | |
748 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); | |
749 | ||
750 | if (!trans_pcie->txq) { | |
751 | IWL_WARN(trans, | |
752 | "Stopping tx queues that aren't allocated...\n"); | |
753 | return 0; | |
754 | } | |
755 | ||
756 | /* Unmap DMA from host system and free skb's */ | |
757 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
758 | txq_id++) | |
759 | iwl_pcie_txq_unmap(trans, txq_id); | |
760 | ||
761 | return 0; | |
762 | } | |
763 | ||
764 | /* | |
765 | * iwl_trans_tx_free - Free TXQ Context | |
766 | * | |
767 | * Destroy all TX DMA queues and structures | |
768 | */ | |
769 | void iwl_pcie_tx_free(struct iwl_trans *trans) | |
770 | { | |
771 | int txq_id; | |
772 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
773 | ||
774 | /* Tx queues */ | |
775 | if (trans_pcie->txq) { | |
776 | for (txq_id = 0; | |
777 | txq_id < trans->cfg->base_params->num_of_queues; txq_id++) | |
778 | iwl_pcie_txq_free(trans, txq_id); | |
779 | } | |
780 | ||
781 | kfree(trans_pcie->txq); | |
782 | trans_pcie->txq = NULL; | |
783 | ||
784 | iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw); | |
785 | ||
786 | iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls); | |
787 | } | |
788 | ||
789 | /* | |
790 | * iwl_pcie_tx_alloc - allocate TX context | |
791 | * Allocate all Tx DMA structures and initialize them | |
792 | */ | |
793 | static int iwl_pcie_tx_alloc(struct iwl_trans *trans) | |
794 | { | |
795 | int ret; | |
796 | int txq_id, slots_num; | |
797 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
798 | ||
799 | u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues * | |
800 | sizeof(struct iwlagn_scd_bc_tbl); | |
801 | ||
802 | /*It is not allowed to alloc twice, so warn when this happens. | |
803 | * We cannot rely on the previous allocation, so free and fail */ | |
804 | if (WARN_ON(trans_pcie->txq)) { | |
805 | ret = -EINVAL; | |
806 | goto error; | |
807 | } | |
808 | ||
809 | ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls, | |
810 | scd_bc_tbls_size); | |
811 | if (ret) { | |
812 | IWL_ERR(trans, "Scheduler BC Table allocation failed\n"); | |
813 | goto error; | |
814 | } | |
815 | ||
816 | /* Alloc keep-warm buffer */ | |
817 | ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE); | |
818 | if (ret) { | |
819 | IWL_ERR(trans, "Keep Warm allocation failed\n"); | |
820 | goto error; | |
821 | } | |
822 | ||
823 | trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues, | |
824 | sizeof(struct iwl_txq), GFP_KERNEL); | |
825 | if (!trans_pcie->txq) { | |
826 | IWL_ERR(trans, "Not enough memory for txq\n"); | |
827 | ret = ENOMEM; | |
828 | goto error; | |
829 | } | |
830 | ||
831 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
832 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
833 | txq_id++) { | |
834 | slots_num = (txq_id == trans_pcie->cmd_queue) ? | |
835 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
836 | ret = iwl_pcie_txq_alloc(trans, &trans_pcie->txq[txq_id], | |
837 | slots_num, txq_id); | |
838 | if (ret) { | |
839 | IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id); | |
840 | goto error; | |
841 | } | |
842 | } | |
843 | ||
844 | return 0; | |
845 | ||
846 | error: | |
847 | iwl_pcie_tx_free(trans); | |
848 | ||
849 | return ret; | |
850 | } | |
851 | int iwl_pcie_tx_init(struct iwl_trans *trans) | |
852 | { | |
853 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
854 | int ret; | |
855 | int txq_id, slots_num; | |
856 | unsigned long flags; | |
857 | bool alloc = false; | |
858 | ||
859 | if (!trans_pcie->txq) { | |
860 | ret = iwl_pcie_tx_alloc(trans); | |
861 | if (ret) | |
862 | goto error; | |
863 | alloc = true; | |
864 | } | |
865 | ||
866 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); | |
867 | ||
868 | /* Turn off all Tx DMA fifos */ | |
869 | iwl_write_prph(trans, SCD_TXFACT, 0); | |
870 | ||
871 | /* Tell NIC where to find the "keep warm" buffer */ | |
872 | iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, | |
873 | trans_pcie->kw.dma >> 4); | |
874 | ||
875 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); | |
876 | ||
877 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
878 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
879 | txq_id++) { | |
880 | slots_num = (txq_id == trans_pcie->cmd_queue) ? | |
881 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
882 | ret = iwl_pcie_txq_init(trans, &trans_pcie->txq[txq_id], | |
883 | slots_num, txq_id); | |
884 | if (ret) { | |
885 | IWL_ERR(trans, "Tx %d queue init failed\n", txq_id); | |
886 | goto error; | |
887 | } | |
888 | } | |
889 | ||
890 | return 0; | |
891 | error: | |
892 | /*Upon error, free only if we allocated something */ | |
893 | if (alloc) | |
894 | iwl_pcie_tx_free(trans); | |
895 | return ret; | |
896 | } | |
897 | ||
898 | static inline void iwl_pcie_txq_progress(struct iwl_trans_pcie *trans_pcie, | |
899 | struct iwl_txq *txq) | |
900 | { | |
901 | if (!trans_pcie->wd_timeout) | |
902 | return; | |
903 | ||
904 | /* | |
905 | * if empty delete timer, otherwise move timer forward | |
906 | * since we're making progress on this queue | |
907 | */ | |
908 | if (txq->q.read_ptr == txq->q.write_ptr) | |
909 | del_timer(&txq->stuck_timer); | |
910 | else | |
911 | mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout); | |
912 | } | |
913 | ||
914 | /* Frees buffers until index _not_ inclusive */ | |
f6d497cd EG |
915 | void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, |
916 | struct sk_buff_head *skbs) | |
f02831be EG |
917 | { |
918 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
919 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
f6d497cd EG |
920 | /* n_bd is usually 256 => n_bd - 1 = 0xff */ |
921 | int tfd_num = ssn & (txq->q.n_bd - 1); | |
f02831be EG |
922 | struct iwl_queue *q = &txq->q; |
923 | int last_to_free; | |
f02831be EG |
924 | |
925 | /* This function is not meant to release cmd queue*/ | |
926 | if (WARN_ON(txq_id == trans_pcie->cmd_queue)) | |
f6d497cd | 927 | return; |
214d14d4 | 928 | |
2bfb5092 | 929 | spin_lock_bh(&txq->lock); |
f6d497cd EG |
930 | |
931 | if (txq->q.read_ptr == tfd_num) | |
932 | goto out; | |
933 | ||
934 | IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n", | |
935 | txq_id, txq->q.read_ptr, tfd_num, ssn); | |
214d14d4 | 936 | |
f02831be EG |
937 | /*Since we free until index _not_ inclusive, the one before index is |
938 | * the last we will free. This one must be used */ | |
f6d497cd | 939 | last_to_free = iwl_queue_dec_wrap(tfd_num, q->n_bd); |
f02831be | 940 | |
6ca6ebc1 | 941 | if (!iwl_queue_used(q, last_to_free)) { |
f02831be EG |
942 | IWL_ERR(trans, |
943 | "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n", | |
944 | __func__, txq_id, last_to_free, q->n_bd, | |
945 | q->write_ptr, q->read_ptr); | |
f6d497cd | 946 | goto out; |
214d14d4 JB |
947 | } |
948 | ||
f02831be | 949 | if (WARN_ON(!skb_queue_empty(skbs))) |
f6d497cd | 950 | goto out; |
214d14d4 | 951 | |
f02831be | 952 | for (; |
f6d497cd | 953 | q->read_ptr != tfd_num; |
f02831be | 954 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { |
214d14d4 | 955 | |
f02831be EG |
956 | if (WARN_ON_ONCE(txq->entries[txq->q.read_ptr].skb == NULL)) |
957 | continue; | |
214d14d4 | 958 | |
f02831be | 959 | __skb_queue_tail(skbs, txq->entries[txq->q.read_ptr].skb); |
214d14d4 | 960 | |
f02831be | 961 | txq->entries[txq->q.read_ptr].skb = NULL; |
fd4abac5 | 962 | |
f02831be | 963 | iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq); |
fd4abac5 | 964 | |
f02831be | 965 | iwl_pcie_txq_free_tfd(trans, txq, DMA_TO_DEVICE); |
f02831be | 966 | } |
fd4abac5 | 967 | |
f02831be EG |
968 | iwl_pcie_txq_progress(trans_pcie, txq); |
969 | ||
f6d497cd EG |
970 | if (iwl_queue_space(&txq->q) > txq->q.low_mark) |
971 | iwl_wake_queue(trans, txq); | |
972 | out: | |
2bfb5092 | 973 | spin_unlock_bh(&txq->lock); |
1053d35f RR |
974 | } |
975 | ||
f02831be EG |
976 | /* |
977 | * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd | |
978 | * | |
979 | * When FW advances 'R' index, all entries between old and new 'R' index | |
980 | * need to be reclaimed. As result, some free space forms. If there is | |
981 | * enough free space (> low mark), wake the stack that feeds us. | |
982 | */ | |
983 | static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx) | |
48d42c42 | 984 | { |
f02831be EG |
985 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
986 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
987 | struct iwl_queue *q = &txq->q; | |
988 | int nfreed = 0; | |
48d42c42 | 989 | |
f02831be | 990 | lockdep_assert_held(&txq->lock); |
48d42c42 | 991 | |
6ca6ebc1 | 992 | if ((idx >= q->n_bd) || (!iwl_queue_used(q, idx))) { |
f02831be EG |
993 | IWL_ERR(trans, |
994 | "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n", | |
995 | __func__, txq_id, idx, q->n_bd, | |
996 | q->write_ptr, q->read_ptr); | |
997 | return; | |
998 | } | |
48d42c42 | 999 | |
f02831be EG |
1000 | for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; |
1001 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
48d42c42 | 1002 | |
f02831be EG |
1003 | if (nfreed++ > 0) { |
1004 | IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", | |
1005 | idx, q->write_ptr, q->read_ptr); | |
1006 | iwl_op_mode_nic_error(trans->op_mode); | |
1007 | } | |
1008 | } | |
1009 | ||
1010 | iwl_pcie_txq_progress(trans_pcie, txq); | |
48d42c42 EG |
1011 | } |
1012 | ||
f02831be | 1013 | static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid, |
1ce8658c | 1014 | u16 txq_id) |
48d42c42 | 1015 | { |
20d3b647 | 1016 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
48d42c42 EG |
1017 | u32 tbl_dw_addr; |
1018 | u32 tbl_dw; | |
1019 | u16 scd_q2ratid; | |
1020 | ||
1021 | scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; | |
1022 | ||
105183b1 | 1023 | tbl_dw_addr = trans_pcie->scd_base_addr + |
48d42c42 EG |
1024 | SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); |
1025 | ||
4fd442db | 1026 | tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr); |
48d42c42 EG |
1027 | |
1028 | if (txq_id & 0x1) | |
1029 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); | |
1030 | else | |
1031 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); | |
1032 | ||
4fd442db | 1033 | iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw); |
48d42c42 EG |
1034 | |
1035 | return 0; | |
1036 | } | |
1037 | ||
f02831be EG |
1038 | static inline void iwl_pcie_txq_set_inactive(struct iwl_trans *trans, |
1039 | u16 txq_id) | |
48d42c42 EG |
1040 | { |
1041 | /* Simply stop the queue, but don't change any configuration; | |
1042 | * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ | |
1042db2a | 1043 | iwl_write_prph(trans, |
48d42c42 EG |
1044 | SCD_QUEUE_STATUS_BITS(txq_id), |
1045 | (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)| | |
1046 | (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); | |
1047 | } | |
1048 | ||
f02831be EG |
1049 | void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, int fifo, |
1050 | int sta_id, int tid, int frame_limit, u16 ssn) | |
48d42c42 | 1051 | { |
9eae88fa | 1052 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
4beaf6c2 | 1053 | |
9eae88fa JB |
1054 | if (test_and_set_bit(txq_id, trans_pcie->queue_used)) |
1055 | WARN_ONCE(1, "queue %d already used - expect issues", txq_id); | |
48d42c42 | 1056 | |
48d42c42 | 1057 | /* Stop this Tx queue before configuring it */ |
f02831be | 1058 | iwl_pcie_txq_set_inactive(trans, txq_id); |
48d42c42 | 1059 | |
4beaf6c2 EG |
1060 | /* Set this queue as a chain-building queue unless it is CMD queue */ |
1061 | if (txq_id != trans_pcie->cmd_queue) | |
1062 | iwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, BIT(txq_id)); | |
1063 | ||
1064 | /* If this queue is mapped to a certain station: it is an AGG queue */ | |
1065 | if (sta_id != IWL_INVALID_STATION) { | |
1066 | u16 ra_tid = BUILD_RAxTID(sta_id, tid); | |
48d42c42 | 1067 | |
4beaf6c2 | 1068 | /* Map receiver-address / traffic-ID to this queue */ |
f02831be | 1069 | iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id); |
48d42c42 | 1070 | |
4beaf6c2 EG |
1071 | /* enable aggregations for the queue */ |
1072 | iwl_set_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id)); | |
1ce8658c EG |
1073 | } else { |
1074 | /* | |
1075 | * disable aggregations for the queue, this will also make the | |
1076 | * ra_tid mapping configuration irrelevant since it is now a | |
1077 | * non-AGG queue. | |
1078 | */ | |
1079 | iwl_clear_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id)); | |
4beaf6c2 | 1080 | } |
48d42c42 EG |
1081 | |
1082 | /* Place first TFD at index corresponding to start sequence number. | |
1083 | * Assumes that ssn_idx is valid (!= 0xFFF) */ | |
822e8b2a EG |
1084 | trans_pcie->txq[txq_id].q.read_ptr = (ssn & 0xff); |
1085 | trans_pcie->txq[txq_id].q.write_ptr = (ssn & 0xff); | |
1ce8658c EG |
1086 | |
1087 | iwl_write_direct32(trans, HBUS_TARG_WRPTR, | |
1088 | (ssn & 0xff) | (txq_id << 8)); | |
1089 | iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn); | |
48d42c42 EG |
1090 | |
1091 | /* Set up Tx window size and frame limit for this queue */ | |
4fd442db | 1092 | iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr + |
4beaf6c2 | 1093 | SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0); |
4fd442db | 1094 | iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr + |
9eae88fa JB |
1095 | SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), |
1096 | ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
1097 | SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
1098 | ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
1099 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
48d42c42 | 1100 | |
48d42c42 | 1101 | /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ |
1ce8658c EG |
1102 | iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id), |
1103 | (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) | | |
1104 | (fifo << SCD_QUEUE_STTS_REG_POS_TXF) | | |
1105 | (1 << SCD_QUEUE_STTS_REG_POS_WSL) | | |
1106 | SCD_QUEUE_STTS_REG_MSK); | |
1107 | IWL_DEBUG_TX_QUEUES(trans, "Activate queue %d on FIFO %d WrPtr: %d\n", | |
1108 | txq_id, fifo, ssn & 0xff); | |
4beaf6c2 EG |
1109 | } |
1110 | ||
f02831be | 1111 | void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id) |
288712a6 | 1112 | { |
8ad71bef | 1113 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
986ea6c9 EG |
1114 | u32 stts_addr = trans_pcie->scd_base_addr + |
1115 | SCD_TX_STTS_QUEUE_OFFSET(txq_id); | |
1116 | static const u32 zero_val[4] = {}; | |
288712a6 | 1117 | |
9eae88fa JB |
1118 | if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) { |
1119 | WARN_ONCE(1, "queue %d not used", txq_id); | |
1120 | return; | |
48d42c42 EG |
1121 | } |
1122 | ||
f02831be | 1123 | iwl_pcie_txq_set_inactive(trans, txq_id); |
ac928f8d | 1124 | |
4fd442db EG |
1125 | iwl_trans_write_mem(trans, stts_addr, (void *)zero_val, |
1126 | ARRAY_SIZE(zero_val)); | |
986ea6c9 | 1127 | |
990aa6d7 | 1128 | iwl_pcie_txq_unmap(trans, txq_id); |
6c3fd3f0 | 1129 | |
1ce8658c | 1130 | IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id); |
48d42c42 EG |
1131 | } |
1132 | ||
fd4abac5 TW |
1133 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ |
1134 | ||
990aa6d7 | 1135 | /* |
f02831be | 1136 | * iwl_pcie_enqueue_hcmd - enqueue a uCode command |
fd4abac5 TW |
1137 | * @priv: device private data point |
1138 | * @cmd: a point to the ucode command structure | |
1139 | * | |
1140 | * The function returns < 0 values to indicate the operation is | |
1141 | * failed. On success, it turns the index (> 0) of command in the | |
1142 | * command queue. | |
1143 | */ | |
f02831be EG |
1144 | static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans, |
1145 | struct iwl_host_cmd *cmd) | |
fd4abac5 | 1146 | { |
8ad71bef | 1147 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1148 | struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
fd4abac5 | 1149 | struct iwl_queue *q = &txq->q; |
c2acea8e JB |
1150 | struct iwl_device_cmd *out_cmd; |
1151 | struct iwl_cmd_meta *out_meta; | |
f4feb8ac | 1152 | void *dup_buf = NULL; |
fd4abac5 | 1153 | dma_addr_t phys_addr; |
f4feb8ac | 1154 | int idx; |
8a964f44 | 1155 | u16 copy_size, cmd_size, dma_size; |
4ce7cc2b JB |
1156 | bool had_nocopy = false; |
1157 | int i; | |
96791422 | 1158 | u32 cmd_pos; |
8a964f44 JB |
1159 | const u8 *cmddata[IWL_MAX_CMD_TFDS]; |
1160 | u16 cmdlen[IWL_MAX_CMD_TFDS]; | |
fd4abac5 | 1161 | |
4ce7cc2b JB |
1162 | copy_size = sizeof(out_cmd->hdr); |
1163 | cmd_size = sizeof(out_cmd->hdr); | |
1164 | ||
1165 | /* need one for the header if the first is NOCOPY */ | |
1166 | BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1); | |
1167 | ||
1168 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
8a964f44 JB |
1169 | cmddata[i] = cmd->data[i]; |
1170 | cmdlen[i] = cmd->len[i]; | |
1171 | ||
4ce7cc2b JB |
1172 | if (!cmd->len[i]) |
1173 | continue; | |
8a964f44 JB |
1174 | |
1175 | /* need at least IWL_HCMD_MIN_COPY_SIZE copied */ | |
1176 | if (copy_size < IWL_HCMD_MIN_COPY_SIZE) { | |
1177 | int copy = IWL_HCMD_MIN_COPY_SIZE - copy_size; | |
1178 | ||
1179 | if (copy > cmdlen[i]) | |
1180 | copy = cmdlen[i]; | |
1181 | cmdlen[i] -= copy; | |
1182 | cmddata[i] += copy; | |
1183 | copy_size += copy; | |
1184 | } | |
1185 | ||
4ce7cc2b JB |
1186 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { |
1187 | had_nocopy = true; | |
f4feb8ac JB |
1188 | if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) { |
1189 | idx = -EINVAL; | |
1190 | goto free_dup_buf; | |
1191 | } | |
1192 | } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) { | |
1193 | /* | |
1194 | * This is also a chunk that isn't copied | |
1195 | * to the static buffer so set had_nocopy. | |
1196 | */ | |
1197 | had_nocopy = true; | |
1198 | ||
1199 | /* only allowed once */ | |
1200 | if (WARN_ON(dup_buf)) { | |
1201 | idx = -EINVAL; | |
1202 | goto free_dup_buf; | |
1203 | } | |
1204 | ||
8a964f44 | 1205 | dup_buf = kmemdup(cmddata[i], cmdlen[i], |
f4feb8ac JB |
1206 | GFP_ATOMIC); |
1207 | if (!dup_buf) | |
1208 | return -ENOMEM; | |
4ce7cc2b JB |
1209 | } else { |
1210 | /* NOCOPY must not be followed by normal! */ | |
f4feb8ac JB |
1211 | if (WARN_ON(had_nocopy)) { |
1212 | idx = -EINVAL; | |
1213 | goto free_dup_buf; | |
1214 | } | |
8a964f44 | 1215 | copy_size += cmdlen[i]; |
4ce7cc2b JB |
1216 | } |
1217 | cmd_size += cmd->len[i]; | |
1218 | } | |
fd4abac5 | 1219 | |
3e41ace5 JB |
1220 | /* |
1221 | * If any of the command structures end up being larger than | |
4ce7cc2b JB |
1222 | * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically |
1223 | * allocated into separate TFDs, then we will need to | |
1224 | * increase the size of the buffers. | |
3e41ace5 | 1225 | */ |
2a79e45e JB |
1226 | if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE, |
1227 | "Command %s (%#x) is too large (%d bytes)\n", | |
990aa6d7 | 1228 | get_cmd_string(trans_pcie, cmd->id), cmd->id, copy_size)) { |
f4feb8ac JB |
1229 | idx = -EINVAL; |
1230 | goto free_dup_buf; | |
1231 | } | |
fd4abac5 | 1232 | |
015c15e1 | 1233 | spin_lock_bh(&txq->lock); |
3598e177 | 1234 | |
c2acea8e | 1235 | if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { |
015c15e1 | 1236 | spin_unlock_bh(&txq->lock); |
3598e177 | 1237 | |
6d8f6eeb | 1238 | IWL_ERR(trans, "No space in command queue\n"); |
0e781842 | 1239 | iwl_op_mode_cmd_queue_full(trans->op_mode); |
f4feb8ac JB |
1240 | idx = -ENOSPC; |
1241 | goto free_dup_buf; | |
fd4abac5 TW |
1242 | } |
1243 | ||
4ce7cc2b | 1244 | idx = get_cmd_index(q, q->write_ptr); |
bf8440e6 JB |
1245 | out_cmd = txq->entries[idx].cmd; |
1246 | out_meta = &txq->entries[idx].meta; | |
c2acea8e | 1247 | |
8ce73f3a | 1248 | memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ |
c2acea8e JB |
1249 | if (cmd->flags & CMD_WANT_SKB) |
1250 | out_meta->source = cmd; | |
fd4abac5 | 1251 | |
4ce7cc2b | 1252 | /* set up the header */ |
fd4abac5 | 1253 | |
4ce7cc2b | 1254 | out_cmd->hdr.cmd = cmd->id; |
fd4abac5 | 1255 | out_cmd->hdr.flags = 0; |
cefeaa5f | 1256 | out_cmd->hdr.sequence = |
c6f600fc | 1257 | cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | |
cefeaa5f | 1258 | INDEX_TO_SEQ(q->write_ptr)); |
4ce7cc2b JB |
1259 | |
1260 | /* and copy the data that needs to be copied */ | |
96791422 | 1261 | cmd_pos = offsetof(struct iwl_device_cmd, payload); |
8a964f44 | 1262 | copy_size = sizeof(out_cmd->hdr); |
4ce7cc2b | 1263 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { |
8a964f44 JB |
1264 | int copy = 0; |
1265 | ||
1266 | if (!cmd->len) | |
4ce7cc2b | 1267 | continue; |
8a964f44 JB |
1268 | |
1269 | /* need at least IWL_HCMD_MIN_COPY_SIZE copied */ | |
1270 | if (copy_size < IWL_HCMD_MIN_COPY_SIZE) { | |
1271 | copy = IWL_HCMD_MIN_COPY_SIZE - copy_size; | |
1272 | ||
1273 | if (copy > cmd->len[i]) | |
1274 | copy = cmd->len[i]; | |
1275 | } | |
1276 | ||
1277 | /* copy everything if not nocopy/dup */ | |
1278 | if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | | |
1279 | IWL_HCMD_DFL_DUP))) | |
1280 | copy = cmd->len[i]; | |
1281 | ||
1282 | if (copy) { | |
1283 | memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); | |
1284 | cmd_pos += copy; | |
1285 | copy_size += copy; | |
1286 | } | |
96791422 EG |
1287 | } |
1288 | ||
1289 | WARN_ON_ONCE(txq->entries[idx].copy_cmd); | |
1290 | ||
1291 | /* | |
1292 | * since out_cmd will be the source address of the FH, it will write | |
1293 | * the retry count there. So when the user needs to receivce the HCMD | |
1294 | * that corresponds to the response in the response handler, it needs | |
1295 | * to set CMD_WANT_HCMD. | |
1296 | */ | |
1297 | if (cmd->flags & CMD_WANT_HCMD) { | |
1298 | txq->entries[idx].copy_cmd = | |
1299 | kmemdup(out_cmd, cmd_pos, GFP_ATOMIC); | |
1300 | if (unlikely(!txq->entries[idx].copy_cmd)) { | |
1301 | idx = -ENOMEM; | |
1302 | goto out; | |
1303 | } | |
ded2ae7c | 1304 | } |
4ce7cc2b | 1305 | |
d9fb6465 | 1306 | IWL_DEBUG_HC(trans, |
20d3b647 | 1307 | "Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n", |
990aa6d7 | 1308 | get_cmd_string(trans_pcie, out_cmd->hdr.cmd), |
20d3b647 JB |
1309 | out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence), |
1310 | cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue); | |
4ce7cc2b | 1311 | |
8a964f44 JB |
1312 | /* |
1313 | * If the entire command is smaller than IWL_HCMD_MIN_COPY_SIZE, we must | |
1314 | * still map at least that many bytes for the hardware to write back to. | |
1315 | * We have enough space, so that's not a problem. | |
1316 | */ | |
1317 | dma_size = max_t(u16, copy_size, IWL_HCMD_MIN_COPY_SIZE); | |
1318 | ||
1319 | phys_addr = dma_map_single(trans->dev, &out_cmd->hdr, dma_size, | |
20d3b647 | 1320 | DMA_BIDIRECTIONAL); |
1042db2a | 1321 | if (unlikely(dma_mapping_error(trans->dev, phys_addr))) { |
2c46f72e JB |
1322 | idx = -ENOMEM; |
1323 | goto out; | |
1324 | } | |
1325 | ||
2e724443 | 1326 | dma_unmap_addr_set(out_meta, mapping, phys_addr); |
8a964f44 | 1327 | dma_unmap_len_set(out_meta, len, dma_size); |
4ce7cc2b | 1328 | |
f02831be | 1329 | iwl_pcie_txq_build_tfd(trans, txq, phys_addr, copy_size, 1); |
4ce7cc2b | 1330 | |
8a964f44 | 1331 | /* map the remaining (adjusted) nocopy/dup fragments */ |
4ce7cc2b | 1332 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { |
8a964f44 | 1333 | const void *data = cmddata[i]; |
f4feb8ac | 1334 | |
8a964f44 | 1335 | if (!cmdlen[i]) |
4ce7cc2b | 1336 | continue; |
f4feb8ac JB |
1337 | if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | |
1338 | IWL_HCMD_DFL_DUP))) | |
4ce7cc2b | 1339 | continue; |
f4feb8ac JB |
1340 | if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) |
1341 | data = dup_buf; | |
1342 | phys_addr = dma_map_single(trans->dev, (void *)data, | |
8a964f44 | 1343 | cmdlen[i], DMA_BIDIRECTIONAL); |
1042db2a | 1344 | if (dma_mapping_error(trans->dev, phys_addr)) { |
f02831be EG |
1345 | iwl_pcie_tfd_unmap(trans, out_meta, |
1346 | &txq->tfds[q->write_ptr], | |
1347 | DMA_BIDIRECTIONAL); | |
4ce7cc2b JB |
1348 | idx = -ENOMEM; |
1349 | goto out; | |
1350 | } | |
1351 | ||
8a964f44 | 1352 | iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], 0); |
4ce7cc2b | 1353 | } |
df833b1d | 1354 | |
afaf6b57 | 1355 | out_meta->flags = cmd->flags; |
f4feb8ac JB |
1356 | if (WARN_ON_ONCE(txq->entries[idx].free_buf)) |
1357 | kfree(txq->entries[idx].free_buf); | |
1358 | txq->entries[idx].free_buf = dup_buf; | |
2c46f72e JB |
1359 | |
1360 | txq->need_update = 1; | |
1361 | ||
8a964f44 | 1362 | trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr); |
df833b1d | 1363 | |
7c5ba4a8 JB |
1364 | /* start timer if queue currently empty */ |
1365 | if (q->read_ptr == q->write_ptr && trans_pcie->wd_timeout) | |
1366 | mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout); | |
1367 | ||
fd4abac5 TW |
1368 | /* Increment and update queue's write index */ |
1369 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
990aa6d7 | 1370 | iwl_pcie_txq_inc_wr_ptr(trans, txq); |
fd4abac5 | 1371 | |
2c46f72e | 1372 | out: |
015c15e1 | 1373 | spin_unlock_bh(&txq->lock); |
f4feb8ac JB |
1374 | free_dup_buf: |
1375 | if (idx < 0) | |
1376 | kfree(dup_buf); | |
7bfedc59 | 1377 | return idx; |
fd4abac5 TW |
1378 | } |
1379 | ||
990aa6d7 EG |
1380 | /* |
1381 | * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them | |
17b88929 | 1382 | * @rxb: Rx buffer to reclaim |
247c61d6 EG |
1383 | * @handler_status: return value of the handler of the command |
1384 | * (put in setup_rx_handlers) | |
17b88929 TW |
1385 | * |
1386 | * If an Rx buffer has an async callback associated with it the callback | |
1387 | * will be executed. The attached skb (if present) will only be freed | |
1388 | * if the callback returns 1 | |
1389 | */ | |
990aa6d7 EG |
1390 | void iwl_pcie_hcmd_complete(struct iwl_trans *trans, |
1391 | struct iwl_rx_cmd_buffer *rxb, int handler_status) | |
17b88929 | 1392 | { |
2f301227 | 1393 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
17b88929 TW |
1394 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
1395 | int txq_id = SEQ_TO_QUEUE(sequence); | |
1396 | int index = SEQ_TO_INDEX(sequence); | |
17b88929 | 1397 | int cmd_index; |
c2acea8e JB |
1398 | struct iwl_device_cmd *cmd; |
1399 | struct iwl_cmd_meta *meta; | |
8ad71bef | 1400 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1401 | struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
17b88929 TW |
1402 | |
1403 | /* If a Tx command is being handled and it isn't in the actual | |
1404 | * command queue then there a command routing bug has been introduced | |
1405 | * in the queue management code. */ | |
c6f600fc | 1406 | if (WARN(txq_id != trans_pcie->cmd_queue, |
13bb9483 | 1407 | "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", |
20d3b647 JB |
1408 | txq_id, trans_pcie->cmd_queue, sequence, |
1409 | trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr, | |
1410 | trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) { | |
3e10caeb | 1411 | iwl_print_hex_error(trans, pkt, 32); |
55d6a3cd | 1412 | return; |
01ef9323 | 1413 | } |
17b88929 | 1414 | |
2bfb5092 | 1415 | spin_lock_bh(&txq->lock); |
015c15e1 | 1416 | |
4ce7cc2b | 1417 | cmd_index = get_cmd_index(&txq->q, index); |
bf8440e6 JB |
1418 | cmd = txq->entries[cmd_index].cmd; |
1419 | meta = &txq->entries[cmd_index].meta; | |
17b88929 | 1420 | |
f02831be | 1421 | iwl_pcie_tfd_unmap(trans, meta, &txq->tfds[index], DMA_BIDIRECTIONAL); |
c33de625 | 1422 | |
17b88929 | 1423 | /* Input error checking is done when commands are added to queue. */ |
c2acea8e | 1424 | if (meta->flags & CMD_WANT_SKB) { |
48a2d66f | 1425 | struct page *p = rxb_steal_page(rxb); |
65b94a4a | 1426 | |
65b94a4a JB |
1427 | meta->source->resp_pkt = pkt; |
1428 | meta->source->_rx_page_addr = (unsigned long)page_address(p); | |
b2cf410c | 1429 | meta->source->_rx_page_order = trans_pcie->rx_page_order; |
247c61d6 | 1430 | meta->source->handler_status = handler_status; |
247c61d6 | 1431 | } |
2624e96c | 1432 | |
f02831be | 1433 | iwl_pcie_cmdq_reclaim(trans, txq_id, index); |
17b88929 | 1434 | |
c2acea8e | 1435 | if (!(meta->flags & CMD_ASYNC)) { |
74fda971 | 1436 | if (!test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) { |
05c89b91 WYG |
1437 | IWL_WARN(trans, |
1438 | "HCMD_ACTIVE already clear for command %s\n", | |
990aa6d7 | 1439 | get_cmd_string(trans_pcie, cmd->hdr.cmd)); |
05c89b91 | 1440 | } |
74fda971 | 1441 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); |
6d8f6eeb | 1442 | IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", |
990aa6d7 | 1443 | get_cmd_string(trans_pcie, cmd->hdr.cmd)); |
f946b529 | 1444 | wake_up(&trans_pcie->wait_command_queue); |
17b88929 | 1445 | } |
3598e177 | 1446 | |
dd487449 | 1447 | meta->flags = 0; |
3598e177 | 1448 | |
2bfb5092 | 1449 | spin_unlock_bh(&txq->lock); |
17b88929 | 1450 | } |
253a634c | 1451 | |
253a634c EG |
1452 | #define HOST_COMPLETE_TIMEOUT (2 * HZ) |
1453 | ||
f02831be EG |
1454 | static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans, |
1455 | struct iwl_host_cmd *cmd) | |
253a634c | 1456 | { |
d9fb6465 | 1457 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
253a634c EG |
1458 | int ret; |
1459 | ||
1460 | /* An asynchronous command can not expect an SKB to be set. */ | |
1461 | if (WARN_ON(cmd->flags & CMD_WANT_SKB)) | |
1462 | return -EINVAL; | |
1463 | ||
f02831be | 1464 | ret = iwl_pcie_enqueue_hcmd(trans, cmd); |
253a634c | 1465 | if (ret < 0) { |
721c32f7 | 1466 | IWL_ERR(trans, |
b36b110c | 1467 | "Error sending %s: enqueue_hcmd failed: %d\n", |
990aa6d7 | 1468 | get_cmd_string(trans_pcie, cmd->id), ret); |
253a634c EG |
1469 | return ret; |
1470 | } | |
1471 | return 0; | |
1472 | } | |
1473 | ||
f02831be EG |
1474 | static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans, |
1475 | struct iwl_host_cmd *cmd) | |
253a634c | 1476 | { |
8ad71bef | 1477 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
253a634c EG |
1478 | int cmd_idx; |
1479 | int ret; | |
1480 | ||
6d8f6eeb | 1481 | IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", |
990aa6d7 | 1482 | get_cmd_string(trans_pcie, cmd->id)); |
253a634c | 1483 | |
2cc39c94 | 1484 | if (WARN_ON(test_and_set_bit(STATUS_HCMD_ACTIVE, |
74fda971 | 1485 | &trans_pcie->status))) { |
2cc39c94 | 1486 | IWL_ERR(trans, "Command %s: a command is already active!\n", |
990aa6d7 | 1487 | get_cmd_string(trans_pcie, cmd->id)); |
2cc39c94 JB |
1488 | return -EIO; |
1489 | } | |
1490 | ||
6d8f6eeb | 1491 | IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", |
990aa6d7 | 1492 | get_cmd_string(trans_pcie, cmd->id)); |
253a634c | 1493 | |
f02831be | 1494 | cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd); |
253a634c EG |
1495 | if (cmd_idx < 0) { |
1496 | ret = cmd_idx; | |
74fda971 | 1497 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); |
721c32f7 | 1498 | IWL_ERR(trans, |
b36b110c | 1499 | "Error sending %s: enqueue_hcmd failed: %d\n", |
990aa6d7 | 1500 | get_cmd_string(trans_pcie, cmd->id), ret); |
253a634c EG |
1501 | return ret; |
1502 | } | |
1503 | ||
f946b529 | 1504 | ret = wait_event_timeout(trans_pcie->wait_command_queue, |
20d3b647 JB |
1505 | !test_bit(STATUS_HCMD_ACTIVE, |
1506 | &trans_pcie->status), | |
1507 | HOST_COMPLETE_TIMEOUT); | |
253a634c | 1508 | if (!ret) { |
74fda971 | 1509 | if (test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) { |
990aa6d7 | 1510 | struct iwl_txq *txq = |
c6f600fc | 1511 | &trans_pcie->txq[trans_pcie->cmd_queue]; |
d10630af WYG |
1512 | struct iwl_queue *q = &txq->q; |
1513 | ||
721c32f7 | 1514 | IWL_ERR(trans, |
253a634c | 1515 | "Error sending %s: time out after %dms.\n", |
990aa6d7 | 1516 | get_cmd_string(trans_pcie, cmd->id), |
253a634c EG |
1517 | jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); |
1518 | ||
721c32f7 | 1519 | IWL_ERR(trans, |
d10630af WYG |
1520 | "Current CMD queue read_ptr %d write_ptr %d\n", |
1521 | q->read_ptr, q->write_ptr); | |
1522 | ||
74fda971 | 1523 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); |
d9fb6465 JB |
1524 | IWL_DEBUG_INFO(trans, |
1525 | "Clearing HCMD_ACTIVE for command %s\n", | |
990aa6d7 | 1526 | get_cmd_string(trans_pcie, cmd->id)); |
253a634c EG |
1527 | ret = -ETIMEDOUT; |
1528 | goto cancel; | |
1529 | } | |
1530 | } | |
1531 | ||
d18aa87f JB |
1532 | if (test_bit(STATUS_FW_ERROR, &trans_pcie->status)) { |
1533 | IWL_ERR(trans, "FW error in SYNC CMD %s\n", | |
990aa6d7 | 1534 | get_cmd_string(trans_pcie, cmd->id)); |
d18aa87f JB |
1535 | ret = -EIO; |
1536 | goto cancel; | |
1537 | } | |
1538 | ||
f946b529 EG |
1539 | if (test_bit(STATUS_RFKILL, &trans_pcie->status)) { |
1540 | IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n"); | |
1541 | ret = -ERFKILL; | |
1542 | goto cancel; | |
1543 | } | |
1544 | ||
65b94a4a | 1545 | if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) { |
6d8f6eeb | 1546 | IWL_ERR(trans, "Error: Response NULL in '%s'\n", |
990aa6d7 | 1547 | get_cmd_string(trans_pcie, cmd->id)); |
253a634c EG |
1548 | ret = -EIO; |
1549 | goto cancel; | |
1550 | } | |
1551 | ||
1552 | return 0; | |
1553 | ||
1554 | cancel: | |
1555 | if (cmd->flags & CMD_WANT_SKB) { | |
1556 | /* | |
1557 | * Cancel the CMD_WANT_SKB flag for the cmd in the | |
1558 | * TX cmd queue. Otherwise in case the cmd comes | |
1559 | * in later, it will possibly set an invalid | |
1560 | * address (cmd->meta.source). | |
1561 | */ | |
bf8440e6 JB |
1562 | trans_pcie->txq[trans_pcie->cmd_queue]. |
1563 | entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB; | |
253a634c | 1564 | } |
9cac4943 | 1565 | |
65b94a4a JB |
1566 | if (cmd->resp_pkt) { |
1567 | iwl_free_resp(cmd); | |
1568 | cmd->resp_pkt = NULL; | |
253a634c EG |
1569 | } |
1570 | ||
1571 | return ret; | |
1572 | } | |
1573 | ||
f02831be | 1574 | int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c | 1575 | { |
f946b529 EG |
1576 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1577 | ||
d18aa87f JB |
1578 | if (test_bit(STATUS_FW_ERROR, &trans_pcie->status)) |
1579 | return -EIO; | |
1580 | ||
f946b529 EG |
1581 | if (test_bit(STATUS_RFKILL, &trans_pcie->status)) |
1582 | return -ERFKILL; | |
1583 | ||
253a634c | 1584 | if (cmd->flags & CMD_ASYNC) |
f02831be | 1585 | return iwl_pcie_send_hcmd_async(trans, cmd); |
253a634c | 1586 | |
f946b529 | 1587 | /* We still can fail on RFKILL that can be asserted while we wait */ |
f02831be | 1588 | return iwl_pcie_send_hcmd_sync(trans, cmd); |
253a634c EG |
1589 | } |
1590 | ||
f02831be EG |
1591 | int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, |
1592 | struct iwl_device_cmd *dev_cmd, int txq_id) | |
a0eaad71 | 1593 | { |
8ad71bef | 1594 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
f02831be EG |
1595 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
1596 | struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload; | |
1597 | struct iwl_cmd_meta *out_meta; | |
1598 | struct iwl_txq *txq; | |
1599 | struct iwl_queue *q; | |
1600 | dma_addr_t phys_addr = 0; | |
1601 | dma_addr_t txcmd_phys; | |
1602 | dma_addr_t scratch_phys; | |
1603 | u16 len, firstlen, secondlen; | |
1604 | u8 wait_write_ptr = 0; | |
1605 | __le16 fc = hdr->frame_control; | |
1606 | u8 hdr_len = ieee80211_hdrlen(fc); | |
1607 | u16 __maybe_unused wifi_seq; | |
1608 | ||
1609 | txq = &trans_pcie->txq[txq_id]; | |
1610 | q = &txq->q; | |
a0eaad71 | 1611 | |
f02831be EG |
1612 | if (unlikely(!test_bit(txq_id, trans_pcie->queue_used))) { |
1613 | WARN_ON_ONCE(1); | |
1614 | return -EINVAL; | |
1615 | } | |
39644e9a | 1616 | |
f02831be | 1617 | spin_lock(&txq->lock); |
015c15e1 | 1618 | |
f02831be EG |
1619 | /* In AGG mode, the index in the ring must correspond to the WiFi |
1620 | * sequence number. This is a HW requirements to help the SCD to parse | |
1621 | * the BA. | |
1622 | * Check here that the packets are in the right place on the ring. | |
1623 | */ | |
1624 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1625 | wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); | |
1626 | WARN_ONCE((iwl_read_prph(trans, SCD_AGGR_SEL) & BIT(txq_id)) && | |
1627 | ((wifi_seq & 0xff) != q->write_ptr), | |
1628 | "Q: %d WiFi Seq %d tfdNum %d", | |
1629 | txq_id, wifi_seq, q->write_ptr); | |
1630 | #endif | |
1631 | ||
1632 | /* Set up driver data for this TFD */ | |
1633 | txq->entries[q->write_ptr].skb = skb; | |
1634 | txq->entries[q->write_ptr].cmd = dev_cmd; | |
1635 | ||
1636 | dev_cmd->hdr.cmd = REPLY_TX; | |
1637 | dev_cmd->hdr.sequence = | |
1638 | cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
1639 | INDEX_TO_SEQ(q->write_ptr))); | |
1640 | ||
1641 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ | |
1642 | out_meta = &txq->entries[q->write_ptr].meta; | |
a0eaad71 | 1643 | |
f02831be EG |
1644 | /* |
1645 | * Use the first empty entry in this queue's command buffer array | |
1646 | * to contain the Tx command and MAC header concatenated together | |
1647 | * (payload data will be in another buffer). | |
1648 | * Size of this varies, due to varying MAC header length. | |
1649 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
1650 | * of the MAC header (device reads on dword boundaries). | |
1651 | * We'll tell device about this padding later. | |
1652 | */ | |
1653 | len = sizeof(struct iwl_tx_cmd) + | |
1654 | sizeof(struct iwl_cmd_header) + hdr_len; | |
1655 | firstlen = (len + 3) & ~3; | |
1656 | ||
1657 | /* Tell NIC about any 2-byte padding after MAC header */ | |
1658 | if (firstlen != len) | |
1659 | tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; | |
1660 | ||
1661 | /* Physical address of this Tx command's header (not MAC header!), | |
1662 | * within command buffer array. */ | |
1663 | txcmd_phys = dma_map_single(trans->dev, | |
1664 | &dev_cmd->hdr, firstlen, | |
1665 | DMA_BIDIRECTIONAL); | |
1666 | if (unlikely(dma_mapping_error(trans->dev, txcmd_phys))) | |
1667 | goto out_err; | |
1668 | dma_unmap_addr_set(out_meta, mapping, txcmd_phys); | |
1669 | dma_unmap_len_set(out_meta, len, firstlen); | |
1670 | ||
1671 | if (!ieee80211_has_morefrags(fc)) { | |
1672 | txq->need_update = 1; | |
1673 | } else { | |
1674 | wait_write_ptr = 1; | |
1675 | txq->need_update = 0; | |
a0eaad71 EG |
1676 | } |
1677 | ||
f02831be EG |
1678 | /* Set up TFD's 2nd entry to point directly to remainder of skb, |
1679 | * if any (802.11 null frames have no payload). */ | |
1680 | secondlen = skb->len - hdr_len; | |
1681 | if (secondlen > 0) { | |
1682 | phys_addr = dma_map_single(trans->dev, skb->data + hdr_len, | |
1683 | secondlen, DMA_TO_DEVICE); | |
1684 | if (unlikely(dma_mapping_error(trans->dev, phys_addr))) { | |
1685 | dma_unmap_single(trans->dev, | |
1686 | dma_unmap_addr(out_meta, mapping), | |
1687 | dma_unmap_len(out_meta, len), | |
1688 | DMA_BIDIRECTIONAL); | |
1689 | goto out_err; | |
1690 | } | |
1691 | } | |
a0eaad71 | 1692 | |
f02831be EG |
1693 | /* Attach buffers to TFD */ |
1694 | iwl_pcie_txq_build_tfd(trans, txq, txcmd_phys, firstlen, 1); | |
1695 | if (secondlen > 0) | |
1696 | iwl_pcie_txq_build_tfd(trans, txq, phys_addr, secondlen, 0); | |
a0eaad71 | 1697 | |
f02831be EG |
1698 | scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) + |
1699 | offsetof(struct iwl_tx_cmd, scratch); | |
a0eaad71 | 1700 | |
f02831be EG |
1701 | /* take back ownership of DMA buffer to enable update */ |
1702 | dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen, | |
1703 | DMA_BIDIRECTIONAL); | |
1704 | tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); | |
1705 | tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); | |
a0eaad71 | 1706 | |
f02831be EG |
1707 | /* Set up entry for this TFD in Tx byte-count array */ |
1708 | iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len)); | |
a0eaad71 | 1709 | |
f02831be EG |
1710 | dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen, |
1711 | DMA_BIDIRECTIONAL); | |
7c5ba4a8 | 1712 | |
f02831be EG |
1713 | trace_iwlwifi_dev_tx(trans->dev, skb, |
1714 | &txq->tfds[txq->q.write_ptr], | |
1715 | sizeof(struct iwl_tfd), | |
1716 | &dev_cmd->hdr, firstlen, | |
1717 | skb->data + hdr_len, secondlen); | |
1718 | trace_iwlwifi_dev_tx_data(trans->dev, skb, | |
1719 | skb->data + hdr_len, secondlen); | |
7c5ba4a8 | 1720 | |
f02831be EG |
1721 | /* start timer if queue currently empty */ |
1722 | if (txq->need_update && q->read_ptr == q->write_ptr && | |
1723 | trans_pcie->wd_timeout) | |
1724 | mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout); | |
1725 | ||
1726 | /* Tell device the write index *just past* this latest filled TFD */ | |
1727 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
1728 | iwl_pcie_txq_inc_wr_ptr(trans, txq); | |
1729 | ||
1730 | /* | |
1731 | * At this point the frame is "transmitted" successfully | |
1732 | * and we will get a TX status notification eventually, | |
1733 | * regardless of the value of ret. "ret" only indicates | |
1734 | * whether or not we should update the write pointer. | |
1735 | */ | |
1736 | if (iwl_queue_space(q) < q->high_mark) { | |
1737 | if (wait_write_ptr) { | |
1738 | txq->need_update = 1; | |
1739 | iwl_pcie_txq_inc_wr_ptr(trans, txq); | |
1740 | } else { | |
1741 | iwl_stop_queue(trans, txq); | |
1742 | } | |
1743 | } | |
1744 | spin_unlock(&txq->lock); | |
1745 | return 0; | |
1746 | out_err: | |
1747 | spin_unlock(&txq->lock); | |
1748 | return -1; | |
a0eaad71 | 1749 | } |